drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39
  40 #include "../pci.h"
  41 #include "pciehp.h"
  42
  43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
  44
  45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
  46 {
  47         struct pci_dev *dev = ctrl->pcie->port;
  48         return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
  49 }
  50
  51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
  52 {
  53         struct pci_dev *dev = ctrl->pcie->port;
  54         return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  55 }
  56
  57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
  58 {
  59         struct pci_dev *dev = ctrl->pcie->port;
  60         return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
  61 }
  62
  63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
  64 {
  65         struct pci_dev *dev = ctrl->pcie->port;
  66         return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
  67 }
  68
  69 /* Power Control Command */
  70 #define POWER_ON        0
  71 #define POWER_OFF       PCI_EXP_SLTCTL_PCC
  72
  73 static irqreturn_t pcie_isr(int irq, void *dev_id);
  74 static void start_int_poll_timer(struct controller *ctrl, int sec);
  75
  76 /* This is the interrupt polling timeout function. */
  77 static void int_poll_timeout(unsigned long data)
  78 {
  79         struct controller *ctrl = (struct controller *)data;
  80
  81         /* Poll for interrupt events.  regs == NULL => polling */
  82         pcie_isr(0, ctrl);
  83
  84         init_timer(&ctrl->poll_timer);
  85         if (!pciehp_poll_time)
  86                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  87
  88         start_int_poll_timer(ctrl, pciehp_poll_time);
  89 }
  90
  91 /* This function starts the interrupt polling timer. */
  92 static void start_int_poll_timer(struct controller *ctrl, int sec)
  93 {
  94         /* Clamp to sane value */
  95         if ((sec <= 0) || (sec > 60))
  96                 sec = 2;
  97
  98         ctrl->poll_timer.function = &int_poll_timeout;
  99         ctrl->poll_timer.data = (unsigned long)ctrl;
 100         ctrl->poll_timer.expires = jiffies + sec * HZ;
 101         add_timer(&ctrl->poll_timer);
 102 }
 103
 104 static inline int pciehp_request_irq(struct controller *ctrl)
 105 {
 106         int retval, irq = ctrl->pcie->irq;
 107
 108         /* Install interrupt polling timer. Start with 10 sec delay */
 109         if (pciehp_poll_mode) {
 110                 init_timer(&ctrl->poll_timer);
 111                 start_int_poll_timer(ctrl, 10);
 112                 return 0;
 113         }
 114
 115         /* Installs the interrupt handler */
 116         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
 117         if (retval)
 118                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
 119                          irq);
 120         return retval;
 121 }
 122
 123 static inline void pciehp_free_irq(struct controller *ctrl)
 124 {
 125         if (pciehp_poll_mode)
 126                 del_timer_sync(&ctrl->poll_timer);
 127         else
 128                 free_irq(ctrl->pcie->irq, ctrl);
 129 }
 130
 131 static int pcie_poll_cmd(struct controller *ctrl)
 132 {
 133         u16 slot_status;
 134         int err, timeout = 1000;
 135
 136         err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 137         if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 138                 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 139                 return 1;
 140         }
 141         while (timeout > 0) {
 142                 msleep(10);
 143                 timeout -= 10;
 144                 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 145                 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
 146                         pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
 147                         return 1;
 148                 }
 149         }
 150         return 0;       /* timeout */
 151 }
 152
 153 static void pcie_wait_cmd(struct controller *ctrl, int poll)
 154 {
 155         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 156         unsigned long timeout = msecs_to_jiffies(msecs);
 157         int rc;
 158
 159         if (poll)
 160                 rc = pcie_poll_cmd(ctrl);
 161         else
 162                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 163         if (!rc)
 164                 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
 165 }
 166
 167 /**
 168  * pcie_write_cmd - Issue controller command
 169  * @ctrl: controller to which the command is issued
 170  * @cmd:  command value written to slot control register
 171  * @mask: bitmask of slot control register to be modified
 172  */
 173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 174 {
 175         int retval = 0;
 176         u16 slot_status;
 177         u16 slot_ctrl;
 178
 179         mutex_lock(&ctrl->ctrl_lock);
 180
 181         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 182         if (retval) {
 183                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 184                          __func__);
 185                 goto out;
 186         }
 187
 188         if (slot_status & PCI_EXP_SLTSTA_CC) {
 189                 if (!ctrl->no_cmd_complete) {
 190                         /*
 191                          * After 1 sec and CMD_COMPLETED still not set, just
 192                          * proceed forward to issue the next command according
 193                          * to spec. Just print out the error message.
 194                          */
 195                         ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
 196                 } else if (!NO_CMD_CMPL(ctrl)) {
 197                         /*
 198                          * This controller semms to notify of command completed
 199                          * event even though it supports none of power
 200                          * controller, attention led, power led and EMI.
 201                          */
 202                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
 203                                  "wait for command completed event.\n");
 204                         ctrl->no_cmd_complete = 0;
 205                 } else {
 206                         ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
 207                                  "the controller is broken.\n");
 208                 }
 209         }
 210
 211         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 212         if (retval) {
 213                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 214                 goto out;
 215         }
 216
 217         slot_ctrl &= ~mask;
 218         slot_ctrl |= (cmd & mask);
 219         ctrl->cmd_busy = 1;
 220         smp_mb();
 221         retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
 222         if (retval)
 223                 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
 224
 225         /*
 226          * Wait for command completion.
 227          */
 228         if (!retval && !ctrl->no_cmd_complete) {
 229                 int poll = 0;
 230                 /*
 231                  * if hotplug interrupt is not enabled or command
 232                  * completed interrupt is not enabled, we need to poll
 233                  * command completed event.
 234                  */
 235                 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
 236                     !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
 237                         poll = 1;
 238                 pcie_wait_cmd(ctrl, poll);
 239         }
 240  out:
 241         mutex_unlock(&ctrl->ctrl_lock);
 242         return retval;
 243 }
 244
 245 static inline int check_link_active(struct controller *ctrl)
 246 {
 247         u16 link_status;
 248
 249         if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
 250                 return 0;
 251         return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
 252 }
 253
 254 static void pcie_wait_link_active(struct controller *ctrl)
 255 {
 256         int timeout = 1000;
 257
 258         if (check_link_active(ctrl))
 259                 return;
 260         while (timeout > 0) {
 261                 msleep(10);
 262                 timeout -= 10;
 263                 if (check_link_active(ctrl))
 264                         return;
 265         }
 266         ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
 267 }
 268
 269 int pciehp_check_link_status(struct controller *ctrl)
 270 {
 271         u16 lnk_status;
 272         int retval = 0;
 273
 274         /*
 275          * Data Link Layer Link Active Reporting must be capable for
 276          * hot-plug capable downstream port. But old controller might
 277          * not implement it. In this case, we wait for 1000 ms.
 278          */
 279         if (ctrl->link_active_reporting){
 280                 /* Wait for Data Link Layer Link Active bit to be set */
 281                 pcie_wait_link_active(ctrl);
 282                 /*
 283                  * We must wait for 100 ms after the Data Link Layer
 284                  * Link Active bit reads 1b before initiating a
 285                  * configuration access to the hot added device.
 286                  */
 287                 msleep(100);
 288         } else
 289                 msleep(1000);
 290
 291         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 292         if (retval) {
 293                 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
 294                 return retval;
 295         }
 296
 297         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 298         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 299             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 300                 ctrl_err(ctrl, "Link Training Error occurs \n");
 301                 retval = -1;
 302                 return retval;
 303         }
 304
 305         return retval;
 306 }
 307
 308 int pciehp_get_attention_status(struct slot *slot, u8 *status)
 309 {
 310         struct controller *ctrl = slot->ctrl;
 311         u16 slot_ctrl;
 312         u8 atten_led_state;
 313         int retval = 0;
 314
 315         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 316         if (retval) {
 317                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 318                 return retval;
 319         }
 320
 321         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 322                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 323
 324         atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
 325
 326         switch (atten_led_state) {
 327         case 0:
 328                 *status = 0xFF; /* Reserved */
 329                 break;
 330         case 1:
 331                 *status = 1;    /* On */
 332                 break;
 333         case 2:
 334                 *status = 2;    /* Blink */
 335                 break;
 336         case 3:
 337                 *status = 0;    /* Off */
 338                 break;
 339         default:
 340                 *status = 0xFF;
 341                 break;
 342         }
 343
 344         return 0;
 345 }
 346
 347 int pciehp_get_power_status(struct slot *slot, u8 *status)
 348 {
 349         struct controller *ctrl = slot->ctrl;
 350         u16 slot_ctrl;
 351         u8 pwr_state;
 352         int     retval = 0;
 353
 354         retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
 355         if (retval) {
 356                 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
 357                 return retval;
 358         }
 359         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 360                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 361
 362         pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
 363
 364         switch (pwr_state) {
 365         case 0:
 366                 *status = 1;
 367                 break;
 368         case 1:
 369                 *status = 0;
 370                 break;
 371         default:
 372                 *status = 0xFF;
 373                 break;
 374         }
 375
 376         return retval;
 377 }
 378
 379 int pciehp_get_latch_status(struct slot *slot, u8 *status)
 380 {
 381         struct controller *ctrl = slot->ctrl;
 382         u16 slot_status;
 383         int retval;
 384
 385         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 386         if (retval) {
 387                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 388                          __func__);
 389                 return retval;
 390         }
 391         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 392         return 0;
 393 }
 394
 395 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
 396 {
 397         struct controller *ctrl = slot->ctrl;
 398         u16 slot_status;
 399         int retval;
 400
 401         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 402         if (retval) {
 403                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 404                          __func__);
 405                 return retval;
 406         }
 407         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 408         return 0;
 409 }
 410
 411 int pciehp_query_power_fault(struct slot *slot)
 412 {
 413         struct controller *ctrl = slot->ctrl;
 414         u16 slot_status;
 415         int retval;
 416
 417         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 418         if (retval) {
 419                 ctrl_err(ctrl, "Cannot check for power fault\n");
 420                 return retval;
 421         }
 422         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 423 }
 424
 425 int pciehp_set_attention_status(struct slot *slot, u8 value)
 426 {
 427         struct controller *ctrl = slot->ctrl;
 428         u16 slot_cmd;
 429         u16 cmd_mask;
 430
 431         cmd_mask = PCI_EXP_SLTCTL_AIC;
 432         switch (value) {
 433         case 0 :        /* turn off */
 434                 slot_cmd = 0x00C0;
 435                 break;
 436         case 1:         /* turn on */
 437                 slot_cmd = 0x0040;
 438                 break;
 439         case 2:         /* turn blink */
 440                 slot_cmd = 0x0080;
 441                 break;
 442         default:
 443                 return -EINVAL;
 444         }
 445         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 446                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 447         return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 448 }
 449
 450 void pciehp_green_led_on(struct slot *slot)
 451 {
 452         struct controller *ctrl = slot->ctrl;
 453         u16 slot_cmd;
 454         u16 cmd_mask;
 455
 456         slot_cmd = 0x0100;
 457         cmd_mask = PCI_EXP_SLTCTL_PIC;
 458         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 459         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 460                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 461 }
 462
 463 void pciehp_green_led_off(struct slot *slot)
 464 {
 465         struct controller *ctrl = slot->ctrl;
 466         u16 slot_cmd;
 467         u16 cmd_mask;
 468
 469         slot_cmd = 0x0300;
 470         cmd_mask = PCI_EXP_SLTCTL_PIC;
 471         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 472         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 473                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 474 }
 475
 476 void pciehp_green_led_blink(struct slot *slot)
 477 {
 478         struct controller *ctrl = slot->ctrl;
 479         u16 slot_cmd;
 480         u16 cmd_mask;
 481
 482         slot_cmd = 0x0200;
 483         cmd_mask = PCI_EXP_SLTCTL_PIC;
 484         pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 485         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 486                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 487 }
 488
 489 int pciehp_power_on_slot(struct slot * slot)
 490 {
 491         struct controller *ctrl = slot->ctrl;
 492         u16 slot_cmd;
 493         u16 cmd_mask;
 494         u16 slot_status;
 495         u16 lnk_status;
 496         int retval = 0;
 497
 498         /* Clear sticky power-fault bit from previous power failures */
 499         retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
 500         if (retval) {
 501                 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
 502                          __func__);
 503                 return retval;
 504         }
 505         slot_status &= PCI_EXP_SLTSTA_PFD;
 506         if (slot_status) {
 507                 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
 508                 if (retval) {
 509                         ctrl_err(ctrl,
 510                                  "%s: Cannot write to SLOTSTATUS register\n",
 511                                  __func__);
 512                         return retval;
 513                 }
 514         }
 515         ctrl->power_fault_detected = 0;
 516
 517         slot_cmd = POWER_ON;
 518         cmd_mask = PCI_EXP_SLTCTL_PCC;
 519         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 520         if (retval) {
 521                 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
 522                 return retval;
 523         }
 524         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 525                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 526
 527         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 528         if (retval) {
 529                 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
 530                                 __func__);
 531                 return retval;
 532         }
 533         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 534
 535         return retval;
 536 }
 537
 538 int pciehp_power_off_slot(struct slot * slot)
 539 {
 540         struct controller *ctrl = slot->ctrl;
 541         u16 slot_cmd;
 542         u16 cmd_mask;
 543         int retval;
 544
 545         slot_cmd = POWER_OFF;
 546         cmd_mask = PCI_EXP_SLTCTL_PCC;
 547         retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
 548         if (retval) {
 549                 ctrl_err(ctrl, "Write command failed!\n");
 550                 return retval;
 551         }
 552         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 553                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 554         return 0;
 555 }
 556
 557 static irqreturn_t pcie_isr(int irq, void *dev_id)
 558 {
 559         struct controller *ctrl = (struct controller *)dev_id;
 560         struct slot *slot = ctrl->slot;
 561         u16 detected, intr_loc;
 562
 563         /*
 564          * In order to guarantee that all interrupt events are
 565          * serviced, we need to re-inspect Slot Status register after
 566          * clearing what is presumed to be the last pending interrupt.
 567          */
 568         intr_loc = 0;
 569         do {
 570                 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
 571                         ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
 572                                  __func__);
 573                         return IRQ_NONE;
 574                 }
 575
 576                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 577                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 578                              PCI_EXP_SLTSTA_CC);
 579                 detected &= ~intr_loc;
 580                 intr_loc |= detected;
 581                 if (!intr_loc)
 582                         return IRQ_NONE;
 583                 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
 584                         ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
 585                                  __func__);
 586                         return IRQ_NONE;
 587                 }
 588         } while (detected);
 589
 590         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 591
 592         /* Check Command Complete Interrupt Pending */
 593         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 594                 ctrl->cmd_busy = 0;
 595                 smp_mb();
 596                 wake_up(&ctrl->queue);
 597         }
 598
 599         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 600                 return IRQ_HANDLED;
 601
 602         /* Check MRL Sensor Changed */
 603         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 604                 pciehp_handle_switch_change(slot);
 605
 606         /* Check Attention Button Pressed */
 607         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 608                 pciehp_handle_attention_button(slot);
 609
 610         /* Check Presence Detect Changed */
 611         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 612                 pciehp_handle_presence_change(slot);
 613
 614         /* Check Power Fault Detected */
 615         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 616                 ctrl->power_fault_detected = 1;
 617                 pciehp_handle_power_fault(slot);
 618         }
 619         return IRQ_HANDLED;
 620 }
 621
 622 int pciehp_get_max_lnk_width(struct slot *slot,
 623                                  enum pcie_link_width *value)
 624 {
 625         struct controller *ctrl = slot->ctrl;
 626         enum pcie_link_width lnk_wdth;
 627         u32     lnk_cap;
 628         int retval = 0;
 629
 630         retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
 631         if (retval) {
 632                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 633                 return retval;
 634         }
 635
 636         switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
 637         case 0:
 638                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 639                 break;
 640         case 1:
 641                 lnk_wdth = PCIE_LNK_X1;
 642                 break;
 643         case 2:
 644                 lnk_wdth = PCIE_LNK_X2;
 645                 break;
 646         case 4:
 647                 lnk_wdth = PCIE_LNK_X4;
 648                 break;
 649         case 8:
 650                 lnk_wdth = PCIE_LNK_X8;
 651                 break;
 652         case 12:
 653                 lnk_wdth = PCIE_LNK_X12;
 654                 break;
 655         case 16:
 656                 lnk_wdth = PCIE_LNK_X16;
 657                 break;
 658         case 32:
 659                 lnk_wdth = PCIE_LNK_X32;
 660                 break;
 661         default:
 662                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 663                 break;
 664         }
 665
 666         *value = lnk_wdth;
 667         ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
 668
 669         return retval;
 670 }
 671
 672 int pciehp_get_cur_lnk_width(struct slot *slot,
 673                                  enum pcie_link_width *value)
 674 {
 675         struct controller *ctrl = slot->ctrl;
 676         enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 677         int retval = 0;
 678         u16 lnk_status;
 679
 680         retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
 681         if (retval) {
 682                 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
 683                          __func__);
 684                 return retval;
 685         }
 686
 687         switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
 688         case 0:
 689                 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
 690                 break;
 691         case 1:
 692                 lnk_wdth = PCIE_LNK_X1;
 693                 break;
 694         case 2:
 695                 lnk_wdth = PCIE_LNK_X2;
 696                 break;
 697         case 4:
 698                 lnk_wdth = PCIE_LNK_X4;
 699                 break;
 700         case 8:
 701                 lnk_wdth = PCIE_LNK_X8;
 702                 break;
 703         case 12:
 704                 lnk_wdth = PCIE_LNK_X12;
 705                 break;
 706         case 16:
 707                 lnk_wdth = PCIE_LNK_X16;
 708                 break;
 709         case 32:
 710                 lnk_wdth = PCIE_LNK_X32;
 711                 break;
 712         default:
 713                 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
 714                 break;
 715         }
 716
 717         *value = lnk_wdth;
 718         ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
 719
 720         return retval;
 721 }
 722
 723 int pcie_enable_notification(struct controller *ctrl)
 724 {
 725         u16 cmd, mask;
 726
 727         /*
 728          * TBD: Power fault detected software notification support.
 729          *
 730          * Power fault detected software notification is not enabled
 731          * now, because it caused power fault detected interrupt storm
 732          * on some machines. On those machines, power fault detected
 733          * bit in the slot status register was set again immediately
 734          * when it is cleared in the interrupt service routine, and
 735          * next power fault detected interrupt was notified again.
 736          */
 737         cmd = PCI_EXP_SLTCTL_PDCE;
 738         if (ATTN_BUTTN(ctrl))
 739                 cmd |= PCI_EXP_SLTCTL_ABPE;
 740         if (MRL_SENS(ctrl))
 741                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 742         if (!pciehp_poll_mode)
 743                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 744
 745         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 746                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 747                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
 748
 749         if (pcie_write_cmd(ctrl, cmd, mask)) {
 750                 ctrl_err(ctrl, "Cannot enable software notification\n");
 751                 return -1;
 752         }
 753         return 0;
 754 }
 755
 756 static void pcie_disable_notification(struct controller *ctrl)
 757 {
 758         u16 mask;
 759         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 760                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 761                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 762                 PCI_EXP_SLTCTL_DLLSCE);
 763         if (pcie_write_cmd(ctrl, 0, mask))
 764                 ctrl_warn(ctrl, "Cannot disable software notification\n");
 765 }
 766
 767 int pcie_init_notification(struct controller *ctrl)
 768 {
 769         if (pciehp_request_irq(ctrl))
 770                 return -1;
 771         if (pcie_enable_notification(ctrl)) {
 772                 pciehp_free_irq(ctrl);
 773                 return -1;
 774         }
 775         ctrl->notification_enabled = 1;
 776         return 0;
 777 }
 778
 779 static void pcie_shutdown_notification(struct controller *ctrl)
 780 {
 781         if (ctrl->notification_enabled) {
 782                 pcie_disable_notification(ctrl);
 783                 pciehp_free_irq(ctrl);
 784                 ctrl->notification_enabled = 0;
 785         }
 786 }
 787
 788 static int pcie_init_slot(struct controller *ctrl)
 789 {
 790         struct slot *slot;
 791
 792         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 793         if (!slot)
 794                 return -ENOMEM;
 795
 796         slot->ctrl = ctrl;
 797         mutex_init(&slot->lock);
 798         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 799         ctrl->slot = slot;
 800         return 0;
 801 }
 802
 803 static void pcie_cleanup_slot(struct controller *ctrl)
 804 {
 805         struct slot *slot = ctrl->slot;
 806         cancel_delayed_work(&slot->work);
 807         flush_scheduled_work();
 808         flush_workqueue(pciehp_wq);
 809         kfree(slot);
 810 }
 811
 812 static inline void dbg_ctrl(struct controller *ctrl)
 813 {
 814         int i;
 815         u16 reg16;
 816         struct pci_dev *pdev = ctrl->pcie->port;
 817
 818         if (!pciehp_debug)
 819                 return;
 820
 821         ctrl_info(ctrl, "Hotplug Controller:\n");
 822         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 823                   pci_name(pdev), pdev->irq);
 824         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 825         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 826         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 827                   pdev->subsystem_device);
 828         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 829                   pdev->subsystem_vendor);
 830         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 831                   pci_pcie_cap(pdev));
 832         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 833                 if (!pci_resource_len(pdev, i))
 834                         continue;
 835                 ctrl_info(ctrl, "  PCI resource [%d]     : 0x%llx@0x%llx\n",
 836                           i, (unsigned long long)pci_resource_len(pdev, i),
 837                           (unsigned long long)pci_resource_start(pdev, i));
 838         }
 839         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 840         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 841         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 842                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 843         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 844                   POWER_CTRL(ctrl) ? "yes" : "no");
 845         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 846                   MRL_SENS(ctrl)   ? "yes" : "no");
 847         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 848                   ATTN_LED(ctrl)   ? "yes" : "no");
 849         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 850                   PWR_LED(ctrl)    ? "yes" : "no");
 851         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 852                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 853         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 854                   EMI(ctrl)        ? "yes" : "no");
 855         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 856                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 857         pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
 858         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 859         pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
 860         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 861 }
 862
 863 struct controller *pcie_init(struct pcie_device *dev)
 864 {
 865         struct controller *ctrl;
 866         u32 slot_cap, link_cap;
 867         struct pci_dev *pdev = dev->port;
 868
 869         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 870         if (!ctrl) {
 871                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 872                 goto abort;
 873         }
 874         ctrl->pcie = dev;
 875         if (!pci_pcie_cap(pdev)) {
 876                 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
 877                 goto abort_ctrl;
 878         }
 879         if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
 880                 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
 881                 goto abort_ctrl;
 882         }
 883
 884         ctrl->slot_cap = slot_cap;
 885         mutex_init(&ctrl->ctrl_lock);
 886         init_waitqueue_head(&ctrl->queue);
 887         dbg_ctrl(ctrl);
 888         /*
 889          * Controller doesn't notify of command completion if the "No
 890          * Command Completed Support" bit is set in Slot Capability
 891          * register or the controller supports none of power
 892          * controller, attention led, power led and EMI.
 893          */
 894         if (NO_CMD_CMPL(ctrl) ||
 895             !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
 896             ctrl->no_cmd_complete = 1;
 897
 898         /* Check if Data Link Layer Link Active Reporting is implemented */
 899         if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
 900                 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
 901                 goto abort_ctrl;
 902         }
 903         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 904                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 905                 ctrl->link_active_reporting = 1;
 906         }
 907
 908         /* Clear all remaining event bits in Slot Status register */
 909         if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
 910                 goto abort_ctrl;
 911
 912         /* Disable sotfware notification */
 913         pcie_disable_notification(ctrl);
 914
 915         /*
 916          * If this is the first controller to be initialized,
 917          * initialize the pciehp work queue
 918          */
 919         if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
 920                 pciehp_wq = create_singlethread_workqueue("pciehpd");
 921                 if (!pciehp_wq)
 922                         goto abort_ctrl;
 923         }
 924
 925         ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
 926                   pdev->vendor, pdev->device, pdev->subsystem_vendor,
 927                   pdev->subsystem_device);
 928
 929         if (pcie_init_slot(ctrl))
 930                 goto abort_ctrl;
 931
 932         return ctrl;
 933
 934 abort_ctrl:
 935         kfree(ctrl);
 936 abort:
 937         return NULL;
 938 }
 939
 940 void pciehp_release_ctrl(struct controller *ctrl)
 941 {
 942         pcie_shutdown_notification(ctrl);
 943         pcie_cleanup_slot(ctrl);
 944         /*
 945          * If this is the last controller to be released, destroy the
 946          * pciehp work queue
 947          */
 948         if (atomic_dec_and_test(&pciehp_num_controllers))
 949                 destroy_workqueue(pciehp_wq);
 950         kfree(ctrl);
 951 }