projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'intelfb-patches' of master.kernel.org:/pub/scm/linux/kernel/git/airlied...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38
39 #include "../pci.h"
40 #include "pciehp.h"
41 #ifdef DEBUG
42 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
43 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
44 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
45 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
46 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
47 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
48 /* Redefine this flagword to set debug level */
49 #define DEBUG_LEVEL DBG_K_STANDARD
50
51 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
52
53 #define DBG_PRINT( dbg_flags, args... ) \
54 do { \
55 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
56 { \
57 int len; \
58 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
59 __FILE__, __LINE__, __FUNCTION__ ); \
60 sprintf( __dbg_str_buf + len, args ); \
61 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
62 } \
63 } while (0)
64
65 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
66 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
67 #else
68 #define DEFINE_DBG_BUFFER
69 #define DBG_ENTER_ROUTINE
70 #define DBG_LEAVE_ROUTINE
71 #endif /* DEBUG */
72
73 struct ctrl_reg {
74 u8 cap_id;
75 u8 nxt_ptr;
76 u16 cap_reg;
77 u32 dev_cap;
78 u16 dev_ctrl;
79 u16 dev_status;
80 u32 lnk_cap;
81 u16 lnk_ctrl;
82 u16 lnk_status;
83 u32 slot_cap;
84 u16 slot_ctrl;
85 u16 slot_status;
86 u16 root_ctrl;
87 u16 rsvp;
88 u32 root_status;
89 } __attribute__ ((packed));
90
91 /* offsets to the controller registers based on the above structure layout */
92 enum ctrl_offsets {
93 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
94 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
95 CAPREG = offsetof(struct ctrl_reg, cap_reg),
96 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
97 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
98 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
99 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
100 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
101 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
102 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
103 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
104 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
105 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
106 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
107 };
108 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
109
110 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
111 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
112 #define CAP_REG(cb) ( cb + CAPREG )
113 #define DEV_CAP(cb) ( cb + DEVCAP )
114 #define DEV_CTRL(cb) ( cb + DEVCTRL )
115 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
116 #define LNK_CAP(cb) ( cb + LNKCAP )
117 #define LNK_CTRL(cb) ( cb + LNKCTRL )
118 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
119 #define SLOT_CAP(cb) ( cb + SLOTCAP )
120 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
121 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
122 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
123 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
124
125 #define hp_register_read_word(pdev, reg , value) \
126 pci_read_config_word(pdev, reg, &value)
127
128 #define hp_register_read_dword(pdev, reg , value) \
129 pci_read_config_dword(pdev, reg, &value)
130
131 #define hp_register_write_word(pdev, reg , value) \
132 pci_write_config_word(pdev, reg, value)
133
134 #define hp_register_dwrite_word(pdev, reg , value) \
135 pci_write_config_dword(pdev, reg, value)
136
137 /* Field definitions in PCI Express Capabilities Register */
138 #define CAP_VER 0x000F
139 #define DEV_PORT_TYPE 0x00F0
140 #define SLOT_IMPL 0x0100
141 #define MSG_NUM 0x3E00
142
143 /* Device or Port Type */
144 #define NAT_ENDPT 0x00
145 #define LEG_ENDPT 0x01
146 #define ROOT_PORT 0x04
147 #define UP_STREAM 0x05
148 #define DN_STREAM 0x06
149 #define PCIE_PCI_BRDG 0x07
150 #define PCI_PCIE_BRDG 0x10
151
152 /* Field definitions in Device Capabilities Register */
153 #define DATTN_BUTTN_PRSN 0x1000
154 #define DATTN_LED_PRSN 0x2000
155 #define DPWR_LED_PRSN 0x4000
156
157 /* Field definitions in Link Capabilities Register */
158 #define MAX_LNK_SPEED 0x000F
159 #define MAX_LNK_WIDTH 0x03F0
160
161 /* Link Width Encoding */
162 #define LNK_X1 0x01
163 #define LNK_X2 0x02
164 #define LNK_X4 0x04
165 #define LNK_X8 0x08
166 #define LNK_X12 0x0C
167 #define LNK_X16 0x10
168 #define LNK_X32 0x20
169
170 /*Field definitions of Link Status Register */
171 #define LNK_SPEED 0x000F
172 #define NEG_LINK_WD 0x03F0
173 #define LNK_TRN_ERR 0x0400
174 #define LNK_TRN 0x0800
175 #define SLOT_CLK_CONF 0x1000
176
177 /* Field definitions in Slot Capabilities Register */
178 #define ATTN_BUTTN_PRSN 0x00000001
179 #define PWR_CTRL_PRSN 0x00000002
180 #define MRL_SENS_PRSN 0x00000004
181 #define ATTN_LED_PRSN 0x00000008
182 #define PWR_LED_PRSN 0x00000010
183 #define HP_SUPR_RM_SUP 0x00000020
184 #define HP_CAP 0x00000040
185 #define SLOT_PWR_VALUE 0x000003F8
186 #define SLOT_PWR_LIMIT 0x00000C00
187 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
188
189 /* Field definitions in Slot Control Register */
190 #define ATTN_BUTTN_ENABLE 0x0001
191 #define PWR_FAULT_DETECT_ENABLE 0x0002
192 #define MRL_DETECT_ENABLE 0x0004
193 #define PRSN_DETECT_ENABLE 0x0008
194 #define CMD_CMPL_INTR_ENABLE 0x0010
195 #define HP_INTR_ENABLE 0x0020
196 #define ATTN_LED_CTRL 0x00C0
197 #define PWR_LED_CTRL 0x0300
198 #define PWR_CTRL 0x0400
199
200 /* Attention indicator and Power indicator states */
201 #define LED_ON 0x01
202 #define LED_BLINK 0x10
203 #define LED_OFF 0x11
204
205 /* Power Control Command */
206 #define POWER_ON 0
207 #define POWER_OFF 0x0400
208
209 /* Field definitions in Slot Status Register */
210 #define ATTN_BUTTN_PRESSED 0x0001
211 #define PWR_FAULT_DETECTED 0x0002
212 #define MRL_SENS_CHANGED 0x0004
213 #define PRSN_DETECT_CHANGED 0x0008
214 #define CMD_COMPLETED 0x0010
215 #define MRL_STATE 0x0020
216 #define PRSN_STATE 0x0040
217
218 static spinlock_t hpc_event_lock;
219
220 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
221 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
222 static int ctlr_seq_num = 0; /* Controller sequence # */
223 static spinlock_t list_lock;
224
225 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
226
227 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
228
229 /* This is the interrupt polling timeout function. */
230 static void int_poll_timeout(unsigned long lphp_ctlr)
231 {
232 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
233
234 DBG_ENTER_ROUTINE
235
236 if ( !php_ctlr ) {
237 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
238 return;
239 }
240
241 /* Poll for interrupt events. regs == NULL => polling */
242 pcie_isr( 0, (void *)php_ctlr, NULL );
243
244 init_timer(&php_ctlr->int_poll_timer);
245
246 if (!pciehp_poll_time)
247 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
248
249 start_int_poll_timer(php_ctlr, pciehp_poll_time);
250
251 return;
252 }
253
254 /* This function starts the interrupt polling timer. */
255 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
256 {
257 if (!php_ctlr) {
258 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
259 return;
260 }
261
262 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
263 seconds = 2; /* Clamp to sane value */
264
265 php_ctlr->int_poll_timer.function = &int_poll_timeout;
266 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
267 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
268 add_timer(&php_ctlr->int_poll_timer);
269
270 return;
271 }
272
273 static int pcie_write_cmd(struct slot *slot, u16 cmd)
274 {
275 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
276 int retval = 0;
277 u16 slot_status;
278
279 DBG_ENTER_ROUTINE
280
281 if (!php_ctlr) {
282 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
283 return -1;
284 }
285
286 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
287 if (retval) {
288 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
289 return retval;
290 }
291
292 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
293 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
294 the next command according to spec. Just print out the error message */
295 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
296 }
297
298 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
299 if (retval) {
300 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
301 return retval;
302 }
303
304 DBG_LEAVE_ROUTINE
305 return retval;
306 }
307
308 static int hpc_check_lnk_status(struct controller *ctrl)
309 {
310 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
311 u16 lnk_status;
312 int retval = 0;
313
314 DBG_ENTER_ROUTINE
315
316 if (!php_ctlr) {
317 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
318 return -1;
319 }
320
321 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
322
323 if (retval) {
324 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
325 return retval;
326 }
327
328 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
329 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
330 !(lnk_status & NEG_LINK_WD)) {
331 err("%s : Link Training Error occurs \n", __FUNCTION__);
332 retval = -1;
333 return retval;
334 }
335
336 DBG_LEAVE_ROUTINE
337 return retval;
338 }
339
340
341 static int hpc_get_attention_status(struct slot *slot, u8 *status)
342 {
343 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
344 u16 slot_ctrl;
345 u8 atten_led_state;
346 int retval = 0;
347
348 DBG_ENTER_ROUTINE
349
350 if (!php_ctlr) {
351 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
352 return -1;
353 }
354
355 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
356
357 if (retval) {
358 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
359 return retval;
360 }
361
362 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
363
364 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
365
366 switch (atten_led_state) {
367 case 0:
368 *status = 0xFF; /* Reserved */
369 break;
370 case 1:
371 *status = 1; /* On */
372 break;
373 case 2:
374 *status = 2; /* Blink */
375 break;
376 case 3:
377 *status = 0; /* Off */
378 break;
379 default:
380 *status = 0xFF;
381 break;
382 }
383
384 DBG_LEAVE_ROUTINE
385 return 0;
386 }
387
388 static int hpc_get_power_status(struct slot * slot, u8 *status)
389 {
390 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
391 u16 slot_ctrl;
392 u8 pwr_state;
393 int retval = 0;
394
395 DBG_ENTER_ROUTINE
396
397 if (!php_ctlr) {
398 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
399 return -1;
400 }
401
402 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
403
404 if (retval) {
405 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
406 return retval;
407 }
408 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
409
410 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
411
412 switch (pwr_state) {
413 case 0:
414 *status = 1;
415 break;
416 case 1:
417 *status = 0;
418 break;
419 default:
420 *status = 0xFF;
421 break;
422 }
423
424 DBG_LEAVE_ROUTINE
425 return retval;
426 }
427
428
429 static int hpc_get_latch_status(struct slot *slot, u8 *status)
430 {
431 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
432 u16 slot_status;
433 int retval = 0;
434
435 DBG_ENTER_ROUTINE
436
437 if (!php_ctlr) {
438 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
439 return -1;
440 }
441
442 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
443
444 if (retval) {
445 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
446 return retval;
447 }
448
449 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
450
451 DBG_LEAVE_ROUTINE
452 return 0;
453 }
454
455 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
456 {
457 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
458 u16 slot_status;
459 u8 card_state;
460 int retval = 0;
461
462 DBG_ENTER_ROUTINE
463
464 if (!php_ctlr) {
465 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
466 return -1;
467 }
468
469 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
470
471 if (retval) {
472 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
473 return retval;
474 }
475 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
476 *status = (card_state == 1) ? 1 : 0;
477
478 DBG_LEAVE_ROUTINE
479 return 0;
480 }
481
482 static int hpc_query_power_fault(struct slot * slot)
483 {
484 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
485 u16 slot_status;
486 u8 pwr_fault;
487 int retval = 0;
488
489 DBG_ENTER_ROUTINE
490
491 if (!php_ctlr) {
492 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
493 return -1;
494 }
495
496 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
497
498 if (retval) {
499 err("%s : Cannot check for power fault\n", __FUNCTION__);
500 return retval;
501 }
502 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
503
504 DBG_LEAVE_ROUTINE
505 return pwr_fault;
506 }
507
508 static int hpc_set_attention_status(struct slot *slot, u8 value)
509 {
510 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
511 u16 slot_cmd = 0;
512 u16 slot_ctrl;
513 int rc = 0;
514
515 DBG_ENTER_ROUTINE
516
517 if (!php_ctlr) {
518 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
519 return -1;
520 }
521
522 if (slot->hp_slot >= php_ctlr->num_slots) {
523 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
524 return -1;
525 }
526 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
527
528 if (rc) {
529 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
530 return rc;
531 }
532
533 switch (value) {
534 case 0 : /* turn off */
535 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
536 break;
537 case 1: /* turn on */
538 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
539 break;
540 case 2: /* turn blink */
541 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
542 break;
543 default:
544 return -1;
545 }
546 if (!pciehp_poll_mode)
547 slot_cmd = slot_cmd | HP_INTR_ENABLE;
548
549 pcie_write_cmd(slot, slot_cmd);
550 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
551
552 DBG_LEAVE_ROUTINE
553 return rc;
554 }
555
556
557 static void hpc_set_green_led_on(struct slot *slot)
558 {
559 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
560 u16 slot_cmd;
561 u16 slot_ctrl;
562 int rc = 0;
563
564 DBG_ENTER_ROUTINE
565
566 if (!php_ctlr) {
567 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
568 return ;
569 }
570
571 if (slot->hp_slot >= php_ctlr->num_slots) {
572 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
573 return ;
574 }
575
576 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
577
578 if (rc) {
579 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
580 return;
581 }
582 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
583 if (!pciehp_poll_mode)
584 slot_cmd = slot_cmd | HP_INTR_ENABLE;
585
586 pcie_write_cmd(slot, slot_cmd);
587
588 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
589 DBG_LEAVE_ROUTINE
590 return;
591 }
592
593 static void hpc_set_green_led_off(struct slot *slot)
594 {
595 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
596 u16 slot_cmd;
597 u16 slot_ctrl;
598 int rc = 0;
599
600 DBG_ENTER_ROUTINE
601
602 if (!php_ctlr) {
603 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
604 return ;
605 }
606
607 if (slot->hp_slot >= php_ctlr->num_slots) {
608 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
609 return ;
610 }
611
612 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
613
614 if (rc) {
615 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
616 return;
617 }
618
619 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
620
621 if (!pciehp_poll_mode)
622 slot_cmd = slot_cmd | HP_INTR_ENABLE;
623 pcie_write_cmd(slot, slot_cmd);
624 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
625
626 DBG_LEAVE_ROUTINE
627 return;
628 }
629
630 static void hpc_set_green_led_blink(struct slot *slot)
631 {
632 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
633 u16 slot_cmd;
634 u16 slot_ctrl;
635 int rc = 0;
636
637 DBG_ENTER_ROUTINE
638
639 if (!php_ctlr) {
640 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
641 return ;
642 }
643
644 if (slot->hp_slot >= php_ctlr->num_slots) {
645 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
646 return ;
647 }
648
649 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
650
651 if (rc) {
652 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
653 return;
654 }
655
656 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
657
658 if (!pciehp_poll_mode)
659 slot_cmd = slot_cmd | HP_INTR_ENABLE;
660 pcie_write_cmd(slot, slot_cmd);
661
662 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
663 DBG_LEAVE_ROUTINE
664 return;
665 }
666
667 int pcie_get_ctlr_slot_config(struct controller *ctrl,
668 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
669 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
670 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
671 u8 *ctrlcap)
672 {
673 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
674 u32 slot_cap;
675 int rc = 0;
676
677 DBG_ENTER_ROUTINE
678
679 if (!php_ctlr) {
680 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
681 return -1;
682 }
683
684 *first_device_num = 0;
685 *num_ctlr_slots = 1;
686
687 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
688
689 if (rc) {
690 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
691 return -1;
692 }
693
694 *physical_slot_num = slot_cap >> 19;
695 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
696
697 *ctrlcap = slot_cap & 0x0000007f;
698
699 DBG_LEAVE_ROUTINE
700 return 0;
701 }
702
703 static void hpc_release_ctlr(struct controller *ctrl)
704 {
705 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
706 struct php_ctlr_state_s *p, *p_prev;
707
708 DBG_ENTER_ROUTINE
709
710 if (!php_ctlr) {
711 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
712 return ;
713 }
714
715 if (pciehp_poll_mode) {
716 del_timer(&php_ctlr->int_poll_timer);
717 } else {
718 if (php_ctlr->irq) {
719 free_irq(php_ctlr->irq, ctrl);
720 php_ctlr->irq = 0;
721 if (!pcie_mch_quirk)
722 pci_disable_msi(php_ctlr->pci_dev);
723 }
724 }
725 if (php_ctlr->pci_dev)
726 php_ctlr->pci_dev = NULL;
727
728 spin_lock(&list_lock);
729 p = php_ctlr_list_head;
730 p_prev = NULL;
731 while (p) {
732 if (p == php_ctlr) {
733 if (p_prev)
734 p_prev->pnext = p->pnext;
735 else
736 php_ctlr_list_head = p->pnext;
737 break;
738 } else {
739 p_prev = p;
740 p = p->pnext;
741 }
742 }
743 spin_unlock(&list_lock);
744
745 kfree(php_ctlr);
746
747 DBG_LEAVE_ROUTINE
748
749 }
750
751 static int hpc_power_on_slot(struct slot * slot)
752 {
753 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
754 u16 slot_cmd;
755 u16 slot_ctrl, slot_status;
756
757 int retval = 0;
758
759 DBG_ENTER_ROUTINE
760
761 if (!php_ctlr) {
762 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
763 return -1;
764 }
765
766 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
767 if (slot->hp_slot >= php_ctlr->num_slots) {
768 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
769 return -1;
770 }
771
772 /* Clear sticky power-fault bit from previous power failures */
773 hp_register_read_word(php_ctlr->pci_dev,
774 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
775 slot_status &= PWR_FAULT_DETECTED;
776 if (slot_status)
777 hp_register_write_word(php_ctlr->pci_dev,
778 SLOT_STATUS(slot->ctrl->cap_base), slot_status);
779
780 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
781
782 if (retval) {
783 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
784 return retval;
785 }
786
787 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
788
789 /* Enable detection that we turned off at slot power-off time */
790 if (!pciehp_poll_mode)
791 slot_cmd = slot_cmd |
792 PWR_FAULT_DETECT_ENABLE |
793 MRL_DETECT_ENABLE |
794 PRSN_DETECT_ENABLE |
795 HP_INTR_ENABLE;
796
797 retval = pcie_write_cmd(slot, slot_cmd);
798
799 if (retval) {
800 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
801 return -1;
802 }
803 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
804
805 DBG_LEAVE_ROUTINE
806
807 return retval;
808 }
809
810 static int hpc_power_off_slot(struct slot * slot)
811 {
812 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
813 u16 slot_cmd;
814 u16 slot_ctrl;
815
816 int retval = 0;
817
818 DBG_ENTER_ROUTINE
819
820 if (!php_ctlr) {
821 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
822 return -1;
823 }
824
825 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
826 slot->hp_slot = 0;
827 if (slot->hp_slot >= php_ctlr->num_slots) {
828 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
829 return -1;
830 }
831 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
832
833 if (retval) {
834 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
835 return retval;
836 }
837
838 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
839
840 /*
841 * If we get MRL or presence detect interrupts now, the isr
842 * will notice the sticky power-fault bit too and issue power
843 * indicator change commands. This will lead to an endless loop
844 * of command completions, since the power-fault bit remains on
845 * till the slot is powered on again.
846 */
847 if (!pciehp_poll_mode)
848 slot_cmd = (slot_cmd &
849 ~PWR_FAULT_DETECT_ENABLE &
850 ~MRL_DETECT_ENABLE &
851 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
852
853 retval = pcie_write_cmd(slot, slot_cmd);
854
855 if (retval) {
856 err("%s: Write command failed!\n", __FUNCTION__);
857 return -1;
858 }
859 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
860
861 DBG_LEAVE_ROUTINE
862
863 return retval;
864 }
865
866 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
867 {
868 struct controller *ctrl = NULL;
869 struct php_ctlr_state_s *php_ctlr;
870 u8 schedule_flag = 0;
871 u16 slot_status, intr_detect, intr_loc;
872 u16 temp_word;
873 int hp_slot = 0; /* only 1 slot per PCI Express port */
874 int rc = 0;
875
876 if (!dev_id)
877 return IRQ_NONE;
878
879 if (!pciehp_poll_mode) {
880 ctrl = dev_id;
881 php_ctlr = ctrl->hpc_ctlr_handle;
882 } else {
883 php_ctlr = dev_id;
884 ctrl = (struct controller *)php_ctlr->callback_instance_id;
885 }
886
887 if (!ctrl) {
888 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
889 return IRQ_NONE;
890 }
891
892 if (!php_ctlr) {
893 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
894 return IRQ_NONE;
895 }
896
897 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
898 if (rc) {
899 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
900 return IRQ_NONE;
901 }
902
903 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
904 PRSN_DETECT_CHANGED | CMD_COMPLETED );
905
906 intr_loc = slot_status & intr_detect;
907
908 /* Check to see if it was our interrupt */
909 if ( !intr_loc )
910 return IRQ_NONE;
911
912 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
913 /* Mask Hot-plug Interrupt Enable */
914 if (!pciehp_poll_mode) {
915 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
916 if (rc) {
917 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
918 return IRQ_NONE;
919 }
920
921 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
922 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
923
924 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
925 if (rc) {
926 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
927 return IRQ_NONE;
928 }
929
930 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
931 if (rc) {
932 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
933 return IRQ_NONE;
934 }
935 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
936
937 /* Clear command complete interrupt caused by this write */
938 temp_word = 0x1f;
939 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
940 if (rc) {
941 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
942 return IRQ_NONE;
943 }
944 }
945
946 if (intr_loc & CMD_COMPLETED) {
947 /*
948 * Command Complete Interrupt Pending
949 */
950 wake_up_interruptible(&ctrl->queue);
951 }
952
953 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
954 schedule_flag += php_ctlr->switch_change_callback(
955 hp_slot, php_ctlr->callback_instance_id);
956 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
957 schedule_flag += php_ctlr->attention_button_callback(
958 hp_slot, php_ctlr->callback_instance_id);
959 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
960 schedule_flag += php_ctlr->presence_change_callback(
961 hp_slot , php_ctlr->callback_instance_id);
962 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
963 schedule_flag += php_ctlr->power_fault_callback(
964 hp_slot, php_ctlr->callback_instance_id);
965
966 /* Clear all events after serving them */
967 temp_word = 0x1F;
968 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
969 if (rc) {
970 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
971 return IRQ_NONE;
972 }
973 /* Unmask Hot-plug Interrupt Enable */
974 if (!pciehp_poll_mode) {
975 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
976 if (rc) {
977 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
978 return IRQ_NONE;
979 }
980
981 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
982 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
983
984 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
985 if (rc) {
986 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
987 return IRQ_NONE;
988 }
989
990 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
991 if (rc) {
992 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
993 return IRQ_NONE;
994 }
995
996 /* Clear command complete interrupt caused by this write */
997 temp_word = 0x1F;
998 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
999 if (rc) {
1000 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1001 return IRQ_NONE;
1002 }
1003 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1004 }
1005
1006 return IRQ_HANDLED;
1007 }
1008
1009 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1010 {
1011 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1012 enum pcie_link_speed lnk_speed;
1013 u32 lnk_cap;
1014 int retval = 0;
1015
1016 DBG_ENTER_ROUTINE
1017
1018 if (!php_ctlr) {
1019 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1020 return -1;
1021 }
1022
1023 if (slot->hp_slot >= php_ctlr->num_slots) {
1024 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1025 return -1;
1026 }
1027
1028 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1029
1030 if (retval) {
1031 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1032 return retval;
1033 }
1034
1035 switch (lnk_cap & 0x000F) {
1036 case 1:
1037 lnk_speed = PCIE_2PT5GB;
1038 break;
1039 default:
1040 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1041 break;
1042 }
1043
1044 *value = lnk_speed;
1045 dbg("Max link speed = %d\n", lnk_speed);
1046 DBG_LEAVE_ROUTINE
1047 return retval;
1048 }
1049
1050 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1051 {
1052 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1053 enum pcie_link_width lnk_wdth;
1054 u32 lnk_cap;
1055 int retval = 0;
1056
1057 DBG_ENTER_ROUTINE
1058
1059 if (!php_ctlr) {
1060 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1061 return -1;
1062 }
1063
1064 if (slot->hp_slot >= php_ctlr->num_slots) {
1065 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1066 return -1;
1067 }
1068
1069 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1070
1071 if (retval) {
1072 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1073 return retval;
1074 }
1075
1076 switch ((lnk_cap & 0x03F0) >> 4){
1077 case 0:
1078 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1079 break;
1080 case 1:
1081 lnk_wdth = PCIE_LNK_X1;
1082 break;
1083 case 2:
1084 lnk_wdth = PCIE_LNK_X2;
1085 break;
1086 case 4:
1087 lnk_wdth = PCIE_LNK_X4;
1088 break;
1089 case 8:
1090 lnk_wdth = PCIE_LNK_X8;
1091 break;
1092 case 12:
1093 lnk_wdth = PCIE_LNK_X12;
1094 break;
1095 case 16:
1096 lnk_wdth = PCIE_LNK_X16;
1097 break;
1098 case 32:
1099 lnk_wdth = PCIE_LNK_X32;
1100 break;
1101 default:
1102 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1103 break;
1104 }
1105
1106 *value = lnk_wdth;
1107 dbg("Max link width = %d\n", lnk_wdth);
1108 DBG_LEAVE_ROUTINE
1109 return retval;
1110 }
1111
1112 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1113 {
1114 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1115 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1116 int retval = 0;
1117 u16 lnk_status;
1118
1119 DBG_ENTER_ROUTINE
1120
1121 if (!php_ctlr) {
1122 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1123 return -1;
1124 }
1125
1126 if (slot->hp_slot >= php_ctlr->num_slots) {
1127 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1128 return -1;
1129 }
1130
1131 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1132
1133 if (retval) {
1134 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1135 return retval;
1136 }
1137
1138 switch (lnk_status & 0x0F) {
1139 case 1:
1140 lnk_speed = PCIE_2PT5GB;
1141 break;
1142 default:
1143 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1144 break;
1145 }
1146
1147 *value = lnk_speed;
1148 dbg("Current link speed = %d\n", lnk_speed);
1149 DBG_LEAVE_ROUTINE
1150 return retval;
1151 }
1152
1153 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1154 {
1155 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1156 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1157 int retval = 0;
1158 u16 lnk_status;
1159
1160 DBG_ENTER_ROUTINE
1161
1162 if (!php_ctlr) {
1163 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1164 return -1;
1165 }
1166
1167 if (slot->hp_slot >= php_ctlr->num_slots) {
1168 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1169 return -1;
1170 }
1171
1172 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1173
1174 if (retval) {
1175 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1176 return retval;
1177 }
1178
1179 switch ((lnk_status & 0x03F0) >> 4){
1180 case 0:
1181 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1182 break;
1183 case 1:
1184 lnk_wdth = PCIE_LNK_X1;
1185 break;
1186 case 2:
1187 lnk_wdth = PCIE_LNK_X2;
1188 break;
1189 case 4:
1190 lnk_wdth = PCIE_LNK_X4;
1191 break;
1192 case 8:
1193 lnk_wdth = PCIE_LNK_X8;
1194 break;
1195 case 12:
1196 lnk_wdth = PCIE_LNK_X12;
1197 break;
1198 case 16:
1199 lnk_wdth = PCIE_LNK_X16;
1200 break;
1201 case 32:
1202 lnk_wdth = PCIE_LNK_X32;
1203 break;
1204 default:
1205 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1206 break;
1207 }
1208
1209 *value = lnk_wdth;
1210 dbg("Current link width = %d\n", lnk_wdth);
1211 DBG_LEAVE_ROUTINE
1212 return retval;
1213 }
1214
1215 static struct hpc_ops pciehp_hpc_ops = {
1216 .power_on_slot = hpc_power_on_slot,
1217 .power_off_slot = hpc_power_off_slot,
1218 .set_attention_status = hpc_set_attention_status,
1219 .get_power_status = hpc_get_power_status,
1220 .get_attention_status = hpc_get_attention_status,
1221 .get_latch_status = hpc_get_latch_status,
1222 .get_adapter_status = hpc_get_adapter_status,
1223
1224 .get_max_bus_speed = hpc_get_max_lnk_speed,
1225 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1226 .get_max_lnk_width = hpc_get_max_lnk_width,
1227 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1228
1229 .query_power_fault = hpc_query_power_fault,
1230 .green_led_on = hpc_set_green_led_on,
1231 .green_led_off = hpc_set_green_led_off,
1232 .green_led_blink = hpc_set_green_led_blink,
1233
1234 .release_ctlr = hpc_release_ctlr,
1235 .check_lnk_status = hpc_check_lnk_status,
1236 };
1237
1238 #ifdef CONFIG_ACPI
1239 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1240 {
1241 acpi_status status;
1242 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1243 struct pci_dev *pdev = dev;
1244 struct pci_bus *parent;
1245 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1246
1247 /*
1248 * Per PCI firmware specification, we should run the ACPI _OSC
1249 * method to get control of hotplug hardware before using it.
1250 * If an _OSC is missing, we look for an OSHP to do the same thing.
1251 * To handle different BIOS behavior, we look for _OSC and OSHP
1252 * within the scope of the hotplug controller and its parents, upto
1253 * the host bridge under which this controller exists.
1254 */
1255 while (!handle) {
1256 /*
1257 * This hotplug controller was not listed in the ACPI name
1258 * space at all. Try to get acpi handle of parent pci bus.
1259 */
1260 if (!pdev || !pdev->bus->parent)
1261 break;
1262 parent = pdev->bus->parent;
1263 dbg("Could not find %s in acpi namespace, trying parent\n",
1264 pci_name(pdev));
1265 if (!parent->self)
1266 /* Parent must be a host bridge */
1267 handle = acpi_get_pci_rootbridge_handle(
1268 pci_domain_nr(parent),
1269 parent->number);
1270 else
1271 handle = DEVICE_ACPI_HANDLE(
1272 &(parent->self->dev));
1273 pdev = parent->self;
1274 }
1275
1276 while (handle) {
1277 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1278 dbg("Trying to get hotplug control for %s \n",
1279 (char *)string.pointer);
1280 status = pci_osc_control_set(handle,
1281 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1282 if (status == AE_NOT_FOUND)
1283 status = acpi_run_oshp(handle);
1284 if (ACPI_SUCCESS(status)) {
1285 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1286 pci_name(dev), (char *)string.pointer);
1287 kfree(string.pointer);
1288 return 0;
1289 }
1290 if (acpi_root_bridge(handle))
1291 break;
1292 chandle = handle;
1293 status = acpi_get_parent(chandle, &handle);
1294 if (ACPI_FAILURE(status))
1295 break;
1296 }
1297
1298 err("Cannot get control of hotplug hardware for pci %s\n",
1299 pci_name(dev));
1300
1301 kfree(string.pointer);
1302 return -1;
1303 }
1304 #endif
1305
1306
1307
1308 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1309 {
1310 struct php_ctlr_state_s *php_ctlr, *p;
1311 void *instance_id = ctrl;
1312 int rc;
1313 static int first = 1;
1314 u16 temp_word;
1315 u16 cap_reg;
1316 u16 intr_enable = 0;
1317 u32 slot_cap;
1318 int cap_base, saved_cap_base;
1319 u16 slot_status, slot_ctrl;
1320 struct pci_dev *pdev;
1321
1322 DBG_ENTER_ROUTINE
1323
1324 spin_lock_init(&list_lock);
1325 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1326
1327 if (!php_ctlr) { /* allocate controller state data */
1328 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1329 goto abort;
1330 }
1331
1332 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1333
1334 pdev = dev->port;
1335 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1336
1337 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1338 __FUNCTION__, pdev->vendor, pdev->device);
1339
1340 saved_cap_base = pcie_cap_base;
1341
1342 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1343 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1344 goto abort_free_ctlr;
1345 }
1346
1347 ctrl->cap_base = cap_base;
1348
1349 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1350
1351 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1352 if (rc) {
1353 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1354 goto abort_free_ctlr;
1355 }
1356 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1357
1358 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1359 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1360 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1361 goto abort_free_ctlr;
1362 }
1363
1364 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1365 if (rc) {
1366 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1367 goto abort_free_ctlr;
1368 }
1369 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1370
1371 if (!(slot_cap & HP_CAP)) {
1372 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1373 goto abort_free_ctlr;
1374 }
1375 /* For debugging purpose */
1376 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1377 if (rc) {
1378 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1379 goto abort_free_ctlr;
1380 }
1381 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1382
1383 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1384 if (rc) {
1385 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1386 goto abort_free_ctlr;
1387 }
1388 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1389
1390 if (first) {
1391 spin_lock_init(&hpc_event_lock);
1392 first = 0;
1393 }
1394
1395 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1396 if (pci_resource_len(pdev, rc) > 0)
1397 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1398 (unsigned long long)pci_resource_start(pdev, rc),
1399 (unsigned long long)pci_resource_len(pdev, rc));
1400
1401 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1402 pdev->subsystem_vendor, pdev->subsystem_device);
1403
1404 mutex_init(&ctrl->crit_sect);
1405 /* setup wait queue */
1406 init_waitqueue_head(&ctrl->queue);
1407
1408 /* find the IRQ */
1409 php_ctlr->irq = dev->irq;
1410
1411 /* Save interrupt callback info */
1412 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1413 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1414 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1415 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1416 php_ctlr->callback_instance_id = instance_id;
1417
1418 /* return PCI Controller Info */
1419 php_ctlr->slot_device_offset = 0;
1420 php_ctlr->num_slots = 1;
1421
1422 /* Mask Hot-plug Interrupt Enable */
1423 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1424 if (rc) {
1425 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1426 goto abort_free_ctlr;
1427 }
1428
1429 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1430 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1431
1432 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1433 if (rc) {
1434 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1435 goto abort_free_ctlr;
1436 }
1437
1438 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1439 if (rc) {
1440 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1441 goto abort_free_ctlr;
1442 }
1443
1444 temp_word = 0x1F; /* Clear all events */
1445 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1446 if (rc) {
1447 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1448 goto abort_free_ctlr;
1449 }
1450
1451 if (pciehp_poll_mode) {/* Install interrupt polling code */
1452 /* Install and start the interrupt polling timer */
1453 init_timer(&php_ctlr->int_poll_timer);
1454 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1455 } else {
1456 /* Installs the interrupt handler */
1457 rc = request_irq(php_ctlr->irq, pcie_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
1458 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1459 if (rc) {
1460 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1461 goto abort_free_ctlr;
1462 }
1463 }
1464
1465 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1466 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1467
1468 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1469 if (rc) {
1470 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1471 goto abort_free_irq;
1472 }
1473
1474 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1475
1476 if (ATTN_BUTTN(slot_cap))
1477 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1478
1479 if (POWER_CTRL(slot_cap))
1480 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1481
1482 if (MRL_SENS(slot_cap))
1483 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1484
1485 temp_word = (temp_word & ~intr_enable) | intr_enable;
1486
1487 if (pciehp_poll_mode) {
1488 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1489 } else {
1490 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1491 }
1492
1493 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1494 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1495 if (rc) {
1496 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1497 goto abort_free_irq;
1498 }
1499 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1500 if (rc) {
1501 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1502 goto abort_disable_intr;
1503 }
1504
1505 temp_word = 0x1F; /* Clear all events */
1506 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1507 if (rc) {
1508 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1509 goto abort_disable_intr;
1510 }
1511
1512 if (pciehp_force) {
1513 dbg("Bypassing BIOS check for pciehp use on %s\n",
1514 pci_name(ctrl->pci_dev));
1515 } else {
1516 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1517 if (rc)
1518 goto abort_disable_intr;
1519 }
1520
1521 /* Add this HPC instance into the HPC list */
1522 spin_lock(&list_lock);
1523 if (php_ctlr_list_head == 0) {
1524 php_ctlr_list_head = php_ctlr;
1525 p = php_ctlr_list_head;
1526 p->pnext = NULL;
1527 } else {
1528 p = php_ctlr_list_head;
1529
1530 while (p->pnext)
1531 p = p->pnext;
1532
1533 p->pnext = php_ctlr;
1534 }
1535 spin_unlock(&list_lock);
1536
1537 ctlr_seq_num++;
1538 ctrl->hpc_ctlr_handle = php_ctlr;
1539 ctrl->hpc_ops = &pciehp_hpc_ops;
1540
1541 DBG_LEAVE_ROUTINE
1542 return 0;
1543
1544 /* We end up here for the many possible ways to fail this API. */
1545 abort_disable_intr:
1546 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1547 if (!rc) {
1548 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1549 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1550 }
1551 if (rc)
1552 err("%s : disabling interrupts failed\n", __FUNCTION__);
1553
1554 abort_free_irq:
1555 if (pciehp_poll_mode)
1556 del_timer_sync(&php_ctlr->int_poll_timer);
1557 else
1558 free_irq(php_ctlr->irq, ctrl);
1559
1560 abort_free_ctlr:
1561 pcie_cap_base = saved_cap_base;
1562 kfree(php_ctlr);
1563 abort:
1564 DBG_LEAVE_ROUTINE
1565 return -1;
1566 }
kernel source for telekom puls (alcatel/mediatek)