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Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46 {
47 struct pci_dev *dev = ctrl->pci_dev;
48 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
49 }
50
51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52 {
53 struct pci_dev *dev = ctrl->pci_dev;
54 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
55 }
56
57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58 {
59 struct pci_dev *dev = ctrl->pci_dev;
60 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
61 }
62
63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64 {
65 struct pci_dev *dev = ctrl->pci_dev;
66 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
67 }
68
69 /* Power Control Command */
70 #define POWER_ON 0
71 #define POWER_OFF PCI_EXP_SLTCTL_PCC
72
73 static irqreturn_t pcie_isr(int irq, void *dev_id);
74 static void start_int_poll_timer(struct controller *ctrl, int sec);
75
76 /* This is the interrupt polling timeout function. */
77 static void int_poll_timeout(unsigned long data)
78 {
79 struct controller *ctrl = (struct controller *)data;
80
81 /* Poll for interrupt events. regs == NULL => polling */
82 pcie_isr(0, ctrl);
83
84 init_timer(&ctrl->poll_timer);
85 if (!pciehp_poll_time)
86 pciehp_poll_time = 2; /* default polling interval is 2 sec */
87
88 start_int_poll_timer(ctrl, pciehp_poll_time);
89 }
90
91 /* This function starts the interrupt polling timer. */
92 static void start_int_poll_timer(struct controller *ctrl, int sec)
93 {
94 /* Clamp to sane value */
95 if ((sec <= 0) || (sec > 60))
96 sec = 2;
97
98 ctrl->poll_timer.function = &int_poll_timeout;
99 ctrl->poll_timer.data = (unsigned long)ctrl;
100 ctrl->poll_timer.expires = jiffies + sec * HZ;
101 add_timer(&ctrl->poll_timer);
102 }
103
104 static inline int pciehp_request_irq(struct controller *ctrl)
105 {
106 int retval, irq = ctrl->pcie->irq;
107
108 /* Install interrupt polling timer. Start with 10 sec delay */
109 if (pciehp_poll_mode) {
110 init_timer(&ctrl->poll_timer);
111 start_int_poll_timer(ctrl, 10);
112 return 0;
113 }
114
115 /* Installs the interrupt handler */
116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 if (retval)
118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
119 irq);
120 return retval;
121 }
122
123 static inline void pciehp_free_irq(struct controller *ctrl)
124 {
125 if (pciehp_poll_mode)
126 del_timer_sync(&ctrl->poll_timer);
127 else
128 free_irq(ctrl->pcie->irq, ctrl);
129 }
130
131 static int pcie_poll_cmd(struct controller *ctrl)
132 {
133 u16 slot_status;
134 int err, timeout = 1000;
135
136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
139 return 1;
140 }
141 while (timeout > 0) {
142 msleep(10);
143 timeout -= 10;
144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
147 return 1;
148 }
149 }
150 return 0; /* timeout */
151 }
152
153 static void pcie_wait_cmd(struct controller *ctrl, int poll)
154 {
155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
156 unsigned long timeout = msecs_to_jiffies(msecs);
157 int rc;
158
159 if (poll)
160 rc = pcie_poll_cmd(ctrl);
161 else
162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 if (!rc)
164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
165 }
166
167 /**
168 * pcie_write_cmd - Issue controller command
169 * @ctrl: controller to which the command is issued
170 * @cmd: command value written to slot control register
171 * @mask: bitmask of slot control register to be modified
172 */
173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
174 {
175 int retval = 0;
176 u16 slot_status;
177 u16 slot_ctrl;
178
179 mutex_lock(&ctrl->ctrl_lock);
180
181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
182 if (retval) {
183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
184 __func__);
185 goto out;
186 }
187
188 if (slot_status & PCI_EXP_SLTSTA_CC) {
189 if (!ctrl->no_cmd_complete) {
190 /*
191 * After 1 sec and CMD_COMPLETED still not set, just
192 * proceed forward to issue the next command according
193 * to spec. Just print out the error message.
194 */
195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
196 } else if (!NO_CMD_CMPL(ctrl)) {
197 /*
198 * This controller semms to notify of command completed
199 * event even though it supports none of power
200 * controller, attention led, power led and EMI.
201 */
202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 "wait for command completed event.\n");
204 ctrl->no_cmd_complete = 0;
205 } else {
206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
207 "the controller is broken.\n");
208 }
209 }
210
211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
212 if (retval) {
213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
214 goto out;
215 }
216
217 slot_ctrl &= ~mask;
218 slot_ctrl |= (cmd & mask);
219 ctrl->cmd_busy = 1;
220 smp_mb();
221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
222 if (retval)
223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
224
225 /*
226 * Wait for command completion.
227 */
228 if (!retval && !ctrl->no_cmd_complete) {
229 int poll = 0;
230 /*
231 * if hotplug interrupt is not enabled or command
232 * completed interrupt is not enabled, we need to poll
233 * command completed event.
234 */
235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
237 poll = 1;
238 pcie_wait_cmd(ctrl, poll);
239 }
240 out:
241 mutex_unlock(&ctrl->ctrl_lock);
242 return retval;
243 }
244
245 static inline int check_link_active(struct controller *ctrl)
246 {
247 u16 link_status;
248
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
250 return 0;
251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
252 }
253
254 static void pcie_wait_link_active(struct controller *ctrl)
255 {
256 int timeout = 1000;
257
258 if (check_link_active(ctrl))
259 return;
260 while (timeout > 0) {
261 msleep(10);
262 timeout -= 10;
263 if (check_link_active(ctrl))
264 return;
265 }
266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
267 }
268
269 static int hpc_check_lnk_status(struct controller *ctrl)
270 {
271 u16 lnk_status;
272 int retval = 0;
273
274 /*
275 * Data Link Layer Link Active Reporting must be capable for
276 * hot-plug capable downstream port. But old controller might
277 * not implement it. In this case, we wait for 1000 ms.
278 */
279 if (ctrl->link_active_reporting){
280 /* Wait for Data Link Layer Link Active bit to be set */
281 pcie_wait_link_active(ctrl);
282 /*
283 * We must wait for 100 ms after the Data Link Layer
284 * Link Active bit reads 1b before initiating a
285 * configuration access to the hot added device.
286 */
287 msleep(100);
288 } else
289 msleep(1000);
290
291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
292 if (retval) {
293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
294 return retval;
295 }
296
297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
298 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
300 ctrl_err(ctrl, "Link Training Error occurs \n");
301 retval = -1;
302 return retval;
303 }
304
305 return retval;
306 }
307
308 static int hpc_get_attention_status(struct slot *slot, u8 *status)
309 {
310 struct controller *ctrl = slot->ctrl;
311 u16 slot_ctrl;
312 u8 atten_led_state;
313 int retval = 0;
314
315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
316 if (retval) {
317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
318 return retval;
319 }
320
321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n",
322 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
323
324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
325
326 switch (atten_led_state) {
327 case 0:
328 *status = 0xFF; /* Reserved */
329 break;
330 case 1:
331 *status = 1; /* On */
332 break;
333 case 2:
334 *status = 2; /* Blink */
335 break;
336 case 3:
337 *status = 0; /* Off */
338 break;
339 default:
340 *status = 0xFF;
341 break;
342 }
343
344 return 0;
345 }
346
347 static int hpc_get_power_status(struct slot *slot, u8 *status)
348 {
349 struct controller *ctrl = slot->ctrl;
350 u16 slot_ctrl;
351 u8 pwr_state;
352 int retval = 0;
353
354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
355 if (retval) {
356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
357 return retval;
358 }
359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n",
360 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_ctrl);
361
362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
363
364 switch (pwr_state) {
365 case 0:
366 *status = 1;
367 break;
368 case 1:
369 *status = 0;
370 break;
371 default:
372 *status = 0xFF;
373 break;
374 }
375
376 return retval;
377 }
378
379 static int hpc_get_latch_status(struct slot *slot, u8 *status)
380 {
381 struct controller *ctrl = slot->ctrl;
382 u16 slot_status;
383 int retval;
384
385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
386 if (retval) {
387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
388 __func__);
389 return retval;
390 }
391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
392 return 0;
393 }
394
395 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
396 {
397 struct controller *ctrl = slot->ctrl;
398 u16 slot_status;
399 int retval;
400
401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
402 if (retval) {
403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
404 __func__);
405 return retval;
406 }
407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
408 return 0;
409 }
410
411 static int hpc_query_power_fault(struct slot *slot)
412 {
413 struct controller *ctrl = slot->ctrl;
414 u16 slot_status;
415 int retval;
416
417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
418 if (retval) {
419 ctrl_err(ctrl, "Cannot check for power fault\n");
420 return retval;
421 }
422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
423 }
424
425 static int hpc_set_attention_status(struct slot *slot, u8 value)
426 {
427 struct controller *ctrl = slot->ctrl;
428 u16 slot_cmd;
429 u16 cmd_mask;
430 int rc;
431
432 cmd_mask = PCI_EXP_SLTCTL_AIC;
433 switch (value) {
434 case 0 : /* turn off */
435 slot_cmd = 0x00C0;
436 break;
437 case 1: /* turn on */
438 slot_cmd = 0x0040;
439 break;
440 case 2: /* turn blink */
441 slot_cmd = 0x0080;
442 break;
443 default:
444 return -1;
445 }
446 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
448 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
449
450 return rc;
451 }
452
453 static void hpc_set_green_led_on(struct slot *slot)
454 {
455 struct controller *ctrl = slot->ctrl;
456 u16 slot_cmd;
457 u16 cmd_mask;
458
459 slot_cmd = 0x0100;
460 cmd_mask = PCI_EXP_SLTCTL_PIC;
461 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
462 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
463 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
464 }
465
466 static void hpc_set_green_led_off(struct slot *slot)
467 {
468 struct controller *ctrl = slot->ctrl;
469 u16 slot_cmd;
470 u16 cmd_mask;
471
472 slot_cmd = 0x0300;
473 cmd_mask = PCI_EXP_SLTCTL_PIC;
474 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
475 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
476 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
477 }
478
479 static void hpc_set_green_led_blink(struct slot *slot)
480 {
481 struct controller *ctrl = slot->ctrl;
482 u16 slot_cmd;
483 u16 cmd_mask;
484
485 slot_cmd = 0x0200;
486 cmd_mask = PCI_EXP_SLTCTL_PIC;
487 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
489 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
490 }
491
492 static int hpc_power_on_slot(struct slot * slot)
493 {
494 struct controller *ctrl = slot->ctrl;
495 u16 slot_cmd;
496 u16 cmd_mask;
497 u16 slot_status;
498 int retval = 0;
499
500 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
501
502 /* Clear sticky power-fault bit from previous power failures */
503 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
504 if (retval) {
505 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
506 __func__);
507 return retval;
508 }
509 slot_status &= PCI_EXP_SLTSTA_PFD;
510 if (slot_status) {
511 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
512 if (retval) {
513 ctrl_err(ctrl,
514 "%s: Cannot write to SLOTSTATUS register\n",
515 __func__);
516 return retval;
517 }
518 }
519
520 slot_cmd = POWER_ON;
521 cmd_mask = PCI_EXP_SLTCTL_PCC;
522 if (!pciehp_poll_mode) {
523 /* Enable power fault detection turned off at power off time */
524 slot_cmd |= PCI_EXP_SLTCTL_PFDE;
525 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
526 }
527
528 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
529 if (retval) {
530 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
531 return retval;
532 }
533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
534 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
535
536 ctrl->power_fault_detected = 0;
537 return retval;
538 }
539
540 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
541 {
542 struct pci_dev *dev = ctrl->pci_dev;
543 int pos;
544 u32 reg;
545
546 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
547 if (!pos)
548 return 0;
549 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
550 if (reg & PCI_ERR_COR_BAD_DLLP)
551 return 0;
552 reg |= PCI_ERR_COR_BAD_DLLP;
553 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
554 return 1;
555 }
556
557 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
558 {
559 struct pci_dev *dev = ctrl->pci_dev;
560 u32 reg;
561 int pos;
562
563 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
564 if (!pos)
565 return;
566 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
567 if (!(reg & PCI_ERR_COR_BAD_DLLP))
568 return;
569 reg &= ~PCI_ERR_COR_BAD_DLLP;
570 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
571 }
572
573 static int hpc_power_off_slot(struct slot * slot)
574 {
575 struct controller *ctrl = slot->ctrl;
576 u16 slot_cmd;
577 u16 cmd_mask;
578 int retval = 0;
579 int changed;
580
581 ctrl_dbg(ctrl, "%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
582
583 /*
584 * Set Bad DLLP Mask bit in Correctable Error Mask
585 * Register. This is the workaround against Bad DLLP error
586 * that sometimes happens during turning power off the slot
587 * which conforms to PCI Express 1.0a spec.
588 */
589 changed = pcie_mask_bad_dllp(ctrl);
590
591 slot_cmd = POWER_OFF;
592 cmd_mask = PCI_EXP_SLTCTL_PCC;
593 if (!pciehp_poll_mode) {
594 /* Disable power fault detection */
595 slot_cmd &= ~PCI_EXP_SLTCTL_PFDE;
596 cmd_mask |= PCI_EXP_SLTCTL_PFDE;
597 }
598
599 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
600 if (retval) {
601 ctrl_err(ctrl, "Write command failed!\n");
602 retval = -1;
603 goto out;
604 }
605 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n",
606 __func__, ctrl->cap_base + PCI_EXP_SLTCTL, slot_cmd);
607 out:
608 if (changed)
609 pcie_unmask_bad_dllp(ctrl);
610
611 return retval;
612 }
613
614 static irqreturn_t pcie_isr(int irq, void *dev_id)
615 {
616 struct controller *ctrl = (struct controller *)dev_id;
617 u16 detected, intr_loc;
618 struct slot *p_slot;
619
620 /*
621 * In order to guarantee that all interrupt events are
622 * serviced, we need to re-inspect Slot Status register after
623 * clearing what is presumed to be the last pending interrupt.
624 */
625 intr_loc = 0;
626 do {
627 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
628 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
629 __func__);
630 return IRQ_NONE;
631 }
632
633 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
634 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
635 PCI_EXP_SLTSTA_CC);
636 detected &= ~intr_loc;
637 intr_loc |= detected;
638 if (!intr_loc)
639 return IRQ_NONE;
640 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
641 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
642 __func__);
643 return IRQ_NONE;
644 }
645 } while (detected);
646
647 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
648
649 /* Check Command Complete Interrupt Pending */
650 if (intr_loc & PCI_EXP_SLTSTA_CC) {
651 ctrl->cmd_busy = 0;
652 smp_mb();
653 wake_up(&ctrl->queue);
654 }
655
656 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
657 return IRQ_HANDLED;
658
659 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
660
661 /* Check MRL Sensor Changed */
662 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
663 pciehp_handle_switch_change(p_slot);
664
665 /* Check Attention Button Pressed */
666 if (intr_loc & PCI_EXP_SLTSTA_ABP)
667 pciehp_handle_attention_button(p_slot);
668
669 /* Check Presence Detect Changed */
670 if (intr_loc & PCI_EXP_SLTSTA_PDC)
671 pciehp_handle_presence_change(p_slot);
672
673 /* Check Power Fault Detected */
674 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
675 ctrl->power_fault_detected = 1;
676 pciehp_handle_power_fault(p_slot);
677 }
678 return IRQ_HANDLED;
679 }
680
681 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
682 {
683 struct controller *ctrl = slot->ctrl;
684 enum pcie_link_speed lnk_speed;
685 u32 lnk_cap;
686 int retval = 0;
687
688 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
689 if (retval) {
690 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
691 return retval;
692 }
693
694 switch (lnk_cap & 0x000F) {
695 case 1:
696 lnk_speed = PCIE_2PT5GB;
697 break;
698 default:
699 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
700 break;
701 }
702
703 *value = lnk_speed;
704 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
705
706 return retval;
707 }
708
709 static int hpc_get_max_lnk_width(struct slot *slot,
710 enum pcie_link_width *value)
711 {
712 struct controller *ctrl = slot->ctrl;
713 enum pcie_link_width lnk_wdth;
714 u32 lnk_cap;
715 int retval = 0;
716
717 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
718 if (retval) {
719 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
720 return retval;
721 }
722
723 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
724 case 0:
725 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
726 break;
727 case 1:
728 lnk_wdth = PCIE_LNK_X1;
729 break;
730 case 2:
731 lnk_wdth = PCIE_LNK_X2;
732 break;
733 case 4:
734 lnk_wdth = PCIE_LNK_X4;
735 break;
736 case 8:
737 lnk_wdth = PCIE_LNK_X8;
738 break;
739 case 12:
740 lnk_wdth = PCIE_LNK_X12;
741 break;
742 case 16:
743 lnk_wdth = PCIE_LNK_X16;
744 break;
745 case 32:
746 lnk_wdth = PCIE_LNK_X32;
747 break;
748 default:
749 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
750 break;
751 }
752
753 *value = lnk_wdth;
754 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
755
756 return retval;
757 }
758
759 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
760 {
761 struct controller *ctrl = slot->ctrl;
762 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
763 int retval = 0;
764 u16 lnk_status;
765
766 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
767 if (retval) {
768 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
769 __func__);
770 return retval;
771 }
772
773 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
774 case 1:
775 lnk_speed = PCIE_2PT5GB;
776 break;
777 default:
778 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
779 break;
780 }
781
782 *value = lnk_speed;
783 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
784
785 return retval;
786 }
787
788 static int hpc_get_cur_lnk_width(struct slot *slot,
789 enum pcie_link_width *value)
790 {
791 struct controller *ctrl = slot->ctrl;
792 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
793 int retval = 0;
794 u16 lnk_status;
795
796 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
797 if (retval) {
798 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
799 __func__);
800 return retval;
801 }
802
803 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
804 case 0:
805 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
806 break;
807 case 1:
808 lnk_wdth = PCIE_LNK_X1;
809 break;
810 case 2:
811 lnk_wdth = PCIE_LNK_X2;
812 break;
813 case 4:
814 lnk_wdth = PCIE_LNK_X4;
815 break;
816 case 8:
817 lnk_wdth = PCIE_LNK_X8;
818 break;
819 case 12:
820 lnk_wdth = PCIE_LNK_X12;
821 break;
822 case 16:
823 lnk_wdth = PCIE_LNK_X16;
824 break;
825 case 32:
826 lnk_wdth = PCIE_LNK_X32;
827 break;
828 default:
829 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
830 break;
831 }
832
833 *value = lnk_wdth;
834 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
835
836 return retval;
837 }
838
839 static void pcie_release_ctrl(struct controller *ctrl);
840 static struct hpc_ops pciehp_hpc_ops = {
841 .power_on_slot = hpc_power_on_slot,
842 .power_off_slot = hpc_power_off_slot,
843 .set_attention_status = hpc_set_attention_status,
844 .get_power_status = hpc_get_power_status,
845 .get_attention_status = hpc_get_attention_status,
846 .get_latch_status = hpc_get_latch_status,
847 .get_adapter_status = hpc_get_adapter_status,
848
849 .get_max_bus_speed = hpc_get_max_lnk_speed,
850 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
851 .get_max_lnk_width = hpc_get_max_lnk_width,
852 .get_cur_lnk_width = hpc_get_cur_lnk_width,
853
854 .query_power_fault = hpc_query_power_fault,
855 .green_led_on = hpc_set_green_led_on,
856 .green_led_off = hpc_set_green_led_off,
857 .green_led_blink = hpc_set_green_led_blink,
858
859 .release_ctlr = pcie_release_ctrl,
860 .check_lnk_status = hpc_check_lnk_status,
861 };
862
863 int pcie_enable_notification(struct controller *ctrl)
864 {
865 u16 cmd, mask;
866
867 cmd = PCI_EXP_SLTCTL_PDCE;
868 if (ATTN_BUTTN(ctrl))
869 cmd |= PCI_EXP_SLTCTL_ABPE;
870 if (POWER_CTRL(ctrl))
871 cmd |= PCI_EXP_SLTCTL_PFDE;
872 if (MRL_SENS(ctrl))
873 cmd |= PCI_EXP_SLTCTL_MRLSCE;
874 if (!pciehp_poll_mode)
875 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
876
877 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
878 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
879 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
880
881 if (pcie_write_cmd(ctrl, cmd, mask)) {
882 ctrl_err(ctrl, "Cannot enable software notification\n");
883 return -1;
884 }
885 return 0;
886 }
887
888 static void pcie_disable_notification(struct controller *ctrl)
889 {
890 u16 mask;
891 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
892 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
893 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
894 if (pcie_write_cmd(ctrl, 0, mask))
895 ctrl_warn(ctrl, "Cannot disable software notification\n");
896 }
897
898 int pcie_init_notification(struct controller *ctrl)
899 {
900 if (pciehp_request_irq(ctrl))
901 return -1;
902 if (pcie_enable_notification(ctrl)) {
903 pciehp_free_irq(ctrl);
904 return -1;
905 }
906 ctrl->notification_enabled = 1;
907 return 0;
908 }
909
910 static void pcie_shutdown_notification(struct controller *ctrl)
911 {
912 if (ctrl->notification_enabled) {
913 pcie_disable_notification(ctrl);
914 pciehp_free_irq(ctrl);
915 ctrl->notification_enabled = 0;
916 }
917 }
918
919 static int pcie_init_slot(struct controller *ctrl)
920 {
921 struct slot *slot;
922
923 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
924 if (!slot)
925 return -ENOMEM;
926
927 slot->hp_slot = 0;
928 slot->ctrl = ctrl;
929 slot->bus = ctrl->pci_dev->subordinate->number;
930 slot->device = ctrl->slot_device_offset + slot->hp_slot;
931 slot->hpc_ops = ctrl->hpc_ops;
932 slot->number = ctrl->first_slot;
933 mutex_init(&slot->lock);
934 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
935 list_add(&slot->slot_list, &ctrl->slot_list);
936 return 0;
937 }
938
939 static void pcie_cleanup_slot(struct controller *ctrl)
940 {
941 struct slot *slot;
942 slot = list_first_entry(&ctrl->slot_list, struct slot, slot_list);
943 list_del(&slot->slot_list);
944 cancel_delayed_work(&slot->work);
945 flush_scheduled_work();
946 flush_workqueue(pciehp_wq);
947 kfree(slot);
948 }
949
950 static inline void dbg_ctrl(struct controller *ctrl)
951 {
952 int i;
953 u16 reg16;
954 struct pci_dev *pdev = ctrl->pci_dev;
955
956 if (!pciehp_debug)
957 return;
958
959 ctrl_info(ctrl, "Hotplug Controller:\n");
960 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
961 pci_name(pdev), pdev->irq);
962 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
963 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
964 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
965 pdev->subsystem_device);
966 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
967 pdev->subsystem_vendor);
968 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
969 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
970 if (!pci_resource_len(pdev, i))
971 continue;
972 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
973 i, (unsigned long long)pci_resource_len(pdev, i),
974 (unsigned long long)pci_resource_start(pdev, i));
975 }
976 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
977 ctrl_info(ctrl, " Physical Slot Number : %d\n", ctrl->first_slot);
978 ctrl_info(ctrl, " Attention Button : %3s\n",
979 ATTN_BUTTN(ctrl) ? "yes" : "no");
980 ctrl_info(ctrl, " Power Controller : %3s\n",
981 POWER_CTRL(ctrl) ? "yes" : "no");
982 ctrl_info(ctrl, " MRL Sensor : %3s\n",
983 MRL_SENS(ctrl) ? "yes" : "no");
984 ctrl_info(ctrl, " Attention Indicator : %3s\n",
985 ATTN_LED(ctrl) ? "yes" : "no");
986 ctrl_info(ctrl, " Power Indicator : %3s\n",
987 PWR_LED(ctrl) ? "yes" : "no");
988 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
989 HP_SUPR_RM(ctrl) ? "yes" : "no");
990 ctrl_info(ctrl, " EMI Present : %3s\n",
991 EMI(ctrl) ? "yes" : "no");
992 ctrl_info(ctrl, " Command Completed : %3s\n",
993 NO_CMD_CMPL(ctrl) ? "no" : "yes");
994 pciehp_readw(ctrl, PCI_EXP_SLTSTA, &reg16);
995 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
996 pciehp_readw(ctrl, PCI_EXP_SLTCTL, &reg16);
997 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
998 }
999
1000 struct controller *pcie_init(struct pcie_device *dev)
1001 {
1002 struct controller *ctrl;
1003 u32 slot_cap, link_cap;
1004 struct pci_dev *pdev = dev->port;
1005
1006 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
1007 if (!ctrl) {
1008 dev_err(&dev->device, "%s: Out of memory\n", __func__);
1009 goto abort;
1010 }
1011 INIT_LIST_HEAD(&ctrl->slot_list);
1012
1013 ctrl->pcie = dev;
1014 ctrl->pci_dev = pdev;
1015 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1016 if (!ctrl->cap_base) {
1017 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
1018 goto abort_ctrl;
1019 }
1020 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
1021 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
1022 goto abort_ctrl;
1023 }
1024
1025 ctrl->slot_cap = slot_cap;
1026 ctrl->first_slot = slot_cap >> 19;
1027 ctrl->slot_device_offset = 0;
1028 ctrl->num_slots = 1;
1029 ctrl->hpc_ops = &pciehp_hpc_ops;
1030 mutex_init(&ctrl->crit_sect);
1031 mutex_init(&ctrl->ctrl_lock);
1032 init_waitqueue_head(&ctrl->queue);
1033 dbg_ctrl(ctrl);
1034 /*
1035 * Controller doesn't notify of command completion if the "No
1036 * Command Completed Support" bit is set in Slot Capability
1037 * register or the controller supports none of power
1038 * controller, attention led, power led and EMI.
1039 */
1040 if (NO_CMD_CMPL(ctrl) ||
1041 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1042 ctrl->no_cmd_complete = 1;
1043
1044 /* Check if Data Link Layer Link Active Reporting is implemented */
1045 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
1046 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
1047 goto abort_ctrl;
1048 }
1049 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
1050 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
1051 ctrl->link_active_reporting = 1;
1052 }
1053
1054 /* Clear all remaining event bits in Slot Status register */
1055 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
1056 goto abort_ctrl;
1057
1058 /* Disable sotfware notification */
1059 pcie_disable_notification(ctrl);
1060
1061 /*
1062 * If this is the first controller to be initialized,
1063 * initialize the pciehp work queue
1064 */
1065 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1066 pciehp_wq = create_singlethread_workqueue("pciehpd");
1067 if (!pciehp_wq)
1068 goto abort_ctrl;
1069 }
1070
1071 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1072 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1073 pdev->subsystem_device);
1074
1075 if (pcie_init_slot(ctrl))
1076 goto abort_ctrl;
1077
1078 return ctrl;
1079
1080 abort_ctrl:
1081 kfree(ctrl);
1082 abort:
1083 return NULL;
1084 }
1085
1086 void pcie_release_ctrl(struct controller *ctrl)
1087 {
1088 pcie_shutdown_notification(ctrl);
1089 pcie_cleanup_slot(ctrl);
1090 /*
1091 * If this is the last controller to be released, destroy the
1092 * pciehp work queue
1093 */
1094 if (atomic_dec_and_test(&pciehp_num_controllers))
1095 destroy_workqueue(pciehp_wq);
1096 kfree(ctrl);
1097 }
kernel source for telekom puls (alcatel/mediatek)