2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 * Intel PCIe NTB Linux driver
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
62 MODULE_DESCRIPTION(NTB_NAME
);
63 MODULE_VERSION(NTB_VER
);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
67 static bool xeon_errata_workaround
= true;
68 module_param(xeon_errata_workaround
, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround
, "Workaround for the Xeon Errata");
72 NTB_CONN_TRANSPARENT
= 0,
87 static struct dentry
*debugfs_dir
;
89 #define BWD_LINK_RECOVERY_TIME 500
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl
) = {
95 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD
)},
96 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF
)},
97 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB
)},
98 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT
)},
99 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX
)},
100 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_PS_JSF
)},
101 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_PS_SNB
)},
102 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_PS_IVT
)},
103 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_PS_HSX
)},
104 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_SS_JSF
)},
105 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_SS_SNB
)},
106 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_SS_IVT
)},
107 {PCI_VDEVICE(INTEL
, PCI_DEVICE_ID_INTEL_NTB_SS_HSX
)},
110 MODULE_DEVICE_TABLE(pci
, ntb_pci_tbl
);
113 * ntb_register_event_callback() - register event callback
114 * @ndev: pointer to ntb_device instance
115 * @func: callback function to register
117 * This function registers a callback for any HW driver events such as link
118 * up/down, power management notices and etc.
120 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
122 int ntb_register_event_callback(struct ntb_device
*ndev
,
123 void (*func
)(void *handle
, enum ntb_hw_event event
))
128 ndev
->event_cb
= func
;
134 * ntb_unregister_event_callback() - unregisters the event callback
135 * @ndev: pointer to ntb_device instance
137 * This function unregisters the existing callback from transport
139 void ntb_unregister_event_callback(struct ntb_device
*ndev
)
141 ndev
->event_cb
= NULL
;
145 * ntb_register_db_callback() - register a callback for doorbell interrupt
146 * @ndev: pointer to ntb_device instance
147 * @idx: doorbell index to register callback, zero based
148 * @data: pointer to be returned to caller with every callback
149 * @func: callback function to register
151 * This function registers a callback function for the doorbell interrupt
152 * on the primary side. The function will unmask the doorbell as well to
155 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
157 int ntb_register_db_callback(struct ntb_device
*ndev
, unsigned int idx
,
158 void *data
, void (*func
)(void *data
, int db_num
))
162 if (idx
>= ndev
->max_cbs
|| ndev
->db_cb
[idx
].callback
) {
163 dev_warn(&ndev
->pdev
->dev
, "Invalid Index.\n");
167 ndev
->db_cb
[idx
].callback
= func
;
168 ndev
->db_cb
[idx
].data
= data
;
170 /* unmask interrupt */
171 mask
= readw(ndev
->reg_ofs
.ldb_mask
);
172 clear_bit(idx
* ndev
->bits_per_vector
, &mask
);
173 writew(mask
, ndev
->reg_ofs
.ldb_mask
);
179 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
180 * @ndev: pointer to ntb_device instance
181 * @idx: doorbell index to register callback, zero based
183 * This function unregisters a callback function for the doorbell interrupt
184 * on the primary side. The function will also mask the said doorbell.
186 void ntb_unregister_db_callback(struct ntb_device
*ndev
, unsigned int idx
)
190 if (idx
>= ndev
->max_cbs
|| !ndev
->db_cb
[idx
].callback
)
193 mask
= readw(ndev
->reg_ofs
.ldb_mask
);
194 set_bit(idx
* ndev
->bits_per_vector
, &mask
);
195 writew(mask
, ndev
->reg_ofs
.ldb_mask
);
197 ndev
->db_cb
[idx
].callback
= NULL
;
201 * ntb_find_transport() - find the transport pointer
202 * @transport: pointer to pci device
204 * Given the pci device pointer, return the transport pointer passed in when
205 * the transport attached when it was inited.
207 * RETURNS: pointer to transport.
209 void *ntb_find_transport(struct pci_dev
*pdev
)
211 struct ntb_device
*ndev
= pci_get_drvdata(pdev
);
212 return ndev
->ntb_transport
;
216 * ntb_register_transport() - Register NTB transport with NTB HW driver
217 * @transport: transport identifier
219 * This function allows a transport to reserve the hardware driver for
222 * RETURNS: pointer to ntb_device, NULL on error.
224 struct ntb_device
*ntb_register_transport(struct pci_dev
*pdev
, void *transport
)
226 struct ntb_device
*ndev
= pci_get_drvdata(pdev
);
228 if (ndev
->ntb_transport
)
231 ndev
->ntb_transport
= transport
;
236 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
237 * @ndev - ntb_device of the transport to be freed
239 * This function unregisters the transport from the HW driver and performs any
240 * necessary cleanups.
242 void ntb_unregister_transport(struct ntb_device
*ndev
)
246 if (!ndev
->ntb_transport
)
249 for (i
= 0; i
< ndev
->max_cbs
; i
++)
250 ntb_unregister_db_callback(ndev
, i
);
252 ntb_unregister_event_callback(ndev
);
253 ndev
->ntb_transport
= NULL
;
257 * ntb_write_local_spad() - write to the secondary scratchpad register
258 * @ndev: pointer to ntb_device instance
259 * @idx: index to the scratchpad register, 0 based
260 * @val: the data value to put into the register
262 * This function allows writing of a 32bit value to the indexed scratchpad
263 * register. This writes over the data mirrored to the local scratchpad register
264 * by the remote system.
266 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
268 int ntb_write_local_spad(struct ntb_device
*ndev
, unsigned int idx
, u32 val
)
270 if (idx
>= ndev
->limits
.max_spads
)
273 dev_dbg(&ndev
->pdev
->dev
, "Writing %x to local scratch pad index %d\n",
275 writel(val
, ndev
->reg_ofs
.spad_read
+ idx
* 4);
281 * ntb_read_local_spad() - read from the primary scratchpad register
282 * @ndev: pointer to ntb_device instance
283 * @idx: index to scratchpad register, 0 based
284 * @val: pointer to 32bit integer for storing the register value
286 * This function allows reading of the 32bit scratchpad register on
287 * the primary (internal) side. This allows the local system to read data
288 * written and mirrored to the scratchpad register by the remote system.
290 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
292 int ntb_read_local_spad(struct ntb_device
*ndev
, unsigned int idx
, u32
*val
)
294 if (idx
>= ndev
->limits
.max_spads
)
297 *val
= readl(ndev
->reg_ofs
.spad_write
+ idx
* 4);
298 dev_dbg(&ndev
->pdev
->dev
,
299 "Reading %x from local scratch pad index %d\n", *val
, idx
);
305 * ntb_write_remote_spad() - write to the secondary scratchpad register
306 * @ndev: pointer to ntb_device instance
307 * @idx: index to the scratchpad register, 0 based
308 * @val: the data value to put into the register
310 * This function allows writing of a 32bit value to the indexed scratchpad
311 * register. The register resides on the secondary (external) side. This allows
312 * the local system to write data to be mirrored to the remote systems
313 * scratchpad register.
315 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
317 int ntb_write_remote_spad(struct ntb_device
*ndev
, unsigned int idx
, u32 val
)
319 if (idx
>= ndev
->limits
.max_spads
)
322 dev_dbg(&ndev
->pdev
->dev
, "Writing %x to remote scratch pad index %d\n",
324 writel(val
, ndev
->reg_ofs
.spad_write
+ idx
* 4);
330 * ntb_read_remote_spad() - read from the primary scratchpad register
331 * @ndev: pointer to ntb_device instance
332 * @idx: index to scratchpad register, 0 based
333 * @val: pointer to 32bit integer for storing the register value
335 * This function allows reading of the 32bit scratchpad register on
336 * the primary (internal) side. This alloows the local system to read the data
337 * it wrote to be mirrored on the remote system.
339 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
341 int ntb_read_remote_spad(struct ntb_device
*ndev
, unsigned int idx
, u32
*val
)
343 if (idx
>= ndev
->limits
.max_spads
)
346 *val
= readl(ndev
->reg_ofs
.spad_read
+ idx
* 4);
347 dev_dbg(&ndev
->pdev
->dev
,
348 "Reading %x from remote scratch pad index %d\n", *val
, idx
);
354 * ntb_get_mw_base() - get addr for the NTB memory window
355 * @ndev: pointer to ntb_device instance
356 * @mw: memory window number
358 * This function provides the base address of the memory window specified.
360 * RETURNS: address, or NULL on error.
362 resource_size_t
ntb_get_mw_base(struct ntb_device
*ndev
, unsigned int mw
)
364 if (mw
>= ntb_max_mw(ndev
))
367 return pci_resource_start(ndev
->pdev
, MW_TO_BAR(mw
));
371 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
372 * @ndev: pointer to ntb_device instance
373 * @mw: memory window number
375 * This function provides the base virtual address of the memory window
378 * RETURNS: pointer to virtual address, or NULL on error.
380 void __iomem
*ntb_get_mw_vbase(struct ntb_device
*ndev
, unsigned int mw
)
382 if (mw
>= ntb_max_mw(ndev
))
385 return ndev
->mw
[mw
].vbase
;
389 * ntb_get_mw_size() - return size of NTB memory window
390 * @ndev: pointer to ntb_device instance
391 * @mw: memory window number
393 * This function provides the physical size of the memory window specified
395 * RETURNS: the size of the memory window or zero on error
397 u64
ntb_get_mw_size(struct ntb_device
*ndev
, unsigned int mw
)
399 if (mw
>= ntb_max_mw(ndev
))
402 return ndev
->mw
[mw
].bar_sz
;
406 * ntb_set_mw_addr - set the memory window address
407 * @ndev: pointer to ntb_device instance
408 * @mw: memory window number
409 * @addr: base address for data
411 * This function sets the base physical address of the memory window. This
412 * memory address is where data from the remote system will be transfered into
413 * or out of depending on how the transport is configured.
415 void ntb_set_mw_addr(struct ntb_device
*ndev
, unsigned int mw
, u64 addr
)
417 if (mw
>= ntb_max_mw(ndev
))
420 dev_dbg(&ndev
->pdev
->dev
, "Writing addr %Lx to BAR %d\n", addr
,
423 ndev
->mw
[mw
].phys_addr
= addr
;
425 switch (MW_TO_BAR(mw
)) {
427 writeq(addr
, ndev
->reg_ofs
.bar2_xlat
);
430 writeq(addr
, ndev
->reg_ofs
.bar4_xlat
);
436 * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
437 * @ndev: pointer to ntb_device instance
438 * @db: doorbell to ring
440 * This function allows triggering of a doorbell on the secondary/external
441 * side that will initiate an interrupt on the remote host
443 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
445 void ntb_ring_doorbell(struct ntb_device
*ndev
, unsigned int db
)
447 dev_dbg(&ndev
->pdev
->dev
, "%s: ringing doorbell %d\n", __func__
, db
);
449 if (ndev
->hw_type
== BWD_HW
)
450 writeq((u64
) 1 << db
, ndev
->reg_ofs
.rdb
);
452 writew(((1 << ndev
->bits_per_vector
) - 1) <<
453 (db
* ndev
->bits_per_vector
), ndev
->reg_ofs
.rdb
);
456 static void bwd_recover_link(struct ntb_device
*ndev
)
460 /* Driver resets the NTB ModPhy lanes - magic! */
461 writeb(0xe0, ndev
->reg_base
+ BWD_MODPHY_PCSREG6
);
462 writeb(0x40, ndev
->reg_base
+ BWD_MODPHY_PCSREG4
);
463 writeb(0x60, ndev
->reg_base
+ BWD_MODPHY_PCSREG4
);
464 writeb(0x60, ndev
->reg_base
+ BWD_MODPHY_PCSREG6
);
466 /* Driver waits 100ms to allow the NTB ModPhy to settle */
469 /* Clear AER Errors, write to clear */
470 status
= readl(ndev
->reg_base
+ BWD_ERRCORSTS_OFFSET
);
471 dev_dbg(&ndev
->pdev
->dev
, "ERRCORSTS = %x\n", status
);
472 status
&= PCI_ERR_COR_REP_ROLL
;
473 writel(status
, ndev
->reg_base
+ BWD_ERRCORSTS_OFFSET
);
475 /* Clear unexpected electrical idle event in LTSSM, write to clear */
476 status
= readl(ndev
->reg_base
+ BWD_LTSSMERRSTS0_OFFSET
);
477 dev_dbg(&ndev
->pdev
->dev
, "LTSSMERRSTS0 = %x\n", status
);
478 status
|= BWD_LTSSMERRSTS0_UNEXPECTEDEI
;
479 writel(status
, ndev
->reg_base
+ BWD_LTSSMERRSTS0_OFFSET
);
481 /* Clear DeSkew Buffer error, write to clear */
482 status
= readl(ndev
->reg_base
+ BWD_DESKEWSTS_OFFSET
);
483 dev_dbg(&ndev
->pdev
->dev
, "DESKEWSTS = %x\n", status
);
484 status
|= BWD_DESKEWSTS_DBERR
;
485 writel(status
, ndev
->reg_base
+ BWD_DESKEWSTS_OFFSET
);
487 status
= readl(ndev
->reg_base
+ BWD_IBSTERRRCRVSTS0_OFFSET
);
488 dev_dbg(&ndev
->pdev
->dev
, "IBSTERRRCRVSTS0 = %x\n", status
);
489 status
&= BWD_IBIST_ERR_OFLOW
;
490 writel(status
, ndev
->reg_base
+ BWD_IBSTERRRCRVSTS0_OFFSET
);
492 /* Releases the NTB state machine to allow the link to retrain */
493 status
= readl(ndev
->reg_base
+ BWD_LTSSMSTATEJMP_OFFSET
);
494 dev_dbg(&ndev
->pdev
->dev
, "LTSSMSTATEJMP = %x\n", status
);
495 status
&= ~BWD_LTSSMSTATEJMP_FORCEDETECT
;
496 writel(status
, ndev
->reg_base
+ BWD_LTSSMSTATEJMP_OFFSET
);
499 static void ntb_link_event(struct ntb_device
*ndev
, int link_state
)
503 if (ndev
->link_status
== link_state
)
506 if (link_state
== NTB_LINK_UP
) {
509 dev_info(&ndev
->pdev
->dev
, "Link Up\n");
510 ndev
->link_status
= NTB_LINK_UP
;
511 event
= NTB_EVENT_HW_LINK_UP
;
513 if (ndev
->hw_type
== BWD_HW
||
514 ndev
->conn_type
== NTB_CONN_TRANSPARENT
)
515 status
= readw(ndev
->reg_ofs
.lnk_stat
);
517 int rc
= pci_read_config_word(ndev
->pdev
,
518 SNB_LINK_STATUS_OFFSET
,
524 ndev
->link_width
= (status
& NTB_LINK_WIDTH_MASK
) >> 4;
525 ndev
->link_speed
= (status
& NTB_LINK_SPEED_MASK
);
526 dev_info(&ndev
->pdev
->dev
, "Link Width %d, Link Speed %d\n",
527 ndev
->link_width
, ndev
->link_speed
);
529 dev_info(&ndev
->pdev
->dev
, "Link Down\n");
530 ndev
->link_status
= NTB_LINK_DOWN
;
531 event
= NTB_EVENT_HW_LINK_DOWN
;
532 /* Don't modify link width/speed, we need it in link recovery */
535 /* notify the upper layer if we have an event change */
537 ndev
->event_cb(ndev
->ntb_transport
, event
);
540 static int ntb_link_status(struct ntb_device
*ndev
)
544 if (ndev
->hw_type
== BWD_HW
) {
547 ntb_cntl
= readl(ndev
->reg_ofs
.lnk_cntl
);
548 if (ntb_cntl
& BWD_CNTL_LINK_DOWN
)
549 link_state
= NTB_LINK_DOWN
;
551 link_state
= NTB_LINK_UP
;
556 rc
= pci_read_config_word(ndev
->pdev
, SNB_LINK_STATUS_OFFSET
,
561 if (status
& NTB_LINK_STATUS_ACTIVE
)
562 link_state
= NTB_LINK_UP
;
564 link_state
= NTB_LINK_DOWN
;
567 ntb_link_event(ndev
, link_state
);
572 static void bwd_link_recovery(struct work_struct
*work
)
574 struct ntb_device
*ndev
= container_of(work
, struct ntb_device
,
578 bwd_recover_link(ndev
);
579 /* There is a potential race between the 2 NTB devices recovering at the
580 * same time. If the times are the same, the link will not recover and
581 * the driver will be stuck in this loop forever. Add a random interval
582 * to the recovery time to prevent this race.
584 msleep(BWD_LINK_RECOVERY_TIME
+ prandom_u32() % BWD_LINK_RECOVERY_TIME
);
586 status32
= readl(ndev
->reg_base
+ BWD_LTSSMSTATEJMP_OFFSET
);
587 if (status32
& BWD_LTSSMSTATEJMP_FORCEDETECT
)
590 status32
= readl(ndev
->reg_base
+ BWD_IBSTERRRCRVSTS0_OFFSET
);
591 if (status32
& BWD_IBIST_ERR_OFLOW
)
594 status32
= readl(ndev
->reg_ofs
.lnk_cntl
);
595 if (!(status32
& BWD_CNTL_LINK_DOWN
)) {
596 unsigned char speed
, width
;
599 status16
= readw(ndev
->reg_ofs
.lnk_stat
);
600 width
= (status16
& NTB_LINK_WIDTH_MASK
) >> 4;
601 speed
= (status16
& NTB_LINK_SPEED_MASK
);
602 if (ndev
->link_width
!= width
|| ndev
->link_speed
!= speed
)
606 schedule_delayed_work(&ndev
->hb_timer
, NTB_HB_TIMEOUT
);
610 schedule_delayed_work(&ndev
->lr_timer
, NTB_HB_TIMEOUT
);
613 /* BWD doesn't have link status interrupt, poll on that platform */
614 static void bwd_link_poll(struct work_struct
*work
)
616 struct ntb_device
*ndev
= container_of(work
, struct ntb_device
,
618 unsigned long ts
= jiffies
;
620 /* If we haven't gotten an interrupt in a while, check the BWD link
623 if (ts
> ndev
->last_ts
+ NTB_HB_TIMEOUT
) {
624 int rc
= ntb_link_status(ndev
);
626 dev_err(&ndev
->pdev
->dev
,
627 "Error determining link status\n");
629 /* Check to see if a link error is the cause of the link down */
630 if (ndev
->link_status
== NTB_LINK_DOWN
) {
631 u32 status32
= readl(ndev
->reg_base
+
632 BWD_LTSSMSTATEJMP_OFFSET
);
633 if (status32
& BWD_LTSSMSTATEJMP_FORCEDETECT
) {
634 schedule_delayed_work(&ndev
->lr_timer
, 0);
640 schedule_delayed_work(&ndev
->hb_timer
, NTB_HB_TIMEOUT
);
643 static int ntb_xeon_setup(struct ntb_device
*ndev
)
648 ndev
->hw_type
= SNB_HW
;
650 rc
= pci_read_config_byte(ndev
->pdev
, NTB_PPD_OFFSET
, &val
);
654 if (val
& SNB_PPD_DEV_TYPE
)
655 ndev
->dev_type
= NTB_DEV_USD
;
657 ndev
->dev_type
= NTB_DEV_DSD
;
659 switch (val
& SNB_PPD_CONN_TYPE
) {
661 dev_info(&ndev
->pdev
->dev
, "Conn Type = B2B\n");
662 ndev
->conn_type
= NTB_CONN_B2B
;
663 ndev
->reg_ofs
.ldb
= ndev
->reg_base
+ SNB_PDOORBELL_OFFSET
;
664 ndev
->reg_ofs
.ldb_mask
= ndev
->reg_base
+ SNB_PDBMSK_OFFSET
;
665 ndev
->reg_ofs
.spad_read
= ndev
->reg_base
+ SNB_SPAD_OFFSET
;
666 ndev
->reg_ofs
.bar2_xlat
= ndev
->reg_base
+ SNB_SBAR2XLAT_OFFSET
;
667 ndev
->reg_ofs
.bar4_xlat
= ndev
->reg_base
+ SNB_SBAR4XLAT_OFFSET
;
668 ndev
->limits
.max_spads
= SNB_MAX_B2B_SPADS
;
670 /* There is a Xeon hardware errata related to writes to
671 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
672 * to NTB MMIO Space, which may hang the system. To workaround
673 * this use the second memory window to access the interrupt and
674 * scratch pad registers on the remote system.
676 if (xeon_errata_workaround
) {
677 if (!ndev
->mw
[1].bar_sz
)
680 ndev
->limits
.max_mw
= SNB_ERRATA_MAX_MW
;
681 ndev
->reg_ofs
.spad_write
= ndev
->mw
[1].vbase
+
683 ndev
->reg_ofs
.rdb
= ndev
->mw
[1].vbase
+
684 SNB_PDOORBELL_OFFSET
;
686 /* Set the Limit register to 4k, the minimum size, to
687 * prevent an illegal access
689 writeq(ndev
->mw
[1].bar_sz
+ 0x1000, ndev
->reg_base
+
690 SNB_PBAR4LMT_OFFSET
);
692 ndev
->limits
.max_mw
= SNB_MAX_MW
;
693 ndev
->reg_ofs
.spad_write
= ndev
->reg_base
+
695 ndev
->reg_ofs
.rdb
= ndev
->reg_base
+
696 SNB_B2B_DOORBELL_OFFSET
;
698 /* Disable the Limit register, just incase it is set to
701 writeq(0, ndev
->reg_base
+ SNB_PBAR4LMT_OFFSET
);
704 /* The Xeon errata workaround requires setting SBAR Base
705 * addresses to known values, so that the PBAR XLAT can be
706 * pointed at SBAR0 of the remote system.
708 if (ndev
->dev_type
== NTB_DEV_USD
) {
709 writeq(SNB_MBAR23_DSD_ADDR
, ndev
->reg_base
+
710 SNB_PBAR2XLAT_OFFSET
);
711 if (xeon_errata_workaround
)
712 writeq(SNB_MBAR01_DSD_ADDR
, ndev
->reg_base
+
713 SNB_PBAR4XLAT_OFFSET
);
715 writeq(SNB_MBAR45_DSD_ADDR
, ndev
->reg_base
+
716 SNB_PBAR4XLAT_OFFSET
);
717 /* B2B_XLAT_OFFSET is a 64bit register, but can
718 * only take 32bit writes
720 writel(SNB_MBAR01_DSD_ADDR
& 0xffffffff,
721 ndev
->reg_base
+ SNB_B2B_XLAT_OFFSETL
);
722 writel(SNB_MBAR01_DSD_ADDR
>> 32,
723 ndev
->reg_base
+ SNB_B2B_XLAT_OFFSETU
);
726 writeq(SNB_MBAR01_USD_ADDR
, ndev
->reg_base
+
727 SNB_SBAR0BASE_OFFSET
);
728 writeq(SNB_MBAR23_USD_ADDR
, ndev
->reg_base
+
729 SNB_SBAR2BASE_OFFSET
);
730 writeq(SNB_MBAR45_USD_ADDR
, ndev
->reg_base
+
731 SNB_SBAR4BASE_OFFSET
);
733 writeq(SNB_MBAR23_USD_ADDR
, ndev
->reg_base
+
734 SNB_PBAR2XLAT_OFFSET
);
735 if (xeon_errata_workaround
)
736 writeq(SNB_MBAR01_USD_ADDR
, ndev
->reg_base
+
737 SNB_PBAR4XLAT_OFFSET
);
739 writeq(SNB_MBAR45_USD_ADDR
, ndev
->reg_base
+
740 SNB_PBAR4XLAT_OFFSET
);
741 /* B2B_XLAT_OFFSET is a 64bit register, but can
742 * only take 32bit writes
744 writel(SNB_MBAR01_DSD_ADDR
& 0xffffffff,
745 ndev
->reg_base
+ SNB_B2B_XLAT_OFFSETL
);
746 writel(SNB_MBAR01_USD_ADDR
>> 32,
747 ndev
->reg_base
+ SNB_B2B_XLAT_OFFSETU
);
749 writeq(SNB_MBAR01_DSD_ADDR
, ndev
->reg_base
+
750 SNB_SBAR0BASE_OFFSET
);
751 writeq(SNB_MBAR23_DSD_ADDR
, ndev
->reg_base
+
752 SNB_SBAR2BASE_OFFSET
);
753 writeq(SNB_MBAR45_DSD_ADDR
, ndev
->reg_base
+
754 SNB_SBAR4BASE_OFFSET
);
758 dev_info(&ndev
->pdev
->dev
, "Conn Type = RP\n");
759 ndev
->conn_type
= NTB_CONN_RP
;
761 if (xeon_errata_workaround
) {
762 dev_err(&ndev
->pdev
->dev
,
763 "NTB-RP disabled due to hardware errata. To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
767 /* Scratch pads need to have exclusive access from the primary
768 * or secondary side. Halve the num spads so that each side can
769 * have an equal amount.
771 ndev
->limits
.max_spads
= SNB_MAX_COMPAT_SPADS
/ 2;
772 /* Note: The SDOORBELL is the cause of the errata. You REALLY
773 * don't want to touch it.
775 ndev
->reg_ofs
.rdb
= ndev
->reg_base
+ SNB_SDOORBELL_OFFSET
;
776 ndev
->reg_ofs
.ldb
= ndev
->reg_base
+ SNB_PDOORBELL_OFFSET
;
777 ndev
->reg_ofs
.ldb_mask
= ndev
->reg_base
+ SNB_PDBMSK_OFFSET
;
778 /* Offset the start of the spads to correspond to whether it is
779 * primary or secondary
781 ndev
->reg_ofs
.spad_write
= ndev
->reg_base
+ SNB_SPAD_OFFSET
+
782 ndev
->limits
.max_spads
* 4;
783 ndev
->reg_ofs
.spad_read
= ndev
->reg_base
+ SNB_SPAD_OFFSET
;
784 ndev
->reg_ofs
.bar2_xlat
= ndev
->reg_base
+ SNB_SBAR2XLAT_OFFSET
;
785 ndev
->reg_ofs
.bar4_xlat
= ndev
->reg_base
+ SNB_SBAR4XLAT_OFFSET
;
786 ndev
->limits
.max_mw
= SNB_MAX_MW
;
788 case NTB_CONN_TRANSPARENT
:
789 dev_info(&ndev
->pdev
->dev
, "Conn Type = TRANSPARENT\n");
790 ndev
->conn_type
= NTB_CONN_TRANSPARENT
;
791 /* Scratch pads need to have exclusive access from the primary
792 * or secondary side. Halve the num spads so that each side can
793 * have an equal amount.
795 ndev
->limits
.max_spads
= SNB_MAX_COMPAT_SPADS
/ 2;
796 ndev
->reg_ofs
.rdb
= ndev
->reg_base
+ SNB_PDOORBELL_OFFSET
;
797 ndev
->reg_ofs
.ldb
= ndev
->reg_base
+ SNB_SDOORBELL_OFFSET
;
798 ndev
->reg_ofs
.ldb_mask
= ndev
->reg_base
+ SNB_SDBMSK_OFFSET
;
799 ndev
->reg_ofs
.spad_write
= ndev
->reg_base
+ SNB_SPAD_OFFSET
;
800 /* Offset the start of the spads to correspond to whether it is
801 * primary or secondary
803 ndev
->reg_ofs
.spad_read
= ndev
->reg_base
+ SNB_SPAD_OFFSET
+
804 ndev
->limits
.max_spads
* 4;
805 ndev
->reg_ofs
.bar2_xlat
= ndev
->reg_base
+ SNB_PBAR2XLAT_OFFSET
;
806 ndev
->reg_ofs
.bar4_xlat
= ndev
->reg_base
+ SNB_PBAR4XLAT_OFFSET
;
808 ndev
->limits
.max_mw
= SNB_MAX_MW
;
811 /* Most likely caused by the remote NTB-RP device not being
814 dev_err(&ndev
->pdev
->dev
, "Unknown PPD %x\n", val
);
818 ndev
->reg_ofs
.lnk_cntl
= ndev
->reg_base
+ SNB_NTBCNTL_OFFSET
;
819 ndev
->reg_ofs
.lnk_stat
= ndev
->reg_base
+ SNB_SLINK_STATUS_OFFSET
;
820 ndev
->reg_ofs
.spci_cmd
= ndev
->reg_base
+ SNB_PCICMD_OFFSET
;
822 ndev
->limits
.max_db_bits
= SNB_MAX_DB_BITS
;
823 ndev
->limits
.msix_cnt
= SNB_MSIX_CNT
;
824 ndev
->bits_per_vector
= SNB_DB_BITS_PER_VEC
;
829 static int ntb_bwd_setup(struct ntb_device
*ndev
)
834 ndev
->hw_type
= BWD_HW
;
836 rc
= pci_read_config_dword(ndev
->pdev
, NTB_PPD_OFFSET
, &val
);
840 switch ((val
& BWD_PPD_CONN_TYPE
) >> 8) {
842 ndev
->conn_type
= NTB_CONN_B2B
;
846 dev_err(&ndev
->pdev
->dev
, "Unsupported NTB configuration\n");
850 if (val
& BWD_PPD_DEV_TYPE
)
851 ndev
->dev_type
= NTB_DEV_DSD
;
853 ndev
->dev_type
= NTB_DEV_USD
;
855 /* Initiate PCI-E link training */
856 rc
= pci_write_config_dword(ndev
->pdev
, NTB_PPD_OFFSET
,
857 val
| BWD_PPD_INIT_LINK
);
861 ndev
->reg_ofs
.ldb
= ndev
->reg_base
+ BWD_PDOORBELL_OFFSET
;
862 ndev
->reg_ofs
.ldb_mask
= ndev
->reg_base
+ BWD_PDBMSK_OFFSET
;
863 ndev
->reg_ofs
.rdb
= ndev
->reg_base
+ BWD_B2B_DOORBELL_OFFSET
;
864 ndev
->reg_ofs
.bar2_xlat
= ndev
->reg_base
+ BWD_SBAR2XLAT_OFFSET
;
865 ndev
->reg_ofs
.bar4_xlat
= ndev
->reg_base
+ BWD_SBAR4XLAT_OFFSET
;
866 ndev
->reg_ofs
.lnk_cntl
= ndev
->reg_base
+ BWD_NTBCNTL_OFFSET
;
867 ndev
->reg_ofs
.lnk_stat
= ndev
->reg_base
+ BWD_LINK_STATUS_OFFSET
;
868 ndev
->reg_ofs
.spad_read
= ndev
->reg_base
+ BWD_SPAD_OFFSET
;
869 ndev
->reg_ofs
.spad_write
= ndev
->reg_base
+ BWD_B2B_SPAD_OFFSET
;
870 ndev
->reg_ofs
.spci_cmd
= ndev
->reg_base
+ BWD_PCICMD_OFFSET
;
871 ndev
->limits
.max_mw
= BWD_MAX_MW
;
872 ndev
->limits
.max_spads
= BWD_MAX_SPADS
;
873 ndev
->limits
.max_db_bits
= BWD_MAX_DB_BITS
;
874 ndev
->limits
.msix_cnt
= BWD_MSIX_CNT
;
875 ndev
->bits_per_vector
= BWD_DB_BITS_PER_VEC
;
877 /* Since bwd doesn't have a link interrupt, setup a poll timer */
878 INIT_DELAYED_WORK(&ndev
->hb_timer
, bwd_link_poll
);
879 INIT_DELAYED_WORK(&ndev
->lr_timer
, bwd_link_recovery
);
880 schedule_delayed_work(&ndev
->hb_timer
, NTB_HB_TIMEOUT
);
885 static int ntb_device_setup(struct ntb_device
*ndev
)
889 switch (ndev
->pdev
->device
) {
890 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF
:
891 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB
:
892 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT
:
893 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX
:
894 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF
:
895 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB
:
896 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT
:
897 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX
:
898 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF
:
899 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB
:
900 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT
:
901 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX
:
902 rc
= ntb_xeon_setup(ndev
);
904 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD
:
905 rc
= ntb_bwd_setup(ndev
);
914 dev_info(&ndev
->pdev
->dev
, "Device Type = %s\n",
915 ndev
->dev_type
== NTB_DEV_USD
? "USD/DSP" : "DSD/USP");
917 if (ndev
->conn_type
== NTB_CONN_B2B
)
918 /* Enable Bus Master and Memory Space on the secondary side */
919 writew(PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
,
920 ndev
->reg_ofs
.spci_cmd
);
925 static void ntb_device_free(struct ntb_device
*ndev
)
927 if (ndev
->hw_type
== BWD_HW
) {
928 cancel_delayed_work_sync(&ndev
->hb_timer
);
929 cancel_delayed_work_sync(&ndev
->lr_timer
);
933 static irqreturn_t
bwd_callback_msix_irq(int irq
, void *data
)
935 struct ntb_db_cb
*db_cb
= data
;
936 struct ntb_device
*ndev
= db_cb
->ndev
;
938 dev_dbg(&ndev
->pdev
->dev
, "MSI-X irq %d received for DB %d\n", irq
,
942 db_cb
->callback(db_cb
->data
, db_cb
->db_num
);
944 /* No need to check for the specific HB irq, any interrupt means
947 ndev
->last_ts
= jiffies
;
949 writeq((u64
) 1 << db_cb
->db_num
, ndev
->reg_ofs
.ldb
);
954 static irqreturn_t
xeon_callback_msix_irq(int irq
, void *data
)
956 struct ntb_db_cb
*db_cb
= data
;
957 struct ntb_device
*ndev
= db_cb
->ndev
;
959 dev_dbg(&ndev
->pdev
->dev
, "MSI-X irq %d received for DB %d\n", irq
,
963 db_cb
->callback(db_cb
->data
, db_cb
->db_num
);
965 /* On Sandybridge, there are 16 bits in the interrupt register
966 * but only 4 vectors. So, 5 bits are assigned to the first 3
967 * vectors, with the 4th having a single bit for link
970 writew(((1 << ndev
->bits_per_vector
) - 1) <<
971 (db_cb
->db_num
* ndev
->bits_per_vector
), ndev
->reg_ofs
.ldb
);
976 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
977 static irqreturn_t
xeon_event_msix_irq(int irq
, void *dev
)
979 struct ntb_device
*ndev
= dev
;
982 dev_dbg(&ndev
->pdev
->dev
, "MSI-X irq %d received for Events\n", irq
);
984 rc
= ntb_link_status(ndev
);
986 dev_err(&ndev
->pdev
->dev
, "Error determining link status\n");
988 /* bit 15 is always the link bit */
989 writew(1 << ndev
->limits
.max_db_bits
, ndev
->reg_ofs
.ldb
);
994 static irqreturn_t
ntb_interrupt(int irq
, void *dev
)
996 struct ntb_device
*ndev
= dev
;
999 if (ndev
->hw_type
== BWD_HW
) {
1000 u64 ldb
= readq(ndev
->reg_ofs
.ldb
);
1002 dev_dbg(&ndev
->pdev
->dev
, "irq %d - ldb = %Lx\n", irq
, ldb
);
1007 bwd_callback_msix_irq(irq
, &ndev
->db_cb
[i
]);
1010 u16 ldb
= readw(ndev
->reg_ofs
.ldb
);
1012 dev_dbg(&ndev
->pdev
->dev
, "irq %d - ldb = %x\n", irq
, ldb
);
1014 if (ldb
& SNB_DB_HW_LINK
) {
1015 xeon_event_msix_irq(irq
, dev
);
1016 ldb
&= ~SNB_DB_HW_LINK
;
1022 xeon_callback_msix_irq(irq
, &ndev
->db_cb
[i
]);
1029 static int ntb_setup_msix(struct ntb_device
*ndev
)
1031 struct pci_dev
*pdev
= ndev
->pdev
;
1032 struct msix_entry
*msix
;
1037 if (!pdev
->msix_cap
) {
1042 rc
= pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &val
);
1046 msix_entries
= msix_table_size(val
);
1047 if (msix_entries
> ndev
->limits
.msix_cnt
) {
1052 ndev
->msix_entries
= kmalloc(sizeof(struct msix_entry
) * msix_entries
,
1054 if (!ndev
->msix_entries
) {
1059 for (i
= 0; i
< msix_entries
; i
++)
1060 ndev
->msix_entries
[i
].entry
= i
;
1062 rc
= pci_enable_msix(pdev
, ndev
->msix_entries
, msix_entries
);
1066 /* On SNB, the link interrupt is always tied to 4th vector. If
1067 * we can't get all 4, then we can't use MSI-X.
1069 if (ndev
->hw_type
!= BWD_HW
) {
1074 dev_warn(&pdev
->dev
,
1075 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1080 for (i
= 0; i
< msix_entries
; i
++) {
1081 msix
= &ndev
->msix_entries
[i
];
1082 WARN_ON(!msix
->vector
);
1084 /* Use the last MSI-X vector for Link status */
1085 if (ndev
->hw_type
== BWD_HW
) {
1086 rc
= request_irq(msix
->vector
, bwd_callback_msix_irq
, 0,
1087 "ntb-callback-msix", &ndev
->db_cb
[i
]);
1091 if (i
== msix_entries
- 1) {
1092 rc
= request_irq(msix
->vector
,
1093 xeon_event_msix_irq
, 0,
1094 "ntb-event-msix", ndev
);
1098 rc
= request_irq(msix
->vector
,
1099 xeon_callback_msix_irq
, 0,
1100 "ntb-callback-msix",
1108 ndev
->num_msix
= msix_entries
;
1109 if (ndev
->hw_type
== BWD_HW
)
1110 ndev
->max_cbs
= msix_entries
;
1112 ndev
->max_cbs
= msix_entries
- 1;
1118 msix
= &ndev
->msix_entries
[i
];
1119 if (ndev
->hw_type
!= BWD_HW
&& i
== ndev
->num_msix
- 1)
1120 free_irq(msix
->vector
, ndev
);
1122 free_irq(msix
->vector
, &ndev
->db_cb
[i
]);
1124 pci_disable_msix(pdev
);
1126 kfree(ndev
->msix_entries
);
1127 dev_err(&pdev
->dev
, "Error allocating MSI-X interrupt\n");
1133 static int ntb_setup_msi(struct ntb_device
*ndev
)
1135 struct pci_dev
*pdev
= ndev
->pdev
;
1138 rc
= pci_enable_msi(pdev
);
1142 rc
= request_irq(pdev
->irq
, ntb_interrupt
, 0, "ntb-msi", ndev
);
1144 pci_disable_msi(pdev
);
1145 dev_err(&pdev
->dev
, "Error allocating MSI interrupt\n");
1152 static int ntb_setup_intx(struct ntb_device
*ndev
)
1154 struct pci_dev
*pdev
= ndev
->pdev
;
1159 /* Verify intx is enabled */
1162 rc
= request_irq(pdev
->irq
, ntb_interrupt
, IRQF_SHARED
, "ntb-intx",
1170 static int ntb_setup_interrupts(struct ntb_device
*ndev
)
1174 /* On BWD, disable all interrupts. On SNB, disable all but Link
1175 * Interrupt. The rest will be unmasked as callbacks are registered.
1177 if (ndev
->hw_type
== BWD_HW
)
1178 writeq(~0, ndev
->reg_ofs
.ldb_mask
);
1180 writew(~(1 << ndev
->limits
.max_db_bits
),
1181 ndev
->reg_ofs
.ldb_mask
);
1183 rc
= ntb_setup_msix(ndev
);
1187 ndev
->bits_per_vector
= 1;
1188 ndev
->max_cbs
= ndev
->limits
.max_db_bits
;
1190 rc
= ntb_setup_msi(ndev
);
1194 rc
= ntb_setup_intx(ndev
);
1196 dev_err(&ndev
->pdev
->dev
, "no usable interrupts\n");
1204 static void ntb_free_interrupts(struct ntb_device
*ndev
)
1206 struct pci_dev
*pdev
= ndev
->pdev
;
1208 /* mask interrupts */
1209 if (ndev
->hw_type
== BWD_HW
)
1210 writeq(~0, ndev
->reg_ofs
.ldb_mask
);
1212 writew(~0, ndev
->reg_ofs
.ldb_mask
);
1214 if (ndev
->num_msix
) {
1215 struct msix_entry
*msix
;
1218 for (i
= 0; i
< ndev
->num_msix
; i
++) {
1219 msix
= &ndev
->msix_entries
[i
];
1220 if (ndev
->hw_type
!= BWD_HW
&& i
== ndev
->num_msix
- 1)
1221 free_irq(msix
->vector
, ndev
);
1223 free_irq(msix
->vector
, &ndev
->db_cb
[i
]);
1225 pci_disable_msix(pdev
);
1227 free_irq(pdev
->irq
, ndev
);
1229 if (pci_dev_msi_enabled(pdev
))
1230 pci_disable_msi(pdev
);
1234 static int ntb_create_callbacks(struct ntb_device
*ndev
)
1238 /* Chicken-egg issue. We won't know how many callbacks are necessary
1239 * until we see how many MSI-X vectors we get, but these pointers need
1240 * to be passed into the MSI-X register function. So, we allocate the
1241 * max, knowing that they might not all be used, to work around this.
1243 ndev
->db_cb
= kcalloc(ndev
->limits
.max_db_bits
,
1244 sizeof(struct ntb_db_cb
),
1249 for (i
= 0; i
< ndev
->limits
.max_db_bits
; i
++) {
1250 ndev
->db_cb
[i
].db_num
= i
;
1251 ndev
->db_cb
[i
].ndev
= ndev
;
1257 static void ntb_free_callbacks(struct ntb_device
*ndev
)
1261 for (i
= 0; i
< ndev
->limits
.max_db_bits
; i
++)
1262 ntb_unregister_db_callback(ndev
, i
);
1267 static void ntb_setup_debugfs(struct ntb_device
*ndev
)
1269 if (!debugfs_initialized())
1273 debugfs_dir
= debugfs_create_dir(KBUILD_MODNAME
, NULL
);
1275 ndev
->debugfs_dir
= debugfs_create_dir(pci_name(ndev
->pdev
),
1279 static void ntb_free_debugfs(struct ntb_device
*ndev
)
1281 debugfs_remove_recursive(ndev
->debugfs_dir
);
1283 if (debugfs_dir
&& simple_empty(debugfs_dir
)) {
1284 debugfs_remove_recursive(debugfs_dir
);
1289 static int ntb_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1291 struct ntb_device
*ndev
;
1294 ndev
= kzalloc(sizeof(struct ntb_device
), GFP_KERNEL
);
1299 ndev
->link_status
= NTB_LINK_DOWN
;
1300 pci_set_drvdata(pdev
, ndev
);
1301 ntb_setup_debugfs(ndev
);
1303 rc
= pci_enable_device(pdev
);
1307 pci_set_master(ndev
->pdev
);
1309 rc
= pci_request_selected_regions(pdev
, NTB_BAR_MASK
, KBUILD_MODNAME
);
1313 ndev
->reg_base
= pci_ioremap_bar(pdev
, NTB_BAR_MMIO
);
1314 if (!ndev
->reg_base
) {
1315 dev_warn(&pdev
->dev
, "Cannot remap BAR 0\n");
1320 for (i
= 0; i
< NTB_MAX_NUM_MW
; i
++) {
1321 ndev
->mw
[i
].bar_sz
= pci_resource_len(pdev
, MW_TO_BAR(i
));
1323 ioremap_wc(pci_resource_start(pdev
, MW_TO_BAR(i
)),
1324 ndev
->mw
[i
].bar_sz
);
1325 dev_info(&pdev
->dev
, "MW %d size %llu\n", i
,
1326 (unsigned long long) ndev
->mw
[i
].bar_sz
);
1327 if (!ndev
->mw
[i
].vbase
) {
1328 dev_warn(&pdev
->dev
, "Cannot remap BAR %d\n",
1335 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
1337 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
1341 dev_warn(&pdev
->dev
, "Cannot DMA highmem\n");
1344 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
1346 rc
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
1350 dev_warn(&pdev
->dev
, "Cannot DMA consistent highmem\n");
1353 rc
= ntb_device_setup(ndev
);
1357 rc
= ntb_create_callbacks(ndev
);
1361 rc
= ntb_setup_interrupts(ndev
);
1365 /* The scratchpad registers keep the values between rmmod/insmod,
1368 for (i
= 0; i
< ndev
->limits
.max_spads
; i
++) {
1369 ntb_write_local_spad(ndev
, i
, 0);
1370 ntb_write_remote_spad(ndev
, i
, 0);
1373 rc
= ntb_transport_init(pdev
);
1377 /* Let's bring the NTB link up */
1378 writel(NTB_CNTL_BAR23_SNOOP
| NTB_CNTL_BAR45_SNOOP
,
1379 ndev
->reg_ofs
.lnk_cntl
);
1384 ntb_free_interrupts(ndev
);
1386 ntb_free_callbacks(ndev
);
1388 ntb_device_free(ndev
);
1390 for (i
--; i
>= 0; i
--)
1391 iounmap(ndev
->mw
[i
].vbase
);
1392 iounmap(ndev
->reg_base
);
1394 pci_release_selected_regions(pdev
, NTB_BAR_MASK
);
1396 pci_disable_device(pdev
);
1398 ntb_free_debugfs(ndev
);
1401 dev_err(&pdev
->dev
, "Error loading %s module\n", KBUILD_MODNAME
);
1405 static void ntb_pci_remove(struct pci_dev
*pdev
)
1407 struct ntb_device
*ndev
= pci_get_drvdata(pdev
);
1411 /* Bring NTB link down */
1412 ntb_cntl
= readl(ndev
->reg_ofs
.lnk_cntl
);
1413 ntb_cntl
|= NTB_CNTL_LINK_DISABLE
;
1414 writel(ntb_cntl
, ndev
->reg_ofs
.lnk_cntl
);
1416 ntb_transport_free(ndev
->ntb_transport
);
1418 ntb_free_interrupts(ndev
);
1419 ntb_free_callbacks(ndev
);
1420 ntb_device_free(ndev
);
1422 for (i
= 0; i
< NTB_MAX_NUM_MW
; i
++)
1423 iounmap(ndev
->mw
[i
].vbase
);
1425 iounmap(ndev
->reg_base
);
1426 pci_release_selected_regions(pdev
, NTB_BAR_MASK
);
1427 pci_disable_device(pdev
);
1428 ntb_free_debugfs(ndev
);
1432 static struct pci_driver ntb_pci_driver
= {
1433 .name
= KBUILD_MODNAME
,
1434 .id_table
= ntb_pci_tbl
,
1435 .probe
= ntb_pci_probe
,
1436 .remove
= ntb_pci_remove
,
1438 module_pci_driver(ntb_pci_driver
);