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[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / ntb / ntb_hw.c
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * BSD LICENSE
14 *
15 * Copyright(c) 2012 Intel Corporation. All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 *
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copy
24 * notice, this list of conditions and the following disclaimer in
25 * the documentation and/or other materials provided with the
26 * distribution.
27 * * Neither the name of Intel Corporation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * Intel PCIe NTB Linux driver
44 *
45 * Contact Information:
46 * Jon Mason <jon.mason@intel.com>
47 */
48 #include <linux/debugfs.h>
49 #include <linux/delay.h>
50 #include <linux/init.h>
51 #include <linux/interrupt.h>
52 #include <linux/module.h>
53 #include <linux/pci.h>
54 #include <linux/random.h>
55 #include <linux/slab.h>
56 #include "ntb_hw.h"
57 #include "ntb_regs.h"
58
59 #define NTB_NAME "Intel(R) PCI-E Non-Transparent Bridge Driver"
60 #define NTB_VER "1.0"
61
62 MODULE_DESCRIPTION(NTB_NAME);
63 MODULE_VERSION(NTB_VER);
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_AUTHOR("Intel Corporation");
66
67 static bool xeon_errata_workaround = true;
68 module_param(xeon_errata_workaround, bool, 0644);
69 MODULE_PARM_DESC(xeon_errata_workaround, "Workaround for the Xeon Errata");
70
71 enum {
72 NTB_CONN_TRANSPARENT = 0,
73 NTB_CONN_B2B,
74 NTB_CONN_RP,
75 };
76
77 enum {
78 NTB_DEV_USD = 0,
79 NTB_DEV_DSD,
80 };
81
82 enum {
83 SNB_HW = 0,
84 BWD_HW,
85 };
86
87 static struct dentry *debugfs_dir;
88
89 #define BWD_LINK_RECOVERY_TIME 500
90
91 /* Translate memory window 0,1 to BAR 2,4 */
92 #define MW_TO_BAR(mw) (mw * NTB_MAX_NUM_MW + 2)
93
94 static DEFINE_PCI_DEVICE_TABLE(ntb_pci_tbl) = {
95 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
96 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
97 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
98 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
99 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_HSX)},
100 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_JSF)},
101 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_SNB)},
102 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_IVT)},
103 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_PS_HSX)},
104 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_JSF)},
105 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_SNB)},
106 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_IVT)},
107 {PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_SS_HSX)},
108 {0}
109 };
110 MODULE_DEVICE_TABLE(pci, ntb_pci_tbl);
111
112 /**
113 * ntb_register_event_callback() - register event callback
114 * @ndev: pointer to ntb_device instance
115 * @func: callback function to register
116 *
117 * This function registers a callback for any HW driver events such as link
118 * up/down, power management notices and etc.
119 *
120 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
121 */
122 int ntb_register_event_callback(struct ntb_device *ndev,
123 void (*func)(void *handle, enum ntb_hw_event event))
124 {
125 if (ndev->event_cb)
126 return -EINVAL;
127
128 ndev->event_cb = func;
129
130 return 0;
131 }
132
133 /**
134 * ntb_unregister_event_callback() - unregisters the event callback
135 * @ndev: pointer to ntb_device instance
136 *
137 * This function unregisters the existing callback from transport
138 */
139 void ntb_unregister_event_callback(struct ntb_device *ndev)
140 {
141 ndev->event_cb = NULL;
142 }
143
144 /**
145 * ntb_register_db_callback() - register a callback for doorbell interrupt
146 * @ndev: pointer to ntb_device instance
147 * @idx: doorbell index to register callback, zero based
148 * @data: pointer to be returned to caller with every callback
149 * @func: callback function to register
150 *
151 * This function registers a callback function for the doorbell interrupt
152 * on the primary side. The function will unmask the doorbell as well to
153 * allow interrupt.
154 *
155 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
156 */
157 int ntb_register_db_callback(struct ntb_device *ndev, unsigned int idx,
158 void *data, void (*func)(void *data, int db_num))
159 {
160 unsigned long mask;
161
162 if (idx >= ndev->max_cbs || ndev->db_cb[idx].callback) {
163 dev_warn(&ndev->pdev->dev, "Invalid Index.\n");
164 return -EINVAL;
165 }
166
167 ndev->db_cb[idx].callback = func;
168 ndev->db_cb[idx].data = data;
169
170 /* unmask interrupt */
171 mask = readw(ndev->reg_ofs.ldb_mask);
172 clear_bit(idx * ndev->bits_per_vector, &mask);
173 writew(mask, ndev->reg_ofs.ldb_mask);
174
175 return 0;
176 }
177
178 /**
179 * ntb_unregister_db_callback() - unregister a callback for doorbell interrupt
180 * @ndev: pointer to ntb_device instance
181 * @idx: doorbell index to register callback, zero based
182 *
183 * This function unregisters a callback function for the doorbell interrupt
184 * on the primary side. The function will also mask the said doorbell.
185 */
186 void ntb_unregister_db_callback(struct ntb_device *ndev, unsigned int idx)
187 {
188 unsigned long mask;
189
190 if (idx >= ndev->max_cbs || !ndev->db_cb[idx].callback)
191 return;
192
193 mask = readw(ndev->reg_ofs.ldb_mask);
194 set_bit(idx * ndev->bits_per_vector, &mask);
195 writew(mask, ndev->reg_ofs.ldb_mask);
196
197 ndev->db_cb[idx].callback = NULL;
198 }
199
200 /**
201 * ntb_find_transport() - find the transport pointer
202 * @transport: pointer to pci device
203 *
204 * Given the pci device pointer, return the transport pointer passed in when
205 * the transport attached when it was inited.
206 *
207 * RETURNS: pointer to transport.
208 */
209 void *ntb_find_transport(struct pci_dev *pdev)
210 {
211 struct ntb_device *ndev = pci_get_drvdata(pdev);
212 return ndev->ntb_transport;
213 }
214
215 /**
216 * ntb_register_transport() - Register NTB transport with NTB HW driver
217 * @transport: transport identifier
218 *
219 * This function allows a transport to reserve the hardware driver for
220 * NTB usage.
221 *
222 * RETURNS: pointer to ntb_device, NULL on error.
223 */
224 struct ntb_device *ntb_register_transport(struct pci_dev *pdev, void *transport)
225 {
226 struct ntb_device *ndev = pci_get_drvdata(pdev);
227
228 if (ndev->ntb_transport)
229 return NULL;
230
231 ndev->ntb_transport = transport;
232 return ndev;
233 }
234
235 /**
236 * ntb_unregister_transport() - Unregister the transport with the NTB HW driver
237 * @ndev - ntb_device of the transport to be freed
238 *
239 * This function unregisters the transport from the HW driver and performs any
240 * necessary cleanups.
241 */
242 void ntb_unregister_transport(struct ntb_device *ndev)
243 {
244 int i;
245
246 if (!ndev->ntb_transport)
247 return;
248
249 for (i = 0; i < ndev->max_cbs; i++)
250 ntb_unregister_db_callback(ndev, i);
251
252 ntb_unregister_event_callback(ndev);
253 ndev->ntb_transport = NULL;
254 }
255
256 /**
257 * ntb_write_local_spad() - write to the secondary scratchpad register
258 * @ndev: pointer to ntb_device instance
259 * @idx: index to the scratchpad register, 0 based
260 * @val: the data value to put into the register
261 *
262 * This function allows writing of a 32bit value to the indexed scratchpad
263 * register. This writes over the data mirrored to the local scratchpad register
264 * by the remote system.
265 *
266 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
267 */
268 int ntb_write_local_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
269 {
270 if (idx >= ndev->limits.max_spads)
271 return -EINVAL;
272
273 dev_dbg(&ndev->pdev->dev, "Writing %x to local scratch pad index %d\n",
274 val, idx);
275 writel(val, ndev->reg_ofs.spad_read + idx * 4);
276
277 return 0;
278 }
279
280 /**
281 * ntb_read_local_spad() - read from the primary scratchpad register
282 * @ndev: pointer to ntb_device instance
283 * @idx: index to scratchpad register, 0 based
284 * @val: pointer to 32bit integer for storing the register value
285 *
286 * This function allows reading of the 32bit scratchpad register on
287 * the primary (internal) side. This allows the local system to read data
288 * written and mirrored to the scratchpad register by the remote system.
289 *
290 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
291 */
292 int ntb_read_local_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
293 {
294 if (idx >= ndev->limits.max_spads)
295 return -EINVAL;
296
297 *val = readl(ndev->reg_ofs.spad_write + idx * 4);
298 dev_dbg(&ndev->pdev->dev,
299 "Reading %x from local scratch pad index %d\n", *val, idx);
300
301 return 0;
302 }
303
304 /**
305 * ntb_write_remote_spad() - write to the secondary scratchpad register
306 * @ndev: pointer to ntb_device instance
307 * @idx: index to the scratchpad register, 0 based
308 * @val: the data value to put into the register
309 *
310 * This function allows writing of a 32bit value to the indexed scratchpad
311 * register. The register resides on the secondary (external) side. This allows
312 * the local system to write data to be mirrored to the remote systems
313 * scratchpad register.
314 *
315 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
316 */
317 int ntb_write_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 val)
318 {
319 if (idx >= ndev->limits.max_spads)
320 return -EINVAL;
321
322 dev_dbg(&ndev->pdev->dev, "Writing %x to remote scratch pad index %d\n",
323 val, idx);
324 writel(val, ndev->reg_ofs.spad_write + idx * 4);
325
326 return 0;
327 }
328
329 /**
330 * ntb_read_remote_spad() - read from the primary scratchpad register
331 * @ndev: pointer to ntb_device instance
332 * @idx: index to scratchpad register, 0 based
333 * @val: pointer to 32bit integer for storing the register value
334 *
335 * This function allows reading of the 32bit scratchpad register on
336 * the primary (internal) side. This alloows the local system to read the data
337 * it wrote to be mirrored on the remote system.
338 *
339 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
340 */
341 int ntb_read_remote_spad(struct ntb_device *ndev, unsigned int idx, u32 *val)
342 {
343 if (idx >= ndev->limits.max_spads)
344 return -EINVAL;
345
346 *val = readl(ndev->reg_ofs.spad_read + idx * 4);
347 dev_dbg(&ndev->pdev->dev,
348 "Reading %x from remote scratch pad index %d\n", *val, idx);
349
350 return 0;
351 }
352
353 /**
354 * ntb_get_mw_base() - get addr for the NTB memory window
355 * @ndev: pointer to ntb_device instance
356 * @mw: memory window number
357 *
358 * This function provides the base address of the memory window specified.
359 *
360 * RETURNS: address, or NULL on error.
361 */
362 resource_size_t ntb_get_mw_base(struct ntb_device *ndev, unsigned int mw)
363 {
364 if (mw >= ntb_max_mw(ndev))
365 return 0;
366
367 return pci_resource_start(ndev->pdev, MW_TO_BAR(mw));
368 }
369
370 /**
371 * ntb_get_mw_vbase() - get virtual addr for the NTB memory window
372 * @ndev: pointer to ntb_device instance
373 * @mw: memory window number
374 *
375 * This function provides the base virtual address of the memory window
376 * specified.
377 *
378 * RETURNS: pointer to virtual address, or NULL on error.
379 */
380 void __iomem *ntb_get_mw_vbase(struct ntb_device *ndev, unsigned int mw)
381 {
382 if (mw >= ntb_max_mw(ndev))
383 return NULL;
384
385 return ndev->mw[mw].vbase;
386 }
387
388 /**
389 * ntb_get_mw_size() - return size of NTB memory window
390 * @ndev: pointer to ntb_device instance
391 * @mw: memory window number
392 *
393 * This function provides the physical size of the memory window specified
394 *
395 * RETURNS: the size of the memory window or zero on error
396 */
397 u64 ntb_get_mw_size(struct ntb_device *ndev, unsigned int mw)
398 {
399 if (mw >= ntb_max_mw(ndev))
400 return 0;
401
402 return ndev->mw[mw].bar_sz;
403 }
404
405 /**
406 * ntb_set_mw_addr - set the memory window address
407 * @ndev: pointer to ntb_device instance
408 * @mw: memory window number
409 * @addr: base address for data
410 *
411 * This function sets the base physical address of the memory window. This
412 * memory address is where data from the remote system will be transfered into
413 * or out of depending on how the transport is configured.
414 */
415 void ntb_set_mw_addr(struct ntb_device *ndev, unsigned int mw, u64 addr)
416 {
417 if (mw >= ntb_max_mw(ndev))
418 return;
419
420 dev_dbg(&ndev->pdev->dev, "Writing addr %Lx to BAR %d\n", addr,
421 MW_TO_BAR(mw));
422
423 ndev->mw[mw].phys_addr = addr;
424
425 switch (MW_TO_BAR(mw)) {
426 case NTB_BAR_23:
427 writeq(addr, ndev->reg_ofs.bar2_xlat);
428 break;
429 case NTB_BAR_45:
430 writeq(addr, ndev->reg_ofs.bar4_xlat);
431 break;
432 }
433 }
434
435 /**
436 * ntb_ring_doorbell() - Set the doorbell on the secondary/external side
437 * @ndev: pointer to ntb_device instance
438 * @db: doorbell to ring
439 *
440 * This function allows triggering of a doorbell on the secondary/external
441 * side that will initiate an interrupt on the remote host
442 *
443 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
444 */
445 void ntb_ring_doorbell(struct ntb_device *ndev, unsigned int db)
446 {
447 dev_dbg(&ndev->pdev->dev, "%s: ringing doorbell %d\n", __func__, db);
448
449 if (ndev->hw_type == BWD_HW)
450 writeq((u64) 1 << db, ndev->reg_ofs.rdb);
451 else
452 writew(((1 << ndev->bits_per_vector) - 1) <<
453 (db * ndev->bits_per_vector), ndev->reg_ofs.rdb);
454 }
455
456 static void bwd_recover_link(struct ntb_device *ndev)
457 {
458 u32 status;
459
460 /* Driver resets the NTB ModPhy lanes - magic! */
461 writeb(0xe0, ndev->reg_base + BWD_MODPHY_PCSREG6);
462 writeb(0x40, ndev->reg_base + BWD_MODPHY_PCSREG4);
463 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG4);
464 writeb(0x60, ndev->reg_base + BWD_MODPHY_PCSREG6);
465
466 /* Driver waits 100ms to allow the NTB ModPhy to settle */
467 msleep(100);
468
469 /* Clear AER Errors, write to clear */
470 status = readl(ndev->reg_base + BWD_ERRCORSTS_OFFSET);
471 dev_dbg(&ndev->pdev->dev, "ERRCORSTS = %x\n", status);
472 status &= PCI_ERR_COR_REP_ROLL;
473 writel(status, ndev->reg_base + BWD_ERRCORSTS_OFFSET);
474
475 /* Clear unexpected electrical idle event in LTSSM, write to clear */
476 status = readl(ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
477 dev_dbg(&ndev->pdev->dev, "LTSSMERRSTS0 = %x\n", status);
478 status |= BWD_LTSSMERRSTS0_UNEXPECTEDEI;
479 writel(status, ndev->reg_base + BWD_LTSSMERRSTS0_OFFSET);
480
481 /* Clear DeSkew Buffer error, write to clear */
482 status = readl(ndev->reg_base + BWD_DESKEWSTS_OFFSET);
483 dev_dbg(&ndev->pdev->dev, "DESKEWSTS = %x\n", status);
484 status |= BWD_DESKEWSTS_DBERR;
485 writel(status, ndev->reg_base + BWD_DESKEWSTS_OFFSET);
486
487 status = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
488 dev_dbg(&ndev->pdev->dev, "IBSTERRRCRVSTS0 = %x\n", status);
489 status &= BWD_IBIST_ERR_OFLOW;
490 writel(status, ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
491
492 /* Releases the NTB state machine to allow the link to retrain */
493 status = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
494 dev_dbg(&ndev->pdev->dev, "LTSSMSTATEJMP = %x\n", status);
495 status &= ~BWD_LTSSMSTATEJMP_FORCEDETECT;
496 writel(status, ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
497 }
498
499 static void ntb_link_event(struct ntb_device *ndev, int link_state)
500 {
501 unsigned int event;
502
503 if (ndev->link_status == link_state)
504 return;
505
506 if (link_state == NTB_LINK_UP) {
507 u16 status;
508
509 dev_info(&ndev->pdev->dev, "Link Up\n");
510 ndev->link_status = NTB_LINK_UP;
511 event = NTB_EVENT_HW_LINK_UP;
512
513 if (ndev->hw_type == BWD_HW ||
514 ndev->conn_type == NTB_CONN_TRANSPARENT)
515 status = readw(ndev->reg_ofs.lnk_stat);
516 else {
517 int rc = pci_read_config_word(ndev->pdev,
518 SNB_LINK_STATUS_OFFSET,
519 &status);
520 if (rc)
521 return;
522 }
523
524 ndev->link_width = (status & NTB_LINK_WIDTH_MASK) >> 4;
525 ndev->link_speed = (status & NTB_LINK_SPEED_MASK);
526 dev_info(&ndev->pdev->dev, "Link Width %d, Link Speed %d\n",
527 ndev->link_width, ndev->link_speed);
528 } else {
529 dev_info(&ndev->pdev->dev, "Link Down\n");
530 ndev->link_status = NTB_LINK_DOWN;
531 event = NTB_EVENT_HW_LINK_DOWN;
532 /* Don't modify link width/speed, we need it in link recovery */
533 }
534
535 /* notify the upper layer if we have an event change */
536 if (ndev->event_cb)
537 ndev->event_cb(ndev->ntb_transport, event);
538 }
539
540 static int ntb_link_status(struct ntb_device *ndev)
541 {
542 int link_state;
543
544 if (ndev->hw_type == BWD_HW) {
545 u32 ntb_cntl;
546
547 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
548 if (ntb_cntl & BWD_CNTL_LINK_DOWN)
549 link_state = NTB_LINK_DOWN;
550 else
551 link_state = NTB_LINK_UP;
552 } else {
553 u16 status;
554 int rc;
555
556 rc = pci_read_config_word(ndev->pdev, SNB_LINK_STATUS_OFFSET,
557 &status);
558 if (rc)
559 return rc;
560
561 if (status & NTB_LINK_STATUS_ACTIVE)
562 link_state = NTB_LINK_UP;
563 else
564 link_state = NTB_LINK_DOWN;
565 }
566
567 ntb_link_event(ndev, link_state);
568
569 return 0;
570 }
571
572 static void bwd_link_recovery(struct work_struct *work)
573 {
574 struct ntb_device *ndev = container_of(work, struct ntb_device,
575 lr_timer.work);
576 u32 status32;
577
578 bwd_recover_link(ndev);
579 /* There is a potential race between the 2 NTB devices recovering at the
580 * same time. If the times are the same, the link will not recover and
581 * the driver will be stuck in this loop forever. Add a random interval
582 * to the recovery time to prevent this race.
583 */
584 msleep(BWD_LINK_RECOVERY_TIME + prandom_u32() % BWD_LINK_RECOVERY_TIME);
585
586 status32 = readl(ndev->reg_base + BWD_LTSSMSTATEJMP_OFFSET);
587 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT)
588 goto retry;
589
590 status32 = readl(ndev->reg_base + BWD_IBSTERRRCRVSTS0_OFFSET);
591 if (status32 & BWD_IBIST_ERR_OFLOW)
592 goto retry;
593
594 status32 = readl(ndev->reg_ofs.lnk_cntl);
595 if (!(status32 & BWD_CNTL_LINK_DOWN)) {
596 unsigned char speed, width;
597 u16 status16;
598
599 status16 = readw(ndev->reg_ofs.lnk_stat);
600 width = (status16 & NTB_LINK_WIDTH_MASK) >> 4;
601 speed = (status16 & NTB_LINK_SPEED_MASK);
602 if (ndev->link_width != width || ndev->link_speed != speed)
603 goto retry;
604 }
605
606 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
607 return;
608
609 retry:
610 schedule_delayed_work(&ndev->lr_timer, NTB_HB_TIMEOUT);
611 }
612
613 /* BWD doesn't have link status interrupt, poll on that platform */
614 static void bwd_link_poll(struct work_struct *work)
615 {
616 struct ntb_device *ndev = container_of(work, struct ntb_device,
617 hb_timer.work);
618 unsigned long ts = jiffies;
619
620 /* If we haven't gotten an interrupt in a while, check the BWD link
621 * status bit
622 */
623 if (ts > ndev->last_ts + NTB_HB_TIMEOUT) {
624 int rc = ntb_link_status(ndev);
625 if (rc)
626 dev_err(&ndev->pdev->dev,
627 "Error determining link status\n");
628
629 /* Check to see if a link error is the cause of the link down */
630 if (ndev->link_status == NTB_LINK_DOWN) {
631 u32 status32 = readl(ndev->reg_base +
632 BWD_LTSSMSTATEJMP_OFFSET);
633 if (status32 & BWD_LTSSMSTATEJMP_FORCEDETECT) {
634 schedule_delayed_work(&ndev->lr_timer, 0);
635 return;
636 }
637 }
638 }
639
640 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
641 }
642
643 static int ntb_xeon_setup(struct ntb_device *ndev)
644 {
645 int rc;
646 u8 val;
647
648 ndev->hw_type = SNB_HW;
649
650 rc = pci_read_config_byte(ndev->pdev, NTB_PPD_OFFSET, &val);
651 if (rc)
652 return rc;
653
654 if (val & SNB_PPD_DEV_TYPE)
655 ndev->dev_type = NTB_DEV_USD;
656 else
657 ndev->dev_type = NTB_DEV_DSD;
658
659 switch (val & SNB_PPD_CONN_TYPE) {
660 case NTB_CONN_B2B:
661 dev_info(&ndev->pdev->dev, "Conn Type = B2B\n");
662 ndev->conn_type = NTB_CONN_B2B;
663 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
664 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
665 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
666 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
667 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
668 ndev->limits.max_spads = SNB_MAX_B2B_SPADS;
669
670 /* There is a Xeon hardware errata related to writes to
671 * SDOORBELL or B2BDOORBELL in conjunction with inbound access
672 * to NTB MMIO Space, which may hang the system. To workaround
673 * this use the second memory window to access the interrupt and
674 * scratch pad registers on the remote system.
675 */
676 if (xeon_errata_workaround) {
677 if (!ndev->mw[1].bar_sz)
678 return -EINVAL;
679
680 ndev->limits.max_mw = SNB_ERRATA_MAX_MW;
681 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
682 ndev->reg_ofs.spad_write = ndev->mw[1].vbase +
683 SNB_SPAD_OFFSET;
684 ndev->reg_ofs.rdb = ndev->mw[1].vbase +
685 SNB_PDOORBELL_OFFSET;
686
687 /* Set the Limit register to 4k, the minimum size, to
688 * prevent an illegal access
689 */
690 writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
691 SNB_PBAR4LMT_OFFSET);
692 /* HW errata on the Limit registers. They can only be
693 * written when the base register is 4GB aligned and
694 * < 32bit. This should already be the case based on the
695 * driver defaults, but write the Limit registers first
696 * just in case.
697 */
698 } else {
699 ndev->limits.max_mw = SNB_MAX_MW;
700
701 /* HW Errata on bit 14 of b2bdoorbell register. Writes
702 * will not be mirrored to the remote system. Shrink
703 * the number of bits by one, since bit 14 is the last
704 * bit.
705 */
706 ndev->limits.max_db_bits = SNB_MAX_DB_BITS - 1;
707 ndev->reg_ofs.spad_write = ndev->reg_base +
708 SNB_B2B_SPAD_OFFSET;
709 ndev->reg_ofs.rdb = ndev->reg_base +
710 SNB_B2B_DOORBELL_OFFSET;
711
712 /* Disable the Limit register, just incase it is set to
713 * something silly
714 */
715 writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
716 /* HW errata on the Limit registers. They can only be
717 * written when the base register is 4GB aligned and
718 * < 32bit. This should already be the case based on the
719 * driver defaults, but write the Limit registers first
720 * just in case.
721 */
722 }
723
724 /* The Xeon errata workaround requires setting SBAR Base
725 * addresses to known values, so that the PBAR XLAT can be
726 * pointed at SBAR0 of the remote system.
727 */
728 if (ndev->dev_type == NTB_DEV_USD) {
729 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
730 SNB_PBAR2XLAT_OFFSET);
731 if (xeon_errata_workaround)
732 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
733 SNB_PBAR4XLAT_OFFSET);
734 else {
735 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
736 SNB_PBAR4XLAT_OFFSET);
737 /* B2B_XLAT_OFFSET is a 64bit register, but can
738 * only take 32bit writes
739 */
740 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
741 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
742 writel(SNB_MBAR01_DSD_ADDR >> 32,
743 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
744 }
745
746 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
747 SNB_SBAR0BASE_OFFSET);
748 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
749 SNB_SBAR2BASE_OFFSET);
750 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
751 SNB_SBAR4BASE_OFFSET);
752 } else {
753 writeq(SNB_MBAR23_USD_ADDR, ndev->reg_base +
754 SNB_PBAR2XLAT_OFFSET);
755 if (xeon_errata_workaround)
756 writeq(SNB_MBAR01_USD_ADDR, ndev->reg_base +
757 SNB_PBAR4XLAT_OFFSET);
758 else {
759 writeq(SNB_MBAR45_USD_ADDR, ndev->reg_base +
760 SNB_PBAR4XLAT_OFFSET);
761 /* B2B_XLAT_OFFSET is a 64bit register, but can
762 * only take 32bit writes
763 */
764 writel(SNB_MBAR01_DSD_ADDR & 0xffffffff,
765 ndev->reg_base + SNB_B2B_XLAT_OFFSETL);
766 writel(SNB_MBAR01_USD_ADDR >> 32,
767 ndev->reg_base + SNB_B2B_XLAT_OFFSETU);
768 }
769 writeq(SNB_MBAR01_DSD_ADDR, ndev->reg_base +
770 SNB_SBAR0BASE_OFFSET);
771 writeq(SNB_MBAR23_DSD_ADDR, ndev->reg_base +
772 SNB_SBAR2BASE_OFFSET);
773 writeq(SNB_MBAR45_DSD_ADDR, ndev->reg_base +
774 SNB_SBAR4BASE_OFFSET);
775 }
776 break;
777 case NTB_CONN_RP:
778 dev_info(&ndev->pdev->dev, "Conn Type = RP\n");
779 ndev->conn_type = NTB_CONN_RP;
780
781 if (xeon_errata_workaround) {
782 dev_err(&ndev->pdev->dev,
783 "NTB-RP disabled due to hardware errata. To disregard this warning and potentially lock-up the system, add the parameter 'xeon_errata_workaround=0'.\n");
784 return -EINVAL;
785 }
786
787 /* Scratch pads need to have exclusive access from the primary
788 * or secondary side. Halve the num spads so that each side can
789 * have an equal amount.
790 */
791 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
792 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
793 /* Note: The SDOORBELL is the cause of the errata. You REALLY
794 * don't want to touch it.
795 */
796 ndev->reg_ofs.rdb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
797 ndev->reg_ofs.ldb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
798 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET;
799 /* Offset the start of the spads to correspond to whether it is
800 * primary or secondary
801 */
802 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET +
803 ndev->limits.max_spads * 4;
804 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET;
805 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET;
806 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET;
807 ndev->limits.max_mw = SNB_MAX_MW;
808 break;
809 case NTB_CONN_TRANSPARENT:
810 dev_info(&ndev->pdev->dev, "Conn Type = TRANSPARENT\n");
811 ndev->conn_type = NTB_CONN_TRANSPARENT;
812 /* Scratch pads need to have exclusive access from the primary
813 * or secondary side. Halve the num spads so that each side can
814 * have an equal amount.
815 */
816 ndev->limits.max_spads = SNB_MAX_COMPAT_SPADS / 2;
817 ndev->limits.max_db_bits = SNB_MAX_DB_BITS;
818 ndev->reg_ofs.rdb = ndev->reg_base + SNB_PDOORBELL_OFFSET;
819 ndev->reg_ofs.ldb = ndev->reg_base + SNB_SDOORBELL_OFFSET;
820 ndev->reg_ofs.ldb_mask = ndev->reg_base + SNB_SDBMSK_OFFSET;
821 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_SPAD_OFFSET;
822 /* Offset the start of the spads to correspond to whether it is
823 * primary or secondary
824 */
825 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET +
826 ndev->limits.max_spads * 4;
827 ndev->reg_ofs.bar2_xlat = ndev->reg_base + SNB_PBAR2XLAT_OFFSET;
828 ndev->reg_ofs.bar4_xlat = ndev->reg_base + SNB_PBAR4XLAT_OFFSET;
829
830 ndev->limits.max_mw = SNB_MAX_MW;
831 break;
832 default:
833 /* Most likely caused by the remote NTB-RP device not being
834 * configured
835 */
836 dev_err(&ndev->pdev->dev, "Unknown PPD %x\n", val);
837 return -EINVAL;
838 }
839
840 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET;
841 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_SLINK_STATUS_OFFSET;
842 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET;
843
844 ndev->limits.msix_cnt = SNB_MSIX_CNT;
845 ndev->bits_per_vector = SNB_DB_BITS_PER_VEC;
846
847 return 0;
848 }
849
850 static int ntb_bwd_setup(struct ntb_device *ndev)
851 {
852 int rc;
853 u32 val;
854
855 ndev->hw_type = BWD_HW;
856
857 rc = pci_read_config_dword(ndev->pdev, NTB_PPD_OFFSET, &val);
858 if (rc)
859 return rc;
860
861 switch ((val & BWD_PPD_CONN_TYPE) >> 8) {
862 case NTB_CONN_B2B:
863 ndev->conn_type = NTB_CONN_B2B;
864 break;
865 case NTB_CONN_RP:
866 default:
867 dev_err(&ndev->pdev->dev, "Unsupported NTB configuration\n");
868 return -EINVAL;
869 }
870
871 if (val & BWD_PPD_DEV_TYPE)
872 ndev->dev_type = NTB_DEV_DSD;
873 else
874 ndev->dev_type = NTB_DEV_USD;
875
876 /* Initiate PCI-E link training */
877 rc = pci_write_config_dword(ndev->pdev, NTB_PPD_OFFSET,
878 val | BWD_PPD_INIT_LINK);
879 if (rc)
880 return rc;
881
882 ndev->reg_ofs.ldb = ndev->reg_base + BWD_PDOORBELL_OFFSET;
883 ndev->reg_ofs.ldb_mask = ndev->reg_base + BWD_PDBMSK_OFFSET;
884 ndev->reg_ofs.rdb = ndev->reg_base + BWD_B2B_DOORBELL_OFFSET;
885 ndev->reg_ofs.bar2_xlat = ndev->reg_base + BWD_SBAR2XLAT_OFFSET;
886 ndev->reg_ofs.bar4_xlat = ndev->reg_base + BWD_SBAR4XLAT_OFFSET;
887 ndev->reg_ofs.lnk_cntl = ndev->reg_base + BWD_NTBCNTL_OFFSET;
888 ndev->reg_ofs.lnk_stat = ndev->reg_base + BWD_LINK_STATUS_OFFSET;
889 ndev->reg_ofs.spad_read = ndev->reg_base + BWD_SPAD_OFFSET;
890 ndev->reg_ofs.spad_write = ndev->reg_base + BWD_B2B_SPAD_OFFSET;
891 ndev->reg_ofs.spci_cmd = ndev->reg_base + BWD_PCICMD_OFFSET;
892 ndev->limits.max_mw = BWD_MAX_MW;
893 ndev->limits.max_spads = BWD_MAX_SPADS;
894 ndev->limits.max_db_bits = BWD_MAX_DB_BITS;
895 ndev->limits.msix_cnt = BWD_MSIX_CNT;
896 ndev->bits_per_vector = BWD_DB_BITS_PER_VEC;
897
898 /* Since bwd doesn't have a link interrupt, setup a poll timer */
899 INIT_DELAYED_WORK(&ndev->hb_timer, bwd_link_poll);
900 INIT_DELAYED_WORK(&ndev->lr_timer, bwd_link_recovery);
901 schedule_delayed_work(&ndev->hb_timer, NTB_HB_TIMEOUT);
902
903 return 0;
904 }
905
906 static int ntb_device_setup(struct ntb_device *ndev)
907 {
908 int rc;
909
910 switch (ndev->pdev->device) {
911 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
912 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
913 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
914 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
915 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
916 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
917 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
918 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
919 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
920 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
921 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
922 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
923 rc = ntb_xeon_setup(ndev);
924 break;
925 case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
926 rc = ntb_bwd_setup(ndev);
927 break;
928 default:
929 rc = -ENODEV;
930 }
931
932 if (rc)
933 return rc;
934
935 dev_info(&ndev->pdev->dev, "Device Type = %s\n",
936 ndev->dev_type == NTB_DEV_USD ? "USD/DSP" : "DSD/USP");
937
938 if (ndev->conn_type == NTB_CONN_B2B)
939 /* Enable Bus Master and Memory Space on the secondary side */
940 writew(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
941 ndev->reg_ofs.spci_cmd);
942
943 return 0;
944 }
945
946 static void ntb_device_free(struct ntb_device *ndev)
947 {
948 if (ndev->hw_type == BWD_HW) {
949 cancel_delayed_work_sync(&ndev->hb_timer);
950 cancel_delayed_work_sync(&ndev->lr_timer);
951 }
952 }
953
954 static irqreturn_t bwd_callback_msix_irq(int irq, void *data)
955 {
956 struct ntb_db_cb *db_cb = data;
957 struct ntb_device *ndev = db_cb->ndev;
958
959 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
960 db_cb->db_num);
961
962 if (db_cb->callback)
963 db_cb->callback(db_cb->data, db_cb->db_num);
964
965 /* No need to check for the specific HB irq, any interrupt means
966 * we're connected.
967 */
968 ndev->last_ts = jiffies;
969
970 writeq((u64) 1 << db_cb->db_num, ndev->reg_ofs.ldb);
971
972 return IRQ_HANDLED;
973 }
974
975 static irqreturn_t xeon_callback_msix_irq(int irq, void *data)
976 {
977 struct ntb_db_cb *db_cb = data;
978 struct ntb_device *ndev = db_cb->ndev;
979
980 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for DB %d\n", irq,
981 db_cb->db_num);
982
983 if (db_cb->callback)
984 db_cb->callback(db_cb->data, db_cb->db_num);
985
986 /* On Sandybridge, there are 16 bits in the interrupt register
987 * but only 4 vectors. So, 5 bits are assigned to the first 3
988 * vectors, with the 4th having a single bit for link
989 * interrupts.
990 */
991 writew(((1 << ndev->bits_per_vector) - 1) <<
992 (db_cb->db_num * ndev->bits_per_vector), ndev->reg_ofs.ldb);
993
994 return IRQ_HANDLED;
995 }
996
997 /* Since we do not have a HW doorbell in BWD, this is only used in JF/JT */
998 static irqreturn_t xeon_event_msix_irq(int irq, void *dev)
999 {
1000 struct ntb_device *ndev = dev;
1001 int rc;
1002
1003 dev_dbg(&ndev->pdev->dev, "MSI-X irq %d received for Events\n", irq);
1004
1005 rc = ntb_link_status(ndev);
1006 if (rc)
1007 dev_err(&ndev->pdev->dev, "Error determining link status\n");
1008
1009 /* bit 15 is always the link bit */
1010 writew(1 << SNB_LINK_DB, ndev->reg_ofs.ldb);
1011
1012 return IRQ_HANDLED;
1013 }
1014
1015 static irqreturn_t ntb_interrupt(int irq, void *dev)
1016 {
1017 struct ntb_device *ndev = dev;
1018 unsigned int i = 0;
1019
1020 if (ndev->hw_type == BWD_HW) {
1021 u64 ldb = readq(ndev->reg_ofs.ldb);
1022
1023 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %Lx\n", irq, ldb);
1024
1025 while (ldb) {
1026 i = __ffs(ldb);
1027 ldb &= ldb - 1;
1028 bwd_callback_msix_irq(irq, &ndev->db_cb[i]);
1029 }
1030 } else {
1031 u16 ldb = readw(ndev->reg_ofs.ldb);
1032
1033 dev_dbg(&ndev->pdev->dev, "irq %d - ldb = %x\n", irq, ldb);
1034
1035 if (ldb & SNB_DB_HW_LINK) {
1036 xeon_event_msix_irq(irq, dev);
1037 ldb &= ~SNB_DB_HW_LINK;
1038 }
1039
1040 while (ldb) {
1041 i = __ffs(ldb);
1042 ldb &= ldb - 1;
1043 xeon_callback_msix_irq(irq, &ndev->db_cb[i]);
1044 }
1045 }
1046
1047 return IRQ_HANDLED;
1048 }
1049
1050 static int ntb_setup_msix(struct ntb_device *ndev)
1051 {
1052 struct pci_dev *pdev = ndev->pdev;
1053 struct msix_entry *msix;
1054 int msix_entries;
1055 int rc, i;
1056 u16 val;
1057
1058 if (!pdev->msix_cap) {
1059 rc = -EIO;
1060 goto err;
1061 }
1062
1063 rc = pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &val);
1064 if (rc)
1065 goto err;
1066
1067 msix_entries = msix_table_size(val);
1068 if (msix_entries > ndev->limits.msix_cnt) {
1069 rc = -EINVAL;
1070 goto err;
1071 }
1072
1073 ndev->msix_entries = kmalloc(sizeof(struct msix_entry) * msix_entries,
1074 GFP_KERNEL);
1075 if (!ndev->msix_entries) {
1076 rc = -ENOMEM;
1077 goto err;
1078 }
1079
1080 for (i = 0; i < msix_entries; i++)
1081 ndev->msix_entries[i].entry = i;
1082
1083 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1084 if (rc < 0)
1085 goto err1;
1086 if (rc > 0) {
1087 /* On SNB, the link interrupt is always tied to 4th vector. If
1088 * we can't get all 4, then we can't use MSI-X.
1089 */
1090 if (ndev->hw_type != BWD_HW) {
1091 rc = -EIO;
1092 goto err1;
1093 }
1094
1095 dev_warn(&pdev->dev,
1096 "Only %d MSI-X vectors. Limiting the number of queues to that number.\n",
1097 rc);
1098 msix_entries = rc;
1099
1100 rc = pci_enable_msix(pdev, ndev->msix_entries, msix_entries);
1101 if (rc)
1102 goto err1;
1103 }
1104
1105 for (i = 0; i < msix_entries; i++) {
1106 msix = &ndev->msix_entries[i];
1107 WARN_ON(!msix->vector);
1108
1109 /* Use the last MSI-X vector for Link status */
1110 if (ndev->hw_type == BWD_HW) {
1111 rc = request_irq(msix->vector, bwd_callback_msix_irq, 0,
1112 "ntb-callback-msix", &ndev->db_cb[i]);
1113 if (rc)
1114 goto err2;
1115 } else {
1116 if (i == msix_entries - 1) {
1117 rc = request_irq(msix->vector,
1118 xeon_event_msix_irq, 0,
1119 "ntb-event-msix", ndev);
1120 if (rc)
1121 goto err2;
1122 } else {
1123 rc = request_irq(msix->vector,
1124 xeon_callback_msix_irq, 0,
1125 "ntb-callback-msix",
1126 &ndev->db_cb[i]);
1127 if (rc)
1128 goto err2;
1129 }
1130 }
1131 }
1132
1133 ndev->num_msix = msix_entries;
1134 if (ndev->hw_type == BWD_HW)
1135 ndev->max_cbs = msix_entries;
1136 else
1137 ndev->max_cbs = msix_entries - 1;
1138
1139 return 0;
1140
1141 err2:
1142 while (--i >= 0) {
1143 msix = &ndev->msix_entries[i];
1144 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1145 free_irq(msix->vector, ndev);
1146 else
1147 free_irq(msix->vector, &ndev->db_cb[i]);
1148 }
1149 pci_disable_msix(pdev);
1150 err1:
1151 kfree(ndev->msix_entries);
1152 dev_err(&pdev->dev, "Error allocating MSI-X interrupt\n");
1153 err:
1154 ndev->num_msix = 0;
1155 return rc;
1156 }
1157
1158 static int ntb_setup_msi(struct ntb_device *ndev)
1159 {
1160 struct pci_dev *pdev = ndev->pdev;
1161 int rc;
1162
1163 rc = pci_enable_msi(pdev);
1164 if (rc)
1165 return rc;
1166
1167 rc = request_irq(pdev->irq, ntb_interrupt, 0, "ntb-msi", ndev);
1168 if (rc) {
1169 pci_disable_msi(pdev);
1170 dev_err(&pdev->dev, "Error allocating MSI interrupt\n");
1171 return rc;
1172 }
1173
1174 return 0;
1175 }
1176
1177 static int ntb_setup_intx(struct ntb_device *ndev)
1178 {
1179 struct pci_dev *pdev = ndev->pdev;
1180 int rc;
1181
1182 pci_msi_off(pdev);
1183
1184 /* Verify intx is enabled */
1185 pci_intx(pdev, 1);
1186
1187 rc = request_irq(pdev->irq, ntb_interrupt, IRQF_SHARED, "ntb-intx",
1188 ndev);
1189 if (rc)
1190 return rc;
1191
1192 return 0;
1193 }
1194
1195 static int ntb_setup_interrupts(struct ntb_device *ndev)
1196 {
1197 int rc;
1198
1199 /* On BWD, disable all interrupts. On SNB, disable all but Link
1200 * Interrupt. The rest will be unmasked as callbacks are registered.
1201 */
1202 if (ndev->hw_type == BWD_HW)
1203 writeq(~0, ndev->reg_ofs.ldb_mask);
1204 else {
1205 u16 var = 1 << SNB_LINK_DB;
1206 writew(~var, ndev->reg_ofs.ldb_mask);
1207 }
1208
1209 rc = ntb_setup_msix(ndev);
1210 if (!rc)
1211 goto done;
1212
1213 ndev->bits_per_vector = 1;
1214 ndev->max_cbs = ndev->limits.max_db_bits;
1215
1216 rc = ntb_setup_msi(ndev);
1217 if (!rc)
1218 goto done;
1219
1220 rc = ntb_setup_intx(ndev);
1221 if (rc) {
1222 dev_err(&ndev->pdev->dev, "no usable interrupts\n");
1223 return rc;
1224 }
1225
1226 done:
1227 return 0;
1228 }
1229
1230 static void ntb_free_interrupts(struct ntb_device *ndev)
1231 {
1232 struct pci_dev *pdev = ndev->pdev;
1233
1234 /* mask interrupts */
1235 if (ndev->hw_type == BWD_HW)
1236 writeq(~0, ndev->reg_ofs.ldb_mask);
1237 else
1238 writew(~0, ndev->reg_ofs.ldb_mask);
1239
1240 if (ndev->num_msix) {
1241 struct msix_entry *msix;
1242 u32 i;
1243
1244 for (i = 0; i < ndev->num_msix; i++) {
1245 msix = &ndev->msix_entries[i];
1246 if (ndev->hw_type != BWD_HW && i == ndev->num_msix - 1)
1247 free_irq(msix->vector, ndev);
1248 else
1249 free_irq(msix->vector, &ndev->db_cb[i]);
1250 }
1251 pci_disable_msix(pdev);
1252 } else {
1253 free_irq(pdev->irq, ndev);
1254
1255 if (pci_dev_msi_enabled(pdev))
1256 pci_disable_msi(pdev);
1257 }
1258 }
1259
1260 static int ntb_create_callbacks(struct ntb_device *ndev)
1261 {
1262 int i;
1263
1264 /* Chicken-egg issue. We won't know how many callbacks are necessary
1265 * until we see how many MSI-X vectors we get, but these pointers need
1266 * to be passed into the MSI-X register function. So, we allocate the
1267 * max, knowing that they might not all be used, to work around this.
1268 */
1269 ndev->db_cb = kcalloc(ndev->limits.max_db_bits,
1270 sizeof(struct ntb_db_cb),
1271 GFP_KERNEL);
1272 if (!ndev->db_cb)
1273 return -ENOMEM;
1274
1275 for (i = 0; i < ndev->limits.max_db_bits; i++) {
1276 ndev->db_cb[i].db_num = i;
1277 ndev->db_cb[i].ndev = ndev;
1278 }
1279
1280 return 0;
1281 }
1282
1283 static void ntb_free_callbacks(struct ntb_device *ndev)
1284 {
1285 int i;
1286
1287 for (i = 0; i < ndev->limits.max_db_bits; i++)
1288 ntb_unregister_db_callback(ndev, i);
1289
1290 kfree(ndev->db_cb);
1291 }
1292
1293 static void ntb_setup_debugfs(struct ntb_device *ndev)
1294 {
1295 if (!debugfs_initialized())
1296 return;
1297
1298 if (!debugfs_dir)
1299 debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL);
1300
1301 ndev->debugfs_dir = debugfs_create_dir(pci_name(ndev->pdev),
1302 debugfs_dir);
1303 }
1304
1305 static void ntb_free_debugfs(struct ntb_device *ndev)
1306 {
1307 debugfs_remove_recursive(ndev->debugfs_dir);
1308
1309 if (debugfs_dir && simple_empty(debugfs_dir)) {
1310 debugfs_remove_recursive(debugfs_dir);
1311 debugfs_dir = NULL;
1312 }
1313 }
1314
1315 static void ntb_hw_link_up(struct ntb_device *ndev)
1316 {
1317 if (ndev->conn_type == NTB_CONN_TRANSPARENT)
1318 ntb_link_event(ndev, NTB_LINK_UP);
1319 else {
1320 u32 ntb_cntl;
1321
1322 /* Let's bring the NTB link up */
1323 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1324 ntb_cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK);
1325 ntb_cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP;
1326 ntb_cntl |= NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP;
1327 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1328 }
1329 }
1330
1331 static void ntb_hw_link_down(struct ntb_device *ndev)
1332 {
1333 u32 ntb_cntl;
1334
1335 if (ndev->conn_type == NTB_CONN_TRANSPARENT) {
1336 ntb_link_event(ndev, NTB_LINK_DOWN);
1337 return;
1338 }
1339
1340 /* Bring NTB link down */
1341 ntb_cntl = readl(ndev->reg_ofs.lnk_cntl);
1342 ntb_cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP);
1343 ntb_cntl &= ~(NTB_CNTL_P2S_BAR45_SNOOP | NTB_CNTL_S2P_BAR45_SNOOP);
1344 ntb_cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK;
1345 writel(ntb_cntl, ndev->reg_ofs.lnk_cntl);
1346 }
1347
1348 static int ntb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1349 {
1350 struct ntb_device *ndev;
1351 int rc, i;
1352
1353 ndev = kzalloc(sizeof(struct ntb_device), GFP_KERNEL);
1354 if (!ndev)
1355 return -ENOMEM;
1356
1357 ndev->pdev = pdev;
1358 ndev->link_status = NTB_LINK_DOWN;
1359 pci_set_drvdata(pdev, ndev);
1360 ntb_setup_debugfs(ndev);
1361
1362 rc = pci_enable_device(pdev);
1363 if (rc)
1364 goto err;
1365
1366 pci_set_master(ndev->pdev);
1367
1368 rc = pci_request_selected_regions(pdev, NTB_BAR_MASK, KBUILD_MODNAME);
1369 if (rc)
1370 goto err1;
1371
1372 ndev->reg_base = pci_ioremap_bar(pdev, NTB_BAR_MMIO);
1373 if (!ndev->reg_base) {
1374 dev_warn(&pdev->dev, "Cannot remap BAR 0\n");
1375 rc = -EIO;
1376 goto err2;
1377 }
1378
1379 for (i = 0; i < NTB_MAX_NUM_MW; i++) {
1380 ndev->mw[i].bar_sz = pci_resource_len(pdev, MW_TO_BAR(i));
1381 ndev->mw[i].vbase =
1382 ioremap_wc(pci_resource_start(pdev, MW_TO_BAR(i)),
1383 ndev->mw[i].bar_sz);
1384 dev_info(&pdev->dev, "MW %d size %llu\n", i,
1385 (unsigned long long) ndev->mw[i].bar_sz);
1386 if (!ndev->mw[i].vbase) {
1387 dev_warn(&pdev->dev, "Cannot remap BAR %d\n",
1388 MW_TO_BAR(i));
1389 rc = -EIO;
1390 goto err3;
1391 }
1392 }
1393
1394 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1395 if (rc) {
1396 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1397 if (rc)
1398 goto err3;
1399
1400 dev_warn(&pdev->dev, "Cannot DMA highmem\n");
1401 }
1402
1403 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1404 if (rc) {
1405 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1406 if (rc)
1407 goto err3;
1408
1409 dev_warn(&pdev->dev, "Cannot DMA consistent highmem\n");
1410 }
1411
1412 rc = ntb_device_setup(ndev);
1413 if (rc)
1414 goto err3;
1415
1416 rc = ntb_create_callbacks(ndev);
1417 if (rc)
1418 goto err4;
1419
1420 rc = ntb_setup_interrupts(ndev);
1421 if (rc)
1422 goto err5;
1423
1424 /* The scratchpad registers keep the values between rmmod/insmod,
1425 * blast them now
1426 */
1427 for (i = 0; i < ndev->limits.max_spads; i++) {
1428 ntb_write_local_spad(ndev, i, 0);
1429 ntb_write_remote_spad(ndev, i, 0);
1430 }
1431
1432 rc = ntb_transport_init(pdev);
1433 if (rc)
1434 goto err6;
1435
1436 ntb_hw_link_up(ndev);
1437
1438 return 0;
1439
1440 err6:
1441 ntb_free_interrupts(ndev);
1442 err5:
1443 ntb_free_callbacks(ndev);
1444 err4:
1445 ntb_device_free(ndev);
1446 err3:
1447 for (i--; i >= 0; i--)
1448 iounmap(ndev->mw[i].vbase);
1449 iounmap(ndev->reg_base);
1450 err2:
1451 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1452 err1:
1453 pci_disable_device(pdev);
1454 err:
1455 ntb_free_debugfs(ndev);
1456 kfree(ndev);
1457
1458 dev_err(&pdev->dev, "Error loading %s module\n", KBUILD_MODNAME);
1459 return rc;
1460 }
1461
1462 static void ntb_pci_remove(struct pci_dev *pdev)
1463 {
1464 struct ntb_device *ndev = pci_get_drvdata(pdev);
1465 int i;
1466
1467 ntb_hw_link_down(ndev);
1468
1469 ntb_transport_free(ndev->ntb_transport);
1470
1471 ntb_free_interrupts(ndev);
1472 ntb_free_callbacks(ndev);
1473 ntb_device_free(ndev);
1474
1475 for (i = 0; i < NTB_MAX_NUM_MW; i++)
1476 iounmap(ndev->mw[i].vbase);
1477
1478 iounmap(ndev->reg_base);
1479 pci_release_selected_regions(pdev, NTB_BAR_MASK);
1480 pci_disable_device(pdev);
1481 ntb_free_debugfs(ndev);
1482 kfree(ndev);
1483 }
1484
1485 static struct pci_driver ntb_pci_driver = {
1486 .name = KBUILD_MODNAME,
1487 .id_table = ntb_pci_tbl,
1488 .probe = ntb_pci_probe,
1489 .remove = ntb_pci_remove,
1490 };
1491 module_pci_driver(ntb_pci_driver);