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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 /*
22 Module: rt61pci
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
25 */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt61pci.h"
39
40 /*
41 * Allow hardware encryption to be disabled.
42 */
43 static int modparam_nohwcrypt = 0;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
47 /*
48 * Register access.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attempt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 */
58 #define WAIT_FOR_BBP(__dev, __reg) \
59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 #define WAIT_FOR_RF(__dev, __reg) \
61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 #define WAIT_FOR_MCU(__dev, __reg) \
63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 H2M_MAILBOX_CSR_OWNER, (__reg))
65
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67 const unsigned int word, const u8 value)
68 {
69 u32 reg;
70
71 mutex_lock(&rt2x00dev->csr_mutex);
72
73 /*
74 * Wait until the BBP becomes available, afterwards we
75 * can safely write the new data into the register.
76 */
77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 reg = 0;
79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
85 }
86
87 mutex_unlock(&rt2x00dev->csr_mutex);
88 }
89
90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
91 const unsigned int word, u8 *value)
92 {
93 u32 reg;
94
95 mutex_lock(&rt2x00dev->csr_mutex);
96
97 /*
98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
104 */
105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106 reg = 0;
107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
110
111 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
112
113 WAIT_FOR_BBP(rt2x00dev, &reg);
114 }
115
116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
117
118 mutex_unlock(&rt2x00dev->csr_mutex);
119 }
120
121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
122 const unsigned int word, const u32 value)
123 {
124 u32 reg;
125
126 mutex_lock(&rt2x00dev->csr_mutex);
127
128 /*
129 * Wait until the RF becomes available, afterwards we
130 * can safely write the new data into the register.
131 */
132 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133 reg = 0;
134 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
136 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
137 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
138
139 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
140 rt2x00_rf_write(rt2x00dev, word, value);
141 }
142
143 mutex_unlock(&rt2x00dev->csr_mutex);
144 }
145
146 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
147 const u8 command, const u8 token,
148 const u8 arg0, const u8 arg1)
149 {
150 u32 reg;
151
152 mutex_lock(&rt2x00dev->csr_mutex);
153
154 /*
155 * Wait until the MCU becomes available, afterwards we
156 * can safely write the new data into the register.
157 */
158 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
159 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
160 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
161 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
162 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
163 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
164
165 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
166 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
167 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
168 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
169 }
170
171 mutex_unlock(&rt2x00dev->csr_mutex);
172
173 }
174
175 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
176 {
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg;
179
180 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
181
182 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
183 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
184 eeprom->reg_data_clock =
185 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
186 eeprom->reg_chip_select =
187 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
188 }
189
190 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
191 {
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
193 u32 reg = 0;
194
195 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
196 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
197 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
198 !!eeprom->reg_data_clock);
199 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
200 !!eeprom->reg_chip_select);
201
202 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
203 }
204
205 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
206 static const struct rt2x00debug rt61pci_rt2x00debug = {
207 .owner = THIS_MODULE,
208 .csr = {
209 .read = rt2x00pci_register_read,
210 .write = rt2x00pci_register_write,
211 .flags = RT2X00DEBUGFS_OFFSET,
212 .word_base = CSR_REG_BASE,
213 .word_size = sizeof(u32),
214 .word_count = CSR_REG_SIZE / sizeof(u32),
215 },
216 .eeprom = {
217 .read = rt2x00_eeprom_read,
218 .write = rt2x00_eeprom_write,
219 .word_base = EEPROM_BASE,
220 .word_size = sizeof(u16),
221 .word_count = EEPROM_SIZE / sizeof(u16),
222 },
223 .bbp = {
224 .read = rt61pci_bbp_read,
225 .write = rt61pci_bbp_write,
226 .word_base = BBP_BASE,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt61pci_rf_write,
233 .word_base = RF_BASE,
234 .word_size = sizeof(u32),
235 .word_count = RF_SIZE / sizeof(u32),
236 },
237 };
238 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
239
240 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 {
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
245 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
246 }
247
248 #ifdef CONFIG_RT2X00_LIB_LEDS
249 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
250 enum led_brightness brightness)
251 {
252 struct rt2x00_led *led =
253 container_of(led_cdev, struct rt2x00_led, led_dev);
254 unsigned int enabled = brightness != LED_OFF;
255 unsigned int a_mode =
256 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
257 unsigned int bg_mode =
258 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
259
260 if (led->type == LED_TYPE_RADIO) {
261 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
262 MCU_LEDCS_RADIO_STATUS, enabled);
263
264 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
265 (led->rt2x00dev->led_mcu_reg & 0xff),
266 ((led->rt2x00dev->led_mcu_reg >> 8)));
267 } else if (led->type == LED_TYPE_ASSOC) {
268 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
269 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
270 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
271 MCU_LEDCS_LINK_A_STATUS, a_mode);
272
273 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
274 (led->rt2x00dev->led_mcu_reg & 0xff),
275 ((led->rt2x00dev->led_mcu_reg >> 8)));
276 } else if (led->type == LED_TYPE_QUALITY) {
277 /*
278 * The brightness is divided into 6 levels (0 - 5),
279 * this means we need to convert the brightness
280 * argument into the matching level within that range.
281 */
282 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
283 brightness / (LED_FULL / 6), 0);
284 }
285 }
286
287 static int rt61pci_blink_set(struct led_classdev *led_cdev,
288 unsigned long *delay_on,
289 unsigned long *delay_off)
290 {
291 struct rt2x00_led *led =
292 container_of(led_cdev, struct rt2x00_led, led_dev);
293 u32 reg;
294
295 rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
296 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
297 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
298 rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
299
300 return 0;
301 }
302
303 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
304 struct rt2x00_led *led,
305 enum led_type type)
306 {
307 led->rt2x00dev = rt2x00dev;
308 led->type = type;
309 led->led_dev.brightness_set = rt61pci_brightness_set;
310 led->led_dev.blink_set = rt61pci_blink_set;
311 led->flags = LED_INITIALIZED;
312 }
313 #endif /* CONFIG_RT2X00_LIB_LEDS */
314
315 /*
316 * Configuration handlers.
317 */
318 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
319 struct rt2x00lib_crypto *crypto,
320 struct ieee80211_key_conf *key)
321 {
322 struct hw_key_entry key_entry;
323 struct rt2x00_field32 field;
324 u32 mask;
325 u32 reg;
326
327 if (crypto->cmd == SET_KEY) {
328 /*
329 * rt2x00lib can't determine the correct free
330 * key_idx for shared keys. We have 1 register
331 * with key valid bits. The goal is simple, read
332 * the register, if that is full we have no slots
333 * left.
334 * Note that each BSS is allowed to have up to 4
335 * shared keys, so put a mask over the allowed
336 * entries.
337 */
338 mask = (0xf << crypto->bssidx);
339
340 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
341 reg &= mask;
342
343 if (reg && reg == mask)
344 return -ENOSPC;
345
346 key->hw_key_idx += reg ? ffz(reg) : 0;
347
348 /*
349 * Upload key to hardware
350 */
351 memcpy(key_entry.key, crypto->key,
352 sizeof(key_entry.key));
353 memcpy(key_entry.tx_mic, crypto->tx_mic,
354 sizeof(key_entry.tx_mic));
355 memcpy(key_entry.rx_mic, crypto->rx_mic,
356 sizeof(key_entry.rx_mic));
357
358 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
359 rt2x00pci_register_multiwrite(rt2x00dev, reg,
360 &key_entry, sizeof(key_entry));
361
362 /*
363 * The cipher types are stored over 2 registers.
364 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
365 * bssidx 1 and 2 keys are stored in SEC_CSR5.
366 * Using the correct defines correctly will cause overhead,
367 * so just calculate the correct offset.
368 */
369 if (key->hw_key_idx < 8) {
370 field.bit_offset = (3 * key->hw_key_idx);
371 field.bit_mask = 0x7 << field.bit_offset;
372
373 rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
374 rt2x00_set_field32(&reg, field, crypto->cipher);
375 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
376 } else {
377 field.bit_offset = (3 * (key->hw_key_idx - 8));
378 field.bit_mask = 0x7 << field.bit_offset;
379
380 rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
381 rt2x00_set_field32(&reg, field, crypto->cipher);
382 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
383 }
384
385 /*
386 * The driver does not support the IV/EIV generation
387 * in hardware. However it doesn't support the IV/EIV
388 * inside the ieee80211 frame either, but requires it
389 * to be provided separately for the descriptor.
390 * rt2x00lib will cut the IV/EIV data out of all frames
391 * given to us by mac80211, but we must tell mac80211
392 * to generate the IV/EIV data.
393 */
394 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
395 }
396
397 /*
398 * SEC_CSR0 contains only single-bit fields to indicate
399 * a particular key is valid. Because using the FIELD32()
400 * defines directly will cause a lot of overhead, we use
401 * a calculation to determine the correct bit directly.
402 */
403 mask = 1 << key->hw_key_idx;
404
405 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
406 if (crypto->cmd == SET_KEY)
407 reg |= mask;
408 else if (crypto->cmd == DISABLE_KEY)
409 reg &= ~mask;
410 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
411
412 return 0;
413 }
414
415 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
416 struct rt2x00lib_crypto *crypto,
417 struct ieee80211_key_conf *key)
418 {
419 struct hw_pairwise_ta_entry addr_entry;
420 struct hw_key_entry key_entry;
421 u32 mask;
422 u32 reg;
423
424 if (crypto->cmd == SET_KEY) {
425 /*
426 * rt2x00lib can't determine the correct free
427 * key_idx for pairwise keys. We have 2 registers
428 * with key valid bits. The goal is simple: read
429 * the first register. If that is full, move to
430 * the next register.
431 * When both registers are full, we drop the key.
432 * Otherwise, we use the first invalid entry.
433 */
434 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
435 if (reg && reg == ~0) {
436 key->hw_key_idx = 32;
437 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
438 if (reg && reg == ~0)
439 return -ENOSPC;
440 }
441
442 key->hw_key_idx += reg ? ffz(reg) : 0;
443
444 /*
445 * Upload key to hardware
446 */
447 memcpy(key_entry.key, crypto->key,
448 sizeof(key_entry.key));
449 memcpy(key_entry.tx_mic, crypto->tx_mic,
450 sizeof(key_entry.tx_mic));
451 memcpy(key_entry.rx_mic, crypto->rx_mic,
452 sizeof(key_entry.rx_mic));
453
454 memset(&addr_entry, 0, sizeof(addr_entry));
455 memcpy(&addr_entry, crypto->address, ETH_ALEN);
456 addr_entry.cipher = crypto->cipher;
457
458 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
459 rt2x00pci_register_multiwrite(rt2x00dev, reg,
460 &key_entry, sizeof(key_entry));
461
462 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
463 rt2x00pci_register_multiwrite(rt2x00dev, reg,
464 &addr_entry, sizeof(addr_entry));
465
466 /*
467 * Enable pairwise lookup table for given BSS idx.
468 * Without this, received frames will not be decrypted
469 * by the hardware.
470 */
471 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
472 reg |= (1 << crypto->bssidx);
473 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
474
475 /*
476 * The driver does not support the IV/EIV generation
477 * in hardware. However it doesn't support the IV/EIV
478 * inside the ieee80211 frame either, but requires it
479 * to be provided separately for the descriptor.
480 * rt2x00lib will cut the IV/EIV data out of all frames
481 * given to us by mac80211, but we must tell mac80211
482 * to generate the IV/EIV data.
483 */
484 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
485 }
486
487 /*
488 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
489 * a particular key is valid. Because using the FIELD32()
490 * defines directly will cause a lot of overhead, we use
491 * a calculation to determine the correct bit directly.
492 */
493 if (key->hw_key_idx < 32) {
494 mask = 1 << key->hw_key_idx;
495
496 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
497 if (crypto->cmd == SET_KEY)
498 reg |= mask;
499 else if (crypto->cmd == DISABLE_KEY)
500 reg &= ~mask;
501 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
502 } else {
503 mask = 1 << (key->hw_key_idx - 32);
504
505 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
506 if (crypto->cmd == SET_KEY)
507 reg |= mask;
508 else if (crypto->cmd == DISABLE_KEY)
509 reg &= ~mask;
510 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
511 }
512
513 return 0;
514 }
515
516 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
517 const unsigned int filter_flags)
518 {
519 u32 reg;
520
521 /*
522 * Start configuration steps.
523 * Note that the version error will always be dropped
524 * and broadcast frames will always be accepted since
525 * there is no filter for it at this time.
526 */
527 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
528 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
529 !(filter_flags & FIF_FCSFAIL));
530 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
531 !(filter_flags & FIF_PLCPFAIL));
532 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
533 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
534 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
535 !(filter_flags & FIF_PROMISC_IN_BSS));
536 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
537 !(filter_flags & FIF_PROMISC_IN_BSS) &&
538 !rt2x00dev->intf_ap_count);
539 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
540 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
541 !(filter_flags & FIF_ALLMULTI));
542 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
543 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
544 !(filter_flags & FIF_CONTROL));
545 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
546 }
547
548 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
549 struct rt2x00_intf *intf,
550 struct rt2x00intf_conf *conf,
551 const unsigned int flags)
552 {
553 unsigned int beacon_base;
554 u32 reg;
555
556 if (flags & CONFIG_UPDATE_TYPE) {
557 /*
558 * Clear current synchronisation setup.
559 * For the Beacon base registers, we only need to clear
560 * the first byte since that byte contains the VALID and OWNER
561 * bits which (when set to 0) will invalidate the entire beacon.
562 */
563 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
564 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
565
566 /*
567 * Enable synchronisation.
568 */
569 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
570 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
572 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
573 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
574 }
575
576 if (flags & CONFIG_UPDATE_MAC) {
577 reg = le32_to_cpu(conf->mac[1]);
578 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
579 conf->mac[1] = cpu_to_le32(reg);
580
581 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
582 conf->mac, sizeof(conf->mac));
583 }
584
585 if (flags & CONFIG_UPDATE_BSSID) {
586 reg = le32_to_cpu(conf->bssid[1]);
587 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
588 conf->bssid[1] = cpu_to_le32(reg);
589
590 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
591 conf->bssid, sizeof(conf->bssid));
592 }
593 }
594
595 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
596 struct rt2x00lib_erp *erp)
597 {
598 u32 reg;
599
600 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
601 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
602 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
603 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
604
605 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
606 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
607 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
608 !!erp->short_preamble);
609 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
610
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
612
613 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
614 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
615 erp->beacon_int * 16);
616 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
617
618 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
619 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
620 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
621
622 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
623 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
624 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
625 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
626 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
627 }
628
629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
630 struct antenna_setup *ant)
631 {
632 u8 r3;
633 u8 r4;
634 u8 r77;
635
636 rt61pci_bbp_read(rt2x00dev, 3, &r3);
637 rt61pci_bbp_read(rt2x00dev, 4, &r4);
638 rt61pci_bbp_read(rt2x00dev, 77, &r77);
639
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
641
642 /*
643 * Configure the RX antenna.
644 */
645 switch (ant->rx) {
646 case ANTENNA_HW_DIVERSITY:
647 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
648 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
649 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
650 break;
651 case ANTENNA_A:
652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
653 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
654 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
655 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
656 else
657 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
658 break;
659 case ANTENNA_B:
660 default:
661 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
662 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
663 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
664 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
665 else
666 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
667 break;
668 }
669
670 rt61pci_bbp_write(rt2x00dev, 77, r77);
671 rt61pci_bbp_write(rt2x00dev, 3, r3);
672 rt61pci_bbp_write(rt2x00dev, 4, r4);
673 }
674
675 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
676 struct antenna_setup *ant)
677 {
678 u8 r3;
679 u8 r4;
680 u8 r77;
681
682 rt61pci_bbp_read(rt2x00dev, 3, &r3);
683 rt61pci_bbp_read(rt2x00dev, 4, &r4);
684 rt61pci_bbp_read(rt2x00dev, 77, &r77);
685
686 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
687 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
688 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
689
690 /*
691 * Configure the RX antenna.
692 */
693 switch (ant->rx) {
694 case ANTENNA_HW_DIVERSITY:
695 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
696 break;
697 case ANTENNA_A:
698 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
699 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
700 break;
701 case ANTENNA_B:
702 default:
703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
704 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
705 break;
706 }
707
708 rt61pci_bbp_write(rt2x00dev, 77, r77);
709 rt61pci_bbp_write(rt2x00dev, 3, r3);
710 rt61pci_bbp_write(rt2x00dev, 4, r4);
711 }
712
713 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
714 const int p1, const int p2)
715 {
716 u32 reg;
717
718 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
719
720 rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
721 rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
722
723 rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
724 rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
725
726 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
727 }
728
729 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
730 struct antenna_setup *ant)
731 {
732 u8 r3;
733 u8 r4;
734 u8 r77;
735
736 rt61pci_bbp_read(rt2x00dev, 3, &r3);
737 rt61pci_bbp_read(rt2x00dev, 4, &r4);
738 rt61pci_bbp_read(rt2x00dev, 77, &r77);
739
740 /*
741 * Configure the RX antenna.
742 */
743 switch (ant->rx) {
744 case ANTENNA_A:
745 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
746 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
747 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
748 break;
749 case ANTENNA_HW_DIVERSITY:
750 /*
751 * FIXME: Antenna selection for the rf 2529 is very confusing
752 * in the legacy driver. Just default to antenna B until the
753 * legacy code can be properly translated into rt2x00 code.
754 */
755 case ANTENNA_B:
756 default:
757 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
758 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
759 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
760 break;
761 }
762
763 rt61pci_bbp_write(rt2x00dev, 77, r77);
764 rt61pci_bbp_write(rt2x00dev, 3, r3);
765 rt61pci_bbp_write(rt2x00dev, 4, r4);
766 }
767
768 struct antenna_sel {
769 u8 word;
770 /*
771 * value[0] -> non-LNA
772 * value[1] -> LNA
773 */
774 u8 value[2];
775 };
776
777 static const struct antenna_sel antenna_sel_a[] = {
778 { 96, { 0x58, 0x78 } },
779 { 104, { 0x38, 0x48 } },
780 { 75, { 0xfe, 0x80 } },
781 { 86, { 0xfe, 0x80 } },
782 { 88, { 0xfe, 0x80 } },
783 { 35, { 0x60, 0x60 } },
784 { 97, { 0x58, 0x58 } },
785 { 98, { 0x58, 0x58 } },
786 };
787
788 static const struct antenna_sel antenna_sel_bg[] = {
789 { 96, { 0x48, 0x68 } },
790 { 104, { 0x2c, 0x3c } },
791 { 75, { 0xfe, 0x80 } },
792 { 86, { 0xfe, 0x80 } },
793 { 88, { 0xfe, 0x80 } },
794 { 35, { 0x50, 0x50 } },
795 { 97, { 0x48, 0x48 } },
796 { 98, { 0x48, 0x48 } },
797 };
798
799 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
800 struct antenna_setup *ant)
801 {
802 const struct antenna_sel *sel;
803 unsigned int lna;
804 unsigned int i;
805 u32 reg;
806
807 /*
808 * We should never come here because rt2x00lib is supposed
809 * to catch this and send us the correct antenna explicitely.
810 */
811 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
812 ant->tx == ANTENNA_SW_DIVERSITY);
813
814 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
815 sel = antenna_sel_a;
816 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
817 } else {
818 sel = antenna_sel_bg;
819 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
820 }
821
822 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
823 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
824
825 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
826
827 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
828 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
829 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
830 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
831
832 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
833
834 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
835 rt61pci_config_antenna_5x(rt2x00dev, ant);
836 else if (rt2x00_rf(rt2x00dev, RF2527))
837 rt61pci_config_antenna_2x(rt2x00dev, ant);
838 else if (rt2x00_rf(rt2x00dev, RF2529)) {
839 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
840 rt61pci_config_antenna_2x(rt2x00dev, ant);
841 else
842 rt61pci_config_antenna_2529(rt2x00dev, ant);
843 }
844 }
845
846 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
847 struct rt2x00lib_conf *libconf)
848 {
849 u16 eeprom;
850 short lna_gain = 0;
851
852 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
853 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
854 lna_gain += 14;
855
856 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
857 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
858 } else {
859 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
860 lna_gain += 14;
861
862 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
863 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
864 }
865
866 rt2x00dev->lna_gain = lna_gain;
867 }
868
869 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
870 struct rf_channel *rf, const int txpower)
871 {
872 u8 r3;
873 u8 r94;
874 u8 smart;
875
876 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
877 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
878
879 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
880
881 rt61pci_bbp_read(rt2x00dev, 3, &r3);
882 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
883 rt61pci_bbp_write(rt2x00dev, 3, r3);
884
885 r94 = 6;
886 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
887 r94 += txpower - MAX_TXPOWER;
888 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
889 r94 += txpower;
890 rt61pci_bbp_write(rt2x00dev, 94, r94);
891
892 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
893 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
894 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
895 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
896
897 udelay(200);
898
899 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
900 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
901 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
902 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
903
904 udelay(200);
905
906 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
907 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
908 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
909 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
910
911 msleep(1);
912 }
913
914 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
915 const int txpower)
916 {
917 struct rf_channel rf;
918
919 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
920 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
921 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
922 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
923
924 rt61pci_config_channel(rt2x00dev, &rf, txpower);
925 }
926
927 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
928 struct rt2x00lib_conf *libconf)
929 {
930 u32 reg;
931
932 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
933 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
934 libconf->conf->long_frame_max_tx_count);
935 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
936 libconf->conf->short_frame_max_tx_count);
937 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
938 }
939
940 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
941 struct rt2x00lib_conf *libconf)
942 {
943 enum dev_state state =
944 (libconf->conf->flags & IEEE80211_CONF_PS) ?
945 STATE_SLEEP : STATE_AWAKE;
946 u32 reg;
947
948 if (state == STATE_SLEEP) {
949 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
950 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
951 rt2x00dev->beacon_int - 10);
952 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
953 libconf->conf->listen_interval - 1);
954 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
955
956 /* We must first disable autowake before it can be enabled */
957 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
958 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
959
960 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
961 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
962
963 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
964 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
965 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
966
967 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
968 } else {
969 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
970 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
971 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
972 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
973 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
974 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
975
976 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
977 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
978 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
979
980 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
981 }
982 }
983
984 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
985 struct rt2x00lib_conf *libconf,
986 const unsigned int flags)
987 {
988 /* Always recalculate LNA gain before changing configuration */
989 rt61pci_config_lna_gain(rt2x00dev, libconf);
990
991 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
992 rt61pci_config_channel(rt2x00dev, &libconf->rf,
993 libconf->conf->power_level);
994 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
995 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
996 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
997 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
998 rt61pci_config_retry_limit(rt2x00dev, libconf);
999 if (flags & IEEE80211_CONF_CHANGE_PS)
1000 rt61pci_config_ps(rt2x00dev, libconf);
1001 }
1002
1003 /*
1004 * Link tuning
1005 */
1006 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1007 struct link_qual *qual)
1008 {
1009 u32 reg;
1010
1011 /*
1012 * Update FCS error count from register.
1013 */
1014 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1015 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1016
1017 /*
1018 * Update False CCA count from register.
1019 */
1020 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1021 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1022 }
1023
1024 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1025 struct link_qual *qual, u8 vgc_level)
1026 {
1027 if (qual->vgc_level != vgc_level) {
1028 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1029 qual->vgc_level = vgc_level;
1030 qual->vgc_level_reg = vgc_level;
1031 }
1032 }
1033
1034 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1035 struct link_qual *qual)
1036 {
1037 rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1038 }
1039
1040 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1041 struct link_qual *qual, const u32 count)
1042 {
1043 u8 up_bound;
1044 u8 low_bound;
1045
1046 /*
1047 * Determine r17 bounds.
1048 */
1049 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1050 low_bound = 0x28;
1051 up_bound = 0x48;
1052 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1053 low_bound += 0x10;
1054 up_bound += 0x10;
1055 }
1056 } else {
1057 low_bound = 0x20;
1058 up_bound = 0x40;
1059 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1060 low_bound += 0x10;
1061 up_bound += 0x10;
1062 }
1063 }
1064
1065 /*
1066 * If we are not associated, we should go straight to the
1067 * dynamic CCA tuning.
1068 */
1069 if (!rt2x00dev->intf_associated)
1070 goto dynamic_cca_tune;
1071
1072 /*
1073 * Special big-R17 for very short distance
1074 */
1075 if (qual->rssi >= -35) {
1076 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1077 return;
1078 }
1079
1080 /*
1081 * Special big-R17 for short distance
1082 */
1083 if (qual->rssi >= -58) {
1084 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1085 return;
1086 }
1087
1088 /*
1089 * Special big-R17 for middle-short distance
1090 */
1091 if (qual->rssi >= -66) {
1092 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1093 return;
1094 }
1095
1096 /*
1097 * Special mid-R17 for middle distance
1098 */
1099 if (qual->rssi >= -74) {
1100 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1101 return;
1102 }
1103
1104 /*
1105 * Special case: Change up_bound based on the rssi.
1106 * Lower up_bound when rssi is weaker then -74 dBm.
1107 */
1108 up_bound -= 2 * (-74 - qual->rssi);
1109 if (low_bound > up_bound)
1110 up_bound = low_bound;
1111
1112 if (qual->vgc_level > up_bound) {
1113 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1114 return;
1115 }
1116
1117 dynamic_cca_tune:
1118
1119 /*
1120 * r17 does not yet exceed upper limit, continue and base
1121 * the r17 tuning on the false CCA count.
1122 */
1123 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1124 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1125 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1126 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1127 }
1128
1129 /*
1130 * Firmware functions
1131 */
1132 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1133 {
1134 u16 chip;
1135 char *fw_name;
1136
1137 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1138 switch (chip) {
1139 case RT2561_PCI_ID:
1140 fw_name = FIRMWARE_RT2561;
1141 break;
1142 case RT2561s_PCI_ID:
1143 fw_name = FIRMWARE_RT2561s;
1144 break;
1145 case RT2661_PCI_ID:
1146 fw_name = FIRMWARE_RT2661;
1147 break;
1148 default:
1149 fw_name = NULL;
1150 break;
1151 }
1152
1153 return fw_name;
1154 }
1155
1156 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1157 const u8 *data, const size_t len)
1158 {
1159 u16 fw_crc;
1160 u16 crc;
1161
1162 /*
1163 * Only support 8kb firmware files.
1164 */
1165 if (len != 8192)
1166 return FW_BAD_LENGTH;
1167
1168 /*
1169 * The last 2 bytes in the firmware array are the crc checksum itself.
1170 * This means that we should never pass those 2 bytes to the crc
1171 * algorithm.
1172 */
1173 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1174
1175 /*
1176 * Use the crc itu-t algorithm.
1177 */
1178 crc = crc_itu_t(0, data, len - 2);
1179 crc = crc_itu_t_byte(crc, 0);
1180 crc = crc_itu_t_byte(crc, 0);
1181
1182 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1183 }
1184
1185 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1186 const u8 *data, const size_t len)
1187 {
1188 int i;
1189 u32 reg;
1190
1191 /*
1192 * Wait for stable hardware.
1193 */
1194 for (i = 0; i < 100; i++) {
1195 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1196 if (reg)
1197 break;
1198 msleep(1);
1199 }
1200
1201 if (!reg) {
1202 ERROR(rt2x00dev, "Unstable hardware.\n");
1203 return -EBUSY;
1204 }
1205
1206 /*
1207 * Prepare MCU and mailbox for firmware loading.
1208 */
1209 reg = 0;
1210 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1211 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1212 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1213 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1214 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1215
1216 /*
1217 * Write firmware to device.
1218 */
1219 reg = 0;
1220 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1221 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1222 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1223
1224 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1225 data, len);
1226
1227 rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1228 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1229
1230 rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1231 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1232
1233 for (i = 0; i < 100; i++) {
1234 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1235 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1236 break;
1237 msleep(1);
1238 }
1239
1240 if (i == 100) {
1241 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1242 return -EBUSY;
1243 }
1244
1245 /*
1246 * Hardware needs another millisecond before it is ready.
1247 */
1248 msleep(1);
1249
1250 /*
1251 * Reset MAC and BBP registers.
1252 */
1253 reg = 0;
1254 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1255 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1256 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1257
1258 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1259 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1260 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1261 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1262
1263 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1264 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1265 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1266
1267 return 0;
1268 }
1269
1270 /*
1271 * Initialization functions.
1272 */
1273 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1274 {
1275 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1276 u32 word;
1277
1278 if (entry->queue->qid == QID_RX) {
1279 rt2x00_desc_read(entry_priv->desc, 0, &word);
1280
1281 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1282 } else {
1283 rt2x00_desc_read(entry_priv->desc, 0, &word);
1284
1285 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1286 rt2x00_get_field32(word, TXD_W0_VALID));
1287 }
1288 }
1289
1290 static void rt61pci_clear_entry(struct queue_entry *entry)
1291 {
1292 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1293 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1294 u32 word;
1295
1296 if (entry->queue->qid == QID_RX) {
1297 rt2x00_desc_read(entry_priv->desc, 5, &word);
1298 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1299 skbdesc->skb_dma);
1300 rt2x00_desc_write(entry_priv->desc, 5, word);
1301
1302 rt2x00_desc_read(entry_priv->desc, 0, &word);
1303 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1304 rt2x00_desc_write(entry_priv->desc, 0, word);
1305 } else {
1306 rt2x00_desc_read(entry_priv->desc, 0, &word);
1307 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1308 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1309 rt2x00_desc_write(entry_priv->desc, 0, word);
1310 }
1311 }
1312
1313 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1314 {
1315 struct queue_entry_priv_pci *entry_priv;
1316 u32 reg;
1317
1318 /*
1319 * Initialize registers.
1320 */
1321 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1322 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1323 rt2x00dev->tx[0].limit);
1324 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1325 rt2x00dev->tx[1].limit);
1326 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1327 rt2x00dev->tx[2].limit);
1328 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1329 rt2x00dev->tx[3].limit);
1330 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1331
1332 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1333 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1334 rt2x00dev->tx[0].desc_size / 4);
1335 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1336
1337 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1338 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1339 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1340 entry_priv->desc_dma);
1341 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1342
1343 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1344 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1345 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1346 entry_priv->desc_dma);
1347 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1348
1349 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1350 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1351 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1352 entry_priv->desc_dma);
1353 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1354
1355 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1356 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1357 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1358 entry_priv->desc_dma);
1359 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1360
1361 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1362 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1363 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1364 rt2x00dev->rx->desc_size / 4);
1365 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1366 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1367
1368 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1369 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1370 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1371 entry_priv->desc_dma);
1372 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1373
1374 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1375 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1376 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1377 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1378 rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1379 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1380
1381 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1382 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1383 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1384 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1385 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1386 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1387
1388 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1389 rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1390 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1391
1392 return 0;
1393 }
1394
1395 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1396 {
1397 u32 reg;
1398
1399 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1400 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1401 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1402 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1403 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1404
1405 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1406 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1407 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1408 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1409 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1410 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1411 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1412 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1413 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1414 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1415
1416 /*
1417 * CCK TXD BBP registers
1418 */
1419 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1420 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1421 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1422 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1423 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1424 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1425 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1426 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1427 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1428 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1429
1430 /*
1431 * OFDM TXD BBP registers
1432 */
1433 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1434 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1435 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1436 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1437 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1438 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1439 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1440 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1441
1442 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1443 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1444 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1445 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1446 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1447 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1448
1449 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1450 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1451 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1452 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1453 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1454 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1455
1456 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1457 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1458 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1459 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1460 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1461 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1462 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1463 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1464
1465 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1466
1467 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1468
1469 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1470 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1471 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1472
1473 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1474
1475 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1476 return -EBUSY;
1477
1478 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1479
1480 /*
1481 * Invalidate all Shared Keys (SEC_CSR0),
1482 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1483 */
1484 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1485 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1486 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1487
1488 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1489 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1490 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1491 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1492
1493 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1494
1495 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1496
1497 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1498
1499 /*
1500 * Clear all beacons
1501 * For the Beacon base registers we only need to clear
1502 * the first byte since that byte contains the VALID and OWNER
1503 * bits which (when set to 0) will invalidate the entire beacon.
1504 */
1505 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1506 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1507 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1508 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1509
1510 /*
1511 * We must clear the error counters.
1512 * These registers are cleared on read,
1513 * so we may pass a useless variable to store the value.
1514 */
1515 rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1516 rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1517 rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1518
1519 /*
1520 * Reset MAC and BBP registers.
1521 */
1522 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1523 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1524 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1525 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1526
1527 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1528 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1529 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1530 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1531
1532 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1533 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1534 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1535
1536 return 0;
1537 }
1538
1539 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1540 {
1541 unsigned int i;
1542 u8 value;
1543
1544 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1545 rt61pci_bbp_read(rt2x00dev, 0, &value);
1546 if ((value != 0xff) && (value != 0x00))
1547 return 0;
1548 udelay(REGISTER_BUSY_DELAY);
1549 }
1550
1551 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1552 return -EACCES;
1553 }
1554
1555 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1556 {
1557 unsigned int i;
1558 u16 eeprom;
1559 u8 reg_id;
1560 u8 value;
1561
1562 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1563 return -EACCES;
1564
1565 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1566 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1567 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1568 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1569 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1570 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1571 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1572 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1573 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1574 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1575 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1576 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1577 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1578 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1579 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1580 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1581 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1582 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1583 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1584 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1585 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1586 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1587 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1588 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1589
1590 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1592
1593 if (eeprom != 0xffff && eeprom != 0x0000) {
1594 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1595 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1596 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1597 }
1598 }
1599
1600 return 0;
1601 }
1602
1603 /*
1604 * Device state switch handlers.
1605 */
1606 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1607 enum dev_state state)
1608 {
1609 u32 reg;
1610
1611 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1612 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1613 (state == STATE_RADIO_RX_OFF) ||
1614 (state == STATE_RADIO_RX_OFF_LINK));
1615 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1616 }
1617
1618 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1619 enum dev_state state)
1620 {
1621 int mask = (state == STATE_RADIO_IRQ_OFF);
1622 u32 reg;
1623
1624 /*
1625 * When interrupts are being enabled, the interrupt registers
1626 * should clear the register to assure a clean state.
1627 */
1628 if (state == STATE_RADIO_IRQ_ON) {
1629 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1630 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1631
1632 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1633 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1634 }
1635
1636 /*
1637 * Only toggle the interrupts bits we are going to use.
1638 * Non-checked interrupt bits are disabled by default.
1639 */
1640 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1641 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1642 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1643 rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1644 rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1645 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1646
1647 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1648 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1649 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1650 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1651 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1652 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1653 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1654 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1655 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1656 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1657 }
1658
1659 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1660 {
1661 u32 reg;
1662
1663 /*
1664 * Initialize all registers.
1665 */
1666 if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1667 rt61pci_init_registers(rt2x00dev) ||
1668 rt61pci_init_bbp(rt2x00dev)))
1669 return -EIO;
1670
1671 /*
1672 * Enable RX.
1673 */
1674 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1675 rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1676 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1677
1678 return 0;
1679 }
1680
1681 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1682 {
1683 /*
1684 * Disable power
1685 */
1686 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1687 }
1688
1689 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1690 {
1691 u32 reg;
1692 unsigned int i;
1693 char put_to_sleep;
1694
1695 put_to_sleep = (state != STATE_AWAKE);
1696
1697 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1698 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1699 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1700 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1701
1702 /*
1703 * Device is not guaranteed to be in the requested state yet.
1704 * We must wait until the register indicates that the
1705 * device has entered the correct state.
1706 */
1707 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1708 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1709 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1710 if (state == !put_to_sleep)
1711 return 0;
1712 msleep(10);
1713 }
1714
1715 return -EBUSY;
1716 }
1717
1718 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1719 enum dev_state state)
1720 {
1721 int retval = 0;
1722
1723 switch (state) {
1724 case STATE_RADIO_ON:
1725 retval = rt61pci_enable_radio(rt2x00dev);
1726 break;
1727 case STATE_RADIO_OFF:
1728 rt61pci_disable_radio(rt2x00dev);
1729 break;
1730 case STATE_RADIO_RX_ON:
1731 case STATE_RADIO_RX_ON_LINK:
1732 case STATE_RADIO_RX_OFF:
1733 case STATE_RADIO_RX_OFF_LINK:
1734 rt61pci_toggle_rx(rt2x00dev, state);
1735 break;
1736 case STATE_RADIO_IRQ_ON:
1737 case STATE_RADIO_IRQ_OFF:
1738 rt61pci_toggle_irq(rt2x00dev, state);
1739 break;
1740 case STATE_DEEP_SLEEP:
1741 case STATE_SLEEP:
1742 case STATE_STANDBY:
1743 case STATE_AWAKE:
1744 retval = rt61pci_set_state(rt2x00dev, state);
1745 break;
1746 default:
1747 retval = -ENOTSUPP;
1748 break;
1749 }
1750
1751 if (unlikely(retval))
1752 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1753 state, retval);
1754
1755 return retval;
1756 }
1757
1758 /*
1759 * TX descriptor initialization
1760 */
1761 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1762 struct sk_buff *skb,
1763 struct txentry_desc *txdesc)
1764 {
1765 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1766 __le32 *txd = skbdesc->desc;
1767 u32 word;
1768
1769 /*
1770 * Start writing the descriptor words.
1771 */
1772 rt2x00_desc_read(txd, 1, &word);
1773 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1774 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1775 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1776 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1777 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1778 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1779 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1780 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1781 rt2x00_desc_write(txd, 1, word);
1782
1783 rt2x00_desc_read(txd, 2, &word);
1784 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1785 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1786 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1787 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1788 rt2x00_desc_write(txd, 2, word);
1789
1790 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1791 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1792 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1793 }
1794
1795 rt2x00_desc_read(txd, 5, &word);
1796 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1797 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1798 skbdesc->entry->entry_idx);
1799 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1800 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1801 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1802 rt2x00_desc_write(txd, 5, word);
1803
1804 rt2x00_desc_read(txd, 6, &word);
1805 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1806 skbdesc->skb_dma);
1807 rt2x00_desc_write(txd, 6, word);
1808
1809 if (skbdesc->desc_len > TXINFO_SIZE) {
1810 rt2x00_desc_read(txd, 11, &word);
1811 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1812 rt2x00_desc_write(txd, 11, word);
1813 }
1814
1815 rt2x00_desc_read(txd, 0, &word);
1816 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1817 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1818 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1819 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1820 rt2x00_set_field32(&word, TXD_W0_ACK,
1821 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1822 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1823 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1824 rt2x00_set_field32(&word, TXD_W0_OFDM,
1825 (txdesc->rate_mode == RATE_MODE_OFDM));
1826 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1827 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1828 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1829 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1830 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1831 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1832 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1833 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1834 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1835 rt2x00_set_field32(&word, TXD_W0_BURST,
1836 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1837 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1838 rt2x00_desc_write(txd, 0, word);
1839 }
1840
1841 /*
1842 * TX data initialization
1843 */
1844 static void rt61pci_write_beacon(struct queue_entry *entry)
1845 {
1846 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1847 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1848 unsigned int beacon_base;
1849 u32 reg;
1850
1851 /*
1852 * Disable beaconing while we are reloading the beacon data,
1853 * otherwise we might be sending out invalid data.
1854 */
1855 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1856 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1857 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1858
1859 /*
1860 * Write entire beacon with descriptor to register.
1861 */
1862 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1863 rt2x00pci_register_multiwrite(rt2x00dev,
1864 beacon_base,
1865 skbdesc->desc, skbdesc->desc_len);
1866 rt2x00pci_register_multiwrite(rt2x00dev,
1867 beacon_base + skbdesc->desc_len,
1868 entry->skb->data, entry->skb->len);
1869
1870 /*
1871 * Clean up beacon skb.
1872 */
1873 dev_kfree_skb_any(entry->skb);
1874 entry->skb = NULL;
1875 }
1876
1877 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1878 const enum data_queue_qid queue)
1879 {
1880 u32 reg;
1881
1882 if (queue == QID_BEACON) {
1883 /*
1884 * For Wi-Fi faily generated beacons between participating
1885 * stations. Set TBTT phase adaptive adjustment step to 8us.
1886 */
1887 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1888
1889 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1890 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1891 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1892 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1893 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1894 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1895 }
1896 return;
1897 }
1898
1899 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1900 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1901 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1902 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1903 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1904 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1905 }
1906
1907 static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1908 const enum data_queue_qid qid)
1909 {
1910 u32 reg;
1911
1912 if (qid == QID_BEACON) {
1913 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1914 return;
1915 }
1916
1917 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1918 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
1919 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
1920 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
1921 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
1922 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1923 }
1924
1925 /*
1926 * RX control handlers
1927 */
1928 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1929 {
1930 u8 offset = rt2x00dev->lna_gain;
1931 u8 lna;
1932
1933 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1934 switch (lna) {
1935 case 3:
1936 offset += 90;
1937 break;
1938 case 2:
1939 offset += 74;
1940 break;
1941 case 1:
1942 offset += 64;
1943 break;
1944 default:
1945 return 0;
1946 }
1947
1948 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1949 if (lna == 3 || lna == 2)
1950 offset += 10;
1951 }
1952
1953 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1954 }
1955
1956 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1957 struct rxdone_entry_desc *rxdesc)
1958 {
1959 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1960 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1961 u32 word0;
1962 u32 word1;
1963
1964 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1965 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1966
1967 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1968 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1969
1970 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1971 rxdesc->cipher =
1972 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1973 rxdesc->cipher_status =
1974 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1975 }
1976
1977 if (rxdesc->cipher != CIPHER_NONE) {
1978 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1979 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1980 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1981
1982 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1983 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1984
1985 /*
1986 * Hardware has stripped IV/EIV data from 802.11 frame during
1987 * decryption. It has provided the data separately but rt2x00lib
1988 * should decide if it should be reinserted.
1989 */
1990 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1991
1992 /*
1993 * FIXME: Legacy driver indicates that the frame does
1994 * contain the Michael Mic. Unfortunately, in rt2x00
1995 * the MIC seems to be missing completely...
1996 */
1997 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1998
1999 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2000 rxdesc->flags |= RX_FLAG_DECRYPTED;
2001 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2002 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2003 }
2004
2005 /*
2006 * Obtain the status about this packet.
2007 * When frame was received with an OFDM bitrate,
2008 * the signal is the PLCP value. If it was received with
2009 * a CCK bitrate the signal is the rate in 100kbit/s.
2010 */
2011 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2012 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2013 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2014
2015 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2016 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2017 else
2018 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2019 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2020 rxdesc->dev_flags |= RXDONE_MY_BSS;
2021 }
2022
2023 /*
2024 * Interrupt functions.
2025 */
2026 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2027 {
2028 struct data_queue *queue;
2029 struct queue_entry *entry;
2030 struct queue_entry *entry_done;
2031 struct queue_entry_priv_pci *entry_priv;
2032 struct txdone_entry_desc txdesc;
2033 u32 word;
2034 u32 reg;
2035 u32 old_reg;
2036 int type;
2037 int index;
2038
2039 /*
2040 * During each loop we will compare the freshly read
2041 * STA_CSR4 register value with the value read from
2042 * the previous loop. If the 2 values are equal then
2043 * we should stop processing because the chance is
2044 * quite big that the device has been unplugged and
2045 * we risk going into an endless loop.
2046 */
2047 old_reg = 0;
2048
2049 while (1) {
2050 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2051 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2052 break;
2053
2054 if (old_reg == reg)
2055 break;
2056 old_reg = reg;
2057
2058 /*
2059 * Skip this entry when it contains an invalid
2060 * queue identication number.
2061 */
2062 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2063 queue = rt2x00queue_get_queue(rt2x00dev, type);
2064 if (unlikely(!queue))
2065 continue;
2066
2067 /*
2068 * Skip this entry when it contains an invalid
2069 * index number.
2070 */
2071 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2072 if (unlikely(index >= queue->limit))
2073 continue;
2074
2075 entry = &queue->entries[index];
2076 entry_priv = entry->priv_data;
2077 rt2x00_desc_read(entry_priv->desc, 0, &word);
2078
2079 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2080 !rt2x00_get_field32(word, TXD_W0_VALID))
2081 return;
2082
2083 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2084 while (entry != entry_done) {
2085 /* Catch up.
2086 * Just report any entries we missed as failed.
2087 */
2088 WARNING(rt2x00dev,
2089 "TX status report missed for entry %d\n",
2090 entry_done->entry_idx);
2091
2092 txdesc.flags = 0;
2093 __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2094 txdesc.retry = 0;
2095
2096 rt2x00lib_txdone(entry_done, &txdesc);
2097 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2098 }
2099
2100 /*
2101 * Obtain the status about this packet.
2102 */
2103 txdesc.flags = 0;
2104 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2105 case 0: /* Success, maybe with retry */
2106 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2107 break;
2108 case 6: /* Failure, excessive retries */
2109 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2110 /* Don't break, this is a failed frame! */
2111 default: /* Failure */
2112 __set_bit(TXDONE_FAILURE, &txdesc.flags);
2113 }
2114 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2115
2116 rt2x00lib_txdone(entry, &txdesc);
2117 }
2118 }
2119
2120 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2121 {
2122 struct rt2x00_dev *rt2x00dev = dev_instance;
2123 u32 reg_mcu;
2124 u32 reg;
2125
2126 /*
2127 * Get the interrupt sources & saved to local variable.
2128 * Write register value back to clear pending interrupts.
2129 */
2130 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2131 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2132
2133 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2134 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2135
2136 if (!reg && !reg_mcu)
2137 return IRQ_NONE;
2138
2139 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2140 return IRQ_HANDLED;
2141
2142 /*
2143 * Handle interrupts, walk through all bits
2144 * and run the tasks, the bits are checked in order of
2145 * priority.
2146 */
2147
2148 /*
2149 * 1 - Rx ring done interrupt.
2150 */
2151 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2152 rt2x00pci_rxdone(rt2x00dev);
2153
2154 /*
2155 * 2 - Tx ring done interrupt.
2156 */
2157 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2158 rt61pci_txdone(rt2x00dev);
2159
2160 /*
2161 * 3 - Handle MCU command done.
2162 */
2163 if (reg_mcu)
2164 rt2x00pci_register_write(rt2x00dev,
2165 M2H_CMD_DONE_CSR, 0xffffffff);
2166
2167 return IRQ_HANDLED;
2168 }
2169
2170 /*
2171 * Device probe functions.
2172 */
2173 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2174 {
2175 struct eeprom_93cx6 eeprom;
2176 u32 reg;
2177 u16 word;
2178 u8 *mac;
2179 s8 value;
2180
2181 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2182
2183 eeprom.data = rt2x00dev;
2184 eeprom.register_read = rt61pci_eepromregister_read;
2185 eeprom.register_write = rt61pci_eepromregister_write;
2186 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2187 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2188 eeprom.reg_data_in = 0;
2189 eeprom.reg_data_out = 0;
2190 eeprom.reg_data_clock = 0;
2191 eeprom.reg_chip_select = 0;
2192
2193 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2194 EEPROM_SIZE / sizeof(u16));
2195
2196 /*
2197 * Start validation of the data that has been read.
2198 */
2199 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2200 if (!is_valid_ether_addr(mac)) {
2201 random_ether_addr(mac);
2202 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2203 }
2204
2205 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2206 if (word == 0xffff) {
2207 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2208 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2209 ANTENNA_B);
2210 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2211 ANTENNA_B);
2212 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2213 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2214 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2215 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2216 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2217 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2218 }
2219
2220 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2221 if (word == 0xffff) {
2222 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2223 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2224 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2225 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2226 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2227 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2228 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2229 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2230 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2231 }
2232
2233 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2234 if (word == 0xffff) {
2235 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2236 LED_MODE_DEFAULT);
2237 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2238 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2239 }
2240
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2242 if (word == 0xffff) {
2243 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2244 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2245 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2246 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2247 }
2248
2249 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2250 if (word == 0xffff) {
2251 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2252 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2253 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2254 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2255 } else {
2256 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2257 if (value < -10 || value > 10)
2258 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2259 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2260 if (value < -10 || value > 10)
2261 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2262 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2263 }
2264
2265 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2266 if (word == 0xffff) {
2267 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2268 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2269 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2270 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2271 } else {
2272 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2273 if (value < -10 || value > 10)
2274 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2275 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2276 if (value < -10 || value > 10)
2277 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2278 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2279 }
2280
2281 return 0;
2282 }
2283
2284 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2285 {
2286 u32 reg;
2287 u16 value;
2288 u16 eeprom;
2289
2290 /*
2291 * Read EEPROM word for configuration.
2292 */
2293 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2294
2295 /*
2296 * Identify RF chipset.
2297 */
2298 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2299 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2300 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2301 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2302
2303 if (!rt2x00_rf(rt2x00dev, RF5225) &&
2304 !rt2x00_rf(rt2x00dev, RF5325) &&
2305 !rt2x00_rf(rt2x00dev, RF2527) &&
2306 !rt2x00_rf(rt2x00dev, RF2529)) {
2307 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2308 return -ENODEV;
2309 }
2310
2311 /*
2312 * Determine number of antennas.
2313 */
2314 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2315 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2316
2317 /*
2318 * Identify default antenna configuration.
2319 */
2320 rt2x00dev->default_ant.tx =
2321 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2322 rt2x00dev->default_ant.rx =
2323 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2324
2325 /*
2326 * Read the Frame type.
2327 */
2328 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2329 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2330
2331 /*
2332 * Detect if this device has a hardware controlled radio.
2333 */
2334 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2335 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2336
2337 /*
2338 * Read frequency offset and RF programming sequence.
2339 */
2340 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2341 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2342 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2343
2344 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2345
2346 /*
2347 * Read external LNA informations.
2348 */
2349 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2350
2351 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2352 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2353 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2354 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2355
2356 /*
2357 * When working with a RF2529 chip without double antenna,
2358 * the antenna settings should be gathered from the NIC
2359 * eeprom word.
2360 */
2361 if (rt2x00_rf(rt2x00dev, RF2529) &&
2362 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2363 rt2x00dev->default_ant.rx =
2364 ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2365 rt2x00dev->default_ant.tx =
2366 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2367
2368 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2369 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2370 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2371 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2372 }
2373
2374 /*
2375 * Store led settings, for correct led behaviour.
2376 * If the eeprom value is invalid,
2377 * switch to default led mode.
2378 */
2379 #ifdef CONFIG_RT2X00_LIB_LEDS
2380 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2381 value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2382
2383 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2384 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2385 if (value == LED_MODE_SIGNAL_STRENGTH)
2386 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2387 LED_TYPE_QUALITY);
2388
2389 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2390 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2391 rt2x00_get_field16(eeprom,
2392 EEPROM_LED_POLARITY_GPIO_0));
2393 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2394 rt2x00_get_field16(eeprom,
2395 EEPROM_LED_POLARITY_GPIO_1));
2396 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2397 rt2x00_get_field16(eeprom,
2398 EEPROM_LED_POLARITY_GPIO_2));
2399 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2400 rt2x00_get_field16(eeprom,
2401 EEPROM_LED_POLARITY_GPIO_3));
2402 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2403 rt2x00_get_field16(eeprom,
2404 EEPROM_LED_POLARITY_GPIO_4));
2405 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2406 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2407 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2408 rt2x00_get_field16(eeprom,
2409 EEPROM_LED_POLARITY_RDY_G));
2410 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2411 rt2x00_get_field16(eeprom,
2412 EEPROM_LED_POLARITY_RDY_A));
2413 #endif /* CONFIG_RT2X00_LIB_LEDS */
2414
2415 return 0;
2416 }
2417
2418 /*
2419 * RF value list for RF5225 & RF5325
2420 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2421 */
2422 static const struct rf_channel rf_vals_noseq[] = {
2423 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2424 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2425 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2426 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2427 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2428 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2429 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2430 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2431 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2432 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2433 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2434 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2435 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2436 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2437
2438 /* 802.11 UNI / HyperLan 2 */
2439 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2440 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2441 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2442 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2443 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2444 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2445 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2446 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2447
2448 /* 802.11 HyperLan 2 */
2449 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2450 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2451 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2452 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2453 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2454 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2455 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2456 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2457 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2458 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2459
2460 /* 802.11 UNII */
2461 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2462 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2463 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2464 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2465 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2466 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2467
2468 /* MMAC(Japan)J52 ch 34,38,42,46 */
2469 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2470 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2471 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2472 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2473 };
2474
2475 /*
2476 * RF value list for RF5225 & RF5325
2477 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2478 */
2479 static const struct rf_channel rf_vals_seq[] = {
2480 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2481 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2482 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2483 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2484 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2485 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2486 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2487 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2488 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2489 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2490 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2491 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2492 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2493 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2494
2495 /* 802.11 UNI / HyperLan 2 */
2496 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2497 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2498 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2499 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2500 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2501 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2502 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2503 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2504
2505 /* 802.11 HyperLan 2 */
2506 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2507 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2508 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2509 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2510 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2511 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2512 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2513 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2514 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2515 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2516
2517 /* 802.11 UNII */
2518 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2519 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2520 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2521 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2522 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2523 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2524
2525 /* MMAC(Japan)J52 ch 34,38,42,46 */
2526 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2527 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2528 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2529 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2530 };
2531
2532 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2533 {
2534 struct hw_mode_spec *spec = &rt2x00dev->spec;
2535 struct channel_info *info;
2536 char *tx_power;
2537 unsigned int i;
2538
2539 /*
2540 * Disable powersaving as default.
2541 */
2542 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2543
2544 /*
2545 * Initialize all hw fields.
2546 */
2547 rt2x00dev->hw->flags =
2548 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2549 IEEE80211_HW_SIGNAL_DBM |
2550 IEEE80211_HW_SUPPORTS_PS |
2551 IEEE80211_HW_PS_NULLFUNC_STACK;
2552
2553 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2554 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2555 rt2x00_eeprom_addr(rt2x00dev,
2556 EEPROM_MAC_ADDR_0));
2557
2558 /*
2559 * Initialize hw_mode information.
2560 */
2561 spec->supported_bands = SUPPORT_BAND_2GHZ;
2562 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2563
2564 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2565 spec->num_channels = 14;
2566 spec->channels = rf_vals_noseq;
2567 } else {
2568 spec->num_channels = 14;
2569 spec->channels = rf_vals_seq;
2570 }
2571
2572 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2573 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2574 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2575 }
2576
2577 /*
2578 * Create channel information array
2579 */
2580 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2581 if (!info)
2582 return -ENOMEM;
2583
2584 spec->channels_info = info;
2585
2586 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2587 for (i = 0; i < 14; i++)
2588 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2589
2590 if (spec->num_channels > 14) {
2591 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2592 for (i = 14; i < spec->num_channels; i++)
2593 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2594 }
2595
2596 return 0;
2597 }
2598
2599 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2600 {
2601 int retval;
2602
2603 /*
2604 * Disable power saving.
2605 */
2606 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2607
2608 /*
2609 * Allocate eeprom data.
2610 */
2611 retval = rt61pci_validate_eeprom(rt2x00dev);
2612 if (retval)
2613 return retval;
2614
2615 retval = rt61pci_init_eeprom(rt2x00dev);
2616 if (retval)
2617 return retval;
2618
2619 /*
2620 * Initialize hw specifications.
2621 */
2622 retval = rt61pci_probe_hw_mode(rt2x00dev);
2623 if (retval)
2624 return retval;
2625
2626 /*
2627 * This device has multiple filters for control frames,
2628 * but has no a separate filter for PS Poll frames.
2629 */
2630 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2631
2632 /*
2633 * This device requires firmware and DMA mapped skbs.
2634 */
2635 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2636 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2637 if (!modparam_nohwcrypt)
2638 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2639
2640 /*
2641 * Set the rssi offset.
2642 */
2643 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2644
2645 return 0;
2646 }
2647
2648 /*
2649 * IEEE80211 stack callback functions.
2650 */
2651 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2652 const struct ieee80211_tx_queue_params *params)
2653 {
2654 struct rt2x00_dev *rt2x00dev = hw->priv;
2655 struct data_queue *queue;
2656 struct rt2x00_field32 field;
2657 int retval;
2658 u32 reg;
2659 u32 offset;
2660
2661 /*
2662 * First pass the configuration through rt2x00lib, that will
2663 * update the queue settings and validate the input. After that
2664 * we are free to update the registers based on the value
2665 * in the queue parameter.
2666 */
2667 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2668 if (retval)
2669 return retval;
2670
2671 /*
2672 * We only need to perform additional register initialization
2673 * for WMM queues.
2674 */
2675 if (queue_idx >= 4)
2676 return 0;
2677
2678 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2679
2680 /* Update WMM TXOP register */
2681 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2682 field.bit_offset = (queue_idx & 1) * 16;
2683 field.bit_mask = 0xffff << field.bit_offset;
2684
2685 rt2x00pci_register_read(rt2x00dev, offset, &reg);
2686 rt2x00_set_field32(&reg, field, queue->txop);
2687 rt2x00pci_register_write(rt2x00dev, offset, reg);
2688
2689 /* Update WMM registers */
2690 field.bit_offset = queue_idx * 4;
2691 field.bit_mask = 0xf << field.bit_offset;
2692
2693 rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2694 rt2x00_set_field32(&reg, field, queue->aifs);
2695 rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2696
2697 rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2698 rt2x00_set_field32(&reg, field, queue->cw_min);
2699 rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2700
2701 rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2702 rt2x00_set_field32(&reg, field, queue->cw_max);
2703 rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2704
2705 return 0;
2706 }
2707
2708 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2709 {
2710 struct rt2x00_dev *rt2x00dev = hw->priv;
2711 u64 tsf;
2712 u32 reg;
2713
2714 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2715 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2716 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2717 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2718
2719 return tsf;
2720 }
2721
2722 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2723 .tx = rt2x00mac_tx,
2724 .start = rt2x00mac_start,
2725 .stop = rt2x00mac_stop,
2726 .add_interface = rt2x00mac_add_interface,
2727 .remove_interface = rt2x00mac_remove_interface,
2728 .config = rt2x00mac_config,
2729 .configure_filter = rt2x00mac_configure_filter,
2730 .set_tim = rt2x00mac_set_tim,
2731 .set_key = rt2x00mac_set_key,
2732 .get_stats = rt2x00mac_get_stats,
2733 .bss_info_changed = rt2x00mac_bss_info_changed,
2734 .conf_tx = rt61pci_conf_tx,
2735 .get_tsf = rt61pci_get_tsf,
2736 .rfkill_poll = rt2x00mac_rfkill_poll,
2737 };
2738
2739 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2740 .irq_handler = rt61pci_interrupt,
2741 .probe_hw = rt61pci_probe_hw,
2742 .get_firmware_name = rt61pci_get_firmware_name,
2743 .check_firmware = rt61pci_check_firmware,
2744 .load_firmware = rt61pci_load_firmware,
2745 .initialize = rt2x00pci_initialize,
2746 .uninitialize = rt2x00pci_uninitialize,
2747 .get_entry_state = rt61pci_get_entry_state,
2748 .clear_entry = rt61pci_clear_entry,
2749 .set_device_state = rt61pci_set_device_state,
2750 .rfkill_poll = rt61pci_rfkill_poll,
2751 .link_stats = rt61pci_link_stats,
2752 .reset_tuner = rt61pci_reset_tuner,
2753 .link_tuner = rt61pci_link_tuner,
2754 .write_tx_desc = rt61pci_write_tx_desc,
2755 .write_tx_data = rt2x00pci_write_tx_data,
2756 .write_beacon = rt61pci_write_beacon,
2757 .kick_tx_queue = rt61pci_kick_tx_queue,
2758 .kill_tx_queue = rt61pci_kill_tx_queue,
2759 .fill_rxdone = rt61pci_fill_rxdone,
2760 .config_shared_key = rt61pci_config_shared_key,
2761 .config_pairwise_key = rt61pci_config_pairwise_key,
2762 .config_filter = rt61pci_config_filter,
2763 .config_intf = rt61pci_config_intf,
2764 .config_erp = rt61pci_config_erp,
2765 .config_ant = rt61pci_config_ant,
2766 .config = rt61pci_config,
2767 };
2768
2769 static const struct data_queue_desc rt61pci_queue_rx = {
2770 .entry_num = RX_ENTRIES,
2771 .data_size = DATA_FRAME_SIZE,
2772 .desc_size = RXD_DESC_SIZE,
2773 .priv_size = sizeof(struct queue_entry_priv_pci),
2774 };
2775
2776 static const struct data_queue_desc rt61pci_queue_tx = {
2777 .entry_num = TX_ENTRIES,
2778 .data_size = DATA_FRAME_SIZE,
2779 .desc_size = TXD_DESC_SIZE,
2780 .priv_size = sizeof(struct queue_entry_priv_pci),
2781 };
2782
2783 static const struct data_queue_desc rt61pci_queue_bcn = {
2784 .entry_num = 4 * BEACON_ENTRIES,
2785 .data_size = 0, /* No DMA required for beacons */
2786 .desc_size = TXINFO_SIZE,
2787 .priv_size = sizeof(struct queue_entry_priv_pci),
2788 };
2789
2790 static const struct rt2x00_ops rt61pci_ops = {
2791 .name = KBUILD_MODNAME,
2792 .max_sta_intf = 1,
2793 .max_ap_intf = 4,
2794 .eeprom_size = EEPROM_SIZE,
2795 .rf_size = RF_SIZE,
2796 .tx_queues = NUM_TX_QUEUES,
2797 .extra_tx_headroom = 0,
2798 .rx = &rt61pci_queue_rx,
2799 .tx = &rt61pci_queue_tx,
2800 .bcn = &rt61pci_queue_bcn,
2801 .lib = &rt61pci_rt2x00_ops,
2802 .hw = &rt61pci_mac80211_ops,
2803 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2804 .debugfs = &rt61pci_rt2x00debug,
2805 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2806 };
2807
2808 /*
2809 * RT61pci module information.
2810 */
2811 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2812 /* RT2561s */
2813 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2814 /* RT2561 v2 */
2815 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2816 /* RT2661 */
2817 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2818 { 0, }
2819 };
2820
2821 MODULE_AUTHOR(DRV_PROJECT);
2822 MODULE_VERSION(DRV_VERSION);
2823 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2824 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2825 "PCI & PCMCIA chipset based cards");
2826 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2827 MODULE_FIRMWARE(FIRMWARE_RT2561);
2828 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2829 MODULE_FIRMWARE(FIRMWARE_RT2661);
2830 MODULE_LICENSE("GPL");
2831
2832 static struct pci_driver rt61pci_driver = {
2833 .name = KBUILD_MODNAME,
2834 .id_table = rt61pci_device_table,
2835 .probe = rt2x00pci_probe,
2836 .remove = __devexit_p(rt2x00pci_remove),
2837 .suspend = rt2x00pci_suspend,
2838 .resume = rt2x00pci_resume,
2839 };
2840
2841 static int __init rt61pci_init(void)
2842 {
2843 return pci_register_driver(&rt61pci_driver);
2844 }
2845
2846 static void __exit rt61pci_exit(void)
2847 {
2848 pci_unregister_driver(&rt61pci_driver);
2849 }
2850
2851 module_init(rt61pci_init);
2852 module_exit(rt61pci_exit);
kernel source for telekom puls (alcatel/mediatek)