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rt2800: 5592: init frequency calibration
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225 {
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283 }
284
285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288 {
289 u32 reg;
290
291 /*
292 * SOC devices don't support MCU requests.
293 */
294 if (rt2x00_is_soc(rt2x00dev))
295 return;
296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316 }
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
318
319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320 {
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333 }
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337 {
338 unsigned int i;
339 u32 reg;
340
341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
351 msleep(10);
352 }
353
354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
355 return -EACCES;
356 }
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360 {
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370 }
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374 {
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403 }
404
405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407 {
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
420 */
421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
422 fw_len = 4096;
423 else
424 fw_len = 8192;
425
426 multiple = true;
427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456 }
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461 {
462 unsigned int i;
463 u32 reg;
464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
471
472 /*
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
475 */
476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
477
478 /*
479 * Wait for stable hardware.
480 */
481 if (rt2800_wait_csr_ready(rt2x00dev))
482 return -EBUSY;
483
484 if (rt2x00_is_pci(rt2x00dev)) {
485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
495 }
496
497 rt2800_disable_wpdma(rt2x00dev);
498
499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
523 rt2800_disable_wpdma(rt2x00dev);
524
525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
530 if (rt2x00_is_usb(rt2x00dev))
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
532 msleep(1);
533
534 return 0;
535 }
536 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
537
538 void rt2800_write_tx_data(struct queue_entry *entry,
539 struct txentry_desc *txdesc)
540 {
541 __le32 *txwi = rt2800_drv_get_txwi(entry);
542 u32 word;
543
544 /*
545 * Initialize TX Info descriptor
546 */
547 rt2x00_desc_read(txwi, 0, &word);
548 rt2x00_set_field32(&word, TXWI_W0_FRAG,
549 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
550 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
551 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
552 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
553 rt2x00_set_field32(&word, TXWI_W0_TS,
554 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
555 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
556 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
557 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
558 txdesc->u.ht.mpdu_density);
559 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
560 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
561 rt2x00_set_field32(&word, TXWI_W0_BW,
562 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
563 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
564 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
565 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
566 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
567 rt2x00_desc_write(txwi, 0, word);
568
569 rt2x00_desc_read(txwi, 1, &word);
570 rt2x00_set_field32(&word, TXWI_W1_ACK,
571 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
572 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
573 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
574 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
575 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
576 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
577 txdesc->key_idx : txdesc->u.ht.wcid);
578 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
579 txdesc->length);
580 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
581 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
582 rt2x00_desc_write(txwi, 1, word);
583
584 /*
585 * Always write 0 to IV/EIV fields, hardware will insert the IV
586 * from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame.
590 */
591 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
592 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
593 }
594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
595
596 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
597 {
598 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
599 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
600 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
601 u16 eeprom;
602 u8 offset0;
603 u8 offset1;
604 u8 offset2;
605
606 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
607 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
608 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
609 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
610 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
611 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
612 } else {
613 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
614 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
615 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
616 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
617 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
618 }
619
620 /*
621 * Convert the value from the descriptor into the RSSI value
622 * If the value in the descriptor is 0, it is considered invalid
623 * and the default (extremely low) rssi value is assumed
624 */
625 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
626 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
627 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
628
629 /*
630 * mac80211 only accepts a single RSSI value. Calculating the
631 * average doesn't deliver a fair answer either since -60:-60 would
632 * be considered equally good as -50:-70 while the second is the one
633 * which gives less energy...
634 */
635 rssi0 = max(rssi0, rssi1);
636 return (int)max(rssi0, rssi2);
637 }
638
639 void rt2800_process_rxwi(struct queue_entry *entry,
640 struct rxdone_entry_desc *rxdesc)
641 {
642 __le32 *rxwi = (__le32 *) entry->skb->data;
643 u32 word;
644
645 rt2x00_desc_read(rxwi, 0, &word);
646
647 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
648 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
649
650 rt2x00_desc_read(rxwi, 1, &word);
651
652 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
653 rxdesc->flags |= RX_FLAG_SHORT_GI;
654
655 if (rt2x00_get_field32(word, RXWI_W1_BW))
656 rxdesc->flags |= RX_FLAG_40MHZ;
657
658 /*
659 * Detect RX rate, always use MCS as signal type.
660 */
661 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
662 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
663 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
664
665 /*
666 * Mask of 0x8 bit to remove the short preamble flag.
667 */
668 if (rxdesc->rate_mode == RATE_MODE_CCK)
669 rxdesc->signal &= ~0x8;
670
671 rt2x00_desc_read(rxwi, 2, &word);
672
673 /*
674 * Convert descriptor AGC value to RSSI value.
675 */
676 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
677
678 /*
679 * Remove RXWI descriptor from start of buffer.
680 */
681 skb_pull(entry->skb, RXWI_DESC_SIZE);
682 }
683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
684
685 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
686 {
687 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
688 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
689 struct txdone_entry_desc txdesc;
690 u32 word;
691 u16 mcs, real_mcs;
692 int aggr, ampdu;
693
694 /*
695 * Obtain the status about this packet.
696 */
697 txdesc.flags = 0;
698 rt2x00_desc_read(txwi, 0, &word);
699
700 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
701 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
702
703 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
704 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
705
706 /*
707 * If a frame was meant to be sent as a single non-aggregated MPDU
708 * but ended up in an aggregate the used tx rate doesn't correlate
709 * with the one specified in the TXWI as the whole aggregate is sent
710 * with the same rate.
711 *
712 * For example: two frames are sent to rt2x00, the first one sets
713 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
714 * and requests MCS15. If the hw aggregates both frames into one
715 * AMDPU the tx status for both frames will contain MCS7 although
716 * the frame was sent successfully.
717 *
718 * Hence, replace the requested rate with the real tx rate to not
719 * confuse the rate control algortihm by providing clearly wrong
720 * data.
721 */
722 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
723 skbdesc->tx_rate_idx = real_mcs;
724 mcs = real_mcs;
725 }
726
727 if (aggr == 1 || ampdu == 1)
728 __set_bit(TXDONE_AMPDU, &txdesc.flags);
729
730 /*
731 * Ralink has a retry mechanism using a global fallback
732 * table. We setup this fallback table to try the immediate
733 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
734 * always contains the MCS used for the last transmission, be
735 * it successful or not.
736 */
737 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
738 /*
739 * Transmission succeeded. The number of retries is
740 * mcs - real_mcs
741 */
742 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
743 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
744 } else {
745 /*
746 * Transmission failed. The number of retries is
747 * always 7 in this case (for a total number of 8
748 * frames sent).
749 */
750 __set_bit(TXDONE_FAILURE, &txdesc.flags);
751 txdesc.retry = rt2x00dev->long_retry;
752 }
753
754 /*
755 * the frame was retried at least once
756 * -> hw used fallback rates
757 */
758 if (txdesc.retry)
759 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
760
761 rt2x00lib_txdone(entry, &txdesc);
762 }
763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
764
765 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
766 {
767 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
768 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
769 unsigned int beacon_base;
770 unsigned int padding_len;
771 u32 orig_reg, reg;
772
773 /*
774 * Disable beaconing while we are reloading the beacon data,
775 * otherwise we might be sending out invalid data.
776 */
777 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
778 orig_reg = reg;
779 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
780 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
781
782 /*
783 * Add space for the TXWI in front of the skb.
784 */
785 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
786
787 /*
788 * Register descriptor details in skb frame descriptor.
789 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE;
793
794 /*
795 * Add the TXWI for the beacon to the skb.
796 */
797 rt2800_write_tx_data(entry, txdesc);
798
799 /*
800 * Dump beacon to userspace through debugfs.
801 */
802 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
803
804 /*
805 * Write entire beacon with TXWI and padding to register.
806 */
807 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
808 if (padding_len && skb_pad(entry->skb, padding_len)) {
809 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */
811 entry->skb = NULL;
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
813 return;
814 }
815
816 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
817 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
818 entry->skb->len + padding_len);
819
820 /*
821 * Enable beaconing again.
822 */
823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825
826 /*
827 * Clean up beacon skb.
828 */
829 dev_kfree_skb_any(entry->skb);
830 entry->skb = NULL;
831 }
832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
833
834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base)
836 {
837 int i;
838
839 /*
840 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon.
843 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846 }
847
848 void rt2800_clear_beacon(struct queue_entry *entry)
849 {
850 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
851 u32 reg;
852
853 /*
854 * Disable beaconing while we are reloading the beacon data,
855 * otherwise we might be sending out invalid data.
856 */
857 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
858 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
859 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
860
861 /*
862 * Clear beacon.
863 */
864 rt2800_clear_beacon_register(rt2x00dev,
865 HW_BEACON_OFFSET(entry->entry_idx));
866
867 /*
868 * Enabled beaconing again.
869 */
870 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
871 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
872 }
873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
874
875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
876 const struct rt2x00debug rt2800_rt2x00debug = {
877 .owner = THIS_MODULE,
878 .csr = {
879 .read = rt2800_register_read,
880 .write = rt2800_register_write,
881 .flags = RT2X00DEBUGFS_OFFSET,
882 .word_base = CSR_REG_BASE,
883 .word_size = sizeof(u32),
884 .word_count = CSR_REG_SIZE / sizeof(u32),
885 },
886 .eeprom = {
887 .read = rt2x00_eeprom_read,
888 .write = rt2x00_eeprom_write,
889 .word_base = EEPROM_BASE,
890 .word_size = sizeof(u16),
891 .word_count = EEPROM_SIZE / sizeof(u16),
892 },
893 .bbp = {
894 .read = rt2800_bbp_read,
895 .write = rt2800_bbp_write,
896 .word_base = BBP_BASE,
897 .word_size = sizeof(u8),
898 .word_count = BBP_SIZE / sizeof(u8),
899 },
900 .rf = {
901 .read = rt2x00_rf_read,
902 .write = rt2800_rf_write,
903 .word_base = RF_BASE,
904 .word_size = sizeof(u32),
905 .word_count = RF_SIZE / sizeof(u32),
906 },
907 .rfcsr = {
908 .read = rt2800_rfcsr_read,
909 .write = rt2800_rfcsr_write,
910 .word_base = RFCSR_BASE,
911 .word_size = sizeof(u8),
912 .word_count = RFCSR_SIZE / sizeof(u8),
913 },
914 };
915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
917
918 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
919 {
920 u32 reg;
921
922 if (rt2x00_rt(rt2x00dev, RT3290)) {
923 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
924 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
925 } else {
926 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
927 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
928 }
929 }
930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
931
932 #ifdef CONFIG_RT2X00_LIB_LEDS
933 static void rt2800_brightness_set(struct led_classdev *led_cdev,
934 enum led_brightness brightness)
935 {
936 struct rt2x00_led *led =
937 container_of(led_cdev, struct rt2x00_led, led_dev);
938 unsigned int enabled = brightness != LED_OFF;
939 unsigned int bg_mode =
940 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
941 unsigned int polarity =
942 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
943 EEPROM_FREQ_LED_POLARITY);
944 unsigned int ledmode =
945 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
946 EEPROM_FREQ_LED_MODE);
947 u32 reg;
948
949 /* Check for SoC (SOC devices don't support MCU requests) */
950 if (rt2x00_is_soc(led->rt2x00dev)) {
951 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
952
953 /* Set LED Polarity */
954 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
955
956 /* Set LED Mode */
957 if (led->type == LED_TYPE_RADIO) {
958 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
959 enabled ? 3 : 0);
960 } else if (led->type == LED_TYPE_ASSOC) {
961 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
962 enabled ? 3 : 0);
963 } else if (led->type == LED_TYPE_QUALITY) {
964 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
965 enabled ? 3 : 0);
966 }
967
968 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
969
970 } else {
971 if (led->type == LED_TYPE_RADIO) {
972 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
973 enabled ? 0x20 : 0);
974 } else if (led->type == LED_TYPE_ASSOC) {
975 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
976 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
977 } else if (led->type == LED_TYPE_QUALITY) {
978 /*
979 * The brightness is divided into 6 levels (0 - 5),
980 * The specs tell us the following levels:
981 * 0, 1 ,3, 7, 15, 31
982 * to determine the level in a simple way we can simply
983 * work with bitshifting:
984 * (1 << level) - 1
985 */
986 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
987 (1 << brightness / (LED_FULL / 6)) - 1,
988 polarity);
989 }
990 }
991 }
992
993 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
994 struct rt2x00_led *led, enum led_type type)
995 {
996 led->rt2x00dev = rt2x00dev;
997 led->type = type;
998 led->led_dev.brightness_set = rt2800_brightness_set;
999 led->flags = LED_INITIALIZED;
1000 }
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003 /*
1004 * Configuration handlers.
1005 */
1006 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007 const u8 *address,
1008 int wcid)
1009 {
1010 struct mac_wcid_entry wcid_entry;
1011 u32 offset;
1012
1013 offset = MAC_WCID_ENTRY(wcid);
1014
1015 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016 if (address)
1017 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019 rt2800_register_multiwrite(rt2x00dev, offset,
1020 &wcid_entry, sizeof(wcid_entry));
1021 }
1022
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024 {
1025 u32 offset;
1026 offset = MAC_WCID_ATTR_ENTRY(wcid);
1027 rt2800_register_write(rt2x00dev, offset, 0);
1028 }
1029
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031 int wcid, u32 bssidx)
1032 {
1033 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034 u32 reg;
1035
1036 /*
1037 * The BSS Idx numbers is split in a main value of 3 bits,
1038 * and a extended field for adding one additional bit to the value.
1039 */
1040 rt2800_register_read(rt2x00dev, offset, &reg);
1041 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043 (bssidx & 0x8) >> 3);
1044 rt2800_register_write(rt2x00dev, offset, reg);
1045 }
1046
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048 struct rt2x00lib_crypto *crypto,
1049 struct ieee80211_key_conf *key)
1050 {
1051 struct mac_iveiv_entry iveiv_entry;
1052 u32 offset;
1053 u32 reg;
1054
1055 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
1057 if (crypto->cmd == SET_KEY) {
1058 rt2800_register_read(rt2x00dev, offset, &reg);
1059 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061 /*
1062 * Both the cipher as the BSS Idx numbers are split in a main
1063 * value of 3 bits, and a extended field for adding one additional
1064 * bit to the value.
1065 */
1066 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067 (crypto->cipher & 0x7));
1068 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069 (crypto->cipher & 0x8) >> 3);
1070 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071 rt2800_register_write(rt2x00dev, offset, reg);
1072 } else {
1073 /* Delete the cipher without touching the bssidx */
1074 rt2800_register_read(rt2x00dev, offset, &reg);
1075 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079 rt2800_register_write(rt2x00dev, offset, reg);
1080 }
1081
1082 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085 if ((crypto->cipher == CIPHER_TKIP) ||
1086 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087 (crypto->cipher == CIPHER_AES))
1088 iveiv_entry.iv[3] |= 0x20;
1089 iveiv_entry.iv[3] |= key->keyidx << 6;
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &iveiv_entry, sizeof(iveiv_entry));
1092 }
1093
1094 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095 struct rt2x00lib_crypto *crypto,
1096 struct ieee80211_key_conf *key)
1097 {
1098 struct hw_key_entry key_entry;
1099 struct rt2x00_field32 field;
1100 u32 offset;
1101 u32 reg;
1102
1103 if (crypto->cmd == SET_KEY) {
1104 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106 memcpy(key_entry.key, crypto->key,
1107 sizeof(key_entry.key));
1108 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109 sizeof(key_entry.tx_mic));
1110 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111 sizeof(key_entry.rx_mic));
1112
1113 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114 rt2800_register_multiwrite(rt2x00dev, offset,
1115 &key_entry, sizeof(key_entry));
1116 }
1117
1118 /*
1119 * The cipher types are stored over multiple registers
1120 * starting with SHARED_KEY_MODE_BASE each word will have
1121 * 32 bits and contains the cipher types for 2 bssidx each.
1122 * Using the correct defines correctly will cause overhead,
1123 * so just calculate the correct offset.
1124 */
1125 field.bit_offset = 4 * (key->hw_key_idx % 8);
1126 field.bit_mask = 0x7 << field.bit_offset;
1127
1128 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130 rt2800_register_read(rt2x00dev, offset, &reg);
1131 rt2x00_set_field32(&reg, field,
1132 (crypto->cmd == SET_KEY) * crypto->cipher);
1133 rt2800_register_write(rt2x00dev, offset, reg);
1134
1135 /*
1136 * Update WCID information
1137 */
1138 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140 crypto->bssidx);
1141 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142
1143 return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
1147 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148 {
1149 struct mac_wcid_entry wcid_entry;
1150 int idx;
1151 u32 offset;
1152
1153 /*
1154 * Search for the first free WCID entry and return the corresponding
1155 * index.
1156 *
1157 * Make sure the WCID starts _after_ the last possible shared key
1158 * entry (>32).
1159 *
1160 * Since parts of the pairwise key table might be shared with
1161 * the beacon frame buffers 6 & 7 we should only write into the
1162 * first 222 entries.
1163 */
1164 for (idx = 33; idx <= 222; idx++) {
1165 offset = MAC_WCID_ENTRY(idx);
1166 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167 sizeof(wcid_entry));
1168 if (is_broadcast_ether_addr(wcid_entry.mac))
1169 return idx;
1170 }
1171
1172 /*
1173 * Use -1 to indicate that we don't have any more space in the WCID
1174 * table.
1175 */
1176 return -1;
1177 }
1178
1179 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180 struct rt2x00lib_crypto *crypto,
1181 struct ieee80211_key_conf *key)
1182 {
1183 struct hw_key_entry key_entry;
1184 u32 offset;
1185
1186 if (crypto->cmd == SET_KEY) {
1187 /*
1188 * Allow key configuration only for STAs that are
1189 * known by the hw.
1190 */
1191 if (crypto->wcid < 0)
1192 return -ENOSPC;
1193 key->hw_key_idx = crypto->wcid;
1194
1195 memcpy(key_entry.key, crypto->key,
1196 sizeof(key_entry.key));
1197 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198 sizeof(key_entry.tx_mic));
1199 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200 sizeof(key_entry.rx_mic));
1201
1202 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203 rt2800_register_multiwrite(rt2x00dev, offset,
1204 &key_entry, sizeof(key_entry));
1205 }
1206
1207 /*
1208 * Update WCID information
1209 */
1210 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211
1212 return 0;
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
1216 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217 struct ieee80211_sta *sta)
1218 {
1219 int wcid;
1220 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222 /*
1223 * Find next free WCID.
1224 */
1225 wcid = rt2800_find_wcid(rt2x00dev);
1226
1227 /*
1228 * Store selected wcid even if it is invalid so that we can
1229 * later decide if the STA is uploaded into the hw.
1230 */
1231 sta_priv->wcid = wcid;
1232
1233 /*
1234 * No space left in the device, however, we can still communicate
1235 * with the STA -> No error.
1236 */
1237 if (wcid < 0)
1238 return 0;
1239
1240 /*
1241 * Clean up WCID attributes and write STA address to the device.
1242 */
1243 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246 rt2x00lib_get_bssidx(rt2x00dev, vif));
1247 return 0;
1248 }
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252 {
1253 /*
1254 * Remove WCID entry, no need to clean the attributes as they will
1255 * get renewed when the WCID is reused.
1256 */
1257 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259 return 0;
1260 }
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
1263 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264 const unsigned int filter_flags)
1265 {
1266 u32 reg;
1267
1268 /*
1269 * Start configuration steps.
1270 * Note that the version error will always be dropped
1271 * and broadcast frames will always be accepted since
1272 * there is no filter for it at this time.
1273 */
1274 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276 !(filter_flags & FIF_FCSFAIL));
1277 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278 !(filter_flags & FIF_PLCPFAIL));
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280 !(filter_flags & FIF_PROMISC_IN_BSS));
1281 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284 !(filter_flags & FIF_ALLMULTI));
1285 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288 !(filter_flags & FIF_CONTROL));
1289 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290 !(filter_flags & FIF_CONTROL));
1291 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292 !(filter_flags & FIF_CONTROL));
1293 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294 !(filter_flags & FIF_CONTROL));
1295 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296 !(filter_flags & FIF_CONTROL));
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298 !(filter_flags & FIF_PSPOLL));
1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1300 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1301 !(filter_flags & FIF_CONTROL));
1302 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1303 !(filter_flags & FIF_CONTROL));
1304 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1305 }
1306 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1307
1308 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1309 struct rt2x00intf_conf *conf, const unsigned int flags)
1310 {
1311 u32 reg;
1312 bool update_bssid = false;
1313
1314 if (flags & CONFIG_UPDATE_TYPE) {
1315 /*
1316 * Enable synchronisation.
1317 */
1318 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1319 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1320 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1321
1322 if (conf->sync == TSF_SYNC_AP_NONE) {
1323 /*
1324 * Tune beacon queue transmit parameters for AP mode
1325 */
1326 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1327 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1328 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1329 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1330 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1331 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1332 } else {
1333 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1334 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1335 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1336 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1337 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1338 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1339 }
1340 }
1341
1342 if (flags & CONFIG_UPDATE_MAC) {
1343 if (flags & CONFIG_UPDATE_TYPE &&
1344 conf->sync == TSF_SYNC_AP_NONE) {
1345 /*
1346 * The BSSID register has to be set to our own mac
1347 * address in AP mode.
1348 */
1349 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1350 update_bssid = true;
1351 }
1352
1353 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1354 reg = le32_to_cpu(conf->mac[1]);
1355 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1356 conf->mac[1] = cpu_to_le32(reg);
1357 }
1358
1359 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1360 conf->mac, sizeof(conf->mac));
1361 }
1362
1363 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1364 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1365 reg = le32_to_cpu(conf->bssid[1]);
1366 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1367 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1368 conf->bssid[1] = cpu_to_le32(reg);
1369 }
1370
1371 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1372 conf->bssid, sizeof(conf->bssid));
1373 }
1374 }
1375 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1376
1377 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1378 struct rt2x00lib_erp *erp)
1379 {
1380 bool any_sta_nongf = !!(erp->ht_opmode &
1381 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1382 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1383 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1384 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1385 u32 reg;
1386
1387 /* default protection rate for HT20: OFDM 24M */
1388 mm20_rate = gf20_rate = 0x4004;
1389
1390 /* default protection rate for HT40: duplicate OFDM 24M */
1391 mm40_rate = gf40_rate = 0x4084;
1392
1393 switch (protection) {
1394 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1395 /*
1396 * All STAs in this BSS are HT20/40 but there might be
1397 * STAs not supporting greenfield mode.
1398 * => Disable protection for HT transmissions.
1399 */
1400 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1401
1402 break;
1403 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1404 /*
1405 * All STAs in this BSS are HT20 or HT20/40 but there
1406 * might be STAs not supporting greenfield mode.
1407 * => Protect all HT40 transmissions.
1408 */
1409 mm20_mode = gf20_mode = 0;
1410 mm40_mode = gf40_mode = 2;
1411
1412 break;
1413 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1414 /*
1415 * Nonmember protection:
1416 * According to 802.11n we _should_ protect all
1417 * HT transmissions (but we don't have to).
1418 *
1419 * But if cts_protection is enabled we _shall_ protect
1420 * all HT transmissions using a CCK rate.
1421 *
1422 * And if any station is non GF we _shall_ protect
1423 * GF transmissions.
1424 *
1425 * We decide to protect everything
1426 * -> fall through to mixed mode.
1427 */
1428 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1429 /*
1430 * Legacy STAs are present
1431 * => Protect all HT transmissions.
1432 */
1433 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1434
1435 /*
1436 * If erp protection is needed we have to protect HT
1437 * transmissions with CCK 11M long preamble.
1438 */
1439 if (erp->cts_protection) {
1440 /* don't duplicate RTS/CTS in CCK mode */
1441 mm20_rate = mm40_rate = 0x0003;
1442 gf20_rate = gf40_rate = 0x0003;
1443 }
1444 break;
1445 }
1446
1447 /* check for STAs not supporting greenfield mode */
1448 if (any_sta_nongf)
1449 gf20_mode = gf40_mode = 2;
1450
1451 /* Update HT protection config */
1452 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1453 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1454 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1455 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1456
1457 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1458 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1459 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1460 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1461
1462 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1463 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1464 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1465 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1466
1467 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1468 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1469 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1470 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1471 }
1472
1473 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1474 u32 changed)
1475 {
1476 u32 reg;
1477
1478 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1479 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1480 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1481 !!erp->short_preamble);
1482 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1483 !!erp->short_preamble);
1484 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1485 }
1486
1487 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1488 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1489 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1490 erp->cts_protection ? 2 : 0);
1491 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1492 }
1493
1494 if (changed & BSS_CHANGED_BASIC_RATES) {
1495 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1496 erp->basic_rates);
1497 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1498 }
1499
1500 if (changed & BSS_CHANGED_ERP_SLOT) {
1501 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1502 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1503 erp->slot_time);
1504 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1505
1506 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1507 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1508 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1509 }
1510
1511 if (changed & BSS_CHANGED_BEACON_INT) {
1512 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1513 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1514 erp->beacon_int * 16);
1515 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1516 }
1517
1518 if (changed & BSS_CHANGED_HT)
1519 rt2800_config_ht_opmode(rt2x00dev, erp);
1520 }
1521 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1522
1523 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1524 {
1525 u32 reg;
1526 u16 eeprom;
1527 u8 led_ctrl, led_g_mode, led_r_mode;
1528
1529 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1530 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1531 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1532 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1533 } else {
1534 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1535 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1536 }
1537 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1538
1539 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1540 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1541 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1542 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1543 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1544 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1545 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1546 if (led_ctrl == 0 || led_ctrl > 0x40) {
1547 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1548 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1549 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1550 } else {
1551 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1552 (led_g_mode << 2) | led_r_mode, 1);
1553 }
1554 }
1555 }
1556
1557 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1558 enum antenna ant)
1559 {
1560 u32 reg;
1561 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1562 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1563
1564 if (rt2x00_is_pci(rt2x00dev)) {
1565 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1566 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1567 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1568 } else if (rt2x00_is_usb(rt2x00dev))
1569 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1570 eesk_pin, 0);
1571
1572 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1573 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1574 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1575 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1576 }
1577
1578 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1579 {
1580 u8 r1;
1581 u8 r3;
1582 u16 eeprom;
1583
1584 rt2800_bbp_read(rt2x00dev, 1, &r1);
1585 rt2800_bbp_read(rt2x00dev, 3, &r3);
1586
1587 if (rt2x00_rt(rt2x00dev, RT3572) &&
1588 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1589 rt2800_config_3572bt_ant(rt2x00dev);
1590
1591 /*
1592 * Configure the TX antenna.
1593 */
1594 switch (ant->tx_chain_num) {
1595 case 1:
1596 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1597 break;
1598 case 2:
1599 if (rt2x00_rt(rt2x00dev, RT3572) &&
1600 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1601 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1602 else
1603 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1604 break;
1605 case 3:
1606 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1607 break;
1608 }
1609
1610 /*
1611 * Configure the RX antenna.
1612 */
1613 switch (ant->rx_chain_num) {
1614 case 1:
1615 if (rt2x00_rt(rt2x00dev, RT3070) ||
1616 rt2x00_rt(rt2x00dev, RT3090) ||
1617 rt2x00_rt(rt2x00dev, RT3352) ||
1618 rt2x00_rt(rt2x00dev, RT3390)) {
1619 rt2x00_eeprom_read(rt2x00dev,
1620 EEPROM_NIC_CONF1, &eeprom);
1621 if (rt2x00_get_field16(eeprom,
1622 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1623 rt2800_set_ant_diversity(rt2x00dev,
1624 rt2x00dev->default_ant.rx);
1625 }
1626 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1627 break;
1628 case 2:
1629 if (rt2x00_rt(rt2x00dev, RT3572) &&
1630 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1631 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1632 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1633 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1634 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1635 } else {
1636 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1637 }
1638 break;
1639 case 3:
1640 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1641 break;
1642 }
1643
1644 rt2800_bbp_write(rt2x00dev, 3, r3);
1645 rt2800_bbp_write(rt2x00dev, 1, r1);
1646 }
1647 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1648
1649 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1650 struct rt2x00lib_conf *libconf)
1651 {
1652 u16 eeprom;
1653 short lna_gain;
1654
1655 if (libconf->rf.channel <= 14) {
1656 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1658 } else if (libconf->rf.channel <= 64) {
1659 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1660 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1661 } else if (libconf->rf.channel <= 128) {
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1663 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1664 } else {
1665 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1666 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1667 }
1668
1669 rt2x00dev->lna_gain = lna_gain;
1670 }
1671
1672 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1673 struct ieee80211_conf *conf,
1674 struct rf_channel *rf,
1675 struct channel_info *info)
1676 {
1677 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1678
1679 if (rt2x00dev->default_ant.tx_chain_num == 1)
1680 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1681
1682 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1683 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1684 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1685 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1686 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1687
1688 if (rf->channel > 14) {
1689 /*
1690 * When TX power is below 0, we should increase it by 7 to
1691 * make it a positive value (Minimum value is -7).
1692 * However this means that values between 0 and 7 have
1693 * double meaning, and we should set a 7DBm boost flag.
1694 */
1695 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1696 (info->default_power1 >= 0));
1697
1698 if (info->default_power1 < 0)
1699 info->default_power1 += 7;
1700
1701 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1702
1703 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1704 (info->default_power2 >= 0));
1705
1706 if (info->default_power2 < 0)
1707 info->default_power2 += 7;
1708
1709 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1710 } else {
1711 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1712 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1713 }
1714
1715 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1716
1717 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1718 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1719 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1720 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1721
1722 udelay(200);
1723
1724 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1725 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1726 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1727 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1728
1729 udelay(200);
1730
1731 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1732 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1733 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1734 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1735 }
1736
1737 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1738 struct ieee80211_conf *conf,
1739 struct rf_channel *rf,
1740 struct channel_info *info)
1741 {
1742 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1743 u8 rfcsr, calib_tx, calib_rx;
1744
1745 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1746
1747 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1748 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1749 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1750
1751 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1752 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1753 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1754
1755 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1756 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1757 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1758
1759 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1760 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1761 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1762
1763 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1765 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1766 rt2x00dev->default_ant.rx_chain_num <= 1);
1767 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1768 rt2x00dev->default_ant.rx_chain_num <= 2);
1769 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1770 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1771 rt2x00dev->default_ant.tx_chain_num <= 1);
1772 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1773 rt2x00dev->default_ant.tx_chain_num <= 2);
1774 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1775
1776 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1777 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1778 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779 msleep(1);
1780 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1781 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1782
1783 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1784 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1785 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1786
1787 if (rt2x00_rt(rt2x00dev, RT3390)) {
1788 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1789 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1790 } else {
1791 if (conf_is_ht40(conf)) {
1792 calib_tx = drv_data->calibration_bw40;
1793 calib_rx = drv_data->calibration_bw40;
1794 } else {
1795 calib_tx = drv_data->calibration_bw20;
1796 calib_rx = drv_data->calibration_bw20;
1797 }
1798 }
1799
1800 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1801 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1802 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1803
1804 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1805 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1806 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1807
1808 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1809 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1810 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1811
1812 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1813 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1814 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815 msleep(1);
1816 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1817 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1818 }
1819
1820 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1821 struct ieee80211_conf *conf,
1822 struct rf_channel *rf,
1823 struct channel_info *info)
1824 {
1825 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1826 u8 rfcsr;
1827 u32 reg;
1828
1829 if (rf->channel <= 14) {
1830 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1831 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1832 } else {
1833 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1834 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1835 }
1836
1837 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1838 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1839
1840 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1841 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1842 if (rf->channel <= 14)
1843 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1844 else
1845 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1846 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1847
1848 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1849 if (rf->channel <= 14)
1850 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1851 else
1852 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1853 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1854
1855 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1856 if (rf->channel <= 14) {
1857 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1858 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1859 info->default_power1);
1860 } else {
1861 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1862 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1863 (info->default_power1 & 0x3) |
1864 ((info->default_power1 & 0xC) << 1));
1865 }
1866 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1867
1868 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1869 if (rf->channel <= 14) {
1870 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1871 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1872 info->default_power2);
1873 } else {
1874 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1875 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1876 (info->default_power2 & 0x3) |
1877 ((info->default_power2 & 0xC) << 1));
1878 }
1879 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1880
1881 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1882 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1885 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1886 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1887 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1888 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1889 if (rf->channel <= 14) {
1890 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1891 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1892 }
1893 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1894 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1895 } else {
1896 switch (rt2x00dev->default_ant.tx_chain_num) {
1897 case 1:
1898 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1899 case 2:
1900 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901 break;
1902 }
1903
1904 switch (rt2x00dev->default_ant.rx_chain_num) {
1905 case 1:
1906 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1907 case 2:
1908 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1909 break;
1910 }
1911 }
1912 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1913
1914 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1915 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1916 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1917
1918 if (conf_is_ht40(conf)) {
1919 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1920 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1921 } else {
1922 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1923 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1924 }
1925
1926 if (rf->channel <= 14) {
1927 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1928 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1929 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1930 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1931 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1932 rfcsr = 0x4c;
1933 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1934 drv_data->txmixer_gain_24g);
1935 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1936 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1937 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1938 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1939 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1940 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1941 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1942 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1943 } else {
1944 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1945 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1946 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1947 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1948 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1949 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1950 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1951 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1952 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1953 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1954 rfcsr = 0x7a;
1955 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1956 drv_data->txmixer_gain_5g);
1957 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1958 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1959 if (rf->channel <= 64) {
1960 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1961 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1962 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1963 } else if (rf->channel <= 128) {
1964 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1965 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1966 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1967 } else {
1968 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1969 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1970 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1971 }
1972 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1973 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1974 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1975 }
1976
1977 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1978 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1979 if (rf->channel <= 14)
1980 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1981 else
1982 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1983 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1984
1985 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1986 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1987 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1988 }
1989
1990 #define POWER_BOUND 0x27
1991 #define POWER_BOUND_5G 0x2b
1992 #define FREQ_OFFSET_BOUND 0x5f
1993
1994 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1995 {
1996 u8 rfcsr;
1997
1998 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1999 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2000 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2001 else
2002 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2003 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2004 }
2005
2006 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2007 struct ieee80211_conf *conf,
2008 struct rf_channel *rf,
2009 struct channel_info *info)
2010 {
2011 u8 rfcsr;
2012
2013 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2014 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2015 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2016 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2017 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2018
2019 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2020 if (info->default_power1 > POWER_BOUND)
2021 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2022 else
2023 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2024 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2025
2026 rt2800_adjust_freq_offset(rt2x00dev);
2027
2028 if (rf->channel <= 14) {
2029 if (rf->channel == 6)
2030 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2031 else
2032 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2033
2034 if (rf->channel >= 1 && rf->channel <= 6)
2035 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2036 else if (rf->channel >= 7 && rf->channel <= 11)
2037 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2038 else if (rf->channel >= 12 && rf->channel <= 14)
2039 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2040 }
2041 }
2042
2043 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2044 struct ieee80211_conf *conf,
2045 struct rf_channel *rf,
2046 struct channel_info *info)
2047 {
2048 u8 rfcsr;
2049
2050 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2051 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2052
2053 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2054 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2055 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2056
2057 if (info->default_power1 > POWER_BOUND)
2058 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2059 else
2060 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2061
2062 if (info->default_power2 > POWER_BOUND)
2063 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2064 else
2065 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2066
2067 rt2800_adjust_freq_offset(rt2x00dev);
2068
2069 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2070 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2071 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2072
2073 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2074 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2075 else
2076 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2077
2078 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2079 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2080 else
2081 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2082
2083 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2084 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2085
2086 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2087
2088 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2089 }
2090
2091 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2092 struct ieee80211_conf *conf,
2093 struct rf_channel *rf,
2094 struct channel_info *info)
2095 {
2096 u8 rfcsr;
2097
2098 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2099 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2100 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2101 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2102 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2103
2104 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2105 if (info->default_power1 > POWER_BOUND)
2106 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2107 else
2108 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2109 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2110
2111 if (rt2x00_rt(rt2x00dev, RT5392)) {
2112 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2113 if (info->default_power1 > POWER_BOUND)
2114 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2115 else
2116 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2117 info->default_power2);
2118 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2119 }
2120
2121 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2122 if (rt2x00_rt(rt2x00dev, RT5392)) {
2123 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2124 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2125 }
2126 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2127 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2128 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2129 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2130 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2131
2132 rt2800_adjust_freq_offset(rt2x00dev);
2133
2134 if (rf->channel <= 14) {
2135 int idx = rf->channel-1;
2136
2137 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2138 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2139 /* r55/r59 value array of channel 1~14 */
2140 static const char r55_bt_rev[] = {0x83, 0x83,
2141 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2142 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2143 static const char r59_bt_rev[] = {0x0e, 0x0e,
2144 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2145 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2146
2147 rt2800_rfcsr_write(rt2x00dev, 55,
2148 r55_bt_rev[idx]);
2149 rt2800_rfcsr_write(rt2x00dev, 59,
2150 r59_bt_rev[idx]);
2151 } else {
2152 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2153 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2154 0x88, 0x88, 0x86, 0x85, 0x84};
2155
2156 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2157 }
2158 } else {
2159 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2160 static const char r55_nonbt_rev[] = {0x23, 0x23,
2161 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2162 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2163 static const char r59_nonbt_rev[] = {0x07, 0x07,
2164 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2165 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2166
2167 rt2800_rfcsr_write(rt2x00dev, 55,
2168 r55_nonbt_rev[idx]);
2169 rt2800_rfcsr_write(rt2x00dev, 59,
2170 r59_nonbt_rev[idx]);
2171 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2172 rt2x00_rt(rt2x00dev, RT5392)) {
2173 static const char r59_non_bt[] = {0x8f, 0x8f,
2174 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2175 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2176
2177 rt2800_rfcsr_write(rt2x00dev, 59,
2178 r59_non_bt[idx]);
2179 }
2180 }
2181 }
2182 }
2183
2184 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2185 struct ieee80211_conf *conf,
2186 struct rf_channel *rf,
2187 struct channel_info *info)
2188 {
2189 u8 rfcsr, ep_reg;
2190 int power_bound;
2191
2192 /* TODO */
2193 const bool is_11b = false;
2194 const bool is_type_ep = false;
2195
2196
2197 /* Order of values on rf_channel entry: N, K, mod, R */
2198 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2199
2200 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2201 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2202 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2203 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2204 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2205
2206 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2207 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2208 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2209 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2210
2211 if (rf->channel <= 14) {
2212 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2213 /* FIXME: RF11 owerwrite ? */
2214 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2215 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2216 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2217 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2218 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2219 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2220 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2221 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2222 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2223 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2224 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2225 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2226 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2227 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2228 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2229 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2230 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2231 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2232 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2233 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2234 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2235 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2236 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2237 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2238 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2239 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2240 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2241 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2242
2243 /* TODO RF27 <- tssi */
2244
2245 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2246 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2247 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2248
2249 if (is_11b) {
2250 /* CCK */
2251 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2252 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2253 if (is_type_ep)
2254 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2255 else
2256 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2257 } else {
2258 /* OFDM */
2259 if (is_type_ep)
2260 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2261 else
2262 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2263 }
2264
2265 power_bound = POWER_BOUND;
2266 ep_reg = 0x2;
2267 } else {
2268 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2269 /* FIMXE: RF11 overwrite */
2270 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2271 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2272 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2273 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2274 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2275 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2276 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2277 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2278 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2279 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2280 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2281 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2282 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2283 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2284
2285 /* TODO RF27 <- tssi */
2286
2287 if (rf->channel >= 36 && rf->channel <= 64) {
2288
2289 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2290 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2291 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2292 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2293 if (rf->channel <= 50)
2294 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2295 else if (rf->channel >= 52)
2296 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2297 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2298 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2299 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2300 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2301 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2302 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2303 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2304 if (rf->channel <= 50) {
2305 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2306 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2307 } else if (rf->channel >= 52) {
2308 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2309 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2310 }
2311
2312 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2313 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2314 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2315
2316 } else if (rf->channel >= 100 && rf->channel <= 165) {
2317
2318 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2319 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2320 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2321 if (rf->channel <= 153) {
2322 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2323 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2324 } else if (rf->channel >= 155) {
2325 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2326 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2327 }
2328 if (rf->channel <= 138) {
2329 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2330 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2331 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2332 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2333 } else if (rf->channel >= 140) {
2334 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2335 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2336 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2337 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2338 }
2339 if (rf->channel <= 124)
2340 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2341 else if (rf->channel >= 126)
2342 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2343 if (rf->channel <= 138)
2344 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2345 else if (rf->channel >= 140)
2346 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2347 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2348 if (rf->channel <= 138)
2349 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2350 else if (rf->channel >= 140)
2351 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2352 if (rf->channel <= 128)
2353 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2354 else if (rf->channel >= 130)
2355 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2356 if (rf->channel <= 116)
2357 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2358 else if (rf->channel >= 118)
2359 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2360 if (rf->channel <= 138)
2361 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2362 else if (rf->channel >= 140)
2363 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2364 if (rf->channel <= 116)
2365 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2366 else if (rf->channel >= 118)
2367 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2368 }
2369
2370 power_bound = POWER_BOUND_5G;
2371 ep_reg = 0x3;
2372 }
2373
2374 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2375 if (info->default_power1 > power_bound)
2376 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2377 else
2378 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2379 if (is_type_ep)
2380 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2381 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2382
2383 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2384 if (info->default_power1 > power_bound)
2385 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2386 else
2387 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2388 if (is_type_ep)
2389 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2390 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2391
2392 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2393 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2394 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2395
2396 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2397 rt2x00dev->default_ant.tx_chain_num >= 1);
2398 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2399 rt2x00dev->default_ant.tx_chain_num == 2);
2400 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2401
2402 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2403 rt2x00dev->default_ant.rx_chain_num >= 1);
2404 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2405 rt2x00dev->default_ant.rx_chain_num == 2);
2406 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2407
2408 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2409 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2410
2411 if (conf_is_ht40(conf))
2412 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2413 else
2414 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2415
2416 if (!is_11b) {
2417 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2418 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2419 }
2420
2421 /* TODO proper frequency adjustment */
2422 rt2800_adjust_freq_offset(rt2x00dev);
2423
2424 /* TODO merge with others */
2425 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2426 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2427 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2428 }
2429
2430 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2431 struct ieee80211_conf *conf,
2432 struct rf_channel *rf,
2433 struct channel_info *info)
2434 {
2435 u32 reg;
2436 unsigned int tx_pin;
2437 u8 bbp, rfcsr;
2438
2439 if (rf->channel <= 14) {
2440 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2441 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2442 } else {
2443 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2444 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2445 }
2446
2447 switch (rt2x00dev->chip.rf) {
2448 case RF2020:
2449 case RF3020:
2450 case RF3021:
2451 case RF3022:
2452 case RF3320:
2453 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2454 break;
2455 case RF3052:
2456 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2457 break;
2458 case RF3290:
2459 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2460 break;
2461 case RF3322:
2462 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2463 break;
2464 case RF5360:
2465 case RF5370:
2466 case RF5372:
2467 case RF5390:
2468 case RF5392:
2469 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2470 break;
2471 case RF5592:
2472 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2473 break;
2474 default:
2475 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2476 }
2477
2478 if (rt2x00_rf(rt2x00dev, RF3290) ||
2479 rt2x00_rf(rt2x00dev, RF3322) ||
2480 rt2x00_rf(rt2x00dev, RF5360) ||
2481 rt2x00_rf(rt2x00dev, RF5370) ||
2482 rt2x00_rf(rt2x00dev, RF5372) ||
2483 rt2x00_rf(rt2x00dev, RF5390) ||
2484 rt2x00_rf(rt2x00dev, RF5392)) {
2485 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2486 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2487 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2488 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2489
2490 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2491 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2492 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2493 }
2494
2495 /*
2496 * Change BBP settings
2497 */
2498 if (rt2x00_rt(rt2x00dev, RT3352)) {
2499 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2500 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2501 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2502 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2503 } else {
2504 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2505 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2506 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2507 rt2800_bbp_write(rt2x00dev, 86, 0);
2508 }
2509
2510 if (rf->channel <= 14) {
2511 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2512 !rt2x00_rt(rt2x00dev, RT5392)) {
2513 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2514 &rt2x00dev->cap_flags)) {
2515 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2516 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2517 } else {
2518 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2519 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2520 }
2521 }
2522 } else {
2523 if (rt2x00_rt(rt2x00dev, RT3572))
2524 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2525 else
2526 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2527
2528 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2529 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2530 else
2531 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2532 }
2533
2534 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2535 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2536 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2537 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2538 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2539
2540 if (rt2x00_rt(rt2x00dev, RT3572))
2541 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2542
2543 tx_pin = 0;
2544
2545 /* Turn on unused PA or LNA when not using 1T or 1R */
2546 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2547 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2548 rf->channel > 14);
2549 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2550 rf->channel <= 14);
2551 }
2552
2553 /* Turn on unused PA or LNA when not using 1T or 1R */
2554 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2555 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2556 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2557 }
2558
2559 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2560 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2561 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2562 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2563 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2564 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2565 else
2566 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2567 rf->channel <= 14);
2568 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2569
2570 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2571
2572 if (rt2x00_rt(rt2x00dev, RT3572))
2573 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2574
2575 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2576 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2577 rt2800_bbp_write(rt2x00dev, 4, bbp);
2578
2579 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2580 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2581 rt2800_bbp_write(rt2x00dev, 3, bbp);
2582
2583 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2584 if (conf_is_ht40(conf)) {
2585 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2586 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2587 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2588 } else {
2589 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2590 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2591 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2592 }
2593 }
2594
2595 msleep(1);
2596
2597 /*
2598 * Clear channel statistic counters
2599 */
2600 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2601 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2602 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2603
2604 /*
2605 * Clear update flag
2606 */
2607 if (rt2x00_rt(rt2x00dev, RT3352)) {
2608 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2609 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2610 rt2800_bbp_write(rt2x00dev, 49, bbp);
2611 }
2612 }
2613
2614 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2615 {
2616 u8 tssi_bounds[9];
2617 u8 current_tssi;
2618 u16 eeprom;
2619 u8 step;
2620 int i;
2621
2622 /*
2623 * Read TSSI boundaries for temperature compensation from
2624 * the EEPROM.
2625 *
2626 * Array idx 0 1 2 3 4 5 6 7 8
2627 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2628 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2629 */
2630 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2631 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2632 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2633 EEPROM_TSSI_BOUND_BG1_MINUS4);
2634 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2635 EEPROM_TSSI_BOUND_BG1_MINUS3);
2636
2637 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2638 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2639 EEPROM_TSSI_BOUND_BG2_MINUS2);
2640 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2641 EEPROM_TSSI_BOUND_BG2_MINUS1);
2642
2643 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2644 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2645 EEPROM_TSSI_BOUND_BG3_REF);
2646 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2647 EEPROM_TSSI_BOUND_BG3_PLUS1);
2648
2649 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2650 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2651 EEPROM_TSSI_BOUND_BG4_PLUS2);
2652 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2653 EEPROM_TSSI_BOUND_BG4_PLUS3);
2654
2655 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2656 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2657 EEPROM_TSSI_BOUND_BG5_PLUS4);
2658
2659 step = rt2x00_get_field16(eeprom,
2660 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2661 } else {
2662 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2663 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2664 EEPROM_TSSI_BOUND_A1_MINUS4);
2665 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2666 EEPROM_TSSI_BOUND_A1_MINUS3);
2667
2668 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2669 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2670 EEPROM_TSSI_BOUND_A2_MINUS2);
2671 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2672 EEPROM_TSSI_BOUND_A2_MINUS1);
2673
2674 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2675 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2676 EEPROM_TSSI_BOUND_A3_REF);
2677 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2678 EEPROM_TSSI_BOUND_A3_PLUS1);
2679
2680 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2681 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2682 EEPROM_TSSI_BOUND_A4_PLUS2);
2683 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2684 EEPROM_TSSI_BOUND_A4_PLUS3);
2685
2686 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2687 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2688 EEPROM_TSSI_BOUND_A5_PLUS4);
2689
2690 step = rt2x00_get_field16(eeprom,
2691 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2692 }
2693
2694 /*
2695 * Check if temperature compensation is supported.
2696 */
2697 if (tssi_bounds[4] == 0xff || step == 0xff)
2698 return 0;
2699
2700 /*
2701 * Read current TSSI (BBP 49).
2702 */
2703 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2704
2705 /*
2706 * Compare TSSI value (BBP49) with the compensation boundaries
2707 * from the EEPROM and increase or decrease tx power.
2708 */
2709 for (i = 0; i <= 3; i++) {
2710 if (current_tssi > tssi_bounds[i])
2711 break;
2712 }
2713
2714 if (i == 4) {
2715 for (i = 8; i >= 5; i--) {
2716 if (current_tssi < tssi_bounds[i])
2717 break;
2718 }
2719 }
2720
2721 return (i - 4) * step;
2722 }
2723
2724 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2725 enum ieee80211_band band)
2726 {
2727 u16 eeprom;
2728 u8 comp_en;
2729 u8 comp_type;
2730 int comp_value = 0;
2731
2732 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2733
2734 /*
2735 * HT40 compensation not required.
2736 */
2737 if (eeprom == 0xffff ||
2738 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2739 return 0;
2740
2741 if (band == IEEE80211_BAND_2GHZ) {
2742 comp_en = rt2x00_get_field16(eeprom,
2743 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2744 if (comp_en) {
2745 comp_type = rt2x00_get_field16(eeprom,
2746 EEPROM_TXPOWER_DELTA_TYPE_2G);
2747 comp_value = rt2x00_get_field16(eeprom,
2748 EEPROM_TXPOWER_DELTA_VALUE_2G);
2749 if (!comp_type)
2750 comp_value = -comp_value;
2751 }
2752 } else {
2753 comp_en = rt2x00_get_field16(eeprom,
2754 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2755 if (comp_en) {
2756 comp_type = rt2x00_get_field16(eeprom,
2757 EEPROM_TXPOWER_DELTA_TYPE_5G);
2758 comp_value = rt2x00_get_field16(eeprom,
2759 EEPROM_TXPOWER_DELTA_VALUE_5G);
2760 if (!comp_type)
2761 comp_value = -comp_value;
2762 }
2763 }
2764
2765 return comp_value;
2766 }
2767
2768 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2769 int power_level, int max_power)
2770 {
2771 int delta;
2772
2773 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2774 return 0;
2775
2776 /*
2777 * XXX: We don't know the maximum transmit power of our hardware since
2778 * the EEPROM doesn't expose it. We only know that we are calibrated
2779 * to 100% tx power.
2780 *
2781 * Hence, we assume the regulatory limit that cfg80211 calulated for
2782 * the current channel is our maximum and if we are requested to lower
2783 * the value we just reduce our tx power accordingly.
2784 */
2785 delta = power_level - max_power;
2786 return min(delta, 0);
2787 }
2788
2789 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2790 enum ieee80211_band band, int power_level,
2791 u8 txpower, int delta)
2792 {
2793 u16 eeprom;
2794 u8 criterion;
2795 u8 eirp_txpower;
2796 u8 eirp_txpower_criterion;
2797 u8 reg_limit;
2798
2799 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2800 /*
2801 * Check if eirp txpower exceed txpower_limit.
2802 * We use OFDM 6M as criterion and its eirp txpower
2803 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2804 * .11b data rate need add additional 4dbm
2805 * when calculating eirp txpower.
2806 */
2807 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2808 &eeprom);
2809 criterion = rt2x00_get_field16(eeprom,
2810 EEPROM_TXPOWER_BYRATE_RATE0);
2811
2812 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2813 &eeprom);
2814
2815 if (band == IEEE80211_BAND_2GHZ)
2816 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2817 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2818 else
2819 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2820 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2821
2822 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2823 (is_rate_b ? 4 : 0) + delta;
2824
2825 reg_limit = (eirp_txpower > power_level) ?
2826 (eirp_txpower - power_level) : 0;
2827 } else
2828 reg_limit = 0;
2829
2830 txpower = max(0, txpower + delta - reg_limit);
2831 return min_t(u8, txpower, 0xc);
2832 }
2833
2834 /*
2835 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2836 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2837 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2838 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2839 * Reference per rate transmit power values are located in the EEPROM at
2840 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2841 * current conditions (i.e. band, bandwidth, temperature, user settings).
2842 */
2843 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2844 struct ieee80211_channel *chan,
2845 int power_level)
2846 {
2847 u8 txpower, r1;
2848 u16 eeprom;
2849 u32 reg, offset;
2850 int i, is_rate_b, delta, power_ctrl;
2851 enum ieee80211_band band = chan->band;
2852
2853 /*
2854 * Calculate HT40 compensation. For 40MHz we need to add or subtract
2855 * value read from EEPROM (different for 2GHz and for 5GHz).
2856 */
2857 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2858
2859 /*
2860 * Calculate temperature compensation. Depends on measurement of current
2861 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
2862 * to temperature or maybe other factors) is smaller or bigger than
2863 * expected. We adjust it, based on TSSI reference and boundaries values
2864 * provided in EEPROM.
2865 */
2866 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2867
2868 /*
2869 * Decrease power according to user settings, on devices with unknown
2870 * maximum tx power. For other devices we take user power_level into
2871 * consideration on rt2800_compensate_txpower().
2872 */
2873 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
2874 chan->max_power);
2875
2876 /*
2877 * BBP_R1 controls TX power for all rates, it allow to set the following
2878 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
2879 *
2880 * TODO: we do not use +6 dBm option to do not increase power beyond
2881 * regulatory limit, however this could be utilized for devices with
2882 * CAPABILITY_POWER_LIMIT.
2883 */
2884 rt2800_bbp_read(rt2x00dev, 1, &r1);
2885 if (delta <= -12) {
2886 power_ctrl = 2;
2887 delta += 12;
2888 } else if (delta <= -6) {
2889 power_ctrl = 1;
2890 delta += 6;
2891 } else {
2892 power_ctrl = 0;
2893 }
2894 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
2895 rt2800_bbp_write(rt2x00dev, 1, r1);
2896 offset = TX_PWR_CFG_0;
2897
2898 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2899 /* just to be safe */
2900 if (offset > TX_PWR_CFG_4)
2901 break;
2902
2903 rt2800_register_read(rt2x00dev, offset, &reg);
2904
2905 /* read the next four txpower values */
2906 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2907 &eeprom);
2908
2909 is_rate_b = i ? 0 : 1;
2910 /*
2911 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2912 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2913 * TX_PWR_CFG_4: unknown
2914 */
2915 txpower = rt2x00_get_field16(eeprom,
2916 EEPROM_TXPOWER_BYRATE_RATE0);
2917 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2918 power_level, txpower, delta);
2919 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2920
2921 /*
2922 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2923 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2924 * TX_PWR_CFG_4: unknown
2925 */
2926 txpower = rt2x00_get_field16(eeprom,
2927 EEPROM_TXPOWER_BYRATE_RATE1);
2928 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2929 power_level, txpower, delta);
2930 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2931
2932 /*
2933 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2934 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2935 * TX_PWR_CFG_4: unknown
2936 */
2937 txpower = rt2x00_get_field16(eeprom,
2938 EEPROM_TXPOWER_BYRATE_RATE2);
2939 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2940 power_level, txpower, delta);
2941 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2942
2943 /*
2944 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2945 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2946 * TX_PWR_CFG_4: unknown
2947 */
2948 txpower = rt2x00_get_field16(eeprom,
2949 EEPROM_TXPOWER_BYRATE_RATE3);
2950 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2951 power_level, txpower, delta);
2952 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2953
2954 /* read the next four txpower values */
2955 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2956 &eeprom);
2957
2958 is_rate_b = 0;
2959 /*
2960 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2961 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2962 * TX_PWR_CFG_4: unknown
2963 */
2964 txpower = rt2x00_get_field16(eeprom,
2965 EEPROM_TXPOWER_BYRATE_RATE0);
2966 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2967 power_level, txpower, delta);
2968 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2969
2970 /*
2971 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2972 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2973 * TX_PWR_CFG_4: unknown
2974 */
2975 txpower = rt2x00_get_field16(eeprom,
2976 EEPROM_TXPOWER_BYRATE_RATE1);
2977 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2978 power_level, txpower, delta);
2979 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2980
2981 /*
2982 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2983 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2984 * TX_PWR_CFG_4: unknown
2985 */
2986 txpower = rt2x00_get_field16(eeprom,
2987 EEPROM_TXPOWER_BYRATE_RATE2);
2988 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2989 power_level, txpower, delta);
2990 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2991
2992 /*
2993 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2994 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2995 * TX_PWR_CFG_4: unknown
2996 */
2997 txpower = rt2x00_get_field16(eeprom,
2998 EEPROM_TXPOWER_BYRATE_RATE3);
2999 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3000 power_level, txpower, delta);
3001 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3002
3003 rt2800_register_write(rt2x00dev, offset, reg);
3004
3005 /* next TX_PWR_CFG register */
3006 offset += 4;
3007 }
3008 }
3009
3010 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3011 {
3012 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3013 rt2x00dev->tx_power);
3014 }
3015 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3016
3017 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3018 {
3019 u32 tx_pin;
3020 u8 rfcsr;
3021
3022 /*
3023 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3024 * designed to be controlled in oscillation frequency by a voltage
3025 * input. Maybe the temperature will affect the frequency of
3026 * oscillation to be shifted. The VCO calibration will be called
3027 * periodically to adjust the frequency to be precision.
3028 */
3029
3030 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3031 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3032 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3033
3034 switch (rt2x00dev->chip.rf) {
3035 case RF2020:
3036 case RF3020:
3037 case RF3021:
3038 case RF3022:
3039 case RF3320:
3040 case RF3052:
3041 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3042 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3043 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3044 break;
3045 case RF3290:
3046 case RF5360:
3047 case RF5370:
3048 case RF5372:
3049 case RF5390:
3050 case RF5392:
3051 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3052 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3053 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3054 break;
3055 default:
3056 return;
3057 }
3058
3059 mdelay(1);
3060
3061 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3062 if (rt2x00dev->rf_channel <= 14) {
3063 switch (rt2x00dev->default_ant.tx_chain_num) {
3064 case 3:
3065 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3066 /* fall through */
3067 case 2:
3068 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3069 /* fall through */
3070 case 1:
3071 default:
3072 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3073 break;
3074 }
3075 } else {
3076 switch (rt2x00dev->default_ant.tx_chain_num) {
3077 case 3:
3078 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3079 /* fall through */
3080 case 2:
3081 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3082 /* fall through */
3083 case 1:
3084 default:
3085 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3086 break;
3087 }
3088 }
3089 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3090
3091 }
3092 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3093
3094 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3095 struct rt2x00lib_conf *libconf)
3096 {
3097 u32 reg;
3098
3099 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3100 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3101 libconf->conf->short_frame_max_tx_count);
3102 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3103 libconf->conf->long_frame_max_tx_count);
3104 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3105 }
3106
3107 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3108 struct rt2x00lib_conf *libconf)
3109 {
3110 enum dev_state state =
3111 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3112 STATE_SLEEP : STATE_AWAKE;
3113 u32 reg;
3114
3115 if (state == STATE_SLEEP) {
3116 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3117
3118 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3119 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3120 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3121 libconf->conf->listen_interval - 1);
3122 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3123 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3124
3125 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3126 } else {
3127 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3128 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3129 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3130 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3131 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3132
3133 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3134 }
3135 }
3136
3137 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3138 struct rt2x00lib_conf *libconf,
3139 const unsigned int flags)
3140 {
3141 /* Always recalculate LNA gain before changing configuration */
3142 rt2800_config_lna_gain(rt2x00dev, libconf);
3143
3144 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3145 rt2800_config_channel(rt2x00dev, libconf->conf,
3146 &libconf->rf, &libconf->channel);
3147 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3148 libconf->conf->power_level);
3149 }
3150 if (flags & IEEE80211_CONF_CHANGE_POWER)
3151 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3152 libconf->conf->power_level);
3153 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3154 rt2800_config_retry_limit(rt2x00dev, libconf);
3155 if (flags & IEEE80211_CONF_CHANGE_PS)
3156 rt2800_config_ps(rt2x00dev, libconf);
3157 }
3158 EXPORT_SYMBOL_GPL(rt2800_config);
3159
3160 /*
3161 * Link tuning
3162 */
3163 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3164 {
3165 u32 reg;
3166
3167 /*
3168 * Update FCS error count from register.
3169 */
3170 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3171 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3172 }
3173 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3174
3175 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3176 {
3177 u8 vgc;
3178
3179 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3180 if (rt2x00_rt(rt2x00dev, RT3070) ||
3181 rt2x00_rt(rt2x00dev, RT3071) ||
3182 rt2x00_rt(rt2x00dev, RT3090) ||
3183 rt2x00_rt(rt2x00dev, RT3290) ||
3184 rt2x00_rt(rt2x00dev, RT3390) ||
3185 rt2x00_rt(rt2x00dev, RT3572) ||
3186 rt2x00_rt(rt2x00dev, RT5390) ||
3187 rt2x00_rt(rt2x00dev, RT5392))
3188 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3189 else
3190 vgc = 0x2e + rt2x00dev->lna_gain;
3191 } else { /* 5GHZ band */
3192 if (rt2x00_rt(rt2x00dev, RT3572))
3193 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3194 else {
3195 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3196 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3197 else
3198 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3199 }
3200 }
3201
3202 return vgc;
3203 }
3204
3205 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3206 struct link_qual *qual, u8 vgc_level)
3207 {
3208 if (qual->vgc_level != vgc_level) {
3209 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3210 qual->vgc_level = vgc_level;
3211 qual->vgc_level_reg = vgc_level;
3212 }
3213 }
3214
3215 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3216 {
3217 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3218 }
3219 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3220
3221 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3222 const u32 count)
3223 {
3224 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3225 return;
3226
3227 /*
3228 * When RSSI is better then -80 increase VGC level with 0x10
3229 */
3230 rt2800_set_vgc(rt2x00dev, qual,
3231 rt2800_get_default_vgc(rt2x00dev) +
3232 ((qual->rssi > -80) * 0x10));
3233 }
3234 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3235
3236 /*
3237 * Initialization functions.
3238 */
3239 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3240 {
3241 u32 reg;
3242 u16 eeprom;
3243 unsigned int i;
3244 int ret;
3245
3246 rt2800_disable_wpdma(rt2x00dev);
3247
3248 ret = rt2800_drv_init_registers(rt2x00dev);
3249 if (ret)
3250 return ret;
3251
3252 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3253 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3254 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3255 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3256 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3257 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3258
3259 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3260 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3261 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3262 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3263 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3264 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3265
3266 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3267 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3268
3269 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3270
3271 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3273 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3274 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3275 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3276 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3277 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3278 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3279
3280 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3281
3282 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3283 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3284 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3285 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3286
3287 if (rt2x00_rt(rt2x00dev, RT3290)) {
3288 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3289 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3290 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3291 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3292 }
3293
3294 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3295 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3296 rt2x00_set_field32(&reg, LDO0_EN, 1);
3297 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3298 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3299 }
3300
3301 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3302 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3303 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3304 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3305 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3306
3307 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3308 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3309 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3310
3311 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3312 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3313 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3314 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3315 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3316 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3317
3318 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3319 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3320 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3321 }
3322
3323 if (rt2x00_rt(rt2x00dev, RT3071) ||
3324 rt2x00_rt(rt2x00dev, RT3090) ||
3325 rt2x00_rt(rt2x00dev, RT3290) ||
3326 rt2x00_rt(rt2x00dev, RT3390)) {
3327
3328 if (rt2x00_rt(rt2x00dev, RT3290))
3329 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3330 0x00000404);
3331 else
3332 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3333 0x00000400);
3334
3335 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3336 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3337 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3338 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3339 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3340 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3341 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3342 0x0000002c);
3343 else
3344 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3345 0x0000000f);
3346 } else {
3347 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3348 }
3349 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3350 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3351
3352 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3353 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3354 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3355 } else {
3356 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3357 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3358 }
3359 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3360 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3361 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3362 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3363 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3364 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3365 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3366 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3367 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3368 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3369 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3370 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3371 rt2x00_rt(rt2x00dev, RT5392) ||
3372 rt2x00_rt(rt2x00dev, RT5592)) {
3373 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3374 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3375 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3376 } else {
3377 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3378 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3379 }
3380
3381 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3382 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3383 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3384 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3385 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3386 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3387 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3388 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3389 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3390 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3391
3392 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3393 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3394 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3395 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3396 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3397
3398 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3399 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3400 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3401 rt2x00_rt(rt2x00dev, RT2883) ||
3402 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3403 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3404 else
3405 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3406 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3407 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3408 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3409
3410 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3411 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3412 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3413 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3414 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3415 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3416 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3417 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3418 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3419
3420 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3421
3422 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3423 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3424 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3425 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3426 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3427 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3428 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3429 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3430
3431 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3432 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3433 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3434 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3435 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3436 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3437 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3438 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3439 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3440
3441 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3442 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3443 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3444 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3445 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3446 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3447 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3448 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3449 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3450 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3451 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3452 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3453
3454 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3455 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3456 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3457 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3458 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3459 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3460 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3461 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3462 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3463 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3464 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3465 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3466
3467 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3468 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3469 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3470 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3471 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3472 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3473 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3474 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3475 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3476 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3477 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3478 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3479
3480 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3481 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3482 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3483 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3484 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3485 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3486 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3487 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3488 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3489 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3490 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3491 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3492
3493 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3494 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3495 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3496 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3497 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3498 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3499 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3500 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3501 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3502 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3503 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3504 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3505
3506 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3507 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3508 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3509 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3510 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3511 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3512 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3513 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3514 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3515 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3516 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3517 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3518
3519 if (rt2x00_is_usb(rt2x00dev)) {
3520 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3521
3522 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3526 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3527 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3528 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3529 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3530 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3531 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3532 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3533 }
3534
3535 /*
3536 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3537 * although it is reserved.
3538 */
3539 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3540 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3541 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3542 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3543 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3544 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3545 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3546 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3547 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3548 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3549 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3550 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3551
3552 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3553 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3554
3555 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3556 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3557 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3558 IEEE80211_MAX_RTS_THRESHOLD);
3559 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3560 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3561
3562 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3563
3564 /*
3565 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3566 * time should be set to 16. However, the original Ralink driver uses
3567 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3568 * connection problems with 11g + CTS protection. Hence, use the same
3569 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3570 */
3571 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3572 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3573 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3574 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3575 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3576 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3577 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3578
3579 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3580
3581 /*
3582 * ASIC will keep garbage value after boot, clear encryption keys.
3583 */
3584 for (i = 0; i < 4; i++)
3585 rt2800_register_write(rt2x00dev,
3586 SHARED_KEY_MODE_ENTRY(i), 0);
3587
3588 for (i = 0; i < 256; i++) {
3589 rt2800_config_wcid(rt2x00dev, NULL, i);
3590 rt2800_delete_wcid_attr(rt2x00dev, i);
3591 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3592 }
3593
3594 /*
3595 * Clear all beacons
3596 */
3597 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3598 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3599 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3600 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3601 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3602 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3603 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3604 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3605
3606 if (rt2x00_is_usb(rt2x00dev)) {
3607 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3608 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3609 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3610 } else if (rt2x00_is_pcie(rt2x00dev)) {
3611 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3612 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3613 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3614 }
3615
3616 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3617 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3618 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3619 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3620 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3621 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3622 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3623 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3624 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3625 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3626
3627 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3628 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3629 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3630 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3631 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3632 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3633 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3634 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3635 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3636 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3637
3638 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3639 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3640 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3641 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3642 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3643 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3644 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3645 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3646 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3647 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3648
3649 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3650 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3651 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3652 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3653 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3654 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3655
3656 /*
3657 * Do not force the BA window size, we use the TXWI to set it
3658 */
3659 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3660 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3661 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3662 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3663
3664 /*
3665 * We must clear the error counters.
3666 * These registers are cleared on read,
3667 * so we may pass a useless variable to store the value.
3668 */
3669 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3670 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3671 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3672 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3673 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3674 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3675
3676 /*
3677 * Setup leadtime for pre tbtt interrupt to 6ms
3678 */
3679 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3680 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3681 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3682
3683 /*
3684 * Set up channel statistics timer
3685 */
3686 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3687 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3688 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3689 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3690 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3691 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3692 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3693
3694 return 0;
3695 }
3696
3697 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3698 {
3699 unsigned int i;
3700 u32 reg;
3701
3702 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3703 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3704 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3705 return 0;
3706
3707 udelay(REGISTER_BUSY_DELAY);
3708 }
3709
3710 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3711 return -EACCES;
3712 }
3713
3714 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3715 {
3716 unsigned int i;
3717 u8 value;
3718
3719 /*
3720 * BBP was enabled after firmware was loaded,
3721 * but we need to reactivate it now.
3722 */
3723 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3724 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3725 msleep(1);
3726
3727 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3728 rt2800_bbp_read(rt2x00dev, 0, &value);
3729 if ((value != 0xff) && (value != 0x00))
3730 return 0;
3731 udelay(REGISTER_BUSY_DELAY);
3732 }
3733
3734 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3735 return -EACCES;
3736 }
3737
3738 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3739 {
3740 u8 value;
3741
3742 rt2800_bbp_read(rt2x00dev, 4, &value);
3743 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3744 rt2800_bbp_write(rt2x00dev, 4, value);
3745 }
3746
3747 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3748 {
3749 rt2800_bbp_write(rt2x00dev, 142, 1);
3750 rt2800_bbp_write(rt2x00dev, 143, 57);
3751 }
3752
3753 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3754 {
3755 const u8 glrt_table[] = {
3756 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3757 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3758 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3759 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3760 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3761 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3762 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3763 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3764 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3765 };
3766 int i;
3767
3768 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3769 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3770 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3771 }
3772 };
3773
3774 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3775 {
3776 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3777 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3778 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3779 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3780 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3781 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3782 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3783 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3784 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3785 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3786 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3787 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3788 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3789 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3790 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3791 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3792 }
3793
3794 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3795 {
3796 int ant, div_mode;
3797 u16 eeprom;
3798 u8 value;
3799
3800 rt2800_init_bbb_early(rt2x00dev);
3801
3802 rt2800_bbp_read(rt2x00dev, 105, &value);
3803 rt2x00_set_field8(&value, BBP105_MLD,
3804 rt2x00dev->default_ant.rx_chain_num == 2);
3805 rt2800_bbp_write(rt2x00dev, 105, value);
3806
3807 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3808
3809 rt2800_bbp_write(rt2x00dev, 20, 0x06);
3810 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3811 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3812 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3813 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3814 rt2800_bbp_write(rt2x00dev, 70, 0x05);
3815 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3816 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3817 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3818 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3819 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3820 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3821 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3822 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3823 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3824 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3825 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3826 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3827 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3828 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3829 /* FIXME BBP105 owerwrite */
3830 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3831 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3832 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3833 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3834 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3835 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3836
3837 /* Initialize GLRT (Generalized Likehood Radio Test) */
3838 rt2800_init_bbp_5592_glrt(rt2x00dev);
3839
3840 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3841
3842 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3843 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3844 ant = (div_mode == 3) ? 1 : 0;
3845 rt2800_bbp_read(rt2x00dev, 152, &value);
3846 if (ant == 0) {
3847 /* Main antenna */
3848 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3849 } else {
3850 /* Auxiliary antenna */
3851 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3852 }
3853 rt2800_bbp_write(rt2x00dev, 152, value);
3854
3855 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
3856 rt2800_bbp_read(rt2x00dev, 254, &value);
3857 rt2x00_set_field8(&value, BBP254_BIT7, 1);
3858 rt2800_bbp_write(rt2x00dev, 254, value);
3859 }
3860
3861 rt2800_init_freq_calibration(rt2x00dev);
3862
3863 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3864 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
3865 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3866 }
3867
3868 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3869 {
3870 unsigned int i;
3871 u16 eeprom;
3872 u8 reg_id;
3873 u8 value;
3874
3875 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3876 rt2800_wait_bbp_ready(rt2x00dev)))
3877 return -EACCES;
3878
3879 if (rt2x00_rt(rt2x00dev, RT5592)) {
3880 rt2800_init_bbp_5592(rt2x00dev);
3881 return 0;
3882 }
3883
3884 if (rt2x00_rt(rt2x00dev, RT3352)) {
3885 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3886 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3887 }
3888
3889 if (rt2x00_rt(rt2x00dev, RT3290) ||
3890 rt2x00_rt(rt2x00dev, RT5390) ||
3891 rt2x00_rt(rt2x00dev, RT5392))
3892 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3893
3894 if (rt2800_is_305x_soc(rt2x00dev) ||
3895 rt2x00_rt(rt2x00dev, RT3290) ||
3896 rt2x00_rt(rt2x00dev, RT3352) ||
3897 rt2x00_rt(rt2x00dev, RT3572) ||
3898 rt2x00_rt(rt2x00dev, RT5390) ||
3899 rt2x00_rt(rt2x00dev, RT5392))
3900 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3901
3902 if (rt2x00_rt(rt2x00dev, RT3352))
3903 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3904
3905 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3906 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3907
3908 if (rt2x00_rt(rt2x00dev, RT3290) ||
3909 rt2x00_rt(rt2x00dev, RT3352) ||
3910 rt2x00_rt(rt2x00dev, RT5390) ||
3911 rt2x00_rt(rt2x00dev, RT5392))
3912 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3913
3914 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3915 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3916 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3917 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3918 rt2x00_rt(rt2x00dev, RT3352) ||
3919 rt2x00_rt(rt2x00dev, RT5390) ||
3920 rt2x00_rt(rt2x00dev, RT5392)) {
3921 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3922 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3923 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3924 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3925
3926 if (rt2x00_rt(rt2x00dev, RT3290))
3927 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3928 else
3929 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3930 } else {
3931 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3932 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3933 }
3934
3935 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3936
3937 if (rt2x00_rt(rt2x00dev, RT3070) ||
3938 rt2x00_rt(rt2x00dev, RT3071) ||
3939 rt2x00_rt(rt2x00dev, RT3090) ||
3940 rt2x00_rt(rt2x00dev, RT3390) ||
3941 rt2x00_rt(rt2x00dev, RT3572) ||
3942 rt2x00_rt(rt2x00dev, RT5390) ||
3943 rt2x00_rt(rt2x00dev, RT5392)) {
3944 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3945 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3946 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3947 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3948 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3949 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3950 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3951 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3952 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3953 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3954 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3955 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3956 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3957 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3958 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3959 } else {
3960 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3961 }
3962
3963 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3964 if (rt2x00_rt(rt2x00dev, RT3290) ||
3965 rt2x00_rt(rt2x00dev, RT5390) ||
3966 rt2x00_rt(rt2x00dev, RT5392))
3967 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3968 else
3969 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3970
3971 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3972 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3973 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3974 rt2x00_rt(rt2x00dev, RT5390) ||
3975 rt2x00_rt(rt2x00dev, RT5392))
3976 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3977 else
3978 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3979
3980 if (rt2x00_rt(rt2x00dev, RT3290) ||
3981 rt2x00_rt(rt2x00dev, RT3352) ||
3982 rt2x00_rt(rt2x00dev, RT5390) ||
3983 rt2x00_rt(rt2x00dev, RT5392))
3984 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3985 else
3986 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3987
3988 if (rt2x00_rt(rt2x00dev, RT3352) ||
3989 rt2x00_rt(rt2x00dev, RT5392))
3990 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3991
3992 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3993
3994 if (rt2x00_rt(rt2x00dev, RT3290) ||
3995 rt2x00_rt(rt2x00dev, RT3352) ||
3996 rt2x00_rt(rt2x00dev, RT5390) ||
3997 rt2x00_rt(rt2x00dev, RT5392))
3998 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3999 else
4000 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4001
4002 if (rt2x00_rt(rt2x00dev, RT5392)) {
4003 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4004 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4005 }
4006
4007 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4008 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4009 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4010 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4011 rt2x00_rt(rt2x00dev, RT3290) ||
4012 rt2x00_rt(rt2x00dev, RT3352) ||
4013 rt2x00_rt(rt2x00dev, RT3572) ||
4014 rt2x00_rt(rt2x00dev, RT5390) ||
4015 rt2x00_rt(rt2x00dev, RT5392) ||
4016 rt2800_is_305x_soc(rt2x00dev))
4017 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4018 else
4019 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4020
4021 if (rt2x00_rt(rt2x00dev, RT3290) ||
4022 rt2x00_rt(rt2x00dev, RT3352) ||
4023 rt2x00_rt(rt2x00dev, RT5390) ||
4024 rt2x00_rt(rt2x00dev, RT5392))
4025 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4026
4027 if (rt2800_is_305x_soc(rt2x00dev))
4028 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4029 else if (rt2x00_rt(rt2x00dev, RT3290))
4030 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4031 else if (rt2x00_rt(rt2x00dev, RT3352))
4032 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4033 else if (rt2x00_rt(rt2x00dev, RT5390) ||
4034 rt2x00_rt(rt2x00dev, RT5392))
4035 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4036 else
4037 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4038
4039 if (rt2x00_rt(rt2x00dev, RT3290) ||
4040 rt2x00_rt(rt2x00dev, RT5390))
4041 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4042 else if (rt2x00_rt(rt2x00dev, RT3352))
4043 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4044 else if (rt2x00_rt(rt2x00dev, RT5392))
4045 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4046 else
4047 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4048
4049 if (rt2x00_rt(rt2x00dev, RT3352))
4050 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4051
4052 if (rt2x00_rt(rt2x00dev, RT3290) ||
4053 rt2x00_rt(rt2x00dev, RT5390) ||
4054 rt2x00_rt(rt2x00dev, RT5392))
4055 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4056
4057 if (rt2x00_rt(rt2x00dev, RT5392)) {
4058 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4059 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4060 }
4061
4062 if (rt2x00_rt(rt2x00dev, RT3352))
4063 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4064
4065 if (rt2x00_rt(rt2x00dev, RT3071) ||
4066 rt2x00_rt(rt2x00dev, RT3090) ||
4067 rt2x00_rt(rt2x00dev, RT3390) ||
4068 rt2x00_rt(rt2x00dev, RT3572) ||
4069 rt2x00_rt(rt2x00dev, RT5390) ||
4070 rt2x00_rt(rt2x00dev, RT5392)) {
4071 rt2800_bbp_read(rt2x00dev, 138, &value);
4072
4073 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4074 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4075 value |= 0x20;
4076 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4077 value &= ~0x02;
4078
4079 rt2800_bbp_write(rt2x00dev, 138, value);
4080 }
4081
4082 if (rt2x00_rt(rt2x00dev, RT3290)) {
4083 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4084 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4085 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4086 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4087 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4088 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4089 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4090 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4091 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4092 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4093
4094 rt2800_bbp_read(rt2x00dev, 47, &value);
4095 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4096 rt2800_bbp_write(rt2x00dev, 47, value);
4097
4098 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4099 rt2800_bbp_read(rt2x00dev, 3, &value);
4100 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4101 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4102 rt2800_bbp_write(rt2x00dev, 3, value);
4103 }
4104
4105 if (rt2x00_rt(rt2x00dev, RT3352)) {
4106 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4107 /* Set ITxBF timeout to 0x9c40=1000msec */
4108 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4109 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4110 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4111 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4112 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4113 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4114 /* Reprogram the inband interface to put right values in RXWI */
4115 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4116 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4117 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4118 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4119 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4120 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4121 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4122 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4123
4124 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4125 }
4126
4127 if (rt2x00_rt(rt2x00dev, RT5390) ||
4128 rt2x00_rt(rt2x00dev, RT5392)) {
4129 int ant, div_mode;
4130
4131 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4132 div_mode = rt2x00_get_field16(eeprom,
4133 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4134 ant = (div_mode == 3) ? 1 : 0;
4135
4136 /* check if this is a Bluetooth combo card */
4137 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4138 u32 reg;
4139
4140 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4141 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4142 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4143 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4144 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4145 if (ant == 0)
4146 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4147 else if (ant == 1)
4148 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4149 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4150 }
4151
4152 /* This chip has hardware antenna diversity*/
4153 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4154 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4155 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4156 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4157 }
4158
4159 rt2800_bbp_read(rt2x00dev, 152, &value);
4160 if (ant == 0)
4161 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4162 else
4163 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4164 rt2800_bbp_write(rt2x00dev, 152, value);
4165
4166 rt2800_init_freq_calibration(rt2x00dev);
4167 }
4168
4169 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4170 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4171
4172 if (eeprom != 0xffff && eeprom != 0x0000) {
4173 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4174 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4175 rt2800_bbp_write(rt2x00dev, reg_id, value);
4176 }
4177 }
4178
4179 return 0;
4180 }
4181
4182 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4183 bool bw40, u8 rfcsr24, u8 filter_target)
4184 {
4185 unsigned int i;
4186 u8 bbp;
4187 u8 rfcsr;
4188 u8 passband;
4189 u8 stopband;
4190 u8 overtuned = 0;
4191
4192 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4193
4194 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4195 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4196 rt2800_bbp_write(rt2x00dev, 4, bbp);
4197
4198 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4199 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4200 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4201
4202 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4203 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4204 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4205
4206 /*
4207 * Set power & frequency of passband test tone
4208 */
4209 rt2800_bbp_write(rt2x00dev, 24, 0);
4210
4211 for (i = 0; i < 100; i++) {
4212 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4213 msleep(1);
4214
4215 rt2800_bbp_read(rt2x00dev, 55, &passband);
4216 if (passband)
4217 break;
4218 }
4219
4220 /*
4221 * Set power & frequency of stopband test tone
4222 */
4223 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4224
4225 for (i = 0; i < 100; i++) {
4226 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4227 msleep(1);
4228
4229 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4230
4231 if ((passband - stopband) <= filter_target) {
4232 rfcsr24++;
4233 overtuned += ((passband - stopband) == filter_target);
4234 } else
4235 break;
4236
4237 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4238 }
4239
4240 rfcsr24 -= !!overtuned;
4241
4242 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4243 return rfcsr24;
4244 }
4245
4246 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4247 {
4248 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4249 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4250 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4251 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4252 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4253 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4254 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4255 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4256 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4257 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4258 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4259 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4260 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4261 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4262 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4263 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4264 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4265 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4266 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4267 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4268 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4269 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4270 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4271 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4272 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4273 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4274 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4275 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4276 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4277 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4278 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4279 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4280 }
4281
4282 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4283 {
4284 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4285 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4286 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4287 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4288 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4289 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4290 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4291 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4292 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4293 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4294 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4295 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4296 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4297 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4298 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4299 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4300 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4301 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4302 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4303 }
4304
4305 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4306 {
4307 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4308 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4309 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4310 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4311 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4312 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4313 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4314 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4315 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4316 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4317 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4318 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4319 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4320 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4321 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4322 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4323 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4324 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4325 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4326 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4327 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4328 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4329 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4330 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4331 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4332 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4333 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4334 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4335 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4336 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4337 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4338 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4339 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4340 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4341 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4342 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4343 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4344 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4345 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4346 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4347 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4348 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4349 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4350 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4351 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4352 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4353 }
4354
4355 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4356 {
4357 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4358 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4359 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4360 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4361 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4362 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4363 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4364 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4365 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4366 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4367 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4368 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4369 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4370 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4371 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4372 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4373 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4374 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4375 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4376 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4377 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4378 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4379 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4380 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4381 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4382 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4383 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4384 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4385 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4386 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4387 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4388 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4389 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4390 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4391 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4392 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4393 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4394 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4395 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4396 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4397 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4398 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4399 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4400 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4401 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4402 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4403 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4404 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4405 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4406 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4407 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4408 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4409 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4410 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4411 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4412 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4413 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4414 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4415 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4416 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4417 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4418 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4419 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4420 }
4421
4422 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4423 {
4424 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4425 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4426 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4427 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4428 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4429 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4430 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4431 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4432 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4433 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4434 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4435 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4436 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4437 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4438 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4439 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4440 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4441 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4442 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4443 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4444 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4445 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4446 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4447 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4448 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4449 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4450 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4451 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4452 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4453 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4454 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4455 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4456 }
4457
4458 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4459 {
4460 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4461 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4462 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4463 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4464 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4465 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4466 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4467 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4468 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4469 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4470 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4471 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4472 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4473 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4474 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4475 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4476 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4477 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4478 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4479 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4480 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4481 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4482 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4483 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4484 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4485 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4486 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4487 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4488 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4489 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4490 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4491 }
4492
4493 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4494 {
4495 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4496 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4497 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4498 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4499 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4500 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4501 else
4502 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4503 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4504 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4505 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4506 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4507 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4508 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4509 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4510 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4511 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4512 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4513
4514 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4515 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4516 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4517 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4518 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4519 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4520 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4521 else
4522 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4523 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4524 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4525 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4526 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4527
4528 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4529 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4530 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4531 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4532 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4533 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4534 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4535 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4536 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4537 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4538
4539 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4540 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4541 else
4542 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4543 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4544 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4545 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4546 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4547 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4548 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4549 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4550 else
4551 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4552 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4553 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4554 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4555
4556 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4557 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4558 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4559 else
4560 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4561 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4562 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4563 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4564 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4565 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4566 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4567
4568 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4569 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4570 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4571 else
4572 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4573 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4574 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4575 }
4576
4577 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4578 {
4579 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4580 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4581 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4582 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4583 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4584 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4585 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4586 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4587 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4588 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4589 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4590 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4591 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4592 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4593 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4594 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4595 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4596 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4597 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4598 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4599 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4600 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4601 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4602 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4603 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4604 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4605 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4606 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4607 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4608 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4609 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4610 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4611 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4612 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4613 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4614 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4615 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4616 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4617 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4618 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4619 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4620 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4621 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4622 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4623 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4624 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4625 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4626 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4627 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4628 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4629 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4630 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4631 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4632 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4633 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4634 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4635 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4636 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4637 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4638 }
4639
4640 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4641 {
4642 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4643 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4644 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4645 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4646 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4647 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4648 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4649 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4650 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4651 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4652 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4653 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4654 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4655 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4656 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4657 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4658 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4659 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4660 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4661 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4662 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4663 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4664
4665 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4666 msleep(1);
4667
4668 rt2800_adjust_freq_offset(rt2x00dev);
4669 }
4670
4671 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4672 {
4673 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4674 u8 rfcsr;
4675 u8 bbp;
4676 u32 reg;
4677 u16 eeprom;
4678
4679 if (!rt2x00_rt(rt2x00dev, RT3070) &&
4680 !rt2x00_rt(rt2x00dev, RT3071) &&
4681 !rt2x00_rt(rt2x00dev, RT3090) &&
4682 !rt2x00_rt(rt2x00dev, RT3290) &&
4683 !rt2x00_rt(rt2x00dev, RT3352) &&
4684 !rt2x00_rt(rt2x00dev, RT3390) &&
4685 !rt2x00_rt(rt2x00dev, RT3572) &&
4686 !rt2x00_rt(rt2x00dev, RT5390) &&
4687 !rt2x00_rt(rt2x00dev, RT5392) &&
4688 !rt2x00_rt(rt2x00dev, RT5392) &&
4689 !rt2800_is_305x_soc(rt2x00dev))
4690 return 0;
4691
4692 /*
4693 * Init RF calibration.
4694 */
4695
4696 if (rt2x00_rt(rt2x00dev, RT3290) ||
4697 rt2x00_rt(rt2x00dev, RT5390) ||
4698 rt2x00_rt(rt2x00dev, RT5392)) {
4699 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4700 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4701 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4702 msleep(1);
4703 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4704 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4705 } else {
4706 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4707 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4708 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4709 msleep(1);
4710 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4711 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4712 }
4713
4714 if (rt2800_is_305x_soc(rt2x00dev)) {
4715 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4716 return 0;
4717 }
4718
4719 switch (rt2x00dev->chip.rt) {
4720 case RT3070:
4721 case RT3071:
4722 case RT3090:
4723 rt2800_init_rfcsr_30xx(rt2x00dev);
4724 break;
4725 case RT3290:
4726 rt2800_init_rfcsr_3290(rt2x00dev);
4727 break;
4728 case RT3352:
4729 rt2800_init_rfcsr_3352(rt2x00dev);
4730 break;
4731 case RT3390:
4732 rt2800_init_rfcsr_3390(rt2x00dev);
4733 break;
4734 case RT3572:
4735 rt2800_init_rfcsr_3572(rt2x00dev);
4736 break;
4737 case RT5390:
4738 rt2800_init_rfcsr_5390(rt2x00dev);
4739 break;
4740 case RT5392:
4741 rt2800_init_rfcsr_5392(rt2x00dev);
4742 break;
4743 case RT5592:
4744 rt2800_init_rfcsr_5592(rt2x00dev);
4745 break;
4746 }
4747
4748 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4749 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4750 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4751 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4752 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4753 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4754 rt2x00_rt(rt2x00dev, RT3090)) {
4755 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4756
4757 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4758 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4759 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4760
4761 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4762 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4763 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4764 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4765 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4766 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4767 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4768 else
4769 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4770 }
4771 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4772
4773 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4774 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4775 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4776 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4777 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4778 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4779 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4780 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4781 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4782 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4783 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4784
4785 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4786 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4787 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4788 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4789 msleep(1);
4790 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4791 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4792 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4793 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4794 }
4795
4796 /*
4797 * Set RX Filter calibration for 20MHz and 40MHz
4798 */
4799 if (rt2x00_rt(rt2x00dev, RT3070)) {
4800 drv_data->calibration_bw20 =
4801 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4802 drv_data->calibration_bw40 =
4803 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4804 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4805 rt2x00_rt(rt2x00dev, RT3090) ||
4806 rt2x00_rt(rt2x00dev, RT3352) ||
4807 rt2x00_rt(rt2x00dev, RT3390) ||
4808 rt2x00_rt(rt2x00dev, RT3572)) {
4809 drv_data->calibration_bw20 =
4810 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4811 drv_data->calibration_bw40 =
4812 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4813 }
4814
4815 /*
4816 * Save BBP 25 & 26 values for later use in channel switching
4817 */
4818 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4819 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4820
4821 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4822 !rt2x00_rt(rt2x00dev, RT5392)) {
4823 /*
4824 * Set back to initial state
4825 */
4826 rt2800_bbp_write(rt2x00dev, 24, 0);
4827
4828 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4829 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4830 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4831
4832 /*
4833 * Set BBP back to BW20
4834 */
4835 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4836 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4837 rt2800_bbp_write(rt2x00dev, 4, bbp);
4838 }
4839
4840 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4841 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4842 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4843 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
4844 rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4845 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4846
4847 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4848 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4849 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4850
4851 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4852 !rt2x00_rt(rt2x00dev, RT5392)) {
4853 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4854 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4855 if (rt2x00_rt(rt2x00dev, RT3070) ||
4856 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4857 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4858 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4859 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4860 &rt2x00dev->cap_flags))
4861 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4862 }
4863 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4864 drv_data->txmixer_gain_24g);
4865 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4866 }
4867
4868 if (rt2x00_rt(rt2x00dev, RT3090) ||
4869 rt2x00_rt(rt2x00dev, RT5592)) {
4870 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4871
4872 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4873 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4874 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4875 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4876 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4877 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4878
4879 rt2800_bbp_write(rt2x00dev, 138, bbp);
4880 }
4881
4882 if (rt2x00_rt(rt2x00dev, RT3071) ||
4883 rt2x00_rt(rt2x00dev, RT3090) ||
4884 rt2x00_rt(rt2x00dev, RT3390)) {
4885 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4886 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4887 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4888 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4889 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4890 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4891 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4892
4893 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4894 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4895 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4896
4897 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4898 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4899 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4900
4901 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4902 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4903 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4904 }
4905
4906 if (rt2x00_rt(rt2x00dev, RT3070)) {
4907 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4908 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4909 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4910 else
4911 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4912 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4913 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4914 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4915 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4916 }
4917
4918 if (rt2x00_rt(rt2x00dev, RT3290)) {
4919 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4920 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4921 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4922 }
4923
4924 if (rt2x00_rt(rt2x00dev, RT5390) ||
4925 rt2x00_rt(rt2x00dev, RT5392) ||
4926 rt2x00_rt(rt2x00dev, RT5592)) {
4927 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4928 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4929 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4930
4931 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4932 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4933 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4934
4935 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4936 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4937 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4938 }
4939
4940 return 0;
4941 }
4942
4943 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4944 {
4945 u32 reg;
4946 u16 word;
4947
4948 /*
4949 * Initialize all registers.
4950 */
4951 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4952 rt2800_init_registers(rt2x00dev) ||
4953 rt2800_init_bbp(rt2x00dev) ||
4954 rt2800_init_rfcsr(rt2x00dev)))
4955 return -EIO;
4956
4957 /*
4958 * Send signal to firmware during boot time.
4959 */
4960 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4961
4962 if (rt2x00_is_usb(rt2x00dev) &&
4963 (rt2x00_rt(rt2x00dev, RT3070) ||
4964 rt2x00_rt(rt2x00dev, RT3071) ||
4965 rt2x00_rt(rt2x00dev, RT3572))) {
4966 udelay(200);
4967 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4968 udelay(10);
4969 }
4970
4971 /*
4972 * Enable RX.
4973 */
4974 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4975 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4976 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4977 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4978
4979 udelay(50);
4980
4981 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4982 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4983 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4984 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4985 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4986 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4987
4988 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4989 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4990 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4991 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4992
4993 /*
4994 * Initialize LED control
4995 */
4996 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4997 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4998 word & 0xff, (word >> 8) & 0xff);
4999
5000 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5001 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5002 word & 0xff, (word >> 8) & 0xff);
5003
5004 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5005 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5006 word & 0xff, (word >> 8) & 0xff);
5007
5008 return 0;
5009 }
5010 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5011
5012 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5013 {
5014 u32 reg;
5015
5016 rt2800_disable_wpdma(rt2x00dev);
5017
5018 /* Wait for DMA, ignore error */
5019 rt2800_wait_wpdma_ready(rt2x00dev);
5020
5021 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5022 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5023 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5024 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5025 }
5026 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5027
5028 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5029 {
5030 u32 reg;
5031 u16 efuse_ctrl_reg;
5032
5033 if (rt2x00_rt(rt2x00dev, RT3290))
5034 efuse_ctrl_reg = EFUSE_CTRL_3290;
5035 else
5036 efuse_ctrl_reg = EFUSE_CTRL;
5037
5038 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5039 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5040 }
5041 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5042
5043 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5044 {
5045 u32 reg;
5046 u16 efuse_ctrl_reg;
5047 u16 efuse_data0_reg;
5048 u16 efuse_data1_reg;
5049 u16 efuse_data2_reg;
5050 u16 efuse_data3_reg;
5051
5052 if (rt2x00_rt(rt2x00dev, RT3290)) {
5053 efuse_ctrl_reg = EFUSE_CTRL_3290;
5054 efuse_data0_reg = EFUSE_DATA0_3290;
5055 efuse_data1_reg = EFUSE_DATA1_3290;
5056 efuse_data2_reg = EFUSE_DATA2_3290;
5057 efuse_data3_reg = EFUSE_DATA3_3290;
5058 } else {
5059 efuse_ctrl_reg = EFUSE_CTRL;
5060 efuse_data0_reg = EFUSE_DATA0;
5061 efuse_data1_reg = EFUSE_DATA1;
5062 efuse_data2_reg = EFUSE_DATA2;
5063 efuse_data3_reg = EFUSE_DATA3;
5064 }
5065 mutex_lock(&rt2x00dev->csr_mutex);
5066
5067 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5068 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5069 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5070 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5071 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5072
5073 /* Wait until the EEPROM has been loaded */
5074 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5075 /* Apparently the data is read from end to start */
5076 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5077 /* The returned value is in CPU order, but eeprom is le */
5078 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5079 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5080 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5081 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5082 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5083 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5084 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5085
5086 mutex_unlock(&rt2x00dev->csr_mutex);
5087 }
5088
5089 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5090 {
5091 unsigned int i;
5092
5093 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5094 rt2800_efuse_read(rt2x00dev, i);
5095
5096 return 0;
5097 }
5098 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5099
5100 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5101 {
5102 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5103 u16 word;
5104 u8 *mac;
5105 u8 default_lna_gain;
5106 int retval;
5107
5108 /*
5109 * Read the EEPROM.
5110 */
5111 retval = rt2800_read_eeprom(rt2x00dev);
5112 if (retval)
5113 return retval;
5114
5115 /*
5116 * Start validation of the data that has been read.
5117 */
5118 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5119 if (!is_valid_ether_addr(mac)) {
5120 eth_random_addr(mac);
5121 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5122 }
5123
5124 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5125 if (word == 0xffff) {
5126 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5127 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5128 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5129 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5130 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5131 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5132 rt2x00_rt(rt2x00dev, RT2872)) {
5133 /*
5134 * There is a max of 2 RX streams for RT28x0 series
5135 */
5136 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5137 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5138 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5139 }
5140
5141 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5142 if (word == 0xffff) {
5143 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5144 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5145 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5146 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5147 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5148 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5149 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5150 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5151 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5152 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5153 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5154 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5155 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5156 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5157 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5158 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5159 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5160 }
5161
5162 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5163 if ((word & 0x00ff) == 0x00ff) {
5164 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5165 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5166 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5167 }
5168 if ((word & 0xff00) == 0xff00) {
5169 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5170 LED_MODE_TXRX_ACTIVITY);
5171 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5172 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5173 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5174 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5175 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5176 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5177 }
5178
5179 /*
5180 * During the LNA validation we are going to use
5181 * lna0 as correct value. Note that EEPROM_LNA
5182 * is never validated.
5183 */
5184 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5185 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5186
5187 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5188 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5189 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5190 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5191 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5192 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5193
5194 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5195 if ((word & 0x00ff) != 0x00ff) {
5196 drv_data->txmixer_gain_24g =
5197 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5198 } else {
5199 drv_data->txmixer_gain_24g = 0;
5200 }
5201
5202 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5203 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5204 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5205 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5206 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5207 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5208 default_lna_gain);
5209 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5210
5211 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5212 if ((word & 0x00ff) != 0x00ff) {
5213 drv_data->txmixer_gain_5g =
5214 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5215 } else {
5216 drv_data->txmixer_gain_5g = 0;
5217 }
5218
5219 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5220 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5221 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5222 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5223 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5224 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5225
5226 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5227 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5228 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5229 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5230 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5231 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5232 default_lna_gain);
5233 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5234
5235 return 0;
5236 }
5237
5238 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5239 {
5240 u32 reg;
5241 u16 value;
5242 u16 eeprom;
5243
5244 /*
5245 * Read EEPROM word for configuration.
5246 */
5247 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5248
5249 /*
5250 * Identify RF chipset by EEPROM value
5251 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5252 * RT53xx: defined in "EEPROM_CHIP_ID" field
5253 */
5254 if (rt2x00_rt(rt2x00dev, RT3290))
5255 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5256 else
5257 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5258
5259 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5260 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5261 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5262 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5263 else
5264 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5265
5266 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5267 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5268
5269 switch (rt2x00dev->chip.rt) {
5270 case RT2860:
5271 case RT2872:
5272 case RT2883:
5273 case RT3070:
5274 case RT3071:
5275 case RT3090:
5276 case RT3290:
5277 case RT3352:
5278 case RT3390:
5279 case RT3572:
5280 case RT5390:
5281 case RT5392:
5282 case RT5592:
5283 break;
5284 default:
5285 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5286 return -ENODEV;
5287 }
5288
5289 switch (rt2x00dev->chip.rf) {
5290 case RF2820:
5291 case RF2850:
5292 case RF2720:
5293 case RF2750:
5294 case RF3020:
5295 case RF2020:
5296 case RF3021:
5297 case RF3022:
5298 case RF3052:
5299 case RF3290:
5300 case RF3320:
5301 case RF3322:
5302 case RF5360:
5303 case RF5370:
5304 case RF5372:
5305 case RF5390:
5306 case RF5392:
5307 case RF5592:
5308 break;
5309 default:
5310 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5311 rt2x00dev->chip.rf);
5312 return -ENODEV;
5313 }
5314
5315 /*
5316 * Identify default antenna configuration.
5317 */
5318 rt2x00dev->default_ant.tx_chain_num =
5319 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5320 rt2x00dev->default_ant.rx_chain_num =
5321 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5322
5323 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5324
5325 if (rt2x00_rt(rt2x00dev, RT3070) ||
5326 rt2x00_rt(rt2x00dev, RT3090) ||
5327 rt2x00_rt(rt2x00dev, RT3352) ||
5328 rt2x00_rt(rt2x00dev, RT3390)) {
5329 value = rt2x00_get_field16(eeprom,
5330 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5331 switch (value) {
5332 case 0:
5333 case 1:
5334 case 2:
5335 rt2x00dev->default_ant.tx = ANTENNA_A;
5336 rt2x00dev->default_ant.rx = ANTENNA_A;
5337 break;
5338 case 3:
5339 rt2x00dev->default_ant.tx = ANTENNA_A;
5340 rt2x00dev->default_ant.rx = ANTENNA_B;
5341 break;
5342 }
5343 } else {
5344 rt2x00dev->default_ant.tx = ANTENNA_A;
5345 rt2x00dev->default_ant.rx = ANTENNA_A;
5346 }
5347
5348 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5349 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5350 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5351 }
5352
5353 /*
5354 * Determine external LNA informations.
5355 */
5356 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5357 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5358 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5359 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5360
5361 /*
5362 * Detect if this device has an hardware controlled radio.
5363 */
5364 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5365 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5366
5367 /*
5368 * Detect if this device has Bluetooth co-existence.
5369 */
5370 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5371 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5372
5373 /*
5374 * Read frequency offset and RF programming sequence.
5375 */
5376 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5377 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5378
5379 /*
5380 * Store led settings, for correct led behaviour.
5381 */
5382 #ifdef CONFIG_RT2X00_LIB_LEDS
5383 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5384 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5385 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5386
5387 rt2x00dev->led_mcu_reg = eeprom;
5388 #endif /* CONFIG_RT2X00_LIB_LEDS */
5389
5390 /*
5391 * Check if support EIRP tx power limit feature.
5392 */
5393 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5394
5395 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5396 EIRP_MAX_TX_POWER_LIMIT)
5397 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5398
5399 return 0;
5400 }
5401
5402 /*
5403 * RF value list for rt28xx
5404 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5405 */
5406 static const struct rf_channel rf_vals[] = {
5407 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5408 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5409 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5410 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5411 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5412 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5413 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5414 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5415 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5416 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5417 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5418 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5419 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5420 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5421
5422 /* 802.11 UNI / HyperLan 2 */
5423 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5424 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5425 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5426 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5427 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5428 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5429 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5430 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5431 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5432 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5433 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5434 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5435
5436 /* 802.11 HyperLan 2 */
5437 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5438 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5439 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5440 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5441 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5442 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5443 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5444 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5445 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5446 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5447 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5448 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5449 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5450 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5451 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5452 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5453
5454 /* 802.11 UNII */
5455 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5456 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5457 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5458 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5459 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5460 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5461 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5462 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5463 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5464 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5465 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5466
5467 /* 802.11 Japan */
5468 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5469 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5470 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5471 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5472 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5473 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5474 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5475 };
5476
5477 /*
5478 * RF value list for rt3xxx
5479 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5480 */
5481 static const struct rf_channel rf_vals_3x[] = {
5482 {1, 241, 2, 2 },
5483 {2, 241, 2, 7 },
5484 {3, 242, 2, 2 },
5485 {4, 242, 2, 7 },
5486 {5, 243, 2, 2 },
5487 {6, 243, 2, 7 },
5488 {7, 244, 2, 2 },
5489 {8, 244, 2, 7 },
5490 {9, 245, 2, 2 },
5491 {10, 245, 2, 7 },
5492 {11, 246, 2, 2 },
5493 {12, 246, 2, 7 },
5494 {13, 247, 2, 2 },
5495 {14, 248, 2, 4 },
5496
5497 /* 802.11 UNI / HyperLan 2 */
5498 {36, 0x56, 0, 4},
5499 {38, 0x56, 0, 6},
5500 {40, 0x56, 0, 8},
5501 {44, 0x57, 0, 0},
5502 {46, 0x57, 0, 2},
5503 {48, 0x57, 0, 4},
5504 {52, 0x57, 0, 8},
5505 {54, 0x57, 0, 10},
5506 {56, 0x58, 0, 0},
5507 {60, 0x58, 0, 4},
5508 {62, 0x58, 0, 6},
5509 {64, 0x58, 0, 8},
5510
5511 /* 802.11 HyperLan 2 */
5512 {100, 0x5b, 0, 8},
5513 {102, 0x5b, 0, 10},
5514 {104, 0x5c, 0, 0},
5515 {108, 0x5c, 0, 4},
5516 {110, 0x5c, 0, 6},
5517 {112, 0x5c, 0, 8},
5518 {116, 0x5d, 0, 0},
5519 {118, 0x5d, 0, 2},
5520 {120, 0x5d, 0, 4},
5521 {124, 0x5d, 0, 8},
5522 {126, 0x5d, 0, 10},
5523 {128, 0x5e, 0, 0},
5524 {132, 0x5e, 0, 4},
5525 {134, 0x5e, 0, 6},
5526 {136, 0x5e, 0, 8},
5527 {140, 0x5f, 0, 0},
5528
5529 /* 802.11 UNII */
5530 {149, 0x5f, 0, 9},
5531 {151, 0x5f, 0, 11},
5532 {153, 0x60, 0, 1},
5533 {157, 0x60, 0, 5},
5534 {159, 0x60, 0, 7},
5535 {161, 0x60, 0, 9},
5536 {165, 0x61, 0, 1},
5537 {167, 0x61, 0, 3},
5538 {169, 0x61, 0, 5},
5539 {171, 0x61, 0, 7},
5540 {173, 0x61, 0, 9},
5541 };
5542
5543 static const struct rf_channel rf_vals_5592_xtal20[] = {
5544 /* Channel, N, K, mod, R */
5545 {1, 482, 4, 10, 3},
5546 {2, 483, 4, 10, 3},
5547 {3, 484, 4, 10, 3},
5548 {4, 485, 4, 10, 3},
5549 {5, 486, 4, 10, 3},
5550 {6, 487, 4, 10, 3},
5551 {7, 488, 4, 10, 3},
5552 {8, 489, 4, 10, 3},
5553 {9, 490, 4, 10, 3},
5554 {10, 491, 4, 10, 3},
5555 {11, 492, 4, 10, 3},
5556 {12, 493, 4, 10, 3},
5557 {13, 494, 4, 10, 3},
5558 {14, 496, 8, 10, 3},
5559 {36, 172, 8, 12, 1},
5560 {38, 173, 0, 12, 1},
5561 {40, 173, 4, 12, 1},
5562 {42, 173, 8, 12, 1},
5563 {44, 174, 0, 12, 1},
5564 {46, 174, 4, 12, 1},
5565 {48, 174, 8, 12, 1},
5566 {50, 175, 0, 12, 1},
5567 {52, 175, 4, 12, 1},
5568 {54, 175, 8, 12, 1},
5569 {56, 176, 0, 12, 1},
5570 {58, 176, 4, 12, 1},
5571 {60, 176, 8, 12, 1},
5572 {62, 177, 0, 12, 1},
5573 {64, 177, 4, 12, 1},
5574 {100, 183, 4, 12, 1},
5575 {102, 183, 8, 12, 1},
5576 {104, 184, 0, 12, 1},
5577 {106, 184, 4, 12, 1},
5578 {108, 184, 8, 12, 1},
5579 {110, 185, 0, 12, 1},
5580 {112, 185, 4, 12, 1},
5581 {114, 185, 8, 12, 1},
5582 {116, 186, 0, 12, 1},
5583 {118, 186, 4, 12, 1},
5584 {120, 186, 8, 12, 1},
5585 {122, 187, 0, 12, 1},
5586 {124, 187, 4, 12, 1},
5587 {126, 187, 8, 12, 1},
5588 {128, 188, 0, 12, 1},
5589 {130, 188, 4, 12, 1},
5590 {132, 188, 8, 12, 1},
5591 {134, 189, 0, 12, 1},
5592 {136, 189, 4, 12, 1},
5593 {138, 189, 8, 12, 1},
5594 {140, 190, 0, 12, 1},
5595 {149, 191, 6, 12, 1},
5596 {151, 191, 10, 12, 1},
5597 {153, 192, 2, 12, 1},
5598 {155, 192, 6, 12, 1},
5599 {157, 192, 10, 12, 1},
5600 {159, 193, 2, 12, 1},
5601 {161, 193, 6, 12, 1},
5602 {165, 194, 2, 12, 1},
5603 {184, 164, 0, 12, 1},
5604 {188, 164, 4, 12, 1},
5605 {192, 165, 8, 12, 1},
5606 {196, 166, 0, 12, 1},
5607 };
5608
5609 static const struct rf_channel rf_vals_5592_xtal40[] = {
5610 /* Channel, N, K, mod, R */
5611 {1, 241, 2, 10, 3},
5612 {2, 241, 7, 10, 3},
5613 {3, 242, 2, 10, 3},
5614 {4, 242, 7, 10, 3},
5615 {5, 243, 2, 10, 3},
5616 {6, 243, 7, 10, 3},
5617 {7, 244, 2, 10, 3},
5618 {8, 244, 7, 10, 3},
5619 {9, 245, 2, 10, 3},
5620 {10, 245, 7, 10, 3},
5621 {11, 246, 2, 10, 3},
5622 {12, 246, 7, 10, 3},
5623 {13, 247, 2, 10, 3},
5624 {14, 248, 4, 10, 3},
5625 {36, 86, 4, 12, 1},
5626 {38, 86, 6, 12, 1},
5627 {40, 86, 8, 12, 1},
5628 {42, 86, 10, 12, 1},
5629 {44, 87, 0, 12, 1},
5630 {46, 87, 2, 12, 1},
5631 {48, 87, 4, 12, 1},
5632 {50, 87, 6, 12, 1},
5633 {52, 87, 8, 12, 1},
5634 {54, 87, 10, 12, 1},
5635 {56, 88, 0, 12, 1},
5636 {58, 88, 2, 12, 1},
5637 {60, 88, 4, 12, 1},
5638 {62, 88, 6, 12, 1},
5639 {64, 88, 8, 12, 1},
5640 {100, 91, 8, 12, 1},
5641 {102, 91, 10, 12, 1},
5642 {104, 92, 0, 12, 1},
5643 {106, 92, 2, 12, 1},
5644 {108, 92, 4, 12, 1},
5645 {110, 92, 6, 12, 1},
5646 {112, 92, 8, 12, 1},
5647 {114, 92, 10, 12, 1},
5648 {116, 93, 0, 12, 1},
5649 {118, 93, 2, 12, 1},
5650 {120, 93, 4, 12, 1},
5651 {122, 93, 6, 12, 1},
5652 {124, 93, 8, 12, 1},
5653 {126, 93, 10, 12, 1},
5654 {128, 94, 0, 12, 1},
5655 {130, 94, 2, 12, 1},
5656 {132, 94, 4, 12, 1},
5657 {134, 94, 6, 12, 1},
5658 {136, 94, 8, 12, 1},
5659 {138, 94, 10, 12, 1},
5660 {140, 95, 0, 12, 1},
5661 {149, 95, 9, 12, 1},
5662 {151, 95, 11, 12, 1},
5663 {153, 96, 1, 12, 1},
5664 {155, 96, 3, 12, 1},
5665 {157, 96, 5, 12, 1},
5666 {159, 96, 7, 12, 1},
5667 {161, 96, 9, 12, 1},
5668 {165, 97, 1, 12, 1},
5669 {184, 82, 0, 12, 1},
5670 {188, 82, 4, 12, 1},
5671 {192, 82, 8, 12, 1},
5672 {196, 83, 0, 12, 1},
5673 };
5674
5675 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5676 {
5677 struct hw_mode_spec *spec = &rt2x00dev->spec;
5678 struct channel_info *info;
5679 char *default_power1;
5680 char *default_power2;
5681 unsigned int i;
5682 u16 eeprom;
5683 u32 reg;
5684
5685 /*
5686 * Disable powersaving as default on PCI devices.
5687 */
5688 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5689 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5690
5691 /*
5692 * Initialize all hw fields.
5693 */
5694 rt2x00dev->hw->flags =
5695 IEEE80211_HW_SIGNAL_DBM |
5696 IEEE80211_HW_SUPPORTS_PS |
5697 IEEE80211_HW_PS_NULLFUNC_STACK |
5698 IEEE80211_HW_AMPDU_AGGREGATION |
5699 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5700
5701 /*
5702 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5703 * unless we are capable of sending the buffered frames out after the
5704 * DTIM transmission using rt2x00lib_beacondone. This will send out
5705 * multicast and broadcast traffic immediately instead of buffering it
5706 * infinitly and thus dropping it after some time.
5707 */
5708 if (!rt2x00_is_usb(rt2x00dev))
5709 rt2x00dev->hw->flags |=
5710 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5711
5712 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5713 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5714 rt2x00_eeprom_addr(rt2x00dev,
5715 EEPROM_MAC_ADDR_0));
5716
5717 /*
5718 * As rt2800 has a global fallback table we cannot specify
5719 * more then one tx rate per frame but since the hw will
5720 * try several rates (based on the fallback table) we should
5721 * initialize max_report_rates to the maximum number of rates
5722 * we are going to try. Otherwise mac80211 will truncate our
5723 * reported tx rates and the rc algortihm will end up with
5724 * incorrect data.
5725 */
5726 rt2x00dev->hw->max_rates = 1;
5727 rt2x00dev->hw->max_report_rates = 7;
5728 rt2x00dev->hw->max_rate_tries = 1;
5729
5730 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5731
5732 /*
5733 * Initialize hw_mode information.
5734 */
5735 spec->supported_bands = SUPPORT_BAND_2GHZ;
5736 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5737
5738 if (rt2x00_rf(rt2x00dev, RF2820) ||
5739 rt2x00_rf(rt2x00dev, RF2720)) {
5740 spec->num_channels = 14;
5741 spec->channels = rf_vals;
5742 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5743 rt2x00_rf(rt2x00dev, RF2750)) {
5744 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5745 spec->num_channels = ARRAY_SIZE(rf_vals);
5746 spec->channels = rf_vals;
5747 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5748 rt2x00_rf(rt2x00dev, RF2020) ||
5749 rt2x00_rf(rt2x00dev, RF3021) ||
5750 rt2x00_rf(rt2x00dev, RF3022) ||
5751 rt2x00_rf(rt2x00dev, RF3290) ||
5752 rt2x00_rf(rt2x00dev, RF3320) ||
5753 rt2x00_rf(rt2x00dev, RF3322) ||
5754 rt2x00_rf(rt2x00dev, RF5360) ||
5755 rt2x00_rf(rt2x00dev, RF5370) ||
5756 rt2x00_rf(rt2x00dev, RF5372) ||
5757 rt2x00_rf(rt2x00dev, RF5390) ||
5758 rt2x00_rf(rt2x00dev, RF5392)) {
5759 spec->num_channels = 14;
5760 spec->channels = rf_vals_3x;
5761 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5762 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5763 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5764 spec->channels = rf_vals_3x;
5765 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5766 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5767
5768 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5769 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5770 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5771 spec->channels = rf_vals_5592_xtal40;
5772 } else {
5773 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5774 spec->channels = rf_vals_5592_xtal20;
5775 }
5776 }
5777
5778 if (WARN_ON_ONCE(!spec->channels))
5779 return -ENODEV;
5780
5781 /*
5782 * Initialize HT information.
5783 */
5784 if (!rt2x00_rf(rt2x00dev, RF2020))
5785 spec->ht.ht_supported = true;
5786 else
5787 spec->ht.ht_supported = false;
5788
5789 spec->ht.cap =
5790 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5791 IEEE80211_HT_CAP_GRN_FLD |
5792 IEEE80211_HT_CAP_SGI_20 |
5793 IEEE80211_HT_CAP_SGI_40;
5794
5795 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5796 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5797
5798 spec->ht.cap |=
5799 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5800 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5801
5802 spec->ht.ampdu_factor = 3;
5803 spec->ht.ampdu_density = 4;
5804 spec->ht.mcs.tx_params =
5805 IEEE80211_HT_MCS_TX_DEFINED |
5806 IEEE80211_HT_MCS_TX_RX_DIFF |
5807 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5808 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5809
5810 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5811 case 3:
5812 spec->ht.mcs.rx_mask[2] = 0xff;
5813 case 2:
5814 spec->ht.mcs.rx_mask[1] = 0xff;
5815 case 1:
5816 spec->ht.mcs.rx_mask[0] = 0xff;
5817 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5818 break;
5819 }
5820
5821 /*
5822 * Create channel information array
5823 */
5824 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5825 if (!info)
5826 return -ENOMEM;
5827
5828 spec->channels_info = info;
5829
5830 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5831 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5832
5833 for (i = 0; i < 14; i++) {
5834 info[i].default_power1 = default_power1[i];
5835 info[i].default_power2 = default_power2[i];
5836 }
5837
5838 if (spec->num_channels > 14) {
5839 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5840 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5841
5842 for (i = 14; i < spec->num_channels; i++) {
5843 info[i].default_power1 = default_power1[i];
5844 info[i].default_power2 = default_power2[i];
5845 }
5846 }
5847
5848 switch (rt2x00dev->chip.rf) {
5849 case RF2020:
5850 case RF3020:
5851 case RF3021:
5852 case RF3022:
5853 case RF3320:
5854 case RF3052:
5855 case RF3290:
5856 case RF5360:
5857 case RF5370:
5858 case RF5372:
5859 case RF5390:
5860 case RF5392:
5861 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5862 break;
5863 }
5864
5865 return 0;
5866 }
5867
5868 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5869 {
5870 int retval;
5871 u32 reg;
5872
5873 /*
5874 * Allocate eeprom data.
5875 */
5876 retval = rt2800_validate_eeprom(rt2x00dev);
5877 if (retval)
5878 return retval;
5879
5880 retval = rt2800_init_eeprom(rt2x00dev);
5881 if (retval)
5882 return retval;
5883
5884 /*
5885 * Enable rfkill polling by setting GPIO direction of the
5886 * rfkill switch GPIO pin correctly.
5887 */
5888 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5889 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5890 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5891
5892 /*
5893 * Initialize hw specifications.
5894 */
5895 retval = rt2800_probe_hw_mode(rt2x00dev);
5896 if (retval)
5897 return retval;
5898
5899 /*
5900 * Set device capabilities.
5901 */
5902 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5903 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5904 if (!rt2x00_is_usb(rt2x00dev))
5905 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5906
5907 /*
5908 * Set device requirements.
5909 */
5910 if (!rt2x00_is_soc(rt2x00dev))
5911 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5912 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5913 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5914 if (!rt2800_hwcrypt_disabled(rt2x00dev))
5915 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5916 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5917 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5918 if (rt2x00_is_usb(rt2x00dev))
5919 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5920 else {
5921 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5922 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5923 }
5924
5925 /*
5926 * Set the rssi offset.
5927 */
5928 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5929
5930 return 0;
5931 }
5932 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5933
5934 /*
5935 * IEEE80211 stack callback functions.
5936 */
5937 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5938 u16 *iv16)
5939 {
5940 struct rt2x00_dev *rt2x00dev = hw->priv;
5941 struct mac_iveiv_entry iveiv_entry;
5942 u32 offset;
5943
5944 offset = MAC_IVEIV_ENTRY(hw_key_idx);
5945 rt2800_register_multiread(rt2x00dev, offset,
5946 &iveiv_entry, sizeof(iveiv_entry));
5947
5948 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5949 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5950 }
5951 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5952
5953 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5954 {
5955 struct rt2x00_dev *rt2x00dev = hw->priv;
5956 u32 reg;
5957 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5958
5959 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5960 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5961 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5962
5963 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5964 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5965 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5966
5967 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5968 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5969 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5970
5971 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5972 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5973 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5974
5975 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5976 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5977 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5978
5979 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5980 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5981 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5982
5983 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5984 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5985 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5986
5987 return 0;
5988 }
5989 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
5990
5991 int rt2800_conf_tx(struct ieee80211_hw *hw,
5992 struct ieee80211_vif *vif, u16 queue_idx,
5993 const struct ieee80211_tx_queue_params *params)
5994 {
5995 struct rt2x00_dev *rt2x00dev = hw->priv;
5996 struct data_queue *queue;
5997 struct rt2x00_field32 field;
5998 int retval;
5999 u32 reg;
6000 u32 offset;
6001
6002 /*
6003 * First pass the configuration through rt2x00lib, that will
6004 * update the queue settings and validate the input. After that
6005 * we are free to update the registers based on the value
6006 * in the queue parameter.
6007 */
6008 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6009 if (retval)
6010 return retval;
6011
6012 /*
6013 * We only need to perform additional register initialization
6014 * for WMM queues/
6015 */
6016 if (queue_idx >= 4)
6017 return 0;
6018
6019 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6020
6021 /* Update WMM TXOP register */
6022 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6023 field.bit_offset = (queue_idx & 1) * 16;
6024 field.bit_mask = 0xffff << field.bit_offset;
6025
6026 rt2800_register_read(rt2x00dev, offset, &reg);
6027 rt2x00_set_field32(&reg, field, queue->txop);
6028 rt2800_register_write(rt2x00dev, offset, reg);
6029
6030 /* Update WMM registers */
6031 field.bit_offset = queue_idx * 4;
6032 field.bit_mask = 0xf << field.bit_offset;
6033
6034 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6035 rt2x00_set_field32(&reg, field, queue->aifs);
6036 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6037
6038 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6039 rt2x00_set_field32(&reg, field, queue->cw_min);
6040 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6041
6042 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6043 rt2x00_set_field32(&reg, field, queue->cw_max);
6044 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6045
6046 /* Update EDCA registers */
6047 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6048
6049 rt2800_register_read(rt2x00dev, offset, &reg);
6050 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6051 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6052 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6053 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6054 rt2800_register_write(rt2x00dev, offset, reg);
6055
6056 return 0;
6057 }
6058 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6059
6060 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6061 {
6062 struct rt2x00_dev *rt2x00dev = hw->priv;
6063 u64 tsf;
6064 u32 reg;
6065
6066 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6067 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6068 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6069 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6070
6071 return tsf;
6072 }
6073 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6074
6075 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6076 enum ieee80211_ampdu_mlme_action action,
6077 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6078 u8 buf_size)
6079 {
6080 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6081 int ret = 0;
6082
6083 /*
6084 * Don't allow aggregation for stations the hardware isn't aware
6085 * of because tx status reports for frames to an unknown station
6086 * always contain wcid=255 and thus we can't distinguish between
6087 * multiple stations which leads to unwanted situations when the
6088 * hw reorders frames due to aggregation.
6089 */
6090 if (sta_priv->wcid < 0)
6091 return 1;
6092
6093 switch (action) {
6094 case IEEE80211_AMPDU_RX_START:
6095 case IEEE80211_AMPDU_RX_STOP:
6096 /*
6097 * The hw itself takes care of setting up BlockAck mechanisms.
6098 * So, we only have to allow mac80211 to nagotiate a BlockAck
6099 * agreement. Once that is done, the hw will BlockAck incoming
6100 * AMPDUs without further setup.
6101 */
6102 break;
6103 case IEEE80211_AMPDU_TX_START:
6104 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6105 break;
6106 case IEEE80211_AMPDU_TX_STOP_CONT:
6107 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6108 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6109 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6110 break;
6111 case IEEE80211_AMPDU_TX_OPERATIONAL:
6112 break;
6113 default:
6114 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6115 }
6116
6117 return ret;
6118 }
6119 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6120
6121 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6122 struct survey_info *survey)
6123 {
6124 struct rt2x00_dev *rt2x00dev = hw->priv;
6125 struct ieee80211_conf *conf = &hw->conf;
6126 u32 idle, busy, busy_ext;
6127
6128 if (idx != 0)
6129 return -ENOENT;
6130
6131 survey->channel = conf->channel;
6132
6133 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6134 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6135 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6136
6137 if (idle || busy) {
6138 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6139 SURVEY_INFO_CHANNEL_TIME_BUSY |
6140 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6141
6142 survey->channel_time = (idle + busy) / 1000;
6143 survey->channel_time_busy = busy / 1000;
6144 survey->channel_time_ext_busy = busy_ext / 1000;
6145 }
6146
6147 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6148 survey->filled |= SURVEY_INFO_IN_USE;
6149
6150 return 0;
6151
6152 }
6153 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6154
6155 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6156 MODULE_VERSION(DRV_VERSION);
6157 MODULE_DESCRIPTION("Ralink RT2800 library");
6158 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)