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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 /*
33 Module: rt2800lib
34 Abstract: rt2800 generic device routines.
35 */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
75 return false;
76
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
81 return true;
82
83 WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
89 {
90 u32 reg;
91
92 mutex_lock(&rt2x00dev->csr_mutex);
93
94 /*
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
97 */
98 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99 reg = 0;
100 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107 }
108
109 mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
114 {
115 u32 reg;
116
117 mutex_lock(&rt2x00dev->csr_mutex);
118
119 /*
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
126 */
127 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128 reg = 0;
129 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136 WAIT_FOR_BBP(rt2x00dev, &reg);
137 }
138
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141 mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
146 {
147 u32 reg;
148
149 mutex_lock(&rt2x00dev->csr_mutex);
150
151 /*
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
154 */
155 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156 reg = 0;
157 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 }
164
165 mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
170 {
171 u32 reg;
172
173 mutex_lock(&rt2x00dev->csr_mutex);
174
175 /*
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
182 */
183 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 reg = 0;
185 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192 }
193
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196 mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
201 {
202 u32 reg;
203
204 mutex_lock(&rt2x00dev->csr_mutex);
205
206 /*
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
209 */
210 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211 reg = 0;
212 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
219 }
220
221 mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
225 {
226 u32 reg;
227 int i, count;
228
229 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
230 if (rt2x00_get_field32(reg, WLAN_EN))
231 return 0;
232
233 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
234 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
235 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
236 rt2x00_set_field32(&reg, WLAN_EN, 1);
237 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
238
239 udelay(REGISTER_BUSY_DELAY);
240
241 count = 0;
242 do {
243 /*
244 * Check PLL_LD & XTAL_RDY.
245 */
246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
247 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
248 if (rt2x00_get_field32(reg, PLL_LD) &&
249 rt2x00_get_field32(reg, XTAL_RDY))
250 break;
251 udelay(REGISTER_BUSY_DELAY);
252 }
253
254 if (i >= REGISTER_BUSY_COUNT) {
255
256 if (count >= 10)
257 return -EIO;
258
259 rt2800_register_write(rt2x00dev, 0x58, 0x018);
260 udelay(REGISTER_BUSY_DELAY);
261 rt2800_register_write(rt2x00dev, 0x58, 0x418);
262 udelay(REGISTER_BUSY_DELAY);
263 rt2800_register_write(rt2x00dev, 0x58, 0x618);
264 udelay(REGISTER_BUSY_DELAY);
265 count++;
266 } else {
267 count = 0;
268 }
269
270 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
271 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
272 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
273 rt2x00_set_field32(&reg, WLAN_RESET, 1);
274 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
275 udelay(10);
276 rt2x00_set_field32(&reg, WLAN_RESET, 0);
277 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
278 udelay(10);
279 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
280 } while (count != 0);
281
282 return 0;
283 }
284
285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
286 const u8 command, const u8 token,
287 const u8 arg0, const u8 arg1)
288 {
289 u32 reg;
290
291 /*
292 * SOC devices don't support MCU requests.
293 */
294 if (rt2x00_is_soc(rt2x00dev))
295 return;
296
297 mutex_lock(&rt2x00dev->csr_mutex);
298
299 /*
300 * Wait until the MCU becomes available, afterwards we
301 * can safely write the new data into the register.
302 */
303 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
304 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
305 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
306 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
307 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
308 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
309
310 reg = 0;
311 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
312 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
313 }
314
315 mutex_unlock(&rt2x00dev->csr_mutex);
316 }
317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
318
319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
320 {
321 unsigned int i = 0;
322 u32 reg;
323
324 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
325 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
326 if (reg && reg != ~0)
327 return 0;
328 msleep(1);
329 }
330
331 ERROR(rt2x00dev, "Unstable hardware.\n");
332 return -EBUSY;
333 }
334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
335
336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
337 {
338 unsigned int i;
339 u32 reg;
340
341 /*
342 * Some devices are really slow to respond here. Wait a whole second
343 * before timing out.
344 */
345 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
346 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
347 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
348 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
349 return 0;
350
351 msleep(10);
352 }
353
354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
355 return -EACCES;
356 }
357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
358
359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
360 {
361 u32 reg;
362
363 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
364 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
365 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
366 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
367 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
368 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
369 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
370 }
371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
372
373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
374 {
375 u16 fw_crc;
376 u16 crc;
377
378 /*
379 * The last 2 bytes in the firmware array are the crc checksum itself,
380 * this means that we should never pass those 2 bytes to the crc
381 * algorithm.
382 */
383 fw_crc = (data[len - 2] << 8 | data[len - 1]);
384
385 /*
386 * Use the crc ccitt algorithm.
387 * This will return the same value as the legacy driver which
388 * used bit ordering reversion on the both the firmware bytes
389 * before input input as well as on the final output.
390 * Obviously using crc ccitt directly is much more efficient.
391 */
392 crc = crc_ccitt(~0, data, len - 2);
393
394 /*
395 * There is a small difference between the crc-itu-t + bitrev and
396 * the crc-ccitt crc calculation. In the latter method the 2 bytes
397 * will be swapped, use swab16 to convert the crc to the correct
398 * value.
399 */
400 crc = swab16(crc);
401
402 return fw_crc == crc;
403 }
404
405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
406 const u8 *data, const size_t len)
407 {
408 size_t offset = 0;
409 size_t fw_len;
410 bool multiple;
411
412 /*
413 * PCI(e) & SOC devices require firmware with a length
414 * of 8kb. USB devices require firmware files with a length
415 * of 4kb. Certain USB chipsets however require different firmware,
416 * which Ralink only provides attached to the original firmware
417 * file. Thus for USB devices, firmware files have a length
418 * which is a multiple of 4kb. The firmware for rt3290 chip also
419 * have a length which is a multiple of 4kb.
420 */
421 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
422 fw_len = 4096;
423 else
424 fw_len = 8192;
425
426 multiple = true;
427 /*
428 * Validate the firmware length
429 */
430 if (len != fw_len && (!multiple || (len % fw_len) != 0))
431 return FW_BAD_LENGTH;
432
433 /*
434 * Check if the chipset requires one of the upper parts
435 * of the firmware.
436 */
437 if (rt2x00_is_usb(rt2x00dev) &&
438 !rt2x00_rt(rt2x00dev, RT2860) &&
439 !rt2x00_rt(rt2x00dev, RT2872) &&
440 !rt2x00_rt(rt2x00dev, RT3070) &&
441 ((len / fw_len) == 1))
442 return FW_BAD_VERSION;
443
444 /*
445 * 8kb firmware files must be checked as if it were
446 * 2 separate firmware files.
447 */
448 while (offset < len) {
449 if (!rt2800_check_firmware_crc(data + offset, fw_len))
450 return FW_BAD_CRC;
451
452 offset += fw_len;
453 }
454
455 return FW_OK;
456 }
457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
458
459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
460 const u8 *data, const size_t len)
461 {
462 unsigned int i;
463 u32 reg;
464 int retval;
465
466 if (rt2x00_rt(rt2x00dev, RT3290)) {
467 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
468 if (retval)
469 return -EBUSY;
470 }
471
472 /*
473 * If driver doesn't wake up firmware here,
474 * rt2800_load_firmware will hang forever when interface is up again.
475 */
476 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
477
478 /*
479 * Wait for stable hardware.
480 */
481 if (rt2800_wait_csr_ready(rt2x00dev))
482 return -EBUSY;
483
484 if (rt2x00_is_pci(rt2x00dev)) {
485 if (rt2x00_rt(rt2x00dev, RT3290) ||
486 rt2x00_rt(rt2x00dev, RT3572) ||
487 rt2x00_rt(rt2x00dev, RT5390) ||
488 rt2x00_rt(rt2x00dev, RT5392)) {
489 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
490 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
491 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
492 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
493 }
494 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
495 }
496
497 rt2800_disable_wpdma(rt2x00dev);
498
499 /*
500 * Write firmware to the device.
501 */
502 rt2800_drv_write_firmware(rt2x00dev, data, len);
503
504 /*
505 * Wait for device to stabilize.
506 */
507 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
508 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
509 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
510 break;
511 msleep(1);
512 }
513
514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n");
516 return -EBUSY;
517 }
518
519 /*
520 * Disable DMA, will be reenabled later when enabling
521 * the radio.
522 */
523 rt2800_disable_wpdma(rt2x00dev);
524
525 /*
526 * Initialize firmware.
527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
530 if (rt2x00_is_usb(rt2x00dev)) {
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
532 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
533 }
534 msleep(1);
535
536 return 0;
537 }
538 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
539
540 void rt2800_write_tx_data(struct queue_entry *entry,
541 struct txentry_desc *txdesc)
542 {
543 __le32 *txwi = rt2800_drv_get_txwi(entry);
544 u32 word;
545
546 /*
547 * Initialize TX Info descriptor
548 */
549 rt2x00_desc_read(txwi, 0, &word);
550 rt2x00_set_field32(&word, TXWI_W0_FRAG,
551 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
552 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
553 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
554 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
555 rt2x00_set_field32(&word, TXWI_W0_TS,
556 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
557 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
558 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
559 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
560 txdesc->u.ht.mpdu_density);
561 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
562 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
563 rt2x00_set_field32(&word, TXWI_W0_BW,
564 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
565 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
566 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
567 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
568 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
569 rt2x00_desc_write(txwi, 0, word);
570
571 rt2x00_desc_read(txwi, 1, &word);
572 rt2x00_set_field32(&word, TXWI_W1_ACK,
573 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
574 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
575 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
576 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
577 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
578 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
579 txdesc->key_idx : txdesc->u.ht.wcid);
580 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
581 txdesc->length);
582 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
583 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
584 rt2x00_desc_write(txwi, 1, word);
585
586 /*
587 * Always write 0 to IV/EIV fields, hardware will insert the IV
588 * from the IVEIV register when TXD_W3_WIV is set to 0.
589 * When TXD_W3_WIV is set to 1 it will use the IV data
590 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
591 * crypto entry in the registers should be used to encrypt the frame.
592 */
593 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
594 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
595 }
596 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
597
598 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
599 {
600 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
601 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
602 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
603 u16 eeprom;
604 u8 offset0;
605 u8 offset1;
606 u8 offset2;
607
608 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
609 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
610 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
611 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
612 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
613 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
614 } else {
615 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
616 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
617 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
618 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
619 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
620 }
621
622 /*
623 * Convert the value from the descriptor into the RSSI value
624 * If the value in the descriptor is 0, it is considered invalid
625 * and the default (extremely low) rssi value is assumed
626 */
627 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
628 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
629 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
630
631 /*
632 * mac80211 only accepts a single RSSI value. Calculating the
633 * average doesn't deliver a fair answer either since -60:-60 would
634 * be considered equally good as -50:-70 while the second is the one
635 * which gives less energy...
636 */
637 rssi0 = max(rssi0, rssi1);
638 return (int)max(rssi0, rssi2);
639 }
640
641 void rt2800_process_rxwi(struct queue_entry *entry,
642 struct rxdone_entry_desc *rxdesc)
643 {
644 __le32 *rxwi = (__le32 *) entry->skb->data;
645 u32 word;
646
647 rt2x00_desc_read(rxwi, 0, &word);
648
649 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
650 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
651
652 rt2x00_desc_read(rxwi, 1, &word);
653
654 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
655 rxdesc->flags |= RX_FLAG_SHORT_GI;
656
657 if (rt2x00_get_field32(word, RXWI_W1_BW))
658 rxdesc->flags |= RX_FLAG_40MHZ;
659
660 /*
661 * Detect RX rate, always use MCS as signal type.
662 */
663 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
664 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
665 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
666
667 /*
668 * Mask of 0x8 bit to remove the short preamble flag.
669 */
670 if (rxdesc->rate_mode == RATE_MODE_CCK)
671 rxdesc->signal &= ~0x8;
672
673 rt2x00_desc_read(rxwi, 2, &word);
674
675 /*
676 * Convert descriptor AGC value to RSSI value.
677 */
678 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
679 }
680 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
681
682 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
683 {
684 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
685 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
686 struct txdone_entry_desc txdesc;
687 u32 word;
688 u16 mcs, real_mcs;
689 int aggr, ampdu;
690
691 /*
692 * Obtain the status about this packet.
693 */
694 txdesc.flags = 0;
695 rt2x00_desc_read(txwi, 0, &word);
696
697 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
698 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
699
700 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
701 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
702
703 /*
704 * If a frame was meant to be sent as a single non-aggregated MPDU
705 * but ended up in an aggregate the used tx rate doesn't correlate
706 * with the one specified in the TXWI as the whole aggregate is sent
707 * with the same rate.
708 *
709 * For example: two frames are sent to rt2x00, the first one sets
710 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
711 * and requests MCS15. If the hw aggregates both frames into one
712 * AMDPU the tx status for both frames will contain MCS7 although
713 * the frame was sent successfully.
714 *
715 * Hence, replace the requested rate with the real tx rate to not
716 * confuse the rate control algortihm by providing clearly wrong
717 * data.
718 */
719 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
720 skbdesc->tx_rate_idx = real_mcs;
721 mcs = real_mcs;
722 }
723
724 if (aggr == 1 || ampdu == 1)
725 __set_bit(TXDONE_AMPDU, &txdesc.flags);
726
727 /*
728 * Ralink has a retry mechanism using a global fallback
729 * table. We setup this fallback table to try the immediate
730 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
731 * always contains the MCS used for the last transmission, be
732 * it successful or not.
733 */
734 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
735 /*
736 * Transmission succeeded. The number of retries is
737 * mcs - real_mcs
738 */
739 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
740 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
741 } else {
742 /*
743 * Transmission failed. The number of retries is
744 * always 7 in this case (for a total number of 8
745 * frames sent).
746 */
747 __set_bit(TXDONE_FAILURE, &txdesc.flags);
748 txdesc.retry = rt2x00dev->long_retry;
749 }
750
751 /*
752 * the frame was retried at least once
753 * -> hw used fallback rates
754 */
755 if (txdesc.retry)
756 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
757
758 rt2x00lib_txdone(entry, &txdesc);
759 }
760 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
761
762 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
763 {
764 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
765 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
766 unsigned int beacon_base;
767 unsigned int padding_len;
768 u32 orig_reg, reg;
769
770 /*
771 * Disable beaconing while we are reloading the beacon data,
772 * otherwise we might be sending out invalid data.
773 */
774 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
775 orig_reg = reg;
776 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
777 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
778
779 /*
780 * Add space for the TXWI in front of the skb.
781 */
782 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
783
784 /*
785 * Register descriptor details in skb frame descriptor.
786 */
787 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
788 skbdesc->desc = entry->skb->data;
789 skbdesc->desc_len = TXWI_DESC_SIZE;
790
791 /*
792 * Add the TXWI for the beacon to the skb.
793 */
794 rt2800_write_tx_data(entry, txdesc);
795
796 /*
797 * Dump beacon to userspace through debugfs.
798 */
799 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
800
801 /*
802 * Write entire beacon with TXWI and padding to register.
803 */
804 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
805 if (padding_len && skb_pad(entry->skb, padding_len)) {
806 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
807 /* skb freed by skb_pad() on failure */
808 entry->skb = NULL;
809 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
810 return;
811 }
812
813 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
814 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
815 entry->skb->len + padding_len);
816
817 /*
818 * Enable beaconing again.
819 */
820 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
821 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
822
823 /*
824 * Clean up beacon skb.
825 */
826 dev_kfree_skb_any(entry->skb);
827 entry->skb = NULL;
828 }
829 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
830
831 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
832 unsigned int beacon_base)
833 {
834 int i;
835
836 /*
837 * For the Beacon base registers we only need to clear
838 * the whole TXWI which (when set to 0) will invalidate
839 * the entire beacon.
840 */
841 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
842 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
843 }
844
845 void rt2800_clear_beacon(struct queue_entry *entry)
846 {
847 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
848 u32 reg;
849
850 /*
851 * Disable beaconing while we are reloading the beacon data,
852 * otherwise we might be sending out invalid data.
853 */
854 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
855 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
856 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
857
858 /*
859 * Clear beacon.
860 */
861 rt2800_clear_beacon_register(rt2x00dev,
862 HW_BEACON_OFFSET(entry->entry_idx));
863
864 /*
865 * Enabled beaconing again.
866 */
867 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
868 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
869 }
870 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
871
872 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
873 const struct rt2x00debug rt2800_rt2x00debug = {
874 .owner = THIS_MODULE,
875 .csr = {
876 .read = rt2800_register_read,
877 .write = rt2800_register_write,
878 .flags = RT2X00DEBUGFS_OFFSET,
879 .word_base = CSR_REG_BASE,
880 .word_size = sizeof(u32),
881 .word_count = CSR_REG_SIZE / sizeof(u32),
882 },
883 .eeprom = {
884 .read = rt2x00_eeprom_read,
885 .write = rt2x00_eeprom_write,
886 .word_base = EEPROM_BASE,
887 .word_size = sizeof(u16),
888 .word_count = EEPROM_SIZE / sizeof(u16),
889 },
890 .bbp = {
891 .read = rt2800_bbp_read,
892 .write = rt2800_bbp_write,
893 .word_base = BBP_BASE,
894 .word_size = sizeof(u8),
895 .word_count = BBP_SIZE / sizeof(u8),
896 },
897 .rf = {
898 .read = rt2x00_rf_read,
899 .write = rt2800_rf_write,
900 .word_base = RF_BASE,
901 .word_size = sizeof(u32),
902 .word_count = RF_SIZE / sizeof(u32),
903 },
904 .rfcsr = {
905 .read = rt2800_rfcsr_read,
906 .write = rt2800_rfcsr_write,
907 .word_base = RFCSR_BASE,
908 .word_size = sizeof(u8),
909 .word_count = RFCSR_SIZE / sizeof(u8),
910 },
911 };
912 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
913 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
914
915 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
916 {
917 u32 reg;
918
919 if (rt2x00_rt(rt2x00dev, RT3290)) {
920 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
921 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
922 } else {
923 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
924 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
925 }
926 }
927 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
928
929 #ifdef CONFIG_RT2X00_LIB_LEDS
930 static void rt2800_brightness_set(struct led_classdev *led_cdev,
931 enum led_brightness brightness)
932 {
933 struct rt2x00_led *led =
934 container_of(led_cdev, struct rt2x00_led, led_dev);
935 unsigned int enabled = brightness != LED_OFF;
936 unsigned int bg_mode =
937 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
938 unsigned int polarity =
939 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
940 EEPROM_FREQ_LED_POLARITY);
941 unsigned int ledmode =
942 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
943 EEPROM_FREQ_LED_MODE);
944 u32 reg;
945
946 /* Check for SoC (SOC devices don't support MCU requests) */
947 if (rt2x00_is_soc(led->rt2x00dev)) {
948 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
949
950 /* Set LED Polarity */
951 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
952
953 /* Set LED Mode */
954 if (led->type == LED_TYPE_RADIO) {
955 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
956 enabled ? 3 : 0);
957 } else if (led->type == LED_TYPE_ASSOC) {
958 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
959 enabled ? 3 : 0);
960 } else if (led->type == LED_TYPE_QUALITY) {
961 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
962 enabled ? 3 : 0);
963 }
964
965 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
966
967 } else {
968 if (led->type == LED_TYPE_RADIO) {
969 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
970 enabled ? 0x20 : 0);
971 } else if (led->type == LED_TYPE_ASSOC) {
972 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
973 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
974 } else if (led->type == LED_TYPE_QUALITY) {
975 /*
976 * The brightness is divided into 6 levels (0 - 5),
977 * The specs tell us the following levels:
978 * 0, 1 ,3, 7, 15, 31
979 * to determine the level in a simple way we can simply
980 * work with bitshifting:
981 * (1 << level) - 1
982 */
983 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
984 (1 << brightness / (LED_FULL / 6)) - 1,
985 polarity);
986 }
987 }
988 }
989
990 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
991 struct rt2x00_led *led, enum led_type type)
992 {
993 led->rt2x00dev = rt2x00dev;
994 led->type = type;
995 led->led_dev.brightness_set = rt2800_brightness_set;
996 led->flags = LED_INITIALIZED;
997 }
998 #endif /* CONFIG_RT2X00_LIB_LEDS */
999
1000 /*
1001 * Configuration handlers.
1002 */
1003 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1004 const u8 *address,
1005 int wcid)
1006 {
1007 struct mac_wcid_entry wcid_entry;
1008 u32 offset;
1009
1010 offset = MAC_WCID_ENTRY(wcid);
1011
1012 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1013 if (address)
1014 memcpy(wcid_entry.mac, address, ETH_ALEN);
1015
1016 rt2800_register_multiwrite(rt2x00dev, offset,
1017 &wcid_entry, sizeof(wcid_entry));
1018 }
1019
1020 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1021 {
1022 u32 offset;
1023 offset = MAC_WCID_ATTR_ENTRY(wcid);
1024 rt2800_register_write(rt2x00dev, offset, 0);
1025 }
1026
1027 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1028 int wcid, u32 bssidx)
1029 {
1030 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1031 u32 reg;
1032
1033 /*
1034 * The BSS Idx numbers is split in a main value of 3 bits,
1035 * and a extended field for adding one additional bit to the value.
1036 */
1037 rt2800_register_read(rt2x00dev, offset, &reg);
1038 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1039 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1040 (bssidx & 0x8) >> 3);
1041 rt2800_register_write(rt2x00dev, offset, reg);
1042 }
1043
1044 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1045 struct rt2x00lib_crypto *crypto,
1046 struct ieee80211_key_conf *key)
1047 {
1048 struct mac_iveiv_entry iveiv_entry;
1049 u32 offset;
1050 u32 reg;
1051
1052 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1053
1054 if (crypto->cmd == SET_KEY) {
1055 rt2800_register_read(rt2x00dev, offset, &reg);
1056 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1057 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1058 /*
1059 * Both the cipher as the BSS Idx numbers are split in a main
1060 * value of 3 bits, and a extended field for adding one additional
1061 * bit to the value.
1062 */
1063 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1064 (crypto->cipher & 0x7));
1065 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1066 (crypto->cipher & 0x8) >> 3);
1067 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1068 rt2800_register_write(rt2x00dev, offset, reg);
1069 } else {
1070 /* Delete the cipher without touching the bssidx */
1071 rt2800_register_read(rt2x00dev, offset, &reg);
1072 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1073 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1074 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1075 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1076 rt2800_register_write(rt2x00dev, offset, reg);
1077 }
1078
1079 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1080
1081 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1082 if ((crypto->cipher == CIPHER_TKIP) ||
1083 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1084 (crypto->cipher == CIPHER_AES))
1085 iveiv_entry.iv[3] |= 0x20;
1086 iveiv_entry.iv[3] |= key->keyidx << 6;
1087 rt2800_register_multiwrite(rt2x00dev, offset,
1088 &iveiv_entry, sizeof(iveiv_entry));
1089 }
1090
1091 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1092 struct rt2x00lib_crypto *crypto,
1093 struct ieee80211_key_conf *key)
1094 {
1095 struct hw_key_entry key_entry;
1096 struct rt2x00_field32 field;
1097 u32 offset;
1098 u32 reg;
1099
1100 if (crypto->cmd == SET_KEY) {
1101 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1102
1103 memcpy(key_entry.key, crypto->key,
1104 sizeof(key_entry.key));
1105 memcpy(key_entry.tx_mic, crypto->tx_mic,
1106 sizeof(key_entry.tx_mic));
1107 memcpy(key_entry.rx_mic, crypto->rx_mic,
1108 sizeof(key_entry.rx_mic));
1109
1110 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1111 rt2800_register_multiwrite(rt2x00dev, offset,
1112 &key_entry, sizeof(key_entry));
1113 }
1114
1115 /*
1116 * The cipher types are stored over multiple registers
1117 * starting with SHARED_KEY_MODE_BASE each word will have
1118 * 32 bits and contains the cipher types for 2 bssidx each.
1119 * Using the correct defines correctly will cause overhead,
1120 * so just calculate the correct offset.
1121 */
1122 field.bit_offset = 4 * (key->hw_key_idx % 8);
1123 field.bit_mask = 0x7 << field.bit_offset;
1124
1125 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1126
1127 rt2800_register_read(rt2x00dev, offset, &reg);
1128 rt2x00_set_field32(&reg, field,
1129 (crypto->cmd == SET_KEY) * crypto->cipher);
1130 rt2800_register_write(rt2x00dev, offset, reg);
1131
1132 /*
1133 * Update WCID information
1134 */
1135 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1136 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1137 crypto->bssidx);
1138 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1139
1140 return 0;
1141 }
1142 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1143
1144 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1145 {
1146 struct mac_wcid_entry wcid_entry;
1147 int idx;
1148 u32 offset;
1149
1150 /*
1151 * Search for the first free WCID entry and return the corresponding
1152 * index.
1153 *
1154 * Make sure the WCID starts _after_ the last possible shared key
1155 * entry (>32).
1156 *
1157 * Since parts of the pairwise key table might be shared with
1158 * the beacon frame buffers 6 & 7 we should only write into the
1159 * first 222 entries.
1160 */
1161 for (idx = 33; idx <= 222; idx++) {
1162 offset = MAC_WCID_ENTRY(idx);
1163 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1164 sizeof(wcid_entry));
1165 if (is_broadcast_ether_addr(wcid_entry.mac))
1166 return idx;
1167 }
1168
1169 /*
1170 * Use -1 to indicate that we don't have any more space in the WCID
1171 * table.
1172 */
1173 return -1;
1174 }
1175
1176 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1177 struct rt2x00lib_crypto *crypto,
1178 struct ieee80211_key_conf *key)
1179 {
1180 struct hw_key_entry key_entry;
1181 u32 offset;
1182
1183 if (crypto->cmd == SET_KEY) {
1184 /*
1185 * Allow key configuration only for STAs that are
1186 * known by the hw.
1187 */
1188 if (crypto->wcid < 0)
1189 return -ENOSPC;
1190 key->hw_key_idx = crypto->wcid;
1191
1192 memcpy(key_entry.key, crypto->key,
1193 sizeof(key_entry.key));
1194 memcpy(key_entry.tx_mic, crypto->tx_mic,
1195 sizeof(key_entry.tx_mic));
1196 memcpy(key_entry.rx_mic, crypto->rx_mic,
1197 sizeof(key_entry.rx_mic));
1198
1199 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1200 rt2800_register_multiwrite(rt2x00dev, offset,
1201 &key_entry, sizeof(key_entry));
1202 }
1203
1204 /*
1205 * Update WCID information
1206 */
1207 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1208
1209 return 0;
1210 }
1211 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1212
1213 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1214 struct ieee80211_sta *sta)
1215 {
1216 int wcid;
1217 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1218
1219 /*
1220 * Find next free WCID.
1221 */
1222 wcid = rt2800_find_wcid(rt2x00dev);
1223
1224 /*
1225 * Store selected wcid even if it is invalid so that we can
1226 * later decide if the STA is uploaded into the hw.
1227 */
1228 sta_priv->wcid = wcid;
1229
1230 /*
1231 * No space left in the device, however, we can still communicate
1232 * with the STA -> No error.
1233 */
1234 if (wcid < 0)
1235 return 0;
1236
1237 /*
1238 * Clean up WCID attributes and write STA address to the device.
1239 */
1240 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1241 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1242 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1243 rt2x00lib_get_bssidx(rt2x00dev, vif));
1244 return 0;
1245 }
1246 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1247
1248 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1249 {
1250 /*
1251 * Remove WCID entry, no need to clean the attributes as they will
1252 * get renewed when the WCID is reused.
1253 */
1254 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1255
1256 return 0;
1257 }
1258 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1259
1260 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1261 const unsigned int filter_flags)
1262 {
1263 u32 reg;
1264
1265 /*
1266 * Start configuration steps.
1267 * Note that the version error will always be dropped
1268 * and broadcast frames will always be accepted since
1269 * there is no filter for it at this time.
1270 */
1271 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1272 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1273 !(filter_flags & FIF_FCSFAIL));
1274 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1275 !(filter_flags & FIF_PLCPFAIL));
1276 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1277 !(filter_flags & FIF_PROMISC_IN_BSS));
1278 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1279 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1280 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1281 !(filter_flags & FIF_ALLMULTI));
1282 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1283 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1284 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1285 !(filter_flags & FIF_CONTROL));
1286 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1287 !(filter_flags & FIF_CONTROL));
1288 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1289 !(filter_flags & FIF_CONTROL));
1290 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1291 !(filter_flags & FIF_CONTROL));
1292 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1293 !(filter_flags & FIF_CONTROL));
1294 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1295 !(filter_flags & FIF_PSPOLL));
1296 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1297 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1298 !(filter_flags & FIF_CONTROL));
1299 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1300 !(filter_flags & FIF_CONTROL));
1301 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1302 }
1303 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1304
1305 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1306 struct rt2x00intf_conf *conf, const unsigned int flags)
1307 {
1308 u32 reg;
1309 bool update_bssid = false;
1310
1311 if (flags & CONFIG_UPDATE_TYPE) {
1312 /*
1313 * Enable synchronisation.
1314 */
1315 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1316 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1317 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1318
1319 if (conf->sync == TSF_SYNC_AP_NONE) {
1320 /*
1321 * Tune beacon queue transmit parameters for AP mode
1322 */
1323 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1324 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1325 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1326 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1327 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1328 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1329 } else {
1330 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1331 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1332 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1333 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1334 rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1335 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1336 }
1337 }
1338
1339 if (flags & CONFIG_UPDATE_MAC) {
1340 if (flags & CONFIG_UPDATE_TYPE &&
1341 conf->sync == TSF_SYNC_AP_NONE) {
1342 /*
1343 * The BSSID register has to be set to our own mac
1344 * address in AP mode.
1345 */
1346 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1347 update_bssid = true;
1348 }
1349
1350 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1351 reg = le32_to_cpu(conf->mac[1]);
1352 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1353 conf->mac[1] = cpu_to_le32(reg);
1354 }
1355
1356 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1357 conf->mac, sizeof(conf->mac));
1358 }
1359
1360 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1361 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1362 reg = le32_to_cpu(conf->bssid[1]);
1363 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1364 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1365 conf->bssid[1] = cpu_to_le32(reg);
1366 }
1367
1368 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1369 conf->bssid, sizeof(conf->bssid));
1370 }
1371 }
1372 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1373
1374 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1375 struct rt2x00lib_erp *erp)
1376 {
1377 bool any_sta_nongf = !!(erp->ht_opmode &
1378 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1379 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1380 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1381 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1382 u32 reg;
1383
1384 /* default protection rate for HT20: OFDM 24M */
1385 mm20_rate = gf20_rate = 0x4004;
1386
1387 /* default protection rate for HT40: duplicate OFDM 24M */
1388 mm40_rate = gf40_rate = 0x4084;
1389
1390 switch (protection) {
1391 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1392 /*
1393 * All STAs in this BSS are HT20/40 but there might be
1394 * STAs not supporting greenfield mode.
1395 * => Disable protection for HT transmissions.
1396 */
1397 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1398
1399 break;
1400 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1401 /*
1402 * All STAs in this BSS are HT20 or HT20/40 but there
1403 * might be STAs not supporting greenfield mode.
1404 * => Protect all HT40 transmissions.
1405 */
1406 mm20_mode = gf20_mode = 0;
1407 mm40_mode = gf40_mode = 2;
1408
1409 break;
1410 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1411 /*
1412 * Nonmember protection:
1413 * According to 802.11n we _should_ protect all
1414 * HT transmissions (but we don't have to).
1415 *
1416 * But if cts_protection is enabled we _shall_ protect
1417 * all HT transmissions using a CCK rate.
1418 *
1419 * And if any station is non GF we _shall_ protect
1420 * GF transmissions.
1421 *
1422 * We decide to protect everything
1423 * -> fall through to mixed mode.
1424 */
1425 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1426 /*
1427 * Legacy STAs are present
1428 * => Protect all HT transmissions.
1429 */
1430 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1431
1432 /*
1433 * If erp protection is needed we have to protect HT
1434 * transmissions with CCK 11M long preamble.
1435 */
1436 if (erp->cts_protection) {
1437 /* don't duplicate RTS/CTS in CCK mode */
1438 mm20_rate = mm40_rate = 0x0003;
1439 gf20_rate = gf40_rate = 0x0003;
1440 }
1441 break;
1442 }
1443
1444 /* check for STAs not supporting greenfield mode */
1445 if (any_sta_nongf)
1446 gf20_mode = gf40_mode = 2;
1447
1448 /* Update HT protection config */
1449 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1450 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1451 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1452 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1453
1454 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1455 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1456 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1457 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1458
1459 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1460 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1461 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1462 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1463
1464 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1465 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1466 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1467 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1468 }
1469
1470 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1471 u32 changed)
1472 {
1473 u32 reg;
1474
1475 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1476 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1477 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1478 !!erp->short_preamble);
1479 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1480 !!erp->short_preamble);
1481 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1482 }
1483
1484 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1485 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1486 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1487 erp->cts_protection ? 2 : 0);
1488 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1489 }
1490
1491 if (changed & BSS_CHANGED_BASIC_RATES) {
1492 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1493 erp->basic_rates);
1494 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1495 }
1496
1497 if (changed & BSS_CHANGED_ERP_SLOT) {
1498 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1499 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1500 erp->slot_time);
1501 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1502
1503 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1504 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1505 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1506 }
1507
1508 if (changed & BSS_CHANGED_BEACON_INT) {
1509 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1510 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1511 erp->beacon_int * 16);
1512 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1513 }
1514
1515 if (changed & BSS_CHANGED_HT)
1516 rt2800_config_ht_opmode(rt2x00dev, erp);
1517 }
1518 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1519
1520 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1521 {
1522 u32 reg;
1523 u16 eeprom;
1524 u8 led_ctrl, led_g_mode, led_r_mode;
1525
1526 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1527 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1528 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1529 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1530 } else {
1531 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1532 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1533 }
1534 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1535
1536 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1537 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1538 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1539 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1540 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1541 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1542 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1543 if (led_ctrl == 0 || led_ctrl > 0x40) {
1544 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1545 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1546 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1547 } else {
1548 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1549 (led_g_mode << 2) | led_r_mode, 1);
1550 }
1551 }
1552 }
1553
1554 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1555 enum antenna ant)
1556 {
1557 u32 reg;
1558 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1559 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1560
1561 if (rt2x00_is_pci(rt2x00dev)) {
1562 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1563 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1564 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1565 } else if (rt2x00_is_usb(rt2x00dev))
1566 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1567 eesk_pin, 0);
1568
1569 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1570 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1571 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1572 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1573 }
1574
1575 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1576 {
1577 u8 r1;
1578 u8 r3;
1579 u16 eeprom;
1580
1581 rt2800_bbp_read(rt2x00dev, 1, &r1);
1582 rt2800_bbp_read(rt2x00dev, 3, &r3);
1583
1584 if (rt2x00_rt(rt2x00dev, RT3572) &&
1585 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1586 rt2800_config_3572bt_ant(rt2x00dev);
1587
1588 /*
1589 * Configure the TX antenna.
1590 */
1591 switch (ant->tx_chain_num) {
1592 case 1:
1593 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1594 break;
1595 case 2:
1596 if (rt2x00_rt(rt2x00dev, RT3572) &&
1597 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1598 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1599 else
1600 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1601 break;
1602 case 3:
1603 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1604 break;
1605 }
1606
1607 /*
1608 * Configure the RX antenna.
1609 */
1610 switch (ant->rx_chain_num) {
1611 case 1:
1612 if (rt2x00_rt(rt2x00dev, RT3070) ||
1613 rt2x00_rt(rt2x00dev, RT3090) ||
1614 rt2x00_rt(rt2x00dev, RT3352) ||
1615 rt2x00_rt(rt2x00dev, RT3390)) {
1616 rt2x00_eeprom_read(rt2x00dev,
1617 EEPROM_NIC_CONF1, &eeprom);
1618 if (rt2x00_get_field16(eeprom,
1619 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1620 rt2800_set_ant_diversity(rt2x00dev,
1621 rt2x00dev->default_ant.rx);
1622 }
1623 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1624 break;
1625 case 2:
1626 if (rt2x00_rt(rt2x00dev, RT3572) &&
1627 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1628 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1629 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1630 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1631 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1632 } else {
1633 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1634 }
1635 break;
1636 case 3:
1637 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1638 break;
1639 }
1640
1641 rt2800_bbp_write(rt2x00dev, 3, r3);
1642 rt2800_bbp_write(rt2x00dev, 1, r1);
1643 }
1644 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1645
1646 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1647 struct rt2x00lib_conf *libconf)
1648 {
1649 u16 eeprom;
1650 short lna_gain;
1651
1652 if (libconf->rf.channel <= 14) {
1653 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1654 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1655 } else if (libconf->rf.channel <= 64) {
1656 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1657 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1658 } else if (libconf->rf.channel <= 128) {
1659 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1660 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1661 } else {
1662 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1663 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1664 }
1665
1666 rt2x00dev->lna_gain = lna_gain;
1667 }
1668
1669 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1670 struct ieee80211_conf *conf,
1671 struct rf_channel *rf,
1672 struct channel_info *info)
1673 {
1674 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1675
1676 if (rt2x00dev->default_ant.tx_chain_num == 1)
1677 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1678
1679 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1680 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1681 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1682 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1683 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1684
1685 if (rf->channel > 14) {
1686 /*
1687 * When TX power is below 0, we should increase it by 7 to
1688 * make it a positive value (Minimum value is -7).
1689 * However this means that values between 0 and 7 have
1690 * double meaning, and we should set a 7DBm boost flag.
1691 */
1692 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1693 (info->default_power1 >= 0));
1694
1695 if (info->default_power1 < 0)
1696 info->default_power1 += 7;
1697
1698 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1699
1700 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1701 (info->default_power2 >= 0));
1702
1703 if (info->default_power2 < 0)
1704 info->default_power2 += 7;
1705
1706 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1707 } else {
1708 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1709 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1710 }
1711
1712 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1713
1714 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1715 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1716 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1717 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1718
1719 udelay(200);
1720
1721 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1722 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1723 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1724 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1725
1726 udelay(200);
1727
1728 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1729 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1730 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1731 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1732 }
1733
1734 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1735 struct ieee80211_conf *conf,
1736 struct rf_channel *rf,
1737 struct channel_info *info)
1738 {
1739 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1740 u8 rfcsr, calib_tx, calib_rx;
1741
1742 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1743
1744 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1745 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1746 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1747
1748 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1749 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1750 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1751
1752 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1753 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1754 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1755
1756 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1757 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1758 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1759
1760 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1761 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1762 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1763 rt2x00dev->default_ant.rx_chain_num <= 1);
1764 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1765 rt2x00dev->default_ant.rx_chain_num <= 2);
1766 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1767 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1768 rt2x00dev->default_ant.tx_chain_num <= 1);
1769 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1770 rt2x00dev->default_ant.tx_chain_num <= 2);
1771 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1772
1773 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1774 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1775 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1776 msleep(1);
1777 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1778 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1779
1780 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1781 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1782 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1783
1784 if (rt2x00_rt(rt2x00dev, RT3390)) {
1785 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1786 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1787 } else {
1788 if (conf_is_ht40(conf)) {
1789 calib_tx = drv_data->calibration_bw40;
1790 calib_rx = drv_data->calibration_bw40;
1791 } else {
1792 calib_tx = drv_data->calibration_bw20;
1793 calib_rx = drv_data->calibration_bw20;
1794 }
1795 }
1796
1797 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1798 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1799 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1800
1801 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1802 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1803 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1804
1805 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1806 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1807 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1808
1809 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1810 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1811 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1812 msleep(1);
1813 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1814 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1815 }
1816
1817 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1818 struct ieee80211_conf *conf,
1819 struct rf_channel *rf,
1820 struct channel_info *info)
1821 {
1822 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1823 u8 rfcsr;
1824 u32 reg;
1825
1826 if (rf->channel <= 14) {
1827 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1828 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1829 } else {
1830 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1831 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1832 }
1833
1834 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1835 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1836
1837 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1838 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1839 if (rf->channel <= 14)
1840 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1841 else
1842 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1843 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1844
1845 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1846 if (rf->channel <= 14)
1847 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1848 else
1849 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1850 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1851
1852 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1853 if (rf->channel <= 14) {
1854 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1855 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1856 info->default_power1);
1857 } else {
1858 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1859 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1860 (info->default_power1 & 0x3) |
1861 ((info->default_power1 & 0xC) << 1));
1862 }
1863 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1864
1865 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1866 if (rf->channel <= 14) {
1867 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1868 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1869 info->default_power2);
1870 } else {
1871 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1872 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1873 (info->default_power2 & 0x3) |
1874 ((info->default_power2 & 0xC) << 1));
1875 }
1876 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1877
1878 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1879 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1880 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1881 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1882 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1883 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1885 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1886 if (rf->channel <= 14) {
1887 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1888 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1889 }
1890 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1891 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1892 } else {
1893 switch (rt2x00dev->default_ant.tx_chain_num) {
1894 case 1:
1895 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1896 case 2:
1897 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1898 break;
1899 }
1900
1901 switch (rt2x00dev->default_ant.rx_chain_num) {
1902 case 1:
1903 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1904 case 2:
1905 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1906 break;
1907 }
1908 }
1909 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1910
1911 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1912 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1913 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1914
1915 if (conf_is_ht40(conf)) {
1916 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1917 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1918 } else {
1919 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1920 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1921 }
1922
1923 if (rf->channel <= 14) {
1924 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1925 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1926 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1927 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1928 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1929 rfcsr = 0x4c;
1930 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1931 drv_data->txmixer_gain_24g);
1932 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1933 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1934 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1935 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1936 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1937 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1938 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1939 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1940 } else {
1941 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1942 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1943 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1944 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1945 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1946 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1947 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1948 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1949 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1950 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1951 rfcsr = 0x7a;
1952 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1953 drv_data->txmixer_gain_5g);
1954 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1955 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1956 if (rf->channel <= 64) {
1957 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1958 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1959 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1960 } else if (rf->channel <= 128) {
1961 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1962 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1963 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1964 } else {
1965 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1966 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1967 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1968 }
1969 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1970 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1971 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1972 }
1973
1974 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1975 rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1976 if (rf->channel <= 14)
1977 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1978 else
1979 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1980 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1981
1982 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1983 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1984 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1985 }
1986
1987 #define POWER_BOUND 0x27
1988 #define POWER_BOUND_5G 0x2b
1989 #define FREQ_OFFSET_BOUND 0x5f
1990
1991 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1992 {
1993 u8 rfcsr;
1994
1995 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1996 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
1997 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
1998 else
1999 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2000 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2001 }
2002
2003 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2004 struct ieee80211_conf *conf,
2005 struct rf_channel *rf,
2006 struct channel_info *info)
2007 {
2008 u8 rfcsr;
2009
2010 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2011 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2012 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2013 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2014 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2015
2016 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2017 if (info->default_power1 > POWER_BOUND)
2018 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2019 else
2020 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2021 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2022
2023 rt2800_adjust_freq_offset(rt2x00dev);
2024
2025 if (rf->channel <= 14) {
2026 if (rf->channel == 6)
2027 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2028 else
2029 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2030
2031 if (rf->channel >= 1 && rf->channel <= 6)
2032 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2033 else if (rf->channel >= 7 && rf->channel <= 11)
2034 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2035 else if (rf->channel >= 12 && rf->channel <= 14)
2036 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2037 }
2038 }
2039
2040 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2041 struct ieee80211_conf *conf,
2042 struct rf_channel *rf,
2043 struct channel_info *info)
2044 {
2045 u8 rfcsr;
2046
2047 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2048 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2049
2050 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2051 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2052 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2053
2054 if (info->default_power1 > POWER_BOUND)
2055 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2056 else
2057 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2058
2059 if (info->default_power2 > POWER_BOUND)
2060 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2061 else
2062 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2063
2064 rt2800_adjust_freq_offset(rt2x00dev);
2065
2066 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2067 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2068 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2069
2070 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2071 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2072 else
2073 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2074
2075 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2076 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2077 else
2078 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2079
2080 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2081 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2082
2083 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2084
2085 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2086 }
2087
2088 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2089 struct ieee80211_conf *conf,
2090 struct rf_channel *rf,
2091 struct channel_info *info)
2092 {
2093 u8 rfcsr;
2094
2095 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2096 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2097 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2098 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2099 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2100
2101 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2102 if (info->default_power1 > POWER_BOUND)
2103 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2104 else
2105 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2106 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2107
2108 if (rt2x00_rt(rt2x00dev, RT5392)) {
2109 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2110 if (info->default_power1 > POWER_BOUND)
2111 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2112 else
2113 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2114 info->default_power2);
2115 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2116 }
2117
2118 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2119 if (rt2x00_rt(rt2x00dev, RT5392)) {
2120 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2121 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2122 }
2123 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2124 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2125 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2126 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2127 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2128
2129 rt2800_adjust_freq_offset(rt2x00dev);
2130
2131 if (rf->channel <= 14) {
2132 int idx = rf->channel-1;
2133
2134 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2135 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2136 /* r55/r59 value array of channel 1~14 */
2137 static const char r55_bt_rev[] = {0x83, 0x83,
2138 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2139 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2140 static const char r59_bt_rev[] = {0x0e, 0x0e,
2141 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2142 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2143
2144 rt2800_rfcsr_write(rt2x00dev, 55,
2145 r55_bt_rev[idx]);
2146 rt2800_rfcsr_write(rt2x00dev, 59,
2147 r59_bt_rev[idx]);
2148 } else {
2149 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2150 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2151 0x88, 0x88, 0x86, 0x85, 0x84};
2152
2153 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2154 }
2155 } else {
2156 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2157 static const char r55_nonbt_rev[] = {0x23, 0x23,
2158 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2159 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2160 static const char r59_nonbt_rev[] = {0x07, 0x07,
2161 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2162 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2163
2164 rt2800_rfcsr_write(rt2x00dev, 55,
2165 r55_nonbt_rev[idx]);
2166 rt2800_rfcsr_write(rt2x00dev, 59,
2167 r59_nonbt_rev[idx]);
2168 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2169 rt2x00_rt(rt2x00dev, RT5392)) {
2170 static const char r59_non_bt[] = {0x8f, 0x8f,
2171 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2172 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2173
2174 rt2800_rfcsr_write(rt2x00dev, 59,
2175 r59_non_bt[idx]);
2176 }
2177 }
2178 }
2179 }
2180
2181 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2182 struct ieee80211_conf *conf,
2183 struct rf_channel *rf,
2184 struct channel_info *info)
2185 {
2186 u8 rfcsr, ep_reg;
2187 u32 reg;
2188 int power_bound;
2189
2190 /* TODO */
2191 const bool is_11b = false;
2192 const bool is_type_ep = false;
2193
2194 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2195 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2196 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2197 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2198
2199 /* Order of values on rf_channel entry: N, K, mod, R */
2200 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2201
2202 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2203 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2204 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2205 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2206 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2207
2208 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2209 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2210 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2211 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2212
2213 if (rf->channel <= 14) {
2214 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2215 /* FIXME: RF11 owerwrite ? */
2216 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2217 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2218 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2219 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2220 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2221 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2222 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2223 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2224 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2225 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2226 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2227 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2228 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2229 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2230 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2231 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2232 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2233 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2234 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2235 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2236 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2237 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2238 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2239 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2240 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2241 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2242 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2243 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2244
2245 /* TODO RF27 <- tssi */
2246
2247 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2248 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2249 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2250
2251 if (is_11b) {
2252 /* CCK */
2253 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2254 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2255 if (is_type_ep)
2256 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2257 else
2258 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2259 } else {
2260 /* OFDM */
2261 if (is_type_ep)
2262 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2263 else
2264 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2265 }
2266
2267 power_bound = POWER_BOUND;
2268 ep_reg = 0x2;
2269 } else {
2270 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2271 /* FIMXE: RF11 overwrite */
2272 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2273 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2274 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2275 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2276 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2277 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2278 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2279 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2280 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2281 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2282 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2283 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2284 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2285 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2286
2287 /* TODO RF27 <- tssi */
2288
2289 if (rf->channel >= 36 && rf->channel <= 64) {
2290
2291 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2292 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2293 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2294 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2295 if (rf->channel <= 50)
2296 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2297 else if (rf->channel >= 52)
2298 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2299 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2300 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2301 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2302 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2303 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2304 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2305 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2306 if (rf->channel <= 50) {
2307 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2308 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2309 } else if (rf->channel >= 52) {
2310 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2311 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2312 }
2313
2314 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2315 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2316 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2317
2318 } else if (rf->channel >= 100 && rf->channel <= 165) {
2319
2320 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2321 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2322 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2323 if (rf->channel <= 153) {
2324 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2325 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2326 } else if (rf->channel >= 155) {
2327 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2328 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2329 }
2330 if (rf->channel <= 138) {
2331 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2332 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2333 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2334 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2335 } else if (rf->channel >= 140) {
2336 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2337 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2338 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2339 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2340 }
2341 if (rf->channel <= 124)
2342 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2343 else if (rf->channel >= 126)
2344 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2345 if (rf->channel <= 138)
2346 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2347 else if (rf->channel >= 140)
2348 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2349 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2350 if (rf->channel <= 138)
2351 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2352 else if (rf->channel >= 140)
2353 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2354 if (rf->channel <= 128)
2355 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2356 else if (rf->channel >= 130)
2357 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2358 if (rf->channel <= 116)
2359 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2360 else if (rf->channel >= 118)
2361 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2362 if (rf->channel <= 138)
2363 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2364 else if (rf->channel >= 140)
2365 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2366 if (rf->channel <= 116)
2367 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2368 else if (rf->channel >= 118)
2369 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2370 }
2371
2372 power_bound = POWER_BOUND_5G;
2373 ep_reg = 0x3;
2374 }
2375
2376 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2377 if (info->default_power1 > power_bound)
2378 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2379 else
2380 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2381 if (is_type_ep)
2382 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2383 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2384
2385 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2386 if (info->default_power1 > power_bound)
2387 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2388 else
2389 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2390 if (is_type_ep)
2391 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2392 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2393
2394 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2395 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2396 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2397
2398 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2399 rt2x00dev->default_ant.tx_chain_num >= 1);
2400 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2401 rt2x00dev->default_ant.tx_chain_num == 2);
2402 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2403
2404 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2405 rt2x00dev->default_ant.rx_chain_num >= 1);
2406 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2407 rt2x00dev->default_ant.rx_chain_num == 2);
2408 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2409
2410 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2411 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2412
2413 if (conf_is_ht40(conf))
2414 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2415 else
2416 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2417
2418 if (!is_11b) {
2419 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2420 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2421 }
2422
2423 /* TODO proper frequency adjustment */
2424 rt2800_adjust_freq_offset(rt2x00dev);
2425
2426 /* TODO merge with others */
2427 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2428 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2429 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2430
2431 /* BBP settings */
2432 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2433 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2434 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2435
2436 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2437 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2438 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2439 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2440
2441 /* GLRT band configuration */
2442 rt2800_bbp_write(rt2x00dev, 195, 128);
2443 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2444 rt2800_bbp_write(rt2x00dev, 195, 129);
2445 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2446 rt2800_bbp_write(rt2x00dev, 195, 130);
2447 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2448 rt2800_bbp_write(rt2x00dev, 195, 131);
2449 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2450 rt2800_bbp_write(rt2x00dev, 195, 133);
2451 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2452 rt2800_bbp_write(rt2x00dev, 195, 124);
2453 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2454 }
2455
2456 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2457 const unsigned int word,
2458 const u8 value)
2459 {
2460 u8 chain, reg;
2461
2462 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2463 rt2800_bbp_read(rt2x00dev, 27, &reg);
2464 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2465 rt2800_bbp_write(rt2x00dev, 27, reg);
2466
2467 rt2800_bbp_write(rt2x00dev, word, value);
2468 }
2469 }
2470
2471 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2472 {
2473 u8 cal;
2474
2475 /* TX0 IQ Gain */
2476 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2477 if (channel <= 14)
2478 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2479 else if (channel >= 36 && channel <= 64)
2480 cal = rt2x00_eeprom_byte(rt2x00dev,
2481 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2482 else if (channel >= 100 && channel <= 138)
2483 cal = rt2x00_eeprom_byte(rt2x00dev,
2484 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2485 else if (channel >= 140 && channel <= 165)
2486 cal = rt2x00_eeprom_byte(rt2x00dev,
2487 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2488 else
2489 cal = 0;
2490 rt2800_bbp_write(rt2x00dev, 159, cal);
2491
2492 /* TX0 IQ Phase */
2493 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2494 if (channel <= 14)
2495 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2496 else if (channel >= 36 && channel <= 64)
2497 cal = rt2x00_eeprom_byte(rt2x00dev,
2498 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2499 else if (channel >= 100 && channel <= 138)
2500 cal = rt2x00_eeprom_byte(rt2x00dev,
2501 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2502 else if (channel >= 140 && channel <= 165)
2503 cal = rt2x00_eeprom_byte(rt2x00dev,
2504 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2505 else
2506 cal = 0;
2507 rt2800_bbp_write(rt2x00dev, 159, cal);
2508
2509 /* TX1 IQ Gain */
2510 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2511 if (channel <= 14)
2512 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2513 else if (channel >= 36 && channel <= 64)
2514 cal = rt2x00_eeprom_byte(rt2x00dev,
2515 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2516 else if (channel >= 100 && channel <= 138)
2517 cal = rt2x00_eeprom_byte(rt2x00dev,
2518 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2519 else if (channel >= 140 && channel <= 165)
2520 cal = rt2x00_eeprom_byte(rt2x00dev,
2521 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2522 else
2523 cal = 0;
2524 rt2800_bbp_write(rt2x00dev, 159, cal);
2525
2526 /* TX1 IQ Phase */
2527 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2528 if (channel <= 14)
2529 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2530 else if (channel >= 36 && channel <= 64)
2531 cal = rt2x00_eeprom_byte(rt2x00dev,
2532 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2533 else if (channel >= 100 && channel <= 138)
2534 cal = rt2x00_eeprom_byte(rt2x00dev,
2535 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2536 else if (channel >= 140 && channel <= 165)
2537 cal = rt2x00_eeprom_byte(rt2x00dev,
2538 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2539 else
2540 cal = 0;
2541 rt2800_bbp_write(rt2x00dev, 159, cal);
2542
2543 /* FIXME: possible RX0, RX1 callibration ? */
2544
2545 /* RF IQ compensation control */
2546 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2547 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2548 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2549
2550 /* RF IQ imbalance compensation control */
2551 rt2800_bbp_write(rt2x00dev, 158, 0x03);
2552 cal = rt2x00_eeprom_byte(rt2x00dev,
2553 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2554 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2555 }
2556
2557 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2558 struct ieee80211_conf *conf,
2559 struct rf_channel *rf,
2560 struct channel_info *info)
2561 {
2562 u32 reg;
2563 unsigned int tx_pin;
2564 u8 bbp, rfcsr;
2565
2566 if (rf->channel <= 14) {
2567 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2568 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2569 } else {
2570 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2571 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2572 }
2573
2574 switch (rt2x00dev->chip.rf) {
2575 case RF2020:
2576 case RF3020:
2577 case RF3021:
2578 case RF3022:
2579 case RF3320:
2580 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2581 break;
2582 case RF3052:
2583 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2584 break;
2585 case RF3290:
2586 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2587 break;
2588 case RF3322:
2589 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2590 break;
2591 case RF5360:
2592 case RF5370:
2593 case RF5372:
2594 case RF5390:
2595 case RF5392:
2596 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2597 break;
2598 case RF5592:
2599 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2600 break;
2601 default:
2602 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2603 }
2604
2605 if (rt2x00_rf(rt2x00dev, RF3290) ||
2606 rt2x00_rf(rt2x00dev, RF3322) ||
2607 rt2x00_rf(rt2x00dev, RF5360) ||
2608 rt2x00_rf(rt2x00dev, RF5370) ||
2609 rt2x00_rf(rt2x00dev, RF5372) ||
2610 rt2x00_rf(rt2x00dev, RF5390) ||
2611 rt2x00_rf(rt2x00dev, RF5392)) {
2612 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2613 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2614 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2615 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2616
2617 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2618 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2619 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2620 }
2621
2622 /*
2623 * Change BBP settings
2624 */
2625 if (rt2x00_rt(rt2x00dev, RT3352)) {
2626 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2627 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2628 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2629 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2630 } else {
2631 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2632 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2633 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2634 rt2800_bbp_write(rt2x00dev, 86, 0);
2635 }
2636
2637 if (rf->channel <= 14) {
2638 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2639 !rt2x00_rt(rt2x00dev, RT5392)) {
2640 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2641 &rt2x00dev->cap_flags)) {
2642 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2643 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2644 } else {
2645 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2646 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2647 }
2648 }
2649 } else {
2650 if (rt2x00_rt(rt2x00dev, RT3572))
2651 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2652 else
2653 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2654
2655 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2656 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2657 else
2658 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2659 }
2660
2661 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2662 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2663 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2664 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2665 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2666
2667 if (rt2x00_rt(rt2x00dev, RT3572))
2668 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2669
2670 tx_pin = 0;
2671
2672 /* Turn on unused PA or LNA when not using 1T or 1R */
2673 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2674 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2675 rf->channel > 14);
2676 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2677 rf->channel <= 14);
2678 }
2679
2680 /* Turn on unused PA or LNA when not using 1T or 1R */
2681 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2682 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2683 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2684 }
2685
2686 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2687 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2688 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2689 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2690 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2691 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2692 else
2693 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2694 rf->channel <= 14);
2695 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2696
2697 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2698
2699 if (rt2x00_rt(rt2x00dev, RT3572))
2700 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2701
2702 if (rt2x00_rt(rt2x00dev, RT5592)) {
2703 rt2800_bbp_write(rt2x00dev, 195, 141);
2704 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2705
2706 /* AGC init */
2707 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2708 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2709
2710 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2711 }
2712
2713 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2714 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2715 rt2800_bbp_write(rt2x00dev, 4, bbp);
2716
2717 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2718 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2719 rt2800_bbp_write(rt2x00dev, 3, bbp);
2720
2721 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2722 if (conf_is_ht40(conf)) {
2723 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2724 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2725 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2726 } else {
2727 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2728 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2729 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2730 }
2731 }
2732
2733 msleep(1);
2734
2735 /*
2736 * Clear channel statistic counters
2737 */
2738 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2739 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2740 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2741
2742 /*
2743 * Clear update flag
2744 */
2745 if (rt2x00_rt(rt2x00dev, RT3352)) {
2746 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2747 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2748 rt2800_bbp_write(rt2x00dev, 49, bbp);
2749 }
2750 }
2751
2752 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2753 {
2754 u8 tssi_bounds[9];
2755 u8 current_tssi;
2756 u16 eeprom;
2757 u8 step;
2758 int i;
2759
2760 /*
2761 * Read TSSI boundaries for temperature compensation from
2762 * the EEPROM.
2763 *
2764 * Array idx 0 1 2 3 4 5 6 7 8
2765 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2766 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2767 */
2768 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2769 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2770 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2771 EEPROM_TSSI_BOUND_BG1_MINUS4);
2772 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2773 EEPROM_TSSI_BOUND_BG1_MINUS3);
2774
2775 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2776 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2777 EEPROM_TSSI_BOUND_BG2_MINUS2);
2778 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2779 EEPROM_TSSI_BOUND_BG2_MINUS1);
2780
2781 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2782 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2783 EEPROM_TSSI_BOUND_BG3_REF);
2784 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2785 EEPROM_TSSI_BOUND_BG3_PLUS1);
2786
2787 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2788 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2789 EEPROM_TSSI_BOUND_BG4_PLUS2);
2790 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2791 EEPROM_TSSI_BOUND_BG4_PLUS3);
2792
2793 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2794 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2795 EEPROM_TSSI_BOUND_BG5_PLUS4);
2796
2797 step = rt2x00_get_field16(eeprom,
2798 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2799 } else {
2800 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2801 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2802 EEPROM_TSSI_BOUND_A1_MINUS4);
2803 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2804 EEPROM_TSSI_BOUND_A1_MINUS3);
2805
2806 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2807 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2808 EEPROM_TSSI_BOUND_A2_MINUS2);
2809 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2810 EEPROM_TSSI_BOUND_A2_MINUS1);
2811
2812 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2813 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2814 EEPROM_TSSI_BOUND_A3_REF);
2815 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2816 EEPROM_TSSI_BOUND_A3_PLUS1);
2817
2818 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2819 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2820 EEPROM_TSSI_BOUND_A4_PLUS2);
2821 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2822 EEPROM_TSSI_BOUND_A4_PLUS3);
2823
2824 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2825 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2826 EEPROM_TSSI_BOUND_A5_PLUS4);
2827
2828 step = rt2x00_get_field16(eeprom,
2829 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2830 }
2831
2832 /*
2833 * Check if temperature compensation is supported.
2834 */
2835 if (tssi_bounds[4] == 0xff || step == 0xff)
2836 return 0;
2837
2838 /*
2839 * Read current TSSI (BBP 49).
2840 */
2841 rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2842
2843 /*
2844 * Compare TSSI value (BBP49) with the compensation boundaries
2845 * from the EEPROM and increase or decrease tx power.
2846 */
2847 for (i = 0; i <= 3; i++) {
2848 if (current_tssi > tssi_bounds[i])
2849 break;
2850 }
2851
2852 if (i == 4) {
2853 for (i = 8; i >= 5; i--) {
2854 if (current_tssi < tssi_bounds[i])
2855 break;
2856 }
2857 }
2858
2859 return (i - 4) * step;
2860 }
2861
2862 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2863 enum ieee80211_band band)
2864 {
2865 u16 eeprom;
2866 u8 comp_en;
2867 u8 comp_type;
2868 int comp_value = 0;
2869
2870 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2871
2872 /*
2873 * HT40 compensation not required.
2874 */
2875 if (eeprom == 0xffff ||
2876 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2877 return 0;
2878
2879 if (band == IEEE80211_BAND_2GHZ) {
2880 comp_en = rt2x00_get_field16(eeprom,
2881 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2882 if (comp_en) {
2883 comp_type = rt2x00_get_field16(eeprom,
2884 EEPROM_TXPOWER_DELTA_TYPE_2G);
2885 comp_value = rt2x00_get_field16(eeprom,
2886 EEPROM_TXPOWER_DELTA_VALUE_2G);
2887 if (!comp_type)
2888 comp_value = -comp_value;
2889 }
2890 } else {
2891 comp_en = rt2x00_get_field16(eeprom,
2892 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2893 if (comp_en) {
2894 comp_type = rt2x00_get_field16(eeprom,
2895 EEPROM_TXPOWER_DELTA_TYPE_5G);
2896 comp_value = rt2x00_get_field16(eeprom,
2897 EEPROM_TXPOWER_DELTA_VALUE_5G);
2898 if (!comp_type)
2899 comp_value = -comp_value;
2900 }
2901 }
2902
2903 return comp_value;
2904 }
2905
2906 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2907 int power_level, int max_power)
2908 {
2909 int delta;
2910
2911 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2912 return 0;
2913
2914 /*
2915 * XXX: We don't know the maximum transmit power of our hardware since
2916 * the EEPROM doesn't expose it. We only know that we are calibrated
2917 * to 100% tx power.
2918 *
2919 * Hence, we assume the regulatory limit that cfg80211 calulated for
2920 * the current channel is our maximum and if we are requested to lower
2921 * the value we just reduce our tx power accordingly.
2922 */
2923 delta = power_level - max_power;
2924 return min(delta, 0);
2925 }
2926
2927 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2928 enum ieee80211_band band, int power_level,
2929 u8 txpower, int delta)
2930 {
2931 u16 eeprom;
2932 u8 criterion;
2933 u8 eirp_txpower;
2934 u8 eirp_txpower_criterion;
2935 u8 reg_limit;
2936
2937 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2938 /*
2939 * Check if eirp txpower exceed txpower_limit.
2940 * We use OFDM 6M as criterion and its eirp txpower
2941 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2942 * .11b data rate need add additional 4dbm
2943 * when calculating eirp txpower.
2944 */
2945 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2946 &eeprom);
2947 criterion = rt2x00_get_field16(eeprom,
2948 EEPROM_TXPOWER_BYRATE_RATE0);
2949
2950 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2951 &eeprom);
2952
2953 if (band == IEEE80211_BAND_2GHZ)
2954 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2955 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2956 else
2957 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2958 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2959
2960 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2961 (is_rate_b ? 4 : 0) + delta;
2962
2963 reg_limit = (eirp_txpower > power_level) ?
2964 (eirp_txpower - power_level) : 0;
2965 } else
2966 reg_limit = 0;
2967
2968 txpower = max(0, txpower + delta - reg_limit);
2969 return min_t(u8, txpower, 0xc);
2970 }
2971
2972 /*
2973 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2974 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2975 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2976 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2977 * Reference per rate transmit power values are located in the EEPROM at
2978 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2979 * current conditions (i.e. band, bandwidth, temperature, user settings).
2980 */
2981 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2982 struct ieee80211_channel *chan,
2983 int power_level)
2984 {
2985 u8 txpower, r1;
2986 u16 eeprom;
2987 u32 reg, offset;
2988 int i, is_rate_b, delta, power_ctrl;
2989 enum ieee80211_band band = chan->band;
2990
2991 /*
2992 * Calculate HT40 compensation. For 40MHz we need to add or subtract
2993 * value read from EEPROM (different for 2GHz and for 5GHz).
2994 */
2995 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2996
2997 /*
2998 * Calculate temperature compensation. Depends on measurement of current
2999 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3000 * to temperature or maybe other factors) is smaller or bigger than
3001 * expected. We adjust it, based on TSSI reference and boundaries values
3002 * provided in EEPROM.
3003 */
3004 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
3005
3006 /*
3007 * Decrease power according to user settings, on devices with unknown
3008 * maximum tx power. For other devices we take user power_level into
3009 * consideration on rt2800_compensate_txpower().
3010 */
3011 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3012 chan->max_power);
3013
3014 /*
3015 * BBP_R1 controls TX power for all rates, it allow to set the following
3016 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3017 *
3018 * TODO: we do not use +6 dBm option to do not increase power beyond
3019 * regulatory limit, however this could be utilized for devices with
3020 * CAPABILITY_POWER_LIMIT.
3021 */
3022 rt2800_bbp_read(rt2x00dev, 1, &r1);
3023 if (delta <= -12) {
3024 power_ctrl = 2;
3025 delta += 12;
3026 } else if (delta <= -6) {
3027 power_ctrl = 1;
3028 delta += 6;
3029 } else {
3030 power_ctrl = 0;
3031 }
3032 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3033 rt2800_bbp_write(rt2x00dev, 1, r1);
3034 offset = TX_PWR_CFG_0;
3035
3036 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3037 /* just to be safe */
3038 if (offset > TX_PWR_CFG_4)
3039 break;
3040
3041 rt2800_register_read(rt2x00dev, offset, &reg);
3042
3043 /* read the next four txpower values */
3044 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
3045 &eeprom);
3046
3047 is_rate_b = i ? 0 : 1;
3048 /*
3049 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3050 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3051 * TX_PWR_CFG_4: unknown
3052 */
3053 txpower = rt2x00_get_field16(eeprom,
3054 EEPROM_TXPOWER_BYRATE_RATE0);
3055 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3056 power_level, txpower, delta);
3057 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3058
3059 /*
3060 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3061 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3062 * TX_PWR_CFG_4: unknown
3063 */
3064 txpower = rt2x00_get_field16(eeprom,
3065 EEPROM_TXPOWER_BYRATE_RATE1);
3066 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3067 power_level, txpower, delta);
3068 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3069
3070 /*
3071 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3072 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
3073 * TX_PWR_CFG_4: unknown
3074 */
3075 txpower = rt2x00_get_field16(eeprom,
3076 EEPROM_TXPOWER_BYRATE_RATE2);
3077 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3078 power_level, txpower, delta);
3079 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3080
3081 /*
3082 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3083 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
3084 * TX_PWR_CFG_4: unknown
3085 */
3086 txpower = rt2x00_get_field16(eeprom,
3087 EEPROM_TXPOWER_BYRATE_RATE3);
3088 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3089 power_level, txpower, delta);
3090 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3091
3092 /* read the next four txpower values */
3093 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3094 &eeprom);
3095
3096 is_rate_b = 0;
3097 /*
3098 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3099 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3100 * TX_PWR_CFG_4: unknown
3101 */
3102 txpower = rt2x00_get_field16(eeprom,
3103 EEPROM_TXPOWER_BYRATE_RATE0);
3104 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3105 power_level, txpower, delta);
3106 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3107
3108 /*
3109 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3110 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3111 * TX_PWR_CFG_4: unknown
3112 */
3113 txpower = rt2x00_get_field16(eeprom,
3114 EEPROM_TXPOWER_BYRATE_RATE1);
3115 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3116 power_level, txpower, delta);
3117 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3118
3119 /*
3120 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3121 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3122 * TX_PWR_CFG_4: unknown
3123 */
3124 txpower = rt2x00_get_field16(eeprom,
3125 EEPROM_TXPOWER_BYRATE_RATE2);
3126 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3127 power_level, txpower, delta);
3128 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3129
3130 /*
3131 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3132 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3133 * TX_PWR_CFG_4: unknown
3134 */
3135 txpower = rt2x00_get_field16(eeprom,
3136 EEPROM_TXPOWER_BYRATE_RATE3);
3137 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3138 power_level, txpower, delta);
3139 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3140
3141 rt2800_register_write(rt2x00dev, offset, reg);
3142
3143 /* next TX_PWR_CFG register */
3144 offset += 4;
3145 }
3146 }
3147
3148 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3149 {
3150 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel,
3151 rt2x00dev->tx_power);
3152 }
3153 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3154
3155 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3156 {
3157 u32 tx_pin;
3158 u8 rfcsr;
3159
3160 /*
3161 * A voltage-controlled oscillator(VCO) is an electronic oscillator
3162 * designed to be controlled in oscillation frequency by a voltage
3163 * input. Maybe the temperature will affect the frequency of
3164 * oscillation to be shifted. The VCO calibration will be called
3165 * periodically to adjust the frequency to be precision.
3166 */
3167
3168 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3169 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3170 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3171
3172 switch (rt2x00dev->chip.rf) {
3173 case RF2020:
3174 case RF3020:
3175 case RF3021:
3176 case RF3022:
3177 case RF3320:
3178 case RF3052:
3179 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3180 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3181 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3182 break;
3183 case RF3290:
3184 case RF5360:
3185 case RF5370:
3186 case RF5372:
3187 case RF5390:
3188 case RF5392:
3189 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3190 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3191 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3192 break;
3193 default:
3194 return;
3195 }
3196
3197 mdelay(1);
3198
3199 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3200 if (rt2x00dev->rf_channel <= 14) {
3201 switch (rt2x00dev->default_ant.tx_chain_num) {
3202 case 3:
3203 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3204 /* fall through */
3205 case 2:
3206 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3207 /* fall through */
3208 case 1:
3209 default:
3210 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3211 break;
3212 }
3213 } else {
3214 switch (rt2x00dev->default_ant.tx_chain_num) {
3215 case 3:
3216 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3217 /* fall through */
3218 case 2:
3219 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3220 /* fall through */
3221 case 1:
3222 default:
3223 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3224 break;
3225 }
3226 }
3227 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3228
3229 }
3230 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3231
3232 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3233 struct rt2x00lib_conf *libconf)
3234 {
3235 u32 reg;
3236
3237 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3238 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3239 libconf->conf->short_frame_max_tx_count);
3240 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3241 libconf->conf->long_frame_max_tx_count);
3242 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3243 }
3244
3245 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3246 struct rt2x00lib_conf *libconf)
3247 {
3248 enum dev_state state =
3249 (libconf->conf->flags & IEEE80211_CONF_PS) ?
3250 STATE_SLEEP : STATE_AWAKE;
3251 u32 reg;
3252
3253 if (state == STATE_SLEEP) {
3254 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3255
3256 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3257 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3258 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3259 libconf->conf->listen_interval - 1);
3260 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3261 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3262
3263 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3264 } else {
3265 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3266 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3267 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3268 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3269 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3270
3271 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3272 }
3273 }
3274
3275 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3276 struct rt2x00lib_conf *libconf,
3277 const unsigned int flags)
3278 {
3279 /* Always recalculate LNA gain before changing configuration */
3280 rt2800_config_lna_gain(rt2x00dev, libconf);
3281
3282 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3283 rt2800_config_channel(rt2x00dev, libconf->conf,
3284 &libconf->rf, &libconf->channel);
3285 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3286 libconf->conf->power_level);
3287 }
3288 if (flags & IEEE80211_CONF_CHANGE_POWER)
3289 rt2800_config_txpower(rt2x00dev, libconf->conf->channel,
3290 libconf->conf->power_level);
3291 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3292 rt2800_config_retry_limit(rt2x00dev, libconf);
3293 if (flags & IEEE80211_CONF_CHANGE_PS)
3294 rt2800_config_ps(rt2x00dev, libconf);
3295 }
3296 EXPORT_SYMBOL_GPL(rt2800_config);
3297
3298 /*
3299 * Link tuning
3300 */
3301 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3302 {
3303 u32 reg;
3304
3305 /*
3306 * Update FCS error count from register.
3307 */
3308 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3309 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3310 }
3311 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3312
3313 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3314 {
3315 u8 vgc;
3316
3317 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3318 if (rt2x00_rt(rt2x00dev, RT3070) ||
3319 rt2x00_rt(rt2x00dev, RT3071) ||
3320 rt2x00_rt(rt2x00dev, RT3090) ||
3321 rt2x00_rt(rt2x00dev, RT3290) ||
3322 rt2x00_rt(rt2x00dev, RT3390) ||
3323 rt2x00_rt(rt2x00dev, RT3572) ||
3324 rt2x00_rt(rt2x00dev, RT5390) ||
3325 rt2x00_rt(rt2x00dev, RT5392) ||
3326 rt2x00_rt(rt2x00dev, RT5592))
3327 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3328 else
3329 vgc = 0x2e + rt2x00dev->lna_gain;
3330 } else { /* 5GHZ band */
3331 if (rt2x00_rt(rt2x00dev, RT3572))
3332 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3333 else if (rt2x00_rt(rt2x00dev, RT5592))
3334 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
3335 else {
3336 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3337 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3338 else
3339 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3340 }
3341 }
3342
3343 return vgc;
3344 }
3345
3346 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3347 struct link_qual *qual, u8 vgc_level)
3348 {
3349 if (qual->vgc_level != vgc_level) {
3350 if (rt2x00_rt(rt2x00dev, RT5592)) {
3351 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3352 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3353 } else
3354 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3355 qual->vgc_level = vgc_level;
3356 qual->vgc_level_reg = vgc_level;
3357 }
3358 }
3359
3360 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3361 {
3362 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3363 }
3364 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3365
3366 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3367 const u32 count)
3368 {
3369 u8 vgc;
3370
3371 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3372 return;
3373 /*
3374 * When RSSI is better then -80 increase VGC level with 0x10, except
3375 * for rt5592 chip.
3376 */
3377
3378 vgc = rt2800_get_default_vgc(rt2x00dev);
3379
3380 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3381 vgc += 0x20;
3382 else if (qual->rssi > -80)
3383 vgc += 0x10;
3384
3385 rt2800_set_vgc(rt2x00dev, qual, vgc);
3386 }
3387 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3388
3389 /*
3390 * Initialization functions.
3391 */
3392 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3393 {
3394 u32 reg;
3395 u16 eeprom;
3396 unsigned int i;
3397 int ret;
3398
3399 rt2800_disable_wpdma(rt2x00dev);
3400
3401 ret = rt2800_drv_init_registers(rt2x00dev);
3402 if (ret)
3403 return ret;
3404
3405 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3406 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3407 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3408 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3409 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3410 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3411
3412 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3413 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3414 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3415 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3416 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3417 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3418
3419 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3420 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3421
3422 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3423
3424 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3425 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3426 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3427 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3428 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3429 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3430 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3431 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3432
3433 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3434
3435 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3436 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3437 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3438 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3439
3440 if (rt2x00_rt(rt2x00dev, RT3290)) {
3441 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3442 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3443 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3444 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3445 }
3446
3447 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3448 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3449 rt2x00_set_field32(&reg, LDO0_EN, 1);
3450 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3451 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3452 }
3453
3454 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3455 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3456 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3457 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3458 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3459
3460 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3461 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3462 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3463
3464 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3465 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3466 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3467 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3468 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3469 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3470
3471 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3472 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3473 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3474 }
3475
3476 if (rt2x00_rt(rt2x00dev, RT3071) ||
3477 rt2x00_rt(rt2x00dev, RT3090) ||
3478 rt2x00_rt(rt2x00dev, RT3290) ||
3479 rt2x00_rt(rt2x00dev, RT3390)) {
3480
3481 if (rt2x00_rt(rt2x00dev, RT3290))
3482 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3483 0x00000404);
3484 else
3485 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3486 0x00000400);
3487
3488 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3489 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3490 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3491 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3492 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3493 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3494 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3495 0x0000002c);
3496 else
3497 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3498 0x0000000f);
3499 } else {
3500 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3501 }
3502 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3503 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3504
3505 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3506 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3507 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3508 } else {
3509 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3510 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3511 }
3512 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3513 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3514 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3515 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3516 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3517 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3518 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3519 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3520 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3521 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3522 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3523 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3524 rt2x00_rt(rt2x00dev, RT5392) ||
3525 rt2x00_rt(rt2x00dev, RT5592)) {
3526 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3527 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3528 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3529 } else {
3530 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3531 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3532 }
3533
3534 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3535 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3536 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3537 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3538 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3539 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3540 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3541 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3542 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3543 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3544
3545 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3546 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3547 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3548 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3549 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3550
3551 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3552 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3553 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3554 rt2x00_rt(rt2x00dev, RT2883) ||
3555 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3556 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3557 else
3558 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3559 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3560 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3561 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3562
3563 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3564 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3565 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3566 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3567 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3568 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3569 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3570 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3571 rt2800_register_write(rt2x00dev, LED_CFG, reg);
3572
3573 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3574
3575 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3576 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3577 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3578 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3579 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3580 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3581 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3582 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3583
3584 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3585 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3586 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3587 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3588 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3589 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3590 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3591 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3592 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3593
3594 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3595 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3596 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3597 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3598 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3599 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3600 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3601 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3602 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3603 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3604 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3605 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3606
3607 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3608 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3609 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3610 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3611 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3612 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3613 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3614 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3615 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3616 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3617 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3618 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3619
3620 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3621 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3622 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3623 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3624 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3625 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3626 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3627 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3628 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3629 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3630 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3631 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3632
3633 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3634 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3635 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3636 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3637 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3638 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3639 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3640 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3641 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3642 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3643 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3644 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3645
3646 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3647 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3648 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3649 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3650 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3651 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3652 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3653 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3654 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3655 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3656 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3657 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3658
3659 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3660 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3661 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3662 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3663 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3664 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3665 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3666 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3667 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3668 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3669 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3670 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3671
3672 if (rt2x00_is_usb(rt2x00dev)) {
3673 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3674
3675 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3676 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3677 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3678 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3679 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3680 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3681 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3682 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3683 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3684 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3685 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3686 }
3687
3688 /*
3689 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3690 * although it is reserved.
3691 */
3692 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3693 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3694 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3695 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3696 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3697 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3698 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3699 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3700 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3701 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3702 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3703 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3704
3705 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3706 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3707
3708 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3709 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3710 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3711 IEEE80211_MAX_RTS_THRESHOLD);
3712 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3713 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3714
3715 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3716
3717 /*
3718 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3719 * time should be set to 16. However, the original Ralink driver uses
3720 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3721 * connection problems with 11g + CTS protection. Hence, use the same
3722 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3723 */
3724 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3725 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3726 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3727 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3728 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3729 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3730 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3731
3732 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3733
3734 /*
3735 * ASIC will keep garbage value after boot, clear encryption keys.
3736 */
3737 for (i = 0; i < 4; i++)
3738 rt2800_register_write(rt2x00dev,
3739 SHARED_KEY_MODE_ENTRY(i), 0);
3740
3741 for (i = 0; i < 256; i++) {
3742 rt2800_config_wcid(rt2x00dev, NULL, i);
3743 rt2800_delete_wcid_attr(rt2x00dev, i);
3744 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3745 }
3746
3747 /*
3748 * Clear all beacons
3749 */
3750 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3751 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3752 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3753 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3754 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3755 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3756 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3757 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3758
3759 if (rt2x00_is_usb(rt2x00dev)) {
3760 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3761 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3762 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3763 } else if (rt2x00_is_pcie(rt2x00dev)) {
3764 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3765 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3766 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3767 }
3768
3769 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3770 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3771 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3772 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3773 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3774 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3775 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3776 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3777 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3778 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3779
3780 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3781 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3782 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3783 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3784 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3785 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3786 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3787 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3788 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3789 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3790
3791 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3792 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3793 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3794 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3795 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3796 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3797 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3798 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3799 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3800 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3801
3802 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3803 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3804 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3805 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3806 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3807 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3808
3809 /*
3810 * Do not force the BA window size, we use the TXWI to set it
3811 */
3812 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3813 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3814 rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3815 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3816
3817 /*
3818 * We must clear the error counters.
3819 * These registers are cleared on read,
3820 * so we may pass a useless variable to store the value.
3821 */
3822 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3823 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3824 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3825 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3826 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3827 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3828
3829 /*
3830 * Setup leadtime for pre tbtt interrupt to 6ms
3831 */
3832 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3833 rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3834 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3835
3836 /*
3837 * Set up channel statistics timer
3838 */
3839 rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3840 rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3841 rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3842 rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3843 rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3844 rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3845 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3846
3847 return 0;
3848 }
3849
3850 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3851 {
3852 unsigned int i;
3853 u32 reg;
3854
3855 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3856 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3857 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3858 return 0;
3859
3860 udelay(REGISTER_BUSY_DELAY);
3861 }
3862
3863 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3864 return -EACCES;
3865 }
3866
3867 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3868 {
3869 unsigned int i;
3870 u8 value;
3871
3872 /*
3873 * BBP was enabled after firmware was loaded,
3874 * but we need to reactivate it now.
3875 */
3876 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3877 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3878 msleep(1);
3879
3880 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3881 rt2800_bbp_read(rt2x00dev, 0, &value);
3882 if ((value != 0xff) && (value != 0x00))
3883 return 0;
3884 udelay(REGISTER_BUSY_DELAY);
3885 }
3886
3887 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3888 return -EACCES;
3889 }
3890
3891 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3892 {
3893 u8 value;
3894
3895 rt2800_bbp_read(rt2x00dev, 4, &value);
3896 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3897 rt2800_bbp_write(rt2x00dev, 4, value);
3898 }
3899
3900 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3901 {
3902 rt2800_bbp_write(rt2x00dev, 142, 1);
3903 rt2800_bbp_write(rt2x00dev, 143, 57);
3904 }
3905
3906 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3907 {
3908 const u8 glrt_table[] = {
3909 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3910 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3911 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3912 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3913 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3914 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3916 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3917 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3918 };
3919 int i;
3920
3921 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3922 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3923 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3924 }
3925 };
3926
3927 static void rt2800_init_bbb_early(struct rt2x00_dev *rt2x00dev)
3928 {
3929 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3930 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3931 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3932 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3933 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3934 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3935 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3936 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3937 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3938 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3939 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3940 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3941 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3942 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3943 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3944 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3945 }
3946
3947 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3948 {
3949 int ant, div_mode;
3950 u16 eeprom;
3951 u8 value;
3952
3953 rt2800_init_bbb_early(rt2x00dev);
3954
3955 rt2800_bbp_read(rt2x00dev, 105, &value);
3956 rt2x00_set_field8(&value, BBP105_MLD,
3957 rt2x00dev->default_ant.rx_chain_num == 2);
3958 rt2800_bbp_write(rt2x00dev, 105, value);
3959
3960 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3961
3962 rt2800_bbp_write(rt2x00dev, 20, 0x06);
3963 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3964 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3965 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3966 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3967 rt2800_bbp_write(rt2x00dev, 70, 0x05);
3968 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3969 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3970 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3971 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3972 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3973 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3974 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3975 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3976 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3977 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3978 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3979 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3980 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3981 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3982 /* FIXME BBP105 owerwrite */
3983 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3984 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3985 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3986 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3987 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3988 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3989
3990 /* Initialize GLRT (Generalized Likehood Radio Test) */
3991 rt2800_init_bbp_5592_glrt(rt2x00dev);
3992
3993 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3994
3995 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3996 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
3997 ant = (div_mode == 3) ? 1 : 0;
3998 rt2800_bbp_read(rt2x00dev, 152, &value);
3999 if (ant == 0) {
4000 /* Main antenna */
4001 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4002 } else {
4003 /* Auxiliary antenna */
4004 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4005 }
4006 rt2800_bbp_write(rt2x00dev, 152, value);
4007
4008 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4009 rt2800_bbp_read(rt2x00dev, 254, &value);
4010 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4011 rt2800_bbp_write(rt2x00dev, 254, value);
4012 }
4013
4014 rt2800_init_freq_calibration(rt2x00dev);
4015
4016 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4017 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4018 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4019 }
4020
4021 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
4022 {
4023 unsigned int i;
4024 u16 eeprom;
4025 u8 reg_id;
4026 u8 value;
4027
4028 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
4029 rt2800_wait_bbp_ready(rt2x00dev)))
4030 return -EACCES;
4031
4032 if (rt2x00_rt(rt2x00dev, RT5592)) {
4033 rt2800_init_bbp_5592(rt2x00dev);
4034 return 0;
4035 }
4036
4037 if (rt2x00_rt(rt2x00dev, RT3352)) {
4038 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4039 rt2800_bbp_write(rt2x00dev, 4, 0x50);
4040 }
4041
4042 if (rt2x00_rt(rt2x00dev, RT3290) ||
4043 rt2x00_rt(rt2x00dev, RT5390) ||
4044 rt2x00_rt(rt2x00dev, RT5392))
4045 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4046
4047 if (rt2800_is_305x_soc(rt2x00dev) ||
4048 rt2x00_rt(rt2x00dev, RT3290) ||
4049 rt2x00_rt(rt2x00dev, RT3352) ||
4050 rt2x00_rt(rt2x00dev, RT3572) ||
4051 rt2x00_rt(rt2x00dev, RT5390) ||
4052 rt2x00_rt(rt2x00dev, RT5392))
4053 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4054
4055 if (rt2x00_rt(rt2x00dev, RT3352))
4056 rt2800_bbp_write(rt2x00dev, 47, 0x48);
4057
4058 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4059 rt2800_bbp_write(rt2x00dev, 66, 0x38);
4060
4061 if (rt2x00_rt(rt2x00dev, RT3290) ||
4062 rt2x00_rt(rt2x00dev, RT3352) ||
4063 rt2x00_rt(rt2x00dev, RT5390) ||
4064 rt2x00_rt(rt2x00dev, RT5392))
4065 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4066
4067 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4068 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4069 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4070 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
4071 rt2x00_rt(rt2x00dev, RT3352) ||
4072 rt2x00_rt(rt2x00dev, RT5390) ||
4073 rt2x00_rt(rt2x00dev, RT5392)) {
4074 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4075 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4076 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4077 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4078
4079 if (rt2x00_rt(rt2x00dev, RT3290))
4080 rt2800_bbp_write(rt2x00dev, 77, 0x58);
4081 else
4082 rt2800_bbp_write(rt2x00dev, 77, 0x59);
4083 } else {
4084 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4085 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4086 }
4087
4088 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4089
4090 if (rt2x00_rt(rt2x00dev, RT3070) ||
4091 rt2x00_rt(rt2x00dev, RT3071) ||
4092 rt2x00_rt(rt2x00dev, RT3090) ||
4093 rt2x00_rt(rt2x00dev, RT3390) ||
4094 rt2x00_rt(rt2x00dev, RT3572) ||
4095 rt2x00_rt(rt2x00dev, RT5390) ||
4096 rt2x00_rt(rt2x00dev, RT5392)) {
4097 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4098 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4099 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4100 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4101 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4102 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4103 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
4104 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4105 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4106 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4107 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4108 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4109 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4110 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4111 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4112 } else {
4113 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4114 }
4115
4116 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4117 if (rt2x00_rt(rt2x00dev, RT3290) ||
4118 rt2x00_rt(rt2x00dev, RT5390) ||
4119 rt2x00_rt(rt2x00dev, RT5392))
4120 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4121 else
4122 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4123
4124 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4125 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4126 else if (rt2x00_rt(rt2x00dev, RT3290) ||
4127 rt2x00_rt(rt2x00dev, RT5390) ||
4128 rt2x00_rt(rt2x00dev, RT5392))
4129 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4130 else
4131 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4132
4133 if (rt2x00_rt(rt2x00dev, RT3290) ||
4134 rt2x00_rt(rt2x00dev, RT3352) ||
4135 rt2x00_rt(rt2x00dev, RT5390) ||
4136 rt2x00_rt(rt2x00dev, RT5392))
4137 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4138 else
4139 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4140
4141 if (rt2x00_rt(rt2x00dev, RT3352) ||
4142 rt2x00_rt(rt2x00dev, RT5392))
4143 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4144
4145 rt2800_bbp_write(rt2x00dev, 91, 0x04);
4146
4147 if (rt2x00_rt(rt2x00dev, RT3290) ||
4148 rt2x00_rt(rt2x00dev, RT3352) ||
4149 rt2x00_rt(rt2x00dev, RT5390) ||
4150 rt2x00_rt(rt2x00dev, RT5392))
4151 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4152 else
4153 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4154
4155 if (rt2x00_rt(rt2x00dev, RT5392)) {
4156 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4157 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4158 }
4159
4160 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4161 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4162 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4163 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4164 rt2x00_rt(rt2x00dev, RT3290) ||
4165 rt2x00_rt(rt2x00dev, RT3352) ||
4166 rt2x00_rt(rt2x00dev, RT3572) ||
4167 rt2x00_rt(rt2x00dev, RT5390) ||
4168 rt2x00_rt(rt2x00dev, RT5392) ||
4169 rt2800_is_305x_soc(rt2x00dev))
4170 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4171 else
4172 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4173
4174 if (rt2x00_rt(rt2x00dev, RT3290) ||
4175 rt2x00_rt(rt2x00dev, RT3352) ||
4176 rt2x00_rt(rt2x00dev, RT5390) ||
4177 rt2x00_rt(rt2x00dev, RT5392))
4178 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4179
4180 if (rt2800_is_305x_soc(rt2x00dev))
4181 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4182 else if (rt2x00_rt(rt2x00dev, RT3290))
4183 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4184 else if (rt2x00_rt(rt2x00dev, RT3352))
4185 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4186 else if (rt2x00_rt(rt2x00dev, RT5390) ||
4187 rt2x00_rt(rt2x00dev, RT5392))
4188 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4189 else
4190 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4191
4192 if (rt2x00_rt(rt2x00dev, RT3290) ||
4193 rt2x00_rt(rt2x00dev, RT5390))
4194 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4195 else if (rt2x00_rt(rt2x00dev, RT3352))
4196 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4197 else if (rt2x00_rt(rt2x00dev, RT5392))
4198 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4199 else
4200 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4201
4202 if (rt2x00_rt(rt2x00dev, RT3352))
4203 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4204
4205 if (rt2x00_rt(rt2x00dev, RT3290) ||
4206 rt2x00_rt(rt2x00dev, RT5390) ||
4207 rt2x00_rt(rt2x00dev, RT5392))
4208 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4209
4210 if (rt2x00_rt(rt2x00dev, RT5392)) {
4211 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4212 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4213 }
4214
4215 if (rt2x00_rt(rt2x00dev, RT3352))
4216 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4217
4218 if (rt2x00_rt(rt2x00dev, RT3071) ||
4219 rt2x00_rt(rt2x00dev, RT3090) ||
4220 rt2x00_rt(rt2x00dev, RT3390) ||
4221 rt2x00_rt(rt2x00dev, RT3572) ||
4222 rt2x00_rt(rt2x00dev, RT5390) ||
4223 rt2x00_rt(rt2x00dev, RT5392)) {
4224 rt2800_bbp_read(rt2x00dev, 138, &value);
4225
4226 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4227 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4228 value |= 0x20;
4229 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4230 value &= ~0x02;
4231
4232 rt2800_bbp_write(rt2x00dev, 138, value);
4233 }
4234
4235 if (rt2x00_rt(rt2x00dev, RT3290)) {
4236 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4237 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4238 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4239 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4240 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4241 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4242 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4243 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4244 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4245 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4246
4247 rt2800_bbp_read(rt2x00dev, 47, &value);
4248 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4249 rt2800_bbp_write(rt2x00dev, 47, value);
4250
4251 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4252 rt2800_bbp_read(rt2x00dev, 3, &value);
4253 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4254 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4255 rt2800_bbp_write(rt2x00dev, 3, value);
4256 }
4257
4258 if (rt2x00_rt(rt2x00dev, RT3352)) {
4259 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4260 /* Set ITxBF timeout to 0x9c40=1000msec */
4261 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4262 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4263 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4264 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4265 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4266 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4267 /* Reprogram the inband interface to put right values in RXWI */
4268 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4269 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4270 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4271 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4272 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4273 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4274 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4275 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4276
4277 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4278 }
4279
4280 if (rt2x00_rt(rt2x00dev, RT5390) ||
4281 rt2x00_rt(rt2x00dev, RT5392)) {
4282 int ant, div_mode;
4283
4284 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4285 div_mode = rt2x00_get_field16(eeprom,
4286 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4287 ant = (div_mode == 3) ? 1 : 0;
4288
4289 /* check if this is a Bluetooth combo card */
4290 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4291 u32 reg;
4292
4293 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4294 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4295 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4296 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4297 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4298 if (ant == 0)
4299 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4300 else if (ant == 1)
4301 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4302 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4303 }
4304
4305 /* This chip has hardware antenna diversity*/
4306 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4307 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4308 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4309 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4310 }
4311
4312 rt2800_bbp_read(rt2x00dev, 152, &value);
4313 if (ant == 0)
4314 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4315 else
4316 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4317 rt2800_bbp_write(rt2x00dev, 152, value);
4318
4319 rt2800_init_freq_calibration(rt2x00dev);
4320 }
4321
4322 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4323 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4324
4325 if (eeprom != 0xffff && eeprom != 0x0000) {
4326 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4327 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4328 rt2800_bbp_write(rt2x00dev, reg_id, value);
4329 }
4330 }
4331
4332 return 0;
4333 }
4334
4335 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
4336 bool bw40, u8 rfcsr24, u8 filter_target)
4337 {
4338 unsigned int i;
4339 u8 bbp;
4340 u8 rfcsr;
4341 u8 passband;
4342 u8 stopband;
4343 u8 overtuned = 0;
4344
4345 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4346
4347 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4348 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4349 rt2800_bbp_write(rt2x00dev, 4, bbp);
4350
4351 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4352 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4353 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4354
4355 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4356 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4357 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4358
4359 /*
4360 * Set power & frequency of passband test tone
4361 */
4362 rt2800_bbp_write(rt2x00dev, 24, 0);
4363
4364 for (i = 0; i < 100; i++) {
4365 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4366 msleep(1);
4367
4368 rt2800_bbp_read(rt2x00dev, 55, &passband);
4369 if (passband)
4370 break;
4371 }
4372
4373 /*
4374 * Set power & frequency of stopband test tone
4375 */
4376 rt2800_bbp_write(rt2x00dev, 24, 0x06);
4377
4378 for (i = 0; i < 100; i++) {
4379 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4380 msleep(1);
4381
4382 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4383
4384 if ((passband - stopband) <= filter_target) {
4385 rfcsr24++;
4386 overtuned += ((passband - stopband) == filter_target);
4387 } else
4388 break;
4389
4390 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4391 }
4392
4393 rfcsr24 -= !!overtuned;
4394
4395 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4396 return rfcsr24;
4397 }
4398
4399 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4400 {
4401 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4402 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4403 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4404 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4405 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4406 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4407 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4408 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4409 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4410 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4411 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4412 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4413 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4414 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4415 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4416 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4417 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4418 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4419 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4420 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4421 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4422 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4423 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4424 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4425 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4426 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4427 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4428 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4429 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4430 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4431 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4432 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4433 }
4434
4435 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4436 {
4437 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4438 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4439 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4440 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4441 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4442 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4443 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4444 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4445 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4446 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4447 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4448 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4449 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4450 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4451 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4452 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4453 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4454 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4455 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4456 }
4457
4458 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4459 {
4460 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4461 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4462 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4463 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4464 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4465 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4466 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4467 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4468 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4469 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4470 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4471 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4472 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4473 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4474 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4475 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4476 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4477 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4478 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4479 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4480 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4481 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4482 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4483 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4484 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4485 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4486 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4487 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4488 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4489 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4490 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4491 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4492 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4493 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4494 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4495 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4496 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4497 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4498 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4499 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4500 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4501 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4502 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4503 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4504 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4505 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4506 }
4507
4508 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4509 {
4510 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4511 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4512 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4513 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4514 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4515 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4516 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4517 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4518 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4519 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4520 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4521 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4522 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4523 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4524 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4525 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4526 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4527 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4528 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4529 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4530 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4531 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4532 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4533 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4534 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4535 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4536 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4537 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4538 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4539 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4540 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4541 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4542 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4543 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4544 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4545 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4546 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4547 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4548 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4549 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4550 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4551 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4552 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4553 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4554 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4555 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4556 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4557 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4558 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4559 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4560 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4561 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4562 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4563 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4564 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4565 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4566 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4567 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4568 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4569 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4570 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4571 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4572 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4573 }
4574
4575 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4576 {
4577 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4578 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4579 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4580 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4581 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4582 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4583 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4584 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4585 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4586 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4587 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4588 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4589 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4590 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4591 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4592 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4593 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4594 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4595 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4596 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4597 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4598 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4599 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4600 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4601 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4602 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4603 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4604 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4605 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4606 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4607 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4608 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4609 }
4610
4611 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4612 {
4613 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4614 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4615 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4616 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4617 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4618 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4619 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4620 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4621 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4622 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4623 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4624 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4625 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4626 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4627 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4628 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4629 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4630 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4631 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4632 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4633 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4634 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4635 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4636 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4637 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4638 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4639 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4640 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4641 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4642 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4643 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4644 }
4645
4646 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4647 {
4648 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4649 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4650 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4651 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4652 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4653 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4654 else
4655 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4656 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4657 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4658 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4659 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4660 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4661 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4662 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4663 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4664 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4665 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4666
4667 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4668 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4669 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4670 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4671 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4672 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4673 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4674 else
4675 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4676 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4677 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4678 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4679 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4680
4681 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4682 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4683 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4684 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4685 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4686 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4687 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4688 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4689 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4690 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4691
4692 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4693 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4694 else
4695 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4696 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4697 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4698 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4699 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4700 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4701 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4702 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4703 else
4704 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4705 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4706 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4707 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4708
4709 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4710 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4711 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4712 else
4713 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4714 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4715 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4716 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4717 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4718 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4719 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4720
4721 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4722 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4723 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4724 else
4725 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4726 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4727 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4728 }
4729
4730 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4731 {
4732 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4733 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4734 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4735 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4736 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4737 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4738 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4739 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4740 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4741 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4742 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4743 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4744 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4745 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4746 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4747 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4748 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4749 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4750 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4751 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4752 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4753 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4754 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4755 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4756 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4757 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4758 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4759 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4760 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4761 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4762 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4763 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4764 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4765 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4766 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4767 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4768 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4769 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4770 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4771 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4772 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4773 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4774 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4775 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4776 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4777 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4778 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4779 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4780 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4781 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4782 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4783 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4784 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4785 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4786 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4787 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4788 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4789 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4790 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4791 }
4792
4793 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4794 {
4795 u8 reg;
4796 u16 eeprom;
4797
4798 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4799 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4800 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4801 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4802 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4803 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4804 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4805 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4806 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4807 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4808 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
4809 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
4810 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
4811 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4812 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4813 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4814 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4815 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4816 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4817 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
4818 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
4819 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4820
4821 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4822 msleep(1);
4823
4824 rt2800_adjust_freq_offset(rt2x00dev);
4825
4826 rt2800_bbp_read(rt2x00dev, 138, &reg);
4827
4828 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4829 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4830 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4831 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4832 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4833 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4834
4835 rt2800_bbp_write(rt2x00dev, 138, reg);
4836
4837 /* Enable DC filter */
4838 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4839 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4840
4841 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4842 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4843 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4844
4845 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4846 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4847 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4848
4849 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4850
4851 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4852 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4853 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4854 }
4855
4856 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4857 {
4858 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4859 u8 rfcsr;
4860 u8 bbp;
4861 u32 reg;
4862 u16 eeprom;
4863
4864 if (!rt2x00_rt(rt2x00dev, RT3070) &&
4865 !rt2x00_rt(rt2x00dev, RT3071) &&
4866 !rt2x00_rt(rt2x00dev, RT3090) &&
4867 !rt2x00_rt(rt2x00dev, RT3290) &&
4868 !rt2x00_rt(rt2x00dev, RT3352) &&
4869 !rt2x00_rt(rt2x00dev, RT3390) &&
4870 !rt2x00_rt(rt2x00dev, RT3572) &&
4871 !rt2x00_rt(rt2x00dev, RT5390) &&
4872 !rt2x00_rt(rt2x00dev, RT5392) &&
4873 !rt2x00_rt(rt2x00dev, RT5392) &&
4874 !rt2x00_rt(rt2x00dev, RT5592) &&
4875 !rt2800_is_305x_soc(rt2x00dev))
4876 return 0;
4877
4878 /*
4879 * Init RF calibration.
4880 */
4881
4882 if (rt2x00_rt(rt2x00dev, RT3290) ||
4883 rt2x00_rt(rt2x00dev, RT5390) ||
4884 rt2x00_rt(rt2x00dev, RT5392)) {
4885 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
4886 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
4887 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4888 msleep(1);
4889 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
4890 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
4891 } else {
4892 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4893 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4894 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4895 msleep(1);
4896 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4897 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4898 }
4899
4900 if (rt2800_is_305x_soc(rt2x00dev)) {
4901 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4902 return 0;
4903 }
4904
4905 switch (rt2x00dev->chip.rt) {
4906 case RT3070:
4907 case RT3071:
4908 case RT3090:
4909 rt2800_init_rfcsr_30xx(rt2x00dev);
4910 break;
4911 case RT3290:
4912 rt2800_init_rfcsr_3290(rt2x00dev);
4913 break;
4914 case RT3352:
4915 rt2800_init_rfcsr_3352(rt2x00dev);
4916 break;
4917 case RT3390:
4918 rt2800_init_rfcsr_3390(rt2x00dev);
4919 break;
4920 case RT3572:
4921 rt2800_init_rfcsr_3572(rt2x00dev);
4922 break;
4923 case RT5390:
4924 rt2800_init_rfcsr_5390(rt2x00dev);
4925 break;
4926 case RT5392:
4927 rt2800_init_rfcsr_5392(rt2x00dev);
4928 break;
4929 case RT5592:
4930 rt2800_init_rfcsr_5592(rt2x00dev);
4931 return 0;
4932 }
4933
4934 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4935 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4936 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4937 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4938 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4939 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4940 rt2x00_rt(rt2x00dev, RT3090)) {
4941 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4942
4943 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4944 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4945 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4946
4947 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4948 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4949 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4950 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4951 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4952 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4953 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4954 else
4955 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4956 }
4957 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4958
4959 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4960 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4961 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4962 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4963 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4964 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4965 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4966 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4967 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4968 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4969 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4970
4971 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4972 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4973 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4974 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4975 msleep(1);
4976 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4977 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4978 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4979 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4980 }
4981
4982 /*
4983 * Set RX Filter calibration for 20MHz and 40MHz
4984 */
4985 if (rt2x00_rt(rt2x00dev, RT3070)) {
4986 drv_data->calibration_bw20 =
4987 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4988 drv_data->calibration_bw40 =
4989 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4990 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4991 rt2x00_rt(rt2x00dev, RT3090) ||
4992 rt2x00_rt(rt2x00dev, RT3352) ||
4993 rt2x00_rt(rt2x00dev, RT3390) ||
4994 rt2x00_rt(rt2x00dev, RT3572)) {
4995 drv_data->calibration_bw20 =
4996 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4997 drv_data->calibration_bw40 =
4998 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4999 }
5000
5001 /*
5002 * Save BBP 25 & 26 values for later use in channel switching
5003 */
5004 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5005 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5006
5007 if (!rt2x00_rt(rt2x00dev, RT5390) &&
5008 !rt2x00_rt(rt2x00dev, RT5392)) {
5009 /*
5010 * Set back to initial state
5011 */
5012 rt2800_bbp_write(rt2x00dev, 24, 0);
5013
5014 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5015 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5016 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5017
5018 /*
5019 * Set BBP back to BW20
5020 */
5021 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5022 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5023 rt2800_bbp_write(rt2x00dev, 4, bbp);
5024 }
5025
5026 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
5027 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5028 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5029 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E) ||
5030 rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
5031 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5032
5033 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5034 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5035 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5036
5037 if (!rt2x00_rt(rt2x00dev, RT5390) &&
5038 !rt2x00_rt(rt2x00dev, RT5392)) {
5039 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5040 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5041 if (rt2x00_rt(rt2x00dev, RT3070) ||
5042 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5043 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5044 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5045 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
5046 &rt2x00dev->cap_flags))
5047 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5048 }
5049 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5050 drv_data->txmixer_gain_24g);
5051 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5052 }
5053
5054 if (rt2x00_rt(rt2x00dev, RT3090) ||
5055 rt2x00_rt(rt2x00dev, RT5592)) {
5056 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5057
5058 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5059 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5060 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5061 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5062 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5063 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5064
5065 rt2800_bbp_write(rt2x00dev, 138, bbp);
5066 }
5067
5068 if (rt2x00_rt(rt2x00dev, RT3071) ||
5069 rt2x00_rt(rt2x00dev, RT3090) ||
5070 rt2x00_rt(rt2x00dev, RT3390)) {
5071 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5072 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5073 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5074 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5075 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5076 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5077 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5078
5079 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5080 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5081 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5082
5083 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5084 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5085 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5086
5087 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5088 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5089 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5090 }
5091
5092 if (rt2x00_rt(rt2x00dev, RT3070)) {
5093 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5094 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5095 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5096 else
5097 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5098 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5099 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5100 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5101 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5102 }
5103
5104 if (rt2x00_rt(rt2x00dev, RT3290)) {
5105 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
5106 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
5107 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
5108 }
5109
5110 if (rt2x00_rt(rt2x00dev, RT5390) ||
5111 rt2x00_rt(rt2x00dev, RT5392) ||
5112 rt2x00_rt(rt2x00dev, RT5592)) {
5113 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5114 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5115 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5116
5117 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5118 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5119 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5120
5121 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5122 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5123 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5124 }
5125
5126 return 0;
5127 }
5128
5129 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5130 {
5131 u32 reg;
5132 u16 word;
5133
5134 /*
5135 * Initialize all registers.
5136 */
5137 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
5138 rt2800_init_registers(rt2x00dev)))
5139 return -EIO;
5140
5141 /*
5142 * Send signal to firmware during boot time.
5143 */
5144 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5145 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5146 if (rt2x00_is_usb(rt2x00dev)) {
5147 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5148 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5149 }
5150 msleep(1);
5151
5152 if (unlikely(rt2800_init_bbp(rt2x00dev) ||
5153 rt2800_init_rfcsr(rt2x00dev)))
5154 return -EIO;
5155
5156 if (rt2x00_is_usb(rt2x00dev) &&
5157 (rt2x00_rt(rt2x00dev, RT3070) ||
5158 rt2x00_rt(rt2x00dev, RT3071) ||
5159 rt2x00_rt(rt2x00dev, RT3572))) {
5160 udelay(200);
5161 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5162 udelay(10);
5163 }
5164
5165 /*
5166 * Enable RX.
5167 */
5168 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5169 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5170 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5171 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5172
5173 udelay(50);
5174
5175 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5176 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5177 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5178 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5179 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5180 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5181
5182 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5183 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5184 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5185 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5186
5187 /*
5188 * Initialize LED control
5189 */
5190 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5191 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5192 word & 0xff, (word >> 8) & 0xff);
5193
5194 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5195 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5196 word & 0xff, (word >> 8) & 0xff);
5197
5198 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5199 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5200 word & 0xff, (word >> 8) & 0xff);
5201
5202 return 0;
5203 }
5204 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5205
5206 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5207 {
5208 u32 reg;
5209
5210 rt2800_disable_wpdma(rt2x00dev);
5211
5212 /* Wait for DMA, ignore error */
5213 rt2800_wait_wpdma_ready(rt2x00dev);
5214
5215 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5216 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5217 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5218 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5219 }
5220 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5221
5222 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5223 {
5224 u32 reg;
5225 u16 efuse_ctrl_reg;
5226
5227 if (rt2x00_rt(rt2x00dev, RT3290))
5228 efuse_ctrl_reg = EFUSE_CTRL_3290;
5229 else
5230 efuse_ctrl_reg = EFUSE_CTRL;
5231
5232 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5233 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5234 }
5235 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5236
5237 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5238 {
5239 u32 reg;
5240 u16 efuse_ctrl_reg;
5241 u16 efuse_data0_reg;
5242 u16 efuse_data1_reg;
5243 u16 efuse_data2_reg;
5244 u16 efuse_data3_reg;
5245
5246 if (rt2x00_rt(rt2x00dev, RT3290)) {
5247 efuse_ctrl_reg = EFUSE_CTRL_3290;
5248 efuse_data0_reg = EFUSE_DATA0_3290;
5249 efuse_data1_reg = EFUSE_DATA1_3290;
5250 efuse_data2_reg = EFUSE_DATA2_3290;
5251 efuse_data3_reg = EFUSE_DATA3_3290;
5252 } else {
5253 efuse_ctrl_reg = EFUSE_CTRL;
5254 efuse_data0_reg = EFUSE_DATA0;
5255 efuse_data1_reg = EFUSE_DATA1;
5256 efuse_data2_reg = EFUSE_DATA2;
5257 efuse_data3_reg = EFUSE_DATA3;
5258 }
5259 mutex_lock(&rt2x00dev->csr_mutex);
5260
5261 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5262 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5263 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5264 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5265 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5266
5267 /* Wait until the EEPROM has been loaded */
5268 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5269 /* Apparently the data is read from end to start */
5270 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5271 /* The returned value is in CPU order, but eeprom is le */
5272 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5273 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5274 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5275 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5276 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5277 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5278 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5279
5280 mutex_unlock(&rt2x00dev->csr_mutex);
5281 }
5282
5283 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5284 {
5285 unsigned int i;
5286
5287 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5288 rt2800_efuse_read(rt2x00dev, i);
5289
5290 return 0;
5291 }
5292 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5293
5294 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5295 {
5296 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5297 u16 word;
5298 u8 *mac;
5299 u8 default_lna_gain;
5300 int retval;
5301
5302 /*
5303 * Read the EEPROM.
5304 */
5305 retval = rt2800_read_eeprom(rt2x00dev);
5306 if (retval)
5307 return retval;
5308
5309 /*
5310 * Start validation of the data that has been read.
5311 */
5312 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5313 if (!is_valid_ether_addr(mac)) {
5314 eth_random_addr(mac);
5315 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
5316 }
5317
5318 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5319 if (word == 0xffff) {
5320 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5321 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5322 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5323 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5324 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
5325 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5326 rt2x00_rt(rt2x00dev, RT2872)) {
5327 /*
5328 * There is a max of 2 RX streams for RT28x0 series
5329 */
5330 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5331 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5332 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5333 }
5334
5335 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5336 if (word == 0xffff) {
5337 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5338 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5339 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5340 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5341 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5342 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5343 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5344 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5345 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5346 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5347 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5348 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5349 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5350 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5351 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5352 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5353 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
5354 }
5355
5356 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5357 if ((word & 0x00ff) == 0x00ff) {
5358 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5359 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5360 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
5361 }
5362 if ((word & 0xff00) == 0xff00) {
5363 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5364 LED_MODE_TXRX_ACTIVITY);
5365 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5366 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5367 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5368 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5369 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5370 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
5371 }
5372
5373 /*
5374 * During the LNA validation we are going to use
5375 * lna0 as correct value. Note that EEPROM_LNA
5376 * is never validated.
5377 */
5378 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5379 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5380
5381 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5382 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5383 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5384 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5385 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5386 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5387
5388 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5389 if ((word & 0x00ff) != 0x00ff) {
5390 drv_data->txmixer_gain_24g =
5391 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5392 } else {
5393 drv_data->txmixer_gain_24g = 0;
5394 }
5395
5396 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5397 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5398 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5399 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5400 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5401 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5402 default_lna_gain);
5403 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5404
5405 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5406 if ((word & 0x00ff) != 0x00ff) {
5407 drv_data->txmixer_gain_5g =
5408 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5409 } else {
5410 drv_data->txmixer_gain_5g = 0;
5411 }
5412
5413 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5414 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5415 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5416 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5417 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5418 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5419
5420 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5421 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5422 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5423 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5424 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5425 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5426 default_lna_gain);
5427 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5428
5429 return 0;
5430 }
5431
5432 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5433 {
5434 u32 reg;
5435 u16 value;
5436 u16 eeprom;
5437
5438 /*
5439 * Read EEPROM word for configuration.
5440 */
5441 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5442
5443 /*
5444 * Identify RF chipset by EEPROM value
5445 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5446 * RT53xx: defined in "EEPROM_CHIP_ID" field
5447 */
5448 if (rt2x00_rt(rt2x00dev, RT3290))
5449 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
5450 else
5451 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
5452
5453 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
5454 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
5455 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
5456 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
5457 else
5458 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5459
5460 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
5461 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
5462
5463 switch (rt2x00dev->chip.rt) {
5464 case RT2860:
5465 case RT2872:
5466 case RT2883:
5467 case RT3070:
5468 case RT3071:
5469 case RT3090:
5470 case RT3290:
5471 case RT3352:
5472 case RT3390:
5473 case RT3572:
5474 case RT5390:
5475 case RT5392:
5476 case RT5592:
5477 break;
5478 default:
5479 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
5480 return -ENODEV;
5481 }
5482
5483 switch (rt2x00dev->chip.rf) {
5484 case RF2820:
5485 case RF2850:
5486 case RF2720:
5487 case RF2750:
5488 case RF3020:
5489 case RF2020:
5490 case RF3021:
5491 case RF3022:
5492 case RF3052:
5493 case RF3290:
5494 case RF3320:
5495 case RF3322:
5496 case RF5360:
5497 case RF5370:
5498 case RF5372:
5499 case RF5390:
5500 case RF5392:
5501 case RF5592:
5502 break;
5503 default:
5504 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
5505 rt2x00dev->chip.rf);
5506 return -ENODEV;
5507 }
5508
5509 /*
5510 * Identify default antenna configuration.
5511 */
5512 rt2x00dev->default_ant.tx_chain_num =
5513 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5514 rt2x00dev->default_ant.rx_chain_num =
5515 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5516
5517 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5518
5519 if (rt2x00_rt(rt2x00dev, RT3070) ||
5520 rt2x00_rt(rt2x00dev, RT3090) ||
5521 rt2x00_rt(rt2x00dev, RT3352) ||
5522 rt2x00_rt(rt2x00dev, RT3390)) {
5523 value = rt2x00_get_field16(eeprom,
5524 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5525 switch (value) {
5526 case 0:
5527 case 1:
5528 case 2:
5529 rt2x00dev->default_ant.tx = ANTENNA_A;
5530 rt2x00dev->default_ant.rx = ANTENNA_A;
5531 break;
5532 case 3:
5533 rt2x00dev->default_ant.tx = ANTENNA_A;
5534 rt2x00dev->default_ant.rx = ANTENNA_B;
5535 break;
5536 }
5537 } else {
5538 rt2x00dev->default_ant.tx = ANTENNA_A;
5539 rt2x00dev->default_ant.rx = ANTENNA_A;
5540 }
5541
5542 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5543 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5544 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5545 }
5546
5547 /*
5548 * Determine external LNA informations.
5549 */
5550 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5551 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5552 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5553 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5554
5555 /*
5556 * Detect if this device has an hardware controlled radio.
5557 */
5558 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5559 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5560
5561 /*
5562 * Detect if this device has Bluetooth co-existence.
5563 */
5564 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5565 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5566
5567 /*
5568 * Read frequency offset and RF programming sequence.
5569 */
5570 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5571 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5572
5573 /*
5574 * Store led settings, for correct led behaviour.
5575 */
5576 #ifdef CONFIG_RT2X00_LIB_LEDS
5577 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5578 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5579 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5580
5581 rt2x00dev->led_mcu_reg = eeprom;
5582 #endif /* CONFIG_RT2X00_LIB_LEDS */
5583
5584 /*
5585 * Check if support EIRP tx power limit feature.
5586 */
5587 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5588
5589 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5590 EIRP_MAX_TX_POWER_LIMIT)
5591 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5592
5593 return 0;
5594 }
5595
5596 /*
5597 * RF value list for rt28xx
5598 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5599 */
5600 static const struct rf_channel rf_vals[] = {
5601 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5602 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5603 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5604 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5605 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5606 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5607 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5608 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5609 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5610 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5611 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5612 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5613 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5614 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5615
5616 /* 802.11 UNI / HyperLan 2 */
5617 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5618 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5619 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5620 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5621 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5622 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5623 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5624 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5625 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5626 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5627 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5628 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5629
5630 /* 802.11 HyperLan 2 */
5631 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5632 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5633 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5634 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5635 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5636 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5637 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5638 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5639 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5640 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5641 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5642 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5643 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5644 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5645 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5646 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5647
5648 /* 802.11 UNII */
5649 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5650 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5651 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5652 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5653 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5654 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5655 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5656 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5657 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5658 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5659 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5660
5661 /* 802.11 Japan */
5662 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5663 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5664 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5665 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5666 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5667 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5668 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5669 };
5670
5671 /*
5672 * RF value list for rt3xxx
5673 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5674 */
5675 static const struct rf_channel rf_vals_3x[] = {
5676 {1, 241, 2, 2 },
5677 {2, 241, 2, 7 },
5678 {3, 242, 2, 2 },
5679 {4, 242, 2, 7 },
5680 {5, 243, 2, 2 },
5681 {6, 243, 2, 7 },
5682 {7, 244, 2, 2 },
5683 {8, 244, 2, 7 },
5684 {9, 245, 2, 2 },
5685 {10, 245, 2, 7 },
5686 {11, 246, 2, 2 },
5687 {12, 246, 2, 7 },
5688 {13, 247, 2, 2 },
5689 {14, 248, 2, 4 },
5690
5691 /* 802.11 UNI / HyperLan 2 */
5692 {36, 0x56, 0, 4},
5693 {38, 0x56, 0, 6},
5694 {40, 0x56, 0, 8},
5695 {44, 0x57, 0, 0},
5696 {46, 0x57, 0, 2},
5697 {48, 0x57, 0, 4},
5698 {52, 0x57, 0, 8},
5699 {54, 0x57, 0, 10},
5700 {56, 0x58, 0, 0},
5701 {60, 0x58, 0, 4},
5702 {62, 0x58, 0, 6},
5703 {64, 0x58, 0, 8},
5704
5705 /* 802.11 HyperLan 2 */
5706 {100, 0x5b, 0, 8},
5707 {102, 0x5b, 0, 10},
5708 {104, 0x5c, 0, 0},
5709 {108, 0x5c, 0, 4},
5710 {110, 0x5c, 0, 6},
5711 {112, 0x5c, 0, 8},
5712 {116, 0x5d, 0, 0},
5713 {118, 0x5d, 0, 2},
5714 {120, 0x5d, 0, 4},
5715 {124, 0x5d, 0, 8},
5716 {126, 0x5d, 0, 10},
5717 {128, 0x5e, 0, 0},
5718 {132, 0x5e, 0, 4},
5719 {134, 0x5e, 0, 6},
5720 {136, 0x5e, 0, 8},
5721 {140, 0x5f, 0, 0},
5722
5723 /* 802.11 UNII */
5724 {149, 0x5f, 0, 9},
5725 {151, 0x5f, 0, 11},
5726 {153, 0x60, 0, 1},
5727 {157, 0x60, 0, 5},
5728 {159, 0x60, 0, 7},
5729 {161, 0x60, 0, 9},
5730 {165, 0x61, 0, 1},
5731 {167, 0x61, 0, 3},
5732 {169, 0x61, 0, 5},
5733 {171, 0x61, 0, 7},
5734 {173, 0x61, 0, 9},
5735 };
5736
5737 static const struct rf_channel rf_vals_5592_xtal20[] = {
5738 /* Channel, N, K, mod, R */
5739 {1, 482, 4, 10, 3},
5740 {2, 483, 4, 10, 3},
5741 {3, 484, 4, 10, 3},
5742 {4, 485, 4, 10, 3},
5743 {5, 486, 4, 10, 3},
5744 {6, 487, 4, 10, 3},
5745 {7, 488, 4, 10, 3},
5746 {8, 489, 4, 10, 3},
5747 {9, 490, 4, 10, 3},
5748 {10, 491, 4, 10, 3},
5749 {11, 492, 4, 10, 3},
5750 {12, 493, 4, 10, 3},
5751 {13, 494, 4, 10, 3},
5752 {14, 496, 8, 10, 3},
5753 {36, 172, 8, 12, 1},
5754 {38, 173, 0, 12, 1},
5755 {40, 173, 4, 12, 1},
5756 {42, 173, 8, 12, 1},
5757 {44, 174, 0, 12, 1},
5758 {46, 174, 4, 12, 1},
5759 {48, 174, 8, 12, 1},
5760 {50, 175, 0, 12, 1},
5761 {52, 175, 4, 12, 1},
5762 {54, 175, 8, 12, 1},
5763 {56, 176, 0, 12, 1},
5764 {58, 176, 4, 12, 1},
5765 {60, 176, 8, 12, 1},
5766 {62, 177, 0, 12, 1},
5767 {64, 177, 4, 12, 1},
5768 {100, 183, 4, 12, 1},
5769 {102, 183, 8, 12, 1},
5770 {104, 184, 0, 12, 1},
5771 {106, 184, 4, 12, 1},
5772 {108, 184, 8, 12, 1},
5773 {110, 185, 0, 12, 1},
5774 {112, 185, 4, 12, 1},
5775 {114, 185, 8, 12, 1},
5776 {116, 186, 0, 12, 1},
5777 {118, 186, 4, 12, 1},
5778 {120, 186, 8, 12, 1},
5779 {122, 187, 0, 12, 1},
5780 {124, 187, 4, 12, 1},
5781 {126, 187, 8, 12, 1},
5782 {128, 188, 0, 12, 1},
5783 {130, 188, 4, 12, 1},
5784 {132, 188, 8, 12, 1},
5785 {134, 189, 0, 12, 1},
5786 {136, 189, 4, 12, 1},
5787 {138, 189, 8, 12, 1},
5788 {140, 190, 0, 12, 1},
5789 {149, 191, 6, 12, 1},
5790 {151, 191, 10, 12, 1},
5791 {153, 192, 2, 12, 1},
5792 {155, 192, 6, 12, 1},
5793 {157, 192, 10, 12, 1},
5794 {159, 193, 2, 12, 1},
5795 {161, 193, 6, 12, 1},
5796 {165, 194, 2, 12, 1},
5797 {184, 164, 0, 12, 1},
5798 {188, 164, 4, 12, 1},
5799 {192, 165, 8, 12, 1},
5800 {196, 166, 0, 12, 1},
5801 };
5802
5803 static const struct rf_channel rf_vals_5592_xtal40[] = {
5804 /* Channel, N, K, mod, R */
5805 {1, 241, 2, 10, 3},
5806 {2, 241, 7, 10, 3},
5807 {3, 242, 2, 10, 3},
5808 {4, 242, 7, 10, 3},
5809 {5, 243, 2, 10, 3},
5810 {6, 243, 7, 10, 3},
5811 {7, 244, 2, 10, 3},
5812 {8, 244, 7, 10, 3},
5813 {9, 245, 2, 10, 3},
5814 {10, 245, 7, 10, 3},
5815 {11, 246, 2, 10, 3},
5816 {12, 246, 7, 10, 3},
5817 {13, 247, 2, 10, 3},
5818 {14, 248, 4, 10, 3},
5819 {36, 86, 4, 12, 1},
5820 {38, 86, 6, 12, 1},
5821 {40, 86, 8, 12, 1},
5822 {42, 86, 10, 12, 1},
5823 {44, 87, 0, 12, 1},
5824 {46, 87, 2, 12, 1},
5825 {48, 87, 4, 12, 1},
5826 {50, 87, 6, 12, 1},
5827 {52, 87, 8, 12, 1},
5828 {54, 87, 10, 12, 1},
5829 {56, 88, 0, 12, 1},
5830 {58, 88, 2, 12, 1},
5831 {60, 88, 4, 12, 1},
5832 {62, 88, 6, 12, 1},
5833 {64, 88, 8, 12, 1},
5834 {100, 91, 8, 12, 1},
5835 {102, 91, 10, 12, 1},
5836 {104, 92, 0, 12, 1},
5837 {106, 92, 2, 12, 1},
5838 {108, 92, 4, 12, 1},
5839 {110, 92, 6, 12, 1},
5840 {112, 92, 8, 12, 1},
5841 {114, 92, 10, 12, 1},
5842 {116, 93, 0, 12, 1},
5843 {118, 93, 2, 12, 1},
5844 {120, 93, 4, 12, 1},
5845 {122, 93, 6, 12, 1},
5846 {124, 93, 8, 12, 1},
5847 {126, 93, 10, 12, 1},
5848 {128, 94, 0, 12, 1},
5849 {130, 94, 2, 12, 1},
5850 {132, 94, 4, 12, 1},
5851 {134, 94, 6, 12, 1},
5852 {136, 94, 8, 12, 1},
5853 {138, 94, 10, 12, 1},
5854 {140, 95, 0, 12, 1},
5855 {149, 95, 9, 12, 1},
5856 {151, 95, 11, 12, 1},
5857 {153, 96, 1, 12, 1},
5858 {155, 96, 3, 12, 1},
5859 {157, 96, 5, 12, 1},
5860 {159, 96, 7, 12, 1},
5861 {161, 96, 9, 12, 1},
5862 {165, 97, 1, 12, 1},
5863 {184, 82, 0, 12, 1},
5864 {188, 82, 4, 12, 1},
5865 {192, 82, 8, 12, 1},
5866 {196, 83, 0, 12, 1},
5867 };
5868
5869 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5870 {
5871 struct hw_mode_spec *spec = &rt2x00dev->spec;
5872 struct channel_info *info;
5873 char *default_power1;
5874 char *default_power2;
5875 unsigned int i;
5876 u16 eeprom;
5877 u32 reg;
5878
5879 /*
5880 * Disable powersaving as default on PCI devices.
5881 */
5882 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5883 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5884
5885 /*
5886 * Initialize all hw fields.
5887 */
5888 rt2x00dev->hw->flags =
5889 IEEE80211_HW_SIGNAL_DBM |
5890 IEEE80211_HW_SUPPORTS_PS |
5891 IEEE80211_HW_PS_NULLFUNC_STACK |
5892 IEEE80211_HW_AMPDU_AGGREGATION |
5893 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5894
5895 /*
5896 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5897 * unless we are capable of sending the buffered frames out after the
5898 * DTIM transmission using rt2x00lib_beacondone. This will send out
5899 * multicast and broadcast traffic immediately instead of buffering it
5900 * infinitly and thus dropping it after some time.
5901 */
5902 if (!rt2x00_is_usb(rt2x00dev))
5903 rt2x00dev->hw->flags |=
5904 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5905
5906 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5907 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5908 rt2x00_eeprom_addr(rt2x00dev,
5909 EEPROM_MAC_ADDR_0));
5910
5911 /*
5912 * As rt2800 has a global fallback table we cannot specify
5913 * more then one tx rate per frame but since the hw will
5914 * try several rates (based on the fallback table) we should
5915 * initialize max_report_rates to the maximum number of rates
5916 * we are going to try. Otherwise mac80211 will truncate our
5917 * reported tx rates and the rc algortihm will end up with
5918 * incorrect data.
5919 */
5920 rt2x00dev->hw->max_rates = 1;
5921 rt2x00dev->hw->max_report_rates = 7;
5922 rt2x00dev->hw->max_rate_tries = 1;
5923
5924 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5925
5926 /*
5927 * Initialize hw_mode information.
5928 */
5929 spec->supported_bands = SUPPORT_BAND_2GHZ;
5930 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5931
5932 if (rt2x00_rf(rt2x00dev, RF2820) ||
5933 rt2x00_rf(rt2x00dev, RF2720)) {
5934 spec->num_channels = 14;
5935 spec->channels = rf_vals;
5936 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5937 rt2x00_rf(rt2x00dev, RF2750)) {
5938 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5939 spec->num_channels = ARRAY_SIZE(rf_vals);
5940 spec->channels = rf_vals;
5941 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5942 rt2x00_rf(rt2x00dev, RF2020) ||
5943 rt2x00_rf(rt2x00dev, RF3021) ||
5944 rt2x00_rf(rt2x00dev, RF3022) ||
5945 rt2x00_rf(rt2x00dev, RF3290) ||
5946 rt2x00_rf(rt2x00dev, RF3320) ||
5947 rt2x00_rf(rt2x00dev, RF3322) ||
5948 rt2x00_rf(rt2x00dev, RF5360) ||
5949 rt2x00_rf(rt2x00dev, RF5370) ||
5950 rt2x00_rf(rt2x00dev, RF5372) ||
5951 rt2x00_rf(rt2x00dev, RF5390) ||
5952 rt2x00_rf(rt2x00dev, RF5392)) {
5953 spec->num_channels = 14;
5954 spec->channels = rf_vals_3x;
5955 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5956 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5957 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5958 spec->channels = rf_vals_3x;
5959 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5960 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5961
5962 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5963 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5964 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5965 spec->channels = rf_vals_5592_xtal40;
5966 } else {
5967 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5968 spec->channels = rf_vals_5592_xtal20;
5969 }
5970 }
5971
5972 if (WARN_ON_ONCE(!spec->channels))
5973 return -ENODEV;
5974
5975 /*
5976 * Initialize HT information.
5977 */
5978 if (!rt2x00_rf(rt2x00dev, RF2020))
5979 spec->ht.ht_supported = true;
5980 else
5981 spec->ht.ht_supported = false;
5982
5983 spec->ht.cap =
5984 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5985 IEEE80211_HT_CAP_GRN_FLD |
5986 IEEE80211_HT_CAP_SGI_20 |
5987 IEEE80211_HT_CAP_SGI_40;
5988
5989 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5990 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5991
5992 spec->ht.cap |=
5993 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5994 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5995
5996 spec->ht.ampdu_factor = 3;
5997 spec->ht.ampdu_density = 4;
5998 spec->ht.mcs.tx_params =
5999 IEEE80211_HT_MCS_TX_DEFINED |
6000 IEEE80211_HT_MCS_TX_RX_DIFF |
6001 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
6002 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
6003
6004 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
6005 case 3:
6006 spec->ht.mcs.rx_mask[2] = 0xff;
6007 case 2:
6008 spec->ht.mcs.rx_mask[1] = 0xff;
6009 case 1:
6010 spec->ht.mcs.rx_mask[0] = 0xff;
6011 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
6012 break;
6013 }
6014
6015 /*
6016 * Create channel information array
6017 */
6018 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
6019 if (!info)
6020 return -ENOMEM;
6021
6022 spec->channels_info = info;
6023
6024 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6025 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
6026
6027 for (i = 0; i < 14; i++) {
6028 info[i].default_power1 = default_power1[i];
6029 info[i].default_power2 = default_power2[i];
6030 }
6031
6032 if (spec->num_channels > 14) {
6033 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
6034 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
6035
6036 for (i = 14; i < spec->num_channels; i++) {
6037 info[i].default_power1 = default_power1[i];
6038 info[i].default_power2 = default_power2[i];
6039 }
6040 }
6041
6042 switch (rt2x00dev->chip.rf) {
6043 case RF2020:
6044 case RF3020:
6045 case RF3021:
6046 case RF3022:
6047 case RF3320:
6048 case RF3052:
6049 case RF3290:
6050 case RF5360:
6051 case RF5370:
6052 case RF5372:
6053 case RF5390:
6054 case RF5392:
6055 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6056 break;
6057 }
6058
6059 return 0;
6060 }
6061
6062 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6063 {
6064 int retval;
6065 u32 reg;
6066
6067 /*
6068 * Allocate eeprom data.
6069 */
6070 retval = rt2800_validate_eeprom(rt2x00dev);
6071 if (retval)
6072 return retval;
6073
6074 retval = rt2800_init_eeprom(rt2x00dev);
6075 if (retval)
6076 return retval;
6077
6078 /*
6079 * Enable rfkill polling by setting GPIO direction of the
6080 * rfkill switch GPIO pin correctly.
6081 */
6082 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6083 rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6084 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6085
6086 /*
6087 * Initialize hw specifications.
6088 */
6089 retval = rt2800_probe_hw_mode(rt2x00dev);
6090 if (retval)
6091 return retval;
6092
6093 /*
6094 * Set device capabilities.
6095 */
6096 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6097 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6098 if (!rt2x00_is_usb(rt2x00dev))
6099 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6100
6101 /*
6102 * Set device requirements.
6103 */
6104 if (!rt2x00_is_soc(rt2x00dev))
6105 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6106 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6107 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6108 if (!rt2800_hwcrypt_disabled(rt2x00dev))
6109 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6110 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6111 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6112 if (rt2x00_is_usb(rt2x00dev))
6113 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6114 else {
6115 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6116 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6117 }
6118
6119 /*
6120 * Set the rssi offset.
6121 */
6122 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6123
6124 return 0;
6125 }
6126 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
6127
6128 /*
6129 * IEEE80211 stack callback functions.
6130 */
6131 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6132 u16 *iv16)
6133 {
6134 struct rt2x00_dev *rt2x00dev = hw->priv;
6135 struct mac_iveiv_entry iveiv_entry;
6136 u32 offset;
6137
6138 offset = MAC_IVEIV_ENTRY(hw_key_idx);
6139 rt2800_register_multiread(rt2x00dev, offset,
6140 &iveiv_entry, sizeof(iveiv_entry));
6141
6142 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6143 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
6144 }
6145 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
6146
6147 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6148 {
6149 struct rt2x00_dev *rt2x00dev = hw->priv;
6150 u32 reg;
6151 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6152
6153 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6154 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6155 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6156
6157 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6158 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6159 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6160
6161 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6162 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6163 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6164
6165 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6166 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6167 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6168
6169 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6170 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6171 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6172
6173 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6174 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6175 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6176
6177 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6178 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6179 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6180
6181 return 0;
6182 }
6183 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6184
6185 int rt2800_conf_tx(struct ieee80211_hw *hw,
6186 struct ieee80211_vif *vif, u16 queue_idx,
6187 const struct ieee80211_tx_queue_params *params)
6188 {
6189 struct rt2x00_dev *rt2x00dev = hw->priv;
6190 struct data_queue *queue;
6191 struct rt2x00_field32 field;
6192 int retval;
6193 u32 reg;
6194 u32 offset;
6195
6196 /*
6197 * First pass the configuration through rt2x00lib, that will
6198 * update the queue settings and validate the input. After that
6199 * we are free to update the registers based on the value
6200 * in the queue parameter.
6201 */
6202 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6203 if (retval)
6204 return retval;
6205
6206 /*
6207 * We only need to perform additional register initialization
6208 * for WMM queues/
6209 */
6210 if (queue_idx >= 4)
6211 return 0;
6212
6213 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6214
6215 /* Update WMM TXOP register */
6216 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6217 field.bit_offset = (queue_idx & 1) * 16;
6218 field.bit_mask = 0xffff << field.bit_offset;
6219
6220 rt2800_register_read(rt2x00dev, offset, &reg);
6221 rt2x00_set_field32(&reg, field, queue->txop);
6222 rt2800_register_write(rt2x00dev, offset, reg);
6223
6224 /* Update WMM registers */
6225 field.bit_offset = queue_idx * 4;
6226 field.bit_mask = 0xf << field.bit_offset;
6227
6228 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6229 rt2x00_set_field32(&reg, field, queue->aifs);
6230 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6231
6232 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6233 rt2x00_set_field32(&reg, field, queue->cw_min);
6234 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6235
6236 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6237 rt2x00_set_field32(&reg, field, queue->cw_max);
6238 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6239
6240 /* Update EDCA registers */
6241 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6242
6243 rt2800_register_read(rt2x00dev, offset, &reg);
6244 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6245 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6246 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6247 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6248 rt2800_register_write(rt2x00dev, offset, reg);
6249
6250 return 0;
6251 }
6252 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6253
6254 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6255 {
6256 struct rt2x00_dev *rt2x00dev = hw->priv;
6257 u64 tsf;
6258 u32 reg;
6259
6260 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6261 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6262 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6263 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6264
6265 return tsf;
6266 }
6267 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6268
6269 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6270 enum ieee80211_ampdu_mlme_action action,
6271 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6272 u8 buf_size)
6273 {
6274 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6275 int ret = 0;
6276
6277 /*
6278 * Don't allow aggregation for stations the hardware isn't aware
6279 * of because tx status reports for frames to an unknown station
6280 * always contain wcid=255 and thus we can't distinguish between
6281 * multiple stations which leads to unwanted situations when the
6282 * hw reorders frames due to aggregation.
6283 */
6284 if (sta_priv->wcid < 0)
6285 return 1;
6286
6287 switch (action) {
6288 case IEEE80211_AMPDU_RX_START:
6289 case IEEE80211_AMPDU_RX_STOP:
6290 /*
6291 * The hw itself takes care of setting up BlockAck mechanisms.
6292 * So, we only have to allow mac80211 to nagotiate a BlockAck
6293 * agreement. Once that is done, the hw will BlockAck incoming
6294 * AMPDUs without further setup.
6295 */
6296 break;
6297 case IEEE80211_AMPDU_TX_START:
6298 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6299 break;
6300 case IEEE80211_AMPDU_TX_STOP_CONT:
6301 case IEEE80211_AMPDU_TX_STOP_FLUSH:
6302 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6303 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6304 break;
6305 case IEEE80211_AMPDU_TX_OPERATIONAL:
6306 break;
6307 default:
6308 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
6309 }
6310
6311 return ret;
6312 }
6313 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6314
6315 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6316 struct survey_info *survey)
6317 {
6318 struct rt2x00_dev *rt2x00dev = hw->priv;
6319 struct ieee80211_conf *conf = &hw->conf;
6320 u32 idle, busy, busy_ext;
6321
6322 if (idx != 0)
6323 return -ENOENT;
6324
6325 survey->channel = conf->channel;
6326
6327 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6328 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6329 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6330
6331 if (idle || busy) {
6332 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6333 SURVEY_INFO_CHANNEL_TIME_BUSY |
6334 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6335
6336 survey->channel_time = (idle + busy) / 1000;
6337 survey->channel_time_busy = busy / 1000;
6338 survey->channel_time_ext_busy = busy_ext / 1000;
6339 }
6340
6341 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6342 survey->filled |= SURVEY_INFO_IN_USE;
6343
6344 return 0;
6345
6346 }
6347 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6348
6349 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6350 MODULE_VERSION(DRV_VERSION);
6351 MODULE_DESCRIPTION("Ralink RT2800 library");
6352 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)