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mwl8k: fix addr4 zeroing and payload overwrite on DMA header creation
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
89 };
90
91 struct mwl8k_device_info {
92 char *part_name;
93 char *helper_image;
94 char *fw_image;
95 struct rxd_ops *rxd_ops;
96 u16 modes;
97 };
98
99 struct mwl8k_rx_queue {
100 int rxd_count;
101
102 /* hw receives here */
103 int head;
104
105 /* refill descs here */
106 int tail;
107
108 void *rxd;
109 dma_addr_t rxd_dma;
110 struct {
111 struct sk_buff *skb;
112 DECLARE_PCI_UNMAP_ADDR(dma)
113 } *buf;
114 };
115
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
118 int head;
119
120 /* sw appends here */
121 int tail;
122
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
127 };
128
129 /* Pointers to the firmware data and meta information about it. */
130 struct mwl8k_firmware {
131 /* Boot helper code */
132 struct firmware *helper;
133
134 /* Microcode */
135 struct firmware *ucode;
136 };
137
138 struct mwl8k_priv {
139 void __iomem *sram;
140 void __iomem *regs;
141 struct ieee80211_hw *hw;
142
143 struct pci_dev *pdev;
144
145 struct mwl8k_device_info *device_info;
146 bool ap_fw;
147 struct rxd_ops *rxd_ops;
148
149 /* firmware files and meta data */
150 struct mwl8k_firmware fw;
151
152 /* firmware access */
153 struct mutex fw_mutex;
154 struct task_struct *fw_mutex_owner;
155 int fw_mutex_depth;
156 struct completion *hostcmd_wait;
157
158 /* lock held over TX and TX reap */
159 spinlock_t tx_lock;
160
161 /* TX quiesce completion, protected by fw_mutex and tx_lock */
162 struct completion *tx_wait;
163
164 struct ieee80211_vif *vif;
165
166 struct ieee80211_channel *current_channel;
167
168 /* power management status cookie from firmware */
169 u32 *cookie;
170 dma_addr_t cookie_dma;
171
172 u16 num_mcaddrs;
173 u8 hw_rev;
174 u32 fw_rev;
175
176 /*
177 * Running count of TX packets in flight, to avoid
178 * iterating over the transmit rings each time.
179 */
180 int pending_tx_pkts;
181
182 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
183 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
184
185 /* PHY parameters */
186 struct ieee80211_supported_band band;
187 struct ieee80211_channel channels[14];
188 struct ieee80211_rate rates[14];
189
190 bool radio_on;
191 bool radio_short_preamble;
192 bool sniffer_enabled;
193 bool wmm_enabled;
194
195 /* XXX need to convert this to handle multiple interfaces */
196 bool capture_beacon;
197 u8 capture_bssid[ETH_ALEN];
198 struct sk_buff *beacon_skb;
199
200 /*
201 * This FJ worker has to be global as it is scheduled from the
202 * RX handler. At this point we don't know which interface it
203 * belongs to until the list of bssids waiting to complete join
204 * is checked.
205 */
206 struct work_struct finalize_join_worker;
207
208 /* Tasklet to reclaim TX descriptors and buffers after tx */
209 struct tasklet_struct tx_reclaim_task;
210 };
211
212 /* Per interface specific private data */
213 struct mwl8k_vif {
214 /* backpointer to parent config block */
215 struct mwl8k_priv *priv;
216
217 /* BSS config of AP or IBSS from mac80211*/
218 struct ieee80211_bss_conf bss_info;
219
220 /* BSSID of AP or IBSS */
221 u8 bssid[ETH_ALEN];
222 u8 mac_addr[ETH_ALEN];
223
224 /* Index into station database.Returned by update_sta_db call */
225 u8 peer_id;
226
227 /* Non AMPDU sequence number assigned by driver */
228 u16 seqno;
229 };
230
231 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
232
233 static const struct ieee80211_channel mwl8k_channels[] = {
234 { .center_freq = 2412, .hw_value = 1, },
235 { .center_freq = 2417, .hw_value = 2, },
236 { .center_freq = 2422, .hw_value = 3, },
237 { .center_freq = 2427, .hw_value = 4, },
238 { .center_freq = 2432, .hw_value = 5, },
239 { .center_freq = 2437, .hw_value = 6, },
240 { .center_freq = 2442, .hw_value = 7, },
241 { .center_freq = 2447, .hw_value = 8, },
242 { .center_freq = 2452, .hw_value = 9, },
243 { .center_freq = 2457, .hw_value = 10, },
244 { .center_freq = 2462, .hw_value = 11, },
245 };
246
247 static const struct ieee80211_rate mwl8k_rates[] = {
248 { .bitrate = 10, .hw_value = 2, },
249 { .bitrate = 20, .hw_value = 4, },
250 { .bitrate = 55, .hw_value = 11, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 220, .hw_value = 44, },
253 { .bitrate = 60, .hw_value = 12, },
254 { .bitrate = 90, .hw_value = 18, },
255 { .bitrate = 120, .hw_value = 24, },
256 { .bitrate = 180, .hw_value = 36, },
257 { .bitrate = 240, .hw_value = 48, },
258 { .bitrate = 360, .hw_value = 72, },
259 { .bitrate = 480, .hw_value = 96, },
260 { .bitrate = 540, .hw_value = 108, },
261 { .bitrate = 720, .hw_value = 144, },
262 };
263
264 static const u8 mwl8k_rateids[12] = {
265 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
266 };
267
268 /* Set or get info from Firmware */
269 #define MWL8K_CMD_SET 0x0001
270 #define MWL8K_CMD_GET 0x0000
271
272 /* Firmware command codes */
273 #define MWL8K_CMD_CODE_DNLD 0x0001
274 #define MWL8K_CMD_GET_HW_SPEC 0x0003
275 #define MWL8K_CMD_SET_HW_SPEC 0x0004
276 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
277 #define MWL8K_CMD_GET_STAT 0x0014
278 #define MWL8K_CMD_RADIO_CONTROL 0x001c
279 #define MWL8K_CMD_RF_TX_POWER 0x001e
280 #define MWL8K_CMD_RF_ANTENNA 0x0020
281 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
282 #define MWL8K_CMD_SET_POST_SCAN 0x0108
283 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284 #define MWL8K_CMD_SET_AID 0x010d
285 #define MWL8K_CMD_SET_RATE 0x0110
286 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
288 #define MWL8K_CMD_SET_SLOT 0x0114
289 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290 #define MWL8K_CMD_SET_WMM_MODE 0x0123
291 #define MWL8K_CMD_MIMO_CONFIG 0x0125
292 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
293 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
294 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
295 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
296 #define MWL8K_CMD_UPDATE_STADB 0x1123
297
298 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299 {
300 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
304 switch (cmd & ~0x8000) {
305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(SET_HW_SPEC);
308 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
309 MWL8K_CMDNAME(GET_STAT);
310 MWL8K_CMDNAME(RADIO_CONTROL);
311 MWL8K_CMDNAME(RF_TX_POWER);
312 MWL8K_CMDNAME(RF_ANTENNA);
313 MWL8K_CMDNAME(SET_PRE_SCAN);
314 MWL8K_CMDNAME(SET_POST_SCAN);
315 MWL8K_CMDNAME(SET_RF_CHANNEL);
316 MWL8K_CMDNAME(SET_AID);
317 MWL8K_CMDNAME(SET_RATE);
318 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
319 MWL8K_CMDNAME(RTS_THRESHOLD);
320 MWL8K_CMDNAME(SET_SLOT);
321 MWL8K_CMDNAME(SET_EDCA_PARAMS);
322 MWL8K_CMDNAME(SET_WMM_MODE);
323 MWL8K_CMDNAME(MIMO_CONFIG);
324 MWL8K_CMDNAME(USE_FIXED_RATE);
325 MWL8K_CMDNAME(ENABLE_SNIFFER);
326 MWL8K_CMDNAME(SET_MAC_ADDR);
327 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
328 MWL8K_CMDNAME(UPDATE_STADB);
329 default:
330 snprintf(buf, bufsize, "0x%x", cmd);
331 }
332 #undef MWL8K_CMDNAME
333
334 return buf;
335 }
336
337 /* Hardware and firmware reset */
338 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
339 {
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 iowrite32(MWL8K_H2A_INT_RESET,
343 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
344 msleep(20);
345 }
346
347 /* Release fw image */
348 static void mwl8k_release_fw(struct firmware **fw)
349 {
350 if (*fw == NULL)
351 return;
352 release_firmware(*fw);
353 *fw = NULL;
354 }
355
356 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
357 {
358 mwl8k_release_fw(&priv->fw.ucode);
359 mwl8k_release_fw(&priv->fw.helper);
360 }
361
362 /* Request fw image */
363 static int mwl8k_request_fw(struct mwl8k_priv *priv,
364 const char *fname, struct firmware **fw)
365 {
366 /* release current image */
367 if (*fw != NULL)
368 mwl8k_release_fw(fw);
369
370 return request_firmware((const struct firmware **)fw,
371 fname, &priv->pdev->dev);
372 }
373
374 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
375 {
376 struct mwl8k_device_info *di = priv->device_info;
377 int rc;
378
379 if (di->helper_image != NULL) {
380 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting helper "
383 "firmware file %s\n", pci_name(priv->pdev),
384 di->helper_image);
385 return rc;
386 }
387 }
388
389 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
390 if (rc) {
391 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
392 pci_name(priv->pdev), di->fw_image);
393 mwl8k_release_fw(&priv->fw.helper);
394 return rc;
395 }
396
397 return 0;
398 }
399
400 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
401 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
402
403 struct mwl8k_cmd_pkt {
404 __le16 code;
405 __le16 length;
406 __le16 seq_num;
407 __le16 result;
408 char payload[0];
409 } __attribute__((packed));
410
411 /*
412 * Firmware loading.
413 */
414 static int
415 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
416 {
417 void __iomem *regs = priv->regs;
418 dma_addr_t dma_addr;
419 int loops;
420
421 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
422 if (pci_dma_mapping_error(priv->pdev, dma_addr))
423 return -ENOMEM;
424
425 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 iowrite32(MWL8K_H2A_INT_DOORBELL,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429 iowrite32(MWL8K_H2A_INT_DUMMY,
430 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431
432 loops = 1000;
433 do {
434 u32 int_code;
435
436 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
437 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
439 break;
440 }
441
442 cond_resched();
443 udelay(1);
444 } while (--loops);
445
446 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
447
448 return loops ? 0 : -ETIMEDOUT;
449 }
450
451 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
452 const u8 *data, size_t length)
453 {
454 struct mwl8k_cmd_pkt *cmd;
455 int done;
456 int rc = 0;
457
458 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
459 if (cmd == NULL)
460 return -ENOMEM;
461
462 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 cmd->seq_num = 0;
464 cmd->result = 0;
465
466 done = 0;
467 while (length) {
468 int block_size = length > 256 ? 256 : length;
469
470 memcpy(cmd->payload, data + done, block_size);
471 cmd->length = cpu_to_le16(block_size);
472
473 rc = mwl8k_send_fw_load_cmd(priv, cmd,
474 sizeof(*cmd) + block_size);
475 if (rc)
476 break;
477
478 done += block_size;
479 length -= block_size;
480 }
481
482 if (!rc) {
483 cmd->length = 0;
484 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
485 }
486
487 kfree(cmd);
488
489 return rc;
490 }
491
492 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
493 const u8 *data, size_t length)
494 {
495 unsigned char *buffer;
496 int may_continue, rc = 0;
497 u32 done, prev_block_size;
498
499 buffer = kmalloc(1024, GFP_KERNEL);
500 if (buffer == NULL)
501 return -ENOMEM;
502
503 done = 0;
504 prev_block_size = 0;
505 may_continue = 1000;
506 while (may_continue > 0) {
507 u32 block_size;
508
509 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
510 if (block_size & 1) {
511 block_size &= ~1;
512 may_continue--;
513 } else {
514 done += prev_block_size;
515 length -= prev_block_size;
516 }
517
518 if (block_size > 1024 || block_size > length) {
519 rc = -EOVERFLOW;
520 break;
521 }
522
523 if (length == 0) {
524 rc = 0;
525 break;
526 }
527
528 if (block_size == 0) {
529 rc = -EPROTO;
530 may_continue--;
531 udelay(1);
532 continue;
533 }
534
535 prev_block_size = block_size;
536 memcpy(buffer, data + done, block_size);
537
538 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
539 if (rc)
540 break;
541 }
542
543 if (!rc && length != 0)
544 rc = -EREMOTEIO;
545
546 kfree(buffer);
547
548 return rc;
549 }
550
551 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
552 {
553 struct mwl8k_priv *priv = hw->priv;
554 struct firmware *fw = priv->fw.ucode;
555 struct mwl8k_device_info *di = priv->device_info;
556 int rc;
557 int loops;
558
559 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
560 struct firmware *helper = priv->fw.helper;
561
562 if (helper == NULL) {
563 printk(KERN_ERR "%s: helper image needed but none "
564 "given\n", pci_name(priv->pdev));
565 return -EINVAL;
566 }
567
568 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
569 if (rc) {
570 printk(KERN_ERR "%s: unable to load firmware "
571 "helper image\n", pci_name(priv->pdev));
572 return rc;
573 }
574 msleep(1);
575
576 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
577 } else {
578 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
579 }
580
581 if (rc) {
582 printk(KERN_ERR "%s: unable to load firmware image\n",
583 pci_name(priv->pdev));
584 return rc;
585 }
586
587 if (di->modes & BIT(NL80211_IFTYPE_AP))
588 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
589 else
590 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
591 msleep(1);
592
593 loops = 200000;
594 do {
595 u32 ready_code;
596
597 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
598 if (ready_code == MWL8K_FWAP_READY) {
599 priv->ap_fw = 1;
600 break;
601 } else if (ready_code == MWL8K_FWSTA_READY) {
602 priv->ap_fw = 0;
603 break;
604 }
605
606 cond_resched();
607 udelay(1);
608 } while (--loops);
609
610 return loops ? 0 : -ETIMEDOUT;
611 }
612
613
614 /*
615 * Defines shared between transmission and reception.
616 */
617 /* HT control fields for firmware */
618 struct ewc_ht_info {
619 __le16 control1;
620 __le16 control2;
621 __le16 control3;
622 } __attribute__((packed));
623
624 /* Firmware Station database operations */
625 #define MWL8K_STA_DB_ADD_ENTRY 0
626 #define MWL8K_STA_DB_MODIFY_ENTRY 1
627 #define MWL8K_STA_DB_DEL_ENTRY 2
628 #define MWL8K_STA_DB_FLUSH 3
629
630 /* Peer Entry flags - used to define the type of the peer node */
631 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
632
633 struct peer_capability_info {
634 /* Peer type - AP vs. STA. */
635 __u8 peer_type;
636
637 /* Basic 802.11 capabilities from assoc resp. */
638 __le16 basic_caps;
639
640 /* Set if peer supports 802.11n high throughput (HT). */
641 __u8 ht_support;
642
643 /* Valid if HT is supported. */
644 __le16 ht_caps;
645 __u8 extended_ht_caps;
646 struct ewc_ht_info ewc_info;
647
648 /* Legacy rate table. Intersection of our rates and peer rates. */
649 __u8 legacy_rates[12];
650
651 /* HT rate table. Intersection of our rates and peer rates. */
652 __u8 ht_rates[16];
653 __u8 pad[16];
654
655 /* If set, interoperability mode, no proprietary extensions. */
656 __u8 interop;
657 __u8 pad2;
658 __u8 station_id;
659 __le16 amsdu_enabled;
660 } __attribute__((packed));
661
662 /* Inline functions to manipulate QoS field in data descriptor. */
663 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
664 {
665 u16 val_mask = 1 << 4;
666
667 /* End of Service Period Bit 4 */
668 return qos | val_mask;
669 }
670
671 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
672 {
673 u16 val_mask = 0x3;
674 u8 shift = 5;
675 u16 qos_mask = ~(val_mask << shift);
676
677 /* Ack Policy Bit 5-6 */
678 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
679 }
680
681 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
682 {
683 u16 val_mask = 1 << 7;
684
685 /* AMSDU present Bit 7 */
686 return qos | val_mask;
687 }
688
689 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
690 {
691 u16 val_mask = 0xff;
692 u8 shift = 8;
693 u16 qos_mask = ~(val_mask << shift);
694
695 /* Queue Length Bits 8-15 */
696 return (qos & qos_mask) | ((len & val_mask) << shift);
697 }
698
699 /* DMA header used by firmware and hardware. */
700 struct mwl8k_dma_data {
701 __le16 fwlen;
702 struct ieee80211_hdr wh;
703 char data[0];
704 } __attribute__((packed));
705
706 /* Routines to add/remove DMA header from skb. */
707 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
708 {
709 struct mwl8k_dma_data *tr;
710 int hdrlen;
711
712 tr = (struct mwl8k_dma_data *)skb->data;
713 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
714
715 if (hdrlen != sizeof(tr->wh)) {
716 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
717 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
718 *((__le16 *)(tr->data - 2)) = qos;
719 } else {
720 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
721 }
722 }
723
724 if (hdrlen != sizeof(*tr))
725 skb_pull(skb, sizeof(*tr) - hdrlen);
726 }
727
728 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
729 {
730 struct ieee80211_hdr *wh;
731 int hdrlen;
732 struct mwl8k_dma_data *tr;
733
734 /*
735 * Add a firmware DMA header; the firmware requires that we
736 * present a 2-byte payload length followed by a 4-address
737 * header (without QoS field), followed (optionally) by any
738 * WEP/ExtIV header (but only filled in for CCMP).
739 */
740 wh = (struct ieee80211_hdr *)skb->data;
741
742 hdrlen = ieee80211_hdrlen(wh->frame_control);
743 if (hdrlen != sizeof(*tr))
744 skb_push(skb, sizeof(*tr) - hdrlen);
745
746 if (ieee80211_is_data_qos(wh->frame_control))
747 hdrlen -= 2;
748
749 tr = (struct mwl8k_dma_data *)skb->data;
750 if (wh != &tr->wh)
751 memmove(&tr->wh, wh, hdrlen);
752 if (hdrlen != sizeof(tr->wh))
753 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
754
755 /*
756 * Firmware length is the length of the fully formed "802.11
757 * payload". That is, everything except for the 802.11 header.
758 * This includes all crypto material including the MIC.
759 */
760 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
761 }
762
763
764 /*
765 * Packet reception for 88w8366.
766 */
767 struct mwl8k_rxd_8366 {
768 __le16 pkt_len;
769 __u8 sq2;
770 __u8 rate;
771 __le32 pkt_phys_addr;
772 __le32 next_rxd_phys_addr;
773 __le16 qos_control;
774 __le16 htsig2;
775 __le32 hw_rssi_info;
776 __le32 hw_noise_floor_info;
777 __u8 noise_floor;
778 __u8 pad0[3];
779 __u8 rssi;
780 __u8 rx_status;
781 __u8 channel;
782 __u8 rx_ctrl;
783 } __attribute__((packed));
784
785 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
786
787 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
788 {
789 struct mwl8k_rxd_8366 *rxd = _rxd;
790
791 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
792 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
793 }
794
795 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
796 {
797 struct mwl8k_rxd_8366 *rxd = _rxd;
798
799 rxd->pkt_len = cpu_to_le16(len);
800 rxd->pkt_phys_addr = cpu_to_le32(addr);
801 wmb();
802 rxd->rx_ctrl = 0;
803 }
804
805 static int
806 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
807 __le16 *qos)
808 {
809 struct mwl8k_rxd_8366 *rxd = _rxd;
810
811 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
812 return -1;
813 rmb();
814
815 memset(status, 0, sizeof(*status));
816
817 status->signal = -rxd->rssi;
818 status->noise = -rxd->noise_floor;
819
820 if (rxd->rate & 0x80) {
821 status->flag |= RX_FLAG_HT;
822 status->rate_idx = rxd->rate & 0x7f;
823 } else {
824 int i;
825
826 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
827 if (mwl8k_rates[i].hw_value == rxd->rate) {
828 status->rate_idx = i;
829 break;
830 }
831 }
832 }
833
834 status->band = IEEE80211_BAND_2GHZ;
835 status->freq = ieee80211_channel_to_frequency(rxd->channel);
836
837 *qos = rxd->qos_control;
838
839 return le16_to_cpu(rxd->pkt_len);
840 }
841
842 static struct rxd_ops rxd_8366_ops = {
843 .rxd_size = sizeof(struct mwl8k_rxd_8366),
844 .rxd_init = mwl8k_rxd_8366_init,
845 .rxd_refill = mwl8k_rxd_8366_refill,
846 .rxd_process = mwl8k_rxd_8366_process,
847 };
848
849 /*
850 * Packet reception for 88w8687.
851 */
852 struct mwl8k_rxd_8687 {
853 __le16 pkt_len;
854 __u8 link_quality;
855 __u8 noise_level;
856 __le32 pkt_phys_addr;
857 __le32 next_rxd_phys_addr;
858 __le16 qos_control;
859 __le16 rate_info;
860 __le32 pad0[4];
861 __u8 rssi;
862 __u8 channel;
863 __le16 pad1;
864 __u8 rx_ctrl;
865 __u8 rx_status;
866 __u8 pad2[2];
867 } __attribute__((packed));
868
869 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
870 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
871 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
872 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
873 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
874 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
875
876 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
877
878 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
879 {
880 struct mwl8k_rxd_8687 *rxd = _rxd;
881
882 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
883 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
884 }
885
886 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
887 {
888 struct mwl8k_rxd_8687 *rxd = _rxd;
889
890 rxd->pkt_len = cpu_to_le16(len);
891 rxd->pkt_phys_addr = cpu_to_le32(addr);
892 wmb();
893 rxd->rx_ctrl = 0;
894 }
895
896 static int
897 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
898 __le16 *qos)
899 {
900 struct mwl8k_rxd_8687 *rxd = _rxd;
901 u16 rate_info;
902
903 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
904 return -1;
905 rmb();
906
907 rate_info = le16_to_cpu(rxd->rate_info);
908
909 memset(status, 0, sizeof(*status));
910
911 status->signal = -rxd->rssi;
912 status->noise = -rxd->noise_level;
913 status->qual = rxd->link_quality;
914 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
915 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
916
917 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
918 status->flag |= RX_FLAG_SHORTPRE;
919 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
920 status->flag |= RX_FLAG_40MHZ;
921 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
922 status->flag |= RX_FLAG_SHORT_GI;
923 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
924 status->flag |= RX_FLAG_HT;
925
926 status->band = IEEE80211_BAND_2GHZ;
927 status->freq = ieee80211_channel_to_frequency(rxd->channel);
928
929 *qos = rxd->qos_control;
930
931 return le16_to_cpu(rxd->pkt_len);
932 }
933
934 static struct rxd_ops rxd_8687_ops = {
935 .rxd_size = sizeof(struct mwl8k_rxd_8687),
936 .rxd_init = mwl8k_rxd_8687_init,
937 .rxd_refill = mwl8k_rxd_8687_refill,
938 .rxd_process = mwl8k_rxd_8687_process,
939 };
940
941
942 #define MWL8K_RX_DESCS 256
943 #define MWL8K_RX_MAXSZ 3800
944
945 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
946 {
947 struct mwl8k_priv *priv = hw->priv;
948 struct mwl8k_rx_queue *rxq = priv->rxq + index;
949 int size;
950 int i;
951
952 rxq->rxd_count = 0;
953 rxq->head = 0;
954 rxq->tail = 0;
955
956 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
957
958 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
959 if (rxq->rxd == NULL) {
960 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
961 wiphy_name(hw->wiphy));
962 return -ENOMEM;
963 }
964 memset(rxq->rxd, 0, size);
965
966 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
967 if (rxq->buf == NULL) {
968 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
969 wiphy_name(hw->wiphy));
970 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
971 return -ENOMEM;
972 }
973 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
974
975 for (i = 0; i < MWL8K_RX_DESCS; i++) {
976 int desc_size;
977 void *rxd;
978 int nexti;
979 dma_addr_t next_dma_addr;
980
981 desc_size = priv->rxd_ops->rxd_size;
982 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
983
984 nexti = i + 1;
985 if (nexti == MWL8K_RX_DESCS)
986 nexti = 0;
987 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
988
989 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
990 }
991
992 return 0;
993 }
994
995 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
996 {
997 struct mwl8k_priv *priv = hw->priv;
998 struct mwl8k_rx_queue *rxq = priv->rxq + index;
999 int refilled;
1000
1001 refilled = 0;
1002 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
1003 struct sk_buff *skb;
1004 dma_addr_t addr;
1005 int rx;
1006 void *rxd;
1007
1008 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1009 if (skb == NULL)
1010 break;
1011
1012 addr = pci_map_single(priv->pdev, skb->data,
1013 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
1014
1015 rxq->rxd_count++;
1016 rx = rxq->tail++;
1017 if (rxq->tail == MWL8K_RX_DESCS)
1018 rxq->tail = 0;
1019 rxq->buf[rx].skb = skb;
1020 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
1021
1022 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1023 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
1024
1025 refilled++;
1026 }
1027
1028 return refilled;
1029 }
1030
1031 /* Must be called only when the card's reception is completely halted */
1032 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1033 {
1034 struct mwl8k_priv *priv = hw->priv;
1035 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1036 int i;
1037
1038 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1039 if (rxq->buf[i].skb != NULL) {
1040 pci_unmap_single(priv->pdev,
1041 pci_unmap_addr(&rxq->buf[i], dma),
1042 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1043 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1044
1045 kfree_skb(rxq->buf[i].skb);
1046 rxq->buf[i].skb = NULL;
1047 }
1048 }
1049
1050 kfree(rxq->buf);
1051 rxq->buf = NULL;
1052
1053 pci_free_consistent(priv->pdev,
1054 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1055 rxq->rxd, rxq->rxd_dma);
1056 rxq->rxd = NULL;
1057 }
1058
1059
1060 /*
1061 * Scan a list of BSSIDs to process for finalize join.
1062 * Allows for extension to process multiple BSSIDs.
1063 */
1064 static inline int
1065 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1066 {
1067 return priv->capture_beacon &&
1068 ieee80211_is_beacon(wh->frame_control) &&
1069 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1070 }
1071
1072 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1073 struct sk_buff *skb)
1074 {
1075 struct mwl8k_priv *priv = hw->priv;
1076
1077 priv->capture_beacon = false;
1078 memset(priv->capture_bssid, 0, ETH_ALEN);
1079
1080 /*
1081 * Use GFP_ATOMIC as rxq_process is called from
1082 * the primary interrupt handler, memory allocation call
1083 * must not sleep.
1084 */
1085 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1086 if (priv->beacon_skb != NULL)
1087 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1088 }
1089
1090 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1091 {
1092 struct mwl8k_priv *priv = hw->priv;
1093 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1094 int processed;
1095
1096 processed = 0;
1097 while (rxq->rxd_count && limit--) {
1098 struct sk_buff *skb;
1099 void *rxd;
1100 int pkt_len;
1101 struct ieee80211_rx_status status;
1102 __le16 qos;
1103
1104 skb = rxq->buf[rxq->head].skb;
1105 if (skb == NULL)
1106 break;
1107
1108 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1109
1110 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1111 if (pkt_len < 0)
1112 break;
1113
1114 rxq->buf[rxq->head].skb = NULL;
1115
1116 pci_unmap_single(priv->pdev,
1117 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1118 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1119 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1120
1121 rxq->head++;
1122 if (rxq->head == MWL8K_RX_DESCS)
1123 rxq->head = 0;
1124
1125 rxq->rxd_count--;
1126
1127 skb_put(skb, pkt_len);
1128 mwl8k_remove_dma_header(skb, qos);
1129
1130 /*
1131 * Check for a pending join operation. Save a
1132 * copy of the beacon and schedule a tasklet to
1133 * send a FINALIZE_JOIN command to the firmware.
1134 */
1135 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1136 mwl8k_save_beacon(hw, skb);
1137
1138 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1139 ieee80211_rx_irqsafe(hw, skb);
1140
1141 processed++;
1142 }
1143
1144 return processed;
1145 }
1146
1147
1148 /*
1149 * Packet transmission.
1150 */
1151
1152 /* Transmit packet ACK policy */
1153 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1154 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1155
1156 #define MWL8K_TXD_STATUS_OK 0x00000001
1157 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1158 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1159 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1160 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1161
1162 struct mwl8k_tx_desc {
1163 __le32 status;
1164 __u8 data_rate;
1165 __u8 tx_priority;
1166 __le16 qos_control;
1167 __le32 pkt_phys_addr;
1168 __le16 pkt_len;
1169 __u8 dest_MAC_addr[ETH_ALEN];
1170 __le32 next_txd_phys_addr;
1171 __le32 reserved;
1172 __le16 rate_info;
1173 __u8 peer_id;
1174 __u8 tx_frag_cnt;
1175 } __attribute__((packed));
1176
1177 #define MWL8K_TX_DESCS 128
1178
1179 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1180 {
1181 struct mwl8k_priv *priv = hw->priv;
1182 struct mwl8k_tx_queue *txq = priv->txq + index;
1183 int size;
1184 int i;
1185
1186 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1187 txq->stats.limit = MWL8K_TX_DESCS;
1188 txq->head = 0;
1189 txq->tail = 0;
1190
1191 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1192
1193 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1194 if (txq->txd == NULL) {
1195 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1196 wiphy_name(hw->wiphy));
1197 return -ENOMEM;
1198 }
1199 memset(txq->txd, 0, size);
1200
1201 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1202 if (txq->skb == NULL) {
1203 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1204 wiphy_name(hw->wiphy));
1205 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1206 return -ENOMEM;
1207 }
1208 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1209
1210 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1211 struct mwl8k_tx_desc *tx_desc;
1212 int nexti;
1213
1214 tx_desc = txq->txd + i;
1215 nexti = (i + 1) % MWL8K_TX_DESCS;
1216
1217 tx_desc->status = 0;
1218 tx_desc->next_txd_phys_addr =
1219 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1220 }
1221
1222 return 0;
1223 }
1224
1225 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1226 {
1227 iowrite32(MWL8K_H2A_INT_PPA_READY,
1228 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1229 iowrite32(MWL8K_H2A_INT_DUMMY,
1230 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1231 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1232 }
1233
1234 struct mwl8k_txq_info {
1235 u32 fw_owned;
1236 u32 drv_owned;
1237 u32 unused;
1238 u32 len;
1239 u32 head;
1240 u32 tail;
1241 };
1242
1243 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1244 struct mwl8k_txq_info *txinfo)
1245 {
1246 int count, desc, status;
1247 struct mwl8k_tx_queue *txq;
1248 struct mwl8k_tx_desc *tx_desc;
1249 int ndescs = 0;
1250
1251 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1252
1253 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1254 txq = priv->txq + count;
1255 txinfo[count].len = txq->stats.len;
1256 txinfo[count].head = txq->head;
1257 txinfo[count].tail = txq->tail;
1258 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1259 tx_desc = txq->txd + desc;
1260 status = le32_to_cpu(tx_desc->status);
1261
1262 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1263 txinfo[count].fw_owned++;
1264 else
1265 txinfo[count].drv_owned++;
1266
1267 if (tx_desc->pkt_len == 0)
1268 txinfo[count].unused++;
1269 }
1270 }
1271
1272 return ndescs;
1273 }
1274
1275 /*
1276 * Must be called with priv->fw_mutex held and tx queues stopped.
1277 */
1278 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1279 {
1280 struct mwl8k_priv *priv = hw->priv;
1281 DECLARE_COMPLETION_ONSTACK(tx_wait);
1282 u32 count;
1283 unsigned long timeout;
1284
1285 might_sleep();
1286
1287 spin_lock_bh(&priv->tx_lock);
1288 count = priv->pending_tx_pkts;
1289 if (count)
1290 priv->tx_wait = &tx_wait;
1291 spin_unlock_bh(&priv->tx_lock);
1292
1293 if (count) {
1294 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1295 int index;
1296 int newcount;
1297
1298 timeout = wait_for_completion_timeout(&tx_wait,
1299 msecs_to_jiffies(5000));
1300 if (timeout)
1301 return 0;
1302
1303 spin_lock_bh(&priv->tx_lock);
1304 priv->tx_wait = NULL;
1305 newcount = priv->pending_tx_pkts;
1306 mwl8k_scan_tx_ring(priv, txinfo);
1307 spin_unlock_bh(&priv->tx_lock);
1308
1309 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1310 __func__, __LINE__, count, newcount);
1311
1312 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1313 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1314 "DRV:%u U:%u\n",
1315 index,
1316 txinfo[index].len,
1317 txinfo[index].head,
1318 txinfo[index].tail,
1319 txinfo[index].fw_owned,
1320 txinfo[index].drv_owned,
1321 txinfo[index].unused);
1322
1323 return -ETIMEDOUT;
1324 }
1325
1326 return 0;
1327 }
1328
1329 #define MWL8K_TXD_SUCCESS(status) \
1330 ((status) & (MWL8K_TXD_STATUS_OK | \
1331 MWL8K_TXD_STATUS_OK_RETRY | \
1332 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1333
1334 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1335 {
1336 struct mwl8k_priv *priv = hw->priv;
1337 struct mwl8k_tx_queue *txq = priv->txq + index;
1338 int wake = 0;
1339
1340 while (txq->stats.len > 0) {
1341 int tx;
1342 struct mwl8k_tx_desc *tx_desc;
1343 unsigned long addr;
1344 int size;
1345 struct sk_buff *skb;
1346 struct ieee80211_tx_info *info;
1347 u32 status;
1348
1349 tx = txq->head;
1350 tx_desc = txq->txd + tx;
1351
1352 status = le32_to_cpu(tx_desc->status);
1353
1354 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1355 if (!force)
1356 break;
1357 tx_desc->status &=
1358 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1359 }
1360
1361 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1362 BUG_ON(txq->stats.len == 0);
1363 txq->stats.len--;
1364 priv->pending_tx_pkts--;
1365
1366 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1367 size = le16_to_cpu(tx_desc->pkt_len);
1368 skb = txq->skb[tx];
1369 txq->skb[tx] = NULL;
1370
1371 BUG_ON(skb == NULL);
1372 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1373
1374 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1375
1376 /* Mark descriptor as unused */
1377 tx_desc->pkt_phys_addr = 0;
1378 tx_desc->pkt_len = 0;
1379
1380 info = IEEE80211_SKB_CB(skb);
1381 ieee80211_tx_info_clear_status(info);
1382 if (MWL8K_TXD_SUCCESS(status))
1383 info->flags |= IEEE80211_TX_STAT_ACK;
1384
1385 ieee80211_tx_status_irqsafe(hw, skb);
1386
1387 wake = 1;
1388 }
1389
1390 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1391 ieee80211_wake_queue(hw, index);
1392 }
1393
1394 /* must be called only when the card's transmit is completely halted */
1395 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1396 {
1397 struct mwl8k_priv *priv = hw->priv;
1398 struct mwl8k_tx_queue *txq = priv->txq + index;
1399
1400 mwl8k_txq_reclaim(hw, index, 1);
1401
1402 kfree(txq->skb);
1403 txq->skb = NULL;
1404
1405 pci_free_consistent(priv->pdev,
1406 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1407 txq->txd, txq->txd_dma);
1408 txq->txd = NULL;
1409 }
1410
1411 static int
1412 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1413 {
1414 struct mwl8k_priv *priv = hw->priv;
1415 struct ieee80211_tx_info *tx_info;
1416 struct mwl8k_vif *mwl8k_vif;
1417 struct ieee80211_hdr *wh;
1418 struct mwl8k_tx_queue *txq;
1419 struct mwl8k_tx_desc *tx;
1420 dma_addr_t dma;
1421 u32 txstatus;
1422 u8 txdatarate;
1423 u16 qos;
1424
1425 wh = (struct ieee80211_hdr *)skb->data;
1426 if (ieee80211_is_data_qos(wh->frame_control))
1427 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1428 else
1429 qos = 0;
1430
1431 mwl8k_add_dma_header(skb);
1432 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1433
1434 tx_info = IEEE80211_SKB_CB(skb);
1435 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1436
1437 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1438 u16 seqno = mwl8k_vif->seqno;
1439
1440 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1441 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1442 mwl8k_vif->seqno = seqno++ % 4096;
1443 }
1444
1445 /* Setup firmware control bit fields for each frame type. */
1446 txstatus = 0;
1447 txdatarate = 0;
1448 if (ieee80211_is_mgmt(wh->frame_control) ||
1449 ieee80211_is_ctl(wh->frame_control)) {
1450 txdatarate = 0;
1451 qos = mwl8k_qos_setbit_eosp(qos);
1452 /* Set Queue size to unspecified */
1453 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1454 } else if (ieee80211_is_data(wh->frame_control)) {
1455 txdatarate = 1;
1456 if (is_multicast_ether_addr(wh->addr1))
1457 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1458
1459 /* Send pkt in an aggregate if AMPDU frame. */
1460 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1461 qos = mwl8k_qos_setbit_ack(qos,
1462 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1463 else
1464 qos = mwl8k_qos_setbit_ack(qos,
1465 MWL8K_TXD_ACK_POLICY_NORMAL);
1466
1467 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1468 qos = mwl8k_qos_setbit_amsdu(qos);
1469 }
1470
1471 dma = pci_map_single(priv->pdev, skb->data,
1472 skb->len, PCI_DMA_TODEVICE);
1473
1474 if (pci_dma_mapping_error(priv->pdev, dma)) {
1475 printk(KERN_DEBUG "%s: failed to dma map skb, "
1476 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1477 dev_kfree_skb(skb);
1478 return NETDEV_TX_OK;
1479 }
1480
1481 spin_lock_bh(&priv->tx_lock);
1482
1483 txq = priv->txq + index;
1484
1485 BUG_ON(txq->skb[txq->tail] != NULL);
1486 txq->skb[txq->tail] = skb;
1487
1488 tx = txq->txd + txq->tail;
1489 tx->data_rate = txdatarate;
1490 tx->tx_priority = index;
1491 tx->qos_control = cpu_to_le16(qos);
1492 tx->pkt_phys_addr = cpu_to_le32(dma);
1493 tx->pkt_len = cpu_to_le16(skb->len);
1494 tx->rate_info = 0;
1495 tx->peer_id = mwl8k_vif->peer_id;
1496 wmb();
1497 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1498
1499 txq->stats.count++;
1500 txq->stats.len++;
1501 priv->pending_tx_pkts++;
1502
1503 txq->tail++;
1504 if (txq->tail == MWL8K_TX_DESCS)
1505 txq->tail = 0;
1506
1507 if (txq->head == txq->tail)
1508 ieee80211_stop_queue(hw, index);
1509
1510 mwl8k_tx_start(priv);
1511
1512 spin_unlock_bh(&priv->tx_lock);
1513
1514 return NETDEV_TX_OK;
1515 }
1516
1517
1518 /*
1519 * Firmware access.
1520 *
1521 * We have the following requirements for issuing firmware commands:
1522 * - Some commands require that the packet transmit path is idle when
1523 * the command is issued. (For simplicity, we'll just quiesce the
1524 * transmit path for every command.)
1525 * - There are certain sequences of commands that need to be issued to
1526 * the hardware sequentially, with no other intervening commands.
1527 *
1528 * This leads to an implementation of a "firmware lock" as a mutex that
1529 * can be taken recursively, and which is taken by both the low-level
1530 * command submission function (mwl8k_post_cmd) as well as any users of
1531 * that function that require issuing of an atomic sequence of commands,
1532 * and quiesces the transmit path whenever it's taken.
1533 */
1534 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1535 {
1536 struct mwl8k_priv *priv = hw->priv;
1537
1538 if (priv->fw_mutex_owner != current) {
1539 int rc;
1540
1541 mutex_lock(&priv->fw_mutex);
1542 ieee80211_stop_queues(hw);
1543
1544 rc = mwl8k_tx_wait_empty(hw);
1545 if (rc) {
1546 ieee80211_wake_queues(hw);
1547 mutex_unlock(&priv->fw_mutex);
1548
1549 return rc;
1550 }
1551
1552 priv->fw_mutex_owner = current;
1553 }
1554
1555 priv->fw_mutex_depth++;
1556
1557 return 0;
1558 }
1559
1560 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1561 {
1562 struct mwl8k_priv *priv = hw->priv;
1563
1564 if (!--priv->fw_mutex_depth) {
1565 ieee80211_wake_queues(hw);
1566 priv->fw_mutex_owner = NULL;
1567 mutex_unlock(&priv->fw_mutex);
1568 }
1569 }
1570
1571
1572 /*
1573 * Command processing.
1574 */
1575
1576 /* Timeout firmware commands after 2000ms */
1577 #define MWL8K_CMD_TIMEOUT_MS 2000
1578
1579 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1580 {
1581 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1582 struct mwl8k_priv *priv = hw->priv;
1583 void __iomem *regs = priv->regs;
1584 dma_addr_t dma_addr;
1585 unsigned int dma_size;
1586 int rc;
1587 unsigned long timeout = 0;
1588 u8 buf[32];
1589
1590 cmd->result = 0xffff;
1591 dma_size = le16_to_cpu(cmd->length);
1592 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1593 PCI_DMA_BIDIRECTIONAL);
1594 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1595 return -ENOMEM;
1596
1597 rc = mwl8k_fw_lock(hw);
1598 if (rc) {
1599 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1600 PCI_DMA_BIDIRECTIONAL);
1601 return rc;
1602 }
1603
1604 priv->hostcmd_wait = &cmd_wait;
1605 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1606 iowrite32(MWL8K_H2A_INT_DOORBELL,
1607 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1608 iowrite32(MWL8K_H2A_INT_DUMMY,
1609 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1610
1611 timeout = wait_for_completion_timeout(&cmd_wait,
1612 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1613
1614 priv->hostcmd_wait = NULL;
1615
1616 mwl8k_fw_unlock(hw);
1617
1618 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1619 PCI_DMA_BIDIRECTIONAL);
1620
1621 if (!timeout) {
1622 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1623 wiphy_name(hw->wiphy),
1624 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1625 MWL8K_CMD_TIMEOUT_MS);
1626 rc = -ETIMEDOUT;
1627 } else {
1628 rc = cmd->result ? -EINVAL : 0;
1629 if (rc)
1630 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1631 wiphy_name(hw->wiphy),
1632 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1633 le16_to_cpu(cmd->result));
1634 }
1635
1636 return rc;
1637 }
1638
1639 /*
1640 * CMD_GET_HW_SPEC (STA version).
1641 */
1642 struct mwl8k_cmd_get_hw_spec_sta {
1643 struct mwl8k_cmd_pkt header;
1644 __u8 hw_rev;
1645 __u8 host_interface;
1646 __le16 num_mcaddrs;
1647 __u8 perm_addr[ETH_ALEN];
1648 __le16 region_code;
1649 __le32 fw_rev;
1650 __le32 ps_cookie;
1651 __le32 caps;
1652 __u8 mcs_bitmap[16];
1653 __le32 rx_queue_ptr;
1654 __le32 num_tx_queues;
1655 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1656 __le32 caps2;
1657 __le32 num_tx_desc_per_queue;
1658 __le32 total_rxd;
1659 } __attribute__((packed));
1660
1661 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1662 {
1663 struct mwl8k_priv *priv = hw->priv;
1664 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1665 int rc;
1666 int i;
1667
1668 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1669 if (cmd == NULL)
1670 return -ENOMEM;
1671
1672 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1673 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1674
1675 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1676 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1677 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1678 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1679 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1680 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1681 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1682 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1683
1684 rc = mwl8k_post_cmd(hw, &cmd->header);
1685
1686 if (!rc) {
1687 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1688 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1689 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1690 priv->hw_rev = cmd->hw_rev;
1691 }
1692
1693 kfree(cmd);
1694 return rc;
1695 }
1696
1697 /*
1698 * CMD_GET_HW_SPEC (AP version).
1699 */
1700 struct mwl8k_cmd_get_hw_spec_ap {
1701 struct mwl8k_cmd_pkt header;
1702 __u8 hw_rev;
1703 __u8 host_interface;
1704 __le16 num_wcb;
1705 __le16 num_mcaddrs;
1706 __u8 perm_addr[ETH_ALEN];
1707 __le16 region_code;
1708 __le16 num_antenna;
1709 __le32 fw_rev;
1710 __le32 wcbbase0;
1711 __le32 rxwrptr;
1712 __le32 rxrdptr;
1713 __le32 ps_cookie;
1714 __le32 wcbbase1;
1715 __le32 wcbbase2;
1716 __le32 wcbbase3;
1717 } __attribute__((packed));
1718
1719 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1720 {
1721 struct mwl8k_priv *priv = hw->priv;
1722 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1723 int rc;
1724
1725 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1726 if (cmd == NULL)
1727 return -ENOMEM;
1728
1729 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1730 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1731
1732 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1733 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1734
1735 rc = mwl8k_post_cmd(hw, &cmd->header);
1736
1737 if (!rc) {
1738 int off;
1739
1740 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1741 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1742 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1743 priv->hw_rev = cmd->hw_rev;
1744
1745 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1746 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1747
1748 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1749 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1750
1751 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1752 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1753
1754 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1755 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1756
1757 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1758 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1759
1760 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1761 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1762 }
1763
1764 kfree(cmd);
1765 return rc;
1766 }
1767
1768 /*
1769 * CMD_SET_HW_SPEC.
1770 */
1771 struct mwl8k_cmd_set_hw_spec {
1772 struct mwl8k_cmd_pkt header;
1773 __u8 hw_rev;
1774 __u8 host_interface;
1775 __le16 num_mcaddrs;
1776 __u8 perm_addr[ETH_ALEN];
1777 __le16 region_code;
1778 __le32 fw_rev;
1779 __le32 ps_cookie;
1780 __le32 caps;
1781 __le32 rx_queue_ptr;
1782 __le32 num_tx_queues;
1783 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1784 __le32 flags;
1785 __le32 num_tx_desc_per_queue;
1786 __le32 total_rxd;
1787 } __attribute__((packed));
1788
1789 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1790
1791 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1792 {
1793 struct mwl8k_priv *priv = hw->priv;
1794 struct mwl8k_cmd_set_hw_spec *cmd;
1795 int rc;
1796 int i;
1797
1798 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1799 if (cmd == NULL)
1800 return -ENOMEM;
1801
1802 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1803 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1804
1805 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1806 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1807 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1808 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1809 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1810 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1811 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1812 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1813
1814 rc = mwl8k_post_cmd(hw, &cmd->header);
1815 kfree(cmd);
1816
1817 return rc;
1818 }
1819
1820 /*
1821 * CMD_MAC_MULTICAST_ADR.
1822 */
1823 struct mwl8k_cmd_mac_multicast_adr {
1824 struct mwl8k_cmd_pkt header;
1825 __le16 action;
1826 __le16 numaddr;
1827 __u8 addr[0][ETH_ALEN];
1828 };
1829
1830 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1831 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1832 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1833 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1834
1835 static struct mwl8k_cmd_pkt *
1836 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1837 int mc_count, struct dev_addr_list *mclist)
1838 {
1839 struct mwl8k_priv *priv = hw->priv;
1840 struct mwl8k_cmd_mac_multicast_adr *cmd;
1841 int size;
1842
1843 if (allmulti || mc_count > priv->num_mcaddrs) {
1844 allmulti = 1;
1845 mc_count = 0;
1846 }
1847
1848 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1849
1850 cmd = kzalloc(size, GFP_ATOMIC);
1851 if (cmd == NULL)
1852 return NULL;
1853
1854 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1855 cmd->header.length = cpu_to_le16(size);
1856 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1857 MWL8K_ENABLE_RX_BROADCAST);
1858
1859 if (allmulti) {
1860 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1861 } else if (mc_count) {
1862 int i;
1863
1864 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1865 cmd->numaddr = cpu_to_le16(mc_count);
1866 for (i = 0; i < mc_count && mclist; i++) {
1867 if (mclist->da_addrlen != ETH_ALEN) {
1868 kfree(cmd);
1869 return NULL;
1870 }
1871 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1872 mclist = mclist->next;
1873 }
1874 }
1875
1876 return &cmd->header;
1877 }
1878
1879 /*
1880 * CMD_802_11_GET_STAT.
1881 */
1882 struct mwl8k_cmd_802_11_get_stat {
1883 struct mwl8k_cmd_pkt header;
1884 __le32 stats[64];
1885 } __attribute__((packed));
1886
1887 #define MWL8K_STAT_ACK_FAILURE 9
1888 #define MWL8K_STAT_RTS_FAILURE 12
1889 #define MWL8K_STAT_FCS_ERROR 24
1890 #define MWL8K_STAT_RTS_SUCCESS 11
1891
1892 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1893 struct ieee80211_low_level_stats *stats)
1894 {
1895 struct mwl8k_cmd_802_11_get_stat *cmd;
1896 int rc;
1897
1898 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1899 if (cmd == NULL)
1900 return -ENOMEM;
1901
1902 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1903 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1904
1905 rc = mwl8k_post_cmd(hw, &cmd->header);
1906 if (!rc) {
1907 stats->dot11ACKFailureCount =
1908 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1909 stats->dot11RTSFailureCount =
1910 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1911 stats->dot11FCSErrorCount =
1912 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1913 stats->dot11RTSSuccessCount =
1914 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1915 }
1916 kfree(cmd);
1917
1918 return rc;
1919 }
1920
1921 /*
1922 * CMD_802_11_RADIO_CONTROL.
1923 */
1924 struct mwl8k_cmd_802_11_radio_control {
1925 struct mwl8k_cmd_pkt header;
1926 __le16 action;
1927 __le16 control;
1928 __le16 radio_on;
1929 } __attribute__((packed));
1930
1931 static int
1932 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1933 {
1934 struct mwl8k_priv *priv = hw->priv;
1935 struct mwl8k_cmd_802_11_radio_control *cmd;
1936 int rc;
1937
1938 if (enable == priv->radio_on && !force)
1939 return 0;
1940
1941 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1942 if (cmd == NULL)
1943 return -ENOMEM;
1944
1945 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1946 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1947 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1948 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1949 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1950
1951 rc = mwl8k_post_cmd(hw, &cmd->header);
1952 kfree(cmd);
1953
1954 if (!rc)
1955 priv->radio_on = enable;
1956
1957 return rc;
1958 }
1959
1960 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1961 {
1962 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1963 }
1964
1965 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1966 {
1967 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1968 }
1969
1970 static int
1971 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1972 {
1973 struct mwl8k_priv *priv;
1974
1975 if (hw == NULL || hw->priv == NULL)
1976 return -EINVAL;
1977 priv = hw->priv;
1978
1979 priv->radio_short_preamble = short_preamble;
1980
1981 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1982 }
1983
1984 /*
1985 * CMD_802_11_RF_TX_POWER.
1986 */
1987 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1988
1989 struct mwl8k_cmd_802_11_rf_tx_power {
1990 struct mwl8k_cmd_pkt header;
1991 __le16 action;
1992 __le16 support_level;
1993 __le16 current_level;
1994 __le16 reserved;
1995 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1996 } __attribute__((packed));
1997
1998 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1999 {
2000 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
2001 int rc;
2002
2003 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2004 if (cmd == NULL)
2005 return -ENOMEM;
2006
2007 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2008 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2009 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2010 cmd->support_level = cpu_to_le16(dBm);
2011
2012 rc = mwl8k_post_cmd(hw, &cmd->header);
2013 kfree(cmd);
2014
2015 return rc;
2016 }
2017
2018 /*
2019 * CMD_RF_ANTENNA.
2020 */
2021 struct mwl8k_cmd_rf_antenna {
2022 struct mwl8k_cmd_pkt header;
2023 __le16 antenna;
2024 __le16 mode;
2025 } __attribute__((packed));
2026
2027 #define MWL8K_RF_ANTENNA_RX 1
2028 #define MWL8K_RF_ANTENNA_TX 2
2029
2030 static int
2031 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2032 {
2033 struct mwl8k_cmd_rf_antenna *cmd;
2034 int rc;
2035
2036 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2037 if (cmd == NULL)
2038 return -ENOMEM;
2039
2040 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2041 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2042 cmd->antenna = cpu_to_le16(antenna);
2043 cmd->mode = cpu_to_le16(mask);
2044
2045 rc = mwl8k_post_cmd(hw, &cmd->header);
2046 kfree(cmd);
2047
2048 return rc;
2049 }
2050
2051 /*
2052 * CMD_SET_PRE_SCAN.
2053 */
2054 struct mwl8k_cmd_set_pre_scan {
2055 struct mwl8k_cmd_pkt header;
2056 } __attribute__((packed));
2057
2058 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2059 {
2060 struct mwl8k_cmd_set_pre_scan *cmd;
2061 int rc;
2062
2063 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2064 if (cmd == NULL)
2065 return -ENOMEM;
2066
2067 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2068 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2069
2070 rc = mwl8k_post_cmd(hw, &cmd->header);
2071 kfree(cmd);
2072
2073 return rc;
2074 }
2075
2076 /*
2077 * CMD_SET_POST_SCAN.
2078 */
2079 struct mwl8k_cmd_set_post_scan {
2080 struct mwl8k_cmd_pkt header;
2081 __le32 isibss;
2082 __u8 bssid[ETH_ALEN];
2083 } __attribute__((packed));
2084
2085 static int
2086 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2087 {
2088 struct mwl8k_cmd_set_post_scan *cmd;
2089 int rc;
2090
2091 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2092 if (cmd == NULL)
2093 return -ENOMEM;
2094
2095 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2096 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2097 cmd->isibss = 0;
2098 memcpy(cmd->bssid, mac, ETH_ALEN);
2099
2100 rc = mwl8k_post_cmd(hw, &cmd->header);
2101 kfree(cmd);
2102
2103 return rc;
2104 }
2105
2106 /*
2107 * CMD_SET_RF_CHANNEL.
2108 */
2109 struct mwl8k_cmd_set_rf_channel {
2110 struct mwl8k_cmd_pkt header;
2111 __le16 action;
2112 __u8 current_channel;
2113 __le32 channel_flags;
2114 } __attribute__((packed));
2115
2116 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2117 struct ieee80211_channel *channel)
2118 {
2119 struct mwl8k_cmd_set_rf_channel *cmd;
2120 int rc;
2121
2122 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2123 if (cmd == NULL)
2124 return -ENOMEM;
2125
2126 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2127 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2128 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2129 cmd->current_channel = channel->hw_value;
2130 if (channel->band == IEEE80211_BAND_2GHZ)
2131 cmd->channel_flags = cpu_to_le32(0x00000081);
2132 else
2133 cmd->channel_flags = cpu_to_le32(0x00000000);
2134
2135 rc = mwl8k_post_cmd(hw, &cmd->header);
2136 kfree(cmd);
2137
2138 return rc;
2139 }
2140
2141 /*
2142 * CMD_SET_SLOT.
2143 */
2144 struct mwl8k_cmd_set_slot {
2145 struct mwl8k_cmd_pkt header;
2146 __le16 action;
2147 __u8 short_slot;
2148 } __attribute__((packed));
2149
2150 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2151 {
2152 struct mwl8k_cmd_set_slot *cmd;
2153 int rc;
2154
2155 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2156 if (cmd == NULL)
2157 return -ENOMEM;
2158
2159 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2160 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2161 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2162 cmd->short_slot = short_slot_time;
2163
2164 rc = mwl8k_post_cmd(hw, &cmd->header);
2165 kfree(cmd);
2166
2167 return rc;
2168 }
2169
2170 /*
2171 * CMD_MIMO_CONFIG.
2172 */
2173 struct mwl8k_cmd_mimo_config {
2174 struct mwl8k_cmd_pkt header;
2175 __le32 action;
2176 __u8 rx_antenna_map;
2177 __u8 tx_antenna_map;
2178 } __attribute__((packed));
2179
2180 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2181 {
2182 struct mwl8k_cmd_mimo_config *cmd;
2183 int rc;
2184
2185 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2186 if (cmd == NULL)
2187 return -ENOMEM;
2188
2189 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2190 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2191 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2192 cmd->rx_antenna_map = rx;
2193 cmd->tx_antenna_map = tx;
2194
2195 rc = mwl8k_post_cmd(hw, &cmd->header);
2196 kfree(cmd);
2197
2198 return rc;
2199 }
2200
2201 /*
2202 * CMD_ENABLE_SNIFFER.
2203 */
2204 struct mwl8k_cmd_enable_sniffer {
2205 struct mwl8k_cmd_pkt header;
2206 __le32 action;
2207 } __attribute__((packed));
2208
2209 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2210 {
2211 struct mwl8k_cmd_enable_sniffer *cmd;
2212 int rc;
2213
2214 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2215 if (cmd == NULL)
2216 return -ENOMEM;
2217
2218 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2219 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2220 cmd->action = cpu_to_le32(!!enable);
2221
2222 rc = mwl8k_post_cmd(hw, &cmd->header);
2223 kfree(cmd);
2224
2225 return rc;
2226 }
2227
2228 /*
2229 * CMD_SET_MAC_ADDR.
2230 */
2231 struct mwl8k_cmd_set_mac_addr {
2232 struct mwl8k_cmd_pkt header;
2233 union {
2234 struct {
2235 __le16 mac_type;
2236 __u8 mac_addr[ETH_ALEN];
2237 } mbss;
2238 __u8 mac_addr[ETH_ALEN];
2239 };
2240 } __attribute__((packed));
2241
2242 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2243 {
2244 struct mwl8k_priv *priv = hw->priv;
2245 struct mwl8k_cmd_set_mac_addr *cmd;
2246 int rc;
2247
2248 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2249 if (cmd == NULL)
2250 return -ENOMEM;
2251
2252 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2253 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2254 if (priv->ap_fw) {
2255 cmd->mbss.mac_type = 0;
2256 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2257 } else {
2258 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2259 }
2260
2261 rc = mwl8k_post_cmd(hw, &cmd->header);
2262 kfree(cmd);
2263
2264 return rc;
2265 }
2266
2267
2268 /*
2269 * CMD_SET_RATEADAPT_MODE.
2270 */
2271 struct mwl8k_cmd_set_rate_adapt_mode {
2272 struct mwl8k_cmd_pkt header;
2273 __le16 action;
2274 __le16 mode;
2275 } __attribute__((packed));
2276
2277 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2278 {
2279 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2280 int rc;
2281
2282 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2283 if (cmd == NULL)
2284 return -ENOMEM;
2285
2286 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2287 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2288 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2289 cmd->mode = cpu_to_le16(mode);
2290
2291 rc = mwl8k_post_cmd(hw, &cmd->header);
2292 kfree(cmd);
2293
2294 return rc;
2295 }
2296
2297 /*
2298 * CMD_SET_WMM_MODE.
2299 */
2300 struct mwl8k_cmd_set_wmm {
2301 struct mwl8k_cmd_pkt header;
2302 __le16 action;
2303 } __attribute__((packed));
2304
2305 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2306 {
2307 struct mwl8k_priv *priv = hw->priv;
2308 struct mwl8k_cmd_set_wmm *cmd;
2309 int rc;
2310
2311 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2312 if (cmd == NULL)
2313 return -ENOMEM;
2314
2315 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2316 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2317 cmd->action = cpu_to_le16(!!enable);
2318
2319 rc = mwl8k_post_cmd(hw, &cmd->header);
2320 kfree(cmd);
2321
2322 if (!rc)
2323 priv->wmm_enabled = enable;
2324
2325 return rc;
2326 }
2327
2328 /*
2329 * CMD_SET_RTS_THRESHOLD.
2330 */
2331 struct mwl8k_cmd_rts_threshold {
2332 struct mwl8k_cmd_pkt header;
2333 __le16 action;
2334 __le16 threshold;
2335 } __attribute__((packed));
2336
2337 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2338 u16 action, u16 threshold)
2339 {
2340 struct mwl8k_cmd_rts_threshold *cmd;
2341 int rc;
2342
2343 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2344 if (cmd == NULL)
2345 return -ENOMEM;
2346
2347 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2348 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2349 cmd->action = cpu_to_le16(action);
2350 cmd->threshold = cpu_to_le16(threshold);
2351
2352 rc = mwl8k_post_cmd(hw, &cmd->header);
2353 kfree(cmd);
2354
2355 return rc;
2356 }
2357
2358 /*
2359 * CMD_SET_EDCA_PARAMS.
2360 */
2361 struct mwl8k_cmd_set_edca_params {
2362 struct mwl8k_cmd_pkt header;
2363
2364 /* See MWL8K_SET_EDCA_XXX below */
2365 __le16 action;
2366
2367 /* TX opportunity in units of 32 us */
2368 __le16 txop;
2369
2370 union {
2371 struct {
2372 /* Log exponent of max contention period: 0...15 */
2373 __le32 log_cw_max;
2374
2375 /* Log exponent of min contention period: 0...15 */
2376 __le32 log_cw_min;
2377
2378 /* Adaptive interframe spacing in units of 32us */
2379 __u8 aifs;
2380
2381 /* TX queue to configure */
2382 __u8 txq;
2383 } ap;
2384 struct {
2385 /* Log exponent of max contention period: 0...15 */
2386 __u8 log_cw_max;
2387
2388 /* Log exponent of min contention period: 0...15 */
2389 __u8 log_cw_min;
2390
2391 /* Adaptive interframe spacing in units of 32us */
2392 __u8 aifs;
2393
2394 /* TX queue to configure */
2395 __u8 txq;
2396 } sta;
2397 };
2398 } __attribute__((packed));
2399
2400 #define MWL8K_SET_EDCA_CW 0x01
2401 #define MWL8K_SET_EDCA_TXOP 0x02
2402 #define MWL8K_SET_EDCA_AIFS 0x04
2403
2404 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2405 MWL8K_SET_EDCA_TXOP | \
2406 MWL8K_SET_EDCA_AIFS)
2407
2408 static int
2409 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2410 __u16 cw_min, __u16 cw_max,
2411 __u8 aifs, __u16 txop)
2412 {
2413 struct mwl8k_priv *priv = hw->priv;
2414 struct mwl8k_cmd_set_edca_params *cmd;
2415 int rc;
2416
2417 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2418 if (cmd == NULL)
2419 return -ENOMEM;
2420
2421 /*
2422 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2423 * this call.
2424 */
2425 qnum ^= !(qnum >> 1);
2426
2427 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2428 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2429 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2430 cmd->txop = cpu_to_le16(txop);
2431 if (priv->ap_fw) {
2432 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2433 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2434 cmd->ap.aifs = aifs;
2435 cmd->ap.txq = qnum;
2436 } else {
2437 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2438 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2439 cmd->sta.aifs = aifs;
2440 cmd->sta.txq = qnum;
2441 }
2442
2443 rc = mwl8k_post_cmd(hw, &cmd->header);
2444 kfree(cmd);
2445
2446 return rc;
2447 }
2448
2449 /*
2450 * CMD_FINALIZE_JOIN.
2451 */
2452
2453 /* FJ beacon buffer size is compiled into the firmware. */
2454 #define MWL8K_FJ_BEACON_MAXLEN 128
2455
2456 struct mwl8k_cmd_finalize_join {
2457 struct mwl8k_cmd_pkt header;
2458 __le32 sleep_interval; /* Number of beacon periods to sleep */
2459 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2460 } __attribute__((packed));
2461
2462 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2463 __u16 framelen, __u16 dtim)
2464 {
2465 struct mwl8k_cmd_finalize_join *cmd;
2466 struct ieee80211_mgmt *payload = frame;
2467 u16 hdrlen;
2468 u32 payload_len;
2469 int rc;
2470
2471 if (frame == NULL)
2472 return -EINVAL;
2473
2474 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2475 if (cmd == NULL)
2476 return -ENOMEM;
2477
2478 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2479 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2480 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2481
2482 hdrlen = ieee80211_hdrlen(payload->frame_control);
2483
2484 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2485
2486 /* XXX TBD Might just have to abort and return an error */
2487 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2488 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2489 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2490 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2491
2492 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2493 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2494
2495 if (payload && payload_len)
2496 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2497
2498 rc = mwl8k_post_cmd(hw, &cmd->header);
2499 kfree(cmd);
2500 return rc;
2501 }
2502
2503 /*
2504 * CMD_UPDATE_STADB.
2505 */
2506 struct mwl8k_cmd_update_sta_db {
2507 struct mwl8k_cmd_pkt header;
2508
2509 /* See STADB_ACTION_TYPE */
2510 __le32 action;
2511
2512 /* Peer MAC address */
2513 __u8 peer_addr[ETH_ALEN];
2514
2515 __le32 reserved;
2516
2517 /* Peer info - valid during add/update. */
2518 struct peer_capability_info peer_info;
2519 } __attribute__((packed));
2520
2521 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2522 struct ieee80211_vif *vif, __u32 action)
2523 {
2524 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2525 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2526 struct mwl8k_cmd_update_sta_db *cmd;
2527 struct peer_capability_info *peer_info;
2528 int rc;
2529
2530 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2531 if (cmd == NULL)
2532 return -ENOMEM;
2533
2534 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2535 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2536
2537 cmd->action = cpu_to_le32(action);
2538 peer_info = &cmd->peer_info;
2539 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2540
2541 switch (action) {
2542 case MWL8K_STA_DB_ADD_ENTRY:
2543 case MWL8K_STA_DB_MODIFY_ENTRY:
2544 /* Build peer_info block */
2545 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2546 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2547 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2548 sizeof(mwl8k_rateids));
2549 peer_info->interop = 1;
2550 peer_info->amsdu_enabled = 0;
2551
2552 rc = mwl8k_post_cmd(hw, &cmd->header);
2553 if (rc == 0)
2554 mv_vif->peer_id = peer_info->station_id;
2555
2556 break;
2557
2558 case MWL8K_STA_DB_DEL_ENTRY:
2559 case MWL8K_STA_DB_FLUSH:
2560 default:
2561 rc = mwl8k_post_cmd(hw, &cmd->header);
2562 if (rc == 0)
2563 mv_vif->peer_id = 0;
2564 break;
2565 }
2566 kfree(cmd);
2567
2568 return rc;
2569 }
2570
2571 /*
2572 * CMD_SET_AID.
2573 */
2574 #define MWL8K_FRAME_PROT_DISABLED 0x00
2575 #define MWL8K_FRAME_PROT_11G 0x07
2576 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2577 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2578
2579 struct mwl8k_cmd_update_set_aid {
2580 struct mwl8k_cmd_pkt header;
2581 __le16 aid;
2582
2583 /* AP's MAC address (BSSID) */
2584 __u8 bssid[ETH_ALEN];
2585 __le16 protection_mode;
2586 __u8 supp_rates[14];
2587 } __attribute__((packed));
2588
2589 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2590 struct ieee80211_vif *vif)
2591 {
2592 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2593 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2594 struct mwl8k_cmd_update_set_aid *cmd;
2595 u16 prot_mode;
2596 int rc;
2597
2598 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2599 if (cmd == NULL)
2600 return -ENOMEM;
2601
2602 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2603 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2604 cmd->aid = cpu_to_le16(info->aid);
2605
2606 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2607
2608 if (info->use_cts_prot) {
2609 prot_mode = MWL8K_FRAME_PROT_11G;
2610 } else {
2611 switch (info->ht_operation_mode &
2612 IEEE80211_HT_OP_MODE_PROTECTION) {
2613 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2614 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2615 break;
2616 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2617 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2618 break;
2619 default:
2620 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2621 break;
2622 }
2623 }
2624 cmd->protection_mode = cpu_to_le16(prot_mode);
2625
2626 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2627
2628 rc = mwl8k_post_cmd(hw, &cmd->header);
2629 kfree(cmd);
2630
2631 return rc;
2632 }
2633
2634 /*
2635 * CMD_SET_RATE.
2636 */
2637 struct mwl8k_cmd_update_rateset {
2638 struct mwl8k_cmd_pkt header;
2639 __u8 legacy_rates[14];
2640
2641 /* Bitmap for supported MCS codes. */
2642 __u8 mcs_set[16];
2643 __u8 reserved[16];
2644 } __attribute__((packed));
2645
2646 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2647 struct ieee80211_vif *vif)
2648 {
2649 struct mwl8k_cmd_update_rateset *cmd;
2650 int rc;
2651
2652 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2653 if (cmd == NULL)
2654 return -ENOMEM;
2655
2656 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2657 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2658 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2659
2660 rc = mwl8k_post_cmd(hw, &cmd->header);
2661 kfree(cmd);
2662
2663 return rc;
2664 }
2665
2666 /*
2667 * CMD_USE_FIXED_RATE.
2668 */
2669 #define MWL8K_RATE_TABLE_SIZE 8
2670 #define MWL8K_UCAST_RATE 0
2671 #define MWL8K_USE_AUTO_RATE 0x0002
2672
2673 struct mwl8k_rate_entry {
2674 /* Set to 1 if HT rate, 0 if legacy. */
2675 __le32 is_ht_rate;
2676
2677 /* Set to 1 to use retry_count field. */
2678 __le32 enable_retry;
2679
2680 /* Specified legacy rate or MCS. */
2681 __le32 rate;
2682
2683 /* Number of allowed retries. */
2684 __le32 retry_count;
2685 } __attribute__((packed));
2686
2687 struct mwl8k_rate_table {
2688 /* 1 to allow specified rate and below */
2689 __le32 allow_rate_drop;
2690 __le32 num_rates;
2691 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2692 } __attribute__((packed));
2693
2694 struct mwl8k_cmd_use_fixed_rate {
2695 struct mwl8k_cmd_pkt header;
2696 __le32 action;
2697 struct mwl8k_rate_table rate_table;
2698
2699 /* Unicast, Broadcast or Multicast */
2700 __le32 rate_type;
2701 __le32 reserved1;
2702 __le32 reserved2;
2703 } __attribute__((packed));
2704
2705 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2706 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2707 {
2708 struct mwl8k_cmd_use_fixed_rate *cmd;
2709 int count;
2710 int rc;
2711
2712 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2713 if (cmd == NULL)
2714 return -ENOMEM;
2715
2716 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2717 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2718
2719 cmd->action = cpu_to_le32(action);
2720 cmd->rate_type = cpu_to_le32(rate_type);
2721
2722 if (rate_table != NULL) {
2723 /*
2724 * Copy over each field manually so that endian
2725 * conversion can be done.
2726 */
2727 cmd->rate_table.allow_rate_drop =
2728 cpu_to_le32(rate_table->allow_rate_drop);
2729 cmd->rate_table.num_rates =
2730 cpu_to_le32(rate_table->num_rates);
2731
2732 for (count = 0; count < rate_table->num_rates; count++) {
2733 struct mwl8k_rate_entry *dst =
2734 &cmd->rate_table.rate_entry[count];
2735 struct mwl8k_rate_entry *src =
2736 &rate_table->rate_entry[count];
2737
2738 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2739 dst->enable_retry = cpu_to_le32(src->enable_retry);
2740 dst->rate = cpu_to_le32(src->rate);
2741 dst->retry_count = cpu_to_le32(src->retry_count);
2742 }
2743 }
2744
2745 rc = mwl8k_post_cmd(hw, &cmd->header);
2746 kfree(cmd);
2747
2748 return rc;
2749 }
2750
2751
2752 /*
2753 * Interrupt handling.
2754 */
2755 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2756 {
2757 struct ieee80211_hw *hw = dev_id;
2758 struct mwl8k_priv *priv = hw->priv;
2759 u32 status;
2760
2761 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2762 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2763
2764 if (!status)
2765 return IRQ_NONE;
2766
2767 if (status & MWL8K_A2H_INT_TX_DONE)
2768 tasklet_schedule(&priv->tx_reclaim_task);
2769
2770 if (status & MWL8K_A2H_INT_RX_READY) {
2771 while (rxq_process(hw, 0, 1))
2772 rxq_refill(hw, 0, 1);
2773 }
2774
2775 if (status & MWL8K_A2H_INT_OPC_DONE) {
2776 if (priv->hostcmd_wait != NULL)
2777 complete(priv->hostcmd_wait);
2778 }
2779
2780 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2781 if (!mutex_is_locked(&priv->fw_mutex) &&
2782 priv->radio_on && priv->pending_tx_pkts)
2783 mwl8k_tx_start(priv);
2784 }
2785
2786 return IRQ_HANDLED;
2787 }
2788
2789
2790 /*
2791 * Core driver operations.
2792 */
2793 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2794 {
2795 struct mwl8k_priv *priv = hw->priv;
2796 int index = skb_get_queue_mapping(skb);
2797 int rc;
2798
2799 if (priv->current_channel == NULL) {
2800 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2801 "disabled\n", wiphy_name(hw->wiphy));
2802 dev_kfree_skb(skb);
2803 return NETDEV_TX_OK;
2804 }
2805
2806 rc = mwl8k_txq_xmit(hw, index, skb);
2807
2808 return rc;
2809 }
2810
2811 static int mwl8k_start(struct ieee80211_hw *hw)
2812 {
2813 struct mwl8k_priv *priv = hw->priv;
2814 int rc;
2815
2816 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2817 IRQF_SHARED, MWL8K_NAME, hw);
2818 if (rc) {
2819 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2820 wiphy_name(hw->wiphy));
2821 return -EIO;
2822 }
2823
2824 /* Enable tx reclaim tasklet */
2825 tasklet_enable(&priv->tx_reclaim_task);
2826
2827 /* Enable interrupts */
2828 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2829
2830 rc = mwl8k_fw_lock(hw);
2831 if (!rc) {
2832 rc = mwl8k_cmd_802_11_radio_enable(hw);
2833
2834 if (!priv->ap_fw) {
2835 if (!rc)
2836 rc = mwl8k_enable_sniffer(hw, 0);
2837
2838 if (!rc)
2839 rc = mwl8k_cmd_set_pre_scan(hw);
2840
2841 if (!rc)
2842 rc = mwl8k_cmd_set_post_scan(hw,
2843 "\x00\x00\x00\x00\x00\x00");
2844 }
2845
2846 if (!rc)
2847 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2848
2849 if (!rc)
2850 rc = mwl8k_set_wmm(hw, 0);
2851
2852 mwl8k_fw_unlock(hw);
2853 }
2854
2855 if (rc) {
2856 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2857 free_irq(priv->pdev->irq, hw);
2858 tasklet_disable(&priv->tx_reclaim_task);
2859 }
2860
2861 return rc;
2862 }
2863
2864 static void mwl8k_stop(struct ieee80211_hw *hw)
2865 {
2866 struct mwl8k_priv *priv = hw->priv;
2867 int i;
2868
2869 mwl8k_cmd_802_11_radio_disable(hw);
2870
2871 ieee80211_stop_queues(hw);
2872
2873 /* Disable interrupts */
2874 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2875 free_irq(priv->pdev->irq, hw);
2876
2877 /* Stop finalize join worker */
2878 cancel_work_sync(&priv->finalize_join_worker);
2879 if (priv->beacon_skb != NULL)
2880 dev_kfree_skb(priv->beacon_skb);
2881
2882 /* Stop tx reclaim tasklet */
2883 tasklet_disable(&priv->tx_reclaim_task);
2884
2885 /* Return all skbs to mac80211 */
2886 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2887 mwl8k_txq_reclaim(hw, i, 1);
2888 }
2889
2890 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2891 struct ieee80211_if_init_conf *conf)
2892 {
2893 struct mwl8k_priv *priv = hw->priv;
2894 struct mwl8k_vif *mwl8k_vif;
2895
2896 /*
2897 * We only support one active interface at a time.
2898 */
2899 if (priv->vif != NULL)
2900 return -EBUSY;
2901
2902 /*
2903 * We only support managed interfaces for now.
2904 */
2905 if (conf->type != NL80211_IFTYPE_STATION)
2906 return -EINVAL;
2907
2908 /*
2909 * Reject interface creation if sniffer mode is active, as
2910 * STA operation is mutually exclusive with hardware sniffer
2911 * mode.
2912 */
2913 if (priv->sniffer_enabled) {
2914 printk(KERN_INFO "%s: unable to create STA "
2915 "interface due to sniffer mode being enabled\n",
2916 wiphy_name(hw->wiphy));
2917 return -EINVAL;
2918 }
2919
2920 /* Clean out driver private area */
2921 mwl8k_vif = MWL8K_VIF(conf->vif);
2922 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2923
2924 /* Set and save the mac address */
2925 mwl8k_set_mac_addr(hw, conf->mac_addr);
2926 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2927
2928 /* Back pointer to parent config block */
2929 mwl8k_vif->priv = priv;
2930
2931 /* Set Initial sequence number to zero */
2932 mwl8k_vif->seqno = 0;
2933
2934 priv->vif = conf->vif;
2935 priv->current_channel = NULL;
2936
2937 return 0;
2938 }
2939
2940 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2941 struct ieee80211_if_init_conf *conf)
2942 {
2943 struct mwl8k_priv *priv = hw->priv;
2944
2945 if (priv->vif == NULL)
2946 return;
2947
2948 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2949
2950 priv->vif = NULL;
2951 }
2952
2953 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2954 {
2955 struct ieee80211_conf *conf = &hw->conf;
2956 struct mwl8k_priv *priv = hw->priv;
2957 int rc;
2958
2959 if (conf->flags & IEEE80211_CONF_IDLE) {
2960 mwl8k_cmd_802_11_radio_disable(hw);
2961 priv->current_channel = NULL;
2962 return 0;
2963 }
2964
2965 rc = mwl8k_fw_lock(hw);
2966 if (rc)
2967 return rc;
2968
2969 rc = mwl8k_cmd_802_11_radio_enable(hw);
2970 if (rc)
2971 goto out;
2972
2973 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2974 if (rc)
2975 goto out;
2976
2977 priv->current_channel = conf->channel;
2978
2979 if (conf->power_level > 18)
2980 conf->power_level = 18;
2981 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2982 if (rc)
2983 goto out;
2984
2985 if (priv->ap_fw) {
2986 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2987 if (!rc)
2988 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2989 } else {
2990 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2991 }
2992
2993 out:
2994 mwl8k_fw_unlock(hw);
2995
2996 return rc;
2997 }
2998
2999 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3000 struct ieee80211_vif *vif,
3001 struct ieee80211_bss_conf *info,
3002 u32 changed)
3003 {
3004 struct mwl8k_priv *priv = hw->priv;
3005 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3006 int rc;
3007
3008 if (changed & BSS_CHANGED_BSSID)
3009 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3010
3011 if ((changed & BSS_CHANGED_ASSOC) == 0)
3012 return;
3013
3014 priv->capture_beacon = false;
3015
3016 rc = mwl8k_fw_lock(hw);
3017 if (rc)
3018 return;
3019
3020 if (info->assoc) {
3021 memcpy(&mwl8k_vif->bss_info, info,
3022 sizeof(struct ieee80211_bss_conf));
3023
3024 /* Install rates */
3025 rc = mwl8k_update_rateset(hw, vif);
3026 if (rc)
3027 goto out;
3028
3029 /* Turn on rate adaptation */
3030 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3031 MWL8K_UCAST_RATE, NULL);
3032 if (rc)
3033 goto out;
3034
3035 /* Set radio preamble */
3036 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3037 if (rc)
3038 goto out;
3039
3040 /* Set slot time */
3041 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3042 if (rc)
3043 goto out;
3044
3045 /* Update peer rate info */
3046 rc = mwl8k_cmd_update_sta_db(hw, vif,
3047 MWL8K_STA_DB_MODIFY_ENTRY);
3048 if (rc)
3049 goto out;
3050
3051 /* Set AID */
3052 rc = mwl8k_cmd_set_aid(hw, vif);
3053 if (rc)
3054 goto out;
3055
3056 /*
3057 * Finalize the join. Tell rx handler to process
3058 * next beacon from our BSSID.
3059 */
3060 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3061 priv->capture_beacon = true;
3062 } else {
3063 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3064 memset(&mwl8k_vif->bss_info, 0,
3065 sizeof(struct ieee80211_bss_conf));
3066 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3067 }
3068
3069 out:
3070 mwl8k_fw_unlock(hw);
3071 }
3072
3073 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3074 int mc_count, struct dev_addr_list *mclist)
3075 {
3076 struct mwl8k_cmd_pkt *cmd;
3077
3078 /*
3079 * Synthesize and return a command packet that programs the
3080 * hardware multicast address filter. At this point we don't
3081 * know whether FIF_ALLMULTI is being requested, but if it is,
3082 * we'll end up throwing this packet away and creating a new
3083 * one in mwl8k_configure_filter().
3084 */
3085 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3086
3087 return (unsigned long)cmd;
3088 }
3089
3090 static int
3091 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3092 unsigned int changed_flags,
3093 unsigned int *total_flags)
3094 {
3095 struct mwl8k_priv *priv = hw->priv;
3096
3097 /*
3098 * Hardware sniffer mode is mutually exclusive with STA
3099 * operation, so refuse to enable sniffer mode if a STA
3100 * interface is active.
3101 */
3102 if (priv->vif != NULL) {
3103 if (net_ratelimit())
3104 printk(KERN_INFO "%s: not enabling sniffer "
3105 "mode because STA interface is active\n",
3106 wiphy_name(hw->wiphy));
3107 return 0;
3108 }
3109
3110 if (!priv->sniffer_enabled) {
3111 if (mwl8k_enable_sniffer(hw, 1))
3112 return 0;
3113 priv->sniffer_enabled = true;
3114 }
3115
3116 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3117 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3118 FIF_OTHER_BSS;
3119
3120 return 1;
3121 }
3122
3123 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3124 unsigned int changed_flags,
3125 unsigned int *total_flags,
3126 u64 multicast)
3127 {
3128 struct mwl8k_priv *priv = hw->priv;
3129 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3130
3131 /*
3132 * AP firmware doesn't allow fine-grained control over
3133 * the receive filter.
3134 */
3135 if (priv->ap_fw) {
3136 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3137 kfree(cmd);
3138 return;
3139 }
3140
3141 /*
3142 * Enable hardware sniffer mode if FIF_CONTROL or
3143 * FIF_OTHER_BSS is requested.
3144 */
3145 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3146 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3147 kfree(cmd);
3148 return;
3149 }
3150
3151 /* Clear unsupported feature flags */
3152 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3153
3154 if (mwl8k_fw_lock(hw))
3155 return;
3156
3157 if (priv->sniffer_enabled) {
3158 mwl8k_enable_sniffer(hw, 0);
3159 priv->sniffer_enabled = false;
3160 }
3161
3162 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3163 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3164 /*
3165 * Disable the BSS filter.
3166 */
3167 mwl8k_cmd_set_pre_scan(hw);
3168 } else {
3169 u8 *bssid;
3170
3171 /*
3172 * Enable the BSS filter.
3173 *
3174 * If there is an active STA interface, use that
3175 * interface's BSSID, otherwise use a dummy one
3176 * (where the OUI part needs to be nonzero for
3177 * the BSSID to be accepted by POST_SCAN).
3178 */
3179 bssid = "\x01\x00\x00\x00\x00\x00";
3180 if (priv->vif != NULL)
3181 bssid = MWL8K_VIF(priv->vif)->bssid;
3182
3183 mwl8k_cmd_set_post_scan(hw, bssid);
3184 }
3185 }
3186
3187 /*
3188 * If FIF_ALLMULTI is being requested, throw away the command
3189 * packet that ->prepare_multicast() built and replace it with
3190 * a command packet that enables reception of all multicast
3191 * packets.
3192 */
3193 if (*total_flags & FIF_ALLMULTI) {
3194 kfree(cmd);
3195 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3196 }
3197
3198 if (cmd != NULL) {
3199 mwl8k_post_cmd(hw, cmd);
3200 kfree(cmd);
3201 }
3202
3203 mwl8k_fw_unlock(hw);
3204 }
3205
3206 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3207 {
3208 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
3209 }
3210
3211 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3212 const struct ieee80211_tx_queue_params *params)
3213 {
3214 struct mwl8k_priv *priv = hw->priv;
3215 int rc;
3216
3217 rc = mwl8k_fw_lock(hw);
3218 if (!rc) {
3219 if (!priv->wmm_enabled)
3220 rc = mwl8k_set_wmm(hw, 1);
3221
3222 if (!rc)
3223 rc = mwl8k_set_edca_params(hw, queue,
3224 params->cw_min,
3225 params->cw_max,
3226 params->aifs,
3227 params->txop);
3228
3229 mwl8k_fw_unlock(hw);
3230 }
3231
3232 return rc;
3233 }
3234
3235 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3236 struct ieee80211_tx_queue_stats *stats)
3237 {
3238 struct mwl8k_priv *priv = hw->priv;
3239 struct mwl8k_tx_queue *txq;
3240 int index;
3241
3242 spin_lock_bh(&priv->tx_lock);
3243 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3244 txq = priv->txq + index;
3245 memcpy(&stats[index], &txq->stats,
3246 sizeof(struct ieee80211_tx_queue_stats));
3247 }
3248 spin_unlock_bh(&priv->tx_lock);
3249
3250 return 0;
3251 }
3252
3253 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3254 struct ieee80211_low_level_stats *stats)
3255 {
3256 return mwl8k_cmd_802_11_get_stat(hw, stats);
3257 }
3258
3259 static const struct ieee80211_ops mwl8k_ops = {
3260 .tx = mwl8k_tx,
3261 .start = mwl8k_start,
3262 .stop = mwl8k_stop,
3263 .add_interface = mwl8k_add_interface,
3264 .remove_interface = mwl8k_remove_interface,
3265 .config = mwl8k_config,
3266 .bss_info_changed = mwl8k_bss_info_changed,
3267 .prepare_multicast = mwl8k_prepare_multicast,
3268 .configure_filter = mwl8k_configure_filter,
3269 .set_rts_threshold = mwl8k_set_rts_threshold,
3270 .conf_tx = mwl8k_conf_tx,
3271 .get_tx_stats = mwl8k_get_tx_stats,
3272 .get_stats = mwl8k_get_stats,
3273 };
3274
3275 static void mwl8k_tx_reclaim_handler(unsigned long data)
3276 {
3277 int i;
3278 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3279 struct mwl8k_priv *priv = hw->priv;
3280
3281 spin_lock_bh(&priv->tx_lock);
3282 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3283 mwl8k_txq_reclaim(hw, i, 0);
3284
3285 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3286 complete(priv->tx_wait);
3287 priv->tx_wait = NULL;
3288 }
3289 spin_unlock_bh(&priv->tx_lock);
3290 }
3291
3292 static void mwl8k_finalize_join_worker(struct work_struct *work)
3293 {
3294 struct mwl8k_priv *priv =
3295 container_of(work, struct mwl8k_priv, finalize_join_worker);
3296 struct sk_buff *skb = priv->beacon_skb;
3297 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3298
3299 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3300 dev_kfree_skb(skb);
3301
3302 priv->beacon_skb = NULL;
3303 }
3304
3305 enum {
3306 MWL8687 = 0,
3307 MWL8366,
3308 };
3309
3310 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3311 {
3312 .part_name = "88w8687",
3313 .helper_image = "mwl8k/helper_8687.fw",
3314 .fw_image = "mwl8k/fmimage_8687.fw",
3315 .rxd_ops = &rxd_8687_ops,
3316 .modes = BIT(NL80211_IFTYPE_STATION),
3317 },
3318 {
3319 .part_name = "88w8366",
3320 .helper_image = "mwl8k/helper_8366.fw",
3321 .fw_image = "mwl8k/fmimage_8366.fw",
3322 .rxd_ops = &rxd_8366_ops,
3323 .modes = 0,
3324 },
3325 };
3326
3327 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3328 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3329 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3330 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3331 { },
3332 };
3333 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3334
3335 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3336 const struct pci_device_id *id)
3337 {
3338 static int printed_version = 0;
3339 struct ieee80211_hw *hw;
3340 struct mwl8k_priv *priv;
3341 int rc;
3342 int i;
3343
3344 if (!printed_version) {
3345 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3346 printed_version = 1;
3347 }
3348
3349 rc = pci_enable_device(pdev);
3350 if (rc) {
3351 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3352 MWL8K_NAME);
3353 return rc;
3354 }
3355
3356 rc = pci_request_regions(pdev, MWL8K_NAME);
3357 if (rc) {
3358 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3359 MWL8K_NAME);
3360 return rc;
3361 }
3362
3363 pci_set_master(pdev);
3364
3365 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3366 if (hw == NULL) {
3367 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3368 rc = -ENOMEM;
3369 goto err_free_reg;
3370 }
3371
3372 priv = hw->priv;
3373 priv->hw = hw;
3374 priv->pdev = pdev;
3375 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3376 priv->rxd_ops = priv->device_info->rxd_ops;
3377 priv->sniffer_enabled = false;
3378 priv->wmm_enabled = false;
3379 priv->pending_tx_pkts = 0;
3380
3381 SET_IEEE80211_DEV(hw, &pdev->dev);
3382 pci_set_drvdata(pdev, hw);
3383
3384 priv->sram = pci_iomap(pdev, 0, 0x10000);
3385 if (priv->sram == NULL) {
3386 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3387 wiphy_name(hw->wiphy));
3388 goto err_iounmap;
3389 }
3390
3391 /*
3392 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3393 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3394 */
3395 priv->regs = pci_iomap(pdev, 1, 0x10000);
3396 if (priv->regs == NULL) {
3397 priv->regs = pci_iomap(pdev, 2, 0x10000);
3398 if (priv->regs == NULL) {
3399 printk(KERN_ERR "%s: Cannot map device registers\n",
3400 wiphy_name(hw->wiphy));
3401 goto err_iounmap;
3402 }
3403 }
3404
3405 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3406 priv->band.band = IEEE80211_BAND_2GHZ;
3407 priv->band.channels = priv->channels;
3408 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3409 priv->band.bitrates = priv->rates;
3410 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3411 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3412
3413 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3414 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3415
3416 /*
3417 * Extra headroom is the size of the required DMA header
3418 * minus the size of the smallest 802.11 frame (CTS frame).
3419 */
3420 hw->extra_tx_headroom =
3421 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3422
3423 hw->channel_change_time = 10;
3424
3425 hw->queues = MWL8K_TX_QUEUES;
3426
3427 hw->wiphy->interface_modes = priv->device_info->modes;
3428
3429 /* Set rssi and noise values to dBm */
3430 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3431 hw->vif_data_size = sizeof(struct mwl8k_vif);
3432 priv->vif = NULL;
3433
3434 /* Set default radio state and preamble */
3435 priv->radio_on = 0;
3436 priv->radio_short_preamble = 0;
3437
3438 /* Finalize join worker */
3439 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3440
3441 /* TX reclaim tasklet */
3442 tasklet_init(&priv->tx_reclaim_task,
3443 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3444 tasklet_disable(&priv->tx_reclaim_task);
3445
3446 /* Power management cookie */
3447 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3448 if (priv->cookie == NULL)
3449 goto err_iounmap;
3450
3451 rc = mwl8k_rxq_init(hw, 0);
3452 if (rc)
3453 goto err_iounmap;
3454 rxq_refill(hw, 0, INT_MAX);
3455
3456 mutex_init(&priv->fw_mutex);
3457 priv->fw_mutex_owner = NULL;
3458 priv->fw_mutex_depth = 0;
3459 priv->hostcmd_wait = NULL;
3460
3461 spin_lock_init(&priv->tx_lock);
3462
3463 priv->tx_wait = NULL;
3464
3465 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3466 rc = mwl8k_txq_init(hw, i);
3467 if (rc)
3468 goto err_free_queues;
3469 }
3470
3471 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3472 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3473 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3474 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3475
3476 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3477 IRQF_SHARED, MWL8K_NAME, hw);
3478 if (rc) {
3479 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3480 wiphy_name(hw->wiphy));
3481 goto err_free_queues;
3482 }
3483
3484 /* Reset firmware and hardware */
3485 mwl8k_hw_reset(priv);
3486
3487 /* Ask userland hotplug daemon for the device firmware */
3488 rc = mwl8k_request_firmware(priv);
3489 if (rc) {
3490 printk(KERN_ERR "%s: Firmware files not found\n",
3491 wiphy_name(hw->wiphy));
3492 goto err_free_irq;
3493 }
3494
3495 /* Load firmware into hardware */
3496 rc = mwl8k_load_firmware(hw);
3497 if (rc) {
3498 printk(KERN_ERR "%s: Cannot start firmware\n",
3499 wiphy_name(hw->wiphy));
3500 goto err_stop_firmware;
3501 }
3502
3503 /* Reclaim memory once firmware is successfully loaded */
3504 mwl8k_release_firmware(priv);
3505
3506 /*
3507 * Temporarily enable interrupts. Initial firmware host
3508 * commands use interrupts and avoids polling. Disable
3509 * interrupts when done.
3510 */
3511 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3512
3513 /* Get config data, mac addrs etc */
3514 if (priv->ap_fw) {
3515 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3516 if (!rc)
3517 rc = mwl8k_cmd_set_hw_spec(hw);
3518 } else {
3519 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3520 }
3521 if (rc) {
3522 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3523 wiphy_name(hw->wiphy));
3524 goto err_stop_firmware;
3525 }
3526
3527 /* Turn radio off */
3528 rc = mwl8k_cmd_802_11_radio_disable(hw);
3529 if (rc) {
3530 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3531 goto err_stop_firmware;
3532 }
3533
3534 /* Clear MAC address */
3535 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3536 if (rc) {
3537 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3538 wiphy_name(hw->wiphy));
3539 goto err_stop_firmware;
3540 }
3541
3542 /* Disable interrupts */
3543 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3544 free_irq(priv->pdev->irq, hw);
3545
3546 rc = ieee80211_register_hw(hw);
3547 if (rc) {
3548 printk(KERN_ERR "%s: Cannot register device\n",
3549 wiphy_name(hw->wiphy));
3550 goto err_stop_firmware;
3551 }
3552
3553 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3554 wiphy_name(hw->wiphy), priv->device_info->part_name,
3555 priv->hw_rev, hw->wiphy->perm_addr,
3556 priv->ap_fw ? "AP" : "STA",
3557 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3558 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3559
3560 return 0;
3561
3562 err_stop_firmware:
3563 mwl8k_hw_reset(priv);
3564 mwl8k_release_firmware(priv);
3565
3566 err_free_irq:
3567 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3568 free_irq(priv->pdev->irq, hw);
3569
3570 err_free_queues:
3571 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3572 mwl8k_txq_deinit(hw, i);
3573 mwl8k_rxq_deinit(hw, 0);
3574
3575 err_iounmap:
3576 if (priv->cookie != NULL)
3577 pci_free_consistent(priv->pdev, 4,
3578 priv->cookie, priv->cookie_dma);
3579
3580 if (priv->regs != NULL)
3581 pci_iounmap(pdev, priv->regs);
3582
3583 if (priv->sram != NULL)
3584 pci_iounmap(pdev, priv->sram);
3585
3586 pci_set_drvdata(pdev, NULL);
3587 ieee80211_free_hw(hw);
3588
3589 err_free_reg:
3590 pci_release_regions(pdev);
3591 pci_disable_device(pdev);
3592
3593 return rc;
3594 }
3595
3596 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3597 {
3598 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3599 }
3600
3601 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3602 {
3603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3604 struct mwl8k_priv *priv;
3605 int i;
3606
3607 if (hw == NULL)
3608 return;
3609 priv = hw->priv;
3610
3611 ieee80211_stop_queues(hw);
3612
3613 ieee80211_unregister_hw(hw);
3614
3615 /* Remove tx reclaim tasklet */
3616 tasklet_kill(&priv->tx_reclaim_task);
3617
3618 /* Stop hardware */
3619 mwl8k_hw_reset(priv);
3620
3621 /* Return all skbs to mac80211 */
3622 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3623 mwl8k_txq_reclaim(hw, i, 1);
3624
3625 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3626 mwl8k_txq_deinit(hw, i);
3627
3628 mwl8k_rxq_deinit(hw, 0);
3629
3630 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3631
3632 pci_iounmap(pdev, priv->regs);
3633 pci_iounmap(pdev, priv->sram);
3634 pci_set_drvdata(pdev, NULL);
3635 ieee80211_free_hw(hw);
3636 pci_release_regions(pdev);
3637 pci_disable_device(pdev);
3638 }
3639
3640 static struct pci_driver mwl8k_driver = {
3641 .name = MWL8K_NAME,
3642 .id_table = mwl8k_pci_id_table,
3643 .probe = mwl8k_probe,
3644 .remove = __devexit_p(mwl8k_remove),
3645 .shutdown = __devexit_p(mwl8k_shutdown),
3646 };
3647
3648 static int __init mwl8k_init(void)
3649 {
3650 return pci_register_driver(&mwl8k_driver);
3651 }
3652
3653 static void __exit mwl8k_exit(void)
3654 {
3655 pci_unregister_driver(&mwl8k_driver);
3656 }
3657
3658 module_init(mwl8k_init);
3659 module_exit(mwl8k_exit);
3660
3661 MODULE_DESCRIPTION(MWL8K_DESC);
3662 MODULE_VERSION(MWL8K_VERSION);
3663 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3664 MODULE_LICENSE("GPL");
Motorola kernel-slsi