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[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
51
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
68
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
82
83 struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88 };
89
90 struct mwl8k_device_info {
91 char *part_name;
92 char *helper_image;
93 char *fw_image;
94 struct rxd_ops *rxd_ops;
95 u16 modes;
96 };
97
98 struct mwl8k_rx_queue {
99 int rxd_count;
100
101 /* hw receives here */
102 int head;
103
104 /* refill descs here */
105 int tail;
106
107 void *rxd;
108 dma_addr_t rxd_dma;
109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
113 };
114
115 struct mwl8k_tx_queue {
116 /* hw transmits here */
117 int head;
118
119 /* sw appends here */
120 int tail;
121
122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
126 };
127
128 /* Pointers to the firmware data and meta information about it. */
129 struct mwl8k_firmware {
130 /* Boot helper code */
131 struct firmware *helper;
132
133 /* Microcode */
134 struct firmware *ucode;
135 };
136
137 struct mwl8k_priv {
138 void __iomem *sram;
139 void __iomem *regs;
140 struct ieee80211_hw *hw;
141
142 struct pci_dev *pdev;
143
144 struct mwl8k_device_info *device_info;
145 bool ap_fw;
146 struct rxd_ops *rxd_ops;
147
148 /* firmware files and meta data */
149 struct mwl8k_firmware fw;
150
151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
155 struct completion *hostcmd_wait;
156
157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
159
160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
163 struct ieee80211_vif *vif;
164
165 struct ieee80211_channel *current_channel;
166
167 /* power management status cookie from firmware */
168 u32 *cookie;
169 dma_addr_t cookie_dma;
170
171 u16 num_mcaddrs;
172 u8 hw_rev;
173 u32 fw_rev;
174
175 /*
176 * Running count of TX packets in flight, to avoid
177 * iterating over the transmit rings each time.
178 */
179 int pending_tx_pkts;
180
181 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
182 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
183
184 /* PHY parameters */
185 struct ieee80211_supported_band band;
186 struct ieee80211_channel channels[14];
187 struct ieee80211_rate rates[13];
188
189 bool radio_on;
190 bool radio_short_preamble;
191 bool sniffer_enabled;
192 bool wmm_enabled;
193
194 /* XXX need to convert this to handle multiple interfaces */
195 bool capture_beacon;
196 u8 capture_bssid[ETH_ALEN];
197 struct sk_buff *beacon_skb;
198
199 /*
200 * This FJ worker has to be global as it is scheduled from the
201 * RX handler. At this point we don't know which interface it
202 * belongs to until the list of bssids waiting to complete join
203 * is checked.
204 */
205 struct work_struct finalize_join_worker;
206
207 /* Tasklet to reclaim TX descriptors and buffers after tx */
208 struct tasklet_struct tx_reclaim_task;
209 };
210
211 /* Per interface specific private data */
212 struct mwl8k_vif {
213 /* backpointer to parent config block */
214 struct mwl8k_priv *priv;
215
216 /* BSS config of AP or IBSS from mac80211*/
217 struct ieee80211_bss_conf bss_info;
218
219 /* BSSID of AP or IBSS */
220 u8 bssid[ETH_ALEN];
221 u8 mac_addr[ETH_ALEN];
222
223 /*
224 * Subset of supported legacy rates.
225 * Intersection of AP and STA supported rates.
226 */
227 struct ieee80211_rate legacy_rates[13];
228
229 /* number of supported legacy rates */
230 u8 legacy_nrates;
231
232 /* Index into station database.Returned by update_sta_db call */
233 u8 peer_id;
234
235 /* Non AMPDU sequence number assigned by driver */
236 u16 seqno;
237 };
238
239 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
240
241 static const struct ieee80211_channel mwl8k_channels[] = {
242 { .center_freq = 2412, .hw_value = 1, },
243 { .center_freq = 2417, .hw_value = 2, },
244 { .center_freq = 2422, .hw_value = 3, },
245 { .center_freq = 2427, .hw_value = 4, },
246 { .center_freq = 2432, .hw_value = 5, },
247 { .center_freq = 2437, .hw_value = 6, },
248 { .center_freq = 2442, .hw_value = 7, },
249 { .center_freq = 2447, .hw_value = 8, },
250 { .center_freq = 2452, .hw_value = 9, },
251 { .center_freq = 2457, .hw_value = 10, },
252 { .center_freq = 2462, .hw_value = 11, },
253 };
254
255 static const struct ieee80211_rate mwl8k_rates[] = {
256 { .bitrate = 10, .hw_value = 2, },
257 { .bitrate = 20, .hw_value = 4, },
258 { .bitrate = 55, .hw_value = 11, },
259 { .bitrate = 110, .hw_value = 22, },
260 { .bitrate = 220, .hw_value = 44, },
261 { .bitrate = 60, .hw_value = 12, },
262 { .bitrate = 90, .hw_value = 18, },
263 { .bitrate = 120, .hw_value = 24, },
264 { .bitrate = 180, .hw_value = 36, },
265 { .bitrate = 240, .hw_value = 48, },
266 { .bitrate = 360, .hw_value = 72, },
267 { .bitrate = 480, .hw_value = 96, },
268 { .bitrate = 540, .hw_value = 108, },
269 };
270
271 /* Set or get info from Firmware */
272 #define MWL8K_CMD_SET 0x0001
273 #define MWL8K_CMD_GET 0x0000
274
275 /* Firmware command codes */
276 #define MWL8K_CMD_CODE_DNLD 0x0001
277 #define MWL8K_CMD_GET_HW_SPEC 0x0003
278 #define MWL8K_CMD_SET_HW_SPEC 0x0004
279 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
280 #define MWL8K_CMD_GET_STAT 0x0014
281 #define MWL8K_CMD_RADIO_CONTROL 0x001c
282 #define MWL8K_CMD_RF_TX_POWER 0x001e
283 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
284 #define MWL8K_CMD_SET_POST_SCAN 0x0108
285 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
286 #define MWL8K_CMD_SET_AID 0x010d
287 #define MWL8K_CMD_SET_RATE 0x0110
288 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
289 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
290 #define MWL8K_CMD_SET_SLOT 0x0114
291 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
292 #define MWL8K_CMD_SET_WMM_MODE 0x0123
293 #define MWL8K_CMD_MIMO_CONFIG 0x0125
294 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
295 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
296 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
297 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
298 #define MWL8K_CMD_UPDATE_STADB 0x1123
299
300 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
301 {
302 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
303 snprintf(buf, bufsize, "%s", #x);\
304 return buf;\
305 } while (0)
306 switch (cmd & ~0x8000) {
307 MWL8K_CMDNAME(CODE_DNLD);
308 MWL8K_CMDNAME(GET_HW_SPEC);
309 MWL8K_CMDNAME(SET_HW_SPEC);
310 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
311 MWL8K_CMDNAME(GET_STAT);
312 MWL8K_CMDNAME(RADIO_CONTROL);
313 MWL8K_CMDNAME(RF_TX_POWER);
314 MWL8K_CMDNAME(SET_PRE_SCAN);
315 MWL8K_CMDNAME(SET_POST_SCAN);
316 MWL8K_CMDNAME(SET_RF_CHANNEL);
317 MWL8K_CMDNAME(SET_AID);
318 MWL8K_CMDNAME(SET_RATE);
319 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
320 MWL8K_CMDNAME(RTS_THRESHOLD);
321 MWL8K_CMDNAME(SET_SLOT);
322 MWL8K_CMDNAME(SET_EDCA_PARAMS);
323 MWL8K_CMDNAME(SET_WMM_MODE);
324 MWL8K_CMDNAME(MIMO_CONFIG);
325 MWL8K_CMDNAME(USE_FIXED_RATE);
326 MWL8K_CMDNAME(ENABLE_SNIFFER);
327 MWL8K_CMDNAME(SET_MAC_ADDR);
328 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
329 MWL8K_CMDNAME(UPDATE_STADB);
330 default:
331 snprintf(buf, bufsize, "0x%x", cmd);
332 }
333 #undef MWL8K_CMDNAME
334
335 return buf;
336 }
337
338 /* Hardware and firmware reset */
339 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
340 {
341 iowrite32(MWL8K_H2A_INT_RESET,
342 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
343 iowrite32(MWL8K_H2A_INT_RESET,
344 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
345 msleep(20);
346 }
347
348 /* Release fw image */
349 static void mwl8k_release_fw(struct firmware **fw)
350 {
351 if (*fw == NULL)
352 return;
353 release_firmware(*fw);
354 *fw = NULL;
355 }
356
357 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
358 {
359 mwl8k_release_fw(&priv->fw.ucode);
360 mwl8k_release_fw(&priv->fw.helper);
361 }
362
363 /* Request fw image */
364 static int mwl8k_request_fw(struct mwl8k_priv *priv,
365 const char *fname, struct firmware **fw)
366 {
367 /* release current image */
368 if (*fw != NULL)
369 mwl8k_release_fw(fw);
370
371 return request_firmware((const struct firmware **)fw,
372 fname, &priv->pdev->dev);
373 }
374
375 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
376 {
377 struct mwl8k_device_info *di = priv->device_info;
378 int rc;
379
380 if (di->helper_image != NULL) {
381 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
382 if (rc) {
383 printk(KERN_ERR "%s: Error requesting helper "
384 "firmware file %s\n", pci_name(priv->pdev),
385 di->helper_image);
386 return rc;
387 }
388 }
389
390 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
391 if (rc) {
392 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
393 pci_name(priv->pdev), di->fw_image);
394 mwl8k_release_fw(&priv->fw.helper);
395 return rc;
396 }
397
398 return 0;
399 }
400
401 struct mwl8k_cmd_pkt {
402 __le16 code;
403 __le16 length;
404 __le16 seq_num;
405 __le16 result;
406 char payload[0];
407 } __attribute__((packed));
408
409 /*
410 * Firmware loading.
411 */
412 static int
413 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
414 {
415 void __iomem *regs = priv->regs;
416 dma_addr_t dma_addr;
417 int loops;
418
419 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
420 if (pci_dma_mapping_error(priv->pdev, dma_addr))
421 return -ENOMEM;
422
423 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
424 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
425 iowrite32(MWL8K_H2A_INT_DOORBELL,
426 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
427 iowrite32(MWL8K_H2A_INT_DUMMY,
428 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
429
430 loops = 1000;
431 do {
432 u32 int_code;
433
434 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
435 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
436 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
437 break;
438 }
439
440 cond_resched();
441 udelay(1);
442 } while (--loops);
443
444 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
445
446 return loops ? 0 : -ETIMEDOUT;
447 }
448
449 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
450 const u8 *data, size_t length)
451 {
452 struct mwl8k_cmd_pkt *cmd;
453 int done;
454 int rc = 0;
455
456 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
457 if (cmd == NULL)
458 return -ENOMEM;
459
460 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
461 cmd->seq_num = 0;
462 cmd->result = 0;
463
464 done = 0;
465 while (length) {
466 int block_size = length > 256 ? 256 : length;
467
468 memcpy(cmd->payload, data + done, block_size);
469 cmd->length = cpu_to_le16(block_size);
470
471 rc = mwl8k_send_fw_load_cmd(priv, cmd,
472 sizeof(*cmd) + block_size);
473 if (rc)
474 break;
475
476 done += block_size;
477 length -= block_size;
478 }
479
480 if (!rc) {
481 cmd->length = 0;
482 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
483 }
484
485 kfree(cmd);
486
487 return rc;
488 }
489
490 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
491 const u8 *data, size_t length)
492 {
493 unsigned char *buffer;
494 int may_continue, rc = 0;
495 u32 done, prev_block_size;
496
497 buffer = kmalloc(1024, GFP_KERNEL);
498 if (buffer == NULL)
499 return -ENOMEM;
500
501 done = 0;
502 prev_block_size = 0;
503 may_continue = 1000;
504 while (may_continue > 0) {
505 u32 block_size;
506
507 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
508 if (block_size & 1) {
509 block_size &= ~1;
510 may_continue--;
511 } else {
512 done += prev_block_size;
513 length -= prev_block_size;
514 }
515
516 if (block_size > 1024 || block_size > length) {
517 rc = -EOVERFLOW;
518 break;
519 }
520
521 if (length == 0) {
522 rc = 0;
523 break;
524 }
525
526 if (block_size == 0) {
527 rc = -EPROTO;
528 may_continue--;
529 udelay(1);
530 continue;
531 }
532
533 prev_block_size = block_size;
534 memcpy(buffer, data + done, block_size);
535
536 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
537 if (rc)
538 break;
539 }
540
541 if (!rc && length != 0)
542 rc = -EREMOTEIO;
543
544 kfree(buffer);
545
546 return rc;
547 }
548
549 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
550 {
551 struct mwl8k_priv *priv = hw->priv;
552 struct firmware *fw = priv->fw.ucode;
553 struct mwl8k_device_info *di = priv->device_info;
554 int rc;
555 int loops;
556
557 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
558 struct firmware *helper = priv->fw.helper;
559
560 if (helper == NULL) {
561 printk(KERN_ERR "%s: helper image needed but none "
562 "given\n", pci_name(priv->pdev));
563 return -EINVAL;
564 }
565
566 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
567 if (rc) {
568 printk(KERN_ERR "%s: unable to load firmware "
569 "helper image\n", pci_name(priv->pdev));
570 return rc;
571 }
572 msleep(1);
573
574 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
575 } else {
576 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
577 }
578
579 if (rc) {
580 printk(KERN_ERR "%s: unable to load firmware image\n",
581 pci_name(priv->pdev));
582 return rc;
583 }
584
585 if (di->modes & BIT(NL80211_IFTYPE_AP))
586 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
587 else
588 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
589 msleep(1);
590
591 loops = 200000;
592 do {
593 u32 ready_code;
594
595 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
596 if (ready_code == MWL8K_FWAP_READY) {
597 priv->ap_fw = 1;
598 break;
599 } else if (ready_code == MWL8K_FWSTA_READY) {
600 priv->ap_fw = 0;
601 break;
602 }
603
604 cond_resched();
605 udelay(1);
606 } while (--loops);
607
608 return loops ? 0 : -ETIMEDOUT;
609 }
610
611
612 /*
613 * Defines shared between transmission and reception.
614 */
615 /* HT control fields for firmware */
616 struct ewc_ht_info {
617 __le16 control1;
618 __le16 control2;
619 __le16 control3;
620 } __attribute__((packed));
621
622 /* Firmware Station database operations */
623 #define MWL8K_STA_DB_ADD_ENTRY 0
624 #define MWL8K_STA_DB_MODIFY_ENTRY 1
625 #define MWL8K_STA_DB_DEL_ENTRY 2
626 #define MWL8K_STA_DB_FLUSH 3
627
628 /* Peer Entry flags - used to define the type of the peer node */
629 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
630
631 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
632 #define MWL8K_MCS_BITMAP_SIZE 16
633
634 struct peer_capability_info {
635 /* Peer type - AP vs. STA. */
636 __u8 peer_type;
637
638 /* Basic 802.11 capabilities from assoc resp. */
639 __le16 basic_caps;
640
641 /* Set if peer supports 802.11n high throughput (HT). */
642 __u8 ht_support;
643
644 /* Valid if HT is supported. */
645 __le16 ht_caps;
646 __u8 extended_ht_caps;
647 struct ewc_ht_info ewc_info;
648
649 /* Legacy rate table. Intersection of our rates and peer rates. */
650 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
651
652 /* HT rate table. Intersection of our rates and peer rates. */
653 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
654 __u8 pad[16];
655
656 /* If set, interoperability mode, no proprietary extensions. */
657 __u8 interop;
658 __u8 pad2;
659 __u8 station_id;
660 __le16 amsdu_enabled;
661 } __attribute__((packed));
662
663 /* Inline functions to manipulate QoS field in data descriptor. */
664 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
665 {
666 u16 val_mask = 1 << 4;
667
668 /* End of Service Period Bit 4 */
669 return qos | val_mask;
670 }
671
672 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
673 {
674 u16 val_mask = 0x3;
675 u8 shift = 5;
676 u16 qos_mask = ~(val_mask << shift);
677
678 /* Ack Policy Bit 5-6 */
679 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
680 }
681
682 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
683 {
684 u16 val_mask = 1 << 7;
685
686 /* AMSDU present Bit 7 */
687 return qos | val_mask;
688 }
689
690 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
691 {
692 u16 val_mask = 0xff;
693 u8 shift = 8;
694 u16 qos_mask = ~(val_mask << shift);
695
696 /* Queue Length Bits 8-15 */
697 return (qos & qos_mask) | ((len & val_mask) << shift);
698 }
699
700 /* DMA header used by firmware and hardware. */
701 struct mwl8k_dma_data {
702 __le16 fwlen;
703 struct ieee80211_hdr wh;
704 } __attribute__((packed));
705
706 /* Routines to add/remove DMA header from skb. */
707 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
708 {
709 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
710 void *dst, *src = &tr->wh;
711 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
712 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
713
714 dst = (void *)tr + space;
715 if (dst != src) {
716 memmove(dst, src, hdrlen);
717 skb_pull(skb, space);
718 }
719 }
720
721 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
722 {
723 struct ieee80211_hdr *wh;
724 u32 hdrlen, pktlen;
725 struct mwl8k_dma_data *tr;
726
727 wh = (struct ieee80211_hdr *)skb->data;
728 hdrlen = ieee80211_hdrlen(wh->frame_control);
729 pktlen = skb->len;
730
731 /*
732 * Copy up/down the 802.11 header; the firmware requires
733 * we present a 2-byte payload length followed by a
734 * 4-address header (w/o QoS), followed (optionally) by
735 * any WEP/ExtIV header (but only filled in for CCMP).
736 */
737 if (hdrlen != sizeof(struct mwl8k_dma_data))
738 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
739
740 tr = (struct mwl8k_dma_data *)skb->data;
741 if (wh != &tr->wh)
742 memmove(&tr->wh, wh, hdrlen);
743
744 /* Clear addr4 */
745 memset(tr->wh.addr4, 0, ETH_ALEN);
746
747 /*
748 * Firmware length is the length of the fully formed "802.11
749 * payload". That is, everything except for the 802.11 header.
750 * This includes all crypto material including the MIC.
751 */
752 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
753 }
754
755
756 /*
757 * Packet reception.
758 */
759 struct mwl8k_rxd_8687 {
760 __le16 pkt_len;
761 __u8 link_quality;
762 __u8 noise_level;
763 __le32 pkt_phys_addr;
764 __le32 next_rxd_phys_addr;
765 __le16 qos_control;
766 __le16 rate_info;
767 __le32 pad0[4];
768 __u8 rssi;
769 __u8 channel;
770 __le16 pad1;
771 __u8 rx_ctrl;
772 __u8 rx_status;
773 __u8 pad2[2];
774 } __attribute__((packed));
775
776 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
777 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
778 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
779 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
780 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
781 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
782
783 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
784
785 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
786 {
787 struct mwl8k_rxd_8687 *rxd = _rxd;
788
789 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
790 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
791 }
792
793 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
794 {
795 struct mwl8k_rxd_8687 *rxd = _rxd;
796
797 rxd->pkt_len = cpu_to_le16(len);
798 rxd->pkt_phys_addr = cpu_to_le32(addr);
799 wmb();
800 rxd->rx_ctrl = 0;
801 }
802
803 static int
804 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
805 {
806 struct mwl8k_rxd_8687 *rxd = _rxd;
807 u16 rate_info;
808
809 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
810 return -1;
811 rmb();
812
813 rate_info = le16_to_cpu(rxd->rate_info);
814
815 memset(status, 0, sizeof(*status));
816
817 status->signal = -rxd->rssi;
818 status->noise = -rxd->noise_level;
819 status->qual = rxd->link_quality;
820 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
821 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
822
823 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
824 status->flag |= RX_FLAG_SHORTPRE;
825 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
826 status->flag |= RX_FLAG_40MHZ;
827 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
828 status->flag |= RX_FLAG_SHORT_GI;
829 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
830 status->flag |= RX_FLAG_HT;
831
832 status->band = IEEE80211_BAND_2GHZ;
833 status->freq = ieee80211_channel_to_frequency(rxd->channel);
834
835 return le16_to_cpu(rxd->pkt_len);
836 }
837
838 static struct rxd_ops rxd_8687_ops = {
839 .rxd_size = sizeof(struct mwl8k_rxd_8687),
840 .rxd_init = mwl8k_rxd_8687_init,
841 .rxd_refill = mwl8k_rxd_8687_refill,
842 .rxd_process = mwl8k_rxd_8687_process,
843 };
844
845
846 #define MWL8K_RX_DESCS 256
847 #define MWL8K_RX_MAXSZ 3800
848
849 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
850 {
851 struct mwl8k_priv *priv = hw->priv;
852 struct mwl8k_rx_queue *rxq = priv->rxq + index;
853 int size;
854 int i;
855
856 rxq->rxd_count = 0;
857 rxq->head = 0;
858 rxq->tail = 0;
859
860 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
861
862 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
863 if (rxq->rxd == NULL) {
864 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
865 wiphy_name(hw->wiphy));
866 return -ENOMEM;
867 }
868 memset(rxq->rxd, 0, size);
869
870 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
871 if (rxq->buf == NULL) {
872 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
873 wiphy_name(hw->wiphy));
874 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
875 return -ENOMEM;
876 }
877 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
878
879 for (i = 0; i < MWL8K_RX_DESCS; i++) {
880 int desc_size;
881 void *rxd;
882 int nexti;
883 dma_addr_t next_dma_addr;
884
885 desc_size = priv->rxd_ops->rxd_size;
886 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
887
888 nexti = i + 1;
889 if (nexti == MWL8K_RX_DESCS)
890 nexti = 0;
891 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
892
893 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
894 }
895
896 return 0;
897 }
898
899 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
900 {
901 struct mwl8k_priv *priv = hw->priv;
902 struct mwl8k_rx_queue *rxq = priv->rxq + index;
903 int refilled;
904
905 refilled = 0;
906 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
907 struct sk_buff *skb;
908 dma_addr_t addr;
909 int rx;
910 void *rxd;
911
912 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
913 if (skb == NULL)
914 break;
915
916 addr = pci_map_single(priv->pdev, skb->data,
917 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
918
919 rxq->rxd_count++;
920 rx = rxq->tail++;
921 if (rxq->tail == MWL8K_RX_DESCS)
922 rxq->tail = 0;
923 rxq->buf[rx].skb = skb;
924 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
925
926 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
927 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
928
929 refilled++;
930 }
931
932 return refilled;
933 }
934
935 /* Must be called only when the card's reception is completely halted */
936 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
937 {
938 struct mwl8k_priv *priv = hw->priv;
939 struct mwl8k_rx_queue *rxq = priv->rxq + index;
940 int i;
941
942 for (i = 0; i < MWL8K_RX_DESCS; i++) {
943 if (rxq->buf[i].skb != NULL) {
944 pci_unmap_single(priv->pdev,
945 pci_unmap_addr(&rxq->buf[i], dma),
946 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
947 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
948
949 kfree_skb(rxq->buf[i].skb);
950 rxq->buf[i].skb = NULL;
951 }
952 }
953
954 kfree(rxq->buf);
955 rxq->buf = NULL;
956
957 pci_free_consistent(priv->pdev,
958 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
959 rxq->rxd, rxq->rxd_dma);
960 rxq->rxd = NULL;
961 }
962
963
964 /*
965 * Scan a list of BSSIDs to process for finalize join.
966 * Allows for extension to process multiple BSSIDs.
967 */
968 static inline int
969 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
970 {
971 return priv->capture_beacon &&
972 ieee80211_is_beacon(wh->frame_control) &&
973 !compare_ether_addr(wh->addr3, priv->capture_bssid);
974 }
975
976 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
977 struct sk_buff *skb)
978 {
979 struct mwl8k_priv *priv = hw->priv;
980
981 priv->capture_beacon = false;
982 memset(priv->capture_bssid, 0, ETH_ALEN);
983
984 /*
985 * Use GFP_ATOMIC as rxq_process is called from
986 * the primary interrupt handler, memory allocation call
987 * must not sleep.
988 */
989 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
990 if (priv->beacon_skb != NULL)
991 ieee80211_queue_work(hw, &priv->finalize_join_worker);
992 }
993
994 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
995 {
996 struct mwl8k_priv *priv = hw->priv;
997 struct mwl8k_rx_queue *rxq = priv->rxq + index;
998 int processed;
999
1000 processed = 0;
1001 while (rxq->rxd_count && limit--) {
1002 struct sk_buff *skb;
1003 void *rxd;
1004 int pkt_len;
1005 struct ieee80211_rx_status status;
1006
1007 skb = rxq->buf[rxq->head].skb;
1008 if (skb == NULL)
1009 break;
1010
1011 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1012
1013 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1014 if (pkt_len < 0)
1015 break;
1016
1017 rxq->buf[rxq->head].skb = NULL;
1018
1019 pci_unmap_single(priv->pdev,
1020 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1021 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1022 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1023
1024 rxq->head++;
1025 if (rxq->head == MWL8K_RX_DESCS)
1026 rxq->head = 0;
1027
1028 rxq->rxd_count--;
1029
1030 skb_put(skb, pkt_len);
1031 mwl8k_remove_dma_header(skb);
1032
1033 /*
1034 * Check for a pending join operation. Save a
1035 * copy of the beacon and schedule a tasklet to
1036 * send a FINALIZE_JOIN command to the firmware.
1037 */
1038 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1039 mwl8k_save_beacon(hw, skb);
1040
1041 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1042 ieee80211_rx_irqsafe(hw, skb);
1043
1044 processed++;
1045 }
1046
1047 return processed;
1048 }
1049
1050
1051 /*
1052 * Packet transmission.
1053 */
1054
1055 /* Transmit packet ACK policy */
1056 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
1057 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1058
1059 #define MWL8K_TXD_STATUS_OK 0x00000001
1060 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1061 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1062 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1063 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1064
1065 struct mwl8k_tx_desc {
1066 __le32 status;
1067 __u8 data_rate;
1068 __u8 tx_priority;
1069 __le16 qos_control;
1070 __le32 pkt_phys_addr;
1071 __le16 pkt_len;
1072 __u8 dest_MAC_addr[ETH_ALEN];
1073 __le32 next_txd_phys_addr;
1074 __le32 reserved;
1075 __le16 rate_info;
1076 __u8 peer_id;
1077 __u8 tx_frag_cnt;
1078 } __attribute__((packed));
1079
1080 #define MWL8K_TX_DESCS 128
1081
1082 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1083 {
1084 struct mwl8k_priv *priv = hw->priv;
1085 struct mwl8k_tx_queue *txq = priv->txq + index;
1086 int size;
1087 int i;
1088
1089 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1090 txq->stats.limit = MWL8K_TX_DESCS;
1091 txq->head = 0;
1092 txq->tail = 0;
1093
1094 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1095
1096 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1097 if (txq->txd == NULL) {
1098 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1099 wiphy_name(hw->wiphy));
1100 return -ENOMEM;
1101 }
1102 memset(txq->txd, 0, size);
1103
1104 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1105 if (txq->skb == NULL) {
1106 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1107 wiphy_name(hw->wiphy));
1108 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1109 return -ENOMEM;
1110 }
1111 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1112
1113 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1114 struct mwl8k_tx_desc *tx_desc;
1115 int nexti;
1116
1117 tx_desc = txq->txd + i;
1118 nexti = (i + 1) % MWL8K_TX_DESCS;
1119
1120 tx_desc->status = 0;
1121 tx_desc->next_txd_phys_addr =
1122 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1123 }
1124
1125 return 0;
1126 }
1127
1128 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1129 {
1130 iowrite32(MWL8K_H2A_INT_PPA_READY,
1131 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1132 iowrite32(MWL8K_H2A_INT_DUMMY,
1133 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1134 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1135 }
1136
1137 struct mwl8k_txq_info {
1138 u32 fw_owned;
1139 u32 drv_owned;
1140 u32 unused;
1141 u32 len;
1142 u32 head;
1143 u32 tail;
1144 };
1145
1146 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1147 struct mwl8k_txq_info *txinfo)
1148 {
1149 int count, desc, status;
1150 struct mwl8k_tx_queue *txq;
1151 struct mwl8k_tx_desc *tx_desc;
1152 int ndescs = 0;
1153
1154 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1155
1156 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1157 txq = priv->txq + count;
1158 txinfo[count].len = txq->stats.len;
1159 txinfo[count].head = txq->head;
1160 txinfo[count].tail = txq->tail;
1161 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1162 tx_desc = txq->txd + desc;
1163 status = le32_to_cpu(tx_desc->status);
1164
1165 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1166 txinfo[count].fw_owned++;
1167 else
1168 txinfo[count].drv_owned++;
1169
1170 if (tx_desc->pkt_len == 0)
1171 txinfo[count].unused++;
1172 }
1173 }
1174
1175 return ndescs;
1176 }
1177
1178 /*
1179 * Must be called with priv->fw_mutex held and tx queues stopped.
1180 */
1181 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1182 {
1183 struct mwl8k_priv *priv = hw->priv;
1184 DECLARE_COMPLETION_ONSTACK(tx_wait);
1185 u32 count;
1186 unsigned long timeout;
1187
1188 might_sleep();
1189
1190 spin_lock_bh(&priv->tx_lock);
1191 count = priv->pending_tx_pkts;
1192 if (count)
1193 priv->tx_wait = &tx_wait;
1194 spin_unlock_bh(&priv->tx_lock);
1195
1196 if (count) {
1197 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1198 int index;
1199 int newcount;
1200
1201 timeout = wait_for_completion_timeout(&tx_wait,
1202 msecs_to_jiffies(5000));
1203 if (timeout)
1204 return 0;
1205
1206 spin_lock_bh(&priv->tx_lock);
1207 priv->tx_wait = NULL;
1208 newcount = priv->pending_tx_pkts;
1209 mwl8k_scan_tx_ring(priv, txinfo);
1210 spin_unlock_bh(&priv->tx_lock);
1211
1212 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1213 __func__, __LINE__, count, newcount);
1214
1215 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1216 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1217 "DRV:%u U:%u\n",
1218 index,
1219 txinfo[index].len,
1220 txinfo[index].head,
1221 txinfo[index].tail,
1222 txinfo[index].fw_owned,
1223 txinfo[index].drv_owned,
1224 txinfo[index].unused);
1225
1226 return -ETIMEDOUT;
1227 }
1228
1229 return 0;
1230 }
1231
1232 #define MWL8K_TXD_SUCCESS(status) \
1233 ((status) & (MWL8K_TXD_STATUS_OK | \
1234 MWL8K_TXD_STATUS_OK_RETRY | \
1235 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1236
1237 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1238 {
1239 struct mwl8k_priv *priv = hw->priv;
1240 struct mwl8k_tx_queue *txq = priv->txq + index;
1241 int wake = 0;
1242
1243 while (txq->stats.len > 0) {
1244 int tx;
1245 struct mwl8k_tx_desc *tx_desc;
1246 unsigned long addr;
1247 int size;
1248 struct sk_buff *skb;
1249 struct ieee80211_tx_info *info;
1250 u32 status;
1251
1252 tx = txq->head;
1253 tx_desc = txq->txd + tx;
1254
1255 status = le32_to_cpu(tx_desc->status);
1256
1257 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1258 if (!force)
1259 break;
1260 tx_desc->status &=
1261 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1262 }
1263
1264 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1265 BUG_ON(txq->stats.len == 0);
1266 txq->stats.len--;
1267 priv->pending_tx_pkts--;
1268
1269 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1270 size = le16_to_cpu(tx_desc->pkt_len);
1271 skb = txq->skb[tx];
1272 txq->skb[tx] = NULL;
1273
1274 BUG_ON(skb == NULL);
1275 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1276
1277 mwl8k_remove_dma_header(skb);
1278
1279 /* Mark descriptor as unused */
1280 tx_desc->pkt_phys_addr = 0;
1281 tx_desc->pkt_len = 0;
1282
1283 info = IEEE80211_SKB_CB(skb);
1284 ieee80211_tx_info_clear_status(info);
1285 if (MWL8K_TXD_SUCCESS(status))
1286 info->flags |= IEEE80211_TX_STAT_ACK;
1287
1288 ieee80211_tx_status_irqsafe(hw, skb);
1289
1290 wake = 1;
1291 }
1292
1293 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1294 ieee80211_wake_queue(hw, index);
1295 }
1296
1297 /* must be called only when the card's transmit is completely halted */
1298 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1299 {
1300 struct mwl8k_priv *priv = hw->priv;
1301 struct mwl8k_tx_queue *txq = priv->txq + index;
1302
1303 mwl8k_txq_reclaim(hw, index, 1);
1304
1305 kfree(txq->skb);
1306 txq->skb = NULL;
1307
1308 pci_free_consistent(priv->pdev,
1309 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1310 txq->txd, txq->txd_dma);
1311 txq->txd = NULL;
1312 }
1313
1314 static int
1315 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1316 {
1317 struct mwl8k_priv *priv = hw->priv;
1318 struct ieee80211_tx_info *tx_info;
1319 struct mwl8k_vif *mwl8k_vif;
1320 struct ieee80211_hdr *wh;
1321 struct mwl8k_tx_queue *txq;
1322 struct mwl8k_tx_desc *tx;
1323 dma_addr_t dma;
1324 u32 txstatus;
1325 u8 txdatarate;
1326 u16 qos;
1327
1328 wh = (struct ieee80211_hdr *)skb->data;
1329 if (ieee80211_is_data_qos(wh->frame_control))
1330 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1331 else
1332 qos = 0;
1333
1334 mwl8k_add_dma_header(skb);
1335 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1336
1337 tx_info = IEEE80211_SKB_CB(skb);
1338 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1339
1340 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1341 u16 seqno = mwl8k_vif->seqno;
1342
1343 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1344 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1345 mwl8k_vif->seqno = seqno++ % 4096;
1346 }
1347
1348 /* Setup firmware control bit fields for each frame type. */
1349 txstatus = 0;
1350 txdatarate = 0;
1351 if (ieee80211_is_mgmt(wh->frame_control) ||
1352 ieee80211_is_ctl(wh->frame_control)) {
1353 txdatarate = 0;
1354 qos = mwl8k_qos_setbit_eosp(qos);
1355 /* Set Queue size to unspecified */
1356 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1357 } else if (ieee80211_is_data(wh->frame_control)) {
1358 txdatarate = 1;
1359 if (is_multicast_ether_addr(wh->addr1))
1360 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1361
1362 /* Send pkt in an aggregate if AMPDU frame. */
1363 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1364 qos = mwl8k_qos_setbit_ack(qos,
1365 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1366 else
1367 qos = mwl8k_qos_setbit_ack(qos,
1368 MWL8K_TXD_ACK_POLICY_NORMAL);
1369
1370 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1371 qos = mwl8k_qos_setbit_amsdu(qos);
1372 }
1373
1374 dma = pci_map_single(priv->pdev, skb->data,
1375 skb->len, PCI_DMA_TODEVICE);
1376
1377 if (pci_dma_mapping_error(priv->pdev, dma)) {
1378 printk(KERN_DEBUG "%s: failed to dma map skb, "
1379 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1380 dev_kfree_skb(skb);
1381 return NETDEV_TX_OK;
1382 }
1383
1384 spin_lock_bh(&priv->tx_lock);
1385
1386 txq = priv->txq + index;
1387
1388 BUG_ON(txq->skb[txq->tail] != NULL);
1389 txq->skb[txq->tail] = skb;
1390
1391 tx = txq->txd + txq->tail;
1392 tx->data_rate = txdatarate;
1393 tx->tx_priority = index;
1394 tx->qos_control = cpu_to_le16(qos);
1395 tx->pkt_phys_addr = cpu_to_le32(dma);
1396 tx->pkt_len = cpu_to_le16(skb->len);
1397 tx->rate_info = 0;
1398 tx->peer_id = mwl8k_vif->peer_id;
1399 wmb();
1400 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1401
1402 txq->stats.count++;
1403 txq->stats.len++;
1404 priv->pending_tx_pkts++;
1405
1406 txq->tail++;
1407 if (txq->tail == MWL8K_TX_DESCS)
1408 txq->tail = 0;
1409
1410 if (txq->head == txq->tail)
1411 ieee80211_stop_queue(hw, index);
1412
1413 mwl8k_tx_start(priv);
1414
1415 spin_unlock_bh(&priv->tx_lock);
1416
1417 return NETDEV_TX_OK;
1418 }
1419
1420
1421 /*
1422 * Firmware access.
1423 *
1424 * We have the following requirements for issuing firmware commands:
1425 * - Some commands require that the packet transmit path is idle when
1426 * the command is issued. (For simplicity, we'll just quiesce the
1427 * transmit path for every command.)
1428 * - There are certain sequences of commands that need to be issued to
1429 * the hardware sequentially, with no other intervening commands.
1430 *
1431 * This leads to an implementation of a "firmware lock" as a mutex that
1432 * can be taken recursively, and which is taken by both the low-level
1433 * command submission function (mwl8k_post_cmd) as well as any users of
1434 * that function that require issuing of an atomic sequence of commands,
1435 * and quiesces the transmit path whenever it's taken.
1436 */
1437 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1438 {
1439 struct mwl8k_priv *priv = hw->priv;
1440
1441 if (priv->fw_mutex_owner != current) {
1442 int rc;
1443
1444 mutex_lock(&priv->fw_mutex);
1445 ieee80211_stop_queues(hw);
1446
1447 rc = mwl8k_tx_wait_empty(hw);
1448 if (rc) {
1449 ieee80211_wake_queues(hw);
1450 mutex_unlock(&priv->fw_mutex);
1451
1452 return rc;
1453 }
1454
1455 priv->fw_mutex_owner = current;
1456 }
1457
1458 priv->fw_mutex_depth++;
1459
1460 return 0;
1461 }
1462
1463 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1464 {
1465 struct mwl8k_priv *priv = hw->priv;
1466
1467 if (!--priv->fw_mutex_depth) {
1468 ieee80211_wake_queues(hw);
1469 priv->fw_mutex_owner = NULL;
1470 mutex_unlock(&priv->fw_mutex);
1471 }
1472 }
1473
1474
1475 /*
1476 * Command processing.
1477 */
1478
1479 /* Timeout firmware commands after 2000ms */
1480 #define MWL8K_CMD_TIMEOUT_MS 2000
1481
1482 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1483 {
1484 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1485 struct mwl8k_priv *priv = hw->priv;
1486 void __iomem *regs = priv->regs;
1487 dma_addr_t dma_addr;
1488 unsigned int dma_size;
1489 int rc;
1490 unsigned long timeout = 0;
1491 u8 buf[32];
1492
1493 cmd->result = 0xffff;
1494 dma_size = le16_to_cpu(cmd->length);
1495 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1496 PCI_DMA_BIDIRECTIONAL);
1497 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1498 return -ENOMEM;
1499
1500 rc = mwl8k_fw_lock(hw);
1501 if (rc) {
1502 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1503 PCI_DMA_BIDIRECTIONAL);
1504 return rc;
1505 }
1506
1507 priv->hostcmd_wait = &cmd_wait;
1508 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1509 iowrite32(MWL8K_H2A_INT_DOORBELL,
1510 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1511 iowrite32(MWL8K_H2A_INT_DUMMY,
1512 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1513
1514 timeout = wait_for_completion_timeout(&cmd_wait,
1515 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1516
1517 priv->hostcmd_wait = NULL;
1518
1519 mwl8k_fw_unlock(hw);
1520
1521 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1522 PCI_DMA_BIDIRECTIONAL);
1523
1524 if (!timeout) {
1525 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1526 wiphy_name(hw->wiphy),
1527 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1528 MWL8K_CMD_TIMEOUT_MS);
1529 rc = -ETIMEDOUT;
1530 } else {
1531 rc = cmd->result ? -EINVAL : 0;
1532 if (rc)
1533 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1534 wiphy_name(hw->wiphy),
1535 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1536 le16_to_cpu(cmd->result));
1537 }
1538
1539 return rc;
1540 }
1541
1542 /*
1543 * CMD_GET_HW_SPEC (STA version).
1544 */
1545 struct mwl8k_cmd_get_hw_spec_sta {
1546 struct mwl8k_cmd_pkt header;
1547 __u8 hw_rev;
1548 __u8 host_interface;
1549 __le16 num_mcaddrs;
1550 __u8 perm_addr[ETH_ALEN];
1551 __le16 region_code;
1552 __le32 fw_rev;
1553 __le32 ps_cookie;
1554 __le32 caps;
1555 __u8 mcs_bitmap[16];
1556 __le32 rx_queue_ptr;
1557 __le32 num_tx_queues;
1558 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1559 __le32 caps2;
1560 __le32 num_tx_desc_per_queue;
1561 __le32 total_rxd;
1562 } __attribute__((packed));
1563
1564 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1565 {
1566 struct mwl8k_priv *priv = hw->priv;
1567 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1568 int rc;
1569 int i;
1570
1571 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1572 if (cmd == NULL)
1573 return -ENOMEM;
1574
1575 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1576 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1577
1578 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1579 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1580 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1581 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1582 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1583 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1584 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1585 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1586
1587 rc = mwl8k_post_cmd(hw, &cmd->header);
1588
1589 if (!rc) {
1590 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1591 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1592 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1593 priv->hw_rev = cmd->hw_rev;
1594 }
1595
1596 kfree(cmd);
1597 return rc;
1598 }
1599
1600 /*
1601 * CMD_GET_HW_SPEC (AP version).
1602 */
1603 struct mwl8k_cmd_get_hw_spec_ap {
1604 struct mwl8k_cmd_pkt header;
1605 __u8 hw_rev;
1606 __u8 host_interface;
1607 __le16 num_wcb;
1608 __le16 num_mcaddrs;
1609 __u8 perm_addr[ETH_ALEN];
1610 __le16 region_code;
1611 __le16 num_antenna;
1612 __le32 fw_rev;
1613 __le32 wcbbase0;
1614 __le32 rxwrptr;
1615 __le32 rxrdptr;
1616 __le32 ps_cookie;
1617 __le32 wcbbase1;
1618 __le32 wcbbase2;
1619 __le32 wcbbase3;
1620 } __attribute__((packed));
1621
1622 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1623 {
1624 struct mwl8k_priv *priv = hw->priv;
1625 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1626 int rc;
1627
1628 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1629 if (cmd == NULL)
1630 return -ENOMEM;
1631
1632 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1633 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1634
1635 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1636 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1637
1638 rc = mwl8k_post_cmd(hw, &cmd->header);
1639
1640 if (!rc) {
1641 int off;
1642
1643 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1644 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1645 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1646 priv->hw_rev = cmd->hw_rev;
1647
1648 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1649 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1650
1651 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1652 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1653
1654 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1655 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1656
1657 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1658 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1659
1660 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1661 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1662
1663 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1664 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1665 }
1666
1667 kfree(cmd);
1668 return rc;
1669 }
1670
1671 /*
1672 * CMD_SET_HW_SPEC.
1673 */
1674 struct mwl8k_cmd_set_hw_spec {
1675 struct mwl8k_cmd_pkt header;
1676 __u8 hw_rev;
1677 __u8 host_interface;
1678 __le16 num_mcaddrs;
1679 __u8 perm_addr[ETH_ALEN];
1680 __le16 region_code;
1681 __le32 fw_rev;
1682 __le32 ps_cookie;
1683 __le32 caps;
1684 __le32 rx_queue_ptr;
1685 __le32 num_tx_queues;
1686 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1687 __le32 flags;
1688 __le32 num_tx_desc_per_queue;
1689 __le32 total_rxd;
1690 } __attribute__((packed));
1691
1692 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1693
1694 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1695 {
1696 struct mwl8k_priv *priv = hw->priv;
1697 struct mwl8k_cmd_set_hw_spec *cmd;
1698 int rc;
1699 int i;
1700
1701 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1702 if (cmd == NULL)
1703 return -ENOMEM;
1704
1705 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1706 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1707
1708 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1709 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1710 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1711 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1712 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1713 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1714 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1715 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1716
1717 rc = mwl8k_post_cmd(hw, &cmd->header);
1718 kfree(cmd);
1719
1720 return rc;
1721 }
1722
1723 /*
1724 * CMD_MAC_MULTICAST_ADR.
1725 */
1726 struct mwl8k_cmd_mac_multicast_adr {
1727 struct mwl8k_cmd_pkt header;
1728 __le16 action;
1729 __le16 numaddr;
1730 __u8 addr[0][ETH_ALEN];
1731 };
1732
1733 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1734 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1735 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1736 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1737
1738 static struct mwl8k_cmd_pkt *
1739 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1740 int mc_count, struct dev_addr_list *mclist)
1741 {
1742 struct mwl8k_priv *priv = hw->priv;
1743 struct mwl8k_cmd_mac_multicast_adr *cmd;
1744 int size;
1745
1746 if (allmulti || mc_count > priv->num_mcaddrs) {
1747 allmulti = 1;
1748 mc_count = 0;
1749 }
1750
1751 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1752
1753 cmd = kzalloc(size, GFP_ATOMIC);
1754 if (cmd == NULL)
1755 return NULL;
1756
1757 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1758 cmd->header.length = cpu_to_le16(size);
1759 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1760 MWL8K_ENABLE_RX_BROADCAST);
1761
1762 if (allmulti) {
1763 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1764 } else if (mc_count) {
1765 int i;
1766
1767 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1768 cmd->numaddr = cpu_to_le16(mc_count);
1769 for (i = 0; i < mc_count && mclist; i++) {
1770 if (mclist->da_addrlen != ETH_ALEN) {
1771 kfree(cmd);
1772 return NULL;
1773 }
1774 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1775 mclist = mclist->next;
1776 }
1777 }
1778
1779 return &cmd->header;
1780 }
1781
1782 /*
1783 * CMD_802_11_GET_STAT.
1784 */
1785 struct mwl8k_cmd_802_11_get_stat {
1786 struct mwl8k_cmd_pkt header;
1787 __le32 stats[64];
1788 } __attribute__((packed));
1789
1790 #define MWL8K_STAT_ACK_FAILURE 9
1791 #define MWL8K_STAT_RTS_FAILURE 12
1792 #define MWL8K_STAT_FCS_ERROR 24
1793 #define MWL8K_STAT_RTS_SUCCESS 11
1794
1795 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1796 struct ieee80211_low_level_stats *stats)
1797 {
1798 struct mwl8k_cmd_802_11_get_stat *cmd;
1799 int rc;
1800
1801 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1802 if (cmd == NULL)
1803 return -ENOMEM;
1804
1805 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1806 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1807
1808 rc = mwl8k_post_cmd(hw, &cmd->header);
1809 if (!rc) {
1810 stats->dot11ACKFailureCount =
1811 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1812 stats->dot11RTSFailureCount =
1813 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1814 stats->dot11FCSErrorCount =
1815 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1816 stats->dot11RTSSuccessCount =
1817 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1818 }
1819 kfree(cmd);
1820
1821 return rc;
1822 }
1823
1824 /*
1825 * CMD_802_11_RADIO_CONTROL.
1826 */
1827 struct mwl8k_cmd_802_11_radio_control {
1828 struct mwl8k_cmd_pkt header;
1829 __le16 action;
1830 __le16 control;
1831 __le16 radio_on;
1832 } __attribute__((packed));
1833
1834 static int
1835 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1836 {
1837 struct mwl8k_priv *priv = hw->priv;
1838 struct mwl8k_cmd_802_11_radio_control *cmd;
1839 int rc;
1840
1841 if (enable == priv->radio_on && !force)
1842 return 0;
1843
1844 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1845 if (cmd == NULL)
1846 return -ENOMEM;
1847
1848 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1849 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1850 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1851 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1852 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1853
1854 rc = mwl8k_post_cmd(hw, &cmd->header);
1855 kfree(cmd);
1856
1857 if (!rc)
1858 priv->radio_on = enable;
1859
1860 return rc;
1861 }
1862
1863 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1864 {
1865 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1866 }
1867
1868 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1869 {
1870 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1871 }
1872
1873 static int
1874 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1875 {
1876 struct mwl8k_priv *priv;
1877
1878 if (hw == NULL || hw->priv == NULL)
1879 return -EINVAL;
1880 priv = hw->priv;
1881
1882 priv->radio_short_preamble = short_preamble;
1883
1884 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1885 }
1886
1887 /*
1888 * CMD_802_11_RF_TX_POWER.
1889 */
1890 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1891
1892 struct mwl8k_cmd_802_11_rf_tx_power {
1893 struct mwl8k_cmd_pkt header;
1894 __le16 action;
1895 __le16 support_level;
1896 __le16 current_level;
1897 __le16 reserved;
1898 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1899 } __attribute__((packed));
1900
1901 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1902 {
1903 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1904 int rc;
1905
1906 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1907 if (cmd == NULL)
1908 return -ENOMEM;
1909
1910 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1911 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1912 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1913 cmd->support_level = cpu_to_le16(dBm);
1914
1915 rc = mwl8k_post_cmd(hw, &cmd->header);
1916 kfree(cmd);
1917
1918 return rc;
1919 }
1920
1921 /*
1922 * CMD_SET_PRE_SCAN.
1923 */
1924 struct mwl8k_cmd_set_pre_scan {
1925 struct mwl8k_cmd_pkt header;
1926 } __attribute__((packed));
1927
1928 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1929 {
1930 struct mwl8k_cmd_set_pre_scan *cmd;
1931 int rc;
1932
1933 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1934 if (cmd == NULL)
1935 return -ENOMEM;
1936
1937 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1938 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1939
1940 rc = mwl8k_post_cmd(hw, &cmd->header);
1941 kfree(cmd);
1942
1943 return rc;
1944 }
1945
1946 /*
1947 * CMD_SET_POST_SCAN.
1948 */
1949 struct mwl8k_cmd_set_post_scan {
1950 struct mwl8k_cmd_pkt header;
1951 __le32 isibss;
1952 __u8 bssid[ETH_ALEN];
1953 } __attribute__((packed));
1954
1955 static int
1956 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1957 {
1958 struct mwl8k_cmd_set_post_scan *cmd;
1959 int rc;
1960
1961 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1962 if (cmd == NULL)
1963 return -ENOMEM;
1964
1965 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1966 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1967 cmd->isibss = 0;
1968 memcpy(cmd->bssid, mac, ETH_ALEN);
1969
1970 rc = mwl8k_post_cmd(hw, &cmd->header);
1971 kfree(cmd);
1972
1973 return rc;
1974 }
1975
1976 /*
1977 * CMD_SET_RF_CHANNEL.
1978 */
1979 struct mwl8k_cmd_set_rf_channel {
1980 struct mwl8k_cmd_pkt header;
1981 __le16 action;
1982 __u8 current_channel;
1983 __le32 channel_flags;
1984 } __attribute__((packed));
1985
1986 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1987 struct ieee80211_channel *channel)
1988 {
1989 struct mwl8k_cmd_set_rf_channel *cmd;
1990 int rc;
1991
1992 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1993 if (cmd == NULL)
1994 return -ENOMEM;
1995
1996 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1997 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1998 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1999 cmd->current_channel = channel->hw_value;
2000 if (channel->band == IEEE80211_BAND_2GHZ)
2001 cmd->channel_flags = cpu_to_le32(0x00000081);
2002 else
2003 cmd->channel_flags = cpu_to_le32(0x00000000);
2004
2005 rc = mwl8k_post_cmd(hw, &cmd->header);
2006 kfree(cmd);
2007
2008 return rc;
2009 }
2010
2011 /*
2012 * CMD_SET_SLOT.
2013 */
2014 struct mwl8k_cmd_set_slot {
2015 struct mwl8k_cmd_pkt header;
2016 __le16 action;
2017 __u8 short_slot;
2018 } __attribute__((packed));
2019
2020 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2021 {
2022 struct mwl8k_cmd_set_slot *cmd;
2023 int rc;
2024
2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2026 if (cmd == NULL)
2027 return -ENOMEM;
2028
2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2030 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2031 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2032 cmd->short_slot = short_slot_time;
2033
2034 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 kfree(cmd);
2036
2037 return rc;
2038 }
2039
2040 /*
2041 * CMD_MIMO_CONFIG.
2042 */
2043 struct mwl8k_cmd_mimo_config {
2044 struct mwl8k_cmd_pkt header;
2045 __le32 action;
2046 __u8 rx_antenna_map;
2047 __u8 tx_antenna_map;
2048 } __attribute__((packed));
2049
2050 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2051 {
2052 struct mwl8k_cmd_mimo_config *cmd;
2053 int rc;
2054
2055 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2056 if (cmd == NULL)
2057 return -ENOMEM;
2058
2059 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2060 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2061 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2062 cmd->rx_antenna_map = rx;
2063 cmd->tx_antenna_map = tx;
2064
2065 rc = mwl8k_post_cmd(hw, &cmd->header);
2066 kfree(cmd);
2067
2068 return rc;
2069 }
2070
2071 /*
2072 * CMD_ENABLE_SNIFFER.
2073 */
2074 struct mwl8k_cmd_enable_sniffer {
2075 struct mwl8k_cmd_pkt header;
2076 __le32 action;
2077 } __attribute__((packed));
2078
2079 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2080 {
2081 struct mwl8k_cmd_enable_sniffer *cmd;
2082 int rc;
2083
2084 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2085 if (cmd == NULL)
2086 return -ENOMEM;
2087
2088 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2089 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2090 cmd->action = cpu_to_le32(!!enable);
2091
2092 rc = mwl8k_post_cmd(hw, &cmd->header);
2093 kfree(cmd);
2094
2095 return rc;
2096 }
2097
2098 /*
2099 * CMD_SET_MAC_ADDR.
2100 */
2101 struct mwl8k_cmd_set_mac_addr {
2102 struct mwl8k_cmd_pkt header;
2103 __u8 mac_addr[ETH_ALEN];
2104 } __attribute__((packed));
2105
2106 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2107 {
2108 struct mwl8k_cmd_set_mac_addr *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2118
2119 rc = mwl8k_post_cmd(hw, &cmd->header);
2120 kfree(cmd);
2121
2122 return rc;
2123 }
2124
2125
2126 /*
2127 * CMD_SET_RATEADAPT_MODE.
2128 */
2129 struct mwl8k_cmd_set_rate_adapt_mode {
2130 struct mwl8k_cmd_pkt header;
2131 __le16 action;
2132 __le16 mode;
2133 } __attribute__((packed));
2134
2135 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2136 {
2137 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2138 int rc;
2139
2140 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2141 if (cmd == NULL)
2142 return -ENOMEM;
2143
2144 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2145 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2146 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2147 cmd->mode = cpu_to_le16(mode);
2148
2149 rc = mwl8k_post_cmd(hw, &cmd->header);
2150 kfree(cmd);
2151
2152 return rc;
2153 }
2154
2155 /*
2156 * CMD_SET_WMM_MODE.
2157 */
2158 struct mwl8k_cmd_set_wmm {
2159 struct mwl8k_cmd_pkt header;
2160 __le16 action;
2161 } __attribute__((packed));
2162
2163 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2164 {
2165 struct mwl8k_priv *priv = hw->priv;
2166 struct mwl8k_cmd_set_wmm *cmd;
2167 int rc;
2168
2169 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2170 if (cmd == NULL)
2171 return -ENOMEM;
2172
2173 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2174 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2175 cmd->action = cpu_to_le16(!!enable);
2176
2177 rc = mwl8k_post_cmd(hw, &cmd->header);
2178 kfree(cmd);
2179
2180 if (!rc)
2181 priv->wmm_enabled = enable;
2182
2183 return rc;
2184 }
2185
2186 /*
2187 * CMD_SET_RTS_THRESHOLD.
2188 */
2189 struct mwl8k_cmd_rts_threshold {
2190 struct mwl8k_cmd_pkt header;
2191 __le16 action;
2192 __le16 threshold;
2193 } __attribute__((packed));
2194
2195 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2196 u16 action, u16 threshold)
2197 {
2198 struct mwl8k_cmd_rts_threshold *cmd;
2199 int rc;
2200
2201 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2202 if (cmd == NULL)
2203 return -ENOMEM;
2204
2205 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2206 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2207 cmd->action = cpu_to_le16(action);
2208 cmd->threshold = cpu_to_le16(threshold);
2209
2210 rc = mwl8k_post_cmd(hw, &cmd->header);
2211 kfree(cmd);
2212
2213 return rc;
2214 }
2215
2216 /*
2217 * CMD_SET_EDCA_PARAMS.
2218 */
2219 struct mwl8k_cmd_set_edca_params {
2220 struct mwl8k_cmd_pkt header;
2221
2222 /* See MWL8K_SET_EDCA_XXX below */
2223 __le16 action;
2224
2225 /* TX opportunity in units of 32 us */
2226 __le16 txop;
2227
2228 /* Log exponent of max contention period: 0...15*/
2229 __u8 log_cw_max;
2230
2231 /* Log exponent of min contention period: 0...15 */
2232 __u8 log_cw_min;
2233
2234 /* Adaptive interframe spacing in units of 32us */
2235 __u8 aifs;
2236
2237 /* TX queue to configure */
2238 __u8 txq;
2239 } __attribute__((packed));
2240
2241 #define MWL8K_SET_EDCA_CW 0x01
2242 #define MWL8K_SET_EDCA_TXOP 0x02
2243 #define MWL8K_SET_EDCA_AIFS 0x04
2244
2245 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2246 MWL8K_SET_EDCA_TXOP | \
2247 MWL8K_SET_EDCA_AIFS)
2248
2249 static int
2250 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2251 __u16 cw_min, __u16 cw_max,
2252 __u8 aifs, __u16 txop)
2253 {
2254 struct mwl8k_cmd_set_edca_params *cmd;
2255 int rc;
2256
2257 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2258 if (cmd == NULL)
2259 return -ENOMEM;
2260
2261 /*
2262 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2263 * this call.
2264 */
2265 qnum ^= !(qnum >> 1);
2266
2267 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2268 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2269 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2270 cmd->txop = cpu_to_le16(txop);
2271 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2272 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2273 cmd->aifs = aifs;
2274 cmd->txq = qnum;
2275
2276 rc = mwl8k_post_cmd(hw, &cmd->header);
2277 kfree(cmd);
2278
2279 return rc;
2280 }
2281
2282 /*
2283 * CMD_FINALIZE_JOIN.
2284 */
2285
2286 /* FJ beacon buffer size is compiled into the firmware. */
2287 #define MWL8K_FJ_BEACON_MAXLEN 128
2288
2289 struct mwl8k_cmd_finalize_join {
2290 struct mwl8k_cmd_pkt header;
2291 __le32 sleep_interval; /* Number of beacon periods to sleep */
2292 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2293 } __attribute__((packed));
2294
2295 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2296 __u16 framelen, __u16 dtim)
2297 {
2298 struct mwl8k_cmd_finalize_join *cmd;
2299 struct ieee80211_mgmt *payload = frame;
2300 u16 hdrlen;
2301 u32 payload_len;
2302 int rc;
2303
2304 if (frame == NULL)
2305 return -EINVAL;
2306
2307 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2308 if (cmd == NULL)
2309 return -ENOMEM;
2310
2311 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2312 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2313 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2314
2315 hdrlen = ieee80211_hdrlen(payload->frame_control);
2316
2317 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2318
2319 /* XXX TBD Might just have to abort and return an error */
2320 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2321 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2322 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2323 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2324
2325 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2326 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2327
2328 if (payload && payload_len)
2329 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2330
2331 rc = mwl8k_post_cmd(hw, &cmd->header);
2332 kfree(cmd);
2333 return rc;
2334 }
2335
2336 /*
2337 * CMD_UPDATE_STADB.
2338 */
2339 struct mwl8k_cmd_update_sta_db {
2340 struct mwl8k_cmd_pkt header;
2341
2342 /* See STADB_ACTION_TYPE */
2343 __le32 action;
2344
2345 /* Peer MAC address */
2346 __u8 peer_addr[ETH_ALEN];
2347
2348 __le32 reserved;
2349
2350 /* Peer info - valid during add/update. */
2351 struct peer_capability_info peer_info;
2352 } __attribute__((packed));
2353
2354 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2355 struct ieee80211_vif *vif, __u32 action)
2356 {
2357 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2358 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2359 struct mwl8k_cmd_update_sta_db *cmd;
2360 struct peer_capability_info *peer_info;
2361 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2362 int rc;
2363 __u8 count, *rates;
2364
2365 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2366 if (cmd == NULL)
2367 return -ENOMEM;
2368
2369 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2370 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2371
2372 cmd->action = cpu_to_le32(action);
2373 peer_info = &cmd->peer_info;
2374 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2375
2376 switch (action) {
2377 case MWL8K_STA_DB_ADD_ENTRY:
2378 case MWL8K_STA_DB_MODIFY_ENTRY:
2379 /* Build peer_info block */
2380 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2381 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2382 peer_info->interop = 1;
2383 peer_info->amsdu_enabled = 0;
2384
2385 rates = peer_info->legacy_rates;
2386 for (count = 0; count < mv_vif->legacy_nrates; count++)
2387 rates[count] = bitrates[count].hw_value;
2388
2389 rc = mwl8k_post_cmd(hw, &cmd->header);
2390 if (rc == 0)
2391 mv_vif->peer_id = peer_info->station_id;
2392
2393 break;
2394
2395 case MWL8K_STA_DB_DEL_ENTRY:
2396 case MWL8K_STA_DB_FLUSH:
2397 default:
2398 rc = mwl8k_post_cmd(hw, &cmd->header);
2399 if (rc == 0)
2400 mv_vif->peer_id = 0;
2401 break;
2402 }
2403 kfree(cmd);
2404
2405 return rc;
2406 }
2407
2408 /*
2409 * CMD_SET_AID.
2410 */
2411 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2412
2413 #define MWL8K_FRAME_PROT_DISABLED 0x00
2414 #define MWL8K_FRAME_PROT_11G 0x07
2415 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2416 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2417
2418 struct mwl8k_cmd_update_set_aid {
2419 struct mwl8k_cmd_pkt header;
2420 __le16 aid;
2421
2422 /* AP's MAC address (BSSID) */
2423 __u8 bssid[ETH_ALEN];
2424 __le16 protection_mode;
2425 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2426 } __attribute__((packed));
2427
2428 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2429 struct ieee80211_vif *vif)
2430 {
2431 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2432 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2433 struct mwl8k_cmd_update_set_aid *cmd;
2434 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2435 int count;
2436 u16 prot_mode;
2437 int rc;
2438
2439 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2440 if (cmd == NULL)
2441 return -ENOMEM;
2442
2443 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2444 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2445 cmd->aid = cpu_to_le16(info->aid);
2446
2447 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2448
2449 if (info->use_cts_prot) {
2450 prot_mode = MWL8K_FRAME_PROT_11G;
2451 } else {
2452 switch (info->ht_operation_mode &
2453 IEEE80211_HT_OP_MODE_PROTECTION) {
2454 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2455 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2456 break;
2457 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2458 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2459 break;
2460 default:
2461 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2462 break;
2463 }
2464 }
2465 cmd->protection_mode = cpu_to_le16(prot_mode);
2466
2467 for (count = 0; count < mv_vif->legacy_nrates; count++)
2468 cmd->supp_rates[count] = bitrates[count].hw_value;
2469
2470 rc = mwl8k_post_cmd(hw, &cmd->header);
2471 kfree(cmd);
2472
2473 return rc;
2474 }
2475
2476 /*
2477 * CMD_SET_RATE.
2478 */
2479 struct mwl8k_cmd_update_rateset {
2480 struct mwl8k_cmd_pkt header;
2481 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2482
2483 /* Bitmap for supported MCS codes. */
2484 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2485 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2486 } __attribute__((packed));
2487
2488 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2489 struct ieee80211_vif *vif)
2490 {
2491 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2492 struct mwl8k_cmd_update_rateset *cmd;
2493 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2494 int count;
2495 int rc;
2496
2497 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2498 if (cmd == NULL)
2499 return -ENOMEM;
2500
2501 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2502 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2503
2504 for (count = 0; count < mv_vif->legacy_nrates; count++)
2505 cmd->legacy_rates[count] = bitrates[count].hw_value;
2506
2507 rc = mwl8k_post_cmd(hw, &cmd->header);
2508 kfree(cmd);
2509
2510 return rc;
2511 }
2512
2513 /*
2514 * CMD_USE_FIXED_RATE.
2515 */
2516 #define MWL8K_RATE_TABLE_SIZE 8
2517 #define MWL8K_UCAST_RATE 0
2518 #define MWL8K_USE_AUTO_RATE 0x0002
2519
2520 struct mwl8k_rate_entry {
2521 /* Set to 1 if HT rate, 0 if legacy. */
2522 __le32 is_ht_rate;
2523
2524 /* Set to 1 to use retry_count field. */
2525 __le32 enable_retry;
2526
2527 /* Specified legacy rate or MCS. */
2528 __le32 rate;
2529
2530 /* Number of allowed retries. */
2531 __le32 retry_count;
2532 } __attribute__((packed));
2533
2534 struct mwl8k_rate_table {
2535 /* 1 to allow specified rate and below */
2536 __le32 allow_rate_drop;
2537 __le32 num_rates;
2538 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2539 } __attribute__((packed));
2540
2541 struct mwl8k_cmd_use_fixed_rate {
2542 struct mwl8k_cmd_pkt header;
2543 __le32 action;
2544 struct mwl8k_rate_table rate_table;
2545
2546 /* Unicast, Broadcast or Multicast */
2547 __le32 rate_type;
2548 __le32 reserved1;
2549 __le32 reserved2;
2550 } __attribute__((packed));
2551
2552 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2553 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2554 {
2555 struct mwl8k_cmd_use_fixed_rate *cmd;
2556 int count;
2557 int rc;
2558
2559 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2560 if (cmd == NULL)
2561 return -ENOMEM;
2562
2563 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2564 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2565
2566 cmd->action = cpu_to_le32(action);
2567 cmd->rate_type = cpu_to_le32(rate_type);
2568
2569 if (rate_table != NULL) {
2570 /*
2571 * Copy over each field manually so that endian
2572 * conversion can be done.
2573 */
2574 cmd->rate_table.allow_rate_drop =
2575 cpu_to_le32(rate_table->allow_rate_drop);
2576 cmd->rate_table.num_rates =
2577 cpu_to_le32(rate_table->num_rates);
2578
2579 for (count = 0; count < rate_table->num_rates; count++) {
2580 struct mwl8k_rate_entry *dst =
2581 &cmd->rate_table.rate_entry[count];
2582 struct mwl8k_rate_entry *src =
2583 &rate_table->rate_entry[count];
2584
2585 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2586 dst->enable_retry = cpu_to_le32(src->enable_retry);
2587 dst->rate = cpu_to_le32(src->rate);
2588 dst->retry_count = cpu_to_le32(src->retry_count);
2589 }
2590 }
2591
2592 rc = mwl8k_post_cmd(hw, &cmd->header);
2593 kfree(cmd);
2594
2595 return rc;
2596 }
2597
2598
2599 /*
2600 * Interrupt handling.
2601 */
2602 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2603 {
2604 struct ieee80211_hw *hw = dev_id;
2605 struct mwl8k_priv *priv = hw->priv;
2606 u32 status;
2607
2608 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2609 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2610
2611 if (!status)
2612 return IRQ_NONE;
2613
2614 if (status & MWL8K_A2H_INT_TX_DONE)
2615 tasklet_schedule(&priv->tx_reclaim_task);
2616
2617 if (status & MWL8K_A2H_INT_RX_READY) {
2618 while (rxq_process(hw, 0, 1))
2619 rxq_refill(hw, 0, 1);
2620 }
2621
2622 if (status & MWL8K_A2H_INT_OPC_DONE) {
2623 if (priv->hostcmd_wait != NULL)
2624 complete(priv->hostcmd_wait);
2625 }
2626
2627 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2628 if (!mutex_is_locked(&priv->fw_mutex) &&
2629 priv->radio_on && priv->pending_tx_pkts)
2630 mwl8k_tx_start(priv);
2631 }
2632
2633 return IRQ_HANDLED;
2634 }
2635
2636
2637 /*
2638 * Core driver operations.
2639 */
2640 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2641 {
2642 struct mwl8k_priv *priv = hw->priv;
2643 int index = skb_get_queue_mapping(skb);
2644 int rc;
2645
2646 if (priv->current_channel == NULL) {
2647 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2648 "disabled\n", wiphy_name(hw->wiphy));
2649 dev_kfree_skb(skb);
2650 return NETDEV_TX_OK;
2651 }
2652
2653 rc = mwl8k_txq_xmit(hw, index, skb);
2654
2655 return rc;
2656 }
2657
2658 static int mwl8k_start(struct ieee80211_hw *hw)
2659 {
2660 struct mwl8k_priv *priv = hw->priv;
2661 int rc;
2662
2663 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2664 IRQF_SHARED, MWL8K_NAME, hw);
2665 if (rc) {
2666 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2667 wiphy_name(hw->wiphy));
2668 return -EIO;
2669 }
2670
2671 /* Enable tx reclaim tasklet */
2672 tasklet_enable(&priv->tx_reclaim_task);
2673
2674 /* Enable interrupts */
2675 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2676
2677 rc = mwl8k_fw_lock(hw);
2678 if (!rc) {
2679 rc = mwl8k_cmd_802_11_radio_enable(hw);
2680
2681 if (!rc)
2682 rc = mwl8k_cmd_set_pre_scan(hw);
2683
2684 if (!rc)
2685 rc = mwl8k_cmd_set_post_scan(hw,
2686 "\x00\x00\x00\x00\x00\x00");
2687
2688 if (!rc)
2689 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2690
2691 if (!rc)
2692 rc = mwl8k_set_wmm(hw, 0);
2693
2694 if (!rc)
2695 rc = mwl8k_enable_sniffer(hw, 0);
2696
2697 mwl8k_fw_unlock(hw);
2698 }
2699
2700 if (rc) {
2701 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2702 free_irq(priv->pdev->irq, hw);
2703 tasklet_disable(&priv->tx_reclaim_task);
2704 }
2705
2706 return rc;
2707 }
2708
2709 static void mwl8k_stop(struct ieee80211_hw *hw)
2710 {
2711 struct mwl8k_priv *priv = hw->priv;
2712 int i;
2713
2714 mwl8k_cmd_802_11_radio_disable(hw);
2715
2716 ieee80211_stop_queues(hw);
2717
2718 /* Disable interrupts */
2719 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2720 free_irq(priv->pdev->irq, hw);
2721
2722 /* Stop finalize join worker */
2723 cancel_work_sync(&priv->finalize_join_worker);
2724 if (priv->beacon_skb != NULL)
2725 dev_kfree_skb(priv->beacon_skb);
2726
2727 /* Stop tx reclaim tasklet */
2728 tasklet_disable(&priv->tx_reclaim_task);
2729
2730 /* Return all skbs to mac80211 */
2731 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2732 mwl8k_txq_reclaim(hw, i, 1);
2733 }
2734
2735 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2736 struct ieee80211_if_init_conf *conf)
2737 {
2738 struct mwl8k_priv *priv = hw->priv;
2739 struct mwl8k_vif *mwl8k_vif;
2740
2741 /*
2742 * We only support one active interface at a time.
2743 */
2744 if (priv->vif != NULL)
2745 return -EBUSY;
2746
2747 /*
2748 * We only support managed interfaces for now.
2749 */
2750 if (conf->type != NL80211_IFTYPE_STATION)
2751 return -EINVAL;
2752
2753 /*
2754 * Reject interface creation if sniffer mode is active, as
2755 * STA operation is mutually exclusive with hardware sniffer
2756 * mode.
2757 */
2758 if (priv->sniffer_enabled) {
2759 printk(KERN_INFO "%s: unable to create STA "
2760 "interface due to sniffer mode being enabled\n",
2761 wiphy_name(hw->wiphy));
2762 return -EINVAL;
2763 }
2764
2765 /* Clean out driver private area */
2766 mwl8k_vif = MWL8K_VIF(conf->vif);
2767 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2768
2769 /* Set and save the mac address */
2770 mwl8k_set_mac_addr(hw, conf->mac_addr);
2771 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2772
2773 /* Back pointer to parent config block */
2774 mwl8k_vif->priv = priv;
2775
2776 /* Setup initial PHY parameters */
2777 memcpy(mwl8k_vif->legacy_rates,
2778 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2779 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2780
2781 /* Set Initial sequence number to zero */
2782 mwl8k_vif->seqno = 0;
2783
2784 priv->vif = conf->vif;
2785 priv->current_channel = NULL;
2786
2787 return 0;
2788 }
2789
2790 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2791 struct ieee80211_if_init_conf *conf)
2792 {
2793 struct mwl8k_priv *priv = hw->priv;
2794
2795 if (priv->vif == NULL)
2796 return;
2797
2798 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2799
2800 priv->vif = NULL;
2801 }
2802
2803 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2804 {
2805 struct ieee80211_conf *conf = &hw->conf;
2806 struct mwl8k_priv *priv = hw->priv;
2807 int rc;
2808
2809 if (conf->flags & IEEE80211_CONF_IDLE) {
2810 mwl8k_cmd_802_11_radio_disable(hw);
2811 priv->current_channel = NULL;
2812 return 0;
2813 }
2814
2815 rc = mwl8k_fw_lock(hw);
2816 if (rc)
2817 return rc;
2818
2819 rc = mwl8k_cmd_802_11_radio_enable(hw);
2820 if (rc)
2821 goto out;
2822
2823 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2824 if (rc)
2825 goto out;
2826
2827 priv->current_channel = conf->channel;
2828
2829 if (conf->power_level > 18)
2830 conf->power_level = 18;
2831 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2832 if (rc)
2833 goto out;
2834
2835 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2836 rc = -EINVAL;
2837
2838 out:
2839 mwl8k_fw_unlock(hw);
2840
2841 return rc;
2842 }
2843
2844 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2845 struct ieee80211_vif *vif,
2846 struct ieee80211_bss_conf *info,
2847 u32 changed)
2848 {
2849 struct mwl8k_priv *priv = hw->priv;
2850 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2851 int rc;
2852
2853 if (changed & BSS_CHANGED_BSSID)
2854 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2855
2856 if ((changed & BSS_CHANGED_ASSOC) == 0)
2857 return;
2858
2859 priv->capture_beacon = false;
2860
2861 rc = mwl8k_fw_lock(hw);
2862 if (rc)
2863 return;
2864
2865 if (info->assoc) {
2866 memcpy(&mwl8k_vif->bss_info, info,
2867 sizeof(struct ieee80211_bss_conf));
2868
2869 /* Install rates */
2870 rc = mwl8k_update_rateset(hw, vif);
2871 if (rc)
2872 goto out;
2873
2874 /* Turn on rate adaptation */
2875 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2876 MWL8K_UCAST_RATE, NULL);
2877 if (rc)
2878 goto out;
2879
2880 /* Set radio preamble */
2881 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2882 if (rc)
2883 goto out;
2884
2885 /* Set slot time */
2886 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2887 if (rc)
2888 goto out;
2889
2890 /* Update peer rate info */
2891 rc = mwl8k_cmd_update_sta_db(hw, vif,
2892 MWL8K_STA_DB_MODIFY_ENTRY);
2893 if (rc)
2894 goto out;
2895
2896 /* Set AID */
2897 rc = mwl8k_cmd_set_aid(hw, vif);
2898 if (rc)
2899 goto out;
2900
2901 /*
2902 * Finalize the join. Tell rx handler to process
2903 * next beacon from our BSSID.
2904 */
2905 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2906 priv->capture_beacon = true;
2907 } else {
2908 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2909 memset(&mwl8k_vif->bss_info, 0,
2910 sizeof(struct ieee80211_bss_conf));
2911 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2912 }
2913
2914 out:
2915 mwl8k_fw_unlock(hw);
2916 }
2917
2918 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2919 int mc_count, struct dev_addr_list *mclist)
2920 {
2921 struct mwl8k_cmd_pkt *cmd;
2922
2923 /*
2924 * Synthesize and return a command packet that programs the
2925 * hardware multicast address filter. At this point we don't
2926 * know whether FIF_ALLMULTI is being requested, but if it is,
2927 * we'll end up throwing this packet away and creating a new
2928 * one in mwl8k_configure_filter().
2929 */
2930 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2931
2932 return (unsigned long)cmd;
2933 }
2934
2935 static int
2936 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2937 unsigned int changed_flags,
2938 unsigned int *total_flags)
2939 {
2940 struct mwl8k_priv *priv = hw->priv;
2941
2942 /*
2943 * Hardware sniffer mode is mutually exclusive with STA
2944 * operation, so refuse to enable sniffer mode if a STA
2945 * interface is active.
2946 */
2947 if (priv->vif != NULL) {
2948 if (net_ratelimit())
2949 printk(KERN_INFO "%s: not enabling sniffer "
2950 "mode because STA interface is active\n",
2951 wiphy_name(hw->wiphy));
2952 return 0;
2953 }
2954
2955 if (!priv->sniffer_enabled) {
2956 if (mwl8k_enable_sniffer(hw, 1))
2957 return 0;
2958 priv->sniffer_enabled = true;
2959 }
2960
2961 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2962 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2963 FIF_OTHER_BSS;
2964
2965 return 1;
2966 }
2967
2968 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2969 unsigned int changed_flags,
2970 unsigned int *total_flags,
2971 u64 multicast)
2972 {
2973 struct mwl8k_priv *priv = hw->priv;
2974 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2975
2976 /*
2977 * Enable hardware sniffer mode if FIF_CONTROL or
2978 * FIF_OTHER_BSS is requested.
2979 */
2980 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2981 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2982 kfree(cmd);
2983 return;
2984 }
2985
2986 /* Clear unsupported feature flags */
2987 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2988
2989 if (mwl8k_fw_lock(hw))
2990 return;
2991
2992 if (priv->sniffer_enabled) {
2993 mwl8k_enable_sniffer(hw, 0);
2994 priv->sniffer_enabled = false;
2995 }
2996
2997 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2998 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2999 /*
3000 * Disable the BSS filter.
3001 */
3002 mwl8k_cmd_set_pre_scan(hw);
3003 } else {
3004 u8 *bssid;
3005
3006 /*
3007 * Enable the BSS filter.
3008 *
3009 * If there is an active STA interface, use that
3010 * interface's BSSID, otherwise use a dummy one
3011 * (where the OUI part needs to be nonzero for
3012 * the BSSID to be accepted by POST_SCAN).
3013 */
3014 bssid = "\x01\x00\x00\x00\x00\x00";
3015 if (priv->vif != NULL)
3016 bssid = MWL8K_VIF(priv->vif)->bssid;
3017
3018 mwl8k_cmd_set_post_scan(hw, bssid);
3019 }
3020 }
3021
3022 /*
3023 * If FIF_ALLMULTI is being requested, throw away the command
3024 * packet that ->prepare_multicast() built and replace it with
3025 * a command packet that enables reception of all multicast
3026 * packets.
3027 */
3028 if (*total_flags & FIF_ALLMULTI) {
3029 kfree(cmd);
3030 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3031 }
3032
3033 if (cmd != NULL) {
3034 mwl8k_post_cmd(hw, cmd);
3035 kfree(cmd);
3036 }
3037
3038 mwl8k_fw_unlock(hw);
3039 }
3040
3041 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3042 {
3043 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
3044 }
3045
3046 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3047 const struct ieee80211_tx_queue_params *params)
3048 {
3049 struct mwl8k_priv *priv = hw->priv;
3050 int rc;
3051
3052 rc = mwl8k_fw_lock(hw);
3053 if (!rc) {
3054 if (!priv->wmm_enabled)
3055 rc = mwl8k_set_wmm(hw, 1);
3056
3057 if (!rc)
3058 rc = mwl8k_set_edca_params(hw, queue,
3059 params->cw_min,
3060 params->cw_max,
3061 params->aifs,
3062 params->txop);
3063
3064 mwl8k_fw_unlock(hw);
3065 }
3066
3067 return rc;
3068 }
3069
3070 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3071 struct ieee80211_tx_queue_stats *stats)
3072 {
3073 struct mwl8k_priv *priv = hw->priv;
3074 struct mwl8k_tx_queue *txq;
3075 int index;
3076
3077 spin_lock_bh(&priv->tx_lock);
3078 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3079 txq = priv->txq + index;
3080 memcpy(&stats[index], &txq->stats,
3081 sizeof(struct ieee80211_tx_queue_stats));
3082 }
3083 spin_unlock_bh(&priv->tx_lock);
3084
3085 return 0;
3086 }
3087
3088 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3089 struct ieee80211_low_level_stats *stats)
3090 {
3091 return mwl8k_cmd_802_11_get_stat(hw, stats);
3092 }
3093
3094 static const struct ieee80211_ops mwl8k_ops = {
3095 .tx = mwl8k_tx,
3096 .start = mwl8k_start,
3097 .stop = mwl8k_stop,
3098 .add_interface = mwl8k_add_interface,
3099 .remove_interface = mwl8k_remove_interface,
3100 .config = mwl8k_config,
3101 .bss_info_changed = mwl8k_bss_info_changed,
3102 .prepare_multicast = mwl8k_prepare_multicast,
3103 .configure_filter = mwl8k_configure_filter,
3104 .set_rts_threshold = mwl8k_set_rts_threshold,
3105 .conf_tx = mwl8k_conf_tx,
3106 .get_tx_stats = mwl8k_get_tx_stats,
3107 .get_stats = mwl8k_get_stats,
3108 };
3109
3110 static void mwl8k_tx_reclaim_handler(unsigned long data)
3111 {
3112 int i;
3113 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3114 struct mwl8k_priv *priv = hw->priv;
3115
3116 spin_lock_bh(&priv->tx_lock);
3117 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3118 mwl8k_txq_reclaim(hw, i, 0);
3119
3120 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3121 complete(priv->tx_wait);
3122 priv->tx_wait = NULL;
3123 }
3124 spin_unlock_bh(&priv->tx_lock);
3125 }
3126
3127 static void mwl8k_finalize_join_worker(struct work_struct *work)
3128 {
3129 struct mwl8k_priv *priv =
3130 container_of(work, struct mwl8k_priv, finalize_join_worker);
3131 struct sk_buff *skb = priv->beacon_skb;
3132 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3133
3134 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3135 dev_kfree_skb(skb);
3136
3137 priv->beacon_skb = NULL;
3138 }
3139
3140 static struct mwl8k_device_info di_8687 = {
3141 .part_name = "88w8687",
3142 .helper_image = "mwl8k/helper_8687.fw",
3143 .fw_image = "mwl8k/fmimage_8687.fw",
3144 .rxd_ops = &rxd_8687_ops,
3145 .modes = BIT(NL80211_IFTYPE_STATION),
3146 };
3147
3148 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3149 {
3150 PCI_VDEVICE(MARVELL, 0x2a2b),
3151 .driver_data = (unsigned long)&di_8687,
3152 }, {
3153 PCI_VDEVICE(MARVELL, 0x2a30),
3154 .driver_data = (unsigned long)&di_8687,
3155 }, {
3156 },
3157 };
3158 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3159
3160 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3161 const struct pci_device_id *id)
3162 {
3163 static int printed_version = 0;
3164 struct ieee80211_hw *hw;
3165 struct mwl8k_priv *priv;
3166 int rc;
3167 int i;
3168
3169 if (!printed_version) {
3170 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3171 printed_version = 1;
3172 }
3173
3174 rc = pci_enable_device(pdev);
3175 if (rc) {
3176 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3177 MWL8K_NAME);
3178 return rc;
3179 }
3180
3181 rc = pci_request_regions(pdev, MWL8K_NAME);
3182 if (rc) {
3183 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3184 MWL8K_NAME);
3185 return rc;
3186 }
3187
3188 pci_set_master(pdev);
3189
3190 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3191 if (hw == NULL) {
3192 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3193 rc = -ENOMEM;
3194 goto err_free_reg;
3195 }
3196
3197 priv = hw->priv;
3198 priv->hw = hw;
3199 priv->pdev = pdev;
3200 priv->device_info = (void *)id->driver_data;
3201 priv->rxd_ops = priv->device_info->rxd_ops;
3202 priv->sniffer_enabled = false;
3203 priv->wmm_enabled = false;
3204 priv->pending_tx_pkts = 0;
3205
3206 SET_IEEE80211_DEV(hw, &pdev->dev);
3207 pci_set_drvdata(pdev, hw);
3208
3209 priv->sram = pci_iomap(pdev, 0, 0x10000);
3210 if (priv->sram == NULL) {
3211 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3212 wiphy_name(hw->wiphy));
3213 goto err_iounmap;
3214 }
3215
3216 /*
3217 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3218 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3219 */
3220 priv->regs = pci_iomap(pdev, 1, 0x10000);
3221 if (priv->regs == NULL) {
3222 priv->regs = pci_iomap(pdev, 2, 0x10000);
3223 if (priv->regs == NULL) {
3224 printk(KERN_ERR "%s: Cannot map device registers\n",
3225 wiphy_name(hw->wiphy));
3226 goto err_iounmap;
3227 }
3228 }
3229
3230 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3231 priv->band.band = IEEE80211_BAND_2GHZ;
3232 priv->band.channels = priv->channels;
3233 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3234 priv->band.bitrates = priv->rates;
3235 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3236 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3237
3238 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3239 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3240
3241 /*
3242 * Extra headroom is the size of the required DMA header
3243 * minus the size of the smallest 802.11 frame (CTS frame).
3244 */
3245 hw->extra_tx_headroom =
3246 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3247
3248 hw->channel_change_time = 10;
3249
3250 hw->queues = MWL8K_TX_QUEUES;
3251
3252 hw->wiphy->interface_modes = priv->device_info->modes;
3253
3254 /* Set rssi and noise values to dBm */
3255 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3256 hw->vif_data_size = sizeof(struct mwl8k_vif);
3257 priv->vif = NULL;
3258
3259 /* Set default radio state and preamble */
3260 priv->radio_on = 0;
3261 priv->radio_short_preamble = 0;
3262
3263 /* Finalize join worker */
3264 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3265
3266 /* TX reclaim tasklet */
3267 tasklet_init(&priv->tx_reclaim_task,
3268 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3269 tasklet_disable(&priv->tx_reclaim_task);
3270
3271 /* Power management cookie */
3272 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3273 if (priv->cookie == NULL)
3274 goto err_iounmap;
3275
3276 rc = mwl8k_rxq_init(hw, 0);
3277 if (rc)
3278 goto err_iounmap;
3279 rxq_refill(hw, 0, INT_MAX);
3280
3281 mutex_init(&priv->fw_mutex);
3282 priv->fw_mutex_owner = NULL;
3283 priv->fw_mutex_depth = 0;
3284 priv->hostcmd_wait = NULL;
3285
3286 spin_lock_init(&priv->tx_lock);
3287
3288 priv->tx_wait = NULL;
3289
3290 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3291 rc = mwl8k_txq_init(hw, i);
3292 if (rc)
3293 goto err_free_queues;
3294 }
3295
3296 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3297 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3298 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3299 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3300
3301 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3302 IRQF_SHARED, MWL8K_NAME, hw);
3303 if (rc) {
3304 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3305 wiphy_name(hw->wiphy));
3306 goto err_free_queues;
3307 }
3308
3309 /* Reset firmware and hardware */
3310 mwl8k_hw_reset(priv);
3311
3312 /* Ask userland hotplug daemon for the device firmware */
3313 rc = mwl8k_request_firmware(priv);
3314 if (rc) {
3315 printk(KERN_ERR "%s: Firmware files not found\n",
3316 wiphy_name(hw->wiphy));
3317 goto err_free_irq;
3318 }
3319
3320 /* Load firmware into hardware */
3321 rc = mwl8k_load_firmware(hw);
3322 if (rc) {
3323 printk(KERN_ERR "%s: Cannot start firmware\n",
3324 wiphy_name(hw->wiphy));
3325 goto err_stop_firmware;
3326 }
3327
3328 /* Reclaim memory once firmware is successfully loaded */
3329 mwl8k_release_firmware(priv);
3330
3331 /*
3332 * Temporarily enable interrupts. Initial firmware host
3333 * commands use interrupts and avoids polling. Disable
3334 * interrupts when done.
3335 */
3336 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3337
3338 /* Get config data, mac addrs etc */
3339 if (priv->ap_fw) {
3340 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3341 if (!rc)
3342 rc = mwl8k_cmd_set_hw_spec(hw);
3343 } else {
3344 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3345 }
3346 if (rc) {
3347 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3348 wiphy_name(hw->wiphy));
3349 goto err_stop_firmware;
3350 }
3351
3352 /* Turn radio off */
3353 rc = mwl8k_cmd_802_11_radio_disable(hw);
3354 if (rc) {
3355 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3356 goto err_stop_firmware;
3357 }
3358
3359 /* Clear MAC address */
3360 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3361 if (rc) {
3362 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3363 wiphy_name(hw->wiphy));
3364 goto err_stop_firmware;
3365 }
3366
3367 /* Disable interrupts */
3368 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3369 free_irq(priv->pdev->irq, hw);
3370
3371 rc = ieee80211_register_hw(hw);
3372 if (rc) {
3373 printk(KERN_ERR "%s: Cannot register device\n",
3374 wiphy_name(hw->wiphy));
3375 goto err_stop_firmware;
3376 }
3377
3378 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3379 wiphy_name(hw->wiphy), priv->device_info->part_name,
3380 priv->hw_rev, hw->wiphy->perm_addr,
3381 priv->ap_fw ? "AP" : "STA",
3382 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3383 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3384
3385 return 0;
3386
3387 err_stop_firmware:
3388 mwl8k_hw_reset(priv);
3389 mwl8k_release_firmware(priv);
3390
3391 err_free_irq:
3392 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3393 free_irq(priv->pdev->irq, hw);
3394
3395 err_free_queues:
3396 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3397 mwl8k_txq_deinit(hw, i);
3398 mwl8k_rxq_deinit(hw, 0);
3399
3400 err_iounmap:
3401 if (priv->cookie != NULL)
3402 pci_free_consistent(priv->pdev, 4,
3403 priv->cookie, priv->cookie_dma);
3404
3405 if (priv->regs != NULL)
3406 pci_iounmap(pdev, priv->regs);
3407
3408 if (priv->sram != NULL)
3409 pci_iounmap(pdev, priv->sram);
3410
3411 pci_set_drvdata(pdev, NULL);
3412 ieee80211_free_hw(hw);
3413
3414 err_free_reg:
3415 pci_release_regions(pdev);
3416 pci_disable_device(pdev);
3417
3418 return rc;
3419 }
3420
3421 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3422 {
3423 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3424 }
3425
3426 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3427 {
3428 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3429 struct mwl8k_priv *priv;
3430 int i;
3431
3432 if (hw == NULL)
3433 return;
3434 priv = hw->priv;
3435
3436 ieee80211_stop_queues(hw);
3437
3438 ieee80211_unregister_hw(hw);
3439
3440 /* Remove tx reclaim tasklet */
3441 tasklet_kill(&priv->tx_reclaim_task);
3442
3443 /* Stop hardware */
3444 mwl8k_hw_reset(priv);
3445
3446 /* Return all skbs to mac80211 */
3447 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3448 mwl8k_txq_reclaim(hw, i, 1);
3449
3450 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3451 mwl8k_txq_deinit(hw, i);
3452
3453 mwl8k_rxq_deinit(hw, 0);
3454
3455 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3456
3457 pci_iounmap(pdev, priv->regs);
3458 pci_iounmap(pdev, priv->sram);
3459 pci_set_drvdata(pdev, NULL);
3460 ieee80211_free_hw(hw);
3461 pci_release_regions(pdev);
3462 pci_disable_device(pdev);
3463 }
3464
3465 static struct pci_driver mwl8k_driver = {
3466 .name = MWL8K_NAME,
3467 .id_table = mwl8k_pci_id_table,
3468 .probe = mwl8k_probe,
3469 .remove = __devexit_p(mwl8k_remove),
3470 .shutdown = __devexit_p(mwl8k_shutdown),
3471 };
3472
3473 static int __init mwl8k_init(void)
3474 {
3475 return pci_register_driver(&mwl8k_driver);
3476 }
3477
3478 static void __exit mwl8k_exit(void)
3479 {
3480 pci_unregister_driver(&mwl8k_driver);
3481 }
3482
3483 module_init(mwl8k_init);
3484 module_exit(mwl8k_exit);
3485
3486 MODULE_DESCRIPTION(MWL8K_DESC);
3487 MODULE_VERSION(MWL8K_VERSION);
3488 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3489 MODULE_LICENSE("GPL");
Motorola kernel-slsi