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[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
26
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
30
31 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
32 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
33 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
34 { }
35 };
36 MODULE_DEVICE_TABLE(pci, mwl8k_table);
37
38 /* Register definitions */
39 #define MWL8K_HIU_GEN_PTR 0x00000c10
40 #define MWL8K_MODE_STA 0x0000005a
41 #define MWL8K_MODE_AP 0x000000a5
42 #define MWL8K_HIU_INT_CODE 0x00000c14
43 #define MWL8K_FWSTA_READY 0xf0f1f2f4
44 #define MWL8K_FWAP_READY 0xf1f2f4a5
45 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
46 #define MWL8K_HIU_SCRATCH 0x00000c40
47
48 /* Host->device communications */
49 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
54 #define MWL8K_H2A_INT_DUMMY (1 << 20)
55 #define MWL8K_H2A_INT_RESET (1 << 15)
56 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
57 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
58
59 /* Device->host communications */
60 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
65 #define MWL8K_A2H_INT_DUMMY (1 << 20)
66 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
67 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
68 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
69 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
70 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
71 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
72 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
73 #define MWL8K_A2H_INT_RX_READY (1 << 1)
74 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
75
76 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
77 MWL8K_A2H_INT_CHNL_SWITCHED | \
78 MWL8K_A2H_INT_QUEUE_EMPTY | \
79 MWL8K_A2H_INT_RADAR_DETECT | \
80 MWL8K_A2H_INT_RADIO_ON | \
81 MWL8K_A2H_INT_RADIO_OFF | \
82 MWL8K_A2H_INT_MAC_EVENT | \
83 MWL8K_A2H_INT_OPC_DONE | \
84 MWL8K_A2H_INT_RX_READY | \
85 MWL8K_A2H_INT_TX_DONE)
86
87 #define MWL8K_RX_QUEUES 1
88 #define MWL8K_TX_QUEUES 4
89
90 struct mwl8k_rx_queue {
91 int rx_desc_count;
92
93 /* hw receives here */
94 int rx_head;
95
96 /* refill descs here */
97 int rx_tail;
98
99 struct mwl8k_rx_desc *rx_desc_area;
100 dma_addr_t rx_desc_dma;
101 struct sk_buff **rx_skb;
102 };
103
104 struct mwl8k_tx_queue {
105 /* hw transmits here */
106 int tx_head;
107
108 /* sw appends here */
109 int tx_tail;
110
111 struct ieee80211_tx_queue_stats tx_stats;
112 struct mwl8k_tx_desc *tx_desc_area;
113 dma_addr_t tx_desc_dma;
114 struct sk_buff **tx_skb;
115 };
116
117 /* Pointers to the firmware data and meta information about it. */
118 struct mwl8k_firmware {
119 /* Microcode */
120 struct firmware *ucode;
121
122 /* Boot helper code */
123 struct firmware *helper;
124 };
125
126 struct mwl8k_priv {
127 void __iomem *regs;
128 struct ieee80211_hw *hw;
129
130 struct pci_dev *pdev;
131
132 /* firmware files and meta data */
133 struct mwl8k_firmware fw;
134 u32 part_num;
135
136 /* firmware access */
137 struct mutex fw_mutex;
138 struct task_struct *fw_mutex_owner;
139 int fw_mutex_depth;
140 struct completion *hostcmd_wait;
141
142 /* lock held over TX and TX reap */
143 spinlock_t tx_lock;
144
145 /* TX quiesce completion, protected by fw_mutex and tx_lock */
146 struct completion *tx_wait;
147
148 struct ieee80211_vif *vif;
149
150 struct ieee80211_channel *current_channel;
151
152 /* power management status cookie from firmware */
153 u32 *cookie;
154 dma_addr_t cookie_dma;
155
156 u16 num_mcaddrs;
157 u8 hw_rev;
158 u32 fw_rev;
159
160 /*
161 * Running count of TX packets in flight, to avoid
162 * iterating over the transmit rings each time.
163 */
164 int pending_tx_pkts;
165
166 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
167 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
168
169 /* PHY parameters */
170 struct ieee80211_supported_band band;
171 struct ieee80211_channel channels[14];
172 struct ieee80211_rate rates[13];
173
174 bool radio_on;
175 bool radio_short_preamble;
176 bool sniffer_enabled;
177 bool wmm_enabled;
178
179 /* XXX need to convert this to handle multiple interfaces */
180 bool capture_beacon;
181 u8 capture_bssid[ETH_ALEN];
182 struct sk_buff *beacon_skb;
183
184 /*
185 * This FJ worker has to be global as it is scheduled from the
186 * RX handler. At this point we don't know which interface it
187 * belongs to until the list of bssids waiting to complete join
188 * is checked.
189 */
190 struct work_struct finalize_join_worker;
191
192 /* Tasklet to reclaim TX descriptors and buffers after tx */
193 struct tasklet_struct tx_reclaim_task;
194 };
195
196 /* Per interface specific private data */
197 struct mwl8k_vif {
198 /* backpointer to parent config block */
199 struct mwl8k_priv *priv;
200
201 /* BSS config of AP or IBSS from mac80211*/
202 struct ieee80211_bss_conf bss_info;
203
204 /* BSSID of AP or IBSS */
205 u8 bssid[ETH_ALEN];
206 u8 mac_addr[ETH_ALEN];
207
208 /*
209 * Subset of supported legacy rates.
210 * Intersection of AP and STA supported rates.
211 */
212 struct ieee80211_rate legacy_rates[13];
213
214 /* number of supported legacy rates */
215 u8 legacy_nrates;
216
217 /* Index into station database.Returned by update_sta_db call */
218 u8 peer_id;
219
220 /* Non AMPDU sequence number assigned by driver */
221 u16 seqno;
222 };
223
224 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
225
226 static const struct ieee80211_channel mwl8k_channels[] = {
227 { .center_freq = 2412, .hw_value = 1, },
228 { .center_freq = 2417, .hw_value = 2, },
229 { .center_freq = 2422, .hw_value = 3, },
230 { .center_freq = 2427, .hw_value = 4, },
231 { .center_freq = 2432, .hw_value = 5, },
232 { .center_freq = 2437, .hw_value = 6, },
233 { .center_freq = 2442, .hw_value = 7, },
234 { .center_freq = 2447, .hw_value = 8, },
235 { .center_freq = 2452, .hw_value = 9, },
236 { .center_freq = 2457, .hw_value = 10, },
237 { .center_freq = 2462, .hw_value = 11, },
238 };
239
240 static const struct ieee80211_rate mwl8k_rates[] = {
241 { .bitrate = 10, .hw_value = 2, },
242 { .bitrate = 20, .hw_value = 4, },
243 { .bitrate = 55, .hw_value = 11, },
244 { .bitrate = 110, .hw_value = 22, },
245 { .bitrate = 220, .hw_value = 44, },
246 { .bitrate = 60, .hw_value = 12, },
247 { .bitrate = 90, .hw_value = 18, },
248 { .bitrate = 120, .hw_value = 24, },
249 { .bitrate = 180, .hw_value = 36, },
250 { .bitrate = 240, .hw_value = 48, },
251 { .bitrate = 360, .hw_value = 72, },
252 { .bitrate = 480, .hw_value = 96, },
253 { .bitrate = 540, .hw_value = 108, },
254 };
255
256 /* Set or get info from Firmware */
257 #define MWL8K_CMD_SET 0x0001
258 #define MWL8K_CMD_GET 0x0000
259
260 /* Firmware command codes */
261 #define MWL8K_CMD_CODE_DNLD 0x0001
262 #define MWL8K_CMD_GET_HW_SPEC 0x0003
263 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
264 #define MWL8K_CMD_GET_STAT 0x0014
265 #define MWL8K_CMD_RADIO_CONTROL 0x001c
266 #define MWL8K_CMD_RF_TX_POWER 0x001e
267 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
268 #define MWL8K_CMD_SET_POST_SCAN 0x0108
269 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
270 #define MWL8K_CMD_SET_AID 0x010d
271 #define MWL8K_CMD_SET_RATE 0x0110
272 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
273 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
274 #define MWL8K_CMD_SET_SLOT 0x0114
275 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
276 #define MWL8K_CMD_SET_WMM_MODE 0x0123
277 #define MWL8K_CMD_MIMO_CONFIG 0x0125
278 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
279 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
280 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
281 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
282 #define MWL8K_CMD_UPDATE_STADB 0x1123
283
284 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
285 {
286 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
287 snprintf(buf, bufsize, "%s", #x);\
288 return buf;\
289 } while (0)
290 switch (cmd & ~0x8000) {
291 MWL8K_CMDNAME(CODE_DNLD);
292 MWL8K_CMDNAME(GET_HW_SPEC);
293 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
294 MWL8K_CMDNAME(GET_STAT);
295 MWL8K_CMDNAME(RADIO_CONTROL);
296 MWL8K_CMDNAME(RF_TX_POWER);
297 MWL8K_CMDNAME(SET_PRE_SCAN);
298 MWL8K_CMDNAME(SET_POST_SCAN);
299 MWL8K_CMDNAME(SET_RF_CHANNEL);
300 MWL8K_CMDNAME(SET_AID);
301 MWL8K_CMDNAME(SET_RATE);
302 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
303 MWL8K_CMDNAME(RTS_THRESHOLD);
304 MWL8K_CMDNAME(SET_SLOT);
305 MWL8K_CMDNAME(SET_EDCA_PARAMS);
306 MWL8K_CMDNAME(SET_WMM_MODE);
307 MWL8K_CMDNAME(MIMO_CONFIG);
308 MWL8K_CMDNAME(USE_FIXED_RATE);
309 MWL8K_CMDNAME(ENABLE_SNIFFER);
310 MWL8K_CMDNAME(SET_MAC_ADDR);
311 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
312 MWL8K_CMDNAME(UPDATE_STADB);
313 default:
314 snprintf(buf, bufsize, "0x%x", cmd);
315 }
316 #undef MWL8K_CMDNAME
317
318 return buf;
319 }
320
321 /* Hardware and firmware reset */
322 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
323 {
324 iowrite32(MWL8K_H2A_INT_RESET,
325 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
326 iowrite32(MWL8K_H2A_INT_RESET,
327 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
328 msleep(20);
329 }
330
331 /* Release fw image */
332 static void mwl8k_release_fw(struct firmware **fw)
333 {
334 if (*fw == NULL)
335 return;
336 release_firmware(*fw);
337 *fw = NULL;
338 }
339
340 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
341 {
342 mwl8k_release_fw(&priv->fw.ucode);
343 mwl8k_release_fw(&priv->fw.helper);
344 }
345
346 /* Request fw image */
347 static int mwl8k_request_fw(struct mwl8k_priv *priv,
348 const char *fname, struct firmware **fw)
349 {
350 /* release current image */
351 if (*fw != NULL)
352 mwl8k_release_fw(fw);
353
354 return request_firmware((const struct firmware **)fw,
355 fname, &priv->pdev->dev);
356 }
357
358 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
359 {
360 u8 filename[64];
361 int rc;
362
363 priv->part_num = part_num;
364
365 snprintf(filename, sizeof(filename),
366 "mwl8k/helper_%u.fw", priv->part_num);
367
368 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
369 if (rc) {
370 printk(KERN_ERR "%s: Error requesting helper firmware "
371 "file %s\n", pci_name(priv->pdev), filename);
372 return rc;
373 }
374
375 snprintf(filename, sizeof(filename),
376 "mwl8k/fmimage_%u.fw", priv->part_num);
377
378 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
379 if (rc) {
380 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
381 pci_name(priv->pdev), filename);
382 mwl8k_release_fw(&priv->fw.helper);
383 return rc;
384 }
385
386 return 0;
387 }
388
389 struct mwl8k_cmd_pkt {
390 __le16 code;
391 __le16 length;
392 __le16 seq_num;
393 __le16 result;
394 char payload[0];
395 } __attribute__((packed));
396
397 /*
398 * Firmware loading.
399 */
400 static int
401 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
402 {
403 void __iomem *regs = priv->regs;
404 dma_addr_t dma_addr;
405 int loops;
406
407 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
408 if (pci_dma_mapping_error(priv->pdev, dma_addr))
409 return -ENOMEM;
410
411 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
412 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
413 iowrite32(MWL8K_H2A_INT_DOORBELL,
414 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
415 iowrite32(MWL8K_H2A_INT_DUMMY,
416 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
417
418 loops = 1000;
419 do {
420 u32 int_code;
421
422 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
423 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
424 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
425 break;
426 }
427
428 cond_resched();
429 udelay(1);
430 } while (--loops);
431
432 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
433
434 return loops ? 0 : -ETIMEDOUT;
435 }
436
437 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
438 const u8 *data, size_t length)
439 {
440 struct mwl8k_cmd_pkt *cmd;
441 int done;
442 int rc = 0;
443
444 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
445 if (cmd == NULL)
446 return -ENOMEM;
447
448 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
449 cmd->seq_num = 0;
450 cmd->result = 0;
451
452 done = 0;
453 while (length) {
454 int block_size = length > 256 ? 256 : length;
455
456 memcpy(cmd->payload, data + done, block_size);
457 cmd->length = cpu_to_le16(block_size);
458
459 rc = mwl8k_send_fw_load_cmd(priv, cmd,
460 sizeof(*cmd) + block_size);
461 if (rc)
462 break;
463
464 done += block_size;
465 length -= block_size;
466 }
467
468 if (!rc) {
469 cmd->length = 0;
470 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
471 }
472
473 kfree(cmd);
474
475 return rc;
476 }
477
478 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
479 const u8 *data, size_t length)
480 {
481 unsigned char *buffer;
482 int may_continue, rc = 0;
483 u32 done, prev_block_size;
484
485 buffer = kmalloc(1024, GFP_KERNEL);
486 if (buffer == NULL)
487 return -ENOMEM;
488
489 done = 0;
490 prev_block_size = 0;
491 may_continue = 1000;
492 while (may_continue > 0) {
493 u32 block_size;
494
495 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
496 if (block_size & 1) {
497 block_size &= ~1;
498 may_continue--;
499 } else {
500 done += prev_block_size;
501 length -= prev_block_size;
502 }
503
504 if (block_size > 1024 || block_size > length) {
505 rc = -EOVERFLOW;
506 break;
507 }
508
509 if (length == 0) {
510 rc = 0;
511 break;
512 }
513
514 if (block_size == 0) {
515 rc = -EPROTO;
516 may_continue--;
517 udelay(1);
518 continue;
519 }
520
521 prev_block_size = block_size;
522 memcpy(buffer, data + done, block_size);
523
524 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
525 if (rc)
526 break;
527 }
528
529 if (!rc && length != 0)
530 rc = -EREMOTEIO;
531
532 kfree(buffer);
533
534 return rc;
535 }
536
537 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
538 {
539 struct mwl8k_priv *priv = hw->priv;
540 struct firmware *fw = priv->fw.ucode;
541 int rc;
542 int loops;
543
544 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
545 struct firmware *helper = priv->fw.helper;
546
547 if (helper == NULL) {
548 printk(KERN_ERR "%s: helper image needed but none "
549 "given\n", pci_name(priv->pdev));
550 return -EINVAL;
551 }
552
553 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
554 if (rc) {
555 printk(KERN_ERR "%s: unable to load firmware "
556 "helper image\n", pci_name(priv->pdev));
557 return rc;
558 }
559 msleep(1);
560
561 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
562 } else {
563 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
564 }
565
566 if (rc) {
567 printk(KERN_ERR "%s: unable to load firmware image\n",
568 pci_name(priv->pdev));
569 return rc;
570 }
571
572 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
573 msleep(1);
574
575 loops = 200000;
576 do {
577 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
578 == MWL8K_FWSTA_READY)
579 break;
580 udelay(1);
581 } while (--loops);
582
583 return loops ? 0 : -ETIMEDOUT;
584 }
585
586
587 /*
588 * Defines shared between transmission and reception.
589 */
590 /* HT control fields for firmware */
591 struct ewc_ht_info {
592 __le16 control1;
593 __le16 control2;
594 __le16 control3;
595 } __attribute__((packed));
596
597 /* Firmware Station database operations */
598 #define MWL8K_STA_DB_ADD_ENTRY 0
599 #define MWL8K_STA_DB_MODIFY_ENTRY 1
600 #define MWL8K_STA_DB_DEL_ENTRY 2
601 #define MWL8K_STA_DB_FLUSH 3
602
603 /* Peer Entry flags - used to define the type of the peer node */
604 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
605
606 #define MWL8K_IEEE_LEGACY_DATA_RATES 13
607 #define MWL8K_MCS_BITMAP_SIZE 16
608
609 struct peer_capability_info {
610 /* Peer type - AP vs. STA. */
611 __u8 peer_type;
612
613 /* Basic 802.11 capabilities from assoc resp. */
614 __le16 basic_caps;
615
616 /* Set if peer supports 802.11n high throughput (HT). */
617 __u8 ht_support;
618
619 /* Valid if HT is supported. */
620 __le16 ht_caps;
621 __u8 extended_ht_caps;
622 struct ewc_ht_info ewc_info;
623
624 /* Legacy rate table. Intersection of our rates and peer rates. */
625 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
626
627 /* HT rate table. Intersection of our rates and peer rates. */
628 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
629 __u8 pad[16];
630
631 /* If set, interoperability mode, no proprietary extensions. */
632 __u8 interop;
633 __u8 pad2;
634 __u8 station_id;
635 __le16 amsdu_enabled;
636 } __attribute__((packed));
637
638 /* Inline functions to manipulate QoS field in data descriptor. */
639 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
640 {
641 u16 val_mask = 1 << 4;
642
643 /* End of Service Period Bit 4 */
644 return qos | val_mask;
645 }
646
647 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
648 {
649 u16 val_mask = 0x3;
650 u8 shift = 5;
651 u16 qos_mask = ~(val_mask << shift);
652
653 /* Ack Policy Bit 5-6 */
654 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
655 }
656
657 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
658 {
659 u16 val_mask = 1 << 7;
660
661 /* AMSDU present Bit 7 */
662 return qos | val_mask;
663 }
664
665 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
666 {
667 u16 val_mask = 0xff;
668 u8 shift = 8;
669 u16 qos_mask = ~(val_mask << shift);
670
671 /* Queue Length Bits 8-15 */
672 return (qos & qos_mask) | ((len & val_mask) << shift);
673 }
674
675 /* DMA header used by firmware and hardware. */
676 struct mwl8k_dma_data {
677 __le16 fwlen;
678 struct ieee80211_hdr wh;
679 } __attribute__((packed));
680
681 /* Routines to add/remove DMA header from skb. */
682 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
683 {
684 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
685 void *dst, *src = &tr->wh;
686 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
687 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
688
689 dst = (void *)tr + space;
690 if (dst != src) {
691 memmove(dst, src, hdrlen);
692 skb_pull(skb, space);
693 }
694 }
695
696 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
697 {
698 struct ieee80211_hdr *wh;
699 u32 hdrlen, pktlen;
700 struct mwl8k_dma_data *tr;
701
702 wh = (struct ieee80211_hdr *)skb->data;
703 hdrlen = ieee80211_hdrlen(wh->frame_control);
704 pktlen = skb->len;
705
706 /*
707 * Copy up/down the 802.11 header; the firmware requires
708 * we present a 2-byte payload length followed by a
709 * 4-address header (w/o QoS), followed (optionally) by
710 * any WEP/ExtIV header (but only filled in for CCMP).
711 */
712 if (hdrlen != sizeof(struct mwl8k_dma_data))
713 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
714
715 tr = (struct mwl8k_dma_data *)skb->data;
716 if (wh != &tr->wh)
717 memmove(&tr->wh, wh, hdrlen);
718
719 /* Clear addr4 */
720 memset(tr->wh.addr4, 0, ETH_ALEN);
721
722 /*
723 * Firmware length is the length of the fully formed "802.11
724 * payload". That is, everything except for the 802.11 header.
725 * This includes all crypto material including the MIC.
726 */
727 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
728 }
729
730
731 /*
732 * Packet reception.
733 */
734 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
735
736 struct mwl8k_rx_desc {
737 __le16 pkt_len;
738 __u8 link_quality;
739 __u8 noise_level;
740 __le32 pkt_phys_addr;
741 __le32 next_rx_desc_phys_addr;
742 __le16 qos_control;
743 __le16 rate_info;
744 __le32 pad0[4];
745 __u8 rssi;
746 __u8 channel;
747 __le16 pad1;
748 __u8 rx_ctrl;
749 __u8 rx_status;
750 __u8 pad2[2];
751 } __attribute__((packed));
752
753 #define MWL8K_RX_DESCS 256
754 #define MWL8K_RX_MAXSZ 3800
755
756 #define RATE_INFO_SHORTPRE 0x8000
757 #define RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
758 #define RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
759 #define RATE_INFO_40MHZ 0x0004
760 #define RATE_INFO_SHORTGI 0x0002
761 #define RATE_INFO_MCS_FORMAT 0x0001
762
763 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
764 {
765 struct mwl8k_priv *priv = hw->priv;
766 struct mwl8k_rx_queue *rxq = priv->rxq + index;
767 int size;
768 int i;
769
770 rxq->rx_desc_count = 0;
771 rxq->rx_head = 0;
772 rxq->rx_tail = 0;
773
774 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
775
776 rxq->rx_desc_area =
777 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
778 if (rxq->rx_desc_area == NULL) {
779 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
780 wiphy_name(hw->wiphy));
781 return -ENOMEM;
782 }
783 memset(rxq->rx_desc_area, 0, size);
784
785 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
786 sizeof(*rxq->rx_skb), GFP_KERNEL);
787 if (rxq->rx_skb == NULL) {
788 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
789 wiphy_name(hw->wiphy));
790 pci_free_consistent(priv->pdev, size,
791 rxq->rx_desc_area, rxq->rx_desc_dma);
792 return -ENOMEM;
793 }
794 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
795
796 for (i = 0; i < MWL8K_RX_DESCS; i++) {
797 struct mwl8k_rx_desc *rx_desc;
798 int nexti;
799
800 rx_desc = rxq->rx_desc_area + i;
801 nexti = (i + 1) % MWL8K_RX_DESCS;
802
803 rx_desc->next_rx_desc_phys_addr =
804 cpu_to_le32(rxq->rx_desc_dma
805 + nexti * sizeof(*rx_desc));
806 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
807 }
808
809 return 0;
810 }
811
812 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
813 {
814 struct mwl8k_priv *priv = hw->priv;
815 struct mwl8k_rx_queue *rxq = priv->rxq + index;
816 int refilled;
817
818 refilled = 0;
819 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
820 struct sk_buff *skb;
821 int rx;
822
823 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
824 if (skb == NULL)
825 break;
826
827 rxq->rx_desc_count++;
828
829 rx = rxq->rx_tail;
830 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
831
832 rxq->rx_desc_area[rx].pkt_phys_addr =
833 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
834 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
835
836 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
837 rxq->rx_skb[rx] = skb;
838 wmb();
839 rxq->rx_desc_area[rx].rx_ctrl = 0;
840
841 refilled++;
842 }
843
844 return refilled;
845 }
846
847 /* Must be called only when the card's reception is completely halted */
848 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
849 {
850 struct mwl8k_priv *priv = hw->priv;
851 struct mwl8k_rx_queue *rxq = priv->rxq + index;
852 int i;
853
854 for (i = 0; i < MWL8K_RX_DESCS; i++) {
855 if (rxq->rx_skb[i] != NULL) {
856 unsigned long addr;
857
858 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
859 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
860 PCI_DMA_FROMDEVICE);
861 kfree_skb(rxq->rx_skb[i]);
862 rxq->rx_skb[i] = NULL;
863 }
864 }
865
866 kfree(rxq->rx_skb);
867 rxq->rx_skb = NULL;
868
869 pci_free_consistent(priv->pdev,
870 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
871 rxq->rx_desc_area, rxq->rx_desc_dma);
872 rxq->rx_desc_area = NULL;
873 }
874
875
876 /*
877 * Scan a list of BSSIDs to process for finalize join.
878 * Allows for extension to process multiple BSSIDs.
879 */
880 static inline int
881 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
882 {
883 return priv->capture_beacon &&
884 ieee80211_is_beacon(wh->frame_control) &&
885 !compare_ether_addr(wh->addr3, priv->capture_bssid);
886 }
887
888 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
889 struct sk_buff *skb)
890 {
891 struct mwl8k_priv *priv = hw->priv;
892
893 priv->capture_beacon = false;
894 memset(priv->capture_bssid, 0, ETH_ALEN);
895
896 /*
897 * Use GFP_ATOMIC as rxq_process is called from
898 * the primary interrupt handler, memory allocation call
899 * must not sleep.
900 */
901 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
902 if (priv->beacon_skb != NULL)
903 ieee80211_queue_work(hw, &priv->finalize_join_worker);
904 }
905
906 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
907 {
908 struct mwl8k_priv *priv = hw->priv;
909 struct mwl8k_rx_queue *rxq = priv->rxq + index;
910 int processed;
911
912 processed = 0;
913 while (rxq->rx_desc_count && limit--) {
914 struct mwl8k_rx_desc *rx_desc;
915 struct sk_buff *skb;
916 struct ieee80211_rx_status status;
917 unsigned long addr;
918 struct ieee80211_hdr *wh;
919 u16 rate_info;
920
921 rx_desc = rxq->rx_desc_area + rxq->rx_head;
922 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
923 break;
924 rmb();
925
926 skb = rxq->rx_skb[rxq->rx_head];
927 if (skb == NULL)
928 break;
929 rxq->rx_skb[rxq->rx_head] = NULL;
930
931 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
932 rxq->rx_desc_count--;
933
934 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
935 pci_unmap_single(priv->pdev, addr,
936 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
937
938 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
939 mwl8k_remove_dma_header(skb);
940
941 wh = (struct ieee80211_hdr *)skb->data;
942
943 /*
944 * Check for a pending join operation. Save a
945 * copy of the beacon and schedule a tasklet to
946 * send a FINALIZE_JOIN command to the firmware.
947 */
948 if (mwl8k_capture_bssid(priv, wh))
949 mwl8k_save_beacon(hw, skb);
950
951 rate_info = le16_to_cpu(rx_desc->rate_info);
952
953 memset(&status, 0, sizeof(status));
954 status.mactime = 0;
955 status.signal = -rx_desc->rssi;
956 status.noise = -rx_desc->noise_level;
957 status.qual = rx_desc->link_quality;
958 status.antenna = RATE_INFO_ANTSELECT(rate_info);
959 status.rate_idx = RATE_INFO_RATEID(rate_info);
960 status.flag = 0;
961 if (rate_info & RATE_INFO_SHORTPRE)
962 status.flag |= RX_FLAG_SHORTPRE;
963 if (rate_info & RATE_INFO_40MHZ)
964 status.flag |= RX_FLAG_40MHZ;
965 if (rate_info & RATE_INFO_SHORTGI)
966 status.flag |= RX_FLAG_SHORT_GI;
967 if (rate_info & RATE_INFO_MCS_FORMAT)
968 status.flag |= RX_FLAG_HT;
969 status.band = IEEE80211_BAND_2GHZ;
970 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
971 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
972 ieee80211_rx_irqsafe(hw, skb);
973
974 processed++;
975 }
976
977 return processed;
978 }
979
980
981 /*
982 * Packet transmission.
983 */
984
985 /* Transmit packet ACK policy */
986 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
987 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
988
989 #define MWL8K_TXD_STATUS_OK 0x00000001
990 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
991 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
992 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
993 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
994
995 struct mwl8k_tx_desc {
996 __le32 status;
997 __u8 data_rate;
998 __u8 tx_priority;
999 __le16 qos_control;
1000 __le32 pkt_phys_addr;
1001 __le16 pkt_len;
1002 __u8 dest_MAC_addr[ETH_ALEN];
1003 __le32 next_tx_desc_phys_addr;
1004 __le32 reserved;
1005 __le16 rate_info;
1006 __u8 peer_id;
1007 __u8 tx_frag_cnt;
1008 } __attribute__((packed));
1009
1010 #define MWL8K_TX_DESCS 128
1011
1012 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1013 {
1014 struct mwl8k_priv *priv = hw->priv;
1015 struct mwl8k_tx_queue *txq = priv->txq + index;
1016 int size;
1017 int i;
1018
1019 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1020 txq->tx_stats.limit = MWL8K_TX_DESCS;
1021 txq->tx_head = 0;
1022 txq->tx_tail = 0;
1023
1024 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1025
1026 txq->tx_desc_area =
1027 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1028 if (txq->tx_desc_area == NULL) {
1029 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1030 wiphy_name(hw->wiphy));
1031 return -ENOMEM;
1032 }
1033 memset(txq->tx_desc_area, 0, size);
1034
1035 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1036 GFP_KERNEL);
1037 if (txq->tx_skb == NULL) {
1038 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1039 wiphy_name(hw->wiphy));
1040 pci_free_consistent(priv->pdev, size,
1041 txq->tx_desc_area, txq->tx_desc_dma);
1042 return -ENOMEM;
1043 }
1044 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1045
1046 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1047 struct mwl8k_tx_desc *tx_desc;
1048 int nexti;
1049
1050 tx_desc = txq->tx_desc_area + i;
1051 nexti = (i + 1) % MWL8K_TX_DESCS;
1052
1053 tx_desc->status = 0;
1054 tx_desc->next_tx_desc_phys_addr =
1055 cpu_to_le32(txq->tx_desc_dma +
1056 nexti * sizeof(*tx_desc));
1057 }
1058
1059 return 0;
1060 }
1061
1062 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1063 {
1064 iowrite32(MWL8K_H2A_INT_PPA_READY,
1065 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1066 iowrite32(MWL8K_H2A_INT_DUMMY,
1067 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1068 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1069 }
1070
1071 struct mwl8k_txq_info {
1072 u32 fw_owned;
1073 u32 drv_owned;
1074 u32 unused;
1075 u32 len;
1076 u32 head;
1077 u32 tail;
1078 };
1079
1080 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1081 struct mwl8k_txq_info *txinfo)
1082 {
1083 int count, desc, status;
1084 struct mwl8k_tx_queue *txq;
1085 struct mwl8k_tx_desc *tx_desc;
1086 int ndescs = 0;
1087
1088 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1089
1090 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1091 txq = priv->txq + count;
1092 txinfo[count].len = txq->tx_stats.len;
1093 txinfo[count].head = txq->tx_head;
1094 txinfo[count].tail = txq->tx_tail;
1095 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1096 tx_desc = txq->tx_desc_area + desc;
1097 status = le32_to_cpu(tx_desc->status);
1098
1099 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1100 txinfo[count].fw_owned++;
1101 else
1102 txinfo[count].drv_owned++;
1103
1104 if (tx_desc->pkt_len == 0)
1105 txinfo[count].unused++;
1106 }
1107 }
1108
1109 return ndescs;
1110 }
1111
1112 /*
1113 * Must be called with priv->fw_mutex held and tx queues stopped.
1114 */
1115 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1116 {
1117 struct mwl8k_priv *priv = hw->priv;
1118 DECLARE_COMPLETION_ONSTACK(tx_wait);
1119 u32 count;
1120 unsigned long timeout;
1121
1122 might_sleep();
1123
1124 spin_lock_bh(&priv->tx_lock);
1125 count = priv->pending_tx_pkts;
1126 if (count)
1127 priv->tx_wait = &tx_wait;
1128 spin_unlock_bh(&priv->tx_lock);
1129
1130 if (count) {
1131 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1132 int index;
1133 int newcount;
1134
1135 timeout = wait_for_completion_timeout(&tx_wait,
1136 msecs_to_jiffies(5000));
1137 if (timeout)
1138 return 0;
1139
1140 spin_lock_bh(&priv->tx_lock);
1141 priv->tx_wait = NULL;
1142 newcount = priv->pending_tx_pkts;
1143 mwl8k_scan_tx_ring(priv, txinfo);
1144 spin_unlock_bh(&priv->tx_lock);
1145
1146 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1147 __func__, __LINE__, count, newcount);
1148
1149 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1150 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1151 "DRV:%u U:%u\n",
1152 index,
1153 txinfo[index].len,
1154 txinfo[index].head,
1155 txinfo[index].tail,
1156 txinfo[index].fw_owned,
1157 txinfo[index].drv_owned,
1158 txinfo[index].unused);
1159
1160 return -ETIMEDOUT;
1161 }
1162
1163 return 0;
1164 }
1165
1166 #define MWL8K_TXD_SUCCESS(status) \
1167 ((status) & (MWL8K_TXD_STATUS_OK | \
1168 MWL8K_TXD_STATUS_OK_RETRY | \
1169 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1170
1171 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1172 {
1173 struct mwl8k_priv *priv = hw->priv;
1174 struct mwl8k_tx_queue *txq = priv->txq + index;
1175 int wake = 0;
1176
1177 while (txq->tx_stats.len > 0) {
1178 int tx;
1179 struct mwl8k_tx_desc *tx_desc;
1180 unsigned long addr;
1181 int size;
1182 struct sk_buff *skb;
1183 struct ieee80211_tx_info *info;
1184 u32 status;
1185
1186 tx = txq->tx_head;
1187 tx_desc = txq->tx_desc_area + tx;
1188
1189 status = le32_to_cpu(tx_desc->status);
1190
1191 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1192 if (!force)
1193 break;
1194 tx_desc->status &=
1195 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1196 }
1197
1198 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1199 BUG_ON(txq->tx_stats.len == 0);
1200 txq->tx_stats.len--;
1201 priv->pending_tx_pkts--;
1202
1203 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1204 size = le16_to_cpu(tx_desc->pkt_len);
1205 skb = txq->tx_skb[tx];
1206 txq->tx_skb[tx] = NULL;
1207
1208 BUG_ON(skb == NULL);
1209 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1210
1211 mwl8k_remove_dma_header(skb);
1212
1213 /* Mark descriptor as unused */
1214 tx_desc->pkt_phys_addr = 0;
1215 tx_desc->pkt_len = 0;
1216
1217 info = IEEE80211_SKB_CB(skb);
1218 ieee80211_tx_info_clear_status(info);
1219 if (MWL8K_TXD_SUCCESS(status))
1220 info->flags |= IEEE80211_TX_STAT_ACK;
1221
1222 ieee80211_tx_status_irqsafe(hw, skb);
1223
1224 wake = 1;
1225 }
1226
1227 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1228 ieee80211_wake_queue(hw, index);
1229 }
1230
1231 /* must be called only when the card's transmit is completely halted */
1232 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1233 {
1234 struct mwl8k_priv *priv = hw->priv;
1235 struct mwl8k_tx_queue *txq = priv->txq + index;
1236
1237 mwl8k_txq_reclaim(hw, index, 1);
1238
1239 kfree(txq->tx_skb);
1240 txq->tx_skb = NULL;
1241
1242 pci_free_consistent(priv->pdev,
1243 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1244 txq->tx_desc_area, txq->tx_desc_dma);
1245 txq->tx_desc_area = NULL;
1246 }
1247
1248 static int
1249 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1250 {
1251 struct mwl8k_priv *priv = hw->priv;
1252 struct ieee80211_tx_info *tx_info;
1253 struct mwl8k_vif *mwl8k_vif;
1254 struct ieee80211_hdr *wh;
1255 struct mwl8k_tx_queue *txq;
1256 struct mwl8k_tx_desc *tx;
1257 dma_addr_t dma;
1258 u32 txstatus;
1259 u8 txdatarate;
1260 u16 qos;
1261
1262 wh = (struct ieee80211_hdr *)skb->data;
1263 if (ieee80211_is_data_qos(wh->frame_control))
1264 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1265 else
1266 qos = 0;
1267
1268 mwl8k_add_dma_header(skb);
1269 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1270
1271 tx_info = IEEE80211_SKB_CB(skb);
1272 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1273
1274 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1275 u16 seqno = mwl8k_vif->seqno;
1276
1277 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1278 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1279 mwl8k_vif->seqno = seqno++ % 4096;
1280 }
1281
1282 /* Setup firmware control bit fields for each frame type. */
1283 txstatus = 0;
1284 txdatarate = 0;
1285 if (ieee80211_is_mgmt(wh->frame_control) ||
1286 ieee80211_is_ctl(wh->frame_control)) {
1287 txdatarate = 0;
1288 qos = mwl8k_qos_setbit_eosp(qos);
1289 /* Set Queue size to unspecified */
1290 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1291 } else if (ieee80211_is_data(wh->frame_control)) {
1292 txdatarate = 1;
1293 if (is_multicast_ether_addr(wh->addr1))
1294 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1295
1296 /* Send pkt in an aggregate if AMPDU frame. */
1297 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1298 qos = mwl8k_qos_setbit_ack(qos,
1299 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1300 else
1301 qos = mwl8k_qos_setbit_ack(qos,
1302 MWL8K_TXD_ACK_POLICY_NORMAL);
1303
1304 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1305 qos = mwl8k_qos_setbit_amsdu(qos);
1306 }
1307
1308 dma = pci_map_single(priv->pdev, skb->data,
1309 skb->len, PCI_DMA_TODEVICE);
1310
1311 if (pci_dma_mapping_error(priv->pdev, dma)) {
1312 printk(KERN_DEBUG "%s: failed to dma map skb, "
1313 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1314 dev_kfree_skb(skb);
1315 return NETDEV_TX_OK;
1316 }
1317
1318 spin_lock_bh(&priv->tx_lock);
1319
1320 txq = priv->txq + index;
1321
1322 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1323 txq->tx_skb[txq->tx_tail] = skb;
1324
1325 tx = txq->tx_desc_area + txq->tx_tail;
1326 tx->data_rate = txdatarate;
1327 tx->tx_priority = index;
1328 tx->qos_control = cpu_to_le16(qos);
1329 tx->pkt_phys_addr = cpu_to_le32(dma);
1330 tx->pkt_len = cpu_to_le16(skb->len);
1331 tx->rate_info = 0;
1332 tx->peer_id = mwl8k_vif->peer_id;
1333 wmb();
1334 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1335
1336 txq->tx_stats.count++;
1337 txq->tx_stats.len++;
1338 priv->pending_tx_pkts++;
1339
1340 txq->tx_tail++;
1341 if (txq->tx_tail == MWL8K_TX_DESCS)
1342 txq->tx_tail = 0;
1343
1344 if (txq->tx_head == txq->tx_tail)
1345 ieee80211_stop_queue(hw, index);
1346
1347 mwl8k_tx_start(priv);
1348
1349 spin_unlock_bh(&priv->tx_lock);
1350
1351 return NETDEV_TX_OK;
1352 }
1353
1354
1355 /*
1356 * Firmware access.
1357 *
1358 * We have the following requirements for issuing firmware commands:
1359 * - Some commands require that the packet transmit path is idle when
1360 * the command is issued. (For simplicity, we'll just quiesce the
1361 * transmit path for every command.)
1362 * - There are certain sequences of commands that need to be issued to
1363 * the hardware sequentially, with no other intervening commands.
1364 *
1365 * This leads to an implementation of a "firmware lock" as a mutex that
1366 * can be taken recursively, and which is taken by both the low-level
1367 * command submission function (mwl8k_post_cmd) as well as any users of
1368 * that function that require issuing of an atomic sequence of commands,
1369 * and quiesces the transmit path whenever it's taken.
1370 */
1371 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1372 {
1373 struct mwl8k_priv *priv = hw->priv;
1374
1375 if (priv->fw_mutex_owner != current) {
1376 int rc;
1377
1378 mutex_lock(&priv->fw_mutex);
1379 ieee80211_stop_queues(hw);
1380
1381 rc = mwl8k_tx_wait_empty(hw);
1382 if (rc) {
1383 ieee80211_wake_queues(hw);
1384 mutex_unlock(&priv->fw_mutex);
1385
1386 return rc;
1387 }
1388
1389 priv->fw_mutex_owner = current;
1390 }
1391
1392 priv->fw_mutex_depth++;
1393
1394 return 0;
1395 }
1396
1397 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1398 {
1399 struct mwl8k_priv *priv = hw->priv;
1400
1401 if (!--priv->fw_mutex_depth) {
1402 ieee80211_wake_queues(hw);
1403 priv->fw_mutex_owner = NULL;
1404 mutex_unlock(&priv->fw_mutex);
1405 }
1406 }
1407
1408
1409 /*
1410 * Command processing.
1411 */
1412
1413 /* Timeout firmware commands after 2000ms */
1414 #define MWL8K_CMD_TIMEOUT_MS 2000
1415
1416 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1417 {
1418 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1419 struct mwl8k_priv *priv = hw->priv;
1420 void __iomem *regs = priv->regs;
1421 dma_addr_t dma_addr;
1422 unsigned int dma_size;
1423 int rc;
1424 unsigned long timeout = 0;
1425 u8 buf[32];
1426
1427 cmd->result = 0xffff;
1428 dma_size = le16_to_cpu(cmd->length);
1429 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1430 PCI_DMA_BIDIRECTIONAL);
1431 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1432 return -ENOMEM;
1433
1434 rc = mwl8k_fw_lock(hw);
1435 if (rc) {
1436 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1437 PCI_DMA_BIDIRECTIONAL);
1438 return rc;
1439 }
1440
1441 priv->hostcmd_wait = &cmd_wait;
1442 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1443 iowrite32(MWL8K_H2A_INT_DOORBELL,
1444 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1445 iowrite32(MWL8K_H2A_INT_DUMMY,
1446 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1447
1448 timeout = wait_for_completion_timeout(&cmd_wait,
1449 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1450
1451 priv->hostcmd_wait = NULL;
1452
1453 mwl8k_fw_unlock(hw);
1454
1455 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1456 PCI_DMA_BIDIRECTIONAL);
1457
1458 if (!timeout) {
1459 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1460 wiphy_name(hw->wiphy),
1461 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1462 MWL8K_CMD_TIMEOUT_MS);
1463 rc = -ETIMEDOUT;
1464 } else {
1465 rc = cmd->result ? -EINVAL : 0;
1466 if (rc)
1467 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1468 wiphy_name(hw->wiphy),
1469 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1470 le16_to_cpu(cmd->result));
1471 }
1472
1473 return rc;
1474 }
1475
1476 /*
1477 * GET_HW_SPEC.
1478 */
1479 struct mwl8k_cmd_get_hw_spec {
1480 struct mwl8k_cmd_pkt header;
1481 __u8 hw_rev;
1482 __u8 host_interface;
1483 __le16 num_mcaddrs;
1484 __u8 perm_addr[ETH_ALEN];
1485 __le16 region_code;
1486 __le32 fw_rev;
1487 __le32 ps_cookie;
1488 __le32 caps;
1489 __u8 mcs_bitmap[16];
1490 __le32 rx_queue_ptr;
1491 __le32 num_tx_queues;
1492 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1493 __le32 caps2;
1494 __le32 num_tx_desc_per_queue;
1495 __le32 total_rx_desc;
1496 } __attribute__((packed));
1497
1498 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1499 {
1500 struct mwl8k_priv *priv = hw->priv;
1501 struct mwl8k_cmd_get_hw_spec *cmd;
1502 int rc;
1503 int i;
1504
1505 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1506 if (cmd == NULL)
1507 return -ENOMEM;
1508
1509 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1510 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1511
1512 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1513 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1514 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1515 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1516 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1517 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1518 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1519 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1520
1521 rc = mwl8k_post_cmd(hw, &cmd->header);
1522
1523 if (!rc) {
1524 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1525 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1526 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1527 priv->hw_rev = cmd->hw_rev;
1528 }
1529
1530 kfree(cmd);
1531 return rc;
1532 }
1533
1534 /*
1535 * CMD_MAC_MULTICAST_ADR.
1536 */
1537 struct mwl8k_cmd_mac_multicast_adr {
1538 struct mwl8k_cmd_pkt header;
1539 __le16 action;
1540 __le16 numaddr;
1541 __u8 addr[0][ETH_ALEN];
1542 };
1543
1544 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1545 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1546 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1547 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1548
1549 static struct mwl8k_cmd_pkt *
1550 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1551 int mc_count, struct dev_addr_list *mclist)
1552 {
1553 struct mwl8k_priv *priv = hw->priv;
1554 struct mwl8k_cmd_mac_multicast_adr *cmd;
1555 int size;
1556
1557 if (allmulti || mc_count > priv->num_mcaddrs) {
1558 allmulti = 1;
1559 mc_count = 0;
1560 }
1561
1562 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1563
1564 cmd = kzalloc(size, GFP_ATOMIC);
1565 if (cmd == NULL)
1566 return NULL;
1567
1568 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1569 cmd->header.length = cpu_to_le16(size);
1570 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1571 MWL8K_ENABLE_RX_BROADCAST);
1572
1573 if (allmulti) {
1574 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1575 } else if (mc_count) {
1576 int i;
1577
1578 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1579 cmd->numaddr = cpu_to_le16(mc_count);
1580 for (i = 0; i < mc_count && mclist; i++) {
1581 if (mclist->da_addrlen != ETH_ALEN) {
1582 kfree(cmd);
1583 return NULL;
1584 }
1585 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1586 mclist = mclist->next;
1587 }
1588 }
1589
1590 return &cmd->header;
1591 }
1592
1593 /*
1594 * CMD_802_11_GET_STAT.
1595 */
1596 struct mwl8k_cmd_802_11_get_stat {
1597 struct mwl8k_cmd_pkt header;
1598 __le32 stats[64];
1599 } __attribute__((packed));
1600
1601 #define MWL8K_STAT_ACK_FAILURE 9
1602 #define MWL8K_STAT_RTS_FAILURE 12
1603 #define MWL8K_STAT_FCS_ERROR 24
1604 #define MWL8K_STAT_RTS_SUCCESS 11
1605
1606 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1607 struct ieee80211_low_level_stats *stats)
1608 {
1609 struct mwl8k_cmd_802_11_get_stat *cmd;
1610 int rc;
1611
1612 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1613 if (cmd == NULL)
1614 return -ENOMEM;
1615
1616 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1617 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1618
1619 rc = mwl8k_post_cmd(hw, &cmd->header);
1620 if (!rc) {
1621 stats->dot11ACKFailureCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1623 stats->dot11RTSFailureCount =
1624 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1625 stats->dot11FCSErrorCount =
1626 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1627 stats->dot11RTSSuccessCount =
1628 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1629 }
1630 kfree(cmd);
1631
1632 return rc;
1633 }
1634
1635 /*
1636 * CMD_802_11_RADIO_CONTROL.
1637 */
1638 struct mwl8k_cmd_802_11_radio_control {
1639 struct mwl8k_cmd_pkt header;
1640 __le16 action;
1641 __le16 control;
1642 __le16 radio_on;
1643 } __attribute__((packed));
1644
1645 static int
1646 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1647 {
1648 struct mwl8k_priv *priv = hw->priv;
1649 struct mwl8k_cmd_802_11_radio_control *cmd;
1650 int rc;
1651
1652 if (enable == priv->radio_on && !force)
1653 return 0;
1654
1655 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1656 if (cmd == NULL)
1657 return -ENOMEM;
1658
1659 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1660 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1661 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1662 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1663 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1664
1665 rc = mwl8k_post_cmd(hw, &cmd->header);
1666 kfree(cmd);
1667
1668 if (!rc)
1669 priv->radio_on = enable;
1670
1671 return rc;
1672 }
1673
1674 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1675 {
1676 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1677 }
1678
1679 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1680 {
1681 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1682 }
1683
1684 static int
1685 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1686 {
1687 struct mwl8k_priv *priv;
1688
1689 if (hw == NULL || hw->priv == NULL)
1690 return -EINVAL;
1691 priv = hw->priv;
1692
1693 priv->radio_short_preamble = short_preamble;
1694
1695 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1696 }
1697
1698 /*
1699 * CMD_802_11_RF_TX_POWER.
1700 */
1701 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1702
1703 struct mwl8k_cmd_802_11_rf_tx_power {
1704 struct mwl8k_cmd_pkt header;
1705 __le16 action;
1706 __le16 support_level;
1707 __le16 current_level;
1708 __le16 reserved;
1709 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1710 } __attribute__((packed));
1711
1712 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1713 {
1714 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1715 int rc;
1716
1717 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1718 if (cmd == NULL)
1719 return -ENOMEM;
1720
1721 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1722 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1723 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1724 cmd->support_level = cpu_to_le16(dBm);
1725
1726 rc = mwl8k_post_cmd(hw, &cmd->header);
1727 kfree(cmd);
1728
1729 return rc;
1730 }
1731
1732 /*
1733 * CMD_SET_PRE_SCAN.
1734 */
1735 struct mwl8k_cmd_set_pre_scan {
1736 struct mwl8k_cmd_pkt header;
1737 } __attribute__((packed));
1738
1739 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1740 {
1741 struct mwl8k_cmd_set_pre_scan *cmd;
1742 int rc;
1743
1744 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1745 if (cmd == NULL)
1746 return -ENOMEM;
1747
1748 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1749 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1750
1751 rc = mwl8k_post_cmd(hw, &cmd->header);
1752 kfree(cmd);
1753
1754 return rc;
1755 }
1756
1757 /*
1758 * CMD_SET_POST_SCAN.
1759 */
1760 struct mwl8k_cmd_set_post_scan {
1761 struct mwl8k_cmd_pkt header;
1762 __le32 isibss;
1763 __u8 bssid[ETH_ALEN];
1764 } __attribute__((packed));
1765
1766 static int
1767 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1768 {
1769 struct mwl8k_cmd_set_post_scan *cmd;
1770 int rc;
1771
1772 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1773 if (cmd == NULL)
1774 return -ENOMEM;
1775
1776 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1777 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1778 cmd->isibss = 0;
1779 memcpy(cmd->bssid, mac, ETH_ALEN);
1780
1781 rc = mwl8k_post_cmd(hw, &cmd->header);
1782 kfree(cmd);
1783
1784 return rc;
1785 }
1786
1787 /*
1788 * CMD_SET_RF_CHANNEL.
1789 */
1790 struct mwl8k_cmd_set_rf_channel {
1791 struct mwl8k_cmd_pkt header;
1792 __le16 action;
1793 __u8 current_channel;
1794 __le32 channel_flags;
1795 } __attribute__((packed));
1796
1797 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1798 struct ieee80211_channel *channel)
1799 {
1800 struct mwl8k_cmd_set_rf_channel *cmd;
1801 int rc;
1802
1803 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1804 if (cmd == NULL)
1805 return -ENOMEM;
1806
1807 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1808 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1809 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1810 cmd->current_channel = channel->hw_value;
1811 if (channel->band == IEEE80211_BAND_2GHZ)
1812 cmd->channel_flags = cpu_to_le32(0x00000081);
1813 else
1814 cmd->channel_flags = cpu_to_le32(0x00000000);
1815
1816 rc = mwl8k_post_cmd(hw, &cmd->header);
1817 kfree(cmd);
1818
1819 return rc;
1820 }
1821
1822 /*
1823 * CMD_SET_SLOT.
1824 */
1825 struct mwl8k_cmd_set_slot {
1826 struct mwl8k_cmd_pkt header;
1827 __le16 action;
1828 __u8 short_slot;
1829 } __attribute__((packed));
1830
1831 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1832 {
1833 struct mwl8k_cmd_set_slot *cmd;
1834 int rc;
1835
1836 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1837 if (cmd == NULL)
1838 return -ENOMEM;
1839
1840 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1841 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1842 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1843 cmd->short_slot = short_slot_time;
1844
1845 rc = mwl8k_post_cmd(hw, &cmd->header);
1846 kfree(cmd);
1847
1848 return rc;
1849 }
1850
1851 /*
1852 * CMD_MIMO_CONFIG.
1853 */
1854 struct mwl8k_cmd_mimo_config {
1855 struct mwl8k_cmd_pkt header;
1856 __le32 action;
1857 __u8 rx_antenna_map;
1858 __u8 tx_antenna_map;
1859 } __attribute__((packed));
1860
1861 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1862 {
1863 struct mwl8k_cmd_mimo_config *cmd;
1864 int rc;
1865
1866 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1867 if (cmd == NULL)
1868 return -ENOMEM;
1869
1870 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1871 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1872 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1873 cmd->rx_antenna_map = rx;
1874 cmd->tx_antenna_map = tx;
1875
1876 rc = mwl8k_post_cmd(hw, &cmd->header);
1877 kfree(cmd);
1878
1879 return rc;
1880 }
1881
1882 /*
1883 * CMD_ENABLE_SNIFFER.
1884 */
1885 struct mwl8k_cmd_enable_sniffer {
1886 struct mwl8k_cmd_pkt header;
1887 __le32 action;
1888 } __attribute__((packed));
1889
1890 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1891 {
1892 struct mwl8k_cmd_enable_sniffer *cmd;
1893 int rc;
1894
1895 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1896 if (cmd == NULL)
1897 return -ENOMEM;
1898
1899 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1900 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1901 cmd->action = cpu_to_le32(!!enable);
1902
1903 rc = mwl8k_post_cmd(hw, &cmd->header);
1904 kfree(cmd);
1905
1906 return rc;
1907 }
1908
1909 /*
1910 * CMD_SET_MAC_ADDR.
1911 */
1912 struct mwl8k_cmd_set_mac_addr {
1913 struct mwl8k_cmd_pkt header;
1914 __u8 mac_addr[ETH_ALEN];
1915 } __attribute__((packed));
1916
1917 static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1918 {
1919 struct mwl8k_cmd_set_mac_addr *cmd;
1920 int rc;
1921
1922 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1923 if (cmd == NULL)
1924 return -ENOMEM;
1925
1926 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1927 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1928 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1929
1930 rc = mwl8k_post_cmd(hw, &cmd->header);
1931 kfree(cmd);
1932
1933 return rc;
1934 }
1935
1936
1937 /*
1938 * CMD_SET_RATEADAPT_MODE.
1939 */
1940 struct mwl8k_cmd_set_rate_adapt_mode {
1941 struct mwl8k_cmd_pkt header;
1942 __le16 action;
1943 __le16 mode;
1944 } __attribute__((packed));
1945
1946 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1947 {
1948 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1949 int rc;
1950
1951 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1952 if (cmd == NULL)
1953 return -ENOMEM;
1954
1955 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1956 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1957 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1958 cmd->mode = cpu_to_le16(mode);
1959
1960 rc = mwl8k_post_cmd(hw, &cmd->header);
1961 kfree(cmd);
1962
1963 return rc;
1964 }
1965
1966 /*
1967 * CMD_SET_WMM_MODE.
1968 */
1969 struct mwl8k_cmd_set_wmm {
1970 struct mwl8k_cmd_pkt header;
1971 __le16 action;
1972 } __attribute__((packed));
1973
1974 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1975 {
1976 struct mwl8k_priv *priv = hw->priv;
1977 struct mwl8k_cmd_set_wmm *cmd;
1978 int rc;
1979
1980 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1981 if (cmd == NULL)
1982 return -ENOMEM;
1983
1984 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1985 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1986 cmd->action = cpu_to_le16(!!enable);
1987
1988 rc = mwl8k_post_cmd(hw, &cmd->header);
1989 kfree(cmd);
1990
1991 if (!rc)
1992 priv->wmm_enabled = enable;
1993
1994 return rc;
1995 }
1996
1997 /*
1998 * CMD_SET_RTS_THRESHOLD.
1999 */
2000 struct mwl8k_cmd_rts_threshold {
2001 struct mwl8k_cmd_pkt header;
2002 __le16 action;
2003 __le16 threshold;
2004 } __attribute__((packed));
2005
2006 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2007 u16 action, u16 threshold)
2008 {
2009 struct mwl8k_cmd_rts_threshold *cmd;
2010 int rc;
2011
2012 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2013 if (cmd == NULL)
2014 return -ENOMEM;
2015
2016 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2017 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2018 cmd->action = cpu_to_le16(action);
2019 cmd->threshold = cpu_to_le16(threshold);
2020
2021 rc = mwl8k_post_cmd(hw, &cmd->header);
2022 kfree(cmd);
2023
2024 return rc;
2025 }
2026
2027 /*
2028 * CMD_SET_EDCA_PARAMS.
2029 */
2030 struct mwl8k_cmd_set_edca_params {
2031 struct mwl8k_cmd_pkt header;
2032
2033 /* See MWL8K_SET_EDCA_XXX below */
2034 __le16 action;
2035
2036 /* TX opportunity in units of 32 us */
2037 __le16 txop;
2038
2039 /* Log exponent of max contention period: 0...15*/
2040 __u8 log_cw_max;
2041
2042 /* Log exponent of min contention period: 0...15 */
2043 __u8 log_cw_min;
2044
2045 /* Adaptive interframe spacing in units of 32us */
2046 __u8 aifs;
2047
2048 /* TX queue to configure */
2049 __u8 txq;
2050 } __attribute__((packed));
2051
2052 #define MWL8K_SET_EDCA_CW 0x01
2053 #define MWL8K_SET_EDCA_TXOP 0x02
2054 #define MWL8K_SET_EDCA_AIFS 0x04
2055
2056 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2057 MWL8K_SET_EDCA_TXOP | \
2058 MWL8K_SET_EDCA_AIFS)
2059
2060 static int
2061 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2062 __u16 cw_min, __u16 cw_max,
2063 __u8 aifs, __u16 txop)
2064 {
2065 struct mwl8k_cmd_set_edca_params *cmd;
2066 int rc;
2067
2068 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2069 if (cmd == NULL)
2070 return -ENOMEM;
2071
2072 /*
2073 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2074 * this call.
2075 */
2076 qnum ^= !(qnum >> 1);
2077
2078 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2079 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2080 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2081 cmd->txop = cpu_to_le16(txop);
2082 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2083 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2084 cmd->aifs = aifs;
2085 cmd->txq = qnum;
2086
2087 rc = mwl8k_post_cmd(hw, &cmd->header);
2088 kfree(cmd);
2089
2090 return rc;
2091 }
2092
2093 /*
2094 * CMD_FINALIZE_JOIN.
2095 */
2096
2097 /* FJ beacon buffer size is compiled into the firmware. */
2098 #define MWL8K_FJ_BEACON_MAXLEN 128
2099
2100 struct mwl8k_cmd_finalize_join {
2101 struct mwl8k_cmd_pkt header;
2102 __le32 sleep_interval; /* Number of beacon periods to sleep */
2103 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2104 } __attribute__((packed));
2105
2106 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2107 __u16 framelen, __u16 dtim)
2108 {
2109 struct mwl8k_cmd_finalize_join *cmd;
2110 struct ieee80211_mgmt *payload = frame;
2111 u16 hdrlen;
2112 u32 payload_len;
2113 int rc;
2114
2115 if (frame == NULL)
2116 return -EINVAL;
2117
2118 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2119 if (cmd == NULL)
2120 return -ENOMEM;
2121
2122 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2123 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2124 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2125
2126 hdrlen = ieee80211_hdrlen(payload->frame_control);
2127
2128 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2129
2130 /* XXX TBD Might just have to abort and return an error */
2131 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2132 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2133 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2134 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2135
2136 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2137 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2138
2139 if (payload && payload_len)
2140 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2141
2142 rc = mwl8k_post_cmd(hw, &cmd->header);
2143 kfree(cmd);
2144 return rc;
2145 }
2146
2147 /*
2148 * CMD_UPDATE_STADB.
2149 */
2150 struct mwl8k_cmd_update_sta_db {
2151 struct mwl8k_cmd_pkt header;
2152
2153 /* See STADB_ACTION_TYPE */
2154 __le32 action;
2155
2156 /* Peer MAC address */
2157 __u8 peer_addr[ETH_ALEN];
2158
2159 __le32 reserved;
2160
2161 /* Peer info - valid during add/update. */
2162 struct peer_capability_info peer_info;
2163 } __attribute__((packed));
2164
2165 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2166 struct ieee80211_vif *vif, __u32 action)
2167 {
2168 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2169 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2170 struct mwl8k_cmd_update_sta_db *cmd;
2171 struct peer_capability_info *peer_info;
2172 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2173 int rc;
2174 __u8 count, *rates;
2175
2176 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2177 if (cmd == NULL)
2178 return -ENOMEM;
2179
2180 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2181 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2182
2183 cmd->action = cpu_to_le32(action);
2184 peer_info = &cmd->peer_info;
2185 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2186
2187 switch (action) {
2188 case MWL8K_STA_DB_ADD_ENTRY:
2189 case MWL8K_STA_DB_MODIFY_ENTRY:
2190 /* Build peer_info block */
2191 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2192 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2193 peer_info->interop = 1;
2194 peer_info->amsdu_enabled = 0;
2195
2196 rates = peer_info->legacy_rates;
2197 for (count = 0; count < mv_vif->legacy_nrates; count++)
2198 rates[count] = bitrates[count].hw_value;
2199
2200 rc = mwl8k_post_cmd(hw, &cmd->header);
2201 if (rc == 0)
2202 mv_vif->peer_id = peer_info->station_id;
2203
2204 break;
2205
2206 case MWL8K_STA_DB_DEL_ENTRY:
2207 case MWL8K_STA_DB_FLUSH:
2208 default:
2209 rc = mwl8k_post_cmd(hw, &cmd->header);
2210 if (rc == 0)
2211 mv_vif->peer_id = 0;
2212 break;
2213 }
2214 kfree(cmd);
2215
2216 return rc;
2217 }
2218
2219 /*
2220 * CMD_SET_AID.
2221 */
2222 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2223
2224 #define MWL8K_FRAME_PROT_DISABLED 0x00
2225 #define MWL8K_FRAME_PROT_11G 0x07
2226 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2227 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2228
2229 struct mwl8k_cmd_update_set_aid {
2230 struct mwl8k_cmd_pkt header;
2231 __le16 aid;
2232
2233 /* AP's MAC address (BSSID) */
2234 __u8 bssid[ETH_ALEN];
2235 __le16 protection_mode;
2236 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2237 } __attribute__((packed));
2238
2239 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2240 struct ieee80211_vif *vif)
2241 {
2242 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2243 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2244 struct mwl8k_cmd_update_set_aid *cmd;
2245 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2246 int count;
2247 u16 prot_mode;
2248 int rc;
2249
2250 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2251 if (cmd == NULL)
2252 return -ENOMEM;
2253
2254 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2255 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2256 cmd->aid = cpu_to_le16(info->aid);
2257
2258 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2259
2260 if (info->use_cts_prot) {
2261 prot_mode = MWL8K_FRAME_PROT_11G;
2262 } else {
2263 switch (info->ht_operation_mode &
2264 IEEE80211_HT_OP_MODE_PROTECTION) {
2265 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2266 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2267 break;
2268 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2269 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2270 break;
2271 default:
2272 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2273 break;
2274 }
2275 }
2276 cmd->protection_mode = cpu_to_le16(prot_mode);
2277
2278 for (count = 0; count < mv_vif->legacy_nrates; count++)
2279 cmd->supp_rates[count] = bitrates[count].hw_value;
2280
2281 rc = mwl8k_post_cmd(hw, &cmd->header);
2282 kfree(cmd);
2283
2284 return rc;
2285 }
2286
2287 /*
2288 * CMD_SET_RATE.
2289 */
2290 struct mwl8k_cmd_update_rateset {
2291 struct mwl8k_cmd_pkt header;
2292 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2293
2294 /* Bitmap for supported MCS codes. */
2295 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2296 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2297 } __attribute__((packed));
2298
2299 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2300 struct ieee80211_vif *vif)
2301 {
2302 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2303 struct mwl8k_cmd_update_rateset *cmd;
2304 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2305 int count;
2306 int rc;
2307
2308 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2309 if (cmd == NULL)
2310 return -ENOMEM;
2311
2312 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2313 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2314
2315 for (count = 0; count < mv_vif->legacy_nrates; count++)
2316 cmd->legacy_rates[count] = bitrates[count].hw_value;
2317
2318 rc = mwl8k_post_cmd(hw, &cmd->header);
2319 kfree(cmd);
2320
2321 return rc;
2322 }
2323
2324 /*
2325 * CMD_USE_FIXED_RATE.
2326 */
2327 #define MWL8K_RATE_TABLE_SIZE 8
2328 #define MWL8K_UCAST_RATE 0
2329 #define MWL8K_USE_AUTO_RATE 0x0002
2330
2331 struct mwl8k_rate_entry {
2332 /* Set to 1 if HT rate, 0 if legacy. */
2333 __le32 is_ht_rate;
2334
2335 /* Set to 1 to use retry_count field. */
2336 __le32 enable_retry;
2337
2338 /* Specified legacy rate or MCS. */
2339 __le32 rate;
2340
2341 /* Number of allowed retries. */
2342 __le32 retry_count;
2343 } __attribute__((packed));
2344
2345 struct mwl8k_rate_table {
2346 /* 1 to allow specified rate and below */
2347 __le32 allow_rate_drop;
2348 __le32 num_rates;
2349 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2350 } __attribute__((packed));
2351
2352 struct mwl8k_cmd_use_fixed_rate {
2353 struct mwl8k_cmd_pkt header;
2354 __le32 action;
2355 struct mwl8k_rate_table rate_table;
2356
2357 /* Unicast, Broadcast or Multicast */
2358 __le32 rate_type;
2359 __le32 reserved1;
2360 __le32 reserved2;
2361 } __attribute__((packed));
2362
2363 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2364 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2365 {
2366 struct mwl8k_cmd_use_fixed_rate *cmd;
2367 int count;
2368 int rc;
2369
2370 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2371 if (cmd == NULL)
2372 return -ENOMEM;
2373
2374 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2375 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2376
2377 cmd->action = cpu_to_le32(action);
2378 cmd->rate_type = cpu_to_le32(rate_type);
2379
2380 if (rate_table != NULL) {
2381 /*
2382 * Copy over each field manually so that endian
2383 * conversion can be done.
2384 */
2385 cmd->rate_table.allow_rate_drop =
2386 cpu_to_le32(rate_table->allow_rate_drop);
2387 cmd->rate_table.num_rates =
2388 cpu_to_le32(rate_table->num_rates);
2389
2390 for (count = 0; count < rate_table->num_rates; count++) {
2391 struct mwl8k_rate_entry *dst =
2392 &cmd->rate_table.rate_entry[count];
2393 struct mwl8k_rate_entry *src =
2394 &rate_table->rate_entry[count];
2395
2396 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2397 dst->enable_retry = cpu_to_le32(src->enable_retry);
2398 dst->rate = cpu_to_le32(src->rate);
2399 dst->retry_count = cpu_to_le32(src->retry_count);
2400 }
2401 }
2402
2403 rc = mwl8k_post_cmd(hw, &cmd->header);
2404 kfree(cmd);
2405
2406 return rc;
2407 }
2408
2409
2410 /*
2411 * Interrupt handling.
2412 */
2413 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2414 {
2415 struct ieee80211_hw *hw = dev_id;
2416 struct mwl8k_priv *priv = hw->priv;
2417 u32 status;
2418
2419 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2420 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2421
2422 if (!status)
2423 return IRQ_NONE;
2424
2425 if (status & MWL8K_A2H_INT_TX_DONE)
2426 tasklet_schedule(&priv->tx_reclaim_task);
2427
2428 if (status & MWL8K_A2H_INT_RX_READY) {
2429 while (rxq_process(hw, 0, 1))
2430 rxq_refill(hw, 0, 1);
2431 }
2432
2433 if (status & MWL8K_A2H_INT_OPC_DONE) {
2434 if (priv->hostcmd_wait != NULL)
2435 complete(priv->hostcmd_wait);
2436 }
2437
2438 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2439 if (!mutex_is_locked(&priv->fw_mutex) &&
2440 priv->radio_on && priv->pending_tx_pkts)
2441 mwl8k_tx_start(priv);
2442 }
2443
2444 return IRQ_HANDLED;
2445 }
2446
2447
2448 /*
2449 * Core driver operations.
2450 */
2451 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2452 {
2453 struct mwl8k_priv *priv = hw->priv;
2454 int index = skb_get_queue_mapping(skb);
2455 int rc;
2456
2457 if (priv->current_channel == NULL) {
2458 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2459 "disabled\n", wiphy_name(hw->wiphy));
2460 dev_kfree_skb(skb);
2461 return NETDEV_TX_OK;
2462 }
2463
2464 rc = mwl8k_txq_xmit(hw, index, skb);
2465
2466 return rc;
2467 }
2468
2469 static int mwl8k_start(struct ieee80211_hw *hw)
2470 {
2471 struct mwl8k_priv *priv = hw->priv;
2472 int rc;
2473
2474 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2475 IRQF_SHARED, MWL8K_NAME, hw);
2476 if (rc) {
2477 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2478 wiphy_name(hw->wiphy));
2479 return -EIO;
2480 }
2481
2482 /* Enable tx reclaim tasklet */
2483 tasklet_enable(&priv->tx_reclaim_task);
2484
2485 /* Enable interrupts */
2486 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2487
2488 rc = mwl8k_fw_lock(hw);
2489 if (!rc) {
2490 rc = mwl8k_cmd_802_11_radio_enable(hw);
2491
2492 if (!rc)
2493 rc = mwl8k_cmd_set_pre_scan(hw);
2494
2495 if (!rc)
2496 rc = mwl8k_cmd_set_post_scan(hw,
2497 "\x00\x00\x00\x00\x00\x00");
2498
2499 if (!rc)
2500 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2501
2502 if (!rc)
2503 rc = mwl8k_set_wmm(hw, 0);
2504
2505 if (!rc)
2506 rc = mwl8k_enable_sniffer(hw, 0);
2507
2508 mwl8k_fw_unlock(hw);
2509 }
2510
2511 if (rc) {
2512 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2513 free_irq(priv->pdev->irq, hw);
2514 tasklet_disable(&priv->tx_reclaim_task);
2515 }
2516
2517 return rc;
2518 }
2519
2520 static void mwl8k_stop(struct ieee80211_hw *hw)
2521 {
2522 struct mwl8k_priv *priv = hw->priv;
2523 int i;
2524
2525 mwl8k_cmd_802_11_radio_disable(hw);
2526
2527 ieee80211_stop_queues(hw);
2528
2529 /* Disable interrupts */
2530 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2531 free_irq(priv->pdev->irq, hw);
2532
2533 /* Stop finalize join worker */
2534 cancel_work_sync(&priv->finalize_join_worker);
2535 if (priv->beacon_skb != NULL)
2536 dev_kfree_skb(priv->beacon_skb);
2537
2538 /* Stop tx reclaim tasklet */
2539 tasklet_disable(&priv->tx_reclaim_task);
2540
2541 /* Return all skbs to mac80211 */
2542 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2543 mwl8k_txq_reclaim(hw, i, 1);
2544 }
2545
2546 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2547 struct ieee80211_if_init_conf *conf)
2548 {
2549 struct mwl8k_priv *priv = hw->priv;
2550 struct mwl8k_vif *mwl8k_vif;
2551
2552 /*
2553 * We only support one active interface at a time.
2554 */
2555 if (priv->vif != NULL)
2556 return -EBUSY;
2557
2558 /*
2559 * We only support managed interfaces for now.
2560 */
2561 if (conf->type != NL80211_IFTYPE_STATION)
2562 return -EINVAL;
2563
2564 /*
2565 * Reject interface creation if sniffer mode is active, as
2566 * STA operation is mutually exclusive with hardware sniffer
2567 * mode.
2568 */
2569 if (priv->sniffer_enabled) {
2570 printk(KERN_INFO "%s: unable to create STA "
2571 "interface due to sniffer mode being enabled\n",
2572 wiphy_name(hw->wiphy));
2573 return -EINVAL;
2574 }
2575
2576 /* Clean out driver private area */
2577 mwl8k_vif = MWL8K_VIF(conf->vif);
2578 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2579
2580 /* Set and save the mac address */
2581 mwl8k_set_mac_addr(hw, conf->mac_addr);
2582 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2583
2584 /* Back pointer to parent config block */
2585 mwl8k_vif->priv = priv;
2586
2587 /* Setup initial PHY parameters */
2588 memcpy(mwl8k_vif->legacy_rates,
2589 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2590 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2591
2592 /* Set Initial sequence number to zero */
2593 mwl8k_vif->seqno = 0;
2594
2595 priv->vif = conf->vif;
2596 priv->current_channel = NULL;
2597
2598 return 0;
2599 }
2600
2601 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2602 struct ieee80211_if_init_conf *conf)
2603 {
2604 struct mwl8k_priv *priv = hw->priv;
2605
2606 if (priv->vif == NULL)
2607 return;
2608
2609 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2610
2611 priv->vif = NULL;
2612 }
2613
2614 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2615 {
2616 struct ieee80211_conf *conf = &hw->conf;
2617 struct mwl8k_priv *priv = hw->priv;
2618 int rc;
2619
2620 if (conf->flags & IEEE80211_CONF_IDLE) {
2621 mwl8k_cmd_802_11_radio_disable(hw);
2622 priv->current_channel = NULL;
2623 return 0;
2624 }
2625
2626 rc = mwl8k_fw_lock(hw);
2627 if (rc)
2628 return rc;
2629
2630 rc = mwl8k_cmd_802_11_radio_enable(hw);
2631 if (rc)
2632 goto out;
2633
2634 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2635 if (rc)
2636 goto out;
2637
2638 priv->current_channel = conf->channel;
2639
2640 if (conf->power_level > 18)
2641 conf->power_level = 18;
2642 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2643 if (rc)
2644 goto out;
2645
2646 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2647 rc = -EINVAL;
2648
2649 out:
2650 mwl8k_fw_unlock(hw);
2651
2652 return rc;
2653 }
2654
2655 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2656 struct ieee80211_vif *vif,
2657 struct ieee80211_bss_conf *info,
2658 u32 changed)
2659 {
2660 struct mwl8k_priv *priv = hw->priv;
2661 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2662 int rc;
2663
2664 if (changed & BSS_CHANGED_BSSID)
2665 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2666
2667 if ((changed & BSS_CHANGED_ASSOC) == 0)
2668 return;
2669
2670 priv->capture_beacon = false;
2671
2672 rc = mwl8k_fw_lock(hw);
2673 if (rc)
2674 return;
2675
2676 if (info->assoc) {
2677 memcpy(&mwl8k_vif->bss_info, info,
2678 sizeof(struct ieee80211_bss_conf));
2679
2680 /* Install rates */
2681 rc = mwl8k_update_rateset(hw, vif);
2682 if (rc)
2683 goto out;
2684
2685 /* Turn on rate adaptation */
2686 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2687 MWL8K_UCAST_RATE, NULL);
2688 if (rc)
2689 goto out;
2690
2691 /* Set radio preamble */
2692 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2693 if (rc)
2694 goto out;
2695
2696 /* Set slot time */
2697 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2698 if (rc)
2699 goto out;
2700
2701 /* Update peer rate info */
2702 rc = mwl8k_cmd_update_sta_db(hw, vif,
2703 MWL8K_STA_DB_MODIFY_ENTRY);
2704 if (rc)
2705 goto out;
2706
2707 /* Set AID */
2708 rc = mwl8k_cmd_set_aid(hw, vif);
2709 if (rc)
2710 goto out;
2711
2712 /*
2713 * Finalize the join. Tell rx handler to process
2714 * next beacon from our BSSID.
2715 */
2716 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2717 priv->capture_beacon = true;
2718 } else {
2719 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2720 memset(&mwl8k_vif->bss_info, 0,
2721 sizeof(struct ieee80211_bss_conf));
2722 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2723 }
2724
2725 out:
2726 mwl8k_fw_unlock(hw);
2727 }
2728
2729 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2730 int mc_count, struct dev_addr_list *mclist)
2731 {
2732 struct mwl8k_cmd_pkt *cmd;
2733
2734 /*
2735 * Synthesize and return a command packet that programs the
2736 * hardware multicast address filter. At this point we don't
2737 * know whether FIF_ALLMULTI is being requested, but if it is,
2738 * we'll end up throwing this packet away and creating a new
2739 * one in mwl8k_configure_filter().
2740 */
2741 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
2742
2743 return (unsigned long)cmd;
2744 }
2745
2746 static int
2747 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2748 unsigned int changed_flags,
2749 unsigned int *total_flags)
2750 {
2751 struct mwl8k_priv *priv = hw->priv;
2752
2753 /*
2754 * Hardware sniffer mode is mutually exclusive with STA
2755 * operation, so refuse to enable sniffer mode if a STA
2756 * interface is active.
2757 */
2758 if (priv->vif != NULL) {
2759 if (net_ratelimit())
2760 printk(KERN_INFO "%s: not enabling sniffer "
2761 "mode because STA interface is active\n",
2762 wiphy_name(hw->wiphy));
2763 return 0;
2764 }
2765
2766 if (!priv->sniffer_enabled) {
2767 if (mwl8k_enable_sniffer(hw, 1))
2768 return 0;
2769 priv->sniffer_enabled = true;
2770 }
2771
2772 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2773 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2774 FIF_OTHER_BSS;
2775
2776 return 1;
2777 }
2778
2779 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2780 unsigned int changed_flags,
2781 unsigned int *total_flags,
2782 u64 multicast)
2783 {
2784 struct mwl8k_priv *priv = hw->priv;
2785 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2786
2787 /*
2788 * Enable hardware sniffer mode if FIF_CONTROL or
2789 * FIF_OTHER_BSS is requested.
2790 */
2791 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2792 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2793 kfree(cmd);
2794 return;
2795 }
2796
2797 /* Clear unsupported feature flags */
2798 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
2799
2800 if (mwl8k_fw_lock(hw))
2801 return;
2802
2803 if (priv->sniffer_enabled) {
2804 mwl8k_enable_sniffer(hw, 0);
2805 priv->sniffer_enabled = false;
2806 }
2807
2808 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2809 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2810 /*
2811 * Disable the BSS filter.
2812 */
2813 mwl8k_cmd_set_pre_scan(hw);
2814 } else {
2815 u8 *bssid;
2816
2817 /*
2818 * Enable the BSS filter.
2819 *
2820 * If there is an active STA interface, use that
2821 * interface's BSSID, otherwise use a dummy one
2822 * (where the OUI part needs to be nonzero for
2823 * the BSSID to be accepted by POST_SCAN).
2824 */
2825 bssid = "\x01\x00\x00\x00\x00\x00";
2826 if (priv->vif != NULL)
2827 bssid = MWL8K_VIF(priv->vif)->bssid;
2828
2829 mwl8k_cmd_set_post_scan(hw, bssid);
2830 }
2831 }
2832
2833 /*
2834 * If FIF_ALLMULTI is being requested, throw away the command
2835 * packet that ->prepare_multicast() built and replace it with
2836 * a command packet that enables reception of all multicast
2837 * packets.
2838 */
2839 if (*total_flags & FIF_ALLMULTI) {
2840 kfree(cmd);
2841 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2842 }
2843
2844 if (cmd != NULL) {
2845 mwl8k_post_cmd(hw, cmd);
2846 kfree(cmd);
2847 }
2848
2849 mwl8k_fw_unlock(hw);
2850 }
2851
2852 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2853 {
2854 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2855 }
2856
2857 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2858 const struct ieee80211_tx_queue_params *params)
2859 {
2860 struct mwl8k_priv *priv = hw->priv;
2861 int rc;
2862
2863 rc = mwl8k_fw_lock(hw);
2864 if (!rc) {
2865 if (!priv->wmm_enabled)
2866 rc = mwl8k_set_wmm(hw, 1);
2867
2868 if (!rc)
2869 rc = mwl8k_set_edca_params(hw, queue,
2870 params->cw_min,
2871 params->cw_max,
2872 params->aifs,
2873 params->txop);
2874
2875 mwl8k_fw_unlock(hw);
2876 }
2877
2878 return rc;
2879 }
2880
2881 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2882 struct ieee80211_tx_queue_stats *stats)
2883 {
2884 struct mwl8k_priv *priv = hw->priv;
2885 struct mwl8k_tx_queue *txq;
2886 int index;
2887
2888 spin_lock_bh(&priv->tx_lock);
2889 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2890 txq = priv->txq + index;
2891 memcpy(&stats[index], &txq->tx_stats,
2892 sizeof(struct ieee80211_tx_queue_stats));
2893 }
2894 spin_unlock_bh(&priv->tx_lock);
2895
2896 return 0;
2897 }
2898
2899 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2900 struct ieee80211_low_level_stats *stats)
2901 {
2902 return mwl8k_cmd_802_11_get_stat(hw, stats);
2903 }
2904
2905 static const struct ieee80211_ops mwl8k_ops = {
2906 .tx = mwl8k_tx,
2907 .start = mwl8k_start,
2908 .stop = mwl8k_stop,
2909 .add_interface = mwl8k_add_interface,
2910 .remove_interface = mwl8k_remove_interface,
2911 .config = mwl8k_config,
2912 .bss_info_changed = mwl8k_bss_info_changed,
2913 .prepare_multicast = mwl8k_prepare_multicast,
2914 .configure_filter = mwl8k_configure_filter,
2915 .set_rts_threshold = mwl8k_set_rts_threshold,
2916 .conf_tx = mwl8k_conf_tx,
2917 .get_tx_stats = mwl8k_get_tx_stats,
2918 .get_stats = mwl8k_get_stats,
2919 };
2920
2921 static void mwl8k_tx_reclaim_handler(unsigned long data)
2922 {
2923 int i;
2924 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2925 struct mwl8k_priv *priv = hw->priv;
2926
2927 spin_lock_bh(&priv->tx_lock);
2928 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2929 mwl8k_txq_reclaim(hw, i, 0);
2930
2931 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
2932 complete(priv->tx_wait);
2933 priv->tx_wait = NULL;
2934 }
2935 spin_unlock_bh(&priv->tx_lock);
2936 }
2937
2938 static void mwl8k_finalize_join_worker(struct work_struct *work)
2939 {
2940 struct mwl8k_priv *priv =
2941 container_of(work, struct mwl8k_priv, finalize_join_worker);
2942 struct sk_buff *skb = priv->beacon_skb;
2943 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2944
2945 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2946 dev_kfree_skb(skb);
2947
2948 priv->beacon_skb = NULL;
2949 }
2950
2951 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2952 const struct pci_device_id *id)
2953 {
2954 static int printed_version = 0;
2955 struct ieee80211_hw *hw;
2956 struct mwl8k_priv *priv;
2957 int rc;
2958 int i;
2959
2960 if (!printed_version) {
2961 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2962 printed_version = 1;
2963 }
2964
2965 rc = pci_enable_device(pdev);
2966 if (rc) {
2967 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2968 MWL8K_NAME);
2969 return rc;
2970 }
2971
2972 rc = pci_request_regions(pdev, MWL8K_NAME);
2973 if (rc) {
2974 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2975 MWL8K_NAME);
2976 return rc;
2977 }
2978
2979 pci_set_master(pdev);
2980
2981 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2982 if (hw == NULL) {
2983 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2984 rc = -ENOMEM;
2985 goto err_free_reg;
2986 }
2987
2988 priv = hw->priv;
2989 priv->hw = hw;
2990 priv->pdev = pdev;
2991 priv->sniffer_enabled = false;
2992 priv->wmm_enabled = false;
2993 priv->pending_tx_pkts = 0;
2994
2995 SET_IEEE80211_DEV(hw, &pdev->dev);
2996 pci_set_drvdata(pdev, hw);
2997
2998 priv->regs = pci_iomap(pdev, 1, 0x10000);
2999 if (priv->regs == NULL) {
3000 printk(KERN_ERR "%s: Cannot map device memory\n",
3001 wiphy_name(hw->wiphy));
3002 goto err_iounmap;
3003 }
3004
3005 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3006 priv->band.band = IEEE80211_BAND_2GHZ;
3007 priv->band.channels = priv->channels;
3008 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3009 priv->band.bitrates = priv->rates;
3010 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3011 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3012
3013 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3014 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3015
3016 /*
3017 * Extra headroom is the size of the required DMA header
3018 * minus the size of the smallest 802.11 frame (CTS frame).
3019 */
3020 hw->extra_tx_headroom =
3021 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3022
3023 hw->channel_change_time = 10;
3024
3025 hw->queues = MWL8K_TX_QUEUES;
3026
3027 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
3028
3029 /* Set rssi and noise values to dBm */
3030 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3031 hw->vif_data_size = sizeof(struct mwl8k_vif);
3032 priv->vif = NULL;
3033
3034 /* Set default radio state and preamble */
3035 priv->radio_on = 0;
3036 priv->radio_short_preamble = 0;
3037
3038 /* Finalize join worker */
3039 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3040
3041 /* TX reclaim tasklet */
3042 tasklet_init(&priv->tx_reclaim_task,
3043 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3044 tasklet_disable(&priv->tx_reclaim_task);
3045
3046 /* Power management cookie */
3047 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3048 if (priv->cookie == NULL)
3049 goto err_iounmap;
3050
3051 rc = mwl8k_rxq_init(hw, 0);
3052 if (rc)
3053 goto err_iounmap;
3054 rxq_refill(hw, 0, INT_MAX);
3055
3056 mutex_init(&priv->fw_mutex);
3057 priv->fw_mutex_owner = NULL;
3058 priv->fw_mutex_depth = 0;
3059 priv->hostcmd_wait = NULL;
3060
3061 spin_lock_init(&priv->tx_lock);
3062
3063 priv->tx_wait = NULL;
3064
3065 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3066 rc = mwl8k_txq_init(hw, i);
3067 if (rc)
3068 goto err_free_queues;
3069 }
3070
3071 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3072 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3073 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3074 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3075
3076 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3077 IRQF_SHARED, MWL8K_NAME, hw);
3078 if (rc) {
3079 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3080 wiphy_name(hw->wiphy));
3081 goto err_free_queues;
3082 }
3083
3084 /* Reset firmware and hardware */
3085 mwl8k_hw_reset(priv);
3086
3087 /* Ask userland hotplug daemon for the device firmware */
3088 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3089 if (rc) {
3090 printk(KERN_ERR "%s: Firmware files not found\n",
3091 wiphy_name(hw->wiphy));
3092 goto err_free_irq;
3093 }
3094
3095 /* Load firmware into hardware */
3096 rc = mwl8k_load_firmware(hw);
3097 if (rc) {
3098 printk(KERN_ERR "%s: Cannot start firmware\n",
3099 wiphy_name(hw->wiphy));
3100 goto err_stop_firmware;
3101 }
3102
3103 /* Reclaim memory once firmware is successfully loaded */
3104 mwl8k_release_firmware(priv);
3105
3106 /*
3107 * Temporarily enable interrupts. Initial firmware host
3108 * commands use interrupts and avoids polling. Disable
3109 * interrupts when done.
3110 */
3111 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3112
3113 /* Get config data, mac addrs etc */
3114 rc = mwl8k_cmd_get_hw_spec(hw);
3115 if (rc) {
3116 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3117 wiphy_name(hw->wiphy));
3118 goto err_stop_firmware;
3119 }
3120
3121 /* Turn radio off */
3122 rc = mwl8k_cmd_802_11_radio_disable(hw);
3123 if (rc) {
3124 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3125 goto err_stop_firmware;
3126 }
3127
3128 /* Clear MAC address */
3129 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3130 if (rc) {
3131 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3132 wiphy_name(hw->wiphy));
3133 goto err_stop_firmware;
3134 }
3135
3136 /* Disable interrupts */
3137 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3138 free_irq(priv->pdev->irq, hw);
3139
3140 rc = ieee80211_register_hw(hw);
3141 if (rc) {
3142 printk(KERN_ERR "%s: Cannot register device\n",
3143 wiphy_name(hw->wiphy));
3144 goto err_stop_firmware;
3145 }
3146
3147 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3148 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3149 hw->wiphy->perm_addr,
3150 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3151 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3152
3153 return 0;
3154
3155 err_stop_firmware:
3156 mwl8k_hw_reset(priv);
3157 mwl8k_release_firmware(priv);
3158
3159 err_free_irq:
3160 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3161 free_irq(priv->pdev->irq, hw);
3162
3163 err_free_queues:
3164 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3165 mwl8k_txq_deinit(hw, i);
3166 mwl8k_rxq_deinit(hw, 0);
3167
3168 err_iounmap:
3169 if (priv->cookie != NULL)
3170 pci_free_consistent(priv->pdev, 4,
3171 priv->cookie, priv->cookie_dma);
3172
3173 if (priv->regs != NULL)
3174 pci_iounmap(pdev, priv->regs);
3175
3176 pci_set_drvdata(pdev, NULL);
3177 ieee80211_free_hw(hw);
3178
3179 err_free_reg:
3180 pci_release_regions(pdev);
3181 pci_disable_device(pdev);
3182
3183 return rc;
3184 }
3185
3186 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3187 {
3188 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3189 }
3190
3191 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3192 {
3193 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3194 struct mwl8k_priv *priv;
3195 int i;
3196
3197 if (hw == NULL)
3198 return;
3199 priv = hw->priv;
3200
3201 ieee80211_stop_queues(hw);
3202
3203 ieee80211_unregister_hw(hw);
3204
3205 /* Remove tx reclaim tasklet */
3206 tasklet_kill(&priv->tx_reclaim_task);
3207
3208 /* Stop hardware */
3209 mwl8k_hw_reset(priv);
3210
3211 /* Return all skbs to mac80211 */
3212 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3213 mwl8k_txq_reclaim(hw, i, 1);
3214
3215 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3216 mwl8k_txq_deinit(hw, i);
3217
3218 mwl8k_rxq_deinit(hw, 0);
3219
3220 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3221
3222 pci_iounmap(pdev, priv->regs);
3223 pci_set_drvdata(pdev, NULL);
3224 ieee80211_free_hw(hw);
3225 pci_release_regions(pdev);
3226 pci_disable_device(pdev);
3227 }
3228
3229 static struct pci_driver mwl8k_driver = {
3230 .name = MWL8K_NAME,
3231 .id_table = mwl8k_table,
3232 .probe = mwl8k_probe,
3233 .remove = __devexit_p(mwl8k_remove),
3234 .shutdown = __devexit_p(mwl8k_shutdown),
3235 };
3236
3237 static int __init mwl8k_init(void)
3238 {
3239 return pci_register_driver(&mwl8k_driver);
3240 }
3241
3242 static void __exit mwl8k_exit(void)
3243 {
3244 pci_unregister_driver(&mwl8k_driver);
3245 }
3246
3247 module_init(mwl8k_init);
3248 module_exit(mwl8k_exit);
3249
3250 MODULE_DESCRIPTION(MWL8K_DESC);
3251 MODULE_VERSION(MWL8K_VERSION);
3252 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3253 MODULE_LICENSE("GPL");
Motorola kernel-slsi