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mwl8k: coding style cleanups
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / mwl8k.c
1 /*
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
4 *
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/completion.h>
20 #include <linux/etherdevice.h>
21 #include <net/mac80211.h>
22 #include <linux/moduleparam.h>
23 #include <linux/firmware.h>
24 #include <linux/workqueue.h>
25
26 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27 #define MWL8K_NAME KBUILD_MODNAME
28 #define MWL8K_VERSION "0.10"
29
30 static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
31 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
32 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
33 { }
34 };
35 MODULE_DEVICE_TABLE(pci, mwl8k_table);
36
37 /* Register definitions */
38 #define MWL8K_HIU_GEN_PTR 0x00000c10
39 #define MWL8K_MODE_STA 0x0000005a
40 #define MWL8K_MODE_AP 0x000000a5
41 #define MWL8K_HIU_INT_CODE 0x00000c14
42 #define MWL8K_FWSTA_READY 0xf0f1f2f4
43 #define MWL8K_FWAP_READY 0xf1f2f4a5
44 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
45 #define MWL8K_HIU_SCRATCH 0x00000c40
46
47 /* Host->device communications */
48 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
49 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
50 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
51 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
52 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
53 #define MWL8K_H2A_INT_DUMMY (1 << 20)
54 #define MWL8K_H2A_INT_RESET (1 << 15)
55 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
56 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
57
58 /* Device->host communications */
59 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
60 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
61 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
62 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
63 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
64 #define MWL8K_A2H_INT_DUMMY (1 << 20)
65 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
66 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
67 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
68 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
69 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
70 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
71 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
72 #define MWL8K_A2H_INT_RX_READY (1 << 1)
73 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
74
75 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
76 MWL8K_A2H_INT_CHNL_SWITCHED | \
77 MWL8K_A2H_INT_QUEUE_EMPTY | \
78 MWL8K_A2H_INT_RADAR_DETECT | \
79 MWL8K_A2H_INT_RADIO_ON | \
80 MWL8K_A2H_INT_RADIO_OFF | \
81 MWL8K_A2H_INT_MAC_EVENT | \
82 MWL8K_A2H_INT_OPC_DONE | \
83 MWL8K_A2H_INT_RX_READY | \
84 MWL8K_A2H_INT_TX_DONE)
85
86 /* WME stream classes */
87 #define WME_AC_BE 0 /* best effort */
88 #define WME_AC_BK 1 /* background */
89 #define WME_AC_VI 2 /* video */
90 #define WME_AC_VO 3 /* voice */
91
92 #define MWL8K_RX_QUEUES 1
93 #define MWL8K_TX_QUEUES 4
94
95 struct mwl8k_rx_queue {
96 int rx_desc_count;
97
98 /* hw receives here */
99 int rx_head;
100
101 /* refill descs here */
102 int rx_tail;
103
104 struct mwl8k_rx_desc *rx_desc_area;
105 dma_addr_t rx_desc_dma;
106 struct sk_buff **rx_skb;
107 };
108
109 struct mwl8k_tx_queue {
110 /* hw transmits here */
111 int tx_head;
112
113 /* sw appends here */
114 int tx_tail;
115
116 struct ieee80211_tx_queue_stats tx_stats;
117 struct mwl8k_tx_desc *tx_desc_area;
118 dma_addr_t tx_desc_dma;
119 struct sk_buff **tx_skb;
120 };
121
122 /* Pointers to the firmware data and meta information about it. */
123 struct mwl8k_firmware {
124 /* Microcode */
125 struct firmware *ucode;
126
127 /* Boot helper code */
128 struct firmware *helper;
129 };
130
131 struct mwl8k_priv {
132 void __iomem *regs;
133 struct ieee80211_hw *hw;
134
135 struct pci_dev *pdev;
136
137 /* firmware files and meta data */
138 struct mwl8k_firmware fw;
139 u32 part_num;
140
141 /* firmware access */
142 struct mutex fw_mutex;
143 struct task_struct *fw_mutex_owner;
144 int fw_mutex_depth;
145 struct completion *tx_wait;
146 struct completion *hostcmd_wait;
147
148 /* lock held over TX and TX reap */
149 spinlock_t tx_lock;
150
151 struct ieee80211_vif *vif;
152
153 struct ieee80211_channel *current_channel;
154
155 /* power management status cookie from firmware */
156 u32 *cookie;
157 dma_addr_t cookie_dma;
158
159 u16 num_mcaddrs;
160 u8 hw_rev;
161 u32 fw_rev;
162
163 /*
164 * Running count of TX packets in flight, to avoid
165 * iterating over the transmit rings each time.
166 */
167 int pending_tx_pkts;
168
169 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
170 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
171
172 /* PHY parameters */
173 struct ieee80211_supported_band band;
174 struct ieee80211_channel channels[14];
175 struct ieee80211_rate rates[12];
176
177 bool radio_on;
178 bool radio_short_preamble;
179 bool wmm_enabled;
180
181 /* XXX need to convert this to handle multiple interfaces */
182 bool capture_beacon;
183 u8 capture_bssid[ETH_ALEN];
184 struct sk_buff *beacon_skb;
185
186 /*
187 * This FJ worker has to be global as it is scheduled from the
188 * RX handler. At this point we don't know which interface it
189 * belongs to until the list of bssids waiting to complete join
190 * is checked.
191 */
192 struct work_struct finalize_join_worker;
193
194 /* Tasklet to reclaim TX descriptors and buffers after tx */
195 struct tasklet_struct tx_reclaim_task;
196
197 /* Work thread to serialize configuration requests */
198 struct workqueue_struct *config_wq;
199 };
200
201 /* Per interface specific private data */
202 struct mwl8k_vif {
203 /* backpointer to parent config block */
204 struct mwl8k_priv *priv;
205
206 /* BSS config of AP or IBSS from mac80211*/
207 struct ieee80211_bss_conf bss_info;
208
209 /* BSSID of AP or IBSS */
210 u8 bssid[ETH_ALEN];
211 u8 mac_addr[ETH_ALEN];
212
213 /*
214 * Subset of supported legacy rates.
215 * Intersection of AP and STA supported rates.
216 */
217 struct ieee80211_rate legacy_rates[12];
218
219 /* number of supported legacy rates */
220 u8 legacy_nrates;
221
222 /* Index into station database.Returned by update_sta_db call */
223 u8 peer_id;
224
225 /* Non AMPDU sequence number assigned by driver */
226 u16 seqno;
227 };
228
229 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
230
231 static const struct ieee80211_channel mwl8k_channels[] = {
232 { .center_freq = 2412, .hw_value = 1, },
233 { .center_freq = 2417, .hw_value = 2, },
234 { .center_freq = 2422, .hw_value = 3, },
235 { .center_freq = 2427, .hw_value = 4, },
236 { .center_freq = 2432, .hw_value = 5, },
237 { .center_freq = 2437, .hw_value = 6, },
238 { .center_freq = 2442, .hw_value = 7, },
239 { .center_freq = 2447, .hw_value = 8, },
240 { .center_freq = 2452, .hw_value = 9, },
241 { .center_freq = 2457, .hw_value = 10, },
242 { .center_freq = 2462, .hw_value = 11, },
243 };
244
245 static const struct ieee80211_rate mwl8k_rates[] = {
246 { .bitrate = 10, .hw_value = 2, },
247 { .bitrate = 20, .hw_value = 4, },
248 { .bitrate = 55, .hw_value = 11, },
249 { .bitrate = 60, .hw_value = 12, },
250 { .bitrate = 90, .hw_value = 18, },
251 { .bitrate = 110, .hw_value = 22, },
252 { .bitrate = 120, .hw_value = 24, },
253 { .bitrate = 180, .hw_value = 36, },
254 { .bitrate = 240, .hw_value = 48, },
255 { .bitrate = 360, .hw_value = 72, },
256 { .bitrate = 480, .hw_value = 96, },
257 { .bitrate = 540, .hw_value = 108, },
258 };
259
260 /* Set or get info from Firmware */
261 #define MWL8K_CMD_SET 0x0001
262 #define MWL8K_CMD_GET 0x0000
263
264 /* Firmware command codes */
265 #define MWL8K_CMD_CODE_DNLD 0x0001
266 #define MWL8K_CMD_GET_HW_SPEC 0x0003
267 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
268 #define MWL8K_CMD_GET_STAT 0x0014
269 #define MWL8K_CMD_RADIO_CONTROL 0x001c
270 #define MWL8K_CMD_RF_TX_POWER 0x001e
271 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
272 #define MWL8K_CMD_SET_POST_SCAN 0x0108
273 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
274 #define MWL8K_CMD_SET_AID 0x010d
275 #define MWL8K_CMD_SET_RATE 0x0110
276 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
277 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
278 #define MWL8K_CMD_SET_SLOT 0x0114
279 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
280 #define MWL8K_CMD_SET_WMM_MODE 0x0123
281 #define MWL8K_CMD_MIMO_CONFIG 0x0125
282 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
283 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
284 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
285 #define MWL8K_CMD_UPDATE_STADB 0x1123
286
287 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
288 {
289 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
290 snprintf(buf, bufsize, "%s", #x);\
291 return buf;\
292 } while (0)
293 switch (cmd & ~0x8000) {
294 MWL8K_CMDNAME(CODE_DNLD);
295 MWL8K_CMDNAME(GET_HW_SPEC);
296 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
297 MWL8K_CMDNAME(GET_STAT);
298 MWL8K_CMDNAME(RADIO_CONTROL);
299 MWL8K_CMDNAME(RF_TX_POWER);
300 MWL8K_CMDNAME(SET_PRE_SCAN);
301 MWL8K_CMDNAME(SET_POST_SCAN);
302 MWL8K_CMDNAME(SET_RF_CHANNEL);
303 MWL8K_CMDNAME(SET_AID);
304 MWL8K_CMDNAME(SET_RATE);
305 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
306 MWL8K_CMDNAME(RTS_THRESHOLD);
307 MWL8K_CMDNAME(SET_SLOT);
308 MWL8K_CMDNAME(SET_EDCA_PARAMS);
309 MWL8K_CMDNAME(SET_WMM_MODE);
310 MWL8K_CMDNAME(MIMO_CONFIG);
311 MWL8K_CMDNAME(USE_FIXED_RATE);
312 MWL8K_CMDNAME(ENABLE_SNIFFER);
313 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
314 MWL8K_CMDNAME(UPDATE_STADB);
315 default:
316 snprintf(buf, bufsize, "0x%x", cmd);
317 }
318 #undef MWL8K_CMDNAME
319
320 return buf;
321 }
322
323 /* Hardware and firmware reset */
324 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
325 {
326 iowrite32(MWL8K_H2A_INT_RESET,
327 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
328 iowrite32(MWL8K_H2A_INT_RESET,
329 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
330 msleep(20);
331 }
332
333 /* Release fw image */
334 static void mwl8k_release_fw(struct firmware **fw)
335 {
336 if (*fw == NULL)
337 return;
338 release_firmware(*fw);
339 *fw = NULL;
340 }
341
342 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
343 {
344 mwl8k_release_fw(&priv->fw.ucode);
345 mwl8k_release_fw(&priv->fw.helper);
346 }
347
348 /* Request fw image */
349 static int mwl8k_request_fw(struct mwl8k_priv *priv,
350 const char *fname, struct firmware **fw)
351 {
352 /* release current image */
353 if (*fw != NULL)
354 mwl8k_release_fw(fw);
355
356 return request_firmware((const struct firmware **)fw,
357 fname, &priv->pdev->dev);
358 }
359
360 static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
361 {
362 u8 filename[64];
363 int rc;
364
365 priv->part_num = part_num;
366
367 snprintf(filename, sizeof(filename),
368 "mwl8k/helper_%u.fw", priv->part_num);
369
370 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
371 if (rc) {
372 printk(KERN_ERR "%s: Error requesting helper firmware "
373 "file %s\n", pci_name(priv->pdev), filename);
374 return rc;
375 }
376
377 snprintf(filename, sizeof(filename),
378 "mwl8k/fmimage_%u.fw", priv->part_num);
379
380 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
381 if (rc) {
382 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
383 pci_name(priv->pdev), filename);
384 mwl8k_release_fw(&priv->fw.helper);
385 return rc;
386 }
387
388 return 0;
389 }
390
391 struct mwl8k_cmd_pkt {
392 __le16 code;
393 __le16 length;
394 __le16 seq_num;
395 __le16 result;
396 char payload[0];
397 } __attribute__((packed));
398
399 /*
400 * Firmware loading.
401 */
402 static int
403 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
404 {
405 void __iomem *regs = priv->regs;
406 dma_addr_t dma_addr;
407 int loops;
408
409 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
410 if (pci_dma_mapping_error(priv->pdev, dma_addr))
411 return -ENOMEM;
412
413 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
414 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
415 iowrite32(MWL8K_H2A_INT_DOORBELL,
416 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
417 iowrite32(MWL8K_H2A_INT_DUMMY,
418 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
419
420 loops = 1000;
421 do {
422 u32 int_code;
423
424 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
425 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
426 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
427 break;
428 }
429
430 udelay(1);
431 } while (--loops);
432
433 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
434
435 return loops ? 0 : -ETIMEDOUT;
436 }
437
438 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
439 const u8 *data, size_t length)
440 {
441 struct mwl8k_cmd_pkt *cmd;
442 int done;
443 int rc = 0;
444
445 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
446 if (cmd == NULL)
447 return -ENOMEM;
448
449 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
450 cmd->seq_num = 0;
451 cmd->result = 0;
452
453 done = 0;
454 while (length) {
455 int block_size = length > 256 ? 256 : length;
456
457 memcpy(cmd->payload, data + done, block_size);
458 cmd->length = cpu_to_le16(block_size);
459
460 rc = mwl8k_send_fw_load_cmd(priv, cmd,
461 sizeof(*cmd) + block_size);
462 if (rc)
463 break;
464
465 done += block_size;
466 length -= block_size;
467 }
468
469 if (!rc) {
470 cmd->length = 0;
471 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
472 }
473
474 kfree(cmd);
475
476 return rc;
477 }
478
479 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
480 const u8 *data, size_t length)
481 {
482 unsigned char *buffer;
483 int may_continue, rc = 0;
484 u32 done, prev_block_size;
485
486 buffer = kmalloc(1024, GFP_KERNEL);
487 if (buffer == NULL)
488 return -ENOMEM;
489
490 done = 0;
491 prev_block_size = 0;
492 may_continue = 1000;
493 while (may_continue > 0) {
494 u32 block_size;
495
496 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
497 if (block_size & 1) {
498 block_size &= ~1;
499 may_continue--;
500 } else {
501 done += prev_block_size;
502 length -= prev_block_size;
503 }
504
505 if (block_size > 1024 || block_size > length) {
506 rc = -EOVERFLOW;
507 break;
508 }
509
510 if (length == 0) {
511 rc = 0;
512 break;
513 }
514
515 if (block_size == 0) {
516 rc = -EPROTO;
517 may_continue--;
518 udelay(1);
519 continue;
520 }
521
522 prev_block_size = block_size;
523 memcpy(buffer, data + done, block_size);
524
525 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
526 if (rc)
527 break;
528 }
529
530 if (!rc && length != 0)
531 rc = -EREMOTEIO;
532
533 kfree(buffer);
534
535 return rc;
536 }
537
538 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
539 {
540 struct mwl8k_priv *priv = hw->priv;
541 struct firmware *fw = priv->fw.ucode;
542 int rc;
543 int loops;
544
545 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
546 struct firmware *helper = priv->fw.helper;
547
548 if (helper == NULL) {
549 printk(KERN_ERR "%s: helper image needed but none "
550 "given\n", pci_name(priv->pdev));
551 return -EINVAL;
552 }
553
554 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
555 if (rc) {
556 printk(KERN_ERR "%s: unable to load firmware "
557 "helper image\n", pci_name(priv->pdev));
558 return rc;
559 }
560 msleep(1);
561
562 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
563 } else {
564 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
565 }
566
567 if (rc) {
568 printk(KERN_ERR "%s: unable to load firmware image\n",
569 pci_name(priv->pdev));
570 return rc;
571 }
572
573 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
574 msleep(1);
575
576 loops = 200000;
577 do {
578 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
579 == MWL8K_FWSTA_READY)
580 break;
581 udelay(1);
582 } while (--loops);
583
584 return loops ? 0 : -ETIMEDOUT;
585 }
586
587
588 /*
589 * Defines shared between transmission and reception.
590 */
591 /* HT control fields for firmware */
592 struct ewc_ht_info {
593 __le16 control1;
594 __le16 control2;
595 __le16 control3;
596 } __attribute__((packed));
597
598 /* Firmware Station database operations */
599 #define MWL8K_STA_DB_ADD_ENTRY 0
600 #define MWL8K_STA_DB_MODIFY_ENTRY 1
601 #define MWL8K_STA_DB_DEL_ENTRY 2
602 #define MWL8K_STA_DB_FLUSH 3
603
604 /* Peer Entry flags - used to define the type of the peer node */
605 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
606
607 #define MWL8K_IEEE_LEGACY_DATA_RATES 12
608 #define MWL8K_MCS_BITMAP_SIZE 16
609
610 struct peer_capability_info {
611 /* Peer type - AP vs. STA. */
612 __u8 peer_type;
613
614 /* Basic 802.11 capabilities from assoc resp. */
615 __le16 basic_caps;
616
617 /* Set if peer supports 802.11n high throughput (HT). */
618 __u8 ht_support;
619
620 /* Valid if HT is supported. */
621 __le16 ht_caps;
622 __u8 extended_ht_caps;
623 struct ewc_ht_info ewc_info;
624
625 /* Legacy rate table. Intersection of our rates and peer rates. */
626 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
627
628 /* HT rate table. Intersection of our rates and peer rates. */
629 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
630 __u8 pad[16];
631
632 /* If set, interoperability mode, no proprietary extensions. */
633 __u8 interop;
634 __u8 pad2;
635 __u8 station_id;
636 __le16 amsdu_enabled;
637 } __attribute__((packed));
638
639 /* Inline functions to manipulate QoS field in data descriptor. */
640 static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
641 {
642 u16 val_mask = 1 << 4;
643
644 /* End of Service Period Bit 4 */
645 return qos | val_mask;
646 }
647
648 static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
649 {
650 u16 val_mask = 0x3;
651 u8 shift = 5;
652 u16 qos_mask = ~(val_mask << shift);
653
654 /* Ack Policy Bit 5-6 */
655 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
656 }
657
658 static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
659 {
660 u16 val_mask = 1 << 7;
661
662 /* AMSDU present Bit 7 */
663 return qos | val_mask;
664 }
665
666 static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
667 {
668 u16 val_mask = 0xff;
669 u8 shift = 8;
670 u16 qos_mask = ~(val_mask << shift);
671
672 /* Queue Length Bits 8-15 */
673 return (qos & qos_mask) | ((len & val_mask) << shift);
674 }
675
676 /* DMA header used by firmware and hardware. */
677 struct mwl8k_dma_data {
678 __le16 fwlen;
679 struct ieee80211_hdr wh;
680 } __attribute__((packed));
681
682 /* Routines to add/remove DMA header from skb. */
683 static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
684 {
685 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
686 void *dst, *src = &tr->wh;
687 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
688 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
689
690 dst = (void *)tr + space;
691 if (dst != src) {
692 memmove(dst, src, hdrlen);
693 skb_pull(skb, space);
694 }
695 }
696
697 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
698 {
699 struct ieee80211_hdr *wh;
700 u32 hdrlen, pktlen;
701 struct mwl8k_dma_data *tr;
702
703 wh = (struct ieee80211_hdr *)skb->data;
704 hdrlen = ieee80211_hdrlen(wh->frame_control);
705 pktlen = skb->len;
706
707 /*
708 * Copy up/down the 802.11 header; the firmware requires
709 * we present a 2-byte payload length followed by a
710 * 4-address header (w/o QoS), followed (optionally) by
711 * any WEP/ExtIV header (but only filled in for CCMP).
712 */
713 if (hdrlen != sizeof(struct mwl8k_dma_data))
714 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
715
716 tr = (struct mwl8k_dma_data *)skb->data;
717 if (wh != &tr->wh)
718 memmove(&tr->wh, wh, hdrlen);
719
720 /* Clear addr4 */
721 memset(tr->wh.addr4, 0, ETH_ALEN);
722
723 /*
724 * Firmware length is the length of the fully formed "802.11
725 * payload". That is, everything except for the 802.11 header.
726 * This includes all crypto material including the MIC.
727 */
728 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
729 }
730
731
732 /*
733 * Packet reception.
734 */
735 #define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
736
737 struct mwl8k_rx_desc {
738 __le16 pkt_len;
739 __u8 link_quality;
740 __u8 noise_level;
741 __le32 pkt_phys_addr;
742 __le32 next_rx_desc_phys_addr;
743 __le16 qos_control;
744 __le16 rate_info;
745 __le32 pad0[4];
746 __u8 rssi;
747 __u8 channel;
748 __le16 pad1;
749 __u8 rx_ctrl;
750 __u8 rx_status;
751 __u8 pad2[2];
752 } __attribute__((packed));
753
754 #define MWL8K_RX_DESCS 256
755 #define MWL8K_RX_MAXSZ 3800
756
757 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
758 {
759 struct mwl8k_priv *priv = hw->priv;
760 struct mwl8k_rx_queue *rxq = priv->rxq + index;
761 int size;
762 int i;
763
764 rxq->rx_desc_count = 0;
765 rxq->rx_head = 0;
766 rxq->rx_tail = 0;
767
768 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
769
770 rxq->rx_desc_area =
771 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
772 if (rxq->rx_desc_area == NULL) {
773 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
774 wiphy_name(hw->wiphy));
775 return -ENOMEM;
776 }
777 memset(rxq->rx_desc_area, 0, size);
778
779 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
780 sizeof(*rxq->rx_skb), GFP_KERNEL);
781 if (rxq->rx_skb == NULL) {
782 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
783 wiphy_name(hw->wiphy));
784 pci_free_consistent(priv->pdev, size,
785 rxq->rx_desc_area, rxq->rx_desc_dma);
786 return -ENOMEM;
787 }
788 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
789
790 for (i = 0; i < MWL8K_RX_DESCS; i++) {
791 struct mwl8k_rx_desc *rx_desc;
792 int nexti;
793
794 rx_desc = rxq->rx_desc_area + i;
795 nexti = (i + 1) % MWL8K_RX_DESCS;
796
797 rx_desc->next_rx_desc_phys_addr =
798 cpu_to_le32(rxq->rx_desc_dma
799 + nexti * sizeof(*rx_desc));
800 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
801 }
802
803 return 0;
804 }
805
806 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
807 {
808 struct mwl8k_priv *priv = hw->priv;
809 struct mwl8k_rx_queue *rxq = priv->rxq + index;
810 int refilled;
811
812 refilled = 0;
813 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
814 struct sk_buff *skb;
815 int rx;
816
817 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
818 if (skb == NULL)
819 break;
820
821 rxq->rx_desc_count++;
822
823 rx = rxq->rx_tail;
824 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
825
826 rxq->rx_desc_area[rx].pkt_phys_addr =
827 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
828 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
829
830 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
831 rxq->rx_skb[rx] = skb;
832 wmb();
833 rxq->rx_desc_area[rx].rx_ctrl = 0;
834
835 refilled++;
836 }
837
838 return refilled;
839 }
840
841 /* Must be called only when the card's reception is completely halted */
842 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
843 {
844 struct mwl8k_priv *priv = hw->priv;
845 struct mwl8k_rx_queue *rxq = priv->rxq + index;
846 int i;
847
848 for (i = 0; i < MWL8K_RX_DESCS; i++) {
849 if (rxq->rx_skb[i] != NULL) {
850 unsigned long addr;
851
852 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
853 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
854 PCI_DMA_FROMDEVICE);
855 kfree_skb(rxq->rx_skb[i]);
856 rxq->rx_skb[i] = NULL;
857 }
858 }
859
860 kfree(rxq->rx_skb);
861 rxq->rx_skb = NULL;
862
863 pci_free_consistent(priv->pdev,
864 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
865 rxq->rx_desc_area, rxq->rx_desc_dma);
866 rxq->rx_desc_area = NULL;
867 }
868
869
870 /*
871 * Scan a list of BSSIDs to process for finalize join.
872 * Allows for extension to process multiple BSSIDs.
873 */
874 static inline int
875 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
876 {
877 return priv->capture_beacon &&
878 ieee80211_is_beacon(wh->frame_control) &&
879 !compare_ether_addr(wh->addr3, priv->capture_bssid);
880 }
881
882 static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
883 struct sk_buff *skb)
884 {
885 priv->capture_beacon = false;
886 memset(priv->capture_bssid, 0, ETH_ALEN);
887
888 /*
889 * Use GFP_ATOMIC as rxq_process is called from
890 * the primary interrupt handler, memory allocation call
891 * must not sleep.
892 */
893 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
894 if (priv->beacon_skb != NULL)
895 queue_work(priv->config_wq,
896 &priv->finalize_join_worker);
897 }
898
899 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
900 {
901 struct mwl8k_priv *priv = hw->priv;
902 struct mwl8k_rx_queue *rxq = priv->rxq + index;
903 int processed;
904
905 processed = 0;
906 while (rxq->rx_desc_count && limit--) {
907 struct mwl8k_rx_desc *rx_desc;
908 struct sk_buff *skb;
909 struct ieee80211_rx_status status;
910 unsigned long addr;
911 struct ieee80211_hdr *wh;
912
913 rx_desc = rxq->rx_desc_area + rxq->rx_head;
914 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
915 break;
916 rmb();
917
918 skb = rxq->rx_skb[rxq->rx_head];
919 if (skb == NULL)
920 break;
921 rxq->rx_skb[rxq->rx_head] = NULL;
922
923 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
924 rxq->rx_desc_count--;
925
926 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
927 pci_unmap_single(priv->pdev, addr,
928 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
929
930 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
931 mwl8k_remove_dma_header(skb);
932
933 wh = (struct ieee80211_hdr *)skb->data;
934
935 /*
936 * Check for a pending join operation. Save a
937 * copy of the beacon and schedule a tasklet to
938 * send a FINALIZE_JOIN command to the firmware.
939 */
940 if (mwl8k_capture_bssid(priv, wh))
941 mwl8k_save_beacon(priv, skb);
942
943 memset(&status, 0, sizeof(status));
944 status.mactime = 0;
945 status.signal = -rx_desc->rssi;
946 status.noise = -rx_desc->noise_level;
947 status.qual = rx_desc->link_quality;
948 status.antenna = 1;
949 status.rate_idx = 1;
950 status.flag = 0;
951 status.band = IEEE80211_BAND_2GHZ;
952 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
953 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
954 ieee80211_rx_irqsafe(hw, skb);
955
956 processed++;
957 }
958
959 return processed;
960 }
961
962
963 /*
964 * Packet transmission.
965 */
966
967 /* Transmit queue assignment. */
968 enum {
969 MWL8K_WME_AC_BK = 0, /* background access */
970 MWL8K_WME_AC_BE = 1, /* best effort access */
971 MWL8K_WME_AC_VI = 2, /* video access */
972 MWL8K_WME_AC_VO = 3, /* voice access */
973 };
974
975 /* Transmit packet ACK policy */
976 #define MWL8K_TXD_ACK_POLICY_NORMAL 0
977 #define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
978
979 #define GET_TXQ(_ac) (\
980 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
981 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
982 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
983 MWL8K_WME_AC_BE)
984
985 #define MWL8K_TXD_STATUS_OK 0x00000001
986 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
987 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
988 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
989 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
990
991 struct mwl8k_tx_desc {
992 __le32 status;
993 __u8 data_rate;
994 __u8 tx_priority;
995 __le16 qos_control;
996 __le32 pkt_phys_addr;
997 __le16 pkt_len;
998 __u8 dest_MAC_addr[ETH_ALEN];
999 __le32 next_tx_desc_phys_addr;
1000 __le32 reserved;
1001 __le16 rate_info;
1002 __u8 peer_id;
1003 __u8 tx_frag_cnt;
1004 } __attribute__((packed));
1005
1006 #define MWL8K_TX_DESCS 128
1007
1008 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1009 {
1010 struct mwl8k_priv *priv = hw->priv;
1011 struct mwl8k_tx_queue *txq = priv->txq + index;
1012 int size;
1013 int i;
1014
1015 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1016 txq->tx_stats.limit = MWL8K_TX_DESCS;
1017 txq->tx_head = 0;
1018 txq->tx_tail = 0;
1019
1020 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1021
1022 txq->tx_desc_area =
1023 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1024 if (txq->tx_desc_area == NULL) {
1025 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1026 wiphy_name(hw->wiphy));
1027 return -ENOMEM;
1028 }
1029 memset(txq->tx_desc_area, 0, size);
1030
1031 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1032 GFP_KERNEL);
1033 if (txq->tx_skb == NULL) {
1034 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1035 wiphy_name(hw->wiphy));
1036 pci_free_consistent(priv->pdev, size,
1037 txq->tx_desc_area, txq->tx_desc_dma);
1038 return -ENOMEM;
1039 }
1040 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1041
1042 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1043 struct mwl8k_tx_desc *tx_desc;
1044 int nexti;
1045
1046 tx_desc = txq->tx_desc_area + i;
1047 nexti = (i + 1) % MWL8K_TX_DESCS;
1048
1049 tx_desc->status = 0;
1050 tx_desc->next_tx_desc_phys_addr =
1051 cpu_to_le32(txq->tx_desc_dma +
1052 nexti * sizeof(*tx_desc));
1053 }
1054
1055 return 0;
1056 }
1057
1058 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1059 {
1060 iowrite32(MWL8K_H2A_INT_PPA_READY,
1061 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1062 iowrite32(MWL8K_H2A_INT_DUMMY,
1063 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1064 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1065 }
1066
1067 static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1068 {
1069 return priv->pending_tx_pkts;
1070 }
1071
1072 struct mwl8k_txq_info {
1073 u32 fw_owned;
1074 u32 drv_owned;
1075 u32 unused;
1076 u32 len;
1077 u32 head;
1078 u32 tail;
1079 };
1080
1081 static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1082 struct mwl8k_txq_info *txinfo)
1083 {
1084 int count, desc, status;
1085 struct mwl8k_tx_queue *txq;
1086 struct mwl8k_tx_desc *tx_desc;
1087 int ndescs = 0;
1088
1089 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1090
1091 spin_lock_bh(&priv->tx_lock);
1092 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
1093 txq = priv->txq + count;
1094 txinfo[count].len = txq->tx_stats.len;
1095 txinfo[count].head = txq->tx_head;
1096 txinfo[count].tail = txq->tx_tail;
1097 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1098 tx_desc = txq->tx_desc_area + desc;
1099 status = le32_to_cpu(tx_desc->status);
1100
1101 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1102 txinfo[count].fw_owned++;
1103 else
1104 txinfo[count].drv_owned++;
1105
1106 if (tx_desc->pkt_len == 0)
1107 txinfo[count].unused++;
1108 }
1109 }
1110 spin_unlock_bh(&priv->tx_lock);
1111
1112 return ndescs;
1113 }
1114
1115 /*
1116 * Must be called with hw->fw_mutex held and tx queues stopped.
1117 */
1118 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1119 {
1120 struct mwl8k_priv *priv = hw->priv;
1121 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1122 u32 count;
1123 unsigned long timeout;
1124
1125 might_sleep();
1126
1127 spin_lock_bh(&priv->tx_lock);
1128 count = mwl8k_txq_busy(priv);
1129 if (count) {
1130 priv->tx_wait = &cmd_wait;
1131 if (priv->radio_on)
1132 mwl8k_tx_start(priv);
1133 }
1134 spin_unlock_bh(&priv->tx_lock);
1135
1136 if (count) {
1137 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
1138 int index;
1139 int newcount;
1140
1141 timeout = wait_for_completion_timeout(&cmd_wait,
1142 msecs_to_jiffies(5000));
1143 if (timeout)
1144 return 0;
1145
1146 spin_lock_bh(&priv->tx_lock);
1147 priv->tx_wait = NULL;
1148 newcount = mwl8k_txq_busy(priv);
1149 spin_unlock_bh(&priv->tx_lock);
1150
1151 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
1152 __func__, __LINE__, count, newcount);
1153
1154 mwl8k_scan_tx_ring(priv, txinfo);
1155 for (index = 0; index < MWL8K_TX_QUEUES; index++)
1156 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1157 "DRV:%u U:%u\n",
1158 index,
1159 txinfo[index].len,
1160 txinfo[index].head,
1161 txinfo[index].tail,
1162 txinfo[index].fw_owned,
1163 txinfo[index].drv_owned,
1164 txinfo[index].unused);
1165
1166 return -ETIMEDOUT;
1167 }
1168
1169 return 0;
1170 }
1171
1172 #define MWL8K_TXD_SUCCESS(status) \
1173 ((status) & (MWL8K_TXD_STATUS_OK | \
1174 MWL8K_TXD_STATUS_OK_RETRY | \
1175 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1176
1177 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1178 {
1179 struct mwl8k_priv *priv = hw->priv;
1180 struct mwl8k_tx_queue *txq = priv->txq + index;
1181 int wake = 0;
1182
1183 while (txq->tx_stats.len > 0) {
1184 int tx;
1185 struct mwl8k_tx_desc *tx_desc;
1186 unsigned long addr;
1187 int size;
1188 struct sk_buff *skb;
1189 struct ieee80211_tx_info *info;
1190 u32 status;
1191
1192 tx = txq->tx_head;
1193 tx_desc = txq->tx_desc_area + tx;
1194
1195 status = le32_to_cpu(tx_desc->status);
1196
1197 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1198 if (!force)
1199 break;
1200 tx_desc->status &=
1201 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1202 }
1203
1204 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1205 BUG_ON(txq->tx_stats.len == 0);
1206 txq->tx_stats.len--;
1207 priv->pending_tx_pkts--;
1208
1209 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1210 size = le16_to_cpu(tx_desc->pkt_len);
1211 skb = txq->tx_skb[tx];
1212 txq->tx_skb[tx] = NULL;
1213
1214 BUG_ON(skb == NULL);
1215 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1216
1217 mwl8k_remove_dma_header(skb);
1218
1219 /* Mark descriptor as unused */
1220 tx_desc->pkt_phys_addr = 0;
1221 tx_desc->pkt_len = 0;
1222
1223 info = IEEE80211_SKB_CB(skb);
1224 ieee80211_tx_info_clear_status(info);
1225 if (MWL8K_TXD_SUCCESS(status))
1226 info->flags |= IEEE80211_TX_STAT_ACK;
1227
1228 ieee80211_tx_status_irqsafe(hw, skb);
1229
1230 wake = 1;
1231 }
1232
1233 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1234 ieee80211_wake_queue(hw, index);
1235 }
1236
1237 /* must be called only when the card's transmit is completely halted */
1238 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1239 {
1240 struct mwl8k_priv *priv = hw->priv;
1241 struct mwl8k_tx_queue *txq = priv->txq + index;
1242
1243 mwl8k_txq_reclaim(hw, index, 1);
1244
1245 kfree(txq->tx_skb);
1246 txq->tx_skb = NULL;
1247
1248 pci_free_consistent(priv->pdev,
1249 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1250 txq->tx_desc_area, txq->tx_desc_dma);
1251 txq->tx_desc_area = NULL;
1252 }
1253
1254 static int
1255 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1256 {
1257 struct mwl8k_priv *priv = hw->priv;
1258 struct ieee80211_tx_info *tx_info;
1259 struct mwl8k_vif *mwl8k_vif;
1260 struct ieee80211_hdr *wh;
1261 struct mwl8k_tx_queue *txq;
1262 struct mwl8k_tx_desc *tx;
1263 dma_addr_t dma;
1264 u32 txstatus;
1265 u8 txdatarate;
1266 u16 qos;
1267
1268 wh = (struct ieee80211_hdr *)skb->data;
1269 if (ieee80211_is_data_qos(wh->frame_control))
1270 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1271 else
1272 qos = 0;
1273
1274 mwl8k_add_dma_header(skb);
1275 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1276
1277 tx_info = IEEE80211_SKB_CB(skb);
1278 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1279
1280 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1281 u16 seqno = mwl8k_vif->seqno;
1282
1283 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1284 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1285 mwl8k_vif->seqno = seqno++ % 4096;
1286 }
1287
1288 /* Setup firmware control bit fields for each frame type. */
1289 txstatus = 0;
1290 txdatarate = 0;
1291 if (ieee80211_is_mgmt(wh->frame_control) ||
1292 ieee80211_is_ctl(wh->frame_control)) {
1293 txdatarate = 0;
1294 qos = mwl8k_qos_setbit_eosp(qos);
1295 /* Set Queue size to unspecified */
1296 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1297 } else if (ieee80211_is_data(wh->frame_control)) {
1298 txdatarate = 1;
1299 if (is_multicast_ether_addr(wh->addr1))
1300 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1301
1302 /* Send pkt in an aggregate if AMPDU frame. */
1303 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1304 qos = mwl8k_qos_setbit_ack(qos,
1305 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1306 else
1307 qos = mwl8k_qos_setbit_ack(qos,
1308 MWL8K_TXD_ACK_POLICY_NORMAL);
1309
1310 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1311 qos = mwl8k_qos_setbit_amsdu(qos);
1312 }
1313
1314 dma = pci_map_single(priv->pdev, skb->data,
1315 skb->len, PCI_DMA_TODEVICE);
1316
1317 if (pci_dma_mapping_error(priv->pdev, dma)) {
1318 printk(KERN_DEBUG "%s: failed to dma map skb, "
1319 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1320 dev_kfree_skb(skb);
1321 return NETDEV_TX_OK;
1322 }
1323
1324 spin_lock_bh(&priv->tx_lock);
1325
1326 txq = priv->txq + index;
1327
1328 BUG_ON(txq->tx_skb[txq->tx_tail] != NULL);
1329 txq->tx_skb[txq->tx_tail] = skb;
1330
1331 tx = txq->tx_desc_area + txq->tx_tail;
1332 tx->data_rate = txdatarate;
1333 tx->tx_priority = index;
1334 tx->qos_control = cpu_to_le16(qos);
1335 tx->pkt_phys_addr = cpu_to_le32(dma);
1336 tx->pkt_len = cpu_to_le16(skb->len);
1337 tx->rate_info = 0;
1338 tx->peer_id = mwl8k_vif->peer_id;
1339 wmb();
1340 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1341
1342 txq->tx_stats.count++;
1343 txq->tx_stats.len++;
1344 priv->pending_tx_pkts++;
1345
1346 txq->tx_tail++;
1347 if (txq->tx_tail == MWL8K_TX_DESCS)
1348 txq->tx_tail = 0;
1349
1350 if (txq->tx_head == txq->tx_tail)
1351 ieee80211_stop_queue(hw, index);
1352
1353 mwl8k_tx_start(priv);
1354
1355 spin_unlock_bh(&priv->tx_lock);
1356
1357 return NETDEV_TX_OK;
1358 }
1359
1360
1361 /*
1362 * Firmware access.
1363 *
1364 * We have the following requirements for issuing firmware commands:
1365 * - Some commands require that the packet transmit path is idle when
1366 * the command is issued. (For simplicity, we'll just quiesce the
1367 * transmit path for every command.)
1368 * - There are certain sequences of commands that need to be issued to
1369 * the hardware sequentially, with no other intervening commands.
1370 *
1371 * This leads to an implementation of a "firmware lock" as a mutex that
1372 * can be taken recursively, and which is taken by both the low-level
1373 * command submission function (mwl8k_post_cmd) as well as any users of
1374 * that function that require issuing of an atomic sequence of commands,
1375 * and quiesces the transmit path whenever it's taken.
1376 */
1377 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1378 {
1379 struct mwl8k_priv *priv = hw->priv;
1380
1381 if (priv->fw_mutex_owner != current) {
1382 int rc;
1383
1384 mutex_lock(&priv->fw_mutex);
1385 ieee80211_stop_queues(hw);
1386
1387 rc = mwl8k_tx_wait_empty(hw);
1388 if (rc) {
1389 ieee80211_wake_queues(hw);
1390 mutex_unlock(&priv->fw_mutex);
1391
1392 return rc;
1393 }
1394
1395 priv->fw_mutex_owner = current;
1396 }
1397
1398 priv->fw_mutex_depth++;
1399
1400 return 0;
1401 }
1402
1403 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1404 {
1405 struct mwl8k_priv *priv = hw->priv;
1406
1407 if (!--priv->fw_mutex_depth) {
1408 ieee80211_wake_queues(hw);
1409 priv->fw_mutex_owner = NULL;
1410 mutex_unlock(&priv->fw_mutex);
1411 }
1412 }
1413
1414
1415 /*
1416 * Command processing.
1417 */
1418
1419 /* Timeout firmware commands after 2000ms */
1420 #define MWL8K_CMD_TIMEOUT_MS 2000
1421
1422 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1423 {
1424 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1425 struct mwl8k_priv *priv = hw->priv;
1426 void __iomem *regs = priv->regs;
1427 dma_addr_t dma_addr;
1428 unsigned int dma_size;
1429 int rc;
1430 unsigned long timeout = 0;
1431 u8 buf[32];
1432
1433 cmd->result = 0xffff;
1434 dma_size = le16_to_cpu(cmd->length);
1435 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1436 PCI_DMA_BIDIRECTIONAL);
1437 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1438 return -ENOMEM;
1439
1440 rc = mwl8k_fw_lock(hw);
1441 if (rc) {
1442 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1443 PCI_DMA_BIDIRECTIONAL);
1444 return rc;
1445 }
1446
1447 priv->hostcmd_wait = &cmd_wait;
1448 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1449 iowrite32(MWL8K_H2A_INT_DOORBELL,
1450 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1451 iowrite32(MWL8K_H2A_INT_DUMMY,
1452 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1453
1454 timeout = wait_for_completion_timeout(&cmd_wait,
1455 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1456
1457 priv->hostcmd_wait = NULL;
1458
1459 mwl8k_fw_unlock(hw);
1460
1461 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1462 PCI_DMA_BIDIRECTIONAL);
1463
1464 if (!timeout) {
1465 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1466 wiphy_name(hw->wiphy),
1467 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1468 MWL8K_CMD_TIMEOUT_MS);
1469 rc = -ETIMEDOUT;
1470 } else {
1471 rc = cmd->result ? -EINVAL : 0;
1472 if (rc)
1473 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1474 wiphy_name(hw->wiphy),
1475 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1476 le16_to_cpu(cmd->result));
1477 }
1478
1479 return rc;
1480 }
1481
1482 /*
1483 * GET_HW_SPEC.
1484 */
1485 struct mwl8k_cmd_get_hw_spec {
1486 struct mwl8k_cmd_pkt header;
1487 __u8 hw_rev;
1488 __u8 host_interface;
1489 __le16 num_mcaddrs;
1490 __u8 perm_addr[ETH_ALEN];
1491 __le16 region_code;
1492 __le32 fw_rev;
1493 __le32 ps_cookie;
1494 __le32 caps;
1495 __u8 mcs_bitmap[16];
1496 __le32 rx_queue_ptr;
1497 __le32 num_tx_queues;
1498 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1499 __le32 caps2;
1500 __le32 num_tx_desc_per_queue;
1501 __le32 total_rx_desc;
1502 } __attribute__((packed));
1503
1504 static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1505 {
1506 struct mwl8k_priv *priv = hw->priv;
1507 struct mwl8k_cmd_get_hw_spec *cmd;
1508 int rc;
1509 int i;
1510
1511 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1512 if (cmd == NULL)
1513 return -ENOMEM;
1514
1515 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1516 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1517
1518 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1519 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1520 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
1521 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1522 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1523 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
1524 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1525 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
1526
1527 rc = mwl8k_post_cmd(hw, &cmd->header);
1528
1529 if (!rc) {
1530 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1531 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1532 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1533 priv->hw_rev = cmd->hw_rev;
1534 }
1535
1536 kfree(cmd);
1537 return rc;
1538 }
1539
1540 /*
1541 * CMD_MAC_MULTICAST_ADR.
1542 */
1543 struct mwl8k_cmd_mac_multicast_adr {
1544 struct mwl8k_cmd_pkt header;
1545 __le16 action;
1546 __le16 numaddr;
1547 __u8 addr[0][ETH_ALEN];
1548 };
1549
1550 #define MWL8K_ENABLE_RX_MULTICAST 0x000F
1551
1552 static struct mwl8k_cmd_pkt *
1553 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1554 int mc_count, struct dev_addr_list *mclist)
1555 {
1556 struct mwl8k_priv *priv = hw->priv;
1557 struct mwl8k_cmd_mac_multicast_adr *cmd;
1558 int size;
1559 int i;
1560
1561 if (mc_count > priv->num_mcaddrs)
1562 mc_count = priv->num_mcaddrs;
1563
1564 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1565
1566 cmd = kzalloc(size, GFP_ATOMIC);
1567 if (cmd == NULL)
1568 return NULL;
1569
1570 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1571 cmd->header.length = cpu_to_le16(size);
1572 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1573 cmd->numaddr = cpu_to_le16(mc_count);
1574
1575 for (i = 0; i < mc_count && mclist; i++) {
1576 if (mclist->da_addrlen != ETH_ALEN) {
1577 kfree(cmd);
1578 return NULL;
1579 }
1580 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1581 mclist = mclist->next;
1582 }
1583
1584 return &cmd->header;
1585 }
1586
1587 /*
1588 * CMD_802_11_GET_STAT.
1589 */
1590 struct mwl8k_cmd_802_11_get_stat {
1591 struct mwl8k_cmd_pkt header;
1592 __le32 stats[64];
1593 } __attribute__((packed));
1594
1595 #define MWL8K_STAT_ACK_FAILURE 9
1596 #define MWL8K_STAT_RTS_FAILURE 12
1597 #define MWL8K_STAT_FCS_ERROR 24
1598 #define MWL8K_STAT_RTS_SUCCESS 11
1599
1600 static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1601 struct ieee80211_low_level_stats *stats)
1602 {
1603 struct mwl8k_cmd_802_11_get_stat *cmd;
1604 int rc;
1605
1606 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1607 if (cmd == NULL)
1608 return -ENOMEM;
1609
1610 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1611 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1612
1613 rc = mwl8k_post_cmd(hw, &cmd->header);
1614 if (!rc) {
1615 stats->dot11ACKFailureCount =
1616 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1617 stats->dot11RTSFailureCount =
1618 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1619 stats->dot11FCSErrorCount =
1620 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1621 stats->dot11RTSSuccessCount =
1622 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1623 }
1624 kfree(cmd);
1625
1626 return rc;
1627 }
1628
1629 /*
1630 * CMD_802_11_RADIO_CONTROL.
1631 */
1632 struct mwl8k_cmd_802_11_radio_control {
1633 struct mwl8k_cmd_pkt header;
1634 __le16 action;
1635 __le16 control;
1636 __le16 radio_on;
1637 } __attribute__((packed));
1638
1639 static int
1640 mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1641 {
1642 struct mwl8k_priv *priv = hw->priv;
1643 struct mwl8k_cmd_802_11_radio_control *cmd;
1644 int rc;
1645
1646 if (enable == priv->radio_on && !force)
1647 return 0;
1648
1649 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1650 if (cmd == NULL)
1651 return -ENOMEM;
1652
1653 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1654 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1655 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1656 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1657 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1658
1659 rc = mwl8k_post_cmd(hw, &cmd->header);
1660 kfree(cmd);
1661
1662 if (!rc)
1663 priv->radio_on = enable;
1664
1665 return rc;
1666 }
1667
1668 static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1669 {
1670 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1671 }
1672
1673 static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1674 {
1675 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1676 }
1677
1678 static int
1679 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1680 {
1681 struct mwl8k_priv *priv;
1682
1683 if (hw == NULL || hw->priv == NULL)
1684 return -EINVAL;
1685 priv = hw->priv;
1686
1687 priv->radio_short_preamble = short_preamble;
1688
1689 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
1690 }
1691
1692 /*
1693 * CMD_802_11_RF_TX_POWER.
1694 */
1695 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1696
1697 struct mwl8k_cmd_802_11_rf_tx_power {
1698 struct mwl8k_cmd_pkt header;
1699 __le16 action;
1700 __le16 support_level;
1701 __le16 current_level;
1702 __le16 reserved;
1703 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1704 } __attribute__((packed));
1705
1706 static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1707 {
1708 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1709 int rc;
1710
1711 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1712 if (cmd == NULL)
1713 return -ENOMEM;
1714
1715 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1716 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1717 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1718 cmd->support_level = cpu_to_le16(dBm);
1719
1720 rc = mwl8k_post_cmd(hw, &cmd->header);
1721 kfree(cmd);
1722
1723 return rc;
1724 }
1725
1726 /*
1727 * CMD_SET_PRE_SCAN.
1728 */
1729 struct mwl8k_cmd_set_pre_scan {
1730 struct mwl8k_cmd_pkt header;
1731 } __attribute__((packed));
1732
1733 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1734 {
1735 struct mwl8k_cmd_set_pre_scan *cmd;
1736 int rc;
1737
1738 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1739 if (cmd == NULL)
1740 return -ENOMEM;
1741
1742 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1743 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1744
1745 rc = mwl8k_post_cmd(hw, &cmd->header);
1746 kfree(cmd);
1747
1748 return rc;
1749 }
1750
1751 /*
1752 * CMD_SET_POST_SCAN.
1753 */
1754 struct mwl8k_cmd_set_post_scan {
1755 struct mwl8k_cmd_pkt header;
1756 __le32 isibss;
1757 __u8 bssid[ETH_ALEN];
1758 } __attribute__((packed));
1759
1760 static int
1761 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
1762 {
1763 struct mwl8k_cmd_set_post_scan *cmd;
1764 int rc;
1765
1766 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1767 if (cmd == NULL)
1768 return -ENOMEM;
1769
1770 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1771 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1772 cmd->isibss = 0;
1773 memcpy(cmd->bssid, mac, ETH_ALEN);
1774
1775 rc = mwl8k_post_cmd(hw, &cmd->header);
1776 kfree(cmd);
1777
1778 return rc;
1779 }
1780
1781 /*
1782 * CMD_SET_RF_CHANNEL.
1783 */
1784 struct mwl8k_cmd_set_rf_channel {
1785 struct mwl8k_cmd_pkt header;
1786 __le16 action;
1787 __u8 current_channel;
1788 __le32 channel_flags;
1789 } __attribute__((packed));
1790
1791 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1792 struct ieee80211_channel *channel)
1793 {
1794 struct mwl8k_cmd_set_rf_channel *cmd;
1795 int rc;
1796
1797 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1798 if (cmd == NULL)
1799 return -ENOMEM;
1800
1801 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1802 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1803 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1804 cmd->current_channel = channel->hw_value;
1805 if (channel->band == IEEE80211_BAND_2GHZ)
1806 cmd->channel_flags = cpu_to_le32(0x00000081);
1807 else
1808 cmd->channel_flags = cpu_to_le32(0x00000000);
1809
1810 rc = mwl8k_post_cmd(hw, &cmd->header);
1811 kfree(cmd);
1812
1813 return rc;
1814 }
1815
1816 /*
1817 * CMD_SET_SLOT.
1818 */
1819 struct mwl8k_cmd_set_slot {
1820 struct mwl8k_cmd_pkt header;
1821 __le16 action;
1822 __u8 short_slot;
1823 } __attribute__((packed));
1824
1825 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
1826 {
1827 struct mwl8k_cmd_set_slot *cmd;
1828 int rc;
1829
1830 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1831 if (cmd == NULL)
1832 return -ENOMEM;
1833
1834 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1835 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1836 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1837 cmd->short_slot = short_slot_time;
1838
1839 rc = mwl8k_post_cmd(hw, &cmd->header);
1840 kfree(cmd);
1841
1842 return rc;
1843 }
1844
1845 /*
1846 * CMD_MIMO_CONFIG.
1847 */
1848 struct mwl8k_cmd_mimo_config {
1849 struct mwl8k_cmd_pkt header;
1850 __le32 action;
1851 __u8 rx_antenna_map;
1852 __u8 tx_antenna_map;
1853 } __attribute__((packed));
1854
1855 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1856 {
1857 struct mwl8k_cmd_mimo_config *cmd;
1858 int rc;
1859
1860 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1861 if (cmd == NULL)
1862 return -ENOMEM;
1863
1864 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1865 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1866 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1867 cmd->rx_antenna_map = rx;
1868 cmd->tx_antenna_map = tx;
1869
1870 rc = mwl8k_post_cmd(hw, &cmd->header);
1871 kfree(cmd);
1872
1873 return rc;
1874 }
1875
1876 /*
1877 * CMD_ENABLE_SNIFFER.
1878 */
1879 struct mwl8k_cmd_enable_sniffer {
1880 struct mwl8k_cmd_pkt header;
1881 __le32 action;
1882 } __attribute__((packed));
1883
1884 static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1885 {
1886 struct mwl8k_cmd_enable_sniffer *cmd;
1887 int rc;
1888
1889 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1890 if (cmd == NULL)
1891 return -ENOMEM;
1892
1893 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1894 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1895 cmd->action = cpu_to_le32(!!enable);
1896
1897 rc = mwl8k_post_cmd(hw, &cmd->header);
1898 kfree(cmd);
1899
1900 return rc;
1901 }
1902
1903 /*
1904 * CMD_SET_RATEADAPT_MODE.
1905 */
1906 struct mwl8k_cmd_set_rate_adapt_mode {
1907 struct mwl8k_cmd_pkt header;
1908 __le16 action;
1909 __le16 mode;
1910 } __attribute__((packed));
1911
1912 static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1913 {
1914 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1915 int rc;
1916
1917 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1918 if (cmd == NULL)
1919 return -ENOMEM;
1920
1921 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1922 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1923 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1924 cmd->mode = cpu_to_le16(mode);
1925
1926 rc = mwl8k_post_cmd(hw, &cmd->header);
1927 kfree(cmd);
1928
1929 return rc;
1930 }
1931
1932 /*
1933 * CMD_SET_WMM_MODE.
1934 */
1935 struct mwl8k_cmd_set_wmm {
1936 struct mwl8k_cmd_pkt header;
1937 __le16 action;
1938 } __attribute__((packed));
1939
1940 static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
1941 {
1942 struct mwl8k_priv *priv = hw->priv;
1943 struct mwl8k_cmd_set_wmm *cmd;
1944 int rc;
1945
1946 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1947 if (cmd == NULL)
1948 return -ENOMEM;
1949
1950 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
1951 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1952 cmd->action = cpu_to_le16(!!enable);
1953
1954 rc = mwl8k_post_cmd(hw, &cmd->header);
1955 kfree(cmd);
1956
1957 if (!rc)
1958 priv->wmm_enabled = enable;
1959
1960 return rc;
1961 }
1962
1963 /*
1964 * CMD_SET_RTS_THRESHOLD.
1965 */
1966 struct mwl8k_cmd_rts_threshold {
1967 struct mwl8k_cmd_pkt header;
1968 __le16 action;
1969 __le16 threshold;
1970 } __attribute__((packed));
1971
1972 static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
1973 u16 action, u16 threshold)
1974 {
1975 struct mwl8k_cmd_rts_threshold *cmd;
1976 int rc;
1977
1978 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1979 if (cmd == NULL)
1980 return -ENOMEM;
1981
1982 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
1983 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1984 cmd->action = cpu_to_le16(action);
1985 cmd->threshold = cpu_to_le16(threshold);
1986
1987 rc = mwl8k_post_cmd(hw, &cmd->header);
1988 kfree(cmd);
1989
1990 return rc;
1991 }
1992
1993 /*
1994 * CMD_SET_EDCA_PARAMS.
1995 */
1996 struct mwl8k_cmd_set_edca_params {
1997 struct mwl8k_cmd_pkt header;
1998
1999 /* See MWL8K_SET_EDCA_XXX below */
2000 __le16 action;
2001
2002 /* TX opportunity in units of 32 us */
2003 __le16 txop;
2004
2005 /* Log exponent of max contention period: 0...15*/
2006 __u8 log_cw_max;
2007
2008 /* Log exponent of min contention period: 0...15 */
2009 __u8 log_cw_min;
2010
2011 /* Adaptive interframe spacing in units of 32us */
2012 __u8 aifs;
2013
2014 /* TX queue to configure */
2015 __u8 txq;
2016 } __attribute__((packed));
2017
2018 #define MWL8K_SET_EDCA_CW 0x01
2019 #define MWL8K_SET_EDCA_TXOP 0x02
2020 #define MWL8K_SET_EDCA_AIFS 0x04
2021
2022 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2023 MWL8K_SET_EDCA_TXOP | \
2024 MWL8K_SET_EDCA_AIFS)
2025
2026 static int
2027 mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2028 __u16 cw_min, __u16 cw_max,
2029 __u8 aifs, __u16 txop)
2030 {
2031 struct mwl8k_cmd_set_edca_params *cmd;
2032 int rc;
2033
2034 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2035 if (cmd == NULL)
2036 return -ENOMEM;
2037
2038 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2039 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2040 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2041 cmd->txop = cpu_to_le16(txop);
2042 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2043 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
2044 cmd->aifs = aifs;
2045 cmd->txq = qnum;
2046
2047 rc = mwl8k_post_cmd(hw, &cmd->header);
2048 kfree(cmd);
2049
2050 return rc;
2051 }
2052
2053 /*
2054 * CMD_FINALIZE_JOIN.
2055 */
2056
2057 /* FJ beacon buffer size is compiled into the firmware. */
2058 #define MWL8K_FJ_BEACON_MAXLEN 128
2059
2060 struct mwl8k_cmd_finalize_join {
2061 struct mwl8k_cmd_pkt header;
2062 __le32 sleep_interval; /* Number of beacon periods to sleep */
2063 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2064 } __attribute__((packed));
2065
2066 static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2067 __u16 framelen, __u16 dtim)
2068 {
2069 struct mwl8k_cmd_finalize_join *cmd;
2070 struct ieee80211_mgmt *payload = frame;
2071 u16 hdrlen;
2072 u32 payload_len;
2073 int rc;
2074
2075 if (frame == NULL)
2076 return -EINVAL;
2077
2078 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2079 if (cmd == NULL)
2080 return -ENOMEM;
2081
2082 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2083 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2084 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2085
2086 hdrlen = ieee80211_hdrlen(payload->frame_control);
2087
2088 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2089
2090 /* XXX TBD Might just have to abort and return an error */
2091 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2092 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2093 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2094 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2095
2096 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2097 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2098
2099 if (payload && payload_len)
2100 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2101
2102 rc = mwl8k_post_cmd(hw, &cmd->header);
2103 kfree(cmd);
2104 return rc;
2105 }
2106
2107 /*
2108 * CMD_UPDATE_STADB.
2109 */
2110 struct mwl8k_cmd_update_sta_db {
2111 struct mwl8k_cmd_pkt header;
2112
2113 /* See STADB_ACTION_TYPE */
2114 __le32 action;
2115
2116 /* Peer MAC address */
2117 __u8 peer_addr[ETH_ALEN];
2118
2119 __le32 reserved;
2120
2121 /* Peer info - valid during add/update. */
2122 struct peer_capability_info peer_info;
2123 } __attribute__((packed));
2124
2125 static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2126 struct ieee80211_vif *vif, __u32 action)
2127 {
2128 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2129 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2130 struct mwl8k_cmd_update_sta_db *cmd;
2131 struct peer_capability_info *peer_info;
2132 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2133 int rc;
2134 __u8 count, *rates;
2135
2136 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2137 if (cmd == NULL)
2138 return -ENOMEM;
2139
2140 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2141 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2142
2143 cmd->action = cpu_to_le32(action);
2144 peer_info = &cmd->peer_info;
2145 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2146
2147 switch (action) {
2148 case MWL8K_STA_DB_ADD_ENTRY:
2149 case MWL8K_STA_DB_MODIFY_ENTRY:
2150 /* Build peer_info block */
2151 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2152 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2153 peer_info->interop = 1;
2154 peer_info->amsdu_enabled = 0;
2155
2156 rates = peer_info->legacy_rates;
2157 for (count = 0; count < mv_vif->legacy_nrates; count++)
2158 rates[count] = bitrates[count].hw_value;
2159
2160 rc = mwl8k_post_cmd(hw, &cmd->header);
2161 if (rc == 0)
2162 mv_vif->peer_id = peer_info->station_id;
2163
2164 break;
2165
2166 case MWL8K_STA_DB_DEL_ENTRY:
2167 case MWL8K_STA_DB_FLUSH:
2168 default:
2169 rc = mwl8k_post_cmd(hw, &cmd->header);
2170 if (rc == 0)
2171 mv_vif->peer_id = 0;
2172 break;
2173 }
2174 kfree(cmd);
2175
2176 return rc;
2177 }
2178
2179 /*
2180 * CMD_SET_AID.
2181 */
2182 #define MWL8K_RATE_INDEX_MAX_ARRAY 14
2183
2184 #define MWL8K_FRAME_PROT_DISABLED 0x00
2185 #define MWL8K_FRAME_PROT_11G 0x07
2186 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2187 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2188
2189 struct mwl8k_cmd_update_set_aid {
2190 struct mwl8k_cmd_pkt header;
2191 __le16 aid;
2192
2193 /* AP's MAC address (BSSID) */
2194 __u8 bssid[ETH_ALEN];
2195 __le16 protection_mode;
2196 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2197 } __attribute__((packed));
2198
2199 static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2200 struct ieee80211_vif *vif)
2201 {
2202 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2203 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2204 struct mwl8k_cmd_update_set_aid *cmd;
2205 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2206 int count;
2207 u16 prot_mode;
2208 int rc;
2209
2210 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2211 if (cmd == NULL)
2212 return -ENOMEM;
2213
2214 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2215 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2216 cmd->aid = cpu_to_le16(info->aid);
2217
2218 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2219
2220 if (info->use_cts_prot) {
2221 prot_mode = MWL8K_FRAME_PROT_11G;
2222 } else {
2223 switch (info->ht_operation_mode &
2224 IEEE80211_HT_OP_MODE_PROTECTION) {
2225 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2226 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2227 break;
2228 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2229 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2230 break;
2231 default:
2232 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2233 break;
2234 }
2235 }
2236 cmd->protection_mode = cpu_to_le16(prot_mode);
2237
2238 for (count = 0; count < mv_vif->legacy_nrates; count++)
2239 cmd->supp_rates[count] = bitrates[count].hw_value;
2240
2241 rc = mwl8k_post_cmd(hw, &cmd->header);
2242 kfree(cmd);
2243
2244 return rc;
2245 }
2246
2247 /*
2248 * CMD_SET_RATE.
2249 */
2250 struct mwl8k_cmd_update_rateset {
2251 struct mwl8k_cmd_pkt header;
2252 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2253
2254 /* Bitmap for supported MCS codes. */
2255 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2256 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2257 } __attribute__((packed));
2258
2259 static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2260 struct ieee80211_vif *vif)
2261 {
2262 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2263 struct mwl8k_cmd_update_rateset *cmd;
2264 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2265 int count;
2266 int rc;
2267
2268 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2269 if (cmd == NULL)
2270 return -ENOMEM;
2271
2272 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2273 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2274
2275 for (count = 0; count < mv_vif->legacy_nrates; count++)
2276 cmd->legacy_rates[count] = bitrates[count].hw_value;
2277
2278 rc = mwl8k_post_cmd(hw, &cmd->header);
2279 kfree(cmd);
2280
2281 return rc;
2282 }
2283
2284 /*
2285 * CMD_USE_FIXED_RATE.
2286 */
2287 #define MWL8K_RATE_TABLE_SIZE 8
2288 #define MWL8K_UCAST_RATE 0
2289 #define MWL8K_USE_AUTO_RATE 0x0002
2290
2291 struct mwl8k_rate_entry {
2292 /* Set to 1 if HT rate, 0 if legacy. */
2293 __le32 is_ht_rate;
2294
2295 /* Set to 1 to use retry_count field. */
2296 __le32 enable_retry;
2297
2298 /* Specified legacy rate or MCS. */
2299 __le32 rate;
2300
2301 /* Number of allowed retries. */
2302 __le32 retry_count;
2303 } __attribute__((packed));
2304
2305 struct mwl8k_rate_table {
2306 /* 1 to allow specified rate and below */
2307 __le32 allow_rate_drop;
2308 __le32 num_rates;
2309 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2310 } __attribute__((packed));
2311
2312 struct mwl8k_cmd_use_fixed_rate {
2313 struct mwl8k_cmd_pkt header;
2314 __le32 action;
2315 struct mwl8k_rate_table rate_table;
2316
2317 /* Unicast, Broadcast or Multicast */
2318 __le32 rate_type;
2319 __le32 reserved1;
2320 __le32 reserved2;
2321 } __attribute__((packed));
2322
2323 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2324 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2325 {
2326 struct mwl8k_cmd_use_fixed_rate *cmd;
2327 int count;
2328 int rc;
2329
2330 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2331 if (cmd == NULL)
2332 return -ENOMEM;
2333
2334 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2335 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2336
2337 cmd->action = cpu_to_le32(action);
2338 cmd->rate_type = cpu_to_le32(rate_type);
2339
2340 if (rate_table != NULL) {
2341 /*
2342 * Copy over each field manually so that endian
2343 * conversion can be done.
2344 */
2345 cmd->rate_table.allow_rate_drop =
2346 cpu_to_le32(rate_table->allow_rate_drop);
2347 cmd->rate_table.num_rates =
2348 cpu_to_le32(rate_table->num_rates);
2349
2350 for (count = 0; count < rate_table->num_rates; count++) {
2351 struct mwl8k_rate_entry *dst =
2352 &cmd->rate_table.rate_entry[count];
2353 struct mwl8k_rate_entry *src =
2354 &rate_table->rate_entry[count];
2355
2356 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2357 dst->enable_retry = cpu_to_le32(src->enable_retry);
2358 dst->rate = cpu_to_le32(src->rate);
2359 dst->retry_count = cpu_to_le32(src->retry_count);
2360 }
2361 }
2362
2363 rc = mwl8k_post_cmd(hw, &cmd->header);
2364 kfree(cmd);
2365
2366 return rc;
2367 }
2368
2369
2370 /*
2371 * Interrupt handling.
2372 */
2373 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2374 {
2375 struct ieee80211_hw *hw = dev_id;
2376 struct mwl8k_priv *priv = hw->priv;
2377 u32 status;
2378
2379 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2380 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2381
2382 if (!status)
2383 return IRQ_NONE;
2384
2385 if (status & MWL8K_A2H_INT_TX_DONE)
2386 tasklet_schedule(&priv->tx_reclaim_task);
2387
2388 if (status & MWL8K_A2H_INT_RX_READY) {
2389 while (rxq_process(hw, 0, 1))
2390 rxq_refill(hw, 0, 1);
2391 }
2392
2393 if (status & MWL8K_A2H_INT_OPC_DONE) {
2394 if (priv->hostcmd_wait != NULL)
2395 complete(priv->hostcmd_wait);
2396 }
2397
2398 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2399 if (!mutex_is_locked(&priv->fw_mutex) &&
2400 priv->radio_on && mwl8k_txq_busy(priv))
2401 mwl8k_tx_start(priv);
2402 }
2403
2404 return IRQ_HANDLED;
2405 }
2406
2407
2408 /*
2409 * Core driver operations.
2410 */
2411 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2412 {
2413 struct mwl8k_priv *priv = hw->priv;
2414 int index = skb_get_queue_mapping(skb);
2415 int rc;
2416
2417 if (priv->current_channel == NULL) {
2418 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2419 "disabled\n", wiphy_name(hw->wiphy));
2420 dev_kfree_skb(skb);
2421 return NETDEV_TX_OK;
2422 }
2423
2424 rc = mwl8k_txq_xmit(hw, index, skb);
2425
2426 return rc;
2427 }
2428
2429 static int mwl8k_start(struct ieee80211_hw *hw)
2430 {
2431 struct mwl8k_priv *priv = hw->priv;
2432 int rc;
2433
2434 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2435 IRQF_SHARED, MWL8K_NAME, hw);
2436 if (rc) {
2437 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2438 wiphy_name(hw->wiphy));
2439 return -EIO;
2440 }
2441
2442 /* Enable tx reclaim tasklet */
2443 tasklet_enable(&priv->tx_reclaim_task);
2444
2445 /* Enable interrupts */
2446 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2447
2448 rc = mwl8k_fw_lock(hw);
2449 if (!rc) {
2450 rc = mwl8k_cmd_802_11_radio_enable(hw);
2451
2452 if (!rc)
2453 rc = mwl8k_cmd_set_pre_scan(hw);
2454
2455 if (!rc)
2456 rc = mwl8k_cmd_set_post_scan(hw,
2457 "\x00\x00\x00\x00\x00\x00");
2458
2459 if (!rc)
2460 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
2461
2462 if (!rc)
2463 rc = mwl8k_set_wmm(hw, 0);
2464
2465 if (!rc)
2466 rc = mwl8k_enable_sniffer(hw, 0);
2467
2468 mwl8k_fw_unlock(hw);
2469 }
2470
2471 if (rc) {
2472 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2473 free_irq(priv->pdev->irq, hw);
2474 tasklet_disable(&priv->tx_reclaim_task);
2475 }
2476
2477 return rc;
2478 }
2479
2480 static void mwl8k_stop(struct ieee80211_hw *hw)
2481 {
2482 struct mwl8k_priv *priv = hw->priv;
2483 int i;
2484
2485 mwl8k_cmd_802_11_radio_disable(hw);
2486
2487 ieee80211_stop_queues(hw);
2488
2489 /* Disable interrupts */
2490 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2491 free_irq(priv->pdev->irq, hw);
2492
2493 /* Stop finalize join worker */
2494 cancel_work_sync(&priv->finalize_join_worker);
2495 if (priv->beacon_skb != NULL)
2496 dev_kfree_skb(priv->beacon_skb);
2497
2498 /* Stop tx reclaim tasklet */
2499 tasklet_disable(&priv->tx_reclaim_task);
2500
2501 /* Stop config thread */
2502 flush_workqueue(priv->config_wq);
2503
2504 /* Return all skbs to mac80211 */
2505 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2506 mwl8k_txq_reclaim(hw, i, 1);
2507 }
2508
2509 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2510 struct ieee80211_if_init_conf *conf)
2511 {
2512 struct mwl8k_priv *priv = hw->priv;
2513 struct mwl8k_vif *mwl8k_vif;
2514
2515 /*
2516 * We only support one active interface at a time.
2517 */
2518 if (priv->vif != NULL)
2519 return -EBUSY;
2520
2521 /*
2522 * We only support managed interfaces for now.
2523 */
2524 if (conf->type != NL80211_IFTYPE_STATION)
2525 return -EINVAL;
2526
2527 /* Clean out driver private area */
2528 mwl8k_vif = MWL8K_VIF(conf->vif);
2529 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2530
2531 /* Save the mac address */
2532 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2533
2534 /* Back pointer to parent config block */
2535 mwl8k_vif->priv = priv;
2536
2537 /* Setup initial PHY parameters */
2538 memcpy(mwl8k_vif->legacy_rates,
2539 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2540 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2541
2542 /* Set Initial sequence number to zero */
2543 mwl8k_vif->seqno = 0;
2544
2545 priv->vif = conf->vif;
2546 priv->current_channel = NULL;
2547
2548 return 0;
2549 }
2550
2551 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2552 struct ieee80211_if_init_conf *conf)
2553 {
2554 struct mwl8k_priv *priv = hw->priv;
2555
2556 if (priv->vif == NULL)
2557 return;
2558
2559 priv->vif = NULL;
2560 }
2561
2562 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2563 {
2564 struct ieee80211_conf *conf = &hw->conf;
2565 struct mwl8k_priv *priv = hw->priv;
2566 int rc;
2567
2568 if (conf->flags & IEEE80211_CONF_IDLE) {
2569 mwl8k_cmd_802_11_radio_disable(hw);
2570 priv->current_channel = NULL;
2571 return 0;
2572 }
2573
2574 rc = mwl8k_fw_lock(hw);
2575 if (rc)
2576 return rc;
2577
2578 rc = mwl8k_cmd_802_11_radio_enable(hw);
2579 if (rc)
2580 goto out;
2581
2582 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2583 if (rc)
2584 goto out;
2585
2586 priv->current_channel = conf->channel;
2587
2588 if (conf->power_level > 18)
2589 conf->power_level = 18;
2590 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2591 if (rc)
2592 goto out;
2593
2594 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2595 rc = -EINVAL;
2596
2597 out:
2598 mwl8k_fw_unlock(hw);
2599
2600 return rc;
2601 }
2602
2603 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2604 struct ieee80211_vif *vif,
2605 struct ieee80211_bss_conf *info,
2606 u32 changed)
2607 {
2608 struct mwl8k_priv *priv = hw->priv;
2609 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2610 int rc;
2611
2612 if (changed & BSS_CHANGED_BSSID)
2613 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2614
2615 if ((changed & BSS_CHANGED_ASSOC) == 0)
2616 return;
2617
2618 priv->capture_beacon = false;
2619
2620 rc = mwl8k_fw_lock(hw);
2621 if (rc)
2622 return;
2623
2624 if (info->assoc) {
2625 memcpy(&mwl8k_vif->bss_info, info,
2626 sizeof(struct ieee80211_bss_conf));
2627
2628 /* Install rates */
2629 rc = mwl8k_update_rateset(hw, vif);
2630 if (rc)
2631 goto out;
2632
2633 /* Turn on rate adaptation */
2634 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2635 MWL8K_UCAST_RATE, NULL);
2636 if (rc)
2637 goto out;
2638
2639 /* Set radio preamble */
2640 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2641 if (rc)
2642 goto out;
2643
2644 /* Set slot time */
2645 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2646 if (rc)
2647 goto out;
2648
2649 /* Update peer rate info */
2650 rc = mwl8k_cmd_update_sta_db(hw, vif,
2651 MWL8K_STA_DB_MODIFY_ENTRY);
2652 if (rc)
2653 goto out;
2654
2655 /* Set AID */
2656 rc = mwl8k_cmd_set_aid(hw, vif);
2657 if (rc)
2658 goto out;
2659
2660 /*
2661 * Finalize the join. Tell rx handler to process
2662 * next beacon from our BSSID.
2663 */
2664 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
2665 priv->capture_beacon = true;
2666 } else {
2667 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
2668 memset(&mwl8k_vif->bss_info, 0,
2669 sizeof(struct ieee80211_bss_conf));
2670 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
2671 }
2672
2673 out:
2674 mwl8k_fw_unlock(hw);
2675 }
2676
2677 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2678 int mc_count, struct dev_addr_list *mclist)
2679 {
2680 struct mwl8k_cmd_pkt *cmd;
2681
2682 cmd = __mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
2683
2684 return (unsigned long)cmd;
2685 }
2686
2687 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2688 unsigned int changed_flags,
2689 unsigned int *total_flags,
2690 u64 multicast)
2691 {
2692 struct mwl8k_priv *priv = hw->priv;
2693 struct mwl8k_cmd_pkt *multicast_adr_cmd;
2694
2695 /* Clear unsupported feature flags */
2696 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
2697
2698 if (mwl8k_fw_lock(hw))
2699 return;
2700
2701 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2702 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2703 mwl8k_cmd_set_pre_scan(hw);
2704 else {
2705 u8 *bssid;
2706
2707 bssid = "\x00\x00\x00\x00\x00\x00";
2708 if (priv->vif != NULL)
2709 bssid = MWL8K_VIF(priv->vif)->bssid;
2710
2711 mwl8k_cmd_set_post_scan(hw, bssid);
2712 }
2713 }
2714
2715 multicast_adr_cmd = (void *)(unsigned long)multicast;
2716 if (multicast_adr_cmd != NULL) {
2717 mwl8k_post_cmd(hw, multicast_adr_cmd);
2718 kfree(multicast_adr_cmd);
2719 }
2720
2721 mwl8k_fw_unlock(hw);
2722 }
2723
2724 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2725 {
2726 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
2727 }
2728
2729 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2730 const struct ieee80211_tx_queue_params *params)
2731 {
2732 struct mwl8k_priv *priv = hw->priv;
2733 int rc;
2734
2735 rc = mwl8k_fw_lock(hw);
2736 if (!rc) {
2737 if (!priv->wmm_enabled)
2738 rc = mwl8k_set_wmm(hw, 1);
2739
2740 if (!rc)
2741 rc = mwl8k_set_edca_params(hw, queue,
2742 params->cw_min,
2743 params->cw_max,
2744 params->aifs,
2745 params->txop);
2746
2747 mwl8k_fw_unlock(hw);
2748 }
2749
2750 return rc;
2751 }
2752
2753 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2754 struct ieee80211_tx_queue_stats *stats)
2755 {
2756 struct mwl8k_priv *priv = hw->priv;
2757 struct mwl8k_tx_queue *txq;
2758 int index;
2759
2760 spin_lock_bh(&priv->tx_lock);
2761 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2762 txq = priv->txq + index;
2763 memcpy(&stats[index], &txq->tx_stats,
2764 sizeof(struct ieee80211_tx_queue_stats));
2765 }
2766 spin_unlock_bh(&priv->tx_lock);
2767
2768 return 0;
2769 }
2770
2771 static int mwl8k_get_stats(struct ieee80211_hw *hw,
2772 struct ieee80211_low_level_stats *stats)
2773 {
2774 return mwl8k_cmd_802_11_get_stat(hw, stats);
2775 }
2776
2777 static const struct ieee80211_ops mwl8k_ops = {
2778 .tx = mwl8k_tx,
2779 .start = mwl8k_start,
2780 .stop = mwl8k_stop,
2781 .add_interface = mwl8k_add_interface,
2782 .remove_interface = mwl8k_remove_interface,
2783 .config = mwl8k_config,
2784 .bss_info_changed = mwl8k_bss_info_changed,
2785 .prepare_multicast = mwl8k_prepare_multicast,
2786 .configure_filter = mwl8k_configure_filter,
2787 .set_rts_threshold = mwl8k_set_rts_threshold,
2788 .conf_tx = mwl8k_conf_tx,
2789 .get_tx_stats = mwl8k_get_tx_stats,
2790 .get_stats = mwl8k_get_stats,
2791 };
2792
2793 static void mwl8k_tx_reclaim_handler(unsigned long data)
2794 {
2795 int i;
2796 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2797 struct mwl8k_priv *priv = hw->priv;
2798
2799 spin_lock_bh(&priv->tx_lock);
2800 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2801 mwl8k_txq_reclaim(hw, i, 0);
2802
2803 if (priv->tx_wait != NULL && mwl8k_txq_busy(priv) == 0) {
2804 complete(priv->tx_wait);
2805 priv->tx_wait = NULL;
2806 }
2807 spin_unlock_bh(&priv->tx_lock);
2808 }
2809
2810 static void mwl8k_finalize_join_worker(struct work_struct *work)
2811 {
2812 struct mwl8k_priv *priv =
2813 container_of(work, struct mwl8k_priv, finalize_join_worker);
2814 struct sk_buff *skb = priv->beacon_skb;
2815 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
2816
2817 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
2818 dev_kfree_skb(skb);
2819
2820 priv->beacon_skb = NULL;
2821 }
2822
2823 static int __devinit mwl8k_probe(struct pci_dev *pdev,
2824 const struct pci_device_id *id)
2825 {
2826 static int printed_version = 0;
2827 struct ieee80211_hw *hw;
2828 struct mwl8k_priv *priv;
2829 int rc;
2830 int i;
2831
2832 if (!printed_version) {
2833 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
2834 printed_version = 1;
2835 }
2836
2837 rc = pci_enable_device(pdev);
2838 if (rc) {
2839 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
2840 MWL8K_NAME);
2841 return rc;
2842 }
2843
2844 rc = pci_request_regions(pdev, MWL8K_NAME);
2845 if (rc) {
2846 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
2847 MWL8K_NAME);
2848 return rc;
2849 }
2850
2851 pci_set_master(pdev);
2852
2853 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
2854 if (hw == NULL) {
2855 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
2856 rc = -ENOMEM;
2857 goto err_free_reg;
2858 }
2859
2860 priv = hw->priv;
2861 priv->hw = hw;
2862 priv->pdev = pdev;
2863 priv->wmm_enabled = false;
2864 priv->pending_tx_pkts = 0;
2865
2866 SET_IEEE80211_DEV(hw, &pdev->dev);
2867 pci_set_drvdata(pdev, hw);
2868
2869 priv->regs = pci_iomap(pdev, 1, 0x10000);
2870 if (priv->regs == NULL) {
2871 printk(KERN_ERR "%s: Cannot map device memory\n",
2872 wiphy_name(hw->wiphy));
2873 goto err_iounmap;
2874 }
2875
2876 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
2877 priv->band.band = IEEE80211_BAND_2GHZ;
2878 priv->band.channels = priv->channels;
2879 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
2880 priv->band.bitrates = priv->rates;
2881 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
2882 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
2883
2884 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
2885 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
2886
2887 /*
2888 * Extra headroom is the size of the required DMA header
2889 * minus the size of the smallest 802.11 frame (CTS frame).
2890 */
2891 hw->extra_tx_headroom =
2892 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
2893
2894 hw->channel_change_time = 10;
2895
2896 hw->queues = MWL8K_TX_QUEUES;
2897
2898 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
2899
2900 /* Set rssi and noise values to dBm */
2901 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
2902 hw->vif_data_size = sizeof(struct mwl8k_vif);
2903 priv->vif = NULL;
2904
2905 /* Set default radio state and preamble */
2906 priv->radio_on = 0;
2907 priv->radio_short_preamble = 0;
2908
2909 /* Finalize join worker */
2910 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
2911
2912 /* TX reclaim tasklet */
2913 tasklet_init(&priv->tx_reclaim_task,
2914 mwl8k_tx_reclaim_handler, (unsigned long)hw);
2915 tasklet_disable(&priv->tx_reclaim_task);
2916
2917 /* Config workthread */
2918 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
2919 if (priv->config_wq == NULL)
2920 goto err_iounmap;
2921
2922 /* Power management cookie */
2923 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
2924 if (priv->cookie == NULL)
2925 goto err_iounmap;
2926
2927 rc = mwl8k_rxq_init(hw, 0);
2928 if (rc)
2929 goto err_iounmap;
2930 rxq_refill(hw, 0, INT_MAX);
2931
2932 mutex_init(&priv->fw_mutex);
2933 priv->fw_mutex_owner = NULL;
2934 priv->fw_mutex_depth = 0;
2935 priv->tx_wait = NULL;
2936 priv->hostcmd_wait = NULL;
2937
2938 spin_lock_init(&priv->tx_lock);
2939
2940 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
2941 rc = mwl8k_txq_init(hw, i);
2942 if (rc)
2943 goto err_free_queues;
2944 }
2945
2946 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2947 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2948 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
2949 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
2950
2951 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2952 IRQF_SHARED, MWL8K_NAME, hw);
2953 if (rc) {
2954 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2955 wiphy_name(hw->wiphy));
2956 goto err_free_queues;
2957 }
2958
2959 /* Reset firmware and hardware */
2960 mwl8k_hw_reset(priv);
2961
2962 /* Ask userland hotplug daemon for the device firmware */
2963 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
2964 if (rc) {
2965 printk(KERN_ERR "%s: Firmware files not found\n",
2966 wiphy_name(hw->wiphy));
2967 goto err_free_irq;
2968 }
2969
2970 /* Load firmware into hardware */
2971 rc = mwl8k_load_firmware(hw);
2972 if (rc) {
2973 printk(KERN_ERR "%s: Cannot start firmware\n",
2974 wiphy_name(hw->wiphy));
2975 goto err_stop_firmware;
2976 }
2977
2978 /* Reclaim memory once firmware is successfully loaded */
2979 mwl8k_release_firmware(priv);
2980
2981 /*
2982 * Temporarily enable interrupts. Initial firmware host
2983 * commands use interrupts and avoids polling. Disable
2984 * interrupts when done.
2985 */
2986 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2987
2988 /* Get config data, mac addrs etc */
2989 rc = mwl8k_cmd_get_hw_spec(hw);
2990 if (rc) {
2991 printk(KERN_ERR "%s: Cannot initialise firmware\n",
2992 wiphy_name(hw->wiphy));
2993 goto err_stop_firmware;
2994 }
2995
2996 /* Turn radio off */
2997 rc = mwl8k_cmd_802_11_radio_disable(hw);
2998 if (rc) {
2999 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3000 goto err_stop_firmware;
3001 }
3002
3003 /* Disable interrupts */
3004 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3005 free_irq(priv->pdev->irq, hw);
3006
3007 rc = ieee80211_register_hw(hw);
3008 if (rc) {
3009 printk(KERN_ERR "%s: Cannot register device\n",
3010 wiphy_name(hw->wiphy));
3011 goto err_stop_firmware;
3012 }
3013
3014 printk(KERN_INFO "%s: 88w%u v%d, %pM, firmware version %u.%u.%u.%u\n",
3015 wiphy_name(hw->wiphy), priv->part_num, priv->hw_rev,
3016 hw->wiphy->perm_addr,
3017 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3018 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3019
3020 return 0;
3021
3022 err_stop_firmware:
3023 mwl8k_hw_reset(priv);
3024 mwl8k_release_firmware(priv);
3025
3026 err_free_irq:
3027 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3028 free_irq(priv->pdev->irq, hw);
3029
3030 err_free_queues:
3031 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3032 mwl8k_txq_deinit(hw, i);
3033 mwl8k_rxq_deinit(hw, 0);
3034
3035 err_iounmap:
3036 if (priv->cookie != NULL)
3037 pci_free_consistent(priv->pdev, 4,
3038 priv->cookie, priv->cookie_dma);
3039
3040 if (priv->regs != NULL)
3041 pci_iounmap(pdev, priv->regs);
3042
3043 if (priv->config_wq != NULL)
3044 destroy_workqueue(priv->config_wq);
3045
3046 pci_set_drvdata(pdev, NULL);
3047 ieee80211_free_hw(hw);
3048
3049 err_free_reg:
3050 pci_release_regions(pdev);
3051 pci_disable_device(pdev);
3052
3053 return rc;
3054 }
3055
3056 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3057 {
3058 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3059 }
3060
3061 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3062 {
3063 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3064 struct mwl8k_priv *priv;
3065 int i;
3066
3067 if (hw == NULL)
3068 return;
3069 priv = hw->priv;
3070
3071 ieee80211_stop_queues(hw);
3072
3073 ieee80211_unregister_hw(hw);
3074
3075 /* Remove tx reclaim tasklet */
3076 tasklet_kill(&priv->tx_reclaim_task);
3077
3078 /* Stop config thread */
3079 destroy_workqueue(priv->config_wq);
3080
3081 /* Stop hardware */
3082 mwl8k_hw_reset(priv);
3083
3084 /* Return all skbs to mac80211 */
3085 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3086 mwl8k_txq_reclaim(hw, i, 1);
3087
3088 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3089 mwl8k_txq_deinit(hw, i);
3090
3091 mwl8k_rxq_deinit(hw, 0);
3092
3093 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3094
3095 pci_iounmap(pdev, priv->regs);
3096 pci_set_drvdata(pdev, NULL);
3097 ieee80211_free_hw(hw);
3098 pci_release_regions(pdev);
3099 pci_disable_device(pdev);
3100 }
3101
3102 static struct pci_driver mwl8k_driver = {
3103 .name = MWL8K_NAME,
3104 .id_table = mwl8k_table,
3105 .probe = mwl8k_probe,
3106 .remove = __devexit_p(mwl8k_remove),
3107 .shutdown = __devexit_p(mwl8k_shutdown),
3108 };
3109
3110 static int __init mwl8k_init(void)
3111 {
3112 return pci_register_driver(&mwl8k_driver);
3113 }
3114
3115 static void __exit mwl8k_exit(void)
3116 {
3117 pci_unregister_driver(&mwl8k_driver);
3118 }
3119
3120 module_init(mwl8k_init);
3121 module_exit(mwl8k_exit);
3122
3123 MODULE_DESCRIPTION(MWL8K_DESC);
3124 MODULE_VERSION(MWL8K_VERSION);
3125 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3126 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)