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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / pcie / trans.c
1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
70
71 #include "iwl-drv.h"
72 #include "iwl-trans.h"
73 #include "iwl-csr.h"
74 #include "iwl-prph.h"
75 #include "iwl-agn-hw.h"
76 #include "internal.h"
77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
78 #include "dvm/commands.h"
79
80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie) \
81 (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
82 (~(1<<(trans_pcie)->cmd_queue)))
83
84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
85 {
86 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
87 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
88 struct device *dev = trans->dev;
89
90 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
91
92 spin_lock_init(&rxq->lock);
93
94 if (WARN_ON(rxq->bd || rxq->rb_stts))
95 return -EINVAL;
96
97 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
98 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
99 &rxq->bd_dma, GFP_KERNEL);
100 if (!rxq->bd)
101 goto err_bd;
102
103 /*Allocate the driver's pointer to receive buffer status */
104 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
105 &rxq->rb_stts_dma, GFP_KERNEL);
106 if (!rxq->rb_stts)
107 goto err_rb_stts;
108
109 return 0;
110
111 err_rb_stts:
112 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
113 rxq->bd, rxq->bd_dma);
114 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
115 rxq->bd = NULL;
116 err_bd:
117 return -ENOMEM;
118 }
119
120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
121 {
122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
123 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
124 int i;
125
126 /* Fill the rx_used queue with _all_ of the Rx buffers */
127 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
128 /* In the reset function, these buffers may have been allocated
129 * to an SKB, so we need to unmap and free potential storage */
130 if (rxq->pool[i].page != NULL) {
131 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
132 PAGE_SIZE << trans_pcie->rx_page_order,
133 DMA_FROM_DEVICE);
134 __free_pages(rxq->pool[i].page,
135 trans_pcie->rx_page_order);
136 rxq->pool[i].page = NULL;
137 }
138 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
139 }
140 }
141
142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
143 struct iwl_rx_queue *rxq)
144 {
145 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
146 u32 rb_size;
147 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
148 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
149
150 if (trans_pcie->rx_buf_size_8k)
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
152 else
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
154
155 /* Stop Rx DMA */
156 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157
158 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
160
161 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8));
164
165 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4);
168
169 /* Enable Rx DMA
170 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
171 * the credit mechanism in 5000 HW RX FIFO
172 * Direct rx interrupts to hosts
173 * Rx buffer size 4 or 8k
174 * RB timeout 0x10
175 * 256 RBDs
176 */
177 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
181 rb_size|
182 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
183 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
184
185 /* Set interrupt coalescing timer to default (2048 usecs) */
186 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
187 }
188
189 static int iwl_rx_init(struct iwl_trans *trans)
190 {
191 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
193
194 int i, err;
195 unsigned long flags;
196
197 if (!rxq->bd) {
198 err = iwl_trans_rx_alloc(trans);
199 if (err)
200 return err;
201 }
202
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
206
207 iwl_trans_rxq_free_rx_bufs(trans);
208
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
211
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
216 rxq->free_count = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
218
219 iwlagn_rx_replenish(trans);
220
221 iwl_trans_rx_hw_init(trans, rxq);
222
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
227
228 return 0;
229 }
230
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
232 {
233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
234 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
235 unsigned long flags;
236
237 /*if rxq->bd is NULL, it means that nothing has been allocated,
238 * exit now */
239 if (!rxq->bd) {
240 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
241 return;
242 }
243
244 spin_lock_irqsave(&rxq->lock, flags);
245 iwl_trans_rxq_free_rx_bufs(trans);
246 spin_unlock_irqrestore(&rxq->lock, flags);
247
248 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
249 rxq->bd, rxq->bd_dma);
250 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
251 rxq->bd = NULL;
252
253 if (rxq->rb_stts)
254 dma_free_coherent(trans->dev,
255 sizeof(struct iwl_rb_status),
256 rxq->rb_stts, rxq->rb_stts_dma);
257 else
258 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
259 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
260 rxq->rb_stts = NULL;
261 }
262
263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
264 {
265
266 /* stop Rx DMA */
267 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
268 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
269 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
270 }
271
272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
273 struct iwl_dma_ptr *ptr, size_t size)
274 {
275 if (WARN_ON(ptr->addr))
276 return -EINVAL;
277
278 ptr->addr = dma_alloc_coherent(trans->dev, size,
279 &ptr->dma, GFP_KERNEL);
280 if (!ptr->addr)
281 return -ENOMEM;
282 ptr->size = size;
283 return 0;
284 }
285
286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
287 struct iwl_dma_ptr *ptr)
288 {
289 if (unlikely(!ptr->addr))
290 return;
291
292 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
293 memset(ptr, 0, sizeof(*ptr));
294 }
295
296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
297 {
298 struct iwl_tx_queue *txq = (void *)data;
299 struct iwl_queue *q = &txq->q;
300 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
301 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
302 u32 scd_sram_addr = trans_pcie->scd_base_addr +
303 SCD_TX_STTS_MEM_LOWER_BOUND + (16 * txq->q.id);
304 u8 buf[16];
305 int i;
306
307 spin_lock(&txq->lock);
308 /* check if triggered erroneously */
309 if (txq->q.read_ptr == txq->q.write_ptr) {
310 spin_unlock(&txq->lock);
311 return;
312 }
313 spin_unlock(&txq->lock);
314
315 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
316 jiffies_to_msecs(trans_pcie->wd_timeout));
317 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
318 txq->q.read_ptr, txq->q.write_ptr);
319
320 iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
321
322 iwl_print_hex_error(trans, buf, sizeof(buf));
323
324 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
325 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
326 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
327
328 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
329 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
330 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
331 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
332 u32 tbl_dw =
333 iwl_read_targ_mem(trans,
334 trans_pcie->scd_base_addr +
335 SCD_TRANS_TBL_OFFSET_QUEUE(i));
336
337 if (i & 0x1)
338 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
339 else
340 tbl_dw = tbl_dw & 0x0000FFFF;
341
342 IWL_ERR(trans,
343 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
344 i, active ? "" : "in", fifo, tbl_dw,
345 iwl_read_prph(trans,
346 SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
347 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
348 }
349
350 for (i = q->read_ptr; i != q->write_ptr;
351 i = iwl_queue_inc_wrap(i, q->n_bd)) {
352 struct iwl_tx_cmd *tx_cmd =
353 (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
354 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
355 get_unaligned_le32(&tx_cmd->scratch));
356 }
357
358 iwl_op_mode_nic_error(trans->op_mode);
359 }
360
361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
362 struct iwl_tx_queue *txq, int slots_num,
363 u32 txq_id)
364 {
365 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
366 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
367 int i;
368
369 if (WARN_ON(txq->entries || txq->tfds))
370 return -EINVAL;
371
372 setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
373 (unsigned long)txq);
374 txq->trans_pcie = trans_pcie;
375
376 txq->q.n_window = slots_num;
377
378 txq->entries = kcalloc(slots_num,
379 sizeof(struct iwl_pcie_tx_queue_entry),
380 GFP_KERNEL);
381
382 if (!txq->entries)
383 goto error;
384
385 if (txq_id == trans_pcie->cmd_queue)
386 for (i = 0; i < slots_num; i++) {
387 txq->entries[i].cmd =
388 kmalloc(sizeof(struct iwl_device_cmd),
389 GFP_KERNEL);
390 if (!txq->entries[i].cmd)
391 goto error;
392 }
393
394 /* Circular buffer of transmit frame descriptors (TFDs),
395 * shared with device */
396 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
397 &txq->q.dma_addr, GFP_KERNEL);
398 if (!txq->tfds) {
399 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
400 goto error;
401 }
402 txq->q.id = txq_id;
403
404 return 0;
405 error:
406 if (txq->entries && txq_id == trans_pcie->cmd_queue)
407 for (i = 0; i < slots_num; i++)
408 kfree(txq->entries[i].cmd);
409 kfree(txq->entries);
410 txq->entries = NULL;
411
412 return -ENOMEM;
413
414 }
415
416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
417 int slots_num, u32 txq_id)
418 {
419 int ret;
420
421 txq->need_update = 0;
422
423 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
424 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
425 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
426
427 /* Initialize queue's high/low-water marks, and head/tail indexes */
428 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
429 txq_id);
430 if (ret)
431 return ret;
432
433 spin_lock_init(&txq->lock);
434
435 /*
436 * Tell nic where to find circular buffer of Tx Frame Descriptors for
437 * given Tx queue, and enable the DMA channel used for that queue.
438 * Circular buffer (TFD queue in DRAM) physical base address */
439 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
440 txq->q.dma_addr >> 8);
441
442 return 0;
443 }
444
445 /**
446 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
447 */
448 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
449 {
450 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
451 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
452 struct iwl_queue *q = &txq->q;
453 enum dma_data_direction dma_dir;
454
455 if (!q->n_bd)
456 return;
457
458 /* In the command queue, all the TBs are mapped as BIDI
459 * so unmap them as such.
460 */
461 if (txq_id == trans_pcie->cmd_queue)
462 dma_dir = DMA_BIDIRECTIONAL;
463 else
464 dma_dir = DMA_TO_DEVICE;
465
466 spin_lock_bh(&txq->lock);
467 while (q->write_ptr != q->read_ptr) {
468 iwl_txq_free_tfd(trans, txq, dma_dir);
469 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
470 }
471 spin_unlock_bh(&txq->lock);
472 }
473
474 /**
475 * iwl_tx_queue_free - Deallocate DMA queue.
476 * @txq: Transmit queue to deallocate.
477 *
478 * Empty queue by removing and destroying all BD's.
479 * Free all buffers.
480 * 0-fill, but do not free "txq" descriptor structure.
481 */
482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
483 {
484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
485 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
486 struct device *dev = trans->dev;
487 int i;
488
489 if (WARN_ON(!txq))
490 return;
491
492 iwl_tx_queue_unmap(trans, txq_id);
493
494 /* De-alloc array of command/tx buffers */
495
496 if (txq_id == trans_pcie->cmd_queue)
497 for (i = 0; i < txq->q.n_window; i++)
498 kfree(txq->entries[i].cmd);
499
500 /* De-alloc circular buffer of TFDs */
501 if (txq->q.n_bd) {
502 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
503 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
504 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
505 }
506
507 kfree(txq->entries);
508 txq->entries = NULL;
509
510 del_timer_sync(&txq->stuck_timer);
511
512 /* 0-fill queue descriptor structure */
513 memset(txq, 0, sizeof(*txq));
514 }
515
516 /**
517 * iwl_trans_tx_free - Free TXQ Context
518 *
519 * Destroy all TX DMA queues and structures
520 */
521 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
522 {
523 int txq_id;
524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
525
526 /* Tx queues */
527 if (trans_pcie->txq) {
528 for (txq_id = 0;
529 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
530 iwl_tx_queue_free(trans, txq_id);
531 }
532
533 kfree(trans_pcie->txq);
534 trans_pcie->txq = NULL;
535
536 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
537
538 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
539 }
540
541 /**
542 * iwl_trans_tx_alloc - allocate TX context
543 * Allocate all Tx DMA structures and initialize them
544 *
545 * @param priv
546 * @return error code
547 */
548 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
549 {
550 int ret;
551 int txq_id, slots_num;
552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
553
554 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
555 sizeof(struct iwlagn_scd_bc_tbl);
556
557 /*It is not allowed to alloc twice, so warn when this happens.
558 * We cannot rely on the previous allocation, so free and fail */
559 if (WARN_ON(trans_pcie->txq)) {
560 ret = -EINVAL;
561 goto error;
562 }
563
564 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
565 scd_bc_tbls_size);
566 if (ret) {
567 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
568 goto error;
569 }
570
571 /* Alloc keep-warm buffer */
572 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
573 if (ret) {
574 IWL_ERR(trans, "Keep Warm allocation failed\n");
575 goto error;
576 }
577
578 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
579 sizeof(struct iwl_tx_queue), GFP_KERNEL);
580 if (!trans_pcie->txq) {
581 IWL_ERR(trans, "Not enough memory for txq\n");
582 ret = ENOMEM;
583 goto error;
584 }
585
586 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
587 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
588 txq_id++) {
589 slots_num = (txq_id == trans_pcie->cmd_queue) ?
590 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
591 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
592 slots_num, txq_id);
593 if (ret) {
594 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
595 goto error;
596 }
597 }
598
599 return 0;
600
601 error:
602 iwl_trans_pcie_tx_free(trans);
603
604 return ret;
605 }
606 static int iwl_tx_init(struct iwl_trans *trans)
607 {
608 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
609 int ret;
610 int txq_id, slots_num;
611 unsigned long flags;
612 bool alloc = false;
613
614 if (!trans_pcie->txq) {
615 ret = iwl_trans_tx_alloc(trans);
616 if (ret)
617 goto error;
618 alloc = true;
619 }
620
621 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
622
623 /* Turn off all Tx DMA fifos */
624 iwl_write_prph(trans, SCD_TXFACT, 0);
625
626 /* Tell NIC where to find the "keep warm" buffer */
627 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
628 trans_pcie->kw.dma >> 4);
629
630 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
631
632 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
633 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
634 txq_id++) {
635 slots_num = (txq_id == trans_pcie->cmd_queue) ?
636 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
637 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
638 slots_num, txq_id);
639 if (ret) {
640 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
641 goto error;
642 }
643 }
644
645 return 0;
646 error:
647 /*Upon error, free only if we allocated something */
648 if (alloc)
649 iwl_trans_pcie_tx_free(trans);
650 return ret;
651 }
652
653 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
654 {
655 /*
656 * (for documentation purposes)
657 * to set power to V_AUX, do:
658
659 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
660 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
661 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
662 ~APMG_PS_CTRL_MSK_PWR_SRC);
663 */
664
665 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
666 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
667 ~APMG_PS_CTRL_MSK_PWR_SRC);
668 }
669
670 /* PCI registers */
671 #define PCI_CFG_RETRY_TIMEOUT 0x041
672 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
673 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
674
675 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
676 {
677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
678 int pos;
679 u16 pci_lnk_ctl;
680
681 struct pci_dev *pci_dev = trans_pcie->pci_dev;
682
683 pos = pci_pcie_cap(pci_dev);
684 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
685 return pci_lnk_ctl;
686 }
687
688 static void iwl_apm_config(struct iwl_trans *trans)
689 {
690 /*
691 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
692 * Check if BIOS (or OS) enabled L1-ASPM on this device.
693 * If so (likely), disable L0S, so device moves directly L0->L1;
694 * costs negligible amount of power savings.
695 * If not (unlikely), enable L0S, so there is at least some
696 * power savings, even without L1.
697 */
698 u16 lctl = iwl_pciexp_link_ctrl(trans);
699
700 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
701 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
702 /* L1-ASPM enabled; disable(!) L0S */
703 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
704 dev_printk(KERN_INFO, trans->dev,
705 "L1 Enabled; Disabling L0S\n");
706 } else {
707 /* L1-ASPM disabled; enable(!) L0S */
708 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
709 dev_printk(KERN_INFO, trans->dev,
710 "L1 Disabled; Enabling L0S\n");
711 }
712 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
713 }
714
715 /*
716 * Start up NIC's basic functionality after it has been reset
717 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
718 * NOTE: This does not load uCode nor start the embedded processor
719 */
720 static int iwl_apm_init(struct iwl_trans *trans)
721 {
722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
723 int ret = 0;
724 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
725
726 /*
727 * Use "set_bit" below rather than "write", to preserve any hardware
728 * bits already set by default after reset.
729 */
730
731 /* Disable L0S exit timer (platform NMI Work/Around) */
732 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
733 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
734
735 /*
736 * Disable L0s without affecting L1;
737 * don't wait for ICH L0s (ICH bug W/A)
738 */
739 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
740 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
741
742 /* Set FH wait threshold to maximum (HW error during stress W/A) */
743 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
744
745 /*
746 * Enable HAP INTA (interrupt from management bus) to
747 * wake device's PCI Express link L1a -> L0s
748 */
749 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
750 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
751
752 iwl_apm_config(trans);
753
754 /* Configure analog phase-lock-loop before activating to D0A */
755 if (trans->cfg->base_params->pll_cfg_val)
756 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
757 trans->cfg->base_params->pll_cfg_val);
758
759 /*
760 * Set "initialization complete" bit to move adapter from
761 * D0U* --> D0A* (powered-up active) state.
762 */
763 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
764
765 /*
766 * Wait for clock stabilization; once stabilized, access to
767 * device-internal resources is supported, e.g. iwl_write_prph()
768 * and accesses to uCode SRAM.
769 */
770 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
771 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
772 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
773 if (ret < 0) {
774 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
775 goto out;
776 }
777
778 /*
779 * Enable DMA clock and wait for it to stabilize.
780 *
781 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
782 * do not disable clocks. This preserves any hardware bits already
783 * set by default in "CLK_CTRL_REG" after reset.
784 */
785 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
786 udelay(20);
787
788 /* Disable L1-Active */
789 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
790 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
791
792 set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
793
794 out:
795 return ret;
796 }
797
798 static int iwl_apm_stop_master(struct iwl_trans *trans)
799 {
800 int ret = 0;
801
802 /* stop device's busmaster DMA activity */
803 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
804
805 ret = iwl_poll_bit(trans, CSR_RESET,
806 CSR_RESET_REG_FLAG_MASTER_DISABLED,
807 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
808 if (ret)
809 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
810
811 IWL_DEBUG_INFO(trans, "stop master\n");
812
813 return ret;
814 }
815
816 static void iwl_apm_stop(struct iwl_trans *trans)
817 {
818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
819 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
820
821 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
822
823 /* Stop device's DMA activity */
824 iwl_apm_stop_master(trans);
825
826 /* Reset the entire device */
827 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
828
829 udelay(10);
830
831 /*
832 * Clear "initialization complete" bit to move adapter from
833 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
834 */
835 iwl_clear_bit(trans, CSR_GP_CNTRL,
836 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
837 }
838
839 static int iwl_nic_init(struct iwl_trans *trans)
840 {
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
842 unsigned long flags;
843
844 /* nic_init */
845 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
846 iwl_apm_init(trans);
847
848 /* Set interrupt coalescing calibration timer to default (512 usecs) */
849 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
850
851 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
852
853 iwl_set_pwr_vmain(trans);
854
855 iwl_op_mode_nic_config(trans->op_mode);
856
857 #ifndef CONFIG_IWLWIFI_IDI
858 /* Allocate the RX queue, or reset if it is already allocated */
859 iwl_rx_init(trans);
860 #endif
861
862 /* Allocate or reset and init all Tx and Command queues */
863 if (iwl_tx_init(trans))
864 return -ENOMEM;
865
866 if (trans->cfg->base_params->shadow_reg_enable) {
867 /* enable shadow regs in HW */
868 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
869 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
870 }
871
872 return 0;
873 }
874
875 #define HW_READY_TIMEOUT (50)
876
877 /* Note: returns poll_bit return value, which is >= 0 if success */
878 static int iwl_set_hw_ready(struct iwl_trans *trans)
879 {
880 int ret;
881
882 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
883 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
884
885 /* See if we got it */
886 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
887 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
888 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
889 HW_READY_TIMEOUT);
890
891 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
892 return ret;
893 }
894
895 /* Note: returns standard 0/-ERROR code */
896 static int iwl_prepare_card_hw(struct iwl_trans *trans)
897 {
898 int ret;
899
900 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
901
902 ret = iwl_set_hw_ready(trans);
903 /* If the card is ready, exit 0 */
904 if (ret >= 0)
905 return 0;
906
907 /* If HW is not ready, prepare the conditions to check again */
908 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
909 CSR_HW_IF_CONFIG_REG_PREPARE);
910
911 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
912 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
913 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
914
915 if (ret < 0)
916 return ret;
917
918 /* HW should be ready by now, check again. */
919 ret = iwl_set_hw_ready(trans);
920 if (ret >= 0)
921 return 0;
922 return ret;
923 }
924
925 /*
926 * ucode
927 */
928 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
929 const struct fw_desc *section)
930 {
931 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
932 dma_addr_t phy_addr = section->p_addr;
933 u32 byte_cnt = section->len;
934 u32 dst_addr = section->offset;
935 int ret;
936
937 trans_pcie->ucode_write_complete = false;
938
939 iwl_write_direct32(trans,
940 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
941 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
942
943 iwl_write_direct32(trans,
944 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
945 dst_addr);
946
947 iwl_write_direct32(trans,
948 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
949 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
950
951 iwl_write_direct32(trans,
952 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
953 (iwl_get_dma_hi_addr(phy_addr)
954 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
955
956 iwl_write_direct32(trans,
957 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
958 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
959 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
960 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
961
962 iwl_write_direct32(trans,
963 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
964 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
965 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
966 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
967
968 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
969 section_num);
970 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
971 trans_pcie->ucode_write_complete, 5 * HZ);
972 if (!ret) {
973 IWL_ERR(trans, "Could not load the [%d] uCode section\n",
974 section_num);
975 return -ETIMEDOUT;
976 }
977
978 return 0;
979 }
980
981 static int iwl_load_given_ucode(struct iwl_trans *trans,
982 const struct fw_img *image)
983 {
984 int ret = 0;
985 int i;
986
987 for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
988 if (!image->sec[i].p_addr)
989 break;
990
991 ret = iwl_load_section(trans, i, &image->sec[i]);
992 if (ret)
993 return ret;
994 }
995
996 /* Remove all resets to allow NIC to operate */
997 iwl_write32(trans, CSR_RESET, 0);
998
999 return 0;
1000 }
1001
1002 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1003 const struct fw_img *fw)
1004 {
1005 int ret;
1006 bool hw_rfkill;
1007
1008 /* This may fail if AMT took ownership of the device */
1009 if (iwl_prepare_card_hw(trans)) {
1010 IWL_WARN(trans, "Exit HW not ready\n");
1011 return -EIO;
1012 }
1013
1014 iwl_enable_rfkill_int(trans);
1015
1016 /* If platform's RF_KILL switch is NOT set to KILL */
1017 hw_rfkill = iwl_is_rfkill_set(trans);
1018 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1019 if (hw_rfkill)
1020 return -ERFKILL;
1021
1022 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1023
1024 ret = iwl_nic_init(trans);
1025 if (ret) {
1026 IWL_ERR(trans, "Unable to init nic\n");
1027 return ret;
1028 }
1029
1030 /* make sure rfkill handshake bits are cleared */
1031 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1032 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1033 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1034
1035 /* clear (again), then enable host interrupts */
1036 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1037 iwl_enable_interrupts(trans);
1038
1039 /* really make sure rfkill handshake bits are cleared */
1040 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1041 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1042
1043 /* Load the given image to the HW */
1044 return iwl_load_given_ucode(trans, fw);
1045 }
1046
1047 /*
1048 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1049 */
1050 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1051 {
1052 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1053 IWL_TRANS_GET_PCIE_TRANS(trans);
1054
1055 iwl_write_prph(trans, SCD_TXFACT, mask);
1056 }
1057
1058 static void iwl_tx_start(struct iwl_trans *trans)
1059 {
1060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061 u32 a;
1062 int chan;
1063 u32 reg_val;
1064
1065 /* make sure all queue are not stopped/used */
1066 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1067 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1068
1069 trans_pcie->scd_base_addr =
1070 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1071 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1072 /* reset conext data memory */
1073 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1074 a += 4)
1075 iwl_write_targ_mem(trans, a, 0);
1076 /* reset tx status memory */
1077 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1078 a += 4)
1079 iwl_write_targ_mem(trans, a, 0);
1080 for (; a < trans_pcie->scd_base_addr +
1081 SCD_TRANS_TBL_OFFSET_QUEUE(
1082 trans->cfg->base_params->num_of_queues);
1083 a += 4)
1084 iwl_write_targ_mem(trans, a, 0);
1085
1086 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1087 trans_pcie->scd_bc_tbls.dma >> 10);
1088
1089 /* The chain extension of the SCD doesn't work well. This feature is
1090 * enabled by default by the HW, so we need to disable it manually.
1091 */
1092 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1093
1094 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1095 trans_pcie->cmd_fifo);
1096
1097 /* Activate all Tx DMA/FIFO channels */
1098 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1099
1100 /* Enable DMA channel */
1101 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1102 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1103 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1104 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1105
1106 /* Update FH chicken bits */
1107 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1108 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1109 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1110
1111 /* Enable L1-Active */
1112 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1113 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1114 }
1115
1116 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1117 {
1118 iwl_reset_ict(trans);
1119 iwl_tx_start(trans);
1120 }
1121
1122 /**
1123 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1124 */
1125 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1126 {
1127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1128 int ch, txq_id, ret;
1129 unsigned long flags;
1130
1131 /* Turn off all Tx DMA fifos */
1132 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1133
1134 iwl_trans_txq_set_sched(trans, 0);
1135
1136 /* Stop each Tx DMA channel, and wait for it to be idle */
1137 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1138 iwl_write_direct32(trans,
1139 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1140 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1141 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1142 if (ret < 0)
1143 IWL_ERR(trans,
1144 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1145 ch,
1146 iwl_read_direct32(trans,
1147 FH_TSSR_TX_STATUS_REG));
1148 }
1149 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1150
1151 if (!trans_pcie->txq) {
1152 IWL_WARN(trans,
1153 "Stopping tx queues that aren't allocated...\n");
1154 return 0;
1155 }
1156
1157 /* Unmap DMA from host system and free skb's */
1158 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1159 txq_id++)
1160 iwl_tx_queue_unmap(trans, txq_id);
1161
1162 return 0;
1163 }
1164
1165 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1166 {
1167 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1168 unsigned long flags;
1169
1170 /* tell the device to stop sending interrupts */
1171 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1172 iwl_disable_interrupts(trans);
1173 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1174
1175 /* device going down, Stop using ICT table */
1176 iwl_disable_ict(trans);
1177
1178 /*
1179 * If a HW restart happens during firmware loading,
1180 * then the firmware loading might call this function
1181 * and later it might be called again due to the
1182 * restart. So don't process again if the device is
1183 * already dead.
1184 */
1185 if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1186 iwl_trans_tx_stop(trans);
1187 #ifndef CONFIG_IWLWIFI_IDI
1188 iwl_trans_rx_stop(trans);
1189 #endif
1190 /* Power-down device's busmaster DMA clocks */
1191 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1192 APMG_CLK_VAL_DMA_CLK_RQT);
1193 udelay(5);
1194 }
1195
1196 /* Make sure (redundant) we've released our request to stay awake */
1197 iwl_clear_bit(trans, CSR_GP_CNTRL,
1198 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1199
1200 /* Stop the device, and put it in low power state */
1201 iwl_apm_stop(trans);
1202
1203 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1204 * Clean again the interrupt here
1205 */
1206 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1207 iwl_disable_interrupts(trans);
1208 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1209
1210 iwl_enable_rfkill_int(trans);
1211
1212 /* wait to make sure we flush pending tasklet*/
1213 synchronize_irq(trans_pcie->irq);
1214 tasklet_kill(&trans_pcie->irq_tasklet);
1215
1216 cancel_work_sync(&trans_pcie->rx_replenish);
1217
1218 /* stop and reset the on-board processor */
1219 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1220
1221 /* clear all status bits */
1222 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1223 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1224 clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1225 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1226 }
1227
1228 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1229 {
1230 /* let the ucode operate on its own */
1231 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1232 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1233
1234 iwl_disable_interrupts(trans);
1235 iwl_clear_bit(trans, CSR_GP_CNTRL,
1236 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1237 }
1238
1239 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1240 struct iwl_device_cmd *dev_cmd, int txq_id)
1241 {
1242 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1244 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1245 struct iwl_cmd_meta *out_meta;
1246 struct iwl_tx_queue *txq;
1247 struct iwl_queue *q;
1248 dma_addr_t phys_addr = 0;
1249 dma_addr_t txcmd_phys;
1250 dma_addr_t scratch_phys;
1251 u16 len, firstlen, secondlen;
1252 u8 wait_write_ptr = 0;
1253 __le16 fc = hdr->frame_control;
1254 u8 hdr_len = ieee80211_hdrlen(fc);
1255 u16 __maybe_unused wifi_seq;
1256
1257 txq = &trans_pcie->txq[txq_id];
1258 q = &txq->q;
1259
1260 if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1261 WARN_ON_ONCE(1);
1262 return -EINVAL;
1263 }
1264
1265 spin_lock(&txq->lock);
1266
1267 /* In AGG mode, the index in the ring must correspond to the WiFi
1268 * sequence number. This is a HW requirements to help the SCD to parse
1269 * the BA.
1270 * Check here that the packets are in the right place on the ring.
1271 */
1272 #ifdef CONFIG_IWLWIFI_DEBUG
1273 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1274 WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1275 ((wifi_seq & 0xff) != q->write_ptr),
1276 "Q: %d WiFi Seq %d tfdNum %d",
1277 txq_id, wifi_seq, q->write_ptr);
1278 #endif
1279
1280 /* Set up driver data for this TFD */
1281 txq->entries[q->write_ptr].skb = skb;
1282 txq->entries[q->write_ptr].cmd = dev_cmd;
1283
1284 dev_cmd->hdr.cmd = REPLY_TX;
1285 dev_cmd->hdr.sequence =
1286 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1287 INDEX_TO_SEQ(q->write_ptr)));
1288
1289 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1290 out_meta = &txq->entries[q->write_ptr].meta;
1291
1292 /*
1293 * Use the first empty entry in this queue's command buffer array
1294 * to contain the Tx command and MAC header concatenated together
1295 * (payload data will be in another buffer).
1296 * Size of this varies, due to varying MAC header length.
1297 * If end is not dword aligned, we'll have 2 extra bytes at the end
1298 * of the MAC header (device reads on dword boundaries).
1299 * We'll tell device about this padding later.
1300 */
1301 len = sizeof(struct iwl_tx_cmd) +
1302 sizeof(struct iwl_cmd_header) + hdr_len;
1303 firstlen = (len + 3) & ~3;
1304
1305 /* Tell NIC about any 2-byte padding after MAC header */
1306 if (firstlen != len)
1307 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1308
1309 /* Physical address of this Tx command's header (not MAC header!),
1310 * within command buffer array. */
1311 txcmd_phys = dma_map_single(trans->dev,
1312 &dev_cmd->hdr, firstlen,
1313 DMA_BIDIRECTIONAL);
1314 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1315 goto out_err;
1316 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1317 dma_unmap_len_set(out_meta, len, firstlen);
1318
1319 if (!ieee80211_has_morefrags(fc)) {
1320 txq->need_update = 1;
1321 } else {
1322 wait_write_ptr = 1;
1323 txq->need_update = 0;
1324 }
1325
1326 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1327 * if any (802.11 null frames have no payload). */
1328 secondlen = skb->len - hdr_len;
1329 if (secondlen > 0) {
1330 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1331 secondlen, DMA_TO_DEVICE);
1332 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1333 dma_unmap_single(trans->dev,
1334 dma_unmap_addr(out_meta, mapping),
1335 dma_unmap_len(out_meta, len),
1336 DMA_BIDIRECTIONAL);
1337 goto out_err;
1338 }
1339 }
1340
1341 /* Attach buffers to TFD */
1342 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1343 if (secondlen > 0)
1344 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1345 secondlen, 0);
1346
1347 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1348 offsetof(struct iwl_tx_cmd, scratch);
1349
1350 /* take back ownership of DMA buffer to enable update */
1351 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1352 DMA_BIDIRECTIONAL);
1353 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1354 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1355
1356 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1357 le16_to_cpu(dev_cmd->hdr.sequence));
1358 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1359
1360 /* Set up entry for this TFD in Tx byte-count array */
1361 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1362
1363 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1364 DMA_BIDIRECTIONAL);
1365
1366 trace_iwlwifi_dev_tx(trans->dev,
1367 &txq->tfds[txq->q.write_ptr],
1368 sizeof(struct iwl_tfd),
1369 &dev_cmd->hdr, firstlen,
1370 skb->data + hdr_len, secondlen);
1371
1372 /* start timer if queue currently empty */
1373 if (txq->need_update && q->read_ptr == q->write_ptr &&
1374 trans_pcie->wd_timeout)
1375 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1376
1377 /* Tell device the write index *just past* this latest filled TFD */
1378 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1379 iwl_txq_update_write_ptr(trans, txq);
1380
1381 /*
1382 * At this point the frame is "transmitted" successfully
1383 * and we will get a TX status notification eventually,
1384 * regardless of the value of ret. "ret" only indicates
1385 * whether or not we should update the write pointer.
1386 */
1387 if (iwl_queue_space(q) < q->high_mark) {
1388 if (wait_write_ptr) {
1389 txq->need_update = 1;
1390 iwl_txq_update_write_ptr(trans, txq);
1391 } else {
1392 iwl_stop_queue(trans, txq);
1393 }
1394 }
1395 spin_unlock(&txq->lock);
1396 return 0;
1397 out_err:
1398 spin_unlock(&txq->lock);
1399 return -1;
1400 }
1401
1402 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1403 {
1404 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1405 int err;
1406 bool hw_rfkill;
1407
1408 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1409
1410 if (!trans_pcie->irq_requested) {
1411 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1412 iwl_irq_tasklet, (unsigned long)trans);
1413
1414 iwl_alloc_isr_ict(trans);
1415
1416 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1417 DRV_NAME, trans);
1418 if (err) {
1419 IWL_ERR(trans, "Error allocating IRQ %d\n",
1420 trans_pcie->irq);
1421 goto error;
1422 }
1423
1424 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1425 trans_pcie->irq_requested = true;
1426 }
1427
1428 err = iwl_prepare_card_hw(trans);
1429 if (err) {
1430 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1431 goto err_free_irq;
1432 }
1433
1434 iwl_apm_init(trans);
1435
1436 /* From now on, the op_mode will be kept updated about RF kill state */
1437 iwl_enable_rfkill_int(trans);
1438
1439 hw_rfkill = iwl_is_rfkill_set(trans);
1440 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1441
1442 return err;
1443
1444 err_free_irq:
1445 free_irq(trans_pcie->irq, trans);
1446 error:
1447 iwl_free_isr_ict(trans);
1448 tasklet_kill(&trans_pcie->irq_tasklet);
1449 return err;
1450 }
1451
1452 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1453 bool op_mode_leaving)
1454 {
1455 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1456 bool hw_rfkill;
1457 unsigned long flags;
1458
1459 iwl_apm_stop(trans);
1460
1461 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1462 iwl_disable_interrupts(trans);
1463 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1464
1465 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1466
1467 if (!op_mode_leaving) {
1468 /*
1469 * Even if we stop the HW, we still want the RF kill
1470 * interrupt
1471 */
1472 iwl_enable_rfkill_int(trans);
1473
1474 /*
1475 * Check again since the RF kill state may have changed while
1476 * all the interrupts were disabled, in this case we couldn't
1477 * receive the RF kill interrupt and update the state in the
1478 * op_mode.
1479 */
1480 hw_rfkill = iwl_is_rfkill_set(trans);
1481 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1482 }
1483 }
1484
1485 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1486 struct sk_buff_head *skbs)
1487 {
1488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1489 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1490 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1491 int tfd_num = ssn & (txq->q.n_bd - 1);
1492 int freed = 0;
1493
1494 spin_lock(&txq->lock);
1495
1496 if (txq->q.read_ptr != tfd_num) {
1497 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1498 txq_id, txq->q.read_ptr, tfd_num, ssn);
1499 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1500 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1501 iwl_wake_queue(trans, txq);
1502 }
1503
1504 spin_unlock(&txq->lock);
1505 }
1506
1507 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1508 {
1509 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1510 }
1511
1512 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1513 {
1514 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1515 }
1516
1517 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1518 {
1519 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1520 }
1521
1522 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1523 const struct iwl_trans_config *trans_cfg)
1524 {
1525 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1526
1527 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1528 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1529 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1530 trans_pcie->n_no_reclaim_cmds = 0;
1531 else
1532 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1533 if (trans_pcie->n_no_reclaim_cmds)
1534 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1535 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1536
1537 trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1538 if (trans_pcie->rx_buf_size_8k)
1539 trans_pcie->rx_page_order = get_order(8 * 1024);
1540 else
1541 trans_pcie->rx_page_order = get_order(4 * 1024);
1542
1543 trans_pcie->wd_timeout =
1544 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1545
1546 trans_pcie->command_names = trans_cfg->command_names;
1547 }
1548
1549 void iwl_trans_pcie_free(struct iwl_trans *trans)
1550 {
1551 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1552
1553 iwl_trans_pcie_tx_free(trans);
1554 #ifndef CONFIG_IWLWIFI_IDI
1555 iwl_trans_pcie_rx_free(trans);
1556 #endif
1557 if (trans_pcie->irq_requested == true) {
1558 free_irq(trans_pcie->irq, trans);
1559 iwl_free_isr_ict(trans);
1560 }
1561
1562 pci_disable_msi(trans_pcie->pci_dev);
1563 iounmap(trans_pcie->hw_base);
1564 pci_release_regions(trans_pcie->pci_dev);
1565 pci_disable_device(trans_pcie->pci_dev);
1566 kmem_cache_destroy(trans->dev_cmd_pool);
1567
1568 kfree(trans);
1569 }
1570
1571 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1572 {
1573 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1574
1575 if (state)
1576 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1577 else
1578 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1579 }
1580
1581 #ifdef CONFIG_PM_SLEEP
1582 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1583 {
1584 return 0;
1585 }
1586
1587 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1588 {
1589 bool hw_rfkill;
1590
1591 iwl_enable_rfkill_int(trans);
1592
1593 hw_rfkill = iwl_is_rfkill_set(trans);
1594 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1595
1596 if (!hw_rfkill)
1597 iwl_enable_interrupts(trans);
1598
1599 return 0;
1600 }
1601 #endif /* CONFIG_PM_SLEEP */
1602
1603 #define IWL_FLUSH_WAIT_MS 2000
1604
1605 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1606 {
1607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608 struct iwl_tx_queue *txq;
1609 struct iwl_queue *q;
1610 int cnt;
1611 unsigned long now = jiffies;
1612 int ret = 0;
1613
1614 /* waiting for all the tx frames complete might take a while */
1615 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1616 if (cnt == trans_pcie->cmd_queue)
1617 continue;
1618 txq = &trans_pcie->txq[cnt];
1619 q = &txq->q;
1620 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1621 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1622 msleep(1);
1623
1624 if (q->read_ptr != q->write_ptr) {
1625 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1626 ret = -ETIMEDOUT;
1627 break;
1628 }
1629 }
1630 return ret;
1631 }
1632
1633 static const char *get_fh_string(int cmd)
1634 {
1635 #define IWL_CMD(x) case x: return #x
1636 switch (cmd) {
1637 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1638 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1639 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1640 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1641 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1642 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1643 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1644 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1645 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1646 default:
1647 return "UNKNOWN";
1648 }
1649 #undef IWL_CMD
1650 }
1651
1652 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1653 {
1654 int i;
1655 #ifdef CONFIG_IWLWIFI_DEBUG
1656 int pos = 0;
1657 size_t bufsz = 0;
1658 #endif
1659 static const u32 fh_tbl[] = {
1660 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1661 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1662 FH_RSCSR_CHNL0_WPTR,
1663 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1664 FH_MEM_RSSR_SHARED_CTRL_REG,
1665 FH_MEM_RSSR_RX_STATUS_REG,
1666 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1667 FH_TSSR_TX_STATUS_REG,
1668 FH_TSSR_TX_ERROR_REG
1669 };
1670 #ifdef CONFIG_IWLWIFI_DEBUG
1671 if (display) {
1672 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1673 *buf = kmalloc(bufsz, GFP_KERNEL);
1674 if (!*buf)
1675 return -ENOMEM;
1676 pos += scnprintf(*buf + pos, bufsz - pos,
1677 "FH register values:\n");
1678 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1679 pos += scnprintf(*buf + pos, bufsz - pos,
1680 " %34s: 0X%08x\n",
1681 get_fh_string(fh_tbl[i]),
1682 iwl_read_direct32(trans, fh_tbl[i]));
1683 }
1684 return pos;
1685 }
1686 #endif
1687 IWL_ERR(trans, "FH register values:\n");
1688 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1689 IWL_ERR(trans, " %34s: 0X%08x\n",
1690 get_fh_string(fh_tbl[i]),
1691 iwl_read_direct32(trans, fh_tbl[i]));
1692 }
1693 return 0;
1694 }
1695
1696 static const char *get_csr_string(int cmd)
1697 {
1698 #define IWL_CMD(x) case x: return #x
1699 switch (cmd) {
1700 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1701 IWL_CMD(CSR_INT_COALESCING);
1702 IWL_CMD(CSR_INT);
1703 IWL_CMD(CSR_INT_MASK);
1704 IWL_CMD(CSR_FH_INT_STATUS);
1705 IWL_CMD(CSR_GPIO_IN);
1706 IWL_CMD(CSR_RESET);
1707 IWL_CMD(CSR_GP_CNTRL);
1708 IWL_CMD(CSR_HW_REV);
1709 IWL_CMD(CSR_EEPROM_REG);
1710 IWL_CMD(CSR_EEPROM_GP);
1711 IWL_CMD(CSR_OTP_GP_REG);
1712 IWL_CMD(CSR_GIO_REG);
1713 IWL_CMD(CSR_GP_UCODE_REG);
1714 IWL_CMD(CSR_GP_DRIVER_REG);
1715 IWL_CMD(CSR_UCODE_DRV_GP1);
1716 IWL_CMD(CSR_UCODE_DRV_GP2);
1717 IWL_CMD(CSR_LED_REG);
1718 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1719 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1720 IWL_CMD(CSR_ANA_PLL_CFG);
1721 IWL_CMD(CSR_HW_REV_WA_REG);
1722 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1723 default:
1724 return "UNKNOWN";
1725 }
1726 #undef IWL_CMD
1727 }
1728
1729 void iwl_dump_csr(struct iwl_trans *trans)
1730 {
1731 int i;
1732 static const u32 csr_tbl[] = {
1733 CSR_HW_IF_CONFIG_REG,
1734 CSR_INT_COALESCING,
1735 CSR_INT,
1736 CSR_INT_MASK,
1737 CSR_FH_INT_STATUS,
1738 CSR_GPIO_IN,
1739 CSR_RESET,
1740 CSR_GP_CNTRL,
1741 CSR_HW_REV,
1742 CSR_EEPROM_REG,
1743 CSR_EEPROM_GP,
1744 CSR_OTP_GP_REG,
1745 CSR_GIO_REG,
1746 CSR_GP_UCODE_REG,
1747 CSR_GP_DRIVER_REG,
1748 CSR_UCODE_DRV_GP1,
1749 CSR_UCODE_DRV_GP2,
1750 CSR_LED_REG,
1751 CSR_DRAM_INT_TBL_REG,
1752 CSR_GIO_CHICKEN_BITS,
1753 CSR_ANA_PLL_CFG,
1754 CSR_HW_REV_WA_REG,
1755 CSR_DBG_HPET_MEM_REG
1756 };
1757 IWL_ERR(trans, "CSR values:\n");
1758 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1759 "CSR_INT_PERIODIC_REG)\n");
1760 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1761 IWL_ERR(trans, " %25s: 0X%08x\n",
1762 get_csr_string(csr_tbl[i]),
1763 iwl_read32(trans, csr_tbl[i]));
1764 }
1765 }
1766
1767 #ifdef CONFIG_IWLWIFI_DEBUGFS
1768 /* create and remove of files */
1769 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1770 if (!debugfs_create_file(#name, mode, parent, trans, \
1771 &iwl_dbgfs_##name##_ops)) \
1772 return -ENOMEM; \
1773 } while (0)
1774
1775 /* file operation */
1776 #define DEBUGFS_READ_FUNC(name) \
1777 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1778 char __user *user_buf, \
1779 size_t count, loff_t *ppos);
1780
1781 #define DEBUGFS_WRITE_FUNC(name) \
1782 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1783 const char __user *user_buf, \
1784 size_t count, loff_t *ppos);
1785
1786
1787 #define DEBUGFS_READ_FILE_OPS(name) \
1788 DEBUGFS_READ_FUNC(name); \
1789 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1790 .read = iwl_dbgfs_##name##_read, \
1791 .open = simple_open, \
1792 .llseek = generic_file_llseek, \
1793 };
1794
1795 #define DEBUGFS_WRITE_FILE_OPS(name) \
1796 DEBUGFS_WRITE_FUNC(name); \
1797 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1798 .write = iwl_dbgfs_##name##_write, \
1799 .open = simple_open, \
1800 .llseek = generic_file_llseek, \
1801 };
1802
1803 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1804 DEBUGFS_READ_FUNC(name); \
1805 DEBUGFS_WRITE_FUNC(name); \
1806 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1807 .write = iwl_dbgfs_##name##_write, \
1808 .read = iwl_dbgfs_##name##_read, \
1809 .open = simple_open, \
1810 .llseek = generic_file_llseek, \
1811 };
1812
1813 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1814 char __user *user_buf,
1815 size_t count, loff_t *ppos)
1816 {
1817 struct iwl_trans *trans = file->private_data;
1818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1819 struct iwl_tx_queue *txq;
1820 struct iwl_queue *q;
1821 char *buf;
1822 int pos = 0;
1823 int cnt;
1824 int ret;
1825 size_t bufsz;
1826
1827 bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1828
1829 if (!trans_pcie->txq)
1830 return -EAGAIN;
1831
1832 buf = kzalloc(bufsz, GFP_KERNEL);
1833 if (!buf)
1834 return -ENOMEM;
1835
1836 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1837 txq = &trans_pcie->txq[cnt];
1838 q = &txq->q;
1839 pos += scnprintf(buf + pos, bufsz - pos,
1840 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1841 cnt, q->read_ptr, q->write_ptr,
1842 !!test_bit(cnt, trans_pcie->queue_used),
1843 !!test_bit(cnt, trans_pcie->queue_stopped));
1844 }
1845 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1846 kfree(buf);
1847 return ret;
1848 }
1849
1850 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1851 char __user *user_buf,
1852 size_t count, loff_t *ppos)
1853 {
1854 struct iwl_trans *trans = file->private_data;
1855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1856 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1857 char buf[256];
1858 int pos = 0;
1859 const size_t bufsz = sizeof(buf);
1860
1861 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1862 rxq->read);
1863 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1864 rxq->write);
1865 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1866 rxq->free_count);
1867 if (rxq->rb_stts) {
1868 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1869 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1870 } else {
1871 pos += scnprintf(buf + pos, bufsz - pos,
1872 "closed_rb_num: Not Allocated\n");
1873 }
1874 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1875 }
1876
1877 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1878 char __user *user_buf,
1879 size_t count, loff_t *ppos)
1880 {
1881 struct iwl_trans *trans = file->private_data;
1882 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1883 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1884
1885 int pos = 0;
1886 char *buf;
1887 int bufsz = 24 * 64; /* 24 items * 64 char per item */
1888 ssize_t ret;
1889
1890 buf = kzalloc(bufsz, GFP_KERNEL);
1891 if (!buf)
1892 return -ENOMEM;
1893
1894 pos += scnprintf(buf + pos, bufsz - pos,
1895 "Interrupt Statistics Report:\n");
1896
1897 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1898 isr_stats->hw);
1899 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1900 isr_stats->sw);
1901 if (isr_stats->sw || isr_stats->hw) {
1902 pos += scnprintf(buf + pos, bufsz - pos,
1903 "\tLast Restarting Code: 0x%X\n",
1904 isr_stats->err_code);
1905 }
1906 #ifdef CONFIG_IWLWIFI_DEBUG
1907 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1908 isr_stats->sch);
1909 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1910 isr_stats->alive);
1911 #endif
1912 pos += scnprintf(buf + pos, bufsz - pos,
1913 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1914
1915 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1916 isr_stats->ctkill);
1917
1918 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1919 isr_stats->wakeup);
1920
1921 pos += scnprintf(buf + pos, bufsz - pos,
1922 "Rx command responses:\t\t %u\n", isr_stats->rx);
1923
1924 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1925 isr_stats->tx);
1926
1927 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1928 isr_stats->unhandled);
1929
1930 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1931 kfree(buf);
1932 return ret;
1933 }
1934
1935 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1936 const char __user *user_buf,
1937 size_t count, loff_t *ppos)
1938 {
1939 struct iwl_trans *trans = file->private_data;
1940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1941 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1942
1943 char buf[8];
1944 int buf_size;
1945 u32 reset_flag;
1946
1947 memset(buf, 0, sizeof(buf));
1948 buf_size = min(count, sizeof(buf) - 1);
1949 if (copy_from_user(buf, user_buf, buf_size))
1950 return -EFAULT;
1951 if (sscanf(buf, "%x", &reset_flag) != 1)
1952 return -EFAULT;
1953 if (reset_flag == 0)
1954 memset(isr_stats, 0, sizeof(*isr_stats));
1955
1956 return count;
1957 }
1958
1959 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1960 const char __user *user_buf,
1961 size_t count, loff_t *ppos)
1962 {
1963 struct iwl_trans *trans = file->private_data;
1964 char buf[8];
1965 int buf_size;
1966 int csr;
1967
1968 memset(buf, 0, sizeof(buf));
1969 buf_size = min(count, sizeof(buf) - 1);
1970 if (copy_from_user(buf, user_buf, buf_size))
1971 return -EFAULT;
1972 if (sscanf(buf, "%d", &csr) != 1)
1973 return -EFAULT;
1974
1975 iwl_dump_csr(trans);
1976
1977 return count;
1978 }
1979
1980 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1981 char __user *user_buf,
1982 size_t count, loff_t *ppos)
1983 {
1984 struct iwl_trans *trans = file->private_data;
1985 char *buf;
1986 int pos = 0;
1987 ssize_t ret = -EFAULT;
1988
1989 ret = pos = iwl_dump_fh(trans, &buf, true);
1990 if (buf) {
1991 ret = simple_read_from_buffer(user_buf,
1992 count, ppos, buf, pos);
1993 kfree(buf);
1994 }
1995
1996 return ret;
1997 }
1998
1999 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2000 const char __user *user_buf,
2001 size_t count, loff_t *ppos)
2002 {
2003 struct iwl_trans *trans = file->private_data;
2004
2005 if (!trans->op_mode)
2006 return -EAGAIN;
2007
2008 local_bh_disable();
2009 iwl_op_mode_nic_error(trans->op_mode);
2010 local_bh_enable();
2011
2012 return count;
2013 }
2014
2015 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2016 DEBUGFS_READ_FILE_OPS(fh_reg);
2017 DEBUGFS_READ_FILE_OPS(rx_queue);
2018 DEBUGFS_READ_FILE_OPS(tx_queue);
2019 DEBUGFS_WRITE_FILE_OPS(csr);
2020 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2021
2022 /*
2023 * Create the debugfs files and directories
2024 *
2025 */
2026 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2027 struct dentry *dir)
2028 {
2029 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2030 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2031 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2032 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2033 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2034 DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2035 return 0;
2036 }
2037 #else
2038 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2039 struct dentry *dir)
2040 {
2041 return 0;
2042 }
2043 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2044
2045 static const struct iwl_trans_ops trans_ops_pcie = {
2046 .start_hw = iwl_trans_pcie_start_hw,
2047 .stop_hw = iwl_trans_pcie_stop_hw,
2048 .fw_alive = iwl_trans_pcie_fw_alive,
2049 .start_fw = iwl_trans_pcie_start_fw,
2050 .stop_device = iwl_trans_pcie_stop_device,
2051
2052 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2053
2054 .send_cmd = iwl_trans_pcie_send_cmd,
2055
2056 .tx = iwl_trans_pcie_tx,
2057 .reclaim = iwl_trans_pcie_reclaim,
2058
2059 .txq_disable = iwl_trans_pcie_txq_disable,
2060 .txq_enable = iwl_trans_pcie_txq_enable,
2061
2062 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2063
2064 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2065
2066 #ifdef CONFIG_PM_SLEEP
2067 .suspend = iwl_trans_pcie_suspend,
2068 .resume = iwl_trans_pcie_resume,
2069 #endif
2070 .write8 = iwl_trans_pcie_write8,
2071 .write32 = iwl_trans_pcie_write32,
2072 .read32 = iwl_trans_pcie_read32,
2073 .configure = iwl_trans_pcie_configure,
2074 .set_pmi = iwl_trans_pcie_set_pmi,
2075 };
2076
2077 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2078 const struct pci_device_id *ent,
2079 const struct iwl_cfg *cfg)
2080 {
2081 struct iwl_trans_pcie *trans_pcie;
2082 struct iwl_trans *trans;
2083 u16 pci_cmd;
2084 int err;
2085
2086 trans = kzalloc(sizeof(struct iwl_trans) +
2087 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2088
2089 if (WARN_ON(!trans))
2090 return NULL;
2091
2092 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2093
2094 trans->ops = &trans_ops_pcie;
2095 trans->cfg = cfg;
2096 trans_pcie->trans = trans;
2097 spin_lock_init(&trans_pcie->irq_lock);
2098 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2099
2100 /* W/A - seems to solve weird behavior. We need to remove this if we
2101 * don't want to stay in L1 all the time. This wastes a lot of power */
2102 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2103 PCIE_LINK_STATE_CLKPM);
2104
2105 if (pci_enable_device(pdev)) {
2106 err = -ENODEV;
2107 goto out_no_pci;
2108 }
2109
2110 pci_set_master(pdev);
2111
2112 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2113 if (!err)
2114 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2115 if (err) {
2116 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2117 if (!err)
2118 err = pci_set_consistent_dma_mask(pdev,
2119 DMA_BIT_MASK(32));
2120 /* both attempts failed: */
2121 if (err) {
2122 dev_printk(KERN_ERR, &pdev->dev,
2123 "No suitable DMA available.\n");
2124 goto out_pci_disable_device;
2125 }
2126 }
2127
2128 err = pci_request_regions(pdev, DRV_NAME);
2129 if (err) {
2130 dev_printk(KERN_ERR, &pdev->dev,
2131 "pci_request_regions failed\n");
2132 goto out_pci_disable_device;
2133 }
2134
2135 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2136 if (!trans_pcie->hw_base) {
2137 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2138 err = -ENODEV;
2139 goto out_pci_release_regions;
2140 }
2141
2142 dev_printk(KERN_INFO, &pdev->dev,
2143 "pci_resource_len = 0x%08llx\n",
2144 (unsigned long long) pci_resource_len(pdev, 0));
2145 dev_printk(KERN_INFO, &pdev->dev,
2146 "pci_resource_base = %p\n", trans_pcie->hw_base);
2147
2148 dev_printk(KERN_INFO, &pdev->dev,
2149 "HW Revision ID = 0x%X\n", pdev->revision);
2150
2151 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2152 * PCI Tx retries from interfering with C3 CPU state */
2153 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2154
2155 err = pci_enable_msi(pdev);
2156 if (err)
2157 dev_printk(KERN_ERR, &pdev->dev,
2158 "pci_enable_msi failed(0X%x)\n", err);
2159
2160 trans->dev = &pdev->dev;
2161 trans_pcie->irq = pdev->irq;
2162 trans_pcie->pci_dev = pdev;
2163 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2164 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2165 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2166 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2167
2168 /* TODO: Move this away, not needed if not MSI */
2169 /* enable rfkill interrupt: hw bug w/a */
2170 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2171 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2172 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2173 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2174 }
2175
2176 /* Initialize the wait queue for commands */
2177 init_waitqueue_head(&trans->wait_command_queue);
2178 spin_lock_init(&trans->reg_lock);
2179
2180 snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2181 "iwl_cmd_pool:%s", dev_name(trans->dev));
2182
2183 trans->dev_cmd_headroom = 0;
2184 trans->dev_cmd_pool =
2185 kmem_cache_create(trans->dev_cmd_pool_name,
2186 sizeof(struct iwl_device_cmd)
2187 + trans->dev_cmd_headroom,
2188 sizeof(void *),
2189 SLAB_HWCACHE_ALIGN,
2190 NULL);
2191
2192 if (!trans->dev_cmd_pool)
2193 goto out_pci_disable_msi;
2194
2195 return trans;
2196
2197 out_pci_disable_msi:
2198 pci_disable_msi(pdev);
2199 out_pci_release_regions:
2200 pci_release_regions(pdev);
2201 out_pci_disable_device:
2202 pci_disable_device(pdev);
2203 out_no_pci:
2204 kfree(trans);
2205 return NULL;
2206 }
kernel source for telekom puls (alcatel/mediatek)