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Merge branch 'x86-irq-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/slab.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/skbuff.h>
41 #include <linux/netdevice.h>
42 #include <linux/wireless.h>
43 #include <linux/firmware.h>
44 #include <linux/etherdevice.h>
45 #include <linux/if_arp.h>
46
47 #include <net/mac80211.h>
48
49 #include <asm/div64.h>
50
51 #define DRV_NAME "iwlagn"
52
53 #include "iwl-eeprom.h"
54 #include "iwl-dev.h"
55 #include "iwl-core.h"
56 #include "iwl-io.h"
57 #include "iwl-helpers.h"
58 #include "iwl-sta.h"
59 #include "iwl-calib.h"
60 #include "iwl-agn.h"
61
62
63 /******************************************************************************
64 *
65 * module boiler plate
66 *
67 ******************************************************************************/
68
69 /*
70 * module name, copyright, version, etc.
71 */
72 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
73
74 #ifdef CONFIG_IWLWIFI_DEBUG
75 #define VD "d"
76 #else
77 #define VD
78 #endif
79
80 #define DRV_VERSION IWLWIFI_VERSION VD
81
82
83 MODULE_DESCRIPTION(DRV_DESCRIPTION);
84 MODULE_VERSION(DRV_VERSION);
85 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
86 MODULE_LICENSE("GPL");
87 MODULE_ALIAS("iwl4965");
88
89 /**
90 * iwl_commit_rxon - commit staging_rxon to hardware
91 *
92 * The RXON command in staging_rxon is committed to the hardware and
93 * the active_rxon structure is updated with the new data. This
94 * function correctly transitions out of the RXON_ASSOC_MSK state if
95 * a HW tune is required based on the RXON structure changes.
96 */
97 int iwl_commit_rxon(struct iwl_priv *priv)
98 {
99 /* cast away the const for active_rxon in this function */
100 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
101 int ret;
102 bool new_assoc =
103 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
104
105 if (!iwl_is_alive(priv))
106 return -EBUSY;
107
108 /* always get timestamp with Rx frame */
109 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
110
111 ret = iwl_check_rxon_cmd(priv);
112 if (ret) {
113 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
114 return -EINVAL;
115 }
116
117 /*
118 * receive commit_rxon request
119 * abort any previous channel switch if still in process
120 */
121 if (priv->switch_rxon.switch_in_progress &&
122 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
123 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
124 le16_to_cpu(priv->switch_rxon.channel));
125 iwl_chswitch_done(priv, false);
126 }
127
128 /* If we don't need to send a full RXON, we can use
129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
130 * and other flags for the current radio configuration. */
131 if (!iwl_full_rxon_required(priv)) {
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
135 return ret;
136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
139 iwl_print_rx_config_cmd(priv);
140 return 0;
141 }
142
143 /* If we are currently associated and the new config requires
144 * an RXON_ASSOC and the new config wants the associated mask enabled,
145 * we must clear the associated from the active configuration
146 * before we apply the new config */
147 if (iwl_is_associated(priv) && new_assoc) {
148 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
149 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
150
151 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
152 sizeof(struct iwl_rxon_cmd),
153 &priv->active_rxon);
154
155 /* If the mask clearing failed then we set
156 * active_rxon back to what it was previously */
157 if (ret) {
158 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
159 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
160 return ret;
161 }
162 iwl_clear_ucode_stations(priv);
163 iwl_restore_stations(priv);
164 ret = iwl_restore_default_wep_keys(priv);
165 if (ret) {
166 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
167 return ret;
168 }
169 }
170
171 IWL_DEBUG_INFO(priv, "Sending RXON\n"
172 "* with%s RXON_FILTER_ASSOC_MSK\n"
173 "* channel = %d\n"
174 "* bssid = %pM\n",
175 (new_assoc ? "" : "out"),
176 le16_to_cpu(priv->staging_rxon.channel),
177 priv->staging_rxon.bssid_addr);
178
179 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
180
181 /* Apply the new configuration
182 * RXON unassoc clears the station table in uCode so restoration of
183 * stations is needed after it (the RXON command) completes
184 */
185 if (!new_assoc) {
186 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
187 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
188 if (ret) {
189 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
190 return ret;
191 }
192 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
193 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
194 iwl_clear_ucode_stations(priv);
195 iwl_restore_stations(priv);
196 ret = iwl_restore_default_wep_keys(priv);
197 if (ret) {
198 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
199 return ret;
200 }
201 }
202
203 priv->start_calib = 0;
204 if (new_assoc) {
205 /* Apply the new configuration
206 * RXON assoc doesn't clear the station table in uCode,
207 */
208 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
209 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
210 if (ret) {
211 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
212 return ret;
213 }
214 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
215 }
216 iwl_print_rx_config_cmd(priv);
217
218 iwl_init_sensitivity(priv);
219
220 /* If we issue a new RXON command which required a tune then we must
221 * send a new TXPOWER command or we won't be able to Tx any frames */
222 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
223 if (ret) {
224 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
225 return ret;
226 }
227
228 return 0;
229 }
230
231 void iwl_update_chain_flags(struct iwl_priv *priv)
232 {
233
234 if (priv->cfg->ops->hcmd->set_rxon_chain)
235 priv->cfg->ops->hcmd->set_rxon_chain(priv);
236 iwlcore_commit_rxon(priv);
237 }
238
239 static void iwl_clear_free_frames(struct iwl_priv *priv)
240 {
241 struct list_head *element;
242
243 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
244 priv->frames_count);
245
246 while (!list_empty(&priv->free_frames)) {
247 element = priv->free_frames.next;
248 list_del(element);
249 kfree(list_entry(element, struct iwl_frame, list));
250 priv->frames_count--;
251 }
252
253 if (priv->frames_count) {
254 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
255 priv->frames_count);
256 priv->frames_count = 0;
257 }
258 }
259
260 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
261 {
262 struct iwl_frame *frame;
263 struct list_head *element;
264 if (list_empty(&priv->free_frames)) {
265 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
266 if (!frame) {
267 IWL_ERR(priv, "Could not allocate frame!\n");
268 return NULL;
269 }
270
271 priv->frames_count++;
272 return frame;
273 }
274
275 element = priv->free_frames.next;
276 list_del(element);
277 return list_entry(element, struct iwl_frame, list);
278 }
279
280 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
281 {
282 memset(frame, 0, sizeof(*frame));
283 list_add(&frame->list, &priv->free_frames);
284 }
285
286 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
287 struct ieee80211_hdr *hdr,
288 int left)
289 {
290 if (!priv->ibss_beacon)
291 return 0;
292
293 if (priv->ibss_beacon->len > left)
294 return 0;
295
296 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
297
298 return priv->ibss_beacon->len;
299 }
300
301 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
302 static void iwl_set_beacon_tim(struct iwl_priv *priv,
303 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
304 u8 *beacon, u32 frame_size)
305 {
306 u16 tim_idx;
307 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
308
309 /*
310 * The index is relative to frame start but we start looking at the
311 * variable-length part of the beacon.
312 */
313 tim_idx = mgmt->u.beacon.variable - beacon;
314
315 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
316 while ((tim_idx < (frame_size - 2)) &&
317 (beacon[tim_idx] != WLAN_EID_TIM))
318 tim_idx += beacon[tim_idx+1] + 2;
319
320 /* If TIM field was found, set variables */
321 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
322 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
323 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
324 } else
325 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
326 }
327
328 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
329 struct iwl_frame *frame)
330 {
331 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
332 u32 frame_size;
333 u32 rate_flags;
334 u32 rate;
335 /*
336 * We have to set up the TX command, the TX Beacon command, and the
337 * beacon contents.
338 */
339
340 /* Initialize memory */
341 tx_beacon_cmd = &frame->u.beacon;
342 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
343
344 /* Set up TX beacon contents */
345 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
346 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
347 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
348 return 0;
349
350 /* Set up TX command fields */
351 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
352 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
353 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
354 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
355 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
356
357 /* Set up TX beacon command fields */
358 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
359 frame_size);
360
361 /* Set up packet rate and flags */
362 rate = iwl_rate_get_lowest_plcp(priv);
363 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
364 priv->hw_params.valid_tx_ant);
365 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
366 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
367 rate_flags |= RATE_MCS_CCK_MSK;
368 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
369 rate_flags);
370
371 return sizeof(*tx_beacon_cmd) + frame_size;
372 }
373 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
374 {
375 struct iwl_frame *frame;
376 unsigned int frame_size;
377 int rc;
378
379 frame = iwl_get_free_frame(priv);
380 if (!frame) {
381 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
382 "command.\n");
383 return -ENOMEM;
384 }
385
386 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
387 if (!frame_size) {
388 IWL_ERR(priv, "Error configuring the beacon command\n");
389 iwl_free_frame(priv, frame);
390 return -EINVAL;
391 }
392
393 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
394 &frame->u.cmd[0]);
395
396 iwl_free_frame(priv, frame);
397
398 return rc;
399 }
400
401 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
402 {
403 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
404
405 dma_addr_t addr = get_unaligned_le32(&tb->lo);
406 if (sizeof(dma_addr_t) > sizeof(u32))
407 addr |=
408 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
409
410 return addr;
411 }
412
413 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
414 {
415 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
416
417 return le16_to_cpu(tb->hi_n_len) >> 4;
418 }
419
420 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
421 dma_addr_t addr, u16 len)
422 {
423 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
424 u16 hi_n_len = len << 4;
425
426 put_unaligned_le32(addr, &tb->lo);
427 if (sizeof(dma_addr_t) > sizeof(u32))
428 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
429
430 tb->hi_n_len = cpu_to_le16(hi_n_len);
431
432 tfd->num_tbs = idx + 1;
433 }
434
435 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
436 {
437 return tfd->num_tbs & 0x1f;
438 }
439
440 /**
441 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
442 * @priv - driver private data
443 * @txq - tx queue
444 *
445 * Does NOT advance any TFD circular buffer read/write indexes
446 * Does NOT free the TFD itself (which is within circular buffer)
447 */
448 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
449 {
450 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
451 struct iwl_tfd *tfd;
452 struct pci_dev *dev = priv->pci_dev;
453 int index = txq->q.read_ptr;
454 int i;
455 int num_tbs;
456
457 tfd = &tfd_tmp[index];
458
459 /* Sanity check on number of chunks */
460 num_tbs = iwl_tfd_get_num_tbs(tfd);
461
462 if (num_tbs >= IWL_NUM_OF_TBS) {
463 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
464 /* @todo issue fatal error, it is quite serious situation */
465 return;
466 }
467
468 /* Unmap tx_cmd */
469 if (num_tbs)
470 pci_unmap_single(dev,
471 dma_unmap_addr(&txq->meta[index], mapping),
472 dma_unmap_len(&txq->meta[index], len),
473 PCI_DMA_BIDIRECTIONAL);
474
475 /* Unmap chunks, if any. */
476 for (i = 1; i < num_tbs; i++)
477 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
478 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
479
480 /* free SKB */
481 if (txq->txb) {
482 struct sk_buff *skb;
483
484 skb = txq->txb[txq->q.read_ptr].skb;
485
486 /* can be called from irqs-disabled context */
487 if (skb) {
488 dev_kfree_skb_any(skb);
489 txq->txb[txq->q.read_ptr].skb = NULL;
490 }
491 }
492 }
493
494 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
495 struct iwl_tx_queue *txq,
496 dma_addr_t addr, u16 len,
497 u8 reset, u8 pad)
498 {
499 struct iwl_queue *q;
500 struct iwl_tfd *tfd, *tfd_tmp;
501 u32 num_tbs;
502
503 q = &txq->q;
504 tfd_tmp = (struct iwl_tfd *)txq->tfds;
505 tfd = &tfd_tmp[q->write_ptr];
506
507 if (reset)
508 memset(tfd, 0, sizeof(*tfd));
509
510 num_tbs = iwl_tfd_get_num_tbs(tfd);
511
512 /* Each TFD can point to a maximum 20 Tx buffers */
513 if (num_tbs >= IWL_NUM_OF_TBS) {
514 IWL_ERR(priv, "Error can not send more than %d chunks\n",
515 IWL_NUM_OF_TBS);
516 return -EINVAL;
517 }
518
519 BUG_ON(addr & ~DMA_BIT_MASK(36));
520 if (unlikely(addr & ~IWL_TX_DMA_MASK))
521 IWL_ERR(priv, "Unaligned address = %llx\n",
522 (unsigned long long)addr);
523
524 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
525
526 return 0;
527 }
528
529 /*
530 * Tell nic where to find circular buffer of Tx Frame Descriptors for
531 * given Tx queue, and enable the DMA channel used for that queue.
532 *
533 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
534 * channels supported in hardware.
535 */
536 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
537 struct iwl_tx_queue *txq)
538 {
539 int txq_id = txq->q.id;
540
541 /* Circular buffer (TFD queue in DRAM) physical base address */
542 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
543 txq->q.dma_addr >> 8);
544
545 return 0;
546 }
547
548 /******************************************************************************
549 *
550 * Generic RX handler implementations
551 *
552 ******************************************************************************/
553 static void iwl_rx_reply_alive(struct iwl_priv *priv,
554 struct iwl_rx_mem_buffer *rxb)
555 {
556 struct iwl_rx_packet *pkt = rxb_addr(rxb);
557 struct iwl_alive_resp *palive;
558 struct delayed_work *pwork;
559
560 palive = &pkt->u.alive_frame;
561
562 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
563 "0x%01X 0x%01X\n",
564 palive->is_valid, palive->ver_type,
565 palive->ver_subtype);
566
567 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
568 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
569 memcpy(&priv->card_alive_init,
570 &pkt->u.alive_frame,
571 sizeof(struct iwl_init_alive_resp));
572 pwork = &priv->init_alive_start;
573 } else {
574 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
575 memcpy(&priv->card_alive, &pkt->u.alive_frame,
576 sizeof(struct iwl_alive_resp));
577 pwork = &priv->alive_start;
578 }
579
580 /* We delay the ALIVE response by 5ms to
581 * give the HW RF Kill time to activate... */
582 if (palive->is_valid == UCODE_VALID_OK)
583 queue_delayed_work(priv->workqueue, pwork,
584 msecs_to_jiffies(5));
585 else
586 IWL_WARN(priv, "uCode did not respond OK.\n");
587 }
588
589 static void iwl_bg_beacon_update(struct work_struct *work)
590 {
591 struct iwl_priv *priv =
592 container_of(work, struct iwl_priv, beacon_update);
593 struct sk_buff *beacon;
594
595 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
596 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
597
598 if (!beacon) {
599 IWL_ERR(priv, "update beacon failed\n");
600 return;
601 }
602
603 mutex_lock(&priv->mutex);
604 /* new beacon skb is allocated every time; dispose previous.*/
605 if (priv->ibss_beacon)
606 dev_kfree_skb(priv->ibss_beacon);
607
608 priv->ibss_beacon = beacon;
609 mutex_unlock(&priv->mutex);
610
611 iwl_send_beacon_cmd(priv);
612 }
613
614 /**
615 * iwl_bg_statistics_periodic - Timer callback to queue statistics
616 *
617 * This callback is provided in order to send a statistics request.
618 *
619 * This timer function is continually reset to execute within
620 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
621 * was received. We need to ensure we receive the statistics in order
622 * to update the temperature used for calibrating the TXPOWER.
623 */
624 static void iwl_bg_statistics_periodic(unsigned long data)
625 {
626 struct iwl_priv *priv = (struct iwl_priv *)data;
627
628 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
629 return;
630
631 /* dont send host command if rf-kill is on */
632 if (!iwl_is_ready_rf(priv))
633 return;
634
635 iwl_send_statistics_request(priv, CMD_ASYNC, false);
636 }
637
638
639 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
640 u32 start_idx, u32 num_events,
641 u32 mode)
642 {
643 u32 i;
644 u32 ptr; /* SRAM byte address of log data */
645 u32 ev, time, data; /* event log data */
646 unsigned long reg_flags;
647
648 if (mode == 0)
649 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
650 else
651 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
652
653 /* Make sure device is powered up for SRAM reads */
654 spin_lock_irqsave(&priv->reg_lock, reg_flags);
655 if (iwl_grab_nic_access(priv)) {
656 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
657 return;
658 }
659
660 /* Set starting address; reads will auto-increment */
661 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
662 rmb();
663
664 /*
665 * "time" is actually "data" for mode 0 (no timestamp).
666 * place event id # at far right for easier visual parsing.
667 */
668 for (i = 0; i < num_events; i++) {
669 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
670 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
671 if (mode == 0) {
672 trace_iwlwifi_dev_ucode_cont_event(priv,
673 0, time, ev);
674 } else {
675 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
676 trace_iwlwifi_dev_ucode_cont_event(priv,
677 time, data, ev);
678 }
679 }
680 /* Allow device to power down */
681 iwl_release_nic_access(priv);
682 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
683 }
684
685 static void iwl_continuous_event_trace(struct iwl_priv *priv)
686 {
687 u32 capacity; /* event log capacity in # entries */
688 u32 base; /* SRAM byte address of event log header */
689 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
690 u32 num_wraps; /* # times uCode wrapped to top of log */
691 u32 next_entry; /* index of next entry to be written by uCode */
692
693 if (priv->ucode_type == UCODE_INIT)
694 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
695 else
696 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
697 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
698 capacity = iwl_read_targ_mem(priv, base);
699 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
700 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
701 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
702 } else
703 return;
704
705 if (num_wraps == priv->event_log.num_wraps) {
706 iwl_print_cont_event_trace(priv,
707 base, priv->event_log.next_entry,
708 next_entry - priv->event_log.next_entry,
709 mode);
710 priv->event_log.non_wraps_count++;
711 } else {
712 if ((num_wraps - priv->event_log.num_wraps) > 1)
713 priv->event_log.wraps_more_count++;
714 else
715 priv->event_log.wraps_once_count++;
716 trace_iwlwifi_dev_ucode_wrap_event(priv,
717 num_wraps - priv->event_log.num_wraps,
718 next_entry, priv->event_log.next_entry);
719 if (next_entry < priv->event_log.next_entry) {
720 iwl_print_cont_event_trace(priv, base,
721 priv->event_log.next_entry,
722 capacity - priv->event_log.next_entry,
723 mode);
724
725 iwl_print_cont_event_trace(priv, base, 0,
726 next_entry, mode);
727 } else {
728 iwl_print_cont_event_trace(priv, base,
729 next_entry, capacity - next_entry,
730 mode);
731
732 iwl_print_cont_event_trace(priv, base, 0,
733 next_entry, mode);
734 }
735 }
736 priv->event_log.num_wraps = num_wraps;
737 priv->event_log.next_entry = next_entry;
738 }
739
740 /**
741 * iwl_bg_ucode_trace - Timer callback to log ucode event
742 *
743 * The timer is continually set to execute every
744 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
745 * this function is to perform continuous uCode event logging operation
746 * if enabled
747 */
748 static void iwl_bg_ucode_trace(unsigned long data)
749 {
750 struct iwl_priv *priv = (struct iwl_priv *)data;
751
752 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
753 return;
754
755 if (priv->event_log.ucode_trace) {
756 iwl_continuous_event_trace(priv);
757 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
758 mod_timer(&priv->ucode_trace,
759 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
760 }
761 }
762
763 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
764 struct iwl_rx_mem_buffer *rxb)
765 {
766 #ifdef CONFIG_IWLWIFI_DEBUG
767 struct iwl_rx_packet *pkt = rxb_addr(rxb);
768 struct iwl4965_beacon_notif *beacon =
769 (struct iwl4965_beacon_notif *)pkt->u.raw;
770 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
771
772 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
773 "tsf %d %d rate %d\n",
774 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
775 beacon->beacon_notify_hdr.failure_frame,
776 le32_to_cpu(beacon->ibss_mgr_status),
777 le32_to_cpu(beacon->high_tsf),
778 le32_to_cpu(beacon->low_tsf), rate);
779 #endif
780
781 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
782 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
783 queue_work(priv->workqueue, &priv->beacon_update);
784 }
785
786 /* Handle notification from uCode that card's power state is changing
787 * due to software, hardware, or critical temperature RFKILL */
788 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
789 struct iwl_rx_mem_buffer *rxb)
790 {
791 struct iwl_rx_packet *pkt = rxb_addr(rxb);
792 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
793 unsigned long status = priv->status;
794
795 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
796 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
797 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
798 (flags & CT_CARD_DISABLED) ?
799 "Reached" : "Not reached");
800
801 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
802 CT_CARD_DISABLED)) {
803
804 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
805 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
806
807 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
808 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
809
810 if (!(flags & RXON_CARD_DISABLED)) {
811 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
812 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
813 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
814 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
815 }
816 if (flags & CT_CARD_DISABLED)
817 iwl_tt_enter_ct_kill(priv);
818 }
819 if (!(flags & CT_CARD_DISABLED))
820 iwl_tt_exit_ct_kill(priv);
821
822 if (flags & HW_CARD_DISABLED)
823 set_bit(STATUS_RF_KILL_HW, &priv->status);
824 else
825 clear_bit(STATUS_RF_KILL_HW, &priv->status);
826
827
828 if (!(flags & RXON_CARD_DISABLED))
829 iwl_scan_cancel(priv);
830
831 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
832 test_bit(STATUS_RF_KILL_HW, &priv->status)))
833 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
834 test_bit(STATUS_RF_KILL_HW, &priv->status));
835 else
836 wake_up_interruptible(&priv->wait_command_queue);
837 }
838
839 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
840 {
841 if (src == IWL_PWR_SRC_VAUX) {
842 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
843 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
844 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
845 ~APMG_PS_CTRL_MSK_PWR_SRC);
846 } else {
847 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
848 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
849 ~APMG_PS_CTRL_MSK_PWR_SRC);
850 }
851
852 return 0;
853 }
854
855 static void iwl_bg_tx_flush(struct work_struct *work)
856 {
857 struct iwl_priv *priv =
858 container_of(work, struct iwl_priv, tx_flush);
859
860 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
861 return;
862
863 /* do nothing if rf-kill is on */
864 if (!iwl_is_ready_rf(priv))
865 return;
866
867 if (priv->cfg->ops->lib->txfifo_flush) {
868 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
869 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
870 }
871 }
872
873 /**
874 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
875 *
876 * Setup the RX handlers for each of the reply types sent from the uCode
877 * to the host.
878 *
879 * This function chains into the hardware specific files for them to setup
880 * any hardware specific handlers as well.
881 */
882 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
883 {
884 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
885 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
886 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
887 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
888 iwl_rx_spectrum_measure_notif;
889 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
890 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
891 iwl_rx_pm_debug_statistics_notif;
892 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
893
894 /*
895 * The same handler is used for both the REPLY to a discrete
896 * statistics request from the host as well as for the periodic
897 * statistics notifications (after received beacons) from the uCode.
898 */
899 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
900 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
901
902 iwl_setup_rx_scan_handlers(priv);
903
904 /* status change handler */
905 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
906
907 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
908 iwl_rx_missed_beacon_notif;
909 /* Rx handlers */
910 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
911 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
912 /* block ack */
913 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
914 /* Set up hardware specific Rx handlers */
915 priv->cfg->ops->lib->rx_handler_setup(priv);
916 }
917
918 /**
919 * iwl_rx_handle - Main entry function for receiving responses from uCode
920 *
921 * Uses the priv->rx_handlers callback function array to invoke
922 * the appropriate handlers, including command responses,
923 * frame-received notifications, and other notifications.
924 */
925 void iwl_rx_handle(struct iwl_priv *priv)
926 {
927 struct iwl_rx_mem_buffer *rxb;
928 struct iwl_rx_packet *pkt;
929 struct iwl_rx_queue *rxq = &priv->rxq;
930 u32 r, i;
931 int reclaim;
932 unsigned long flags;
933 u8 fill_rx = 0;
934 u32 count = 8;
935 int total_empty;
936
937 /* uCode's read index (stored in shared DRAM) indicates the last Rx
938 * buffer that the driver may process (last buffer filled by ucode). */
939 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
940 i = rxq->read;
941
942 /* Rx interrupt, but nothing sent from uCode */
943 if (i == r)
944 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
945
946 /* calculate total frames need to be restock after handling RX */
947 total_empty = r - rxq->write_actual;
948 if (total_empty < 0)
949 total_empty += RX_QUEUE_SIZE;
950
951 if (total_empty > (RX_QUEUE_SIZE / 2))
952 fill_rx = 1;
953
954 while (i != r) {
955 int len;
956
957 rxb = rxq->queue[i];
958
959 /* If an RXB doesn't have a Rx queue slot associated with it,
960 * then a bug has been introduced in the queue refilling
961 * routines -- catch it here */
962 BUG_ON(rxb == NULL);
963
964 rxq->queue[i] = NULL;
965
966 pci_unmap_page(priv->pci_dev, rxb->page_dma,
967 PAGE_SIZE << priv->hw_params.rx_page_order,
968 PCI_DMA_FROMDEVICE);
969 pkt = rxb_addr(rxb);
970
971 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
972 len += sizeof(u32); /* account for status word */
973 trace_iwlwifi_dev_rx(priv, pkt, len);
974
975 /* Reclaim a command buffer only if this packet is a response
976 * to a (driver-originated) command.
977 * If the packet (e.g. Rx frame) originated from uCode,
978 * there is no command buffer to reclaim.
979 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
980 * but apparently a few don't get set; catch them here. */
981 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
982 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
983 (pkt->hdr.cmd != REPLY_RX) &&
984 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
985 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
986 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
987 (pkt->hdr.cmd != REPLY_TX);
988
989 /* Based on type of command response or notification,
990 * handle those that need handling via function in
991 * rx_handlers table. See iwl_setup_rx_handlers() */
992 if (priv->rx_handlers[pkt->hdr.cmd]) {
993 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
994 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
995 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
996 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
997 } else {
998 /* No handling needed */
999 IWL_DEBUG_RX(priv,
1000 "r %d i %d No handler needed for %s, 0x%02x\n",
1001 r, i, get_cmd_string(pkt->hdr.cmd),
1002 pkt->hdr.cmd);
1003 }
1004
1005 /*
1006 * XXX: After here, we should always check rxb->page
1007 * against NULL before touching it or its virtual
1008 * memory (pkt). Because some rx_handler might have
1009 * already taken or freed the pages.
1010 */
1011
1012 if (reclaim) {
1013 /* Invoke any callbacks, transfer the buffer to caller,
1014 * and fire off the (possibly) blocking iwl_send_cmd()
1015 * as we reclaim the driver command queue */
1016 if (rxb->page)
1017 iwl_tx_cmd_complete(priv, rxb);
1018 else
1019 IWL_WARN(priv, "Claim null rxb?\n");
1020 }
1021
1022 /* Reuse the page if possible. For notification packets and
1023 * SKBs that fail to Rx correctly, add them back into the
1024 * rx_free list for reuse later. */
1025 spin_lock_irqsave(&rxq->lock, flags);
1026 if (rxb->page != NULL) {
1027 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1028 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1029 PCI_DMA_FROMDEVICE);
1030 list_add_tail(&rxb->list, &rxq->rx_free);
1031 rxq->free_count++;
1032 } else
1033 list_add_tail(&rxb->list, &rxq->rx_used);
1034
1035 spin_unlock_irqrestore(&rxq->lock, flags);
1036
1037 i = (i + 1) & RX_QUEUE_MASK;
1038 /* If there are a lot of unused frames,
1039 * restock the Rx queue so ucode wont assert. */
1040 if (fill_rx) {
1041 count++;
1042 if (count >= 8) {
1043 rxq->read = i;
1044 iwlagn_rx_replenish_now(priv);
1045 count = 0;
1046 }
1047 }
1048 }
1049
1050 /* Backtrack one entry */
1051 rxq->read = i;
1052 if (fill_rx)
1053 iwlagn_rx_replenish_now(priv);
1054 else
1055 iwlagn_rx_queue_restock(priv);
1056 }
1057
1058 /* call this function to flush any scheduled tasklet */
1059 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1060 {
1061 /* wait to make sure we flush pending tasklet*/
1062 synchronize_irq(priv->pci_dev->irq);
1063 tasklet_kill(&priv->irq_tasklet);
1064 }
1065
1066 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1067 {
1068 u32 inta, handled = 0;
1069 u32 inta_fh;
1070 unsigned long flags;
1071 u32 i;
1072 #ifdef CONFIG_IWLWIFI_DEBUG
1073 u32 inta_mask;
1074 #endif
1075
1076 spin_lock_irqsave(&priv->lock, flags);
1077
1078 /* Ack/clear/reset pending uCode interrupts.
1079 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1080 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
1081 inta = iwl_read32(priv, CSR_INT);
1082 iwl_write32(priv, CSR_INT, inta);
1083
1084 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1085 * Any new interrupts that happen after this, either while we're
1086 * in this tasklet, or later, will show up in next ISR/tasklet. */
1087 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1088 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1089
1090 #ifdef CONFIG_IWLWIFI_DEBUG
1091 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1092 /* just for debug */
1093 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1094 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1095 inta, inta_mask, inta_fh);
1096 }
1097 #endif
1098
1099 spin_unlock_irqrestore(&priv->lock, flags);
1100
1101 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1102 * atomic, make sure that inta covers all the interrupts that
1103 * we've discovered, even if FH interrupt came in just after
1104 * reading CSR_INT. */
1105 if (inta_fh & CSR49_FH_INT_RX_MASK)
1106 inta |= CSR_INT_BIT_FH_RX;
1107 if (inta_fh & CSR49_FH_INT_TX_MASK)
1108 inta |= CSR_INT_BIT_FH_TX;
1109
1110 /* Now service all interrupt bits discovered above. */
1111 if (inta & CSR_INT_BIT_HW_ERR) {
1112 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1113
1114 /* Tell the device to stop sending interrupts */
1115 iwl_disable_interrupts(priv);
1116
1117 priv->isr_stats.hw++;
1118 iwl_irq_handle_error(priv);
1119
1120 handled |= CSR_INT_BIT_HW_ERR;
1121
1122 return;
1123 }
1124
1125 #ifdef CONFIG_IWLWIFI_DEBUG
1126 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1127 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1128 if (inta & CSR_INT_BIT_SCD) {
1129 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1130 "the frame/frames.\n");
1131 priv->isr_stats.sch++;
1132 }
1133
1134 /* Alive notification via Rx interrupt will do the real work */
1135 if (inta & CSR_INT_BIT_ALIVE) {
1136 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1137 priv->isr_stats.alive++;
1138 }
1139 }
1140 #endif
1141 /* Safely ignore these bits for debug checks below */
1142 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1143
1144 /* HW RF KILL switch toggled */
1145 if (inta & CSR_INT_BIT_RF_KILL) {
1146 int hw_rf_kill = 0;
1147 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1148 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1149 hw_rf_kill = 1;
1150
1151 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1152 hw_rf_kill ? "disable radio" : "enable radio");
1153
1154 priv->isr_stats.rfkill++;
1155
1156 /* driver only loads ucode once setting the interface up.
1157 * the driver allows loading the ucode even if the radio
1158 * is killed. Hence update the killswitch state here. The
1159 * rfkill handler will care about restarting if needed.
1160 */
1161 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1162 if (hw_rf_kill)
1163 set_bit(STATUS_RF_KILL_HW, &priv->status);
1164 else
1165 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1166 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1167 }
1168
1169 handled |= CSR_INT_BIT_RF_KILL;
1170 }
1171
1172 /* Chip got too hot and stopped itself */
1173 if (inta & CSR_INT_BIT_CT_KILL) {
1174 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1175 priv->isr_stats.ctkill++;
1176 handled |= CSR_INT_BIT_CT_KILL;
1177 }
1178
1179 /* Error detected by uCode */
1180 if (inta & CSR_INT_BIT_SW_ERR) {
1181 IWL_ERR(priv, "Microcode SW error detected. "
1182 " Restarting 0x%X.\n", inta);
1183 priv->isr_stats.sw++;
1184 priv->isr_stats.sw_err = inta;
1185 iwl_irq_handle_error(priv);
1186 handled |= CSR_INT_BIT_SW_ERR;
1187 }
1188
1189 /*
1190 * uCode wakes up after power-down sleep.
1191 * Tell device about any new tx or host commands enqueued,
1192 * and about any Rx buffers made available while asleep.
1193 */
1194 if (inta & CSR_INT_BIT_WAKEUP) {
1195 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1196 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1197 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1198 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1199 priv->isr_stats.wakeup++;
1200 handled |= CSR_INT_BIT_WAKEUP;
1201 }
1202
1203 /* All uCode command responses, including Tx command responses,
1204 * Rx "responses" (frame-received notification), and other
1205 * notifications from uCode come through here*/
1206 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1207 iwl_rx_handle(priv);
1208 priv->isr_stats.rx++;
1209 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1210 }
1211
1212 /* This "Tx" DMA channel is used only for loading uCode */
1213 if (inta & CSR_INT_BIT_FH_TX) {
1214 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1215 priv->isr_stats.tx++;
1216 handled |= CSR_INT_BIT_FH_TX;
1217 /* Wake up uCode load routine, now that load is complete */
1218 priv->ucode_write_complete = 1;
1219 wake_up_interruptible(&priv->wait_command_queue);
1220 }
1221
1222 if (inta & ~handled) {
1223 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1224 priv->isr_stats.unhandled++;
1225 }
1226
1227 if (inta & ~(priv->inta_mask)) {
1228 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1229 inta & ~priv->inta_mask);
1230 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1231 }
1232
1233 /* Re-enable all interrupts */
1234 /* only Re-enable if diabled by irq */
1235 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1236 iwl_enable_interrupts(priv);
1237
1238 #ifdef CONFIG_IWLWIFI_DEBUG
1239 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1240 inta = iwl_read32(priv, CSR_INT);
1241 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1242 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1243 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1244 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1245 }
1246 #endif
1247 }
1248
1249 /* tasklet for iwlagn interrupt */
1250 static void iwl_irq_tasklet(struct iwl_priv *priv)
1251 {
1252 u32 inta = 0;
1253 u32 handled = 0;
1254 unsigned long flags;
1255 u32 i;
1256 #ifdef CONFIG_IWLWIFI_DEBUG
1257 u32 inta_mask;
1258 #endif
1259
1260 spin_lock_irqsave(&priv->lock, flags);
1261
1262 /* Ack/clear/reset pending uCode interrupts.
1263 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1264 */
1265 /* There is a hardware bug in the interrupt mask function that some
1266 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1267 * they are disabled in the CSR_INT_MASK register. Furthermore the
1268 * ICT interrupt handling mechanism has another bug that might cause
1269 * these unmasked interrupts fail to be detected. We workaround the
1270 * hardware bugs here by ACKing all the possible interrupts so that
1271 * interrupt coalescing can still be achieved.
1272 */
1273 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1274
1275 inta = priv->_agn.inta;
1276
1277 #ifdef CONFIG_IWLWIFI_DEBUG
1278 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1279 /* just for debug */
1280 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1281 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1282 inta, inta_mask);
1283 }
1284 #endif
1285
1286 spin_unlock_irqrestore(&priv->lock, flags);
1287
1288 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1289 priv->_agn.inta = 0;
1290
1291 /* Now service all interrupt bits discovered above. */
1292 if (inta & CSR_INT_BIT_HW_ERR) {
1293 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1294
1295 /* Tell the device to stop sending interrupts */
1296 iwl_disable_interrupts(priv);
1297
1298 priv->isr_stats.hw++;
1299 iwl_irq_handle_error(priv);
1300
1301 handled |= CSR_INT_BIT_HW_ERR;
1302
1303 return;
1304 }
1305
1306 #ifdef CONFIG_IWLWIFI_DEBUG
1307 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1308 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1309 if (inta & CSR_INT_BIT_SCD) {
1310 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1311 "the frame/frames.\n");
1312 priv->isr_stats.sch++;
1313 }
1314
1315 /* Alive notification via Rx interrupt will do the real work */
1316 if (inta & CSR_INT_BIT_ALIVE) {
1317 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1318 priv->isr_stats.alive++;
1319 }
1320 }
1321 #endif
1322 /* Safely ignore these bits for debug checks below */
1323 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1324
1325 /* HW RF KILL switch toggled */
1326 if (inta & CSR_INT_BIT_RF_KILL) {
1327 int hw_rf_kill = 0;
1328 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1329 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1330 hw_rf_kill = 1;
1331
1332 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1333 hw_rf_kill ? "disable radio" : "enable radio");
1334
1335 priv->isr_stats.rfkill++;
1336
1337 /* driver only loads ucode once setting the interface up.
1338 * the driver allows loading the ucode even if the radio
1339 * is killed. Hence update the killswitch state here. The
1340 * rfkill handler will care about restarting if needed.
1341 */
1342 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1343 if (hw_rf_kill)
1344 set_bit(STATUS_RF_KILL_HW, &priv->status);
1345 else
1346 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1347 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1348 }
1349
1350 handled |= CSR_INT_BIT_RF_KILL;
1351 }
1352
1353 /* Chip got too hot and stopped itself */
1354 if (inta & CSR_INT_BIT_CT_KILL) {
1355 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1356 priv->isr_stats.ctkill++;
1357 handled |= CSR_INT_BIT_CT_KILL;
1358 }
1359
1360 /* Error detected by uCode */
1361 if (inta & CSR_INT_BIT_SW_ERR) {
1362 IWL_ERR(priv, "Microcode SW error detected. "
1363 " Restarting 0x%X.\n", inta);
1364 priv->isr_stats.sw++;
1365 priv->isr_stats.sw_err = inta;
1366 iwl_irq_handle_error(priv);
1367 handled |= CSR_INT_BIT_SW_ERR;
1368 }
1369
1370 /* uCode wakes up after power-down sleep */
1371 if (inta & CSR_INT_BIT_WAKEUP) {
1372 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1373 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1374 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1375 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1376
1377 priv->isr_stats.wakeup++;
1378
1379 handled |= CSR_INT_BIT_WAKEUP;
1380 }
1381
1382 /* All uCode command responses, including Tx command responses,
1383 * Rx "responses" (frame-received notification), and other
1384 * notifications from uCode come through here*/
1385 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1386 CSR_INT_BIT_RX_PERIODIC)) {
1387 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1388 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1389 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1390 iwl_write32(priv, CSR_FH_INT_STATUS,
1391 CSR49_FH_INT_RX_MASK);
1392 }
1393 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1394 handled |= CSR_INT_BIT_RX_PERIODIC;
1395 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1396 }
1397 /* Sending RX interrupt require many steps to be done in the
1398 * the device:
1399 * 1- write interrupt to current index in ICT table.
1400 * 2- dma RX frame.
1401 * 3- update RX shared data to indicate last write index.
1402 * 4- send interrupt.
1403 * This could lead to RX race, driver could receive RX interrupt
1404 * but the shared data changes does not reflect this;
1405 * periodic interrupt will detect any dangling Rx activity.
1406 */
1407
1408 /* Disable periodic interrupt; we use it as just a one-shot. */
1409 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1410 CSR_INT_PERIODIC_DIS);
1411 iwl_rx_handle(priv);
1412
1413 /*
1414 * Enable periodic interrupt in 8 msec only if we received
1415 * real RX interrupt (instead of just periodic int), to catch
1416 * any dangling Rx interrupt. If it was just the periodic
1417 * interrupt, there was no dangling Rx activity, and no need
1418 * to extend the periodic interrupt; one-shot is enough.
1419 */
1420 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1421 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1422 CSR_INT_PERIODIC_ENA);
1423
1424 priv->isr_stats.rx++;
1425 }
1426
1427 /* This "Tx" DMA channel is used only for loading uCode */
1428 if (inta & CSR_INT_BIT_FH_TX) {
1429 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1430 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1431 priv->isr_stats.tx++;
1432 handled |= CSR_INT_BIT_FH_TX;
1433 /* Wake up uCode load routine, now that load is complete */
1434 priv->ucode_write_complete = 1;
1435 wake_up_interruptible(&priv->wait_command_queue);
1436 }
1437
1438 if (inta & ~handled) {
1439 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1440 priv->isr_stats.unhandled++;
1441 }
1442
1443 if (inta & ~(priv->inta_mask)) {
1444 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1445 inta & ~priv->inta_mask);
1446 }
1447
1448 /* Re-enable all interrupts */
1449 /* only Re-enable if diabled by irq */
1450 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1451 iwl_enable_interrupts(priv);
1452 }
1453
1454 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1455 #define ACK_CNT_RATIO (50)
1456 #define BA_TIMEOUT_CNT (5)
1457 #define BA_TIMEOUT_MAX (16)
1458
1459 /**
1460 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1461 *
1462 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1463 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1464 * operation state.
1465 */
1466 bool iwl_good_ack_health(struct iwl_priv *priv,
1467 struct iwl_rx_packet *pkt)
1468 {
1469 bool rc = true;
1470 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1471 int ba_timeout_delta;
1472
1473 actual_ack_cnt_delta =
1474 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1475 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1476 expected_ack_cnt_delta =
1477 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1478 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1479 ba_timeout_delta =
1480 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1481 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1482 if ((priv->_agn.agg_tids_count > 0) &&
1483 (expected_ack_cnt_delta > 0) &&
1484 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1485 < ACK_CNT_RATIO) &&
1486 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1487 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1488 " expected_ack_cnt = %d\n",
1489 actual_ack_cnt_delta, expected_ack_cnt_delta);
1490
1491 #ifdef CONFIG_IWLWIFI_DEBUGFS
1492 /*
1493 * This is ifdef'ed on DEBUGFS because otherwise the
1494 * statistics aren't available. If DEBUGFS is set but
1495 * DEBUG is not, these will just compile out.
1496 */
1497 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1498 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1499 IWL_DEBUG_RADIO(priv,
1500 "ack_or_ba_timeout_collision delta = %d\n",
1501 priv->_agn.delta_statistics.tx.
1502 ack_or_ba_timeout_collision);
1503 #endif
1504 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1505 ba_timeout_delta);
1506 if (!actual_ack_cnt_delta &&
1507 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1508 rc = false;
1509 }
1510 return rc;
1511 }
1512
1513
1514 /*****************************************************************************
1515 *
1516 * sysfs attributes
1517 *
1518 *****************************************************************************/
1519
1520 #ifdef CONFIG_IWLWIFI_DEBUG
1521
1522 /*
1523 * The following adds a new attribute to the sysfs representation
1524 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1525 * used for controlling the debug level.
1526 *
1527 * See the level definitions in iwl for details.
1528 *
1529 * The debug_level being managed using sysfs below is a per device debug
1530 * level that is used instead of the global debug level if it (the per
1531 * device debug level) is set.
1532 */
1533 static ssize_t show_debug_level(struct device *d,
1534 struct device_attribute *attr, char *buf)
1535 {
1536 struct iwl_priv *priv = dev_get_drvdata(d);
1537 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1538 }
1539 static ssize_t store_debug_level(struct device *d,
1540 struct device_attribute *attr,
1541 const char *buf, size_t count)
1542 {
1543 struct iwl_priv *priv = dev_get_drvdata(d);
1544 unsigned long val;
1545 int ret;
1546
1547 ret = strict_strtoul(buf, 0, &val);
1548 if (ret)
1549 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1550 else {
1551 priv->debug_level = val;
1552 if (iwl_alloc_traffic_mem(priv))
1553 IWL_ERR(priv,
1554 "Not enough memory to generate traffic log\n");
1555 }
1556 return strnlen(buf, count);
1557 }
1558
1559 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1560 show_debug_level, store_debug_level);
1561
1562
1563 #endif /* CONFIG_IWLWIFI_DEBUG */
1564
1565
1566 static ssize_t show_temperature(struct device *d,
1567 struct device_attribute *attr, char *buf)
1568 {
1569 struct iwl_priv *priv = dev_get_drvdata(d);
1570
1571 if (!iwl_is_alive(priv))
1572 return -EAGAIN;
1573
1574 return sprintf(buf, "%d\n", priv->temperature);
1575 }
1576
1577 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1578
1579 static ssize_t show_tx_power(struct device *d,
1580 struct device_attribute *attr, char *buf)
1581 {
1582 struct iwl_priv *priv = dev_get_drvdata(d);
1583
1584 if (!iwl_is_ready_rf(priv))
1585 return sprintf(buf, "off\n");
1586 else
1587 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1588 }
1589
1590 static ssize_t store_tx_power(struct device *d,
1591 struct device_attribute *attr,
1592 const char *buf, size_t count)
1593 {
1594 struct iwl_priv *priv = dev_get_drvdata(d);
1595 unsigned long val;
1596 int ret;
1597
1598 ret = strict_strtoul(buf, 10, &val);
1599 if (ret)
1600 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1601 else {
1602 ret = iwl_set_tx_power(priv, val, false);
1603 if (ret)
1604 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1605 ret);
1606 else
1607 ret = count;
1608 }
1609 return ret;
1610 }
1611
1612 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1613
1614 static struct attribute *iwl_sysfs_entries[] = {
1615 &dev_attr_temperature.attr,
1616 &dev_attr_tx_power.attr,
1617 #ifdef CONFIG_IWLWIFI_DEBUG
1618 &dev_attr_debug_level.attr,
1619 #endif
1620 NULL
1621 };
1622
1623 static struct attribute_group iwl_attribute_group = {
1624 .name = NULL, /* put in device directory */
1625 .attrs = iwl_sysfs_entries,
1626 };
1627
1628 /******************************************************************************
1629 *
1630 * uCode download functions
1631 *
1632 ******************************************************************************/
1633
1634 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1635 {
1636 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1637 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1638 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1639 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1640 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1641 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1642 }
1643
1644 static void iwl_nic_start(struct iwl_priv *priv)
1645 {
1646 /* Remove all resets to allow NIC to operate */
1647 iwl_write32(priv, CSR_RESET, 0);
1648 }
1649
1650 struct iwlagn_ucode_capabilities {
1651 u32 max_probe_length;
1652 u32 standard_phy_calibration_size;
1653 };
1654
1655 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1656 static int iwl_mac_setup_register(struct iwl_priv *priv,
1657 struct iwlagn_ucode_capabilities *capa);
1658
1659 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1660 {
1661 const char *name_pre = priv->cfg->fw_name_pre;
1662
1663 if (first)
1664 priv->fw_index = priv->cfg->ucode_api_max;
1665 else
1666 priv->fw_index--;
1667
1668 if (priv->fw_index < priv->cfg->ucode_api_min) {
1669 IWL_ERR(priv, "no suitable firmware found!\n");
1670 return -ENOENT;
1671 }
1672
1673 sprintf(priv->firmware_name, "%s%d%s",
1674 name_pre, priv->fw_index, ".ucode");
1675
1676 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1677 priv->firmware_name);
1678
1679 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1680 &priv->pci_dev->dev, GFP_KERNEL, priv,
1681 iwl_ucode_callback);
1682 }
1683
1684 struct iwlagn_firmware_pieces {
1685 const void *inst, *data, *init, *init_data, *boot;
1686 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1687
1688 u32 build;
1689
1690 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1691 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1692 };
1693
1694 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1695 const struct firmware *ucode_raw,
1696 struct iwlagn_firmware_pieces *pieces)
1697 {
1698 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1699 u32 api_ver, hdr_size;
1700 const u8 *src;
1701
1702 priv->ucode_ver = le32_to_cpu(ucode->ver);
1703 api_ver = IWL_UCODE_API(priv->ucode_ver);
1704
1705 switch (api_ver) {
1706 default:
1707 /*
1708 * 4965 doesn't revision the firmware file format
1709 * along with the API version, it always uses v1
1710 * file format.
1711 */
1712 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1713 CSR_HW_REV_TYPE_4965) {
1714 hdr_size = 28;
1715 if (ucode_raw->size < hdr_size) {
1716 IWL_ERR(priv, "File size too small!\n");
1717 return -EINVAL;
1718 }
1719 pieces->build = le32_to_cpu(ucode->u.v2.build);
1720 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1721 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1722 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1723 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1724 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1725 src = ucode->u.v2.data;
1726 break;
1727 }
1728 /* fall through for 4965 */
1729 case 0:
1730 case 1:
1731 case 2:
1732 hdr_size = 24;
1733 if (ucode_raw->size < hdr_size) {
1734 IWL_ERR(priv, "File size too small!\n");
1735 return -EINVAL;
1736 }
1737 pieces->build = 0;
1738 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1739 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1740 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1741 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1742 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1743 src = ucode->u.v1.data;
1744 break;
1745 }
1746
1747 /* Verify size of file vs. image size info in file's header */
1748 if (ucode_raw->size != hdr_size + pieces->inst_size +
1749 pieces->data_size + pieces->init_size +
1750 pieces->init_data_size + pieces->boot_size) {
1751
1752 IWL_ERR(priv,
1753 "uCode file size %d does not match expected size\n",
1754 (int)ucode_raw->size);
1755 return -EINVAL;
1756 }
1757
1758 pieces->inst = src;
1759 src += pieces->inst_size;
1760 pieces->data = src;
1761 src += pieces->data_size;
1762 pieces->init = src;
1763 src += pieces->init_size;
1764 pieces->init_data = src;
1765 src += pieces->init_data_size;
1766 pieces->boot = src;
1767 src += pieces->boot_size;
1768
1769 return 0;
1770 }
1771
1772 static int iwlagn_wanted_ucode_alternative = 1;
1773
1774 static int iwlagn_load_firmware(struct iwl_priv *priv,
1775 const struct firmware *ucode_raw,
1776 struct iwlagn_firmware_pieces *pieces,
1777 struct iwlagn_ucode_capabilities *capa)
1778 {
1779 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1780 struct iwl_ucode_tlv *tlv;
1781 size_t len = ucode_raw->size;
1782 const u8 *data;
1783 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1784 u64 alternatives;
1785 u32 tlv_len;
1786 enum iwl_ucode_tlv_type tlv_type;
1787 const u8 *tlv_data;
1788
1789 if (len < sizeof(*ucode)) {
1790 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1791 return -EINVAL;
1792 }
1793
1794 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1795 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1796 le32_to_cpu(ucode->magic));
1797 return -EINVAL;
1798 }
1799
1800 /*
1801 * Check which alternatives are present, and "downgrade"
1802 * when the chosen alternative is not present, warning
1803 * the user when that happens. Some files may not have
1804 * any alternatives, so don't warn in that case.
1805 */
1806 alternatives = le64_to_cpu(ucode->alternatives);
1807 tmp = wanted_alternative;
1808 if (wanted_alternative > 63)
1809 wanted_alternative = 63;
1810 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1811 wanted_alternative--;
1812 if (wanted_alternative && wanted_alternative != tmp)
1813 IWL_WARN(priv,
1814 "uCode alternative %d not available, choosing %d\n",
1815 tmp, wanted_alternative);
1816
1817 priv->ucode_ver = le32_to_cpu(ucode->ver);
1818 pieces->build = le32_to_cpu(ucode->build);
1819 data = ucode->data;
1820
1821 len -= sizeof(*ucode);
1822
1823 while (len >= sizeof(*tlv)) {
1824 u16 tlv_alt;
1825
1826 len -= sizeof(*tlv);
1827 tlv = (void *)data;
1828
1829 tlv_len = le32_to_cpu(tlv->length);
1830 tlv_type = le16_to_cpu(tlv->type);
1831 tlv_alt = le16_to_cpu(tlv->alternative);
1832 tlv_data = tlv->data;
1833
1834 if (len < tlv_len) {
1835 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1836 len, tlv_len);
1837 return -EINVAL;
1838 }
1839 len -= ALIGN(tlv_len, 4);
1840 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1841
1842 /*
1843 * Alternative 0 is always valid.
1844 *
1845 * Skip alternative TLVs that are not selected.
1846 */
1847 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1848 continue;
1849
1850 switch (tlv_type) {
1851 case IWL_UCODE_TLV_INST:
1852 pieces->inst = tlv_data;
1853 pieces->inst_size = tlv_len;
1854 break;
1855 case IWL_UCODE_TLV_DATA:
1856 pieces->data = tlv_data;
1857 pieces->data_size = tlv_len;
1858 break;
1859 case IWL_UCODE_TLV_INIT:
1860 pieces->init = tlv_data;
1861 pieces->init_size = tlv_len;
1862 break;
1863 case IWL_UCODE_TLV_INIT_DATA:
1864 pieces->init_data = tlv_data;
1865 pieces->init_data_size = tlv_len;
1866 break;
1867 case IWL_UCODE_TLV_BOOT:
1868 pieces->boot = tlv_data;
1869 pieces->boot_size = tlv_len;
1870 break;
1871 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1872 if (tlv_len != sizeof(u32))
1873 goto invalid_tlv_len;
1874 capa->max_probe_length =
1875 le32_to_cpup((__le32 *)tlv_data);
1876 break;
1877 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1878 if (tlv_len != sizeof(u32))
1879 goto invalid_tlv_len;
1880 pieces->init_evtlog_ptr =
1881 le32_to_cpup((__le32 *)tlv_data);
1882 break;
1883 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1884 if (tlv_len != sizeof(u32))
1885 goto invalid_tlv_len;
1886 pieces->init_evtlog_size =
1887 le32_to_cpup((__le32 *)tlv_data);
1888 break;
1889 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1890 if (tlv_len != sizeof(u32))
1891 goto invalid_tlv_len;
1892 pieces->init_errlog_ptr =
1893 le32_to_cpup((__le32 *)tlv_data);
1894 break;
1895 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1896 if (tlv_len != sizeof(u32))
1897 goto invalid_tlv_len;
1898 pieces->inst_evtlog_ptr =
1899 le32_to_cpup((__le32 *)tlv_data);
1900 break;
1901 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1902 if (tlv_len != sizeof(u32))
1903 goto invalid_tlv_len;
1904 pieces->inst_evtlog_size =
1905 le32_to_cpup((__le32 *)tlv_data);
1906 break;
1907 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1908 if (tlv_len != sizeof(u32))
1909 goto invalid_tlv_len;
1910 pieces->inst_errlog_ptr =
1911 le32_to_cpup((__le32 *)tlv_data);
1912 break;
1913 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1914 if (tlv_len)
1915 goto invalid_tlv_len;
1916 priv->enhance_sensitivity_table = true;
1917 break;
1918 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1919 if (tlv_len != sizeof(u32))
1920 goto invalid_tlv_len;
1921 capa->standard_phy_calibration_size =
1922 le32_to_cpup((__le32 *)tlv_data);
1923 break;
1924 default:
1925 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1926 break;
1927 }
1928 }
1929
1930 if (len) {
1931 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1932 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1933 return -EINVAL;
1934 }
1935
1936 return 0;
1937
1938 invalid_tlv_len:
1939 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1940 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1941
1942 return -EINVAL;
1943 }
1944
1945 /**
1946 * iwl_ucode_callback - callback when firmware was loaded
1947 *
1948 * If loaded successfully, copies the firmware into buffers
1949 * for the card to fetch (via DMA).
1950 */
1951 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1952 {
1953 struct iwl_priv *priv = context;
1954 struct iwl_ucode_header *ucode;
1955 int err;
1956 struct iwlagn_firmware_pieces pieces;
1957 const unsigned int api_max = priv->cfg->ucode_api_max;
1958 const unsigned int api_min = priv->cfg->ucode_api_min;
1959 u32 api_ver;
1960 char buildstr[25];
1961 u32 build;
1962 struct iwlagn_ucode_capabilities ucode_capa = {
1963 .max_probe_length = 200,
1964 .standard_phy_calibration_size =
1965 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1966 };
1967
1968 memset(&pieces, 0, sizeof(pieces));
1969
1970 if (!ucode_raw) {
1971 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
1972 priv->firmware_name);
1973 goto try_again;
1974 }
1975
1976 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1977 priv->firmware_name, ucode_raw->size);
1978
1979 /* Make sure that we got at least the API version number */
1980 if (ucode_raw->size < 4) {
1981 IWL_ERR(priv, "File size way too small!\n");
1982 goto try_again;
1983 }
1984
1985 /* Data from ucode file: header followed by uCode images */
1986 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1987
1988 if (ucode->ver)
1989 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1990 else
1991 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1992 &ucode_capa);
1993
1994 if (err)
1995 goto try_again;
1996
1997 api_ver = IWL_UCODE_API(priv->ucode_ver);
1998 build = pieces.build;
1999
2000 /*
2001 * api_ver should match the api version forming part of the
2002 * firmware filename ... but we don't check for that and only rely
2003 * on the API version read from firmware header from here on forward
2004 */
2005 if (api_ver < api_min || api_ver > api_max) {
2006 IWL_ERR(priv, "Driver unable to support your firmware API. "
2007 "Driver supports v%u, firmware is v%u.\n",
2008 api_max, api_ver);
2009 goto try_again;
2010 }
2011
2012 if (api_ver != api_max)
2013 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2014 "got v%u. New firmware can be obtained "
2015 "from http://www.intellinuxwireless.org.\n",
2016 api_max, api_ver);
2017
2018 if (build)
2019 sprintf(buildstr, " build %u", build);
2020 else
2021 buildstr[0] = '\0';
2022
2023 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2024 IWL_UCODE_MAJOR(priv->ucode_ver),
2025 IWL_UCODE_MINOR(priv->ucode_ver),
2026 IWL_UCODE_API(priv->ucode_ver),
2027 IWL_UCODE_SERIAL(priv->ucode_ver),
2028 buildstr);
2029
2030 snprintf(priv->hw->wiphy->fw_version,
2031 sizeof(priv->hw->wiphy->fw_version),
2032 "%u.%u.%u.%u%s",
2033 IWL_UCODE_MAJOR(priv->ucode_ver),
2034 IWL_UCODE_MINOR(priv->ucode_ver),
2035 IWL_UCODE_API(priv->ucode_ver),
2036 IWL_UCODE_SERIAL(priv->ucode_ver),
2037 buildstr);
2038
2039 /*
2040 * For any of the failures below (before allocating pci memory)
2041 * we will try to load a version with a smaller API -- maybe the
2042 * user just got a corrupted version of the latest API.
2043 */
2044
2045 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2046 priv->ucode_ver);
2047 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2048 pieces.inst_size);
2049 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2050 pieces.data_size);
2051 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2052 pieces.init_size);
2053 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2054 pieces.init_data_size);
2055 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2056 pieces.boot_size);
2057
2058 /* Verify that uCode images will fit in card's SRAM */
2059 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2060 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2061 pieces.inst_size);
2062 goto try_again;
2063 }
2064
2065 if (pieces.data_size > priv->hw_params.max_data_size) {
2066 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2067 pieces.data_size);
2068 goto try_again;
2069 }
2070
2071 if (pieces.init_size > priv->hw_params.max_inst_size) {
2072 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2073 pieces.init_size);
2074 goto try_again;
2075 }
2076
2077 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2078 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2079 pieces.init_data_size);
2080 goto try_again;
2081 }
2082
2083 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2084 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2085 pieces.boot_size);
2086 goto try_again;
2087 }
2088
2089 /* Allocate ucode buffers for card's bus-master loading ... */
2090
2091 /* Runtime instructions and 2 copies of data:
2092 * 1) unmodified from disk
2093 * 2) backup cache for save/restore during power-downs */
2094 priv->ucode_code.len = pieces.inst_size;
2095 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2096
2097 priv->ucode_data.len = pieces.data_size;
2098 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2099
2100 priv->ucode_data_backup.len = pieces.data_size;
2101 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2102
2103 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2104 !priv->ucode_data_backup.v_addr)
2105 goto err_pci_alloc;
2106
2107 /* Initialization instructions and data */
2108 if (pieces.init_size && pieces.init_data_size) {
2109 priv->ucode_init.len = pieces.init_size;
2110 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2111
2112 priv->ucode_init_data.len = pieces.init_data_size;
2113 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2114
2115 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2116 goto err_pci_alloc;
2117 }
2118
2119 /* Bootstrap (instructions only, no data) */
2120 if (pieces.boot_size) {
2121 priv->ucode_boot.len = pieces.boot_size;
2122 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2123
2124 if (!priv->ucode_boot.v_addr)
2125 goto err_pci_alloc;
2126 }
2127
2128 /* Now that we can no longer fail, copy information */
2129
2130 /*
2131 * The (size - 16) / 12 formula is based on the information recorded
2132 * for each event, which is of mode 1 (including timestamp) for all
2133 * new microcodes that include this information.
2134 */
2135 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2136 if (pieces.init_evtlog_size)
2137 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2138 else
2139 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2140 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2141 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2142 if (pieces.inst_evtlog_size)
2143 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2144 else
2145 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2146 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2147
2148 /* Copy images into buffers for card's bus-master reads ... */
2149
2150 /* Runtime instructions (first block of data in file) */
2151 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2152 pieces.inst_size);
2153 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2154
2155 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2156 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2157
2158 /*
2159 * Runtime data
2160 * NOTE: Copy into backup buffer will be done in iwl_up()
2161 */
2162 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2163 pieces.data_size);
2164 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2165 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2166
2167 /* Initialization instructions */
2168 if (pieces.init_size) {
2169 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2170 pieces.init_size);
2171 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2172 }
2173
2174 /* Initialization data */
2175 if (pieces.init_data_size) {
2176 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2177 pieces.init_data_size);
2178 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2179 pieces.init_data_size);
2180 }
2181
2182 /* Bootstrap instructions */
2183 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2184 pieces.boot_size);
2185 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2186
2187 /*
2188 * figure out the offset of chain noise reset and gain commands
2189 * base on the size of standard phy calibration commands table size
2190 */
2191 if (ucode_capa.standard_phy_calibration_size >
2192 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2193 ucode_capa.standard_phy_calibration_size =
2194 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2195
2196 priv->_agn.phy_calib_chain_noise_reset_cmd =
2197 ucode_capa.standard_phy_calibration_size;
2198 priv->_agn.phy_calib_chain_noise_gain_cmd =
2199 ucode_capa.standard_phy_calibration_size + 1;
2200
2201 /**************************************************
2202 * This is still part of probe() in a sense...
2203 *
2204 * 9. Setup and register with mac80211 and debugfs
2205 **************************************************/
2206 err = iwl_mac_setup_register(priv, &ucode_capa);
2207 if (err)
2208 goto out_unbind;
2209
2210 err = iwl_dbgfs_register(priv, DRV_NAME);
2211 if (err)
2212 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2213
2214 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2215 &iwl_attribute_group);
2216 if (err) {
2217 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2218 goto out_unbind;
2219 }
2220
2221 /* We have our copies now, allow OS release its copies */
2222 release_firmware(ucode_raw);
2223 complete(&priv->_agn.firmware_loading_complete);
2224 return;
2225
2226 try_again:
2227 /* try next, if any */
2228 if (iwl_request_firmware(priv, false))
2229 goto out_unbind;
2230 release_firmware(ucode_raw);
2231 return;
2232
2233 err_pci_alloc:
2234 IWL_ERR(priv, "failed to allocate pci memory\n");
2235 iwl_dealloc_ucode_pci(priv);
2236 out_unbind:
2237 complete(&priv->_agn.firmware_loading_complete);
2238 device_release_driver(&priv->pci_dev->dev);
2239 release_firmware(ucode_raw);
2240 }
2241
2242 static const char *desc_lookup_text[] = {
2243 "OK",
2244 "FAIL",
2245 "BAD_PARAM",
2246 "BAD_CHECKSUM",
2247 "NMI_INTERRUPT_WDG",
2248 "SYSASSERT",
2249 "FATAL_ERROR",
2250 "BAD_COMMAND",
2251 "HW_ERROR_TUNE_LOCK",
2252 "HW_ERROR_TEMPERATURE",
2253 "ILLEGAL_CHAN_FREQ",
2254 "VCC_NOT_STABLE",
2255 "FH_ERROR",
2256 "NMI_INTERRUPT_HOST",
2257 "NMI_INTERRUPT_ACTION_PT",
2258 "NMI_INTERRUPT_UNKNOWN",
2259 "UCODE_VERSION_MISMATCH",
2260 "HW_ERROR_ABS_LOCK",
2261 "HW_ERROR_CAL_LOCK_FAIL",
2262 "NMI_INTERRUPT_INST_ACTION_PT",
2263 "NMI_INTERRUPT_DATA_ACTION_PT",
2264 "NMI_TRM_HW_ER",
2265 "NMI_INTERRUPT_TRM",
2266 "NMI_INTERRUPT_BREAK_POINT"
2267 "DEBUG_0",
2268 "DEBUG_1",
2269 "DEBUG_2",
2270 "DEBUG_3",
2271 };
2272
2273 static struct { char *name; u8 num; } advanced_lookup[] = {
2274 { "NMI_INTERRUPT_WDG", 0x34 },
2275 { "SYSASSERT", 0x35 },
2276 { "UCODE_VERSION_MISMATCH", 0x37 },
2277 { "BAD_COMMAND", 0x38 },
2278 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2279 { "FATAL_ERROR", 0x3D },
2280 { "NMI_TRM_HW_ERR", 0x46 },
2281 { "NMI_INTERRUPT_TRM", 0x4C },
2282 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2283 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2284 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2285 { "NMI_INTERRUPT_HOST", 0x66 },
2286 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2287 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2288 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2289 { "ADVANCED_SYSASSERT", 0 },
2290 };
2291
2292 static const char *desc_lookup(u32 num)
2293 {
2294 int i;
2295 int max = ARRAY_SIZE(desc_lookup_text);
2296
2297 if (num < max)
2298 return desc_lookup_text[num];
2299
2300 max = ARRAY_SIZE(advanced_lookup) - 1;
2301 for (i = 0; i < max; i++) {
2302 if (advanced_lookup[i].num == num)
2303 break;;
2304 }
2305 return advanced_lookup[i].name;
2306 }
2307
2308 #define ERROR_START_OFFSET (1 * sizeof(u32))
2309 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
2310
2311 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2312 {
2313 u32 data2, line;
2314 u32 desc, time, count, base, data1;
2315 u32 blink1, blink2, ilink1, ilink2;
2316 u32 pc, hcmd;
2317
2318 if (priv->ucode_type == UCODE_INIT) {
2319 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2320 if (!base)
2321 base = priv->_agn.init_errlog_ptr;
2322 } else {
2323 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2324 if (!base)
2325 base = priv->_agn.inst_errlog_ptr;
2326 }
2327
2328 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2329 IWL_ERR(priv,
2330 "Not valid error log pointer 0x%08X for %s uCode\n",
2331 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2332 return;
2333 }
2334
2335 count = iwl_read_targ_mem(priv, base);
2336
2337 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2338 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2339 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2340 priv->status, count);
2341 }
2342
2343 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2344 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2345 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2346 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2347 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2348 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2349 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2350 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2351 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2352 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2353 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2354
2355 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2356 blink1, blink2, ilink1, ilink2);
2357
2358 IWL_ERR(priv, "Desc Time "
2359 "data1 data2 line\n");
2360 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2361 desc_lookup(desc), desc, time, data1, data2, line);
2362 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2363 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2364 pc, blink1, blink2, ilink1, ilink2, hcmd);
2365 }
2366
2367 #define EVENT_START_OFFSET (4 * sizeof(u32))
2368
2369 /**
2370 * iwl_print_event_log - Dump error event log to syslog
2371 *
2372 */
2373 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2374 u32 num_events, u32 mode,
2375 int pos, char **buf, size_t bufsz)
2376 {
2377 u32 i;
2378 u32 base; /* SRAM byte address of event log header */
2379 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2380 u32 ptr; /* SRAM byte address of log data */
2381 u32 ev, time, data; /* event log data */
2382 unsigned long reg_flags;
2383
2384 if (num_events == 0)
2385 return pos;
2386
2387 if (priv->ucode_type == UCODE_INIT) {
2388 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2389 if (!base)
2390 base = priv->_agn.init_evtlog_ptr;
2391 } else {
2392 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2393 if (!base)
2394 base = priv->_agn.inst_evtlog_ptr;
2395 }
2396
2397 if (mode == 0)
2398 event_size = 2 * sizeof(u32);
2399 else
2400 event_size = 3 * sizeof(u32);
2401
2402 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2403
2404 /* Make sure device is powered up for SRAM reads */
2405 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2406 iwl_grab_nic_access(priv);
2407
2408 /* Set starting address; reads will auto-increment */
2409 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2410 rmb();
2411
2412 /* "time" is actually "data" for mode 0 (no timestamp).
2413 * place event id # at far right for easier visual parsing. */
2414 for (i = 0; i < num_events; i++) {
2415 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2416 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2417 if (mode == 0) {
2418 /* data, ev */
2419 if (bufsz) {
2420 pos += scnprintf(*buf + pos, bufsz - pos,
2421 "EVT_LOG:0x%08x:%04u\n",
2422 time, ev);
2423 } else {
2424 trace_iwlwifi_dev_ucode_event(priv, 0,
2425 time, ev);
2426 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2427 time, ev);
2428 }
2429 } else {
2430 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2431 if (bufsz) {
2432 pos += scnprintf(*buf + pos, bufsz - pos,
2433 "EVT_LOGT:%010u:0x%08x:%04u\n",
2434 time, data, ev);
2435 } else {
2436 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2437 time, data, ev);
2438 trace_iwlwifi_dev_ucode_event(priv, time,
2439 data, ev);
2440 }
2441 }
2442 }
2443
2444 /* Allow device to power down */
2445 iwl_release_nic_access(priv);
2446 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2447 return pos;
2448 }
2449
2450 /**
2451 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2452 */
2453 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2454 u32 num_wraps, u32 next_entry,
2455 u32 size, u32 mode,
2456 int pos, char **buf, size_t bufsz)
2457 {
2458 /*
2459 * display the newest DEFAULT_LOG_ENTRIES entries
2460 * i.e the entries just before the next ont that uCode would fill.
2461 */
2462 if (num_wraps) {
2463 if (next_entry < size) {
2464 pos = iwl_print_event_log(priv,
2465 capacity - (size - next_entry),
2466 size - next_entry, mode,
2467 pos, buf, bufsz);
2468 pos = iwl_print_event_log(priv, 0,
2469 next_entry, mode,
2470 pos, buf, bufsz);
2471 } else
2472 pos = iwl_print_event_log(priv, next_entry - size,
2473 size, mode, pos, buf, bufsz);
2474 } else {
2475 if (next_entry < size) {
2476 pos = iwl_print_event_log(priv, 0, next_entry,
2477 mode, pos, buf, bufsz);
2478 } else {
2479 pos = iwl_print_event_log(priv, next_entry - size,
2480 size, mode, pos, buf, bufsz);
2481 }
2482 }
2483 return pos;
2484 }
2485
2486 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2487
2488 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2489 char **buf, bool display)
2490 {
2491 u32 base; /* SRAM byte address of event log header */
2492 u32 capacity; /* event log capacity in # entries */
2493 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2494 u32 num_wraps; /* # times uCode wrapped to top of log */
2495 u32 next_entry; /* index of next entry to be written by uCode */
2496 u32 size; /* # entries that we'll print */
2497 u32 logsize;
2498 int pos = 0;
2499 size_t bufsz = 0;
2500
2501 if (priv->ucode_type == UCODE_INIT) {
2502 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2503 logsize = priv->_agn.init_evtlog_size;
2504 if (!base)
2505 base = priv->_agn.init_evtlog_ptr;
2506 } else {
2507 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2508 logsize = priv->_agn.inst_evtlog_size;
2509 if (!base)
2510 base = priv->_agn.inst_evtlog_ptr;
2511 }
2512
2513 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2514 IWL_ERR(priv,
2515 "Invalid event log pointer 0x%08X for %s uCode\n",
2516 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2517 return -EINVAL;
2518 }
2519
2520 /* event log header */
2521 capacity = iwl_read_targ_mem(priv, base);
2522 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2523 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2524 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2525
2526 if (capacity > logsize) {
2527 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2528 capacity, logsize);
2529 capacity = logsize;
2530 }
2531
2532 if (next_entry > logsize) {
2533 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2534 next_entry, logsize);
2535 next_entry = logsize;
2536 }
2537
2538 size = num_wraps ? capacity : next_entry;
2539
2540 /* bail out if nothing in log */
2541 if (size == 0) {
2542 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2543 return pos;
2544 }
2545
2546 #ifdef CONFIG_IWLWIFI_DEBUG
2547 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2548 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2549 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2550 #else
2551 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2552 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2553 #endif
2554 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2555 size);
2556
2557 #ifdef CONFIG_IWLWIFI_DEBUG
2558 if (display) {
2559 if (full_log)
2560 bufsz = capacity * 48;
2561 else
2562 bufsz = size * 48;
2563 *buf = kmalloc(bufsz, GFP_KERNEL);
2564 if (!*buf)
2565 return -ENOMEM;
2566 }
2567 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2568 /*
2569 * if uCode has wrapped back to top of log,
2570 * start at the oldest entry,
2571 * i.e the next one that uCode would fill.
2572 */
2573 if (num_wraps)
2574 pos = iwl_print_event_log(priv, next_entry,
2575 capacity - next_entry, mode,
2576 pos, buf, bufsz);
2577 /* (then/else) start at top of log */
2578 pos = iwl_print_event_log(priv, 0,
2579 next_entry, mode, pos, buf, bufsz);
2580 } else
2581 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2582 next_entry, size, mode,
2583 pos, buf, bufsz);
2584 #else
2585 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2586 next_entry, size, mode,
2587 pos, buf, bufsz);
2588 #endif
2589 return pos;
2590 }
2591
2592 /**
2593 * iwl_alive_start - called after REPLY_ALIVE notification received
2594 * from protocol/runtime uCode (initialization uCode's
2595 * Alive gets handled by iwl_init_alive_start()).
2596 */
2597 static void iwl_alive_start(struct iwl_priv *priv)
2598 {
2599 int ret = 0;
2600
2601 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2602
2603 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2604 /* We had an error bringing up the hardware, so take it
2605 * all the way back down so we can try again */
2606 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2607 goto restart;
2608 }
2609
2610 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2611 * This is a paranoid check, because we would not have gotten the
2612 * "runtime" alive if code weren't properly loaded. */
2613 if (iwl_verify_ucode(priv)) {
2614 /* Runtime instruction load was bad;
2615 * take it all the way back down so we can try again */
2616 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2617 goto restart;
2618 }
2619
2620 ret = priv->cfg->ops->lib->alive_notify(priv);
2621 if (ret) {
2622 IWL_WARN(priv,
2623 "Could not complete ALIVE transition [ntf]: %d\n", ret);
2624 goto restart;
2625 }
2626
2627 /* After the ALIVE response, we can send host commands to the uCode */
2628 set_bit(STATUS_ALIVE, &priv->status);
2629
2630 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2631 /* Enable timer to monitor the driver queues */
2632 mod_timer(&priv->monitor_recover,
2633 jiffies +
2634 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2635 }
2636
2637 if (iwl_is_rfkill(priv))
2638 return;
2639
2640 ieee80211_wake_queues(priv->hw);
2641
2642 priv->active_rate = IWL_RATES_MASK;
2643
2644 /* Configure Tx antenna selection based on H/W config */
2645 if (priv->cfg->ops->hcmd->set_tx_ant)
2646 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2647
2648 if (iwl_is_associated(priv)) {
2649 struct iwl_rxon_cmd *active_rxon =
2650 (struct iwl_rxon_cmd *)&priv->active_rxon;
2651 /* apply any changes in staging */
2652 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2653 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2654 } else {
2655 /* Initialize our rx_config data */
2656 iwl_connection_init_rx_config(priv, NULL);
2657
2658 if (priv->cfg->ops->hcmd->set_rxon_chain)
2659 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2660 }
2661
2662 /* Configure Bluetooth device coexistence support */
2663 priv->cfg->ops->hcmd->send_bt_config(priv);
2664
2665 iwl_reset_run_time_calib(priv);
2666
2667 /* Configure the adapter for unassociated operation */
2668 iwlcore_commit_rxon(priv);
2669
2670 /* At this point, the NIC is initialized and operational */
2671 iwl_rf_kill_ct_config(priv);
2672
2673 iwl_leds_init(priv);
2674
2675 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2676 set_bit(STATUS_READY, &priv->status);
2677 wake_up_interruptible(&priv->wait_command_queue);
2678
2679 iwl_power_update_mode(priv, true);
2680 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2681
2682
2683 return;
2684
2685 restart:
2686 queue_work(priv->workqueue, &priv->restart);
2687 }
2688
2689 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2690
2691 static void __iwl_down(struct iwl_priv *priv)
2692 {
2693 unsigned long flags;
2694 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2695
2696 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2697
2698 if (!exit_pending)
2699 set_bit(STATUS_EXIT_PENDING, &priv->status);
2700
2701 iwl_clear_ucode_stations(priv);
2702 iwl_dealloc_bcast_station(priv);
2703 iwl_clear_driver_stations(priv);
2704
2705 /* Unblock any waiting calls */
2706 wake_up_interruptible_all(&priv->wait_command_queue);
2707
2708 /* Wipe out the EXIT_PENDING status bit if we are not actually
2709 * exiting the module */
2710 if (!exit_pending)
2711 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2712
2713 /* stop and reset the on-board processor */
2714 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2715
2716 /* tell the device to stop sending interrupts */
2717 spin_lock_irqsave(&priv->lock, flags);
2718 iwl_disable_interrupts(priv);
2719 spin_unlock_irqrestore(&priv->lock, flags);
2720 iwl_synchronize_irq(priv);
2721
2722 if (priv->mac80211_registered)
2723 ieee80211_stop_queues(priv->hw);
2724
2725 /* If we have not previously called iwl_init() then
2726 * clear all bits but the RF Kill bit and return */
2727 if (!iwl_is_init(priv)) {
2728 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2729 STATUS_RF_KILL_HW |
2730 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2731 STATUS_GEO_CONFIGURED |
2732 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2733 STATUS_EXIT_PENDING;
2734 goto exit;
2735 }
2736
2737 /* ...otherwise clear out all the status bits but the RF Kill
2738 * bit and continue taking the NIC down. */
2739 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2740 STATUS_RF_KILL_HW |
2741 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2742 STATUS_GEO_CONFIGURED |
2743 test_bit(STATUS_FW_ERROR, &priv->status) <<
2744 STATUS_FW_ERROR |
2745 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2746 STATUS_EXIT_PENDING;
2747
2748 /* device going down, Stop using ICT table */
2749 iwl_disable_ict(priv);
2750
2751 iwlagn_txq_ctx_stop(priv);
2752 iwlagn_rxq_stop(priv);
2753
2754 /* Power-down device's busmaster DMA clocks */
2755 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2756 udelay(5);
2757
2758 /* Make sure (redundant) we've released our request to stay awake */
2759 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2760
2761 /* Stop the device, and put it in low power state */
2762 priv->cfg->ops->lib->apm_ops.stop(priv);
2763
2764 exit:
2765 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2766
2767 if (priv->ibss_beacon)
2768 dev_kfree_skb(priv->ibss_beacon);
2769 priv->ibss_beacon = NULL;
2770
2771 /* clear out any free frames */
2772 iwl_clear_free_frames(priv);
2773 }
2774
2775 static void iwl_down(struct iwl_priv *priv)
2776 {
2777 mutex_lock(&priv->mutex);
2778 __iwl_down(priv);
2779 mutex_unlock(&priv->mutex);
2780
2781 iwl_cancel_deferred_work(priv);
2782 }
2783
2784 #define HW_READY_TIMEOUT (50)
2785
2786 static int iwl_set_hw_ready(struct iwl_priv *priv)
2787 {
2788 int ret = 0;
2789
2790 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2791 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2792
2793 /* See if we got it */
2794 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2795 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2796 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2797 HW_READY_TIMEOUT);
2798 if (ret != -ETIMEDOUT)
2799 priv->hw_ready = true;
2800 else
2801 priv->hw_ready = false;
2802
2803 IWL_DEBUG_INFO(priv, "hardware %s\n",
2804 (priv->hw_ready == 1) ? "ready" : "not ready");
2805 return ret;
2806 }
2807
2808 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2809 {
2810 int ret = 0;
2811
2812 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2813
2814 ret = iwl_set_hw_ready(priv);
2815 if (priv->hw_ready)
2816 return ret;
2817
2818 /* If HW is not ready, prepare the conditions to check again */
2819 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2820 CSR_HW_IF_CONFIG_REG_PREPARE);
2821
2822 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2823 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2824 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2825
2826 /* HW should be ready by now, check again. */
2827 if (ret != -ETIMEDOUT)
2828 iwl_set_hw_ready(priv);
2829
2830 return ret;
2831 }
2832
2833 #define MAX_HW_RESTARTS 5
2834
2835 static int __iwl_up(struct iwl_priv *priv)
2836 {
2837 int i;
2838 int ret;
2839
2840 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2841 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2842 return -EIO;
2843 }
2844
2845 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2846 IWL_ERR(priv, "ucode not available for device bringup\n");
2847 return -EIO;
2848 }
2849
2850 ret = iwl_alloc_bcast_station(priv, true);
2851 if (ret)
2852 return ret;
2853
2854 iwl_prepare_card_hw(priv);
2855
2856 if (!priv->hw_ready) {
2857 IWL_WARN(priv, "Exit HW not ready\n");
2858 return -EIO;
2859 }
2860
2861 /* If platform's RF_KILL switch is NOT set to KILL */
2862 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2863 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2864 else
2865 set_bit(STATUS_RF_KILL_HW, &priv->status);
2866
2867 if (iwl_is_rfkill(priv)) {
2868 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2869
2870 iwl_enable_interrupts(priv);
2871 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2872 return 0;
2873 }
2874
2875 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2876
2877 ret = iwlagn_hw_nic_init(priv);
2878 if (ret) {
2879 IWL_ERR(priv, "Unable to init nic\n");
2880 return ret;
2881 }
2882
2883 /* make sure rfkill handshake bits are cleared */
2884 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2885 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2886 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2887
2888 /* clear (again), then enable host interrupts */
2889 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2890 iwl_enable_interrupts(priv);
2891
2892 /* really make sure rfkill handshake bits are cleared */
2893 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2894 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2895
2896 /* Copy original ucode data image from disk into backup cache.
2897 * This will be used to initialize the on-board processor's
2898 * data SRAM for a clean start when the runtime program first loads. */
2899 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2900 priv->ucode_data.len);
2901
2902 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2903
2904 /* load bootstrap state machine,
2905 * load bootstrap program into processor's memory,
2906 * prepare to load the "initialize" uCode */
2907 ret = priv->cfg->ops->lib->load_ucode(priv);
2908
2909 if (ret) {
2910 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2911 ret);
2912 continue;
2913 }
2914
2915 /* start card; "initialize" will load runtime ucode */
2916 iwl_nic_start(priv);
2917
2918 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2919
2920 return 0;
2921 }
2922
2923 set_bit(STATUS_EXIT_PENDING, &priv->status);
2924 __iwl_down(priv);
2925 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2926
2927 /* tried to restart and config the device for as long as our
2928 * patience could withstand */
2929 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2930 return -EIO;
2931 }
2932
2933
2934 /*****************************************************************************
2935 *
2936 * Workqueue callbacks
2937 *
2938 *****************************************************************************/
2939
2940 static void iwl_bg_init_alive_start(struct work_struct *data)
2941 {
2942 struct iwl_priv *priv =
2943 container_of(data, struct iwl_priv, init_alive_start.work);
2944
2945 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2946 return;
2947
2948 mutex_lock(&priv->mutex);
2949 priv->cfg->ops->lib->init_alive_start(priv);
2950 mutex_unlock(&priv->mutex);
2951 }
2952
2953 static void iwl_bg_alive_start(struct work_struct *data)
2954 {
2955 struct iwl_priv *priv =
2956 container_of(data, struct iwl_priv, alive_start.work);
2957
2958 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2959 return;
2960
2961 /* enable dram interrupt */
2962 iwl_reset_ict(priv);
2963
2964 mutex_lock(&priv->mutex);
2965 iwl_alive_start(priv);
2966 mutex_unlock(&priv->mutex);
2967 }
2968
2969 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2970 {
2971 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2972 run_time_calib_work);
2973
2974 mutex_lock(&priv->mutex);
2975
2976 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2977 test_bit(STATUS_SCANNING, &priv->status)) {
2978 mutex_unlock(&priv->mutex);
2979 return;
2980 }
2981
2982 if (priv->start_calib) {
2983 if (priv->cfg->bt_statistics) {
2984 iwl_chain_noise_calibration(priv,
2985 (void *)&priv->_agn.statistics_bt);
2986 iwl_sensitivity_calibration(priv,
2987 (void *)&priv->_agn.statistics_bt);
2988 } else {
2989 iwl_chain_noise_calibration(priv,
2990 (void *)&priv->_agn.statistics);
2991 iwl_sensitivity_calibration(priv,
2992 (void *)&priv->_agn.statistics);
2993 }
2994 }
2995
2996 mutex_unlock(&priv->mutex);
2997 }
2998
2999 static void iwl_bg_restart(struct work_struct *data)
3000 {
3001 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3002
3003 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3004 return;
3005
3006 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3007 mutex_lock(&priv->mutex);
3008 priv->vif = NULL;
3009 priv->is_open = 0;
3010 mutex_unlock(&priv->mutex);
3011 iwl_down(priv);
3012 ieee80211_restart_hw(priv->hw);
3013 } else {
3014 iwl_down(priv);
3015
3016 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3017 return;
3018
3019 mutex_lock(&priv->mutex);
3020 __iwl_up(priv);
3021 mutex_unlock(&priv->mutex);
3022 }
3023 }
3024
3025 static void iwl_bg_rx_replenish(struct work_struct *data)
3026 {
3027 struct iwl_priv *priv =
3028 container_of(data, struct iwl_priv, rx_replenish);
3029
3030 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3031 return;
3032
3033 mutex_lock(&priv->mutex);
3034 iwlagn_rx_replenish(priv);
3035 mutex_unlock(&priv->mutex);
3036 }
3037
3038 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3039
3040 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3041 {
3042 struct ieee80211_conf *conf = NULL;
3043 int ret = 0;
3044
3045 if (!vif || !priv->is_open)
3046 return;
3047
3048 if (vif->type == NL80211_IFTYPE_AP) {
3049 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3050 return;
3051 }
3052
3053 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3054 return;
3055
3056 iwl_scan_cancel_timeout(priv, 200);
3057
3058 conf = ieee80211_get_hw_conf(priv->hw);
3059
3060 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3061 iwlcore_commit_rxon(priv);
3062
3063 iwl_setup_rxon_timing(priv, vif);
3064 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3065 sizeof(priv->rxon_timing), &priv->rxon_timing);
3066 if (ret)
3067 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
3068 "Attempting to continue.\n");
3069
3070 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3071
3072 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3073
3074 if (priv->cfg->ops->hcmd->set_rxon_chain)
3075 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3076
3077 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3078
3079 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3080 vif->bss_conf.aid, vif->bss_conf.beacon_int);
3081
3082 if (vif->bss_conf.use_short_preamble)
3083 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3084 else
3085 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3086
3087 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
3088 if (vif->bss_conf.use_short_slot)
3089 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3090 else
3091 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3092 }
3093
3094 iwlcore_commit_rxon(priv);
3095
3096 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3097 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
3098
3099 switch (vif->type) {
3100 case NL80211_IFTYPE_STATION:
3101 break;
3102 case NL80211_IFTYPE_ADHOC:
3103 iwl_send_beacon_cmd(priv);
3104 break;
3105 default:
3106 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3107 __func__, vif->type);
3108 break;
3109 }
3110
3111 /* the chain noise calibration will enabled PM upon completion
3112 * If chain noise has already been run, then we need to enable
3113 * power management here */
3114 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3115 iwl_power_update_mode(priv, false);
3116
3117 /* Enable Rx differential gain and sensitivity calibrations */
3118 iwl_chain_noise_reset(priv);
3119 priv->start_calib = 1;
3120
3121 }
3122
3123 /*****************************************************************************
3124 *
3125 * mac80211 entry point functions
3126 *
3127 *****************************************************************************/
3128
3129 #define UCODE_READY_TIMEOUT (4 * HZ)
3130
3131 /*
3132 * Not a mac80211 entry point function, but it fits in with all the
3133 * other mac80211 functions grouped here.
3134 */
3135 static int iwl_mac_setup_register(struct iwl_priv *priv,
3136 struct iwlagn_ucode_capabilities *capa)
3137 {
3138 int ret;
3139 struct ieee80211_hw *hw = priv->hw;
3140 hw->rate_control_algorithm = "iwl-agn-rs";
3141
3142 /* Tell mac80211 our characteristics */
3143 hw->flags = IEEE80211_HW_SIGNAL_DBM |
3144 IEEE80211_HW_AMPDU_AGGREGATION |
3145 IEEE80211_HW_SPECTRUM_MGMT;
3146
3147 if (!priv->cfg->broken_powersave)
3148 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3149 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3150
3151 if (priv->cfg->sku & IWL_SKU_N)
3152 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3153 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3154
3155 hw->sta_data_size = sizeof(struct iwl_station_priv);
3156 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3157
3158 hw->wiphy->interface_modes =
3159 BIT(NL80211_IFTYPE_STATION) |
3160 BIT(NL80211_IFTYPE_ADHOC);
3161
3162 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3163 WIPHY_FLAG_DISABLE_BEACON_HINTS;
3164
3165 /*
3166 * For now, disable PS by default because it affects
3167 * RX performance significantly.
3168 */
3169 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3170
3171 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3172 /* we create the 802.11 header and a zero-length SSID element */
3173 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3174
3175 /* Default value; 4 EDCA QOS priorities */
3176 hw->queues = 4;
3177
3178 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3179
3180 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3181 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3182 &priv->bands[IEEE80211_BAND_2GHZ];
3183 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3184 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3185 &priv->bands[IEEE80211_BAND_5GHZ];
3186
3187 ret = ieee80211_register_hw(priv->hw);
3188 if (ret) {
3189 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3190 return ret;
3191 }
3192 priv->mac80211_registered = 1;
3193
3194 return 0;
3195 }
3196
3197
3198 static int iwl_mac_start(struct ieee80211_hw *hw)
3199 {
3200 struct iwl_priv *priv = hw->priv;
3201 int ret;
3202
3203 IWL_DEBUG_MAC80211(priv, "enter\n");
3204
3205 /* we should be verifying the device is ready to be opened */
3206 mutex_lock(&priv->mutex);
3207 ret = __iwl_up(priv);
3208 mutex_unlock(&priv->mutex);
3209
3210 if (ret)
3211 return ret;
3212
3213 if (iwl_is_rfkill(priv))
3214 goto out;
3215
3216 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3217
3218 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3219 * mac80211 will not be run successfully. */
3220 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3221 test_bit(STATUS_READY, &priv->status),
3222 UCODE_READY_TIMEOUT);
3223 if (!ret) {
3224 if (!test_bit(STATUS_READY, &priv->status)) {
3225 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3226 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3227 return -ETIMEDOUT;
3228 }
3229 }
3230
3231 iwl_led_start(priv);
3232
3233 out:
3234 priv->is_open = 1;
3235 IWL_DEBUG_MAC80211(priv, "leave\n");
3236 return 0;
3237 }
3238
3239 static void iwl_mac_stop(struct ieee80211_hw *hw)
3240 {
3241 struct iwl_priv *priv = hw->priv;
3242
3243 IWL_DEBUG_MAC80211(priv, "enter\n");
3244
3245 if (!priv->is_open)
3246 return;
3247
3248 priv->is_open = 0;
3249
3250 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3251 /* stop mac, cancel any scan request and clear
3252 * RXON_FILTER_ASSOC_MSK BIT
3253 */
3254 mutex_lock(&priv->mutex);
3255 iwl_scan_cancel_timeout(priv, 100);
3256 mutex_unlock(&priv->mutex);
3257 }
3258
3259 iwl_down(priv);
3260
3261 flush_workqueue(priv->workqueue);
3262
3263 /* enable interrupts again in order to receive rfkill changes */
3264 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3265 iwl_enable_interrupts(priv);
3266
3267 IWL_DEBUG_MAC80211(priv, "leave\n");
3268 }
3269
3270 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3271 {
3272 struct iwl_priv *priv = hw->priv;
3273
3274 IWL_DEBUG_MACDUMP(priv, "enter\n");
3275
3276 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3277 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3278
3279 if (iwlagn_tx_skb(priv, skb))
3280 dev_kfree_skb_any(skb);
3281
3282 IWL_DEBUG_MACDUMP(priv, "leave\n");
3283 return NETDEV_TX_OK;
3284 }
3285
3286 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3287 {
3288 int ret = 0;
3289
3290 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3291 return;
3292
3293 /* The following should be done only at AP bring up */
3294 if (!iwl_is_associated(priv)) {
3295
3296 /* RXON - unassoc (to set timing command) */
3297 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3298 iwlcore_commit_rxon(priv);
3299
3300 /* RXON Timing */
3301 iwl_setup_rxon_timing(priv, vif);
3302 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
3303 sizeof(priv->rxon_timing), &priv->rxon_timing);
3304 if (ret)
3305 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
3306 "Attempting to continue.\n");
3307
3308 /* AP has all antennas */
3309 priv->chain_noise_data.active_chains =
3310 priv->hw_params.valid_rx_ant;
3311 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3312 if (priv->cfg->ops->hcmd->set_rxon_chain)
3313 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3314
3315 priv->staging_rxon.assoc_id = 0;
3316
3317 if (vif->bss_conf.use_short_preamble)
3318 priv->staging_rxon.flags |=
3319 RXON_FLG_SHORT_PREAMBLE_MSK;
3320 else
3321 priv->staging_rxon.flags &=
3322 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3323
3324 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
3325 if (vif->bss_conf.use_short_slot)
3326 priv->staging_rxon.flags |=
3327 RXON_FLG_SHORT_SLOT_MSK;
3328 else
3329 priv->staging_rxon.flags &=
3330 ~RXON_FLG_SHORT_SLOT_MSK;
3331 }
3332 /* restore RXON assoc */
3333 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3334 iwlcore_commit_rxon(priv);
3335 }
3336 iwl_send_beacon_cmd(priv);
3337
3338 /* FIXME - we need to add code here to detect a totally new
3339 * configuration, reset the AP, unassoc, rxon timing, assoc,
3340 * clear sta table, add BCAST sta... */
3341 }
3342
3343 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3344 struct ieee80211_vif *vif,
3345 struct ieee80211_key_conf *keyconf,
3346 struct ieee80211_sta *sta,
3347 u32 iv32, u16 *phase1key)
3348 {
3349
3350 struct iwl_priv *priv = hw->priv;
3351 IWL_DEBUG_MAC80211(priv, "enter\n");
3352
3353 iwl_update_tkip_key(priv, keyconf, sta,
3354 iv32, phase1key);
3355
3356 IWL_DEBUG_MAC80211(priv, "leave\n");
3357 }
3358
3359 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3360 struct ieee80211_vif *vif,
3361 struct ieee80211_sta *sta,
3362 struct ieee80211_key_conf *key)
3363 {
3364 struct iwl_priv *priv = hw->priv;
3365 int ret;
3366 u8 sta_id;
3367 bool is_default_wep_key = false;
3368
3369 IWL_DEBUG_MAC80211(priv, "enter\n");
3370
3371 if (priv->cfg->mod_params->sw_crypto) {
3372 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3373 return -EOPNOTSUPP;
3374 }
3375
3376 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3377 if (sta_id == IWL_INVALID_STATION)
3378 return -EINVAL;
3379
3380 mutex_lock(&priv->mutex);
3381 iwl_scan_cancel_timeout(priv, 100);
3382
3383 /*
3384 * If we are getting WEP group key and we didn't receive any key mapping
3385 * so far, we are in legacy wep mode (group key only), otherwise we are
3386 * in 1X mode.
3387 * In legacy wep mode, we use another host command to the uCode.
3388 */
3389 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
3390 if (cmd == SET_KEY)
3391 is_default_wep_key = !priv->key_mapping_key;
3392 else
3393 is_default_wep_key =
3394 (key->hw_key_idx == HW_KEY_DEFAULT);
3395 }
3396
3397 switch (cmd) {
3398 case SET_KEY:
3399 if (is_default_wep_key)
3400 ret = iwl_set_default_wep_key(priv, key);
3401 else
3402 ret = iwl_set_dynamic_key(priv, key, sta_id);
3403
3404 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3405 break;
3406 case DISABLE_KEY:
3407 if (is_default_wep_key)
3408 ret = iwl_remove_default_wep_key(priv, key);
3409 else
3410 ret = iwl_remove_dynamic_key(priv, key, sta_id);
3411
3412 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3413 break;
3414 default:
3415 ret = -EINVAL;
3416 }
3417
3418 mutex_unlock(&priv->mutex);
3419 IWL_DEBUG_MAC80211(priv, "leave\n");
3420
3421 return ret;
3422 }
3423
3424 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3425 struct ieee80211_vif *vif,
3426 enum ieee80211_ampdu_mlme_action action,
3427 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3428 {
3429 struct iwl_priv *priv = hw->priv;
3430 int ret = -EINVAL;
3431
3432 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3433 sta->addr, tid);
3434
3435 if (!(priv->cfg->sku & IWL_SKU_N))
3436 return -EACCES;
3437
3438 mutex_lock(&priv->mutex);
3439
3440 switch (action) {
3441 case IEEE80211_AMPDU_RX_START:
3442 IWL_DEBUG_HT(priv, "start Rx\n");
3443 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3444 break;
3445 case IEEE80211_AMPDU_RX_STOP:
3446 IWL_DEBUG_HT(priv, "stop Rx\n");
3447 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3448 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3449 ret = 0;
3450 break;
3451 case IEEE80211_AMPDU_TX_START:
3452 IWL_DEBUG_HT(priv, "start Tx\n");
3453 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3454 if (ret == 0) {
3455 priv->_agn.agg_tids_count++;
3456 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3457 priv->_agn.agg_tids_count);
3458 }
3459 break;
3460 case IEEE80211_AMPDU_TX_STOP:
3461 IWL_DEBUG_HT(priv, "stop Tx\n");
3462 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3463 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3464 priv->_agn.agg_tids_count--;
3465 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3466 priv->_agn.agg_tids_count);
3467 }
3468 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3469 ret = 0;
3470 if (priv->cfg->use_rts_for_aggregation) {
3471 struct iwl_station_priv *sta_priv =
3472 (void *) sta->drv_priv;
3473 /*
3474 * switch off RTS/CTS if it was previously enabled
3475 */
3476
3477 sta_priv->lq_sta.lq.general_params.flags &=
3478 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3479 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3480 CMD_ASYNC, false);
3481 }
3482 break;
3483 case IEEE80211_AMPDU_TX_OPERATIONAL:
3484 if (priv->cfg->use_rts_for_aggregation) {
3485 struct iwl_station_priv *sta_priv =
3486 (void *) sta->drv_priv;
3487
3488 /*
3489 * switch to RTS/CTS if it is the prefer protection
3490 * method for HT traffic
3491 */
3492
3493 sta_priv->lq_sta.lq.general_params.flags |=
3494 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3495 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3496 CMD_ASYNC, false);
3497 }
3498 ret = 0;
3499 break;
3500 }
3501 mutex_unlock(&priv->mutex);
3502
3503 return ret;
3504 }
3505
3506 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3507 struct ieee80211_vif *vif,
3508 enum sta_notify_cmd cmd,
3509 struct ieee80211_sta *sta)
3510 {
3511 struct iwl_priv *priv = hw->priv;
3512 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3513 int sta_id;
3514
3515 switch (cmd) {
3516 case STA_NOTIFY_SLEEP:
3517 WARN_ON(!sta_priv->client);
3518 sta_priv->asleep = true;
3519 if (atomic_read(&sta_priv->pending_frames) > 0)
3520 ieee80211_sta_block_awake(hw, sta, true);
3521 break;
3522 case STA_NOTIFY_AWAKE:
3523 WARN_ON(!sta_priv->client);
3524 if (!sta_priv->asleep)
3525 break;
3526 sta_priv->asleep = false;
3527 sta_id = iwl_sta_id(sta);
3528 if (sta_id != IWL_INVALID_STATION)
3529 iwl_sta_modify_ps_wake(priv, sta_id);
3530 break;
3531 default:
3532 break;
3533 }
3534 }
3535
3536 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3537 struct ieee80211_vif *vif,
3538 struct ieee80211_sta *sta)
3539 {
3540 struct iwl_priv *priv = hw->priv;
3541 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3542 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3543 int ret;
3544 u8 sta_id;
3545
3546 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3547 sta->addr);
3548 mutex_lock(&priv->mutex);
3549 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3550 sta->addr);
3551 sta_priv->common.sta_id = IWL_INVALID_STATION;
3552
3553 atomic_set(&sta_priv->pending_frames, 0);
3554 if (vif->type == NL80211_IFTYPE_AP)
3555 sta_priv->client = true;
3556
3557 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3558 &sta_id);
3559 if (ret) {
3560 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3561 sta->addr, ret);
3562 /* Should we return success if return code is EEXIST ? */
3563 mutex_unlock(&priv->mutex);
3564 return ret;
3565 }
3566
3567 sta_priv->common.sta_id = sta_id;
3568
3569 /* Initialize rate scaling */
3570 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3571 sta->addr);
3572 iwl_rs_rate_init(priv, sta, sta_id);
3573 mutex_unlock(&priv->mutex);
3574
3575 return 0;
3576 }
3577
3578 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3579 struct ieee80211_channel_switch *ch_switch)
3580 {
3581 struct iwl_priv *priv = hw->priv;
3582 const struct iwl_channel_info *ch_info;
3583 struct ieee80211_conf *conf = &hw->conf;
3584 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3585 u16 ch;
3586 unsigned long flags = 0;
3587
3588 IWL_DEBUG_MAC80211(priv, "enter\n");
3589
3590 if (iwl_is_rfkill(priv))
3591 goto out_exit;
3592
3593 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3594 test_bit(STATUS_SCANNING, &priv->status))
3595 goto out_exit;
3596
3597 if (!iwl_is_associated(priv))
3598 goto out_exit;
3599
3600 /* channel switch in progress */
3601 if (priv->switch_rxon.switch_in_progress == true)
3602 goto out_exit;
3603
3604 mutex_lock(&priv->mutex);
3605 if (priv->cfg->ops->lib->set_channel_switch) {
3606
3607 ch = ieee80211_frequency_to_channel(
3608 ch_switch->channel->center_freq);
3609 if (le16_to_cpu(priv->active_rxon.channel) != ch) {
3610 ch_info = iwl_get_channel_info(priv,
3611 conf->channel->band,
3612 ch);
3613 if (!is_channel_valid(ch_info)) {
3614 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3615 goto out;
3616 }
3617 spin_lock_irqsave(&priv->lock, flags);
3618
3619 priv->current_ht_config.smps = conf->smps_mode;
3620
3621 /* Configure HT40 channels */
3622 ht_conf->is_ht = conf_is_ht(conf);
3623 if (ht_conf->is_ht) {
3624 if (conf_is_ht40_minus(conf)) {
3625 ht_conf->extension_chan_offset =
3626 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3627 ht_conf->is_40mhz = true;
3628 } else if (conf_is_ht40_plus(conf)) {
3629 ht_conf->extension_chan_offset =
3630 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3631 ht_conf->is_40mhz = true;
3632 } else {
3633 ht_conf->extension_chan_offset =
3634 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3635 ht_conf->is_40mhz = false;
3636 }
3637 } else
3638 ht_conf->is_40mhz = false;
3639
3640 /* if we are switching from ht to 2.4 clear flags
3641 * from any ht related info since 2.4 does not
3642 * support ht */
3643 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
3644 priv->staging_rxon.flags = 0;
3645
3646 iwl_set_rxon_channel(priv, conf->channel);
3647 iwl_set_rxon_ht(priv, ht_conf);
3648 iwl_set_flags_for_band(priv, conf->channel->band,
3649 priv->vif);
3650 spin_unlock_irqrestore(&priv->lock, flags);
3651
3652 iwl_set_rate(priv);
3653 /*
3654 * at this point, staging_rxon has the
3655 * configuration for channel switch
3656 */
3657 if (priv->cfg->ops->lib->set_channel_switch(priv,
3658 ch_switch))
3659 priv->switch_rxon.switch_in_progress = false;
3660 }
3661 }
3662 out:
3663 mutex_unlock(&priv->mutex);
3664 out_exit:
3665 if (!priv->switch_rxon.switch_in_progress)
3666 ieee80211_chswitch_done(priv->vif, false);
3667 IWL_DEBUG_MAC80211(priv, "leave\n");
3668 }
3669
3670 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3671 unsigned int changed_flags,
3672 unsigned int *total_flags,
3673 u64 multicast)
3674 {
3675 struct iwl_priv *priv = hw->priv;
3676 __le32 filter_or = 0, filter_nand = 0;
3677
3678 #define CHK(test, flag) do { \
3679 if (*total_flags & (test)) \
3680 filter_or |= (flag); \
3681 else \
3682 filter_nand |= (flag); \
3683 } while (0)
3684
3685 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3686 changed_flags, *total_flags);
3687
3688 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3689 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3690 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3691
3692 #undef CHK
3693
3694 mutex_lock(&priv->mutex);
3695
3696 priv->staging_rxon.filter_flags &= ~filter_nand;
3697 priv->staging_rxon.filter_flags |= filter_or;
3698
3699 iwlcore_commit_rxon(priv);
3700
3701 mutex_unlock(&priv->mutex);
3702
3703 /*
3704 * Receiving all multicast frames is always enabled by the
3705 * default flags setup in iwl_connection_init_rx_config()
3706 * since we currently do not support programming multicast
3707 * filters into the device.
3708 */
3709 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3710 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3711 }
3712
3713 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3714 {
3715 struct iwl_priv *priv = hw->priv;
3716
3717 mutex_lock(&priv->mutex);
3718 IWL_DEBUG_MAC80211(priv, "enter\n");
3719
3720 /* do not support "flush" */
3721 if (!priv->cfg->ops->lib->txfifo_flush)
3722 goto done;
3723
3724 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3725 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3726 goto done;
3727 }
3728 if (iwl_is_rfkill(priv)) {
3729 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3730 goto done;
3731 }
3732
3733 /*
3734 * mac80211 will not push any more frames for transmit
3735 * until the flush is completed
3736 */
3737 if (drop) {
3738 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3739 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3740 IWL_ERR(priv, "flush request fail\n");
3741 goto done;
3742 }
3743 }
3744 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3745 iwlagn_wait_tx_queue_empty(priv);
3746 done:
3747 mutex_unlock(&priv->mutex);
3748 IWL_DEBUG_MAC80211(priv, "leave\n");
3749 }
3750
3751 /*****************************************************************************
3752 *
3753 * driver setup and teardown
3754 *
3755 *****************************************************************************/
3756
3757 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3758 {
3759 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3760
3761 init_waitqueue_head(&priv->wait_command_queue);
3762
3763 INIT_WORK(&priv->restart, iwl_bg_restart);
3764 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3765 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3766 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3767 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3768 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3769 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3770
3771 iwl_setup_scan_deferred_work(priv);
3772
3773 if (priv->cfg->ops->lib->setup_deferred_work)
3774 priv->cfg->ops->lib->setup_deferred_work(priv);
3775
3776 init_timer(&priv->statistics_periodic);
3777 priv->statistics_periodic.data = (unsigned long)priv;
3778 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3779
3780 init_timer(&priv->ucode_trace);
3781 priv->ucode_trace.data = (unsigned long)priv;
3782 priv->ucode_trace.function = iwl_bg_ucode_trace;
3783
3784 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3785 init_timer(&priv->monitor_recover);
3786 priv->monitor_recover.data = (unsigned long)priv;
3787 priv->monitor_recover.function =
3788 priv->cfg->ops->lib->recover_from_tx_stall;
3789 }
3790
3791 if (!priv->cfg->use_isr_legacy)
3792 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3793 iwl_irq_tasklet, (unsigned long)priv);
3794 else
3795 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3796 iwl_irq_tasklet_legacy, (unsigned long)priv);
3797 }
3798
3799 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3800 {
3801 if (priv->cfg->ops->lib->cancel_deferred_work)
3802 priv->cfg->ops->lib->cancel_deferred_work(priv);
3803
3804 cancel_delayed_work_sync(&priv->init_alive_start);
3805 cancel_delayed_work(&priv->scan_check);
3806 cancel_work_sync(&priv->start_internal_scan);
3807 cancel_delayed_work(&priv->alive_start);
3808 cancel_work_sync(&priv->run_time_calib_work);
3809 cancel_work_sync(&priv->beacon_update);
3810 del_timer_sync(&priv->statistics_periodic);
3811 del_timer_sync(&priv->ucode_trace);
3812 if (priv->cfg->ops->lib->recover_from_tx_stall)
3813 del_timer_sync(&priv->monitor_recover);
3814 }
3815
3816 static void iwl_init_hw_rates(struct iwl_priv *priv,
3817 struct ieee80211_rate *rates)
3818 {
3819 int i;
3820
3821 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3822 rates[i].bitrate = iwl_rates[i].ieee * 5;
3823 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3824 rates[i].hw_value_short = i;
3825 rates[i].flags = 0;
3826 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3827 /*
3828 * If CCK != 1M then set short preamble rate flag.
3829 */
3830 rates[i].flags |=
3831 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3832 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3833 }
3834 }
3835 }
3836
3837 static int iwl_init_drv(struct iwl_priv *priv)
3838 {
3839 int ret;
3840
3841 priv->ibss_beacon = NULL;
3842
3843 spin_lock_init(&priv->sta_lock);
3844 spin_lock_init(&priv->hcmd_lock);
3845
3846 INIT_LIST_HEAD(&priv->free_frames);
3847
3848 mutex_init(&priv->mutex);
3849 mutex_init(&priv->sync_cmd_mutex);
3850
3851 priv->ieee_channels = NULL;
3852 priv->ieee_rates = NULL;
3853 priv->band = IEEE80211_BAND_2GHZ;
3854
3855 priv->iw_mode = NL80211_IFTYPE_STATION;
3856 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3857 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3858 priv->_agn.agg_tids_count = 0;
3859
3860 /* initialize force reset */
3861 priv->force_reset[IWL_RF_RESET].reset_duration =
3862 IWL_DELAY_NEXT_FORCE_RF_RESET;
3863 priv->force_reset[IWL_FW_RESET].reset_duration =
3864 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3865
3866 /* Choose which receivers/antennas to use */
3867 if (priv->cfg->ops->hcmd->set_rxon_chain)
3868 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3869
3870 iwl_init_scan_params(priv);
3871
3872 /* Set the tx_power_user_lmt to the lowest power level
3873 * this value will get overwritten by channel max power avg
3874 * from eeprom */
3875 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3876
3877 ret = iwl_init_channel_map(priv);
3878 if (ret) {
3879 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3880 goto err;
3881 }
3882
3883 ret = iwlcore_init_geos(priv);
3884 if (ret) {
3885 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3886 goto err_free_channel_map;
3887 }
3888 iwl_init_hw_rates(priv, priv->ieee_rates);
3889
3890 return 0;
3891
3892 err_free_channel_map:
3893 iwl_free_channel_map(priv);
3894 err:
3895 return ret;
3896 }
3897
3898 static void iwl_uninit_drv(struct iwl_priv *priv)
3899 {
3900 iwl_calib_free_results(priv);
3901 iwlcore_free_geos(priv);
3902 iwl_free_channel_map(priv);
3903 kfree(priv->scan_cmd);
3904 }
3905
3906 static struct ieee80211_ops iwl_hw_ops = {
3907 .tx = iwl_mac_tx,
3908 .start = iwl_mac_start,
3909 .stop = iwl_mac_stop,
3910 .add_interface = iwl_mac_add_interface,
3911 .remove_interface = iwl_mac_remove_interface,
3912 .config = iwl_mac_config,
3913 .configure_filter = iwlagn_configure_filter,
3914 .set_key = iwl_mac_set_key,
3915 .update_tkip_key = iwl_mac_update_tkip_key,
3916 .conf_tx = iwl_mac_conf_tx,
3917 .reset_tsf = iwl_mac_reset_tsf,
3918 .bss_info_changed = iwl_bss_info_changed,
3919 .ampdu_action = iwl_mac_ampdu_action,
3920 .hw_scan = iwl_mac_hw_scan,
3921 .sta_notify = iwl_mac_sta_notify,
3922 .sta_add = iwlagn_mac_sta_add,
3923 .sta_remove = iwl_mac_sta_remove,
3924 .channel_switch = iwl_mac_channel_switch,
3925 .flush = iwl_mac_flush,
3926 };
3927
3928 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3929 {
3930 int err = 0;
3931 struct iwl_priv *priv;
3932 struct ieee80211_hw *hw;
3933 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3934 unsigned long flags;
3935 u16 pci_cmd, num_mac;
3936
3937 /************************
3938 * 1. Allocating HW data
3939 ************************/
3940
3941 /* Disabling hardware scan means that mac80211 will perform scans
3942 * "the hard way", rather than using device's scan. */
3943 if (cfg->mod_params->disable_hw_scan) {
3944 if (iwl_debug_level & IWL_DL_INFO)
3945 dev_printk(KERN_DEBUG, &(pdev->dev),
3946 "Disabling hw_scan\n");
3947 iwl_hw_ops.hw_scan = NULL;
3948 }
3949
3950 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3951 if (!hw) {
3952 err = -ENOMEM;
3953 goto out;
3954 }
3955 priv = hw->priv;
3956 /* At this point both hw and priv are allocated. */
3957
3958 SET_IEEE80211_DEV(hw, &pdev->dev);
3959
3960 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3961 priv->cfg = cfg;
3962 priv->pci_dev = pdev;
3963 priv->inta_mask = CSR_INI_SET_MASK;
3964
3965 if (iwl_alloc_traffic_mem(priv))
3966 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3967
3968 /**************************
3969 * 2. Initializing PCI bus
3970 **************************/
3971 if (pci_enable_device(pdev)) {
3972 err = -ENODEV;
3973 goto out_ieee80211_free_hw;
3974 }
3975
3976 pci_set_master(pdev);
3977
3978 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3979 if (!err)
3980 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3981 if (err) {
3982 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3983 if (!err)
3984 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3985 /* both attempts failed: */
3986 if (err) {
3987 IWL_WARN(priv, "No suitable DMA available.\n");
3988 goto out_pci_disable_device;
3989 }
3990 }
3991
3992 err = pci_request_regions(pdev, DRV_NAME);
3993 if (err)
3994 goto out_pci_disable_device;
3995
3996 pci_set_drvdata(pdev, priv);
3997
3998
3999 /***********************
4000 * 3. Read REV register
4001 ***********************/
4002 priv->hw_base = pci_iomap(pdev, 0, 0);
4003 if (!priv->hw_base) {
4004 err = -ENODEV;
4005 goto out_pci_release_regions;
4006 }
4007
4008 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4009 (unsigned long long) pci_resource_len(pdev, 0));
4010 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4011
4012 /* these spin locks will be used in apm_ops.init and EEPROM access
4013 * we should init now
4014 */
4015 spin_lock_init(&priv->reg_lock);
4016 spin_lock_init(&priv->lock);
4017
4018 /*
4019 * stop and reset the on-board processor just in case it is in a
4020 * strange state ... like being left stranded by a primary kernel
4021 * and this is now the kdump kernel trying to start up
4022 */
4023 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4024
4025 iwl_hw_detect(priv);
4026 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4027 priv->cfg->name, priv->hw_rev);
4028
4029 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4030 * PCI Tx retries from interfering with C3 CPU state */
4031 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4032
4033 iwl_prepare_card_hw(priv);
4034 if (!priv->hw_ready) {
4035 IWL_WARN(priv, "Failed, HW not ready\n");
4036 goto out_iounmap;
4037 }
4038
4039 /*****************
4040 * 4. Read EEPROM
4041 *****************/
4042 /* Read the EEPROM */
4043 err = iwl_eeprom_init(priv);
4044 if (err) {
4045 IWL_ERR(priv, "Unable to init EEPROM\n");
4046 goto out_iounmap;
4047 }
4048 err = iwl_eeprom_check_version(priv);
4049 if (err)
4050 goto out_free_eeprom;
4051
4052 /* extract MAC Address */
4053 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4054 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4055 priv->hw->wiphy->addresses = priv->addresses;
4056 priv->hw->wiphy->n_addresses = 1;
4057 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4058 if (num_mac > 1) {
4059 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4060 ETH_ALEN);
4061 priv->addresses[1].addr[5]++;
4062 priv->hw->wiphy->n_addresses++;
4063 }
4064
4065 /************************
4066 * 5. Setup HW constants
4067 ************************/
4068 if (iwl_set_hw_params(priv)) {
4069 IWL_ERR(priv, "failed to set hw parameters\n");
4070 goto out_free_eeprom;
4071 }
4072
4073 /*******************
4074 * 6. Setup priv
4075 *******************/
4076
4077 err = iwl_init_drv(priv);
4078 if (err)
4079 goto out_free_eeprom;
4080 /* At this point both hw and priv are initialized. */
4081
4082 /********************
4083 * 7. Setup services
4084 ********************/
4085 spin_lock_irqsave(&priv->lock, flags);
4086 iwl_disable_interrupts(priv);
4087 spin_unlock_irqrestore(&priv->lock, flags);
4088
4089 pci_enable_msi(priv->pci_dev);
4090
4091 iwl_alloc_isr_ict(priv);
4092 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4093 IRQF_SHARED, DRV_NAME, priv);
4094 if (err) {
4095 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4096 goto out_disable_msi;
4097 }
4098
4099 iwl_setup_deferred_work(priv);
4100 iwl_setup_rx_handlers(priv);
4101
4102 /*********************************************
4103 * 8. Enable interrupts and read RFKILL state
4104 *********************************************/
4105
4106 /* enable interrupts if needed: hw bug w/a */
4107 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4108 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4109 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4110 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4111 }
4112
4113 iwl_enable_interrupts(priv);
4114
4115 /* If platform's RF_KILL switch is NOT set to KILL */
4116 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4117 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4118 else
4119 set_bit(STATUS_RF_KILL_HW, &priv->status);
4120
4121 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4122 test_bit(STATUS_RF_KILL_HW, &priv->status));
4123
4124 iwl_power_initialize(priv);
4125 iwl_tt_initialize(priv);
4126
4127 init_completion(&priv->_agn.firmware_loading_complete);
4128
4129 err = iwl_request_firmware(priv, true);
4130 if (err)
4131 goto out_destroy_workqueue;
4132
4133 return 0;
4134
4135 out_destroy_workqueue:
4136 destroy_workqueue(priv->workqueue);
4137 priv->workqueue = NULL;
4138 free_irq(priv->pci_dev->irq, priv);
4139 iwl_free_isr_ict(priv);
4140 out_disable_msi:
4141 pci_disable_msi(priv->pci_dev);
4142 iwl_uninit_drv(priv);
4143 out_free_eeprom:
4144 iwl_eeprom_free(priv);
4145 out_iounmap:
4146 pci_iounmap(pdev, priv->hw_base);
4147 out_pci_release_regions:
4148 pci_set_drvdata(pdev, NULL);
4149 pci_release_regions(pdev);
4150 out_pci_disable_device:
4151 pci_disable_device(pdev);
4152 out_ieee80211_free_hw:
4153 iwl_free_traffic_mem(priv);
4154 ieee80211_free_hw(priv->hw);
4155 out:
4156 return err;
4157 }
4158
4159 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4160 {
4161 struct iwl_priv *priv = pci_get_drvdata(pdev);
4162 unsigned long flags;
4163
4164 if (!priv)
4165 return;
4166
4167 wait_for_completion(&priv->_agn.firmware_loading_complete);
4168
4169 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4170
4171 iwl_dbgfs_unregister(priv);
4172 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4173
4174 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4175 * to be called and iwl_down since we are removing the device
4176 * we need to set STATUS_EXIT_PENDING bit.
4177 */
4178 set_bit(STATUS_EXIT_PENDING, &priv->status);
4179 if (priv->mac80211_registered) {
4180 ieee80211_unregister_hw(priv->hw);
4181 priv->mac80211_registered = 0;
4182 } else {
4183 iwl_down(priv);
4184 }
4185
4186 /*
4187 * Make sure device is reset to low power before unloading driver.
4188 * This may be redundant with iwl_down(), but there are paths to
4189 * run iwl_down() without calling apm_ops.stop(), and there are
4190 * paths to avoid running iwl_down() at all before leaving driver.
4191 * This (inexpensive) call *makes sure* device is reset.
4192 */
4193 priv->cfg->ops->lib->apm_ops.stop(priv);
4194
4195 iwl_tt_exit(priv);
4196
4197 /* make sure we flush any pending irq or
4198 * tasklet for the driver
4199 */
4200 spin_lock_irqsave(&priv->lock, flags);
4201 iwl_disable_interrupts(priv);
4202 spin_unlock_irqrestore(&priv->lock, flags);
4203
4204 iwl_synchronize_irq(priv);
4205
4206 iwl_dealloc_ucode_pci(priv);
4207
4208 if (priv->rxq.bd)
4209 iwlagn_rx_queue_free(priv, &priv->rxq);
4210 iwlagn_hw_txq_ctx_free(priv);
4211
4212 iwl_eeprom_free(priv);
4213
4214
4215 /*netif_stop_queue(dev); */
4216 flush_workqueue(priv->workqueue);
4217
4218 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4219 * priv->workqueue... so we can't take down the workqueue
4220 * until now... */
4221 destroy_workqueue(priv->workqueue);
4222 priv->workqueue = NULL;
4223 iwl_free_traffic_mem(priv);
4224
4225 free_irq(priv->pci_dev->irq, priv);
4226 pci_disable_msi(priv->pci_dev);
4227 pci_iounmap(pdev, priv->hw_base);
4228 pci_release_regions(pdev);
4229 pci_disable_device(pdev);
4230 pci_set_drvdata(pdev, NULL);
4231
4232 iwl_uninit_drv(priv);
4233
4234 iwl_free_isr_ict(priv);
4235
4236 if (priv->ibss_beacon)
4237 dev_kfree_skb(priv->ibss_beacon);
4238
4239 ieee80211_free_hw(priv->hw);
4240 }
4241
4242
4243 /*****************************************************************************
4244 *
4245 * driver and module entry point
4246 *
4247 *****************************************************************************/
4248
4249 /* Hardware specific file defines the PCI IDs table for that hardware module */
4250 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4251 #ifdef CONFIG_IWL4965
4252 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4253 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4254 #endif /* CONFIG_IWL4965 */
4255 #ifdef CONFIG_IWL5000
4256 /* 5100 Series WiFi */
4257 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4258 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4259 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4260 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4261 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4262 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4263 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4264 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4265 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4266 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4267 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4268 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4269 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4270 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4271 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4272 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4273 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4274 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4275 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4276 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4277 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4278 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4279 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4280 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4281
4282 /* 5300 Series WiFi */
4283 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4284 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4285 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4286 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4287 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4288 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4289 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4290 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4291 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4292 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4293 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4294 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4295
4296 /* 5350 Series WiFi/WiMax */
4297 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4298 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4299 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4300
4301 /* 5150 Series Wifi/WiMax */
4302 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4303 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4304 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4305 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4306 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4307 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4308
4309 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4310 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4311 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4312 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4313
4314 /* 6x00 Series */
4315 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4316 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4317 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4318 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4319 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4320 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4321 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4322 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4323 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4324 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4325
4326 /* 6x00 Series Gen2a */
4327 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4328 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4329 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4330 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4331 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4332 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4333 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4334 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4335 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4336 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4337 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4338 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4339 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4340 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4341
4342 /* 6x00 Series Gen2b */
4343 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4344 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4345 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4346 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4347 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4348 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4349 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4350 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4351 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4352 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4353 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4354 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4355 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4356 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4357 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4358 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4359 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4360 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4361 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4362 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4363 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4364 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4365 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4366 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4367 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4368 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4369 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4370 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4371
4372 /* 6x50 WiFi/WiMax Series */
4373 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4374 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4375 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4376 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4377 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4378 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4379
4380 /* 6x50 WiFi/WiMax Series Gen2 */
4381 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4382 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4383 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4384 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4385 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4386 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4387
4388 /* 1000 Series WiFi */
4389 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4390 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4391 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4392 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4393 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4394 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4395 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4396 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4397 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4398 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4399 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4400 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4401 #endif /* CONFIG_IWL5000 */
4402
4403 {0}
4404 };
4405 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4406
4407 static struct pci_driver iwl_driver = {
4408 .name = DRV_NAME,
4409 .id_table = iwl_hw_card_ids,
4410 .probe = iwl_pci_probe,
4411 .remove = __devexit_p(iwl_pci_remove),
4412 #ifdef CONFIG_PM
4413 .suspend = iwl_pci_suspend,
4414 .resume = iwl_pci_resume,
4415 #endif
4416 };
4417
4418 static int __init iwl_init(void)
4419 {
4420
4421 int ret;
4422 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4423 pr_info(DRV_COPYRIGHT "\n");
4424
4425 ret = iwlagn_rate_control_register();
4426 if (ret) {
4427 pr_err("Unable to register rate control algorithm: %d\n", ret);
4428 return ret;
4429 }
4430
4431 ret = pci_register_driver(&iwl_driver);
4432 if (ret) {
4433 pr_err("Unable to initialize PCI module\n");
4434 goto error_register;
4435 }
4436
4437 return ret;
4438
4439 error_register:
4440 iwlagn_rate_control_unregister();
4441 return ret;
4442 }
4443
4444 static void __exit iwl_exit(void)
4445 {
4446 pci_unregister_driver(&iwl_driver);
4447 iwlagn_rate_control_unregister();
4448 }
4449
4450 module_exit(iwl_exit);
4451 module_init(iwl_init);
4452
4453 #ifdef CONFIG_IWLWIFI_DEBUG
4454 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4455 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4456 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4457 MODULE_PARM_DESC(debug, "debug output mask");
4458 #endif
4459
4460 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4461 MODULE_PARM_DESC(swcrypto50,
4462 "using crypto in software (default 0 [hardware]) (deprecated)");
4463 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4464 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4465 module_param_named(queues_num50,
4466 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4467 MODULE_PARM_DESC(queues_num50,
4468 "number of hw queues in 50xx series (deprecated)");
4469 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4470 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4471 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4472 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4473 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4474 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4475 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4476 int, S_IRUGO);
4477 MODULE_PARM_DESC(amsdu_size_8K50,
4478 "enable 8K amsdu size in 50XX series (deprecated)");
4479 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4480 int, S_IRUGO);
4481 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4482 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4483 MODULE_PARM_DESC(fw_restart50,
4484 "restart firmware in case of error (deprecated)");
4485 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4486 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4487 module_param_named(
4488 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4489 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4490
4491 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4492 S_IRUGO);
4493 MODULE_PARM_DESC(ucode_alternative,
4494 "specify ucode alternative to use from ucode file");
kernel source for telekom puls (alcatel/mediatek)