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iwlagn: reduce redundant parameter definitions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwl5000_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwl5000_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
409 memset(&info->status, 0, sizeof(info->status));
410
411 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
412 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
413
414 spin_lock_irqsave(&priv->sta_lock, flags);
415 if (txq->sched_retry) {
416 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
417 struct iwl_ht_agg *agg;
418
419 agg = &priv->stations[sta_id].tid[tid].agg;
420 /*
421 * If the BT kill count is non-zero, we'll get this
422 * notification again.
423 */
424 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
425 priv->cfg->bt_params &&
426 priv->cfg->bt_params->advanced_bt_coexist) {
427 IWL_WARN(priv, "receive reply tx with bt_kill\n");
428 }
429 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
430
431 /* check if BAR is needed */
432 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
433 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
434
435 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
436 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
437 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
438 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
439 scd_ssn , index, txq_id, txq->swq_id);
440
441 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
442 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
443
444 if (priv->mac80211_registered &&
445 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
446 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
447 if (agg->state == IWL_AGG_OFF)
448 iwl_wake_queue(priv, txq_id);
449 else
450 iwl_wake_queue(priv, txq->swq_id);
451 }
452 }
453 } else {
454 BUG_ON(txq_id != txq->swq_id);
455 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
456 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
457 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
458
459 if (priv->mac80211_registered &&
460 (iwl_queue_space(&txq->q) > txq->q.low_mark))
461 iwl_wake_queue(priv, txq_id);
462 }
463
464 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
465
466 iwl_check_abort_status(priv, tx_resp->frame_count, status);
467 spin_unlock_irqrestore(&priv->sta_lock, flags);
468 }
469
470 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
471 {
472 /* init calibration handlers */
473 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
474 iwlagn_rx_calib_result;
475 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
476 iwlagn_rx_calib_complete;
477 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
478 }
479
480 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
481 {
482 /* in agn, the tx power calibration is done in uCode */
483 priv->disable_tx_power_cal = 1;
484 }
485
486 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
487 {
488 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
489 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
490 }
491
492 int iwlagn_send_tx_power(struct iwl_priv *priv)
493 {
494 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
495 u8 tx_ant_cfg_cmd;
496
497 /* half dBm need to multiply */
498 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
499
500 if (priv->tx_power_lmt_in_half_dbm &&
501 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
502 /*
503 * For the newer devices which using enhanced/extend tx power
504 * table in EEPROM, the format is in half dBm. driver need to
505 * convert to dBm format before report to mac80211.
506 * By doing so, there is a possibility of 1/2 dBm resolution
507 * lost. driver will perform "round-up" operation before
508 * reporting, but it will cause 1/2 dBm tx power over the
509 * regulatory limit. Perform the checking here, if the
510 * "tx_power_user_lmt" is higher than EEPROM value (in
511 * half-dBm format), lower the tx power based on EEPROM
512 */
513 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
514 }
515 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
516 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
517
518 if (IWL_UCODE_API(priv->ucode_ver) == 1)
519 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
520 else
521 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
522
523 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
524 sizeof(tx_power_cmd), &tx_power_cmd,
525 NULL);
526 }
527
528 void iwlagn_temperature(struct iwl_priv *priv)
529 {
530 /* store temperature from statistics (in Celsius) */
531 priv->temperature =
532 le32_to_cpu(priv->_agn.statistics.general.common.temperature);
533 iwl_tt_handler(priv);
534 }
535
536 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
537 {
538 struct iwl_eeprom_calib_hdr {
539 u8 version;
540 u8 pa_type;
541 u16 voltage;
542 } *hdr;
543
544 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
545 EEPROM_CALIB_ALL);
546 return hdr->version;
547
548 }
549
550 /*
551 * EEPROM
552 */
553 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
554 {
555 u16 offset = 0;
556
557 if ((address & INDIRECT_ADDRESS) == 0)
558 return address;
559
560 switch (address & INDIRECT_TYPE_MSK) {
561 case INDIRECT_HOST:
562 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
563 break;
564 case INDIRECT_GENERAL:
565 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
566 break;
567 case INDIRECT_REGULATORY:
568 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
569 break;
570 case INDIRECT_CALIBRATION:
571 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
572 break;
573 case INDIRECT_PROCESS_ADJST:
574 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
575 break;
576 case INDIRECT_OTHERS:
577 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
578 break;
579 default:
580 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
581 address & INDIRECT_TYPE_MSK);
582 break;
583 }
584
585 /* translate the offset from words to byte */
586 return (address & ADDRESS_MSK) + (offset << 1);
587 }
588
589 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
590 size_t offset)
591 {
592 u32 address = eeprom_indirect_address(priv, offset);
593 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
594 return &priv->eeprom[address];
595 }
596
597 struct iwl_mod_params iwlagn_mod_params = {
598 .amsdu_size_8K = 1,
599 .restart_fw = 1,
600 /* the rest are 0 by default */
601 };
602
603 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
604 {
605 unsigned long flags;
606 int i;
607 spin_lock_irqsave(&rxq->lock, flags);
608 INIT_LIST_HEAD(&rxq->rx_free);
609 INIT_LIST_HEAD(&rxq->rx_used);
610 /* Fill the rx_used queue with _all_ of the Rx buffers */
611 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
612 /* In the reset function, these buffers may have been allocated
613 * to an SKB, so we need to unmap and free potential storage */
614 if (rxq->pool[i].page != NULL) {
615 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
616 PAGE_SIZE << priv->hw_params.rx_page_order,
617 PCI_DMA_FROMDEVICE);
618 __iwl_free_pages(priv, rxq->pool[i].page);
619 rxq->pool[i].page = NULL;
620 }
621 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
622 }
623
624 for (i = 0; i < RX_QUEUE_SIZE; i++)
625 rxq->queue[i] = NULL;
626
627 /* Set us so that we have processed and used all buffers, but have
628 * not restocked the Rx queue with fresh buffers */
629 rxq->read = rxq->write = 0;
630 rxq->write_actual = 0;
631 rxq->free_count = 0;
632 spin_unlock_irqrestore(&rxq->lock, flags);
633 }
634
635 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
636 {
637 u32 rb_size;
638 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
639 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
640
641 if (!priv->cfg->base_params->use_isr_legacy)
642 rb_timeout = RX_RB_TIMEOUT;
643
644 if (priv->cfg->mod_params->amsdu_size_8K)
645 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
646 else
647 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
648
649 /* Stop Rx DMA */
650 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
651
652 /* Reset driver's Rx queue write index */
653 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
654
655 /* Tell device where to find RBD circular buffer in DRAM */
656 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
657 (u32)(rxq->bd_dma >> 8));
658
659 /* Tell device where in DRAM to update its Rx status */
660 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
661 rxq->rb_stts_dma >> 4);
662
663 /* Enable Rx DMA
664 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
665 * the credit mechanism in 5000 HW RX FIFO
666 * Direct rx interrupts to hosts
667 * Rx buffer size 4 or 8k
668 * RB timeout 0x10
669 * 256 RBDs
670 */
671 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
672 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
673 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
674 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
675 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
676 rb_size|
677 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
678 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
679
680 /* Set interrupt coalescing timer to default (2048 usecs) */
681 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
682
683 return 0;
684 }
685
686 int iwlagn_hw_nic_init(struct iwl_priv *priv)
687 {
688 unsigned long flags;
689 struct iwl_rx_queue *rxq = &priv->rxq;
690 int ret;
691
692 /* nic_init */
693 spin_lock_irqsave(&priv->lock, flags);
694 priv->cfg->ops->lib->apm_ops.init(priv);
695
696 /* Set interrupt coalescing calibration timer to default (512 usecs) */
697 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
698
699 spin_unlock_irqrestore(&priv->lock, flags);
700
701 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
702
703 priv->cfg->ops->lib->apm_ops.config(priv);
704
705 /* Allocate the RX queue, or reset if it is already allocated */
706 if (!rxq->bd) {
707 ret = iwl_rx_queue_alloc(priv);
708 if (ret) {
709 IWL_ERR(priv, "Unable to initialize Rx queue\n");
710 return -ENOMEM;
711 }
712 } else
713 iwlagn_rx_queue_reset(priv, rxq);
714
715 iwlagn_rx_replenish(priv);
716
717 iwlagn_rx_init(priv, rxq);
718
719 spin_lock_irqsave(&priv->lock, flags);
720
721 rxq->need_update = 1;
722 iwl_rx_queue_update_write_ptr(priv, rxq);
723
724 spin_unlock_irqrestore(&priv->lock, flags);
725
726 /* Allocate or reset and init all Tx and Command queues */
727 if (!priv->txq) {
728 ret = iwlagn_txq_ctx_alloc(priv);
729 if (ret)
730 return ret;
731 } else
732 iwlagn_txq_ctx_reset(priv);
733
734 set_bit(STATUS_INIT, &priv->status);
735
736 return 0;
737 }
738
739 /**
740 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
741 */
742 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
743 dma_addr_t dma_addr)
744 {
745 return cpu_to_le32((u32)(dma_addr >> 8));
746 }
747
748 /**
749 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
750 *
751 * If there are slots in the RX queue that need to be restocked,
752 * and we have free pre-allocated buffers, fill the ranks as much
753 * as we can, pulling from rx_free.
754 *
755 * This moves the 'write' index forward to catch up with 'processed', and
756 * also updates the memory address in the firmware to reference the new
757 * target buffer.
758 */
759 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
760 {
761 struct iwl_rx_queue *rxq = &priv->rxq;
762 struct list_head *element;
763 struct iwl_rx_mem_buffer *rxb;
764 unsigned long flags;
765
766 spin_lock_irqsave(&rxq->lock, flags);
767 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
768 /* The overwritten rxb must be a used one */
769 rxb = rxq->queue[rxq->write];
770 BUG_ON(rxb && rxb->page);
771
772 /* Get next free Rx buffer, remove from free list */
773 element = rxq->rx_free.next;
774 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
775 list_del(element);
776
777 /* Point to Rx buffer via next RBD in circular buffer */
778 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
779 rxb->page_dma);
780 rxq->queue[rxq->write] = rxb;
781 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
782 rxq->free_count--;
783 }
784 spin_unlock_irqrestore(&rxq->lock, flags);
785 /* If the pre-allocated buffer pool is dropping low, schedule to
786 * refill it */
787 if (rxq->free_count <= RX_LOW_WATERMARK)
788 queue_work(priv->workqueue, &priv->rx_replenish);
789
790
791 /* If we've added more space for the firmware to place data, tell it.
792 * Increment device's write pointer in multiples of 8. */
793 if (rxq->write_actual != (rxq->write & ~0x7)) {
794 spin_lock_irqsave(&rxq->lock, flags);
795 rxq->need_update = 1;
796 spin_unlock_irqrestore(&rxq->lock, flags);
797 iwl_rx_queue_update_write_ptr(priv, rxq);
798 }
799 }
800
801 /**
802 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
803 *
804 * When moving to rx_free an SKB is allocated for the slot.
805 *
806 * Also restock the Rx queue via iwl_rx_queue_restock.
807 * This is called as a scheduled work item (except for during initialization)
808 */
809 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
810 {
811 struct iwl_rx_queue *rxq = &priv->rxq;
812 struct list_head *element;
813 struct iwl_rx_mem_buffer *rxb;
814 struct page *page;
815 unsigned long flags;
816 gfp_t gfp_mask = priority;
817
818 while (1) {
819 spin_lock_irqsave(&rxq->lock, flags);
820 if (list_empty(&rxq->rx_used)) {
821 spin_unlock_irqrestore(&rxq->lock, flags);
822 return;
823 }
824 spin_unlock_irqrestore(&rxq->lock, flags);
825
826 if (rxq->free_count > RX_LOW_WATERMARK)
827 gfp_mask |= __GFP_NOWARN;
828
829 if (priv->hw_params.rx_page_order > 0)
830 gfp_mask |= __GFP_COMP;
831
832 /* Alloc a new receive buffer */
833 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
834 if (!page) {
835 if (net_ratelimit())
836 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
837 "order: %d\n",
838 priv->hw_params.rx_page_order);
839
840 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
841 net_ratelimit())
842 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
843 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
844 rxq->free_count);
845 /* We don't reschedule replenish work here -- we will
846 * call the restock method and if it still needs
847 * more buffers it will schedule replenish */
848 return;
849 }
850
851 spin_lock_irqsave(&rxq->lock, flags);
852
853 if (list_empty(&rxq->rx_used)) {
854 spin_unlock_irqrestore(&rxq->lock, flags);
855 __free_pages(page, priv->hw_params.rx_page_order);
856 return;
857 }
858 element = rxq->rx_used.next;
859 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
860 list_del(element);
861
862 spin_unlock_irqrestore(&rxq->lock, flags);
863
864 BUG_ON(rxb->page);
865 rxb->page = page;
866 /* Get physical address of the RB */
867 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
868 PAGE_SIZE << priv->hw_params.rx_page_order,
869 PCI_DMA_FROMDEVICE);
870 /* dma address must be no more than 36 bits */
871 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
872 /* and also 256 byte aligned! */
873 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
874
875 spin_lock_irqsave(&rxq->lock, flags);
876
877 list_add_tail(&rxb->list, &rxq->rx_free);
878 rxq->free_count++;
879 priv->alloc_rxb_page++;
880
881 spin_unlock_irqrestore(&rxq->lock, flags);
882 }
883 }
884
885 void iwlagn_rx_replenish(struct iwl_priv *priv)
886 {
887 unsigned long flags;
888
889 iwlagn_rx_allocate(priv, GFP_KERNEL);
890
891 spin_lock_irqsave(&priv->lock, flags);
892 iwlagn_rx_queue_restock(priv);
893 spin_unlock_irqrestore(&priv->lock, flags);
894 }
895
896 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
897 {
898 iwlagn_rx_allocate(priv, GFP_ATOMIC);
899
900 iwlagn_rx_queue_restock(priv);
901 }
902
903 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
904 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
905 * This free routine walks the list of POOL entries and if SKB is set to
906 * non NULL it is unmapped and freed
907 */
908 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
909 {
910 int i;
911 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
912 if (rxq->pool[i].page != NULL) {
913 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
914 PAGE_SIZE << priv->hw_params.rx_page_order,
915 PCI_DMA_FROMDEVICE);
916 __iwl_free_pages(priv, rxq->pool[i].page);
917 rxq->pool[i].page = NULL;
918 }
919 }
920
921 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
922 rxq->bd_dma);
923 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
924 rxq->rb_stts, rxq->rb_stts_dma);
925 rxq->bd = NULL;
926 rxq->rb_stts = NULL;
927 }
928
929 int iwlagn_rxq_stop(struct iwl_priv *priv)
930 {
931
932 /* stop Rx DMA */
933 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
934 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
935 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
936
937 return 0;
938 }
939
940 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
941 {
942 int idx = 0;
943 int band_offset = 0;
944
945 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
946 if (rate_n_flags & RATE_MCS_HT_MSK) {
947 idx = (rate_n_flags & 0xff);
948 return idx;
949 /* Legacy rate format, search for match in table */
950 } else {
951 if (band == IEEE80211_BAND_5GHZ)
952 band_offset = IWL_FIRST_OFDM_RATE;
953 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
954 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
955 return idx - band_offset;
956 }
957
958 return -1;
959 }
960
961 /* Calc max signal level (dBm) among 3 possible receivers */
962 static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
963 struct iwl_rx_phy_res *rx_resp)
964 {
965 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
966 }
967
968 static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
969 {
970 u32 decrypt_out = 0;
971
972 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
973 RX_RES_STATUS_STATION_FOUND)
974 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
975 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
976
977 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
978
979 /* packet was not encrypted */
980 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
981 RX_RES_STATUS_SEC_TYPE_NONE)
982 return decrypt_out;
983
984 /* packet was encrypted with unknown alg */
985 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
986 RX_RES_STATUS_SEC_TYPE_ERR)
987 return decrypt_out;
988
989 /* decryption was not done in HW */
990 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
991 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
992 return decrypt_out;
993
994 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
995
996 case RX_RES_STATUS_SEC_TYPE_CCMP:
997 /* alg is CCM: check MIC only */
998 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
999 /* Bad MIC */
1000 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1001 else
1002 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1003
1004 break;
1005
1006 case RX_RES_STATUS_SEC_TYPE_TKIP:
1007 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
1008 /* Bad TTAK */
1009 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
1010 break;
1011 }
1012 /* fall through if TTAK OK */
1013 default:
1014 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
1015 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
1016 else
1017 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
1018 break;
1019 }
1020
1021 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
1022 decrypt_in, decrypt_out);
1023
1024 return decrypt_out;
1025 }
1026
1027 static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
1028 struct ieee80211_hdr *hdr,
1029 u16 len,
1030 u32 ampdu_status,
1031 struct iwl_rx_mem_buffer *rxb,
1032 struct ieee80211_rx_status *stats)
1033 {
1034 struct sk_buff *skb;
1035 __le16 fc = hdr->frame_control;
1036
1037 /* We only process data packets if the interface is open */
1038 if (unlikely(!priv->is_open)) {
1039 IWL_DEBUG_DROP_LIMIT(priv,
1040 "Dropping packet while interface is not open.\n");
1041 return;
1042 }
1043
1044 /* In case of HW accelerated crypto and bad decryption, drop */
1045 if (!priv->cfg->mod_params->sw_crypto &&
1046 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
1047 return;
1048
1049 skb = dev_alloc_skb(128);
1050 if (!skb) {
1051 IWL_ERR(priv, "dev_alloc_skb failed\n");
1052 return;
1053 }
1054
1055 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
1056
1057 iwl_update_stats(priv, false, fc, len);
1058 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
1059
1060 ieee80211_rx(priv->hw, skb);
1061 priv->alloc_rxb_page--;
1062 rxb->page = NULL;
1063 }
1064
1065 /* Called for REPLY_RX (legacy ABG frames), or
1066 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
1067 void iwlagn_rx_reply_rx(struct iwl_priv *priv,
1068 struct iwl_rx_mem_buffer *rxb)
1069 {
1070 struct ieee80211_hdr *header;
1071 struct ieee80211_rx_status rx_status;
1072 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1073 struct iwl_rx_phy_res *phy_res;
1074 __le32 rx_pkt_status;
1075 struct iwl_rx_mpdu_res_start *amsdu;
1076 u32 len;
1077 u32 ampdu_status;
1078 u32 rate_n_flags;
1079
1080 /**
1081 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
1082 * REPLY_RX: physical layer info is in this buffer
1083 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
1084 * command and cached in priv->last_phy_res
1085 *
1086 * Here we set up local variables depending on which command is
1087 * received.
1088 */
1089 if (pkt->hdr.cmd == REPLY_RX) {
1090 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
1091 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
1092 + phy_res->cfg_phy_cnt);
1093
1094 len = le16_to_cpu(phy_res->byte_count);
1095 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
1096 phy_res->cfg_phy_cnt + len);
1097 ampdu_status = le32_to_cpu(rx_pkt_status);
1098 } else {
1099 if (!priv->_agn.last_phy_res_valid) {
1100 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
1101 return;
1102 }
1103 phy_res = &priv->_agn.last_phy_res;
1104 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
1105 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
1106 len = le16_to_cpu(amsdu->byte_count);
1107 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
1108 ampdu_status = iwlagn_translate_rx_status(priv,
1109 le32_to_cpu(rx_pkt_status));
1110 }
1111
1112 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
1113 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
1114 phy_res->cfg_phy_cnt);
1115 return;
1116 }
1117
1118 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
1119 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
1120 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
1121 le32_to_cpu(rx_pkt_status));
1122 return;
1123 }
1124
1125 /* This will be used in several places later */
1126 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
1127
1128 /* rx_status carries information about the packet to mac80211 */
1129 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
1130 rx_status.freq =
1131 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
1132 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
1133 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1134 rx_status.rate_idx =
1135 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
1136 rx_status.flag = 0;
1137
1138 /* TSF isn't reliable. In order to allow smooth user experience,
1139 * this W/A doesn't propagate it to the mac80211 */
1140 /*rx_status.flag |= RX_FLAG_TSFT;*/
1141
1142 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1143
1144 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1145 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1146
1147 iwl_dbg_log_rx_data_frame(priv, len, header);
1148 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
1149 rx_status.signal, (unsigned long long)rx_status.mactime);
1150
1151 /*
1152 * "antenna number"
1153 *
1154 * It seems that the antenna field in the phy flags value
1155 * is actually a bit field. This is undefined by radiotap,
1156 * it wants an actual antenna number but I always get "7"
1157 * for most legacy frames I receive indicating that the
1158 * same frame was received on all three RX chains.
1159 *
1160 * I think this field should be removed in favor of a
1161 * new 802.11n radiotap field "RX chains" that is defined
1162 * as a bitmask.
1163 */
1164 rx_status.antenna =
1165 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
1166 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
1167
1168 /* set the preamble flag if appropriate */
1169 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
1170 rx_status.flag |= RX_FLAG_SHORTPRE;
1171
1172 /* Set up the HT phy flags */
1173 if (rate_n_flags & RATE_MCS_HT_MSK)
1174 rx_status.flag |= RX_FLAG_HT;
1175 if (rate_n_flags & RATE_MCS_HT40_MSK)
1176 rx_status.flag |= RX_FLAG_40MHZ;
1177 if (rate_n_flags & RATE_MCS_SGI_MSK)
1178 rx_status.flag |= RX_FLAG_SHORT_GI;
1179
1180 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
1181 rxb, &rx_status);
1182 }
1183
1184 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
1185 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
1186 void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
1187 struct iwl_rx_mem_buffer *rxb)
1188 {
1189 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1190 priv->_agn.last_phy_res_valid = true;
1191 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
1192 sizeof(struct iwl_rx_phy_res));
1193 }
1194
1195 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1196 struct ieee80211_vif *vif,
1197 enum ieee80211_band band,
1198 struct iwl_scan_channel *scan_ch)
1199 {
1200 const struct ieee80211_supported_band *sband;
1201 u16 passive_dwell = 0;
1202 u16 active_dwell = 0;
1203 int added = 0;
1204 u16 channel = 0;
1205
1206 sband = iwl_get_hw_mode(priv, band);
1207 if (!sband) {
1208 IWL_ERR(priv, "invalid band\n");
1209 return added;
1210 }
1211
1212 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1213 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1214
1215 if (passive_dwell <= active_dwell)
1216 passive_dwell = active_dwell + 1;
1217
1218 channel = iwl_get_single_channel_number(priv, band);
1219 if (channel) {
1220 scan_ch->channel = cpu_to_le16(channel);
1221 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1222 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1223 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1224 /* Set txpower levels to defaults */
1225 scan_ch->dsp_atten = 110;
1226 if (band == IEEE80211_BAND_5GHZ)
1227 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1228 else
1229 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1230 added++;
1231 } else
1232 IWL_ERR(priv, "no valid channel found\n");
1233 return added;
1234 }
1235
1236 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1237 struct ieee80211_vif *vif,
1238 enum ieee80211_band band,
1239 u8 is_active, u8 n_probes,
1240 struct iwl_scan_channel *scan_ch)
1241 {
1242 struct ieee80211_channel *chan;
1243 const struct ieee80211_supported_band *sband;
1244 const struct iwl_channel_info *ch_info;
1245 u16 passive_dwell = 0;
1246 u16 active_dwell = 0;
1247 int added, i;
1248 u16 channel;
1249
1250 sband = iwl_get_hw_mode(priv, band);
1251 if (!sband)
1252 return 0;
1253
1254 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1255 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1256
1257 if (passive_dwell <= active_dwell)
1258 passive_dwell = active_dwell + 1;
1259
1260 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1261 chan = priv->scan_request->channels[i];
1262
1263 if (chan->band != band)
1264 continue;
1265
1266 channel = chan->hw_value;
1267 scan_ch->channel = cpu_to_le16(channel);
1268
1269 ch_info = iwl_get_channel_info(priv, band, channel);
1270 if (!is_channel_valid(ch_info)) {
1271 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1272 channel);
1273 continue;
1274 }
1275
1276 if (!is_active || is_channel_passive(ch_info) ||
1277 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1278 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1279 else
1280 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1281
1282 if (n_probes)
1283 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1284
1285 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1286 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1287
1288 /* Set txpower levels to defaults */
1289 scan_ch->dsp_atten = 110;
1290
1291 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1292 * power level:
1293 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1294 */
1295 if (band == IEEE80211_BAND_5GHZ)
1296 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1297 else
1298 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1299
1300 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1301 channel, le32_to_cpu(scan_ch->type),
1302 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1303 "ACTIVE" : "PASSIVE",
1304 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1305 active_dwell : passive_dwell);
1306
1307 scan_ch++;
1308 added++;
1309 }
1310
1311 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1312 return added;
1313 }
1314
1315 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1316 {
1317 struct iwl_host_cmd cmd = {
1318 .id = REPLY_SCAN_CMD,
1319 .len = sizeof(struct iwl_scan_cmd),
1320 .flags = CMD_SIZE_HUGE,
1321 };
1322 struct iwl_scan_cmd *scan;
1323 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1324 u32 rate_flags = 0;
1325 u16 cmd_len;
1326 u16 rx_chain = 0;
1327 enum ieee80211_band band;
1328 u8 n_probes = 0;
1329 u8 rx_ant = priv->hw_params.valid_rx_ant;
1330 u8 rate;
1331 bool is_active = false;
1332 int chan_mod;
1333 u8 active_chains;
1334 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1335 int ret;
1336
1337 lockdep_assert_held(&priv->mutex);
1338
1339 if (vif)
1340 ctx = iwl_rxon_ctx_from_vif(vif);
1341
1342 if (!priv->scan_cmd) {
1343 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1344 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1345 if (!priv->scan_cmd) {
1346 IWL_DEBUG_SCAN(priv,
1347 "fail to allocate memory for scan\n");
1348 return -ENOMEM;
1349 }
1350 }
1351 scan = priv->scan_cmd;
1352 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1353
1354 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1355 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1356
1357 if (iwl_is_any_associated(priv)) {
1358 u16 interval = 0;
1359 u32 extra;
1360 u32 suspend_time = 100;
1361 u32 scan_suspend_time = 100;
1362 unsigned long flags;
1363
1364 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1365 spin_lock_irqsave(&priv->lock, flags);
1366 if (priv->is_internal_short_scan)
1367 interval = 0;
1368 else
1369 interval = vif->bss_conf.beacon_int;
1370 spin_unlock_irqrestore(&priv->lock, flags);
1371
1372 scan->suspend_time = 0;
1373 scan->max_out_time = cpu_to_le32(200 * 1024);
1374 if (!interval)
1375 interval = suspend_time;
1376
1377 extra = (suspend_time / interval) << 22;
1378 scan_suspend_time = (extra |
1379 ((suspend_time % interval) * 1024));
1380 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1381 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1382 scan_suspend_time, interval);
1383 }
1384
1385 if (priv->is_internal_short_scan) {
1386 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1387 } else if (priv->scan_request->n_ssids) {
1388 int i, p = 0;
1389 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1390 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1391 /* always does wildcard anyway */
1392 if (!priv->scan_request->ssids[i].ssid_len)
1393 continue;
1394 scan->direct_scan[p].id = WLAN_EID_SSID;
1395 scan->direct_scan[p].len =
1396 priv->scan_request->ssids[i].ssid_len;
1397 memcpy(scan->direct_scan[p].ssid,
1398 priv->scan_request->ssids[i].ssid,
1399 priv->scan_request->ssids[i].ssid_len);
1400 n_probes++;
1401 p++;
1402 }
1403 is_active = true;
1404 } else
1405 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1406
1407 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1408 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1409 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1410
1411 switch (priv->scan_band) {
1412 case IEEE80211_BAND_2GHZ:
1413 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1414 chan_mod = le32_to_cpu(
1415 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1416 RXON_FLG_CHANNEL_MODE_MSK)
1417 >> RXON_FLG_CHANNEL_MODE_POS;
1418 if (chan_mod == CHANNEL_MODE_PURE_40) {
1419 rate = IWL_RATE_6M_PLCP;
1420 } else {
1421 rate = IWL_RATE_1M_PLCP;
1422 rate_flags = RATE_MCS_CCK_MSK;
1423 }
1424 /*
1425 * Internal scans are passive, so we can indiscriminately set
1426 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1427 */
1428 if (priv->cfg->bt_params &&
1429 priv->cfg->bt_params->advanced_bt_coexist)
1430 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1431 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
1432 break;
1433 case IEEE80211_BAND_5GHZ:
1434 rate = IWL_RATE_6M_PLCP;
1435 /*
1436 * If active scanning is requested but a certain channel is
1437 * marked passive, we can do active scanning if we detect
1438 * transmissions.
1439 *
1440 * There is an issue with some firmware versions that triggers
1441 * a sysassert on a "good CRC threshold" of zero (== disabled),
1442 * on a radar channel even though this means that we should NOT
1443 * send probes.
1444 *
1445 * The "good CRC threshold" is the number of frames that we
1446 * need to receive during our dwell time on a channel before
1447 * sending out probes -- setting this to a huge value will
1448 * mean we never reach it, but at the same time work around
1449 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1450 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1451 */
1452 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1453 IWL_GOOD_CRC_TH_NEVER;
1454 break;
1455 default:
1456 IWL_WARN(priv, "Invalid scan band\n");
1457 return -EIO;
1458 }
1459
1460 band = priv->scan_band;
1461
1462 if (priv->cfg->scan_rx_antennas[band])
1463 rx_ant = priv->cfg->scan_rx_antennas[band];
1464
1465 if (priv->cfg->scan_tx_antennas[band])
1466 scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
1467
1468 if (priv->cfg->bt_params &&
1469 priv->cfg->bt_params->advanced_bt_coexist &&
1470 priv->bt_full_concurrent) {
1471 /* operated as 1x1 in full concurrency mode */
1472 scan_tx_antennas = first_antenna(
1473 priv->cfg->scan_tx_antennas[band]);
1474 }
1475
1476 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1477 scan_tx_antennas);
1478 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1479 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1480
1481 /* In power save mode use one chain, otherwise use all chains */
1482 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1483 /* rx_ant has been set to all valid chains previously */
1484 active_chains = rx_ant &
1485 ((u8)(priv->chain_noise_data.active_chains));
1486 if (!active_chains)
1487 active_chains = rx_ant;
1488
1489 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1490 priv->chain_noise_data.active_chains);
1491
1492 rx_ant = first_antenna(active_chains);
1493 }
1494 if (priv->cfg->bt_params &&
1495 priv->cfg->bt_params->advanced_bt_coexist &&
1496 priv->bt_full_concurrent) {
1497 /* operated as 1x1 in full concurrency mode */
1498 rx_ant = first_antenna(rx_ant);
1499 }
1500
1501 /* MIMO is not used here, but value is required */
1502 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1503 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1504 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1505 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1506 scan->rx_chain = cpu_to_le16(rx_chain);
1507 if (!priv->is_internal_short_scan) {
1508 cmd_len = iwl_fill_probe_req(priv,
1509 (struct ieee80211_mgmt *)scan->data,
1510 vif->addr,
1511 priv->scan_request->ie,
1512 priv->scan_request->ie_len,
1513 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1514 } else {
1515 /* use bcast addr, will not be transmitted but must be valid */
1516 cmd_len = iwl_fill_probe_req(priv,
1517 (struct ieee80211_mgmt *)scan->data,
1518 iwl_bcast_addr, NULL, 0,
1519 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1520
1521 }
1522 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1523
1524 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1525 RXON_FILTER_BCON_AWARE_MSK);
1526
1527 if (priv->is_internal_short_scan) {
1528 scan->channel_count =
1529 iwl_get_single_channel_for_scan(priv, vif, band,
1530 (void *)&scan->data[le16_to_cpu(
1531 scan->tx_cmd.len)]);
1532 } else {
1533 scan->channel_count =
1534 iwl_get_channels_for_scan(priv, vif, band,
1535 is_active, n_probes,
1536 (void *)&scan->data[le16_to_cpu(
1537 scan->tx_cmd.len)]);
1538 }
1539 if (scan->channel_count == 0) {
1540 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1541 return -EIO;
1542 }
1543
1544 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1545 scan->channel_count * sizeof(struct iwl_scan_channel);
1546 cmd.data = scan;
1547 scan->len = cpu_to_le16(cmd.len);
1548
1549 if (priv->cfg->ops->hcmd->set_pan_params) {
1550 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1551 if (ret)
1552 return ret;
1553 }
1554
1555 set_bit(STATUS_SCAN_HW, &priv->status);
1556 ret = iwl_send_cmd_sync(priv, &cmd);
1557 if (ret) {
1558 clear_bit(STATUS_SCAN_HW, &priv->status);
1559 if (priv->cfg->ops->hcmd->set_pan_params)
1560 priv->cfg->ops->hcmd->set_pan_params(priv);
1561 }
1562
1563 return ret;
1564 }
1565
1566 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1567 struct ieee80211_vif *vif, bool add)
1568 {
1569 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1570
1571 if (add)
1572 return iwl_add_bssid_station(priv, vif_priv->ctx,
1573 vif->bss_conf.bssid, true,
1574 &vif_priv->ibss_bssid_sta_id);
1575 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1576 vif->bss_conf.bssid);
1577 }
1578
1579 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1580 int sta_id, int tid, int freed)
1581 {
1582 lockdep_assert_held(&priv->sta_lock);
1583
1584 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1585 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1586 else {
1587 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1588 priv->stations[sta_id].tid[tid].tfds_in_queue,
1589 freed);
1590 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1591 }
1592 }
1593
1594 #define IWL_FLUSH_WAIT_MS 2000
1595
1596 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1597 {
1598 struct iwl_tx_queue *txq;
1599 struct iwl_queue *q;
1600 int cnt;
1601 unsigned long now = jiffies;
1602 int ret = 0;
1603
1604 /* waiting for all the tx frames complete might take a while */
1605 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1606 if (cnt == priv->cmd_queue)
1607 continue;
1608 txq = &priv->txq[cnt];
1609 q = &txq->q;
1610 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1611 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1612 msleep(1);
1613
1614 if (q->read_ptr != q->write_ptr) {
1615 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1616 ret = -ETIMEDOUT;
1617 break;
1618 }
1619 }
1620 return ret;
1621 }
1622
1623 #define IWL_TX_QUEUE_MSK 0xfffff
1624
1625 /**
1626 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1627 *
1628 * pre-requirements:
1629 * 1. acquire mutex before calling
1630 * 2. make sure rf is on and not in exit state
1631 */
1632 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1633 {
1634 struct iwl_txfifo_flush_cmd flush_cmd;
1635 struct iwl_host_cmd cmd = {
1636 .id = REPLY_TXFIFO_FLUSH,
1637 .len = sizeof(struct iwl_txfifo_flush_cmd),
1638 .flags = CMD_SYNC,
1639 .data = &flush_cmd,
1640 };
1641
1642 might_sleep();
1643
1644 memset(&flush_cmd, 0, sizeof(flush_cmd));
1645 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1646 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1647 if (priv->cfg->sku & IWL_SKU_N)
1648 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1649
1650 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1651 flush_cmd.fifo_control);
1652 flush_cmd.flush_control = cpu_to_le16(flush_control);
1653
1654 return iwl_send_cmd(priv, &cmd);
1655 }
1656
1657 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1658 {
1659 mutex_lock(&priv->mutex);
1660 ieee80211_stop_queues(priv->hw);
1661 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1662 IWL_ERR(priv, "flush request fail\n");
1663 goto done;
1664 }
1665 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1666 iwlagn_wait_tx_queue_empty(priv);
1667 done:
1668 ieee80211_wake_queues(priv->hw);
1669 mutex_unlock(&priv->mutex);
1670 }
1671
1672 /*
1673 * BT coex
1674 */
1675 /*
1676 * Macros to access the lookup table.
1677 *
1678 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1679 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1680 *
1681 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1682 *
1683 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1684 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1685 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1686 *
1687 * These macros encode that format.
1688 */
1689 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1690 wifi_txrx, wifi_sh_ant_req) \
1691 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1692 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1693
1694 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1695 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1696 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1697 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1698 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1699 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1700 wifi_sh_ant_req))))
1701 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1702 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1703 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1704 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1705 wifi_sh_ant_req))
1706 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1707 wifi_req, wifi_prio, wifi_txrx, \
1708 wifi_sh_ant_req) \
1709 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1710 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1711 wifi_sh_ant_req))
1712
1713 #define LUT_WLAN_KILL_OP(lut, op, val) \
1714 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1715 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1716 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1717 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1718 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1719 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1720 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1721 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1722 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1723 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1724 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1725 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1726 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1727
1728 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1729 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1730 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1731 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1732 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1733 wifi_req, wifi_prio, wifi_txrx, \
1734 wifi_sh_ant_req))))
1735 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1736 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1737 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1738 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1739 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1740 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1741 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1742 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1743
1744 static const __le32 iwlagn_def_3w_lookup[12] = {
1745 cpu_to_le32(0xaaaaaaaa),
1746 cpu_to_le32(0xaaaaaaaa),
1747 cpu_to_le32(0xaeaaaaaa),
1748 cpu_to_le32(0xaaaaaaaa),
1749 cpu_to_le32(0xcc00ff28),
1750 cpu_to_le32(0x0000aaaa),
1751 cpu_to_le32(0xcc00aaaa),
1752 cpu_to_le32(0x0000aaaa),
1753 cpu_to_le32(0xc0004000),
1754 cpu_to_le32(0x00004000),
1755 cpu_to_le32(0xf0005000),
1756 cpu_to_le32(0xf0004000),
1757 };
1758
1759 static const __le32 iwlagn_concurrent_lookup[12] = {
1760 cpu_to_le32(0xaaaaaaaa),
1761 cpu_to_le32(0xaaaaaaaa),
1762 cpu_to_le32(0xaaaaaaaa),
1763 cpu_to_le32(0xaaaaaaaa),
1764 cpu_to_le32(0xaaaaaaaa),
1765 cpu_to_le32(0xaaaaaaaa),
1766 cpu_to_le32(0xaaaaaaaa),
1767 cpu_to_le32(0xaaaaaaaa),
1768 cpu_to_le32(0x00000000),
1769 cpu_to_le32(0x00000000),
1770 cpu_to_le32(0x00000000),
1771 cpu_to_le32(0x00000000),
1772 };
1773
1774 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1775 {
1776 struct iwlagn_bt_cmd bt_cmd = {
1777 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1778 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1779 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1780 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1781 };
1782
1783 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1784 sizeof(bt_cmd.bt3_lookup_table));
1785
1786 if (priv->cfg->bt_params)
1787 bt_cmd.prio_boost = priv->cfg->bt_params->bt_prio_boost;
1788 else
1789 bt_cmd.prio_boost = 0;
1790 bt_cmd.kill_ack_mask = priv->kill_ack_mask;
1791 bt_cmd.kill_cts_mask = priv->kill_cts_mask;
1792 bt_cmd.valid = priv->bt_valid;
1793 bt_cmd.tx_prio_boost = 0;
1794 bt_cmd.rx_prio_boost = 0;
1795
1796 /*
1797 * Configure BT coex mode to "no coexistence" when the
1798 * user disabled BT coexistence, we have no interface
1799 * (might be in monitor mode), or the interface is in
1800 * IBSS mode (no proper uCode support for coex then).
1801 */
1802 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1803 bt_cmd.flags = 0;
1804 } else {
1805 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1806 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1807 if (priv->bt_ch_announce)
1808 bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1809 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
1810 }
1811 if (priv->bt_full_concurrent)
1812 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
1813 sizeof(iwlagn_concurrent_lookup));
1814 else
1815 memcpy(bt_cmd.bt3_lookup_table, iwlagn_def_3w_lookup,
1816 sizeof(iwlagn_def_3w_lookup));
1817
1818 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1819 bt_cmd.flags ? "active" : "disabled",
1820 priv->bt_full_concurrent ?
1821 "full concurrency" : "3-wire");
1822
1823 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, sizeof(bt_cmd), &bt_cmd))
1824 IWL_ERR(priv, "failed to send BT Coex Config\n");
1825
1826 /*
1827 * When we are doing a restart, need to also reconfigure BT
1828 * SCO to the device. If not doing a restart, bt_sco_active
1829 * will always be false, so there's no need to have an extra
1830 * variable to check for it.
1831 */
1832 if (priv->bt_sco_active) {
1833 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1834
1835 if (priv->bt_sco_active)
1836 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
1837 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_SCO,
1838 sizeof(sco_cmd), &sco_cmd))
1839 IWL_ERR(priv, "failed to send BT SCO command\n");
1840 }
1841 }
1842
1843 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1844 {
1845 struct iwl_priv *priv =
1846 container_of(work, struct iwl_priv, bt_traffic_change_work);
1847 struct iwl_rxon_context *ctx;
1848 int smps_request = -1;
1849
1850 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1851 priv->bt_traffic_load);
1852
1853 switch (priv->bt_traffic_load) {
1854 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1855 smps_request = IEEE80211_SMPS_AUTOMATIC;
1856 break;
1857 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1858 smps_request = IEEE80211_SMPS_DYNAMIC;
1859 break;
1860 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1861 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1862 smps_request = IEEE80211_SMPS_STATIC;
1863 break;
1864 default:
1865 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1866 priv->bt_traffic_load);
1867 break;
1868 }
1869
1870 mutex_lock(&priv->mutex);
1871
1872 if (priv->cfg->ops->lib->update_chain_flags)
1873 priv->cfg->ops->lib->update_chain_flags(priv);
1874
1875 if (smps_request != -1) {
1876 for_each_context(priv, ctx) {
1877 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1878 ieee80211_request_smps(ctx->vif, smps_request);
1879 }
1880 }
1881
1882 mutex_unlock(&priv->mutex);
1883 }
1884
1885 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1886 struct iwl_bt_uart_msg *uart_msg)
1887 {
1888 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1889 "Update Req = 0x%X",
1890 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1891 BT_UART_MSG_FRAME1MSGTYPE_POS,
1892 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1893 BT_UART_MSG_FRAME1SSN_POS,
1894 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1895 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1896
1897 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1898 "Chl_SeqN = 0x%X, In band = 0x%X",
1899 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1900 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1901 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1902 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1903 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1904 BT_UART_MSG_FRAME2CHLSEQN_POS,
1905 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1906 BT_UART_MSG_FRAME2INBAND_POS);
1907
1908 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1909 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1910 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1911 BT_UART_MSG_FRAME3SCOESCO_POS,
1912 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1913 BT_UART_MSG_FRAME3SNIFF_POS,
1914 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1915 BT_UART_MSG_FRAME3A2DP_POS,
1916 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1917 BT_UART_MSG_FRAME3ACL_POS,
1918 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1919 BT_UART_MSG_FRAME3MASTER_POS,
1920 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1921 BT_UART_MSG_FRAME3OBEX_POS);
1922
1923 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1924 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1925 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1926
1927 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1928 "eSCO Retransmissions = 0x%X",
1929 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1930 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1931 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1932 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1933 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1934 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1935
1936 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1937 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1938 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1939 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1940 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1941
1942 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Inquiry/Page SR Mode = "
1943 "0x%X, Connectable = 0x%X",
1944 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1945 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1946 (BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_MSK & uart_msg->frame7) >>
1947 BT_UART_MSG_FRAME7INQUIRYPAGESRMODE_POS,
1948 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1949 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1950 }
1951
1952 static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
1953 struct iwl_bt_uart_msg *uart_msg)
1954 {
1955 u8 kill_ack_msk;
1956 __le32 bt_kill_ack_msg[2] = {
1957 cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
1958
1959 kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
1960 BT_UART_MSG_FRAME3SNIFF_MSK |
1961 BT_UART_MSG_FRAME3SCOESCO_MSK) &
1962 uart_msg->frame3) == 0) ? 1 : 0;
1963 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
1964 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1965 priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
1966 /* schedule to send runtime bt_config */
1967 queue_work(priv->workqueue, &priv->bt_runtime_config);
1968 }
1969
1970 }
1971
1972 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1973 struct iwl_rx_mem_buffer *rxb)
1974 {
1975 unsigned long flags;
1976 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1977 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1978 struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
1979 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1980 u8 last_traffic_load;
1981
1982 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1983 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1984 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1985 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1986 coex->bt_ci_compliance);
1987 iwlagn_print_uartmsg(priv, uart_msg);
1988
1989 last_traffic_load = priv->notif_bt_traffic_load;
1990 priv->notif_bt_traffic_load = coex->bt_traffic_load;
1991 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1992 if (priv->bt_status != coex->bt_status ||
1993 last_traffic_load != coex->bt_traffic_load) {
1994 if (coex->bt_status) {
1995 /* BT on */
1996 if (!priv->bt_ch_announce)
1997 priv->bt_traffic_load =
1998 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1999 else
2000 priv->bt_traffic_load =
2001 coex->bt_traffic_load;
2002 } else {
2003 /* BT off */
2004 priv->bt_traffic_load =
2005 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
2006 }
2007 priv->bt_status = coex->bt_status;
2008 queue_work(priv->workqueue,
2009 &priv->bt_traffic_change_work);
2010 }
2011 if (priv->bt_sco_active !=
2012 (uart_msg->frame3 & BT_UART_MSG_FRAME3SCOESCO_MSK)) {
2013 priv->bt_sco_active = uart_msg->frame3 &
2014 BT_UART_MSG_FRAME3SCOESCO_MSK;
2015 if (priv->bt_sco_active)
2016 sco_cmd.flags |= IWLAGN_BT_SCO_ACTIVE;
2017 iwl_send_cmd_pdu_async(priv, REPLY_BT_COEX_SCO,
2018 sizeof(sco_cmd), &sco_cmd, NULL);
2019 }
2020 }
2021
2022 iwlagn_set_kill_ack_msk(priv, uart_msg);
2023
2024 /* FIXME: based on notification, adjust the prio_boost */
2025
2026 spin_lock_irqsave(&priv->lock, flags);
2027 priv->bt_ci_compliance = coex->bt_ci_compliance;
2028 spin_unlock_irqrestore(&priv->lock, flags);
2029 }
2030
2031 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
2032 {
2033 iwlagn_rx_handler_setup(priv);
2034 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
2035 iwlagn_bt_coex_profile_notif;
2036 }
2037
2038 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
2039 {
2040 iwlagn_setup_deferred_work(priv);
2041
2042 INIT_WORK(&priv->bt_traffic_change_work,
2043 iwlagn_bt_traffic_change_work);
2044 }
2045
2046 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
2047 {
2048 cancel_work_sync(&priv->bt_traffic_change_work);
2049 }
kernel source for telekom puls (alcatel/mediatek)