1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
47 #include "iwl-eeprom.h"
49 #include "iwl-helpers.h"
51 #include "iwl-3945-led.h"
53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
73 const struct iwl3945_rate_info iwl3945_rates
[IWL_RATE_COUNT_3945
] = {
74 IWL_DECLARE_RATE_INFO(1, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
88 /* 1 = enable the iwl3945_disable_events() function */
89 #define IWL_EVT_DISABLE (0)
90 #define IWL_EVT_DISABLE_SIZE (1532/32)
93 * iwl3945_disable_events - Disable selected events in uCode event log
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
101 void iwl3945_disable_events(struct iwl_priv
*priv
)
104 u32 base
; /* SRAM address of event log header */
105 u32 disable_ptr
; /* SRAM address of event-disable bitmap array */
106 u32 array_size
; /* # of u32 entries in array */
107 u32 evt_disable
[IWL_EVT_DISABLE_SIZE
] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
157 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
158 if (!iwl3945_hw_valid_rtc_data_addr(base
)) {
159 IWL_ERR(priv
, "Invalid event log pointer 0x%08X\n", base
);
163 disable_ptr
= iwl_read_targ_mem(priv
, base
+ (4 * sizeof(u32
)));
164 array_size
= iwl_read_targ_mem(priv
, base
+ (5 * sizeof(u32
)));
166 if (IWL_EVT_DISABLE
&& (array_size
== IWL_EVT_DISABLE_SIZE
)) {
167 IWL_DEBUG_INFO(priv
, "Disabling selected uCode log events at 0x%x\n",
169 for (i
= 0; i
< IWL_EVT_DISABLE_SIZE
; i
++)
170 iwl_write_targ_mem(priv
,
171 disable_ptr
+ (i
* sizeof(u32
)),
175 IWL_DEBUG_INFO(priv
, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv
, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv
, " in SRAM at 0x%x, size %d u32s\n",
178 disable_ptr
, array_size
);
183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp
)
187 for (idx
= 0; idx
< IWL_RATE_COUNT_3945
; idx
++)
188 if (iwl3945_rates
[idx
].plcp
== plcp
)
193 #ifdef CONFIG_IWLWIFI_DEBUG
194 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
196 static const char *iwl3945_get_tx_fail_reason(u32 status
)
198 switch (status
& TX_STATUS_MSK
) {
199 case TX_3945_STATUS_SUCCESS
:
201 TX_STATUS_ENTRY(SHORT_LIMIT
);
202 TX_STATUS_ENTRY(LONG_LIMIT
);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
204 TX_STATUS_ENTRY(MGMNT_ABORT
);
205 TX_STATUS_ENTRY(NEXT_FRAG
);
206 TX_STATUS_ENTRY(LIFE_EXPIRE
);
207 TX_STATUS_ENTRY(DEST_PS
);
208 TX_STATUS_ENTRY(ABORTED
);
209 TX_STATUS_ENTRY(BT_RETRY
);
210 TX_STATUS_ENTRY(STA_INVALID
);
211 TX_STATUS_ENTRY(FRAG_DROPPED
);
212 TX_STATUS_ENTRY(TID_DISABLE
);
213 TX_STATUS_ENTRY(FRAME_FLUSHED
);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
215 TX_STATUS_ENTRY(TX_LOCKED
);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
222 static inline const char *iwl3945_get_tx_fail_reason(u32 status
)
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
233 int iwl3945_rs_next_rate(struct iwl_priv
*priv
, int rate
)
235 int next_rate
= iwl3945_get_prev_ieee_rate(rate
);
237 switch (priv
->band
) {
238 case IEEE80211_BAND_5GHZ
:
239 if (rate
== IWL_RATE_12M_INDEX
)
240 next_rate
= IWL_RATE_9M_INDEX
;
241 else if (rate
== IWL_RATE_6M_INDEX
)
242 next_rate
= IWL_RATE_6M_INDEX
;
244 case IEEE80211_BAND_2GHZ
:
245 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
246 iwl_is_associated(priv
)) {
247 if (rate
== IWL_RATE_11M_INDEX
)
248 next_rate
= IWL_RATE_5M_INDEX
;
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
267 static void iwl3945_tx_queue_reclaim(struct iwl_priv
*priv
,
268 int txq_id
, int index
)
270 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
271 struct iwl_queue
*q
= &txq
->q
;
272 struct iwl_tx_info
*tx_info
;
274 BUG_ON(txq_id
== IWL_CMD_QUEUE_NUM
);
276 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
277 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
279 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
280 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
281 tx_info
->skb
[0] = NULL
;
282 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
285 if (iwl_queue_space(q
) > q
->low_mark
&& (txq_id
>= 0) &&
286 (txq_id
!= IWL_CMD_QUEUE_NUM
) &&
287 priv
->mac80211_registered
)
288 iwl_wake_queue(priv
, txq_id
);
292 * iwl3945_rx_reply_tx - Handle Tx response
294 static void iwl3945_rx_reply_tx(struct iwl_priv
*priv
,
295 struct iwl_rx_mem_buffer
*rxb
)
297 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
298 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
299 int txq_id
= SEQ_TO_QUEUE(sequence
);
300 int index
= SEQ_TO_INDEX(sequence
);
301 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
302 struct ieee80211_tx_info
*info
;
303 struct iwl3945_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
304 u32 status
= le32_to_cpu(tx_resp
->status
);
308 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
309 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
310 "is out of range [0-%d] %d %d\n", txq_id
,
311 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
316 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
317 ieee80211_tx_info_clear_status(info
);
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx
= iwl3945_hwrate_to_plcp_idx(tx_resp
->rate
);
321 if (info
->band
== IEEE80211_BAND_5GHZ
)
322 rate_idx
-= IWL_FIRST_OFDM_RATE
;
324 fail
= tx_resp
->failure_frame
;
326 info
->status
.rates
[0].idx
= rate_idx
;
327 info
->status
.rates
[0].count
= fail
+ 1; /* add final attempt */
329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
330 info
->flags
|= ((status
& TX_STATUS_MSK
) == TX_STATUS_SUCCESS
) ?
331 IEEE80211_TX_STAT_ACK
: 0;
333 IWL_DEBUG_TX(priv
, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
334 txq_id
, iwl3945_get_tx_fail_reason(status
), status
,
335 tx_resp
->rate
, tx_resp
->failure_frame
);
337 IWL_DEBUG_TX_REPLY(priv
, "Tx queue reclaim %d\n", index
);
338 iwl3945_tx_queue_reclaim(priv
, txq_id
, index
);
340 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
341 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
346 /*****************************************************************************
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
350 * RX handler implementations
352 *****************************************************************************/
354 void iwl3945_hw_rx_statistics(struct iwl_priv
*priv
,
355 struct iwl_rx_mem_buffer
*rxb
)
357 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
358 IWL_DEBUG_RX(priv
, "Statistics notification received (%d vs %d).\n",
359 (int)sizeof(struct iwl3945_notif_statistics
),
360 le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
);
362 memcpy(&priv
->_3945
.statistics
, pkt
->u
.raw
, sizeof(priv
->_3945
.statistics
));
365 /******************************************************************************
367 * Misc. internal state and helper functions
369 ******************************************************************************/
370 #ifdef CONFIG_IWLWIFI_DEBUG
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
379 static void _iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
380 struct iwl_rx_packet
*pkt
,
381 struct ieee80211_hdr
*header
, int group100
)
384 u32 print_summary
= 0;
385 u32 print_dump
= 0; /* set to 1 to dump all frames' contents */
401 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
402 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
403 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
404 u8
*data
= IWL_RX_DATA(pkt
);
407 fc
= header
->frame_control
;
408 seq_ctl
= le16_to_cpu(header
->seq_ctrl
);
411 channel
= le16_to_cpu(rx_hdr
->channel
);
412 phy_flags
= le16_to_cpu(rx_hdr
->phy_flags
);
413 length
= le16_to_cpu(rx_hdr
->len
);
415 /* end-of-frame status and timestamp */
416 status
= le32_to_cpu(rx_end
->status
);
417 bcn_tmr
= le32_to_cpu(rx_end
->beacon_timestamp
);
418 tsf_low
= le64_to_cpu(rx_end
->timestamp
) & 0x0ffffffff;
419 tsf
= le64_to_cpu(rx_end
->timestamp
);
421 /* signal statistics */
422 rssi
= rx_stats
->rssi
;
424 sig_avg
= le16_to_cpu(rx_stats
->sig_avg
);
425 noise_diff
= le16_to_cpu(rx_stats
->noise_diff
);
427 to_us
= !compare_ether_addr(header
->addr1
, priv
->mac_addr
);
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
431 if (to_us
&& (fc
& ~cpu_to_le16(IEEE80211_FCTL_PROTECTED
)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS
| IEEE80211_FTYPE_DATA
)) {
435 print_summary
= 1; /* print each frame */
436 else if (priv
->framecnt_to_us
< 100) {
437 priv
->framecnt_to_us
++;
440 priv
->framecnt_to_us
= 0;
445 /* print summary for all other frames */
455 else if (ieee80211_has_retry(fc
))
457 else if (ieee80211_is_assoc_resp(fc
))
459 else if (ieee80211_is_reassoc_resp(fc
))
461 else if (ieee80211_is_probe_resp(fc
)) {
463 print_dump
= 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc
)) {
466 print_dump
= 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc
))
469 else if (ieee80211_is_auth(fc
))
471 else if (ieee80211_is_deauth(fc
))
473 else if (ieee80211_is_disassoc(fc
))
478 rate
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
482 rate
= iwl3945_rates
[rate
].ieee
/ 2;
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
488 IWL_DEBUG_RX(priv
, "%s: mhd=0x%04x, dst=0x%02x, "
489 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
490 title
, le16_to_cpu(fc
), header
->addr1
[5],
491 length
, rssi
, channel
, rate
);
493 /* src/dst addresses assume managed mode */
494 IWL_DEBUG_RX(priv
, "%s: 0x%04x, dst=0x%02x, "
495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
497 title
, le16_to_cpu(fc
), header
->addr1
[5],
498 header
->addr3
[5], rssi
,
499 tsf_low
- priv
->scan_start_tsf
,
504 iwl_print_hex_dump(priv
, IWL_DL_RX
, data
, length
);
507 static void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
508 struct iwl_rx_packet
*pkt
,
509 struct ieee80211_hdr
*header
, int group100
)
511 if (iwl_get_debug_level(priv
) & IWL_DL_RX
)
512 _iwl3945_dbg_report_frame(priv
, pkt
, header
, group100
);
516 static inline void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
517 struct iwl_rx_packet
*pkt
,
518 struct ieee80211_hdr
*header
, int group100
)
523 /* This is necessary only for a number of statistics, see the caller. */
524 static int iwl3945_is_network_packet(struct iwl_priv
*priv
,
525 struct ieee80211_hdr
*header
)
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv
->iw_mode
) {
530 case NL80211_IFTYPE_ADHOC
: /* Header: Dest. | Source | BSSID */
531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header
->addr3
, priv
->bssid
);
533 case NL80211_IFTYPE_STATION
: /* Header: Dest. | AP{BSSID} | Source */
534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header
->addr2
, priv
->bssid
);
541 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv
*priv
,
542 struct iwl_rx_mem_buffer
*rxb
,
543 struct ieee80211_rx_status
*stats
)
545 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
546 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
547 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
548 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
549 u16 len
= le16_to_cpu(rx_hdr
->len
);
551 __le16 fc
= hdr
->frame_control
;
553 /* We received data from the HW, so stop the watchdog */
554 if (unlikely(len
+ IWL39_RX_FRAME_SIZE
>
555 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
)) {
556 IWL_DEBUG_DROP(priv
, "Corruption detected!\n");
560 /* We only process data packets if the interface is open */
561 if (unlikely(!priv
->is_open
)) {
562 IWL_DEBUG_DROP_LIMIT(priv
,
563 "Dropping packet while interface is not open.\n");
567 skb
= dev_alloc_skb(128);
569 IWL_ERR(priv
, "dev_alloc_skb failed\n");
573 if (!iwl3945_mod_params
.sw_crypto
)
574 iwl_set_decrypted_flag(priv
,
575 (struct ieee80211_hdr
*)rxb_addr(rxb
),
576 le32_to_cpu(rx_end
->status
), stats
);
578 skb_add_rx_frag(skb
, 0, rxb
->page
,
579 (void *)rx_hdr
->payload
- (void *)pkt
, len
);
581 iwl_update_stats(priv
, false, fc
, len
);
582 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
584 ieee80211_rx(priv
->hw
, skb
);
585 priv
->alloc_rxb_page
--;
589 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
591 static void iwl3945_rx_reply_rx(struct iwl_priv
*priv
,
592 struct iwl_rx_mem_buffer
*rxb
)
594 struct ieee80211_hdr
*header
;
595 struct ieee80211_rx_status rx_status
;
596 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
597 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
598 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
599 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
600 u16 rx_stats_sig_avg __maybe_unused
= le16_to_cpu(rx_stats
->sig_avg
);
601 u16 rx_stats_noise_diff __maybe_unused
= le16_to_cpu(rx_stats
->noise_diff
);
605 rx_status
.mactime
= le64_to_cpu(rx_end
->timestamp
);
607 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr
->channel
));
608 rx_status
.band
= (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
609 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
611 rx_status
.rate_idx
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
612 if (rx_status
.band
== IEEE80211_BAND_5GHZ
)
613 rx_status
.rate_idx
-= IWL_FIRST_OFDM_RATE
;
615 rx_status
.antenna
= (le16_to_cpu(rx_hdr
->phy_flags
) &
616 RX_RES_PHY_FLAGS_ANTENNA_MSK
) >> 4;
618 /* set the preamble flag if appropriate */
619 if (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
620 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
622 if ((unlikely(rx_stats
->phy_count
> 20))) {
623 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
624 rx_stats
->phy_count
);
628 if (!(rx_end
->status
& RX_RES_STATUS_NO_CRC32_ERROR
)
629 || !(rx_end
->status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
630 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n", rx_end
->status
);
636 /* Convert 3945's rssi indicator to dBm */
637 rx_status
.signal
= rx_stats
->rssi
- IWL39_RSSI_OFFSET
;
639 IWL_DEBUG_STATS(priv
, "Rssi %d sig_avg %d noise_diff %d\n",
640 rx_status
.signal
, rx_stats_sig_avg
,
641 rx_stats_noise_diff
);
643 header
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
645 network_packet
= iwl3945_is_network_packet(priv
, header
);
647 IWL_DEBUG_STATS_LIMIT(priv
, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
648 network_packet
? '*' : ' ',
649 le16_to_cpu(rx_hdr
->channel
),
650 rx_status
.signal
, rx_status
.signal
,
653 /* Set "1" to report good data frames in groups of 100 */
654 iwl3945_dbg_report_frame(priv
, pkt
, header
, 1);
655 iwl_dbg_log_rx_data_frame(priv
, le16_to_cpu(rx_hdr
->len
), header
);
657 if (network_packet
) {
658 priv
->_3945
.last_beacon_time
=
659 le32_to_cpu(rx_end
->beacon_timestamp
);
660 priv
->_3945
.last_tsf
= le64_to_cpu(rx_end
->timestamp
);
661 priv
->_3945
.last_rx_rssi
= rx_status
.signal
;
664 iwl3945_pass_packet_to_mac80211(priv
, rxb
, &rx_status
);
667 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
668 struct iwl_tx_queue
*txq
,
669 dma_addr_t addr
, u16 len
, u8 reset
, u8 pad
)
673 struct iwl3945_tfd
*tfd
, *tfd_tmp
;
676 tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
677 tfd
= &tfd_tmp
[q
->write_ptr
];
680 memset(tfd
, 0, sizeof(*tfd
));
682 count
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
684 if ((count
>= NUM_TFD_CHUNKS
) || (count
< 0)) {
685 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
690 tfd
->tbs
[count
].addr
= cpu_to_le32(addr
);
691 tfd
->tbs
[count
].len
= cpu_to_le32(len
);
695 tfd
->control_flags
= cpu_to_le32(TFD_CTL_COUNT_SET(count
) |
696 TFD_CTL_PAD_SET(pad
));
702 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
704 * Does NOT advance any indexes
706 void iwl3945_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
708 struct iwl3945_tfd
*tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
709 int index
= txq
->q
.read_ptr
;
710 struct iwl3945_tfd
*tfd
= &tfd_tmp
[index
];
711 struct pci_dev
*dev
= priv
->pci_dev
;
716 counter
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
717 if (counter
> NUM_TFD_CHUNKS
) {
718 IWL_ERR(priv
, "Too many chunks: %i\n", counter
);
719 /* @todo issue fatal error, it is quite serious situation */
725 pci_unmap_single(dev
,
726 pci_unmap_addr(&txq
->meta
[index
], mapping
),
727 pci_unmap_len(&txq
->meta
[index
], len
),
730 /* unmap chunks if any */
732 for (i
= 1; i
< counter
; i
++) {
733 pci_unmap_single(dev
, le32_to_cpu(tfd
->tbs
[i
].addr
),
734 le32_to_cpu(tfd
->tbs
[i
].len
), PCI_DMA_TODEVICE
);
735 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
736 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[0];
737 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
738 /* Can be called from interrupt context */
739 dev_kfree_skb_any(skb
);
740 txq
->txb
[txq
->q
.read_ptr
].skb
[0] = NULL
;
748 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
751 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv
*priv
,
752 struct iwl_device_cmd
*cmd
,
753 struct ieee80211_tx_info
*info
,
754 struct ieee80211_hdr
*hdr
,
755 int sta_id
, int tx_id
)
757 u16 hw_value
= ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
;
758 u16 rate_index
= min(hw_value
& 0xffff, IWL_RATE_COUNT_3945
);
764 __le16 fc
= hdr
->frame_control
;
765 struct iwl3945_tx_cmd
*tx_cmd
= (struct iwl3945_tx_cmd
*)cmd
->cmd
.payload
;
767 rate
= iwl3945_rates
[rate_index
].plcp
;
768 tx_flags
= tx_cmd
->tx_flags
;
770 /* We need to figure out how to get the sta->supp_rates while
771 * in this running context */
772 rate_mask
= IWL_RATES_MASK
;
775 /* Set retry limit on DATA packets and Probe Responses*/
776 if (ieee80211_is_probe_resp(fc
))
777 data_retry_limit
= 3;
779 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
780 tx_cmd
->data_retry_limit
= data_retry_limit
;
782 if (tx_id
>= IWL_CMD_QUEUE_NUM
)
787 if (data_retry_limit
< rts_retry_limit
)
788 rts_retry_limit
= data_retry_limit
;
789 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
791 if (ieee80211_is_mgmt(fc
)) {
792 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
793 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
794 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
795 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
796 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
797 if (tx_flags
& TX_CMD_FLG_RTS_MSK
) {
798 tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
799 tx_flags
|= TX_CMD_FLG_CTS_MSK
;
808 tx_cmd
->tx_flags
= tx_flags
;
811 tx_cmd
->supp_rates
[0] =
812 ((rate_mask
& IWL_OFDM_RATES_MASK
) >> IWL_FIRST_OFDM_RATE
) & 0xFF;
815 tx_cmd
->supp_rates
[1] = (rate_mask
& 0xF);
817 IWL_DEBUG_RATE(priv
, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
818 "cck/ofdm mask: 0x%x/0x%x\n", sta_id
,
819 tx_cmd
->rate
, le32_to_cpu(tx_cmd
->tx_flags
),
820 tx_cmd
->supp_rates
[1], tx_cmd
->supp_rates
[0]);
823 u8
iwl3945_sync_sta(struct iwl_priv
*priv
, int sta_id
, u16 tx_rate
, u8 flags
)
825 unsigned long flags_spin
;
826 struct iwl_station_entry
*station
;
828 if (sta_id
== IWL_INVALID_STATION
)
829 return IWL_INVALID_STATION
;
831 spin_lock_irqsave(&priv
->sta_lock
, flags_spin
);
832 station
= &priv
->stations
[sta_id
];
834 station
->sta
.sta
.modify_mask
= STA_MODIFY_TX_RATE_MSK
;
835 station
->sta
.rate_n_flags
= cpu_to_le16(tx_rate
);
836 station
->sta
.mode
= STA_CONTROL_MODIFY_MSK
;
838 spin_unlock_irqrestore(&priv
->sta_lock
, flags_spin
);
840 iwl_send_add_sta(priv
, &station
->sta
, flags
);
841 IWL_DEBUG_RATE(priv
, "SCALE sync station %d to rate %d\n",
846 static int iwl3945_set_pwr_src(struct iwl_priv
*priv
, enum iwl_pwr_src src
)
848 if (src
== IWL_PWR_SRC_VAUX
) {
849 if (pci_pme_capable(priv
->pci_dev
, PCI_D3cold
)) {
850 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
851 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
852 ~APMG_PS_CTRL_MSK_PWR_SRC
);
854 iwl_poll_bit(priv
, CSR_GPIO_IN
,
855 CSR_GPIO_IN_VAL_VAUX_PWR_SRC
,
856 CSR_GPIO_IN_BIT_AUX_POWER
, 5000);
859 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
860 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
861 ~APMG_PS_CTRL_MSK_PWR_SRC
);
863 iwl_poll_bit(priv
, CSR_GPIO_IN
, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC
,
864 CSR_GPIO_IN_BIT_AUX_POWER
, 5000); /* uS */
870 static int iwl3945_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
872 iwl_write_direct32(priv
, FH39_RCSR_RBD_BASE(0), rxq
->dma_addr
);
873 iwl_write_direct32(priv
, FH39_RCSR_RPTR_ADDR(0), rxq
->rb_stts_dma
);
874 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), 0);
875 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0),
876 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE
|
877 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE
|
878 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN
|
879 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128
|
880 (RX_QUEUE_SIZE_LOG
<< FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE
) |
881 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST
|
882 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH
) |
883 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH
);
885 /* fake read to flush all prev I/O */
886 iwl_read_direct32(priv
, FH39_RSSR_CTRL
);
891 static int iwl3945_tx_reset(struct iwl_priv
*priv
)
895 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0x2);
898 iwl_write_prph(priv
, ALM_SCD_ARASTAT_REG
, 0x01);
900 /* all 6 fifo are active */
901 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0x3f);
903 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_1_REG
, 0x010000);
904 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_2_REG
, 0x030002);
905 iwl_write_prph(priv
, ALM_SCD_TXF4MF_REG
, 0x000004);
906 iwl_write_prph(priv
, ALM_SCD_TXF5MF_REG
, 0x000005);
908 iwl_write_direct32(priv
, FH39_TSSR_CBB_BASE
,
909 priv
->_3945
.shared_phys
);
911 iwl_write_direct32(priv
, FH39_TSSR_MSG_CONFIG
,
912 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON
|
913 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON
|
914 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B
|
915 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON
|
916 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON
|
917 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH
|
918 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH
);
925 * iwl3945_txq_ctx_reset - Reset TX queue context
927 * Destroys all DMA structures and initialize them again
929 static int iwl3945_txq_ctx_reset(struct iwl_priv
*priv
)
932 int txq_id
, slots_num
;
934 iwl3945_hw_txq_ctx_free(priv
);
936 /* allocate tx queue structure */
937 rc
= iwl_alloc_txq_mem(priv
);
942 rc
= iwl3945_tx_reset(priv
);
947 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
948 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
949 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
950 rc
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
953 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
961 iwl3945_hw_txq_ctx_free(priv
);
967 * Start up 3945's basic functionality after it has been reset
968 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
969 * NOTE: This does not load uCode nor start the embedded processor
971 static int iwl3945_apm_init(struct iwl_priv
*priv
)
973 int ret
= iwl_apm_init(priv
);
975 /* Clear APMG (NIC's internal power management) interrupts */
976 iwl_write_prph(priv
, APMG_RTC_INT_MSK_REG
, 0x0);
977 iwl_write_prph(priv
, APMG_RTC_INT_STT_REG
, 0xFFFFFFFF);
979 /* Reset radio chip */
980 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
982 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
987 static void iwl3945_nic_config(struct iwl_priv
*priv
)
989 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
993 spin_lock_irqsave(&priv
->lock
, flags
);
995 /* Determine HW type */
996 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &rev_id
);
998 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", rev_id
);
1000 if (rev_id
& PCI_CFG_REV_ID_BIT_RTP
)
1001 IWL_DEBUG_INFO(priv
, "RTP type\n");
1002 else if (rev_id
& PCI_CFG_REV_ID_BIT_BASIC_SKU
) {
1003 IWL_DEBUG_INFO(priv
, "3945 RADIO-MB type\n");
1004 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1005 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB
);
1007 IWL_DEBUG_INFO(priv
, "3945 RADIO-MM type\n");
1008 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1009 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM
);
1012 if (EEPROM_SKU_CAP_OP_MODE_MRC
== eeprom
->sku_cap
) {
1013 IWL_DEBUG_INFO(priv
, "SKU OP mode is mrc\n");
1014 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1015 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC
);
1017 IWL_DEBUG_INFO(priv
, "SKU OP mode is basic\n");
1019 if ((eeprom
->board_revision
& 0xF0) == 0xD0) {
1020 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1021 eeprom
->board_revision
);
1022 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1023 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1025 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1026 eeprom
->board_revision
);
1027 iwl_clear_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1028 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1031 if (eeprom
->almgor_m_version
<= 1) {
1032 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1033 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A
);
1034 IWL_DEBUG_INFO(priv
, "Card M type A version is 0x%X\n",
1035 eeprom
->almgor_m_version
);
1037 IWL_DEBUG_INFO(priv
, "Card M type B version is 0x%X\n",
1038 eeprom
->almgor_m_version
);
1039 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1040 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B
);
1042 spin_unlock_irqrestore(&priv
->lock
, flags
);
1044 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_SW_RF_KILL_ENABLE
)
1045 IWL_DEBUG_RF_KILL(priv
, "SW RF KILL supported in EEPROM.\n");
1047 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_HW_RF_KILL_ENABLE
)
1048 IWL_DEBUG_RF_KILL(priv
, "HW RF KILL supported in EEPROM.\n");
1051 int iwl3945_hw_nic_init(struct iwl_priv
*priv
)
1054 unsigned long flags
;
1055 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
1057 spin_lock_irqsave(&priv
->lock
, flags
);
1058 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
1059 spin_unlock_irqrestore(&priv
->lock
, flags
);
1061 rc
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
1065 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
1067 /* Allocate the RX queue, or reset if it is already allocated */
1069 rc
= iwl_rx_queue_alloc(priv
);
1071 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
1075 iwl3945_rx_queue_reset(priv
, rxq
);
1077 iwl3945_rx_replenish(priv
);
1079 iwl3945_rx_init(priv
, rxq
);
1082 /* Look at using this instead:
1083 rxq->need_update = 1;
1084 iwl_rx_queue_update_write_ptr(priv, rxq);
1087 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), rxq
->write
& ~7);
1089 rc
= iwl3945_txq_ctx_reset(priv
);
1093 set_bit(STATUS_INIT
, &priv
->status
);
1099 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1101 * Destroy all TX DMA queues and structures
1103 void iwl3945_hw_txq_ctx_free(struct iwl_priv
*priv
)
1109 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
;
1111 if (txq_id
== IWL_CMD_QUEUE_NUM
)
1112 iwl_cmd_queue_free(priv
);
1114 iwl_tx_queue_free(priv
, txq_id
);
1116 /* free tx queue structure */
1117 iwl_free_txq_mem(priv
);
1120 void iwl3945_hw_txq_ctx_stop(struct iwl_priv
*priv
)
1125 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0);
1126 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0);
1128 /* reset TFD queues */
1129 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
1130 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
), 0x0);
1131 iwl_poll_direct_bit(priv
, FH39_TSSR_TX_STATUS
,
1132 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id
),
1136 iwl3945_hw_txq_ctx_free(priv
);
1140 * iwl3945_hw_reg_adjust_power_by_temp
1141 * return index delta into power gain settings table
1143 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading
, int old_reading
)
1145 return (new_reading
- old_reading
) * (-11) / 100;
1149 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1151 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature
)
1153 return ((temperature
< -260) || (temperature
> 25)) ? 1 : 0;
1156 int iwl3945_hw_get_temperature(struct iwl_priv
*priv
)
1158 return iwl_read32(priv
, CSR_UCODE_DRV_GP2
);
1162 * iwl3945_hw_reg_txpower_get_temperature
1163 * get the current temperature by reading from NIC
1165 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv
*priv
)
1167 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1170 temperature
= iwl3945_hw_get_temperature(priv
);
1172 /* driver's okay range is -260 to +25.
1173 * human readable okay range is 0 to +285 */
1174 IWL_DEBUG_INFO(priv
, "Temperature: %d\n", temperature
+ IWL_TEMP_CONVERT
);
1176 /* handle insane temp reading */
1177 if (iwl3945_hw_reg_temp_out_of_range(temperature
)) {
1178 IWL_ERR(priv
, "Error bad temperature value %d\n", temperature
);
1180 /* if really really hot(?),
1181 * substitute the 3rd band/group's temp measured at factory */
1182 if (priv
->last_temperature
> 100)
1183 temperature
= eeprom
->groups
[2].temperature
;
1184 else /* else use most recent "sane" value from driver */
1185 temperature
= priv
->last_temperature
;
1188 return temperature
; /* raw, not "human readable" */
1191 /* Adjust Txpower only if temperature variance is greater than threshold.
1193 * Both are lower than older versions' 9 degrees */
1194 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1197 * is_temp_calib_needed - determines if new calibration is needed
1199 * records new temperature in tx_mgr->temperature.
1200 * replaces tx_mgr->last_temperature *only* if calib needed
1201 * (assumes caller will actually do the calibration!). */
1202 static int is_temp_calib_needed(struct iwl_priv
*priv
)
1206 priv
->temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
1207 temp_diff
= priv
->temperature
- priv
->last_temperature
;
1209 /* get absolute value */
1210 if (temp_diff
< 0) {
1211 IWL_DEBUG_POWER(priv
, "Getting cooler, delta %d,\n", temp_diff
);
1212 temp_diff
= -temp_diff
;
1213 } else if (temp_diff
== 0)
1214 IWL_DEBUG_POWER(priv
, "Same temp,\n");
1216 IWL_DEBUG_POWER(priv
, "Getting warmer, delta %d,\n", temp_diff
);
1218 /* if we don't need calibration, *don't* update last_temperature */
1219 if (temp_diff
< IWL_TEMPERATURE_LIMIT_TIMER
) {
1220 IWL_DEBUG_POWER(priv
, "Timed thermal calib not needed\n");
1224 IWL_DEBUG_POWER(priv
, "Timed thermal calib needed\n");
1226 /* assume that caller will actually do calib ...
1227 * update the "last temperature" value */
1228 priv
->last_temperature
= priv
->temperature
;
1232 #define IWL_MAX_GAIN_ENTRIES 78
1233 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1234 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1236 /* radio and DSP power table, each step is 1/2 dB.
1237 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1238 static struct iwl3945_tx_power power_gain_table
[2][IWL_MAX_GAIN_ENTRIES
] = {
1240 {251, 127}, /* 2.4 GHz, highest power */
1317 {3, 95} }, /* 2.4 GHz, lowest power */
1319 {251, 127}, /* 5.x GHz, highest power */
1396 {3, 120} } /* 5.x GHz, lowest power */
1399 static inline u8
iwl3945_hw_reg_fix_power_index(int index
)
1403 if (index
>= IWL_MAX_GAIN_ENTRIES
)
1404 return IWL_MAX_GAIN_ENTRIES
- 1;
1408 /* Kick off thermal recalibration check every 60 seconds */
1409 #define REG_RECALIB_PERIOD (60)
1412 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1414 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1415 * or 6 Mbit (OFDM) rates.
1417 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv
*priv
, u32 scan_tbl_index
,
1418 s32 rate_index
, const s8
*clip_pwrs
,
1419 struct iwl_channel_info
*ch_info
,
1422 struct iwl3945_scan_power_info
*scan_power_info
;
1426 scan_power_info
= &ch_info
->scan_pwr_info
[scan_tbl_index
];
1428 /* use this channel group's 6Mbit clipping/saturation pwr,
1429 * but cap at regulatory scan power restriction (set during init
1430 * based on eeprom channel data) for this channel. */
1431 power
= min(ch_info
->scan_power
, clip_pwrs
[IWL_RATE_6M_INDEX_TABLE
]);
1433 /* further limit to user's max power preference.
1434 * FIXME: Other spectrum management power limitations do not
1435 * seem to apply?? */
1436 power
= min(power
, priv
->tx_power_user_lmt
);
1437 scan_power_info
->requested_power
= power
;
1439 /* find difference between new scan *power* and current "normal"
1440 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1441 * current "normal" temperature-compensated Tx power *index* for
1442 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1444 power_index
= ch_info
->power_info
[rate_index
].power_table_index
1445 - (power
- ch_info
->power_info
1446 [IWL_RATE_6M_INDEX_TABLE
].requested_power
) * 2;
1448 /* store reference index that we use when adjusting *all* scan
1449 * powers. So we can accommodate user (all channel) or spectrum
1450 * management (single channel) power changes "between" temperature
1451 * feedback compensation procedures.
1452 * don't force fit this reference index into gain table; it may be a
1453 * negative number. This will help avoid errors when we're at
1454 * the lower bounds (highest gains, for warmest temperatures)
1457 /* don't exceed table bounds for "real" setting */
1458 power_index
= iwl3945_hw_reg_fix_power_index(power_index
);
1460 scan_power_info
->power_table_index
= power_index
;
1461 scan_power_info
->tpc
.tx_gain
=
1462 power_gain_table
[band_index
][power_index
].tx_gain
;
1463 scan_power_info
->tpc
.dsp_atten
=
1464 power_gain_table
[band_index
][power_index
].dsp_atten
;
1468 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1470 * Configures power settings for all rates for the current channel,
1471 * using values from channel info struct, and send to NIC
1473 static int iwl3945_send_tx_power(struct iwl_priv
*priv
)
1476 const struct iwl_channel_info
*ch_info
= NULL
;
1477 struct iwl3945_txpowertable_cmd txpower
= {
1478 .channel
= priv
->active_rxon
.channel
,
1481 txpower
.band
= (priv
->band
== IEEE80211_BAND_5GHZ
) ? 0 : 1;
1482 ch_info
= iwl_get_channel_info(priv
,
1484 le16_to_cpu(priv
->active_rxon
.channel
));
1487 "Failed to get channel info for channel %d [%d]\n",
1488 le16_to_cpu(priv
->active_rxon
.channel
), priv
->band
);
1492 if (!is_channel_valid(ch_info
)) {
1493 IWL_DEBUG_POWER(priv
, "Not calling TX_PWR_TABLE_CMD on "
1494 "non-Tx channel.\n");
1498 /* fill cmd with power settings for all rates for current channel */
1499 /* Fill OFDM rate */
1500 for (rate_idx
= IWL_FIRST_OFDM_RATE
, i
= 0;
1501 rate_idx
<= IWL39_LAST_OFDM_RATE
; rate_idx
++, i
++) {
1503 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1504 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1506 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1507 le16_to_cpu(txpower
.channel
),
1509 txpower
.power
[i
].tpc
.tx_gain
,
1510 txpower
.power
[i
].tpc
.dsp_atten
,
1511 txpower
.power
[i
].rate
);
1513 /* Fill CCK rates */
1514 for (rate_idx
= IWL_FIRST_CCK_RATE
;
1515 rate_idx
<= IWL_LAST_CCK_RATE
; rate_idx
++, i
++) {
1516 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1517 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1519 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1520 le16_to_cpu(txpower
.channel
),
1522 txpower
.power
[i
].tpc
.tx_gain
,
1523 txpower
.power
[i
].tpc
.dsp_atten
,
1524 txpower
.power
[i
].rate
);
1527 return iwl_send_cmd_pdu(priv
, REPLY_TX_PWR_TABLE_CMD
,
1528 sizeof(struct iwl3945_txpowertable_cmd
),
1534 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1535 * @ch_info: Channel to update. Uses power_info.requested_power.
1537 * Replace requested_power and base_power_index ch_info fields for
1540 * Called if user or spectrum management changes power preferences.
1541 * Takes into account h/w and modulation limitations (clip power).
1543 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1545 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1546 * properly fill out the scan powers, and actual h/w gain settings,
1547 * and send changes to NIC
1549 static int iwl3945_hw_reg_set_new_power(struct iwl_priv
*priv
,
1550 struct iwl_channel_info
*ch_info
)
1552 struct iwl3945_channel_power_info
*power_info
;
1553 int power_changed
= 0;
1555 const s8
*clip_pwrs
;
1558 /* Get this chnlgrp's rate-to-max/clip-powers table */
1559 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1561 /* Get this channel's rate-to-current-power settings table */
1562 power_info
= ch_info
->power_info
;
1564 /* update OFDM Txpower settings */
1565 for (i
= IWL_RATE_6M_INDEX_TABLE
; i
<= IWL_RATE_54M_INDEX_TABLE
;
1566 i
++, ++power_info
) {
1569 /* limit new power to be no more than h/w capability */
1570 power
= min(ch_info
->curr_txpow
, clip_pwrs
[i
]);
1571 if (power
== power_info
->requested_power
)
1574 /* find difference between old and new requested powers,
1575 * update base (non-temp-compensated) power index */
1576 delta_idx
= (power
- power_info
->requested_power
) * 2;
1577 power_info
->base_power_index
-= delta_idx
;
1579 /* save new requested power value */
1580 power_info
->requested_power
= power
;
1585 /* update CCK Txpower settings, based on OFDM 12M setting ...
1586 * ... all CCK power settings for a given channel are the *same*. */
1587 if (power_changed
) {
1589 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1590 requested_power
+ IWL_CCK_FROM_OFDM_POWER_DIFF
;
1592 /* do all CCK rates' iwl3945_channel_power_info structures */
1593 for (i
= IWL_RATE_1M_INDEX_TABLE
; i
<= IWL_RATE_11M_INDEX_TABLE
; i
++) {
1594 power_info
->requested_power
= power
;
1595 power_info
->base_power_index
=
1596 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1597 base_power_index
+ IWL_CCK_FROM_OFDM_INDEX_DIFF
;
1606 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1608 * NOTE: Returned power limit may be less (but not more) than requested,
1609 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1610 * (no consideration for h/w clipping limitations).
1612 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info
*ch_info
)
1617 /* if we're using TGd limits, use lower of TGd or EEPROM */
1618 if (ch_info
->tgd_data
.max_power
!= 0)
1619 max_power
= min(ch_info
->tgd_data
.max_power
,
1620 ch_info
->eeprom
.max_power_avg
);
1622 /* else just use EEPROM limits */
1625 max_power
= ch_info
->eeprom
.max_power_avg
;
1627 return min(max_power
, ch_info
->max_power_avg
);
1631 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1633 * Compensate txpower settings of *all* channels for temperature.
1634 * This only accounts for the difference between current temperature
1635 * and the factory calibration temperatures, and bases the new settings
1636 * on the channel's base_power_index.
1638 * If RxOn is "associated", this sends the new Txpower to NIC!
1640 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv
*priv
)
1642 struct iwl_channel_info
*ch_info
= NULL
;
1643 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1645 const s8
*clip_pwrs
; /* array of h/w max power levels for each rate */
1651 int temperature
= priv
->temperature
;
1653 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1654 for (i
= 0; i
< priv
->channel_count
; i
++) {
1655 ch_info
= &priv
->channel_info
[i
];
1656 a_band
= is_channel_a_band(ch_info
);
1658 /* Get this chnlgrp's factory calibration temperature */
1659 ref_temp
= (s16
)eeprom
->groups
[ch_info
->group_index
].
1662 /* get power index adjustment based on current and factory
1664 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
1667 /* set tx power value for all rates, OFDM and CCK */
1668 for (rate_index
= 0; rate_index
< IWL_RATE_COUNT
;
1671 ch_info
->power_info
[rate_index
].base_power_index
;
1673 /* temperature compensate */
1674 power_idx
+= delta_index
;
1676 /* stay within table range */
1677 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
1678 ch_info
->power_info
[rate_index
].
1679 power_table_index
= (u8
) power_idx
;
1680 ch_info
->power_info
[rate_index
].tpc
=
1681 power_gain_table
[a_band
][power_idx
];
1684 /* Get this chnlgrp's rate-to-max/clip-powers table */
1685 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
1687 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1688 for (scan_tbl_index
= 0;
1689 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
1690 s32 actual_index
= (scan_tbl_index
== 0) ?
1691 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
1692 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
1693 actual_index
, clip_pwrs
,
1698 /* send Txpower command for current channel to ucode */
1699 return priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1702 int iwl3945_hw_reg_set_txpower(struct iwl_priv
*priv
, s8 power
)
1704 struct iwl_channel_info
*ch_info
;
1709 if (priv
->tx_power_user_lmt
== power
) {
1710 IWL_DEBUG_POWER(priv
, "Requested Tx power same as current "
1711 "limit: %ddBm.\n", power
);
1715 IWL_DEBUG_POWER(priv
, "Setting upper limit clamp to %ddBm.\n", power
);
1716 priv
->tx_power_user_lmt
= power
;
1718 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1720 for (i
= 0; i
< priv
->channel_count
; i
++) {
1721 ch_info
= &priv
->channel_info
[i
];
1722 a_band
= is_channel_a_band(ch_info
);
1724 /* find minimum power of all user and regulatory constraints
1725 * (does not consider h/w clipping limitations) */
1726 max_power
= iwl3945_hw_reg_get_ch_txpower_limit(ch_info
);
1727 max_power
= min(power
, max_power
);
1728 if (max_power
!= ch_info
->curr_txpow
) {
1729 ch_info
->curr_txpow
= max_power
;
1731 /* this considers the h/w clipping limitations */
1732 iwl3945_hw_reg_set_new_power(priv
, ch_info
);
1736 /* update txpower settings for all channels,
1737 * send to NIC if associated. */
1738 is_temp_calib_needed(priv
);
1739 iwl3945_hw_reg_comp_txpower_temp(priv
);
1744 static int iwl3945_send_rxon_assoc(struct iwl_priv
*priv
)
1747 struct iwl_rx_packet
*pkt
;
1748 struct iwl3945_rxon_assoc_cmd rxon_assoc
;
1749 struct iwl_host_cmd cmd
= {
1750 .id
= REPLY_RXON_ASSOC
,
1751 .len
= sizeof(rxon_assoc
),
1752 .flags
= CMD_WANT_SKB
,
1753 .data
= &rxon_assoc
,
1755 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1756 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1758 if ((rxon1
->flags
== rxon2
->flags
) &&
1759 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1760 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1761 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1762 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1766 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1767 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1768 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1769 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1770 rxon_assoc
.reserved
= 0;
1772 rc
= iwl_send_cmd_sync(priv
, &cmd
);
1776 pkt
= (struct iwl_rx_packet
*)cmd
.reply_page
;
1777 if (pkt
->hdr
.flags
& IWL_CMD_FAILED_MSK
) {
1778 IWL_ERR(priv
, "Bad return from REPLY_RXON_ASSOC command\n");
1782 iwl_free_pages(priv
, cmd
.reply_page
);
1788 * iwl3945_commit_rxon - commit staging_rxon to hardware
1790 * The RXON command in staging_rxon is committed to the hardware and
1791 * the active_rxon structure is updated with the new data. This
1792 * function correctly transitions out of the RXON_ASSOC_MSK state if
1793 * a HW tune is required based on the RXON structure changes.
1795 static int iwl3945_commit_rxon(struct iwl_priv
*priv
)
1797 /* cast away the const for active_rxon in this function */
1798 struct iwl3945_rxon_cmd
*active_rxon
= (void *)&priv
->active_rxon
;
1799 struct iwl3945_rxon_cmd
*staging_rxon
= (void *)&priv
->staging_rxon
;
1802 !!(priv
->staging_rxon
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
1804 if (!iwl_is_alive(priv
))
1807 /* always get timestamp with Rx frame */
1808 staging_rxon
->flags
|= RXON_FLG_TSF2HOST_MSK
;
1810 /* select antenna */
1811 staging_rxon
->flags
&=
1812 ~(RXON_FLG_DIS_DIV_MSK
| RXON_FLG_ANT_SEL_MSK
);
1813 staging_rxon
->flags
|= iwl3945_get_antenna_flags(priv
);
1815 rc
= iwl_check_rxon_cmd(priv
);
1817 IWL_ERR(priv
, "Invalid RXON configuration. Not committing.\n");
1821 /* If we don't need to send a full RXON, we can use
1822 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1823 * and other flags for the current radio configuration. */
1824 if (!iwl_full_rxon_required(priv
)) {
1825 rc
= iwl_send_rxon_assoc(priv
);
1827 IWL_ERR(priv
, "Error setting RXON_ASSOC "
1828 "configuration (%d).\n", rc
);
1832 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1837 /* If we are currently associated and the new config requires
1838 * an RXON_ASSOC and the new config wants the associated mask enabled,
1839 * we must clear the associated from the active configuration
1840 * before we apply the new config */
1841 if (iwl_is_associated(priv
) && new_assoc
) {
1842 IWL_DEBUG_INFO(priv
, "Toggling associated bit on current RXON\n");
1843 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
1846 * reserved4 and 5 could have been filled by the iwlcore code.
1847 * Let's clear them before pushing to the 3945.
1849 active_rxon
->reserved4
= 0;
1850 active_rxon
->reserved5
= 0;
1851 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1852 sizeof(struct iwl3945_rxon_cmd
),
1853 &priv
->active_rxon
);
1855 /* If the mask clearing failed then we set
1856 * active_rxon back to what it was previously */
1858 active_rxon
->filter_flags
|= RXON_FILTER_ASSOC_MSK
;
1859 IWL_ERR(priv
, "Error clearing ASSOC_MSK on current "
1860 "configuration (%d).\n", rc
);
1863 iwl_clear_ucode_stations(priv
, false);
1864 iwl_restore_stations(priv
);
1867 IWL_DEBUG_INFO(priv
, "Sending RXON\n"
1868 "* with%s RXON_FILTER_ASSOC_MSK\n"
1871 (new_assoc
? "" : "out"),
1872 le16_to_cpu(staging_rxon
->channel
),
1873 staging_rxon
->bssid_addr
);
1876 * reserved4 and 5 could have been filled by the iwlcore code.
1877 * Let's clear them before pushing to the 3945.
1879 staging_rxon
->reserved4
= 0;
1880 staging_rxon
->reserved5
= 0;
1882 iwl_set_rxon_hwcrypto(priv
, !iwl3945_mod_params
.sw_crypto
);
1884 /* Apply the new configuration */
1885 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1886 sizeof(struct iwl3945_rxon_cmd
),
1889 IWL_ERR(priv
, "Error setting new configuration (%d).\n", rc
);
1893 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1896 iwl_clear_ucode_stations(priv
, false);
1897 iwl_restore_stations(priv
);
1900 /* If we issue a new RXON command which required a tune then we must
1901 * send a new TXPOWER command or we won't be able to Tx any frames */
1902 rc
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1904 IWL_ERR(priv
, "Error setting Tx power (%d).\n", rc
);
1908 /* Init the hardware's rate fallback order based on the band */
1909 rc
= iwl3945_init_hw_rate_table(priv
);
1911 IWL_ERR(priv
, "Error setting HW rate table: %02X\n", rc
);
1919 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1921 * -- reset periodic timer
1922 * -- see if temp has changed enough to warrant re-calibration ... if so:
1923 * -- correct coeffs for temp (can reset temp timer)
1924 * -- save this temp as "last",
1925 * -- send new set of gain settings to NIC
1926 * NOTE: This should continue working, even when we're not associated,
1927 * so we can keep our internal table of scan powers current. */
1928 void iwl3945_reg_txpower_periodic(struct iwl_priv
*priv
)
1930 /* This will kick in the "brute force"
1931 * iwl3945_hw_reg_comp_txpower_temp() below */
1932 if (!is_temp_calib_needed(priv
))
1935 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1936 * This is based *only* on current temperature,
1937 * ignoring any previous power measurements */
1938 iwl3945_hw_reg_comp_txpower_temp(priv
);
1941 queue_delayed_work(priv
->workqueue
,
1942 &priv
->_3945
.thermal_periodic
, REG_RECALIB_PERIOD
* HZ
);
1945 static void iwl3945_bg_reg_txpower_periodic(struct work_struct
*work
)
1947 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
1948 _3945
.thermal_periodic
.work
);
1950 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
1953 mutex_lock(&priv
->mutex
);
1954 iwl3945_reg_txpower_periodic(priv
);
1955 mutex_unlock(&priv
->mutex
);
1959 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1962 * This function is used when initializing channel-info structs.
1964 * NOTE: These channel groups do *NOT* match the bands above!
1965 * These channel groups are based on factory-tested channels;
1966 * on A-band, EEPROM's "group frequency" entries represent the top
1967 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1969 static u16
iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv
*priv
,
1970 const struct iwl_channel_info
*ch_info
)
1972 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1973 struct iwl3945_eeprom_txpower_group
*ch_grp
= &eeprom
->groups
[0];
1975 u16 group_index
= 0; /* based on factory calib frequencies */
1978 /* Find the group index for the channel ... don't use index 1(?) */
1979 if (is_channel_a_band(ch_info
)) {
1980 for (group
= 1; group
< 5; group
++) {
1981 grp_channel
= ch_grp
[group
].group_channel
;
1982 if (ch_info
->channel
<= grp_channel
) {
1983 group_index
= group
;
1987 /* group 4 has a few channels *above* its factory cal freq */
1991 group_index
= 0; /* 2.4 GHz, group 0 */
1993 IWL_DEBUG_POWER(priv
, "Chnl %d mapped to grp %d\n", ch_info
->channel
,
1999 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2001 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2002 * into radio/DSP gain settings table for requested power.
2004 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv
*priv
,
2006 s32 setting_index
, s32
*new_index
)
2008 const struct iwl3945_eeprom_txpower_group
*chnl_grp
= NULL
;
2009 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2011 s32 power
= 2 * requested_power
;
2013 const struct iwl3945_eeprom_txpower_sample
*samples
;
2018 chnl_grp
= &eeprom
->groups
[setting_index
];
2019 samples
= chnl_grp
->samples
;
2020 for (i
= 0; i
< 5; i
++) {
2021 if (power
== samples
[i
].power
) {
2022 *new_index
= samples
[i
].gain_index
;
2027 if (power
> samples
[1].power
) {
2030 } else if (power
> samples
[2].power
) {
2033 } else if (power
> samples
[3].power
) {
2041 denominator
= (s32
) samples
[index1
].power
- (s32
) samples
[index0
].power
;
2042 if (denominator
== 0)
2044 gains0
= (s32
) samples
[index0
].gain_index
* (1 << 19);
2045 gains1
= (s32
) samples
[index1
].gain_index
* (1 << 19);
2046 res
= gains0
+ (gains1
- gains0
) *
2047 ((s32
) power
- (s32
) samples
[index0
].power
) / denominator
+
2049 *new_index
= res
>> 19;
2053 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv
*priv
)
2057 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2058 const struct iwl3945_eeprom_txpower_group
*group
;
2060 IWL_DEBUG_POWER(priv
, "Initializing factory calib info from EEPROM\n");
2062 for (i
= 0; i
< IWL_NUM_TX_CALIB_GROUPS
; i
++) {
2063 s8
*clip_pwrs
; /* table of power levels for each rate */
2064 s8 satur_pwr
; /* saturation power for each chnl group */
2065 group
= &eeprom
->groups
[i
];
2067 /* sanity check on factory saturation power value */
2068 if (group
->saturation_power
< 40) {
2069 IWL_WARN(priv
, "Error: saturation power is %d, "
2070 "less than minimum expected 40\n",
2071 group
->saturation_power
);
2076 * Derive requested power levels for each rate, based on
2077 * hardware capabilities (saturation power for band).
2078 * Basic value is 3dB down from saturation, with further
2079 * power reductions for highest 3 data rates. These
2080 * backoffs provide headroom for high rate modulation
2081 * power peaks, without too much distortion (clipping).
2083 /* we'll fill in this array with h/w max power levels */
2084 clip_pwrs
= (s8
*) priv
->_3945
.clip_groups
[i
].clip_powers
;
2086 /* divide factory saturation power by 2 to find -3dB level */
2087 satur_pwr
= (s8
) (group
->saturation_power
>> 1);
2089 /* fill in channel group's nominal powers for each rate */
2090 for (rate_index
= 0;
2091 rate_index
< IWL_RATE_COUNT_3945
; rate_index
++, clip_pwrs
++) {
2092 switch (rate_index
) {
2093 case IWL_RATE_36M_INDEX_TABLE
:
2094 if (i
== 0) /* B/G */
2095 *clip_pwrs
= satur_pwr
;
2097 *clip_pwrs
= satur_pwr
- 5;
2099 case IWL_RATE_48M_INDEX_TABLE
:
2101 *clip_pwrs
= satur_pwr
- 7;
2103 *clip_pwrs
= satur_pwr
- 10;
2105 case IWL_RATE_54M_INDEX_TABLE
:
2107 *clip_pwrs
= satur_pwr
- 9;
2109 *clip_pwrs
= satur_pwr
- 12;
2112 *clip_pwrs
= satur_pwr
;
2120 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2122 * Second pass (during init) to set up priv->channel_info
2124 * Set up Tx-power settings in our channel info database for each VALID
2125 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2126 * and current temperature.
2128 * Since this is based on current temperature (at init time), these values may
2129 * not be valid for very long, but it gives us a starting/default point,
2130 * and allows us to active (i.e. using Tx) scan.
2132 * This does *not* write values to NIC, just sets up our internal table.
2134 int iwl3945_txpower_set_from_eeprom(struct iwl_priv
*priv
)
2136 struct iwl_channel_info
*ch_info
= NULL
;
2137 struct iwl3945_channel_power_info
*pwr_info
;
2138 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2142 const s8
*clip_pwrs
; /* array of power levels for each rate */
2145 u8 pwr_index
, base_pwr_index
, a_band
;
2149 /* save temperature reference,
2150 * so we can determine next time to calibrate */
2151 temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
2152 priv
->last_temperature
= temperature
;
2154 iwl3945_hw_reg_init_channel_groups(priv
);
2156 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2157 for (i
= 0, ch_info
= priv
->channel_info
; i
< priv
->channel_count
;
2159 a_band
= is_channel_a_band(ch_info
);
2160 if (!is_channel_valid(ch_info
))
2163 /* find this channel's channel group (*not* "band") index */
2164 ch_info
->group_index
=
2165 iwl3945_hw_reg_get_ch_grp_index(priv
, ch_info
);
2167 /* Get this chnlgrp's rate->max/clip-powers table */
2168 clip_pwrs
= priv
->_3945
.clip_groups
[ch_info
->group_index
].clip_powers
;
2170 /* calculate power index *adjustment* value according to
2171 * diff between current temperature and factory temperature */
2172 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
2173 eeprom
->groups
[ch_info
->group_index
].
2176 IWL_DEBUG_POWER(priv
, "Delta index for channel %d: %d [%d]\n",
2177 ch_info
->channel
, delta_index
, temperature
+
2180 /* set tx power value for all OFDM rates */
2181 for (rate_index
= 0; rate_index
< IWL_OFDM_RATES
;
2183 s32
uninitialized_var(power_idx
);
2186 /* use channel group's clip-power table,
2187 * but don't exceed channel's max power */
2188 s8 pwr
= min(ch_info
->max_power_avg
,
2189 clip_pwrs
[rate_index
]);
2191 pwr_info
= &ch_info
->power_info
[rate_index
];
2193 /* get base (i.e. at factory-measured temperature)
2194 * power table index for this rate's power */
2195 rc
= iwl3945_hw_reg_get_matched_power_index(priv
, pwr
,
2196 ch_info
->group_index
,
2199 IWL_ERR(priv
, "Invalid power index\n");
2202 pwr_info
->base_power_index
= (u8
) power_idx
;
2204 /* temperature compensate */
2205 power_idx
+= delta_index
;
2207 /* stay within range of gain table */
2208 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
2210 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2211 pwr_info
->requested_power
= pwr
;
2212 pwr_info
->power_table_index
= (u8
) power_idx
;
2213 pwr_info
->tpc
.tx_gain
=
2214 power_gain_table
[a_band
][power_idx
].tx_gain
;
2215 pwr_info
->tpc
.dsp_atten
=
2216 power_gain_table
[a_band
][power_idx
].dsp_atten
;
2219 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2220 pwr_info
= &ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
];
2221 power
= pwr_info
->requested_power
+
2222 IWL_CCK_FROM_OFDM_POWER_DIFF
;
2223 pwr_index
= pwr_info
->power_table_index
+
2224 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2225 base_pwr_index
= pwr_info
->base_power_index
+
2226 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2228 /* stay within table range */
2229 pwr_index
= iwl3945_hw_reg_fix_power_index(pwr_index
);
2230 gain
= power_gain_table
[a_band
][pwr_index
].tx_gain
;
2231 dsp_atten
= power_gain_table
[a_band
][pwr_index
].dsp_atten
;
2233 /* fill each CCK rate's iwl3945_channel_power_info structure
2234 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2235 * NOTE: CCK rates start at end of OFDM rates! */
2236 for (rate_index
= 0;
2237 rate_index
< IWL_CCK_RATES
; rate_index
++) {
2238 pwr_info
= &ch_info
->power_info
[rate_index
+IWL_OFDM_RATES
];
2239 pwr_info
->requested_power
= power
;
2240 pwr_info
->power_table_index
= pwr_index
;
2241 pwr_info
->base_power_index
= base_pwr_index
;
2242 pwr_info
->tpc
.tx_gain
= gain
;
2243 pwr_info
->tpc
.dsp_atten
= dsp_atten
;
2246 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2247 for (scan_tbl_index
= 0;
2248 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
2249 s32 actual_index
= (scan_tbl_index
== 0) ?
2250 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
2251 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
2252 actual_index
, clip_pwrs
, ch_info
, a_band
);
2259 int iwl3945_hw_rxq_stop(struct iwl_priv
*priv
)
2263 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0), 0);
2264 rc
= iwl_poll_direct_bit(priv
, FH39_RSSR_STATUS
,
2265 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
2267 IWL_ERR(priv
, "Can't stop Rx DMA.\n");
2272 int iwl3945_hw_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
2274 int txq_id
= txq
->q
.id
;
2276 struct iwl3945_shared
*shared_data
= priv
->_3945
.shared_virt
;
2278 shared_data
->tx_base_ptr
[txq_id
] = cpu_to_le32((u32
)txq
->q
.dma_addr
);
2280 iwl_write_direct32(priv
, FH39_CBCC_CTRL(txq_id
), 0);
2281 iwl_write_direct32(priv
, FH39_CBCC_BASE(txq_id
), 0);
2283 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
),
2284 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
|
2285 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
|
2286 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
|
2287 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
2288 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
);
2290 /* fake read to flush all prev. writes */
2291 iwl_read32(priv
, FH39_TSSR_CBB_BASE
);
2299 static u16
iwl3945_get_hcmd_size(u8 cmd_id
, u16 len
)
2303 return sizeof(struct iwl3945_rxon_cmd
);
2304 case POWER_TABLE_CMD
:
2305 return sizeof(struct iwl3945_powertable_cmd
);
2312 static u16
iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
2314 struct iwl3945_addsta_cmd
*addsta
= (struct iwl3945_addsta_cmd
*)data
;
2315 addsta
->mode
= cmd
->mode
;
2316 memcpy(&addsta
->sta
, &cmd
->sta
, sizeof(struct sta_id_modify
));
2317 memcpy(&addsta
->key
, &cmd
->key
, sizeof(struct iwl4965_keyinfo
));
2318 addsta
->station_flags
= cmd
->station_flags
;
2319 addsta
->station_flags_msk
= cmd
->station_flags_msk
;
2320 addsta
->tid_disable_tx
= cpu_to_le16(0);
2321 addsta
->rate_n_flags
= cmd
->rate_n_flags
;
2322 addsta
->add_immediate_ba_tid
= cmd
->add_immediate_ba_tid
;
2323 addsta
->remove_immediate_ba_tid
= cmd
->remove_immediate_ba_tid
;
2324 addsta
->add_immediate_ba_ssn
= cmd
->add_immediate_ba_ssn
;
2326 return (u16
)sizeof(struct iwl3945_addsta_cmd
);
2331 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2333 int iwl3945_init_hw_rate_table(struct iwl_priv
*priv
)
2335 int rc
, i
, index
, prev_index
;
2336 struct iwl3945_rate_scaling_cmd rate_cmd
= {
2337 .reserved
= {0, 0, 0},
2339 struct iwl3945_rate_scaling_info
*table
= rate_cmd
.table
;
2341 for (i
= 0; i
< ARRAY_SIZE(iwl3945_rates
); i
++) {
2342 index
= iwl3945_rates
[i
].table_rs_index
;
2344 table
[index
].rate_n_flags
=
2345 iwl3945_hw_set_rate_n_flags(iwl3945_rates
[i
].plcp
, 0);
2346 table
[index
].try_cnt
= priv
->retry_rate
;
2347 prev_index
= iwl3945_get_prev_ieee_rate(i
);
2348 table
[index
].next_rate_index
=
2349 iwl3945_rates
[prev_index
].table_rs_index
;
2352 switch (priv
->band
) {
2353 case IEEE80211_BAND_5GHZ
:
2354 IWL_DEBUG_RATE(priv
, "Select A mode rate scale\n");
2355 /* If one of the following CCK rates is used,
2356 * have it fall back to the 6M OFDM rate */
2357 for (i
= IWL_RATE_1M_INDEX_TABLE
;
2358 i
<= IWL_RATE_11M_INDEX_TABLE
; i
++)
2359 table
[i
].next_rate_index
=
2360 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2362 /* Don't fall back to CCK rates */
2363 table
[IWL_RATE_12M_INDEX_TABLE
].next_rate_index
=
2364 IWL_RATE_9M_INDEX_TABLE
;
2366 /* Don't drop out of OFDM rates */
2367 table
[IWL_RATE_6M_INDEX_TABLE
].next_rate_index
=
2368 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2371 case IEEE80211_BAND_2GHZ
:
2372 IWL_DEBUG_RATE(priv
, "Select B/G mode rate scale\n");
2373 /* If an OFDM rate is used, have it fall back to the
2376 if (!(priv
->_3945
.sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
2377 iwl_is_associated(priv
)) {
2379 index
= IWL_FIRST_CCK_RATE
;
2380 for (i
= IWL_RATE_6M_INDEX_TABLE
;
2381 i
<= IWL_RATE_54M_INDEX_TABLE
; i
++)
2382 table
[i
].next_rate_index
=
2383 iwl3945_rates
[index
].table_rs_index
;
2385 index
= IWL_RATE_11M_INDEX_TABLE
;
2386 /* CCK shouldn't fall back to OFDM... */
2387 table
[index
].next_rate_index
= IWL_RATE_5M_INDEX_TABLE
;
2396 /* Update the rate scaling for control frame Tx */
2397 rate_cmd
.table_id
= 0;
2398 rc
= iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2403 /* Update the rate scaling for data frame Tx */
2404 rate_cmd
.table_id
= 1;
2405 return iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2409 /* Called when initializing driver */
2410 int iwl3945_hw_set_hw_params(struct iwl_priv
*priv
)
2412 memset((void *)&priv
->hw_params
, 0,
2413 sizeof(struct iwl_hw_params
));
2415 priv
->_3945
.shared_virt
=
2416 dma_alloc_coherent(&priv
->pci_dev
->dev
,
2417 sizeof(struct iwl3945_shared
),
2418 &priv
->_3945
.shared_phys
, GFP_KERNEL
);
2419 if (!priv
->_3945
.shared_virt
) {
2420 IWL_ERR(priv
, "failed to allocate pci memory\n");
2421 mutex_unlock(&priv
->mutex
);
2425 /* Assign number of Usable TX queues */
2426 priv
->hw_params
.max_txq_num
= priv
->cfg
->num_of_queues
;
2428 priv
->hw_params
.tfd_size
= sizeof(struct iwl3945_tfd
);
2429 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_3K
);
2430 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
2431 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
2432 priv
->hw_params
.max_stations
= IWL3945_STATION_COUNT
;
2433 priv
->hw_params
.bcast_sta_id
= IWL3945_BROADCAST_ID
;
2435 priv
->hw_params
.rx_wrt_ptr_reg
= FH39_RSCSR_CHNL0_WPTR
;
2436 priv
->hw_params
.max_beacon_itrvl
= IWL39_MAX_UCODE_BEACON_INTERVAL
;
2441 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv
*priv
,
2442 struct iwl3945_frame
*frame
, u8 rate
)
2444 struct iwl3945_tx_beacon_cmd
*tx_beacon_cmd
;
2445 unsigned int frame_size
;
2447 tx_beacon_cmd
= (struct iwl3945_tx_beacon_cmd
*)&frame
->u
;
2448 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
2450 tx_beacon_cmd
->tx
.sta_id
= priv
->hw_params
.bcast_sta_id
;
2451 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
2453 frame_size
= iwl3945_fill_beacon_frame(priv
,
2454 tx_beacon_cmd
->frame
,
2455 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
2457 BUG_ON(frame_size
> MAX_MPDU_SIZE
);
2458 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
2460 tx_beacon_cmd
->tx
.rate
= rate
;
2461 tx_beacon_cmd
->tx
.tx_flags
= (TX_CMD_FLG_SEQ_CTL_MSK
|
2462 TX_CMD_FLG_TSF_MSK
);
2464 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2465 tx_beacon_cmd
->tx
.supp_rates
[0] =
2466 (IWL_OFDM_BASIC_RATES_MASK
>> IWL_FIRST_OFDM_RATE
) & 0xFF;
2468 tx_beacon_cmd
->tx
.supp_rates
[1] =
2469 (IWL_CCK_BASIC_RATES_MASK
& 0xF);
2471 return sizeof(struct iwl3945_tx_beacon_cmd
) + frame_size
;
2474 void iwl3945_hw_rx_handler_setup(struct iwl_priv
*priv
)
2476 priv
->rx_handlers
[REPLY_TX
] = iwl3945_rx_reply_tx
;
2477 priv
->rx_handlers
[REPLY_3945_RX
] = iwl3945_rx_reply_rx
;
2480 void iwl3945_hw_setup_deferred_work(struct iwl_priv
*priv
)
2482 INIT_DELAYED_WORK(&priv
->_3945
.thermal_periodic
,
2483 iwl3945_bg_reg_txpower_periodic
);
2486 void iwl3945_hw_cancel_deferred_work(struct iwl_priv
*priv
)
2488 cancel_delayed_work(&priv
->_3945
.thermal_periodic
);
2491 /* check contents of special bootstrap uCode SRAM */
2492 static int iwl3945_verify_bsm(struct iwl_priv
*priv
)
2494 __le32
*image
= priv
->ucode_boot
.v_addr
;
2495 u32 len
= priv
->ucode_boot
.len
;
2499 IWL_DEBUG_INFO(priv
, "Begin verify bsm\n");
2501 /* verify BSM SRAM contents */
2502 val
= iwl_read_prph(priv
, BSM_WR_DWCOUNT_REG
);
2503 for (reg
= BSM_SRAM_LOWER_BOUND
;
2504 reg
< BSM_SRAM_LOWER_BOUND
+ len
;
2505 reg
+= sizeof(u32
), image
++) {
2506 val
= iwl_read_prph(priv
, reg
);
2507 if (val
!= le32_to_cpu(*image
)) {
2508 IWL_ERR(priv
, "BSM uCode verification failed at "
2509 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2510 BSM_SRAM_LOWER_BOUND
,
2511 reg
- BSM_SRAM_LOWER_BOUND
, len
,
2512 val
, le32_to_cpu(*image
));
2517 IWL_DEBUG_INFO(priv
, "BSM bootstrap uCode image OK\n");
2523 /******************************************************************************
2525 * EEPROM related functions
2527 ******************************************************************************/
2530 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2531 * embedded controller) as EEPROM reader; each read is a series of pulses
2532 * to/from the EEPROM chip, not a single event, so even reads could conflict
2533 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2534 * simply claims ownership, which should be safe when this function is called
2535 * (i.e. before loading uCode!).
2537 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv
*priv
)
2539 _iwl_clear_bit(priv
, CSR_EEPROM_GP
, CSR_EEPROM_GP_IF_OWNER_MSK
);
2544 static void iwl3945_eeprom_release_semaphore(struct iwl_priv
*priv
)
2550 * iwl3945_load_bsm - Load bootstrap instructions
2554 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2555 * in special SRAM that does not power down during RFKILL. When powering back
2556 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2557 * the bootstrap program into the on-board processor, and starts it.
2559 * The bootstrap program loads (via DMA) instructions and data for a new
2560 * program from host DRAM locations indicated by the host driver in the
2561 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2564 * When initializing the NIC, the host driver points the BSM to the
2565 * "initialize" uCode image. This uCode sets up some internal data, then
2566 * notifies host via "initialize alive" that it is complete.
2568 * The host then replaces the BSM_DRAM_* pointer values to point to the
2569 * normal runtime uCode instructions and a backup uCode data cache buffer
2570 * (filled initially with starting data values for the on-board processor),
2571 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2572 * which begins normal operation.
2574 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2575 * the backup data cache in DRAM before SRAM is powered down.
2577 * When powering back up, the BSM loads the bootstrap program. This reloads
2578 * the runtime uCode instructions and the backup data cache into SRAM,
2579 * and re-launches the runtime uCode from where it left off.
2581 static int iwl3945_load_bsm(struct iwl_priv
*priv
)
2583 __le32
*image
= priv
->ucode_boot
.v_addr
;
2584 u32 len
= priv
->ucode_boot
.len
;
2594 IWL_DEBUG_INFO(priv
, "Begin load bsm\n");
2596 /* make sure bootstrap program is no larger than BSM's SRAM size */
2597 if (len
> IWL39_MAX_BSM_SIZE
)
2600 /* Tell bootstrap uCode where to find the "Initialize" uCode
2601 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2602 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2603 * after the "initialize" uCode has run, to point to
2604 * runtime/protocol instructions and backup data cache. */
2605 pinst
= priv
->ucode_init
.p_addr
;
2606 pdata
= priv
->ucode_init_data
.p_addr
;
2607 inst_len
= priv
->ucode_init
.len
;
2608 data_len
= priv
->ucode_init_data
.len
;
2610 iwl_write_prph(priv
, BSM_DRAM_INST_PTR_REG
, pinst
);
2611 iwl_write_prph(priv
, BSM_DRAM_DATA_PTR_REG
, pdata
);
2612 iwl_write_prph(priv
, BSM_DRAM_INST_BYTECOUNT_REG
, inst_len
);
2613 iwl_write_prph(priv
, BSM_DRAM_DATA_BYTECOUNT_REG
, data_len
);
2615 /* Fill BSM memory with bootstrap instructions */
2616 for (reg_offset
= BSM_SRAM_LOWER_BOUND
;
2617 reg_offset
< BSM_SRAM_LOWER_BOUND
+ len
;
2618 reg_offset
+= sizeof(u32
), image
++)
2619 _iwl_write_prph(priv
, reg_offset
,
2620 le32_to_cpu(*image
));
2622 rc
= iwl3945_verify_bsm(priv
);
2626 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2627 iwl_write_prph(priv
, BSM_WR_MEM_SRC_REG
, 0x0);
2628 iwl_write_prph(priv
, BSM_WR_MEM_DST_REG
,
2629 IWL39_RTC_INST_LOWER_BOUND
);
2630 iwl_write_prph(priv
, BSM_WR_DWCOUNT_REG
, len
/ sizeof(u32
));
2632 /* Load bootstrap code into instruction SRAM now,
2633 * to prepare to load "initialize" uCode */
2634 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2635 BSM_WR_CTRL_REG_BIT_START
);
2637 /* Wait for load of bootstrap uCode to finish */
2638 for (i
= 0; i
< 100; i
++) {
2639 done
= iwl_read_prph(priv
, BSM_WR_CTRL_REG
);
2640 if (!(done
& BSM_WR_CTRL_REG_BIT_START
))
2645 IWL_DEBUG_INFO(priv
, "BSM write complete, poll %d iterations\n", i
);
2647 IWL_ERR(priv
, "BSM write did not complete!\n");
2651 /* Enable future boot loads whenever power management unit triggers it
2652 * (e.g. when powering back up after power-save shutdown) */
2653 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2654 BSM_WR_CTRL_REG_BIT_START_EN
);
2659 #define IWL3945_UCODE_GET(item) \
2660 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2663 return le32_to_cpu(ucode->u.v1.item); \
2666 static u32
iwl3945_ucode_get_header_size(u32 api_ver
)
2668 return UCODE_HEADER_SIZE(1);
2670 static u32
iwl3945_ucode_get_build(const struct iwl_ucode_header
*ucode
,
2675 static u8
*iwl3945_ucode_get_data(const struct iwl_ucode_header
*ucode
,
2678 return (u8
*) ucode
->u
.v1
.data
;
2681 IWL3945_UCODE_GET(inst_size
);
2682 IWL3945_UCODE_GET(data_size
);
2683 IWL3945_UCODE_GET(init_size
);
2684 IWL3945_UCODE_GET(init_data_size
);
2685 IWL3945_UCODE_GET(boot_size
);
2687 static struct iwl_hcmd_ops iwl3945_hcmd
= {
2688 .rxon_assoc
= iwl3945_send_rxon_assoc
,
2689 .commit_rxon
= iwl3945_commit_rxon
,
2692 static struct iwl_ucode_ops iwl3945_ucode
= {
2693 .get_header_size
= iwl3945_ucode_get_header_size
,
2694 .get_build
= iwl3945_ucode_get_build
,
2695 .get_inst_size
= iwl3945_ucode_get_inst_size
,
2696 .get_data_size
= iwl3945_ucode_get_data_size
,
2697 .get_init_size
= iwl3945_ucode_get_init_size
,
2698 .get_init_data_size
= iwl3945_ucode_get_init_data_size
,
2699 .get_boot_size
= iwl3945_ucode_get_boot_size
,
2700 .get_data
= iwl3945_ucode_get_data
,
2703 static struct iwl_lib_ops iwl3945_lib
= {
2704 .txq_attach_buf_to_tfd
= iwl3945_hw_txq_attach_buf_to_tfd
,
2705 .txq_free_tfd
= iwl3945_hw_txq_free_tfd
,
2706 .txq_init
= iwl3945_hw_tx_queue_init
,
2707 .load_ucode
= iwl3945_load_bsm
,
2708 .dump_nic_event_log
= iwl3945_dump_nic_event_log
,
2709 .dump_nic_error_log
= iwl3945_dump_nic_error_log
,
2711 .init
= iwl3945_apm_init
,
2712 .stop
= iwl_apm_stop
,
2713 .config
= iwl3945_nic_config
,
2714 .set_pwr_src
= iwl3945_set_pwr_src
,
2717 .regulatory_bands
= {
2718 EEPROM_REGULATORY_BAND_1_CHANNELS
,
2719 EEPROM_REGULATORY_BAND_2_CHANNELS
,
2720 EEPROM_REGULATORY_BAND_3_CHANNELS
,
2721 EEPROM_REGULATORY_BAND_4_CHANNELS
,
2722 EEPROM_REGULATORY_BAND_5_CHANNELS
,
2723 EEPROM_REGULATORY_BAND_NO_HT40
,
2724 EEPROM_REGULATORY_BAND_NO_HT40
,
2726 .verify_signature
= iwlcore_eeprom_verify_signature
,
2727 .acquire_semaphore
= iwl3945_eeprom_acquire_semaphore
,
2728 .release_semaphore
= iwl3945_eeprom_release_semaphore
,
2729 .query_addr
= iwlcore_eeprom_query_addr
,
2731 .send_tx_power
= iwl3945_send_tx_power
,
2732 .is_valid_rtc_data_addr
= iwl3945_hw_valid_rtc_data_addr
,
2733 .post_associate
= iwl3945_post_associate
,
2734 .isr
= iwl_isr_legacy
,
2735 .config_ap
= iwl3945_config_ap
,
2736 .add_bcast_station
= iwl3945_add_bcast_station
,
2739 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils
= {
2740 .get_hcmd_size
= iwl3945_get_hcmd_size
,
2741 .build_addsta_hcmd
= iwl3945_build_addsta_hcmd
,
2742 .rts_tx_cmd_flag
= iwlcore_rts_tx_cmd_flag
,
2745 static const struct iwl_ops iwl3945_ops
= {
2746 .ucode
= &iwl3945_ucode
,
2747 .lib
= &iwl3945_lib
,
2748 .hcmd
= &iwl3945_hcmd
,
2749 .utils
= &iwl3945_hcmd_utils
,
2750 .led
= &iwl3945_led_ops
,
2753 static struct iwl_cfg iwl3945_bg_cfg
= {
2755 .fw_name_pre
= IWL3945_FW_PRE
,
2756 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2757 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2759 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2760 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2761 .ops
= &iwl3945_ops
,
2762 .num_of_queues
= IWL39_NUM_QUEUES
,
2763 .mod_params
= &iwl3945_mod_params
,
2764 .pll_cfg_val
= CSR39_ANA_PLL_CFG_VAL
,
2767 .use_isr_legacy
= true,
2768 .ht_greenfield_support
= false,
2769 .led_compensation
= 64,
2770 .broken_powersave
= true,
2771 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2772 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2773 .max_event_log_size
= 512,
2776 static struct iwl_cfg iwl3945_abg_cfg
= {
2778 .fw_name_pre
= IWL3945_FW_PRE
,
2779 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2780 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2781 .sku
= IWL_SKU_A
|IWL_SKU_G
,
2782 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2783 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2784 .ops
= &iwl3945_ops
,
2785 .num_of_queues
= IWL39_NUM_QUEUES
,
2786 .mod_params
= &iwl3945_mod_params
,
2787 .use_isr_legacy
= true,
2788 .ht_greenfield_support
= false,
2789 .led_compensation
= 64,
2790 .broken_powersave
= true,
2791 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2792 .monitor_recover_period
= IWL_MONITORING_PERIOD
,
2793 .max_event_log_size
= 512,
2796 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids
) = {
2797 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg
)},
2798 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg
)},
2799 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg
)},
2800 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg
)},
2801 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2802 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2806 MODULE_DEVICE_TABLE(pci
, iwl3945_hw_card_ids
);