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Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
41
42 #include "iwl-fh.h"
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
45 #include "iwl-sta.h"
46 #include "iwl-3945.h"
47 #include "iwl-eeprom.h"
48 #include "iwl-helpers.h"
49 #include "iwl-core.h"
50 #include "iwl-led.h"
51 #include "iwl-3945-led.h"
52
53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
64
65 /*
66 * Parameter order:
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
68 *
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
71 *
72 */
73 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
74 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
86 };
87
88 /* 1 = enable the iwl3945_disable_events() function */
89 #define IWL_EVT_DISABLE (0)
90 #define IWL_EVT_DISABLE_SIZE (1532/32)
91
92 /**
93 * iwl3945_disable_events - Disable selected events in uCode event log
94 *
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
101 void iwl3945_disable_events(struct iwl_priv *priv)
102 {
103 int i;
104 u32 base; /* SRAM address of event log header */
105 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
106 u32 array_size; /* # of u32 entries in array */
107 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
155 };
156
157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
158 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
159 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
160 return;
161 }
162
163 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
165
166 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
167 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
168 disable_ptr);
169 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
170 iwl_write_targ_mem(priv,
171 disable_ptr + (i * sizeof(u32)),
172 evt_disable[i]);
173
174 } else {
175 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
178 disable_ptr, array_size);
179 }
180
181 }
182
183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184 {
185 int idx;
186
187 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
188 if (iwl3945_rates[idx].plcp == plcp)
189 return idx;
190 return -1;
191 }
192
193 #ifdef CONFIG_IWLWIFI_DEBUG
194 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
195
196 static const char *iwl3945_get_tx_fail_reason(u32 status)
197 {
198 switch (status & TX_STATUS_MSK) {
199 case TX_STATUS_SUCCESS:
200 return "SUCCESS";
201 TX_STATUS_ENTRY(SHORT_LIMIT);
202 TX_STATUS_ENTRY(LONG_LIMIT);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204 TX_STATUS_ENTRY(MGMNT_ABORT);
205 TX_STATUS_ENTRY(NEXT_FRAG);
206 TX_STATUS_ENTRY(LIFE_EXPIRE);
207 TX_STATUS_ENTRY(DEST_PS);
208 TX_STATUS_ENTRY(ABORTED);
209 TX_STATUS_ENTRY(BT_RETRY);
210 TX_STATUS_ENTRY(STA_INVALID);
211 TX_STATUS_ENTRY(FRAG_DROPPED);
212 TX_STATUS_ENTRY(TID_DISABLE);
213 TX_STATUS_ENTRY(FRAME_FLUSHED);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215 TX_STATUS_ENTRY(TX_LOCKED);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217 }
218
219 return "UNKNOWN";
220 }
221 #else
222 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223 {
224 return "";
225 }
226 #endif
227
228 /*
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
231 * value
232 */
233 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
234 {
235 int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237 switch (priv->band) {
238 case IEEE80211_BAND_5GHZ:
239 if (rate == IWL_RATE_12M_INDEX)
240 next_rate = IWL_RATE_9M_INDEX;
241 else if (rate == IWL_RATE_6M_INDEX)
242 next_rate = IWL_RATE_6M_INDEX;
243 break;
244 case IEEE80211_BAND_2GHZ:
245 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
246 iwl_is_associated(priv)) {
247 if (rate == IWL_RATE_11M_INDEX)
248 next_rate = IWL_RATE_5M_INDEX;
249 }
250 break;
251
252 default:
253 break;
254 }
255
256 return next_rate;
257 }
258
259
260 /**
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262 *
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
266 */
267 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
268 int txq_id, int index)
269 {
270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
271 struct iwl_queue *q = &txq->q;
272 struct iwl_tx_info *tx_info;
273
274 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279 tx_info = &txq->txb[txq->q.read_ptr];
280 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
281 tx_info->skb[0] = NULL;
282 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
283 }
284
285 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
286 (txq_id != IWL_CMD_QUEUE_NUM) &&
287 priv->mac80211_registered)
288 iwl_wake_queue(priv, txq_id);
289 }
290
291 /**
292 * iwl3945_rx_reply_tx - Handle Tx response
293 */
294 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
295 struct iwl_rx_mem_buffer *rxb)
296 {
297 struct iwl_rx_packet *pkt = rxb_addr(rxb);
298 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299 int txq_id = SEQ_TO_QUEUE(sequence);
300 int index = SEQ_TO_INDEX(sequence);
301 struct iwl_tx_queue *txq = &priv->txq[txq_id];
302 struct ieee80211_tx_info *info;
303 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304 u32 status = le32_to_cpu(tx_resp->status);
305 int rate_idx;
306 int fail;
307
308 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
309 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
310 "is out of range [0-%d] %d %d\n", txq_id,
311 index, txq->q.n_bd, txq->q.write_ptr,
312 txq->q.read_ptr);
313 return;
314 }
315
316 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
317 ieee80211_tx_info_clear_status(info);
318
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321 if (info->band == IEEE80211_BAND_5GHZ)
322 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324 fail = tx_resp->failure_frame;
325
326 info->status.rates[0].idx = rate_idx;
327 info->status.rates[0].count = fail + 1; /* add final attempt */
328
329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
330 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331 IEEE80211_TX_STAT_ACK : 0;
332
333 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
334 txq_id, iwl3945_get_tx_fail_reason(status), status,
335 tx_resp->rate, tx_resp->failure_frame);
336
337 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
341 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
342 }
343
344
345
346 /*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
352 *****************************************************************************/
353
354 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355 struct iwl_rx_mem_buffer *rxb)
356 {
357 struct iwl_rx_packet *pkt = rxb_addr(rxb);
358 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
359 (int)sizeof(struct iwl3945_notif_statistics),
360 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
361
362 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
363 }
364
365 /******************************************************************************
366 *
367 * Misc. internal state and helper functions
368 *
369 ******************************************************************************/
370 #ifdef CONFIG_IWLWIFI_DEBUG
371
372 /**
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
374 *
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
378 */
379 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
380 struct iwl_rx_packet *pkt,
381 struct ieee80211_hdr *header, int group100)
382 {
383 u32 to_us;
384 u32 print_summary = 0;
385 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
386 u32 hundred = 0;
387 u32 dataframe = 0;
388 __le16 fc;
389 u16 seq_ctl;
390 u16 channel;
391 u16 phy_flags;
392 u16 length;
393 u16 status;
394 u16 bcn_tmr;
395 u32 tsf_low;
396 u64 tsf;
397 u8 rssi;
398 u8 agc;
399 u16 sig_avg;
400 u16 noise_diff;
401 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
402 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
403 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
404 u8 *data = IWL_RX_DATA(pkt);
405
406 /* MAC header */
407 fc = header->frame_control;
408 seq_ctl = le16_to_cpu(header->seq_ctrl);
409
410 /* metadata */
411 channel = le16_to_cpu(rx_hdr->channel);
412 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
413 length = le16_to_cpu(rx_hdr->len);
414
415 /* end-of-frame status and timestamp */
416 status = le32_to_cpu(rx_end->status);
417 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
418 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
419 tsf = le64_to_cpu(rx_end->timestamp);
420
421 /* signal statistics */
422 rssi = rx_stats->rssi;
423 agc = rx_stats->agc;
424 sig_avg = le16_to_cpu(rx_stats->sig_avg);
425 noise_diff = le16_to_cpu(rx_stats->noise_diff);
426
427 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
428
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
431 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
433 dataframe = 1;
434 if (!group100)
435 print_summary = 1; /* print each frame */
436 else if (priv->framecnt_to_us < 100) {
437 priv->framecnt_to_us++;
438 print_summary = 0;
439 } else {
440 priv->framecnt_to_us = 0;
441 print_summary = 1;
442 hundred = 1;
443 }
444 } else {
445 /* print summary for all other frames */
446 print_summary = 1;
447 }
448
449 if (print_summary) {
450 char *title;
451 int rate;
452
453 if (hundred)
454 title = "100Frames";
455 else if (ieee80211_has_retry(fc))
456 title = "Retry";
457 else if (ieee80211_is_assoc_resp(fc))
458 title = "AscRsp";
459 else if (ieee80211_is_reassoc_resp(fc))
460 title = "RasRsp";
461 else if (ieee80211_is_probe_resp(fc)) {
462 title = "PrbRsp";
463 print_dump = 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc)) {
465 title = "Beacon";
466 print_dump = 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc))
468 title = "ATIM";
469 else if (ieee80211_is_auth(fc))
470 title = "Auth";
471 else if (ieee80211_is_deauth(fc))
472 title = "DeAuth";
473 else if (ieee80211_is_disassoc(fc))
474 title = "DisAssoc";
475 else
476 title = "Frame";
477
478 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
479 if (rate == -1)
480 rate = 0;
481 else
482 rate = iwl3945_rates[rate].ieee / 2;
483
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
487 if (dataframe)
488 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
489 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
490 title, le16_to_cpu(fc), header->addr1[5],
491 length, rssi, channel, rate);
492 else {
493 /* src/dst addresses assume managed mode */
494 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
497 title, le16_to_cpu(fc), header->addr1[5],
498 header->addr3[5], rssi,
499 tsf_low - priv->scan_start_tsf,
500 phy_flags, channel);
501 }
502 }
503 if (print_dump)
504 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
505 }
506
507 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
508 struct iwl_rx_packet *pkt,
509 struct ieee80211_hdr *header, int group100)
510 {
511 if (iwl_get_debug_level(priv) & IWL_DL_RX)
512 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
513 }
514
515 #else
516 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
517 struct iwl_rx_packet *pkt,
518 struct ieee80211_hdr *header, int group100)
519 {
520 }
521 #endif
522
523 /* This is necessary only for a number of statistics, see the caller. */
524 static int iwl3945_is_network_packet(struct iwl_priv *priv,
525 struct ieee80211_hdr *header)
526 {
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv->iw_mode) {
530 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header->addr3, priv->bssid);
533 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header->addr2, priv->bssid);
536 default:
537 return 1;
538 }
539 }
540
541 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
542 struct iwl_rx_mem_buffer *rxb,
543 struct ieee80211_rx_status *stats)
544 {
545 struct iwl_rx_packet *pkt = rxb_addr(rxb);
546 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
547 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
548 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
549 u16 len = le16_to_cpu(rx_hdr->len);
550 struct sk_buff *skb;
551 int ret;
552 __le16 fc = hdr->frame_control;
553
554 /* We received data from the HW, so stop the watchdog */
555 if (unlikely(len + IWL39_RX_FRAME_SIZE >
556 PAGE_SIZE << priv->hw_params.rx_page_order)) {
557 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
558 return;
559 }
560
561 /* We only process data packets if the interface is open */
562 if (unlikely(!priv->is_open)) {
563 IWL_DEBUG_DROP_LIMIT(priv,
564 "Dropping packet while interface is not open.\n");
565 return;
566 }
567
568 skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
569 if (!skb) {
570 IWL_ERR(priv, "alloc_skb failed\n");
571 return;
572 }
573
574 if (!iwl3945_mod_params.sw_crypto)
575 iwl_set_decrypted_flag(priv,
576 (struct ieee80211_hdr *)rxb_addr(rxb),
577 le32_to_cpu(rx_end->status), stats);
578
579 skb_reserve(skb, IWL_LINK_HDR_MAX);
580 skb_add_rx_frag(skb, 0, rxb->page,
581 (void *)rx_hdr->payload - (void *)pkt, len);
582
583 /* mac80211 currently doesn't support paged SKB. Convert it to
584 * linear SKB for management frame and data frame requires
585 * software decryption or software defragementation. */
586 if (ieee80211_is_mgmt(fc) ||
587 ieee80211_has_protected(fc) ||
588 ieee80211_has_morefrags(fc) ||
589 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
590 ret = skb_linearize(skb);
591 else
592 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
593 0 : -ENOMEM;
594
595 if (ret) {
596 kfree_skb(skb);
597 goto out;
598 }
599
600 /*
601 * XXX: We cannot touch the page and its virtual memory (pkt) after
602 * here. It might have already been freed by the above skb change.
603 */
604
605 iwl_update_stats(priv, false, fc, len);
606 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
607
608 ieee80211_rx(priv->hw, skb);
609 out:
610 priv->alloc_rxb_page--;
611 rxb->page = NULL;
612 }
613
614 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
616 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
617 struct iwl_rx_mem_buffer *rxb)
618 {
619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
621 struct iwl_rx_packet *pkt = rxb_addr(rxb);
622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
625 int snr;
626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
628 u8 network_packet;
629
630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
632 rx_status.freq =
633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
640
641 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
648 if ((unlikely(rx_stats->phy_count > 20))) {
649 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
650 rx_stats->phy_count);
651 return;
652 }
653
654 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
655 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
656 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
657 return;
658 }
659
660
661
662 /* Convert 3945's rssi indicator to dBm */
663 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
664
665 /* Set default noise value to -127 */
666 if (priv->last_rx_noise == 0)
667 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
668
669 /* 3945 provides noise info for OFDM frames only.
670 * sig_avg and noise_diff are measured by the 3945's digital signal
671 * processor (DSP), and indicate linear levels of signal level and
672 * distortion/noise within the packet preamble after
673 * automatic gain control (AGC). sig_avg should stay fairly
674 * constant if the radio's AGC is working well.
675 * Since these values are linear (not dB or dBm), linear
676 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
677 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
678 * to obtain noise level in dBm.
679 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
680 if (rx_stats_noise_diff) {
681 snr = rx_stats_sig_avg / rx_stats_noise_diff;
682 rx_status.noise = rx_status.signal -
683 iwl3945_calc_db_from_ratio(snr);
684 } else {
685 rx_status.noise = priv->last_rx_noise;
686 }
687
688
689 IWL_DEBUG_STATS(priv, "Rssi %d noise %d sig_avg %d noise_diff %d\n",
690 rx_status.signal, rx_status.noise,
691 rx_stats_sig_avg, rx_stats_noise_diff);
692
693 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
694
695 network_packet = iwl3945_is_network_packet(priv, header);
696
697 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
698 network_packet ? '*' : ' ',
699 le16_to_cpu(rx_hdr->channel),
700 rx_status.signal, rx_status.signal,
701 rx_status.noise, rx_status.rate_idx);
702
703 /* Set "1" to report good data frames in groups of 100 */
704 iwl3945_dbg_report_frame(priv, pkt, header, 1);
705 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
706
707 if (network_packet) {
708 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
709 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
710 priv->last_rx_rssi = rx_status.signal;
711 priv->last_rx_noise = rx_status.noise;
712 }
713
714 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
715 }
716
717 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
718 struct iwl_tx_queue *txq,
719 dma_addr_t addr, u16 len, u8 reset, u8 pad)
720 {
721 int count;
722 struct iwl_queue *q;
723 struct iwl3945_tfd *tfd, *tfd_tmp;
724
725 q = &txq->q;
726 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
727 tfd = &tfd_tmp[q->write_ptr];
728
729 if (reset)
730 memset(tfd, 0, sizeof(*tfd));
731
732 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
733
734 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
735 IWL_ERR(priv, "Error can not send more than %d chunks\n",
736 NUM_TFD_CHUNKS);
737 return -EINVAL;
738 }
739
740 tfd->tbs[count].addr = cpu_to_le32(addr);
741 tfd->tbs[count].len = cpu_to_le32(len);
742
743 count++;
744
745 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
746 TFD_CTL_PAD_SET(pad));
747
748 return 0;
749 }
750
751 /**
752 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
753 *
754 * Does NOT advance any indexes
755 */
756 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
757 {
758 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
759 int index = txq->q.read_ptr;
760 struct iwl3945_tfd *tfd = &tfd_tmp[index];
761 struct pci_dev *dev = priv->pci_dev;
762 int i;
763 int counter;
764
765 /* sanity check */
766 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
767 if (counter > NUM_TFD_CHUNKS) {
768 IWL_ERR(priv, "Too many chunks: %i\n", counter);
769 /* @todo issue fatal error, it is quite serious situation */
770 return;
771 }
772
773 /* Unmap tx_cmd */
774 if (counter)
775 pci_unmap_single(dev,
776 pci_unmap_addr(&txq->meta[index], mapping),
777 pci_unmap_len(&txq->meta[index], len),
778 PCI_DMA_TODEVICE);
779
780 /* unmap chunks if any */
781
782 for (i = 1; i < counter; i++) {
783 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
784 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
785 if (txq->txb[txq->q.read_ptr].skb[0]) {
786 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
787 if (txq->txb[txq->q.read_ptr].skb[0]) {
788 /* Can be called from interrupt context */
789 dev_kfree_skb_any(skb);
790 txq->txb[txq->q.read_ptr].skb[0] = NULL;
791 }
792 }
793 }
794 return ;
795 }
796
797 /**
798 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
799 *
800 */
801 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
802 struct iwl_device_cmd *cmd,
803 struct ieee80211_tx_info *info,
804 struct ieee80211_hdr *hdr,
805 int sta_id, int tx_id)
806 {
807 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
808 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
809 u16 rate_mask;
810 int rate;
811 u8 rts_retry_limit;
812 u8 data_retry_limit;
813 __le32 tx_flags;
814 __le16 fc = hdr->frame_control;
815 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
816
817 rate = iwl3945_rates[rate_index].plcp;
818 tx_flags = tx_cmd->tx_flags;
819
820 /* We need to figure out how to get the sta->supp_rates while
821 * in this running context */
822 rate_mask = IWL_RATES_MASK;
823
824
825 /* Set retry limit on DATA packets and Probe Responses*/
826 if (ieee80211_is_probe_resp(fc))
827 data_retry_limit = 3;
828 else
829 data_retry_limit = IWL_DEFAULT_TX_RETRY;
830 tx_cmd->data_retry_limit = data_retry_limit;
831
832 if (tx_id >= IWL_CMD_QUEUE_NUM)
833 rts_retry_limit = 3;
834 else
835 rts_retry_limit = 7;
836
837 if (data_retry_limit < rts_retry_limit)
838 rts_retry_limit = data_retry_limit;
839 tx_cmd->rts_retry_limit = rts_retry_limit;
840
841 if (ieee80211_is_mgmt(fc)) {
842 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
843 case cpu_to_le16(IEEE80211_STYPE_AUTH):
844 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
845 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
846 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
847 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
848 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
849 tx_flags |= TX_CMD_FLG_CTS_MSK;
850 }
851 break;
852 default:
853 break;
854 }
855 }
856
857 tx_cmd->rate = rate;
858 tx_cmd->tx_flags = tx_flags;
859
860 /* OFDM */
861 tx_cmd->supp_rates[0] =
862 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
863
864 /* CCK */
865 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
866
867 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
868 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
869 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
870 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
871 }
872
873 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
874 {
875 unsigned long flags_spin;
876 struct iwl_station_entry *station;
877
878 if (sta_id == IWL_INVALID_STATION)
879 return IWL_INVALID_STATION;
880
881 spin_lock_irqsave(&priv->sta_lock, flags_spin);
882 station = &priv->stations[sta_id];
883
884 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
885 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
886 station->sta.mode = STA_CONTROL_MODIFY_MSK;
887
888 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
889
890 iwl_send_add_sta(priv, &station->sta, flags);
891 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
892 sta_id, tx_rate);
893 return sta_id;
894 }
895
896 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
897 {
898 if (src == IWL_PWR_SRC_VAUX) {
899 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
900 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
901 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
902 ~APMG_PS_CTRL_MSK_PWR_SRC);
903
904 iwl_poll_bit(priv, CSR_GPIO_IN,
905 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
906 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
907 }
908 } else {
909 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
910 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
911 ~APMG_PS_CTRL_MSK_PWR_SRC);
912
913 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
914 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
915 }
916
917 return 0;
918 }
919
920 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
921 {
922 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
923 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
924 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
925 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
926 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
927 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
928 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
929 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
930 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
931 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
932 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
933 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
934
935 /* fake read to flush all prev I/O */
936 iwl_read_direct32(priv, FH39_RSSR_CTRL);
937
938 return 0;
939 }
940
941 static int iwl3945_tx_reset(struct iwl_priv *priv)
942 {
943
944 /* bypass mode */
945 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
946
947 /* RA 0 is active */
948 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
949
950 /* all 6 fifo are active */
951 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
952
953 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
954 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
955 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
956 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
957
958 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
959 priv->shared_phys);
960
961 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
962 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
963 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
969
970
971 return 0;
972 }
973
974 /**
975 * iwl3945_txq_ctx_reset - Reset TX queue context
976 *
977 * Destroys all DMA structures and initialize them again
978 */
979 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
980 {
981 int rc;
982 int txq_id, slots_num;
983
984 iwl3945_hw_txq_ctx_free(priv);
985
986 /* allocate tx queue structure */
987 rc = iwl_alloc_txq_mem(priv);
988 if (rc)
989 return rc;
990
991 /* Tx CMD queue */
992 rc = iwl3945_tx_reset(priv);
993 if (rc)
994 goto error;
995
996 /* Tx queue(s) */
997 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
998 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
999 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1000 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1001 txq_id);
1002 if (rc) {
1003 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1004 goto error;
1005 }
1006 }
1007
1008 return rc;
1009
1010 error:
1011 iwl3945_hw_txq_ctx_free(priv);
1012 return rc;
1013 }
1014
1015
1016 /*
1017 * Start up 3945's basic functionality after it has been reset
1018 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1019 * NOTE: This does not load uCode nor start the embedded processor
1020 */
1021 static int iwl3945_apm_init(struct iwl_priv *priv)
1022 {
1023 int ret = iwl_apm_init(priv);
1024
1025 /* Clear APMG (NIC's internal power management) interrupts */
1026 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1027 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1028
1029 /* Reset radio chip */
1030 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1031 udelay(5);
1032 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1033
1034 return ret;
1035 }
1036
1037 static void iwl3945_nic_config(struct iwl_priv *priv)
1038 {
1039 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1040 unsigned long flags;
1041 u8 rev_id = 0;
1042
1043 spin_lock_irqsave(&priv->lock, flags);
1044
1045 /* Determine HW type */
1046 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1047
1048 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1049
1050 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1051 IWL_DEBUG_INFO(priv, "RTP type \n");
1052 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1053 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1054 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1055 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1056 } else {
1057 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1058 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1059 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1060 }
1061
1062 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1063 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1064 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1065 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1066 } else
1067 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1068
1069 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1070 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1071 eeprom->board_revision);
1072 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1073 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1074 } else {
1075 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1076 eeprom->board_revision);
1077 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1078 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1079 }
1080
1081 if (eeprom->almgor_m_version <= 1) {
1082 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1083 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1084 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1085 eeprom->almgor_m_version);
1086 } else {
1087 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1088 eeprom->almgor_m_version);
1089 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1090 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1091 }
1092 spin_unlock_irqrestore(&priv->lock, flags);
1093
1094 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1095 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1096
1097 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1098 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1099 }
1100
1101 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1102 {
1103 int rc;
1104 unsigned long flags;
1105 struct iwl_rx_queue *rxq = &priv->rxq;
1106
1107 spin_lock_irqsave(&priv->lock, flags);
1108 priv->cfg->ops->lib->apm_ops.init(priv);
1109 spin_unlock_irqrestore(&priv->lock, flags);
1110
1111 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1112 if (rc)
1113 return rc;
1114
1115 priv->cfg->ops->lib->apm_ops.config(priv);
1116
1117 /* Allocate the RX queue, or reset if it is already allocated */
1118 if (!rxq->bd) {
1119 rc = iwl_rx_queue_alloc(priv);
1120 if (rc) {
1121 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1122 return -ENOMEM;
1123 }
1124 } else
1125 iwl3945_rx_queue_reset(priv, rxq);
1126
1127 iwl3945_rx_replenish(priv);
1128
1129 iwl3945_rx_init(priv, rxq);
1130
1131
1132 /* Look at using this instead:
1133 rxq->need_update = 1;
1134 iwl_rx_queue_update_write_ptr(priv, rxq);
1135 */
1136
1137 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1138
1139 rc = iwl3945_txq_ctx_reset(priv);
1140 if (rc)
1141 return rc;
1142
1143 set_bit(STATUS_INIT, &priv->status);
1144
1145 return 0;
1146 }
1147
1148 /**
1149 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1150 *
1151 * Destroy all TX DMA queues and structures
1152 */
1153 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1154 {
1155 int txq_id;
1156
1157 /* Tx queues */
1158 if (priv->txq)
1159 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1160 txq_id++)
1161 if (txq_id == IWL_CMD_QUEUE_NUM)
1162 iwl_cmd_queue_free(priv);
1163 else
1164 iwl_tx_queue_free(priv, txq_id);
1165
1166 /* free tx queue structure */
1167 iwl_free_txq_mem(priv);
1168 }
1169
1170 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1171 {
1172 int txq_id;
1173
1174 /* stop SCD */
1175 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1176 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1177
1178 /* reset TFD queues */
1179 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1180 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1181 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1182 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1183 1000);
1184 }
1185
1186 iwl3945_hw_txq_ctx_free(priv);
1187 }
1188
1189 /**
1190 * iwl3945_hw_reg_adjust_power_by_temp
1191 * return index delta into power gain settings table
1192 */
1193 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1194 {
1195 return (new_reading - old_reading) * (-11) / 100;
1196 }
1197
1198 /**
1199 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1200 */
1201 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1202 {
1203 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1204 }
1205
1206 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1207 {
1208 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1209 }
1210
1211 /**
1212 * iwl3945_hw_reg_txpower_get_temperature
1213 * get the current temperature by reading from NIC
1214 */
1215 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1216 {
1217 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1218 int temperature;
1219
1220 temperature = iwl3945_hw_get_temperature(priv);
1221
1222 /* driver's okay range is -260 to +25.
1223 * human readable okay range is 0 to +285 */
1224 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1225
1226 /* handle insane temp reading */
1227 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1228 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1229
1230 /* if really really hot(?),
1231 * substitute the 3rd band/group's temp measured at factory */
1232 if (priv->last_temperature > 100)
1233 temperature = eeprom->groups[2].temperature;
1234 else /* else use most recent "sane" value from driver */
1235 temperature = priv->last_temperature;
1236 }
1237
1238 return temperature; /* raw, not "human readable" */
1239 }
1240
1241 /* Adjust Txpower only if temperature variance is greater than threshold.
1242 *
1243 * Both are lower than older versions' 9 degrees */
1244 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1245
1246 /**
1247 * is_temp_calib_needed - determines if new calibration is needed
1248 *
1249 * records new temperature in tx_mgr->temperature.
1250 * replaces tx_mgr->last_temperature *only* if calib needed
1251 * (assumes caller will actually do the calibration!). */
1252 static int is_temp_calib_needed(struct iwl_priv *priv)
1253 {
1254 int temp_diff;
1255
1256 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1257 temp_diff = priv->temperature - priv->last_temperature;
1258
1259 /* get absolute value */
1260 if (temp_diff < 0) {
1261 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1262 temp_diff = -temp_diff;
1263 } else if (temp_diff == 0)
1264 IWL_DEBUG_POWER(priv, "Same temp,\n");
1265 else
1266 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1267
1268 /* if we don't need calibration, *don't* update last_temperature */
1269 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1270 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1271 return 0;
1272 }
1273
1274 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1275
1276 /* assume that caller will actually do calib ...
1277 * update the "last temperature" value */
1278 priv->last_temperature = priv->temperature;
1279 return 1;
1280 }
1281
1282 #define IWL_MAX_GAIN_ENTRIES 78
1283 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1284 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1285
1286 /* radio and DSP power table, each step is 1/2 dB.
1287 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1288 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1289 {
1290 {251, 127}, /* 2.4 GHz, highest power */
1291 {251, 127},
1292 {251, 127},
1293 {251, 127},
1294 {251, 125},
1295 {251, 110},
1296 {251, 105},
1297 {251, 98},
1298 {187, 125},
1299 {187, 115},
1300 {187, 108},
1301 {187, 99},
1302 {243, 119},
1303 {243, 111},
1304 {243, 105},
1305 {243, 97},
1306 {243, 92},
1307 {211, 106},
1308 {211, 100},
1309 {179, 120},
1310 {179, 113},
1311 {179, 107},
1312 {147, 125},
1313 {147, 119},
1314 {147, 112},
1315 {147, 106},
1316 {147, 101},
1317 {147, 97},
1318 {147, 91},
1319 {115, 107},
1320 {235, 121},
1321 {235, 115},
1322 {235, 109},
1323 {203, 127},
1324 {203, 121},
1325 {203, 115},
1326 {203, 108},
1327 {203, 102},
1328 {203, 96},
1329 {203, 92},
1330 {171, 110},
1331 {171, 104},
1332 {171, 98},
1333 {139, 116},
1334 {227, 125},
1335 {227, 119},
1336 {227, 113},
1337 {227, 107},
1338 {227, 101},
1339 {227, 96},
1340 {195, 113},
1341 {195, 106},
1342 {195, 102},
1343 {195, 95},
1344 {163, 113},
1345 {163, 106},
1346 {163, 102},
1347 {163, 95},
1348 {131, 113},
1349 {131, 106},
1350 {131, 102},
1351 {131, 95},
1352 {99, 113},
1353 {99, 106},
1354 {99, 102},
1355 {99, 95},
1356 {67, 113},
1357 {67, 106},
1358 {67, 102},
1359 {67, 95},
1360 {35, 113},
1361 {35, 106},
1362 {35, 102},
1363 {35, 95},
1364 {3, 113},
1365 {3, 106},
1366 {3, 102},
1367 {3, 95} }, /* 2.4 GHz, lowest power */
1368 {
1369 {251, 127}, /* 5.x GHz, highest power */
1370 {251, 120},
1371 {251, 114},
1372 {219, 119},
1373 {219, 101},
1374 {187, 113},
1375 {187, 102},
1376 {155, 114},
1377 {155, 103},
1378 {123, 117},
1379 {123, 107},
1380 {123, 99},
1381 {123, 92},
1382 {91, 108},
1383 {59, 125},
1384 {59, 118},
1385 {59, 109},
1386 {59, 102},
1387 {59, 96},
1388 {59, 90},
1389 {27, 104},
1390 {27, 98},
1391 {27, 92},
1392 {115, 118},
1393 {115, 111},
1394 {115, 104},
1395 {83, 126},
1396 {83, 121},
1397 {83, 113},
1398 {83, 105},
1399 {83, 99},
1400 {51, 118},
1401 {51, 111},
1402 {51, 104},
1403 {51, 98},
1404 {19, 116},
1405 {19, 109},
1406 {19, 102},
1407 {19, 98},
1408 {19, 93},
1409 {171, 113},
1410 {171, 107},
1411 {171, 99},
1412 {139, 120},
1413 {139, 113},
1414 {139, 107},
1415 {139, 99},
1416 {107, 120},
1417 {107, 113},
1418 {107, 107},
1419 {107, 99},
1420 {75, 120},
1421 {75, 113},
1422 {75, 107},
1423 {75, 99},
1424 {43, 120},
1425 {43, 113},
1426 {43, 107},
1427 {43, 99},
1428 {11, 120},
1429 {11, 113},
1430 {11, 107},
1431 {11, 99},
1432 {131, 107},
1433 {131, 99},
1434 {99, 120},
1435 {99, 113},
1436 {99, 107},
1437 {99, 99},
1438 {67, 120},
1439 {67, 113},
1440 {67, 107},
1441 {67, 99},
1442 {35, 120},
1443 {35, 113},
1444 {35, 107},
1445 {35, 99},
1446 {3, 120} } /* 5.x GHz, lowest power */
1447 };
1448
1449 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1450 {
1451 if (index < 0)
1452 return 0;
1453 if (index >= IWL_MAX_GAIN_ENTRIES)
1454 return IWL_MAX_GAIN_ENTRIES - 1;
1455 return (u8) index;
1456 }
1457
1458 /* Kick off thermal recalibration check every 60 seconds */
1459 #define REG_RECALIB_PERIOD (60)
1460
1461 /**
1462 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1463 *
1464 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1465 * or 6 Mbit (OFDM) rates.
1466 */
1467 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1468 s32 rate_index, const s8 *clip_pwrs,
1469 struct iwl_channel_info *ch_info,
1470 int band_index)
1471 {
1472 struct iwl3945_scan_power_info *scan_power_info;
1473 s8 power;
1474 u8 power_index;
1475
1476 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1477
1478 /* use this channel group's 6Mbit clipping/saturation pwr,
1479 * but cap at regulatory scan power restriction (set during init
1480 * based on eeprom channel data) for this channel. */
1481 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1482
1483 /* further limit to user's max power preference.
1484 * FIXME: Other spectrum management power limitations do not
1485 * seem to apply?? */
1486 power = min(power, priv->tx_power_user_lmt);
1487 scan_power_info->requested_power = power;
1488
1489 /* find difference between new scan *power* and current "normal"
1490 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1491 * current "normal" temperature-compensated Tx power *index* for
1492 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1493 * *index*. */
1494 power_index = ch_info->power_info[rate_index].power_table_index
1495 - (power - ch_info->power_info
1496 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1497
1498 /* store reference index that we use when adjusting *all* scan
1499 * powers. So we can accommodate user (all channel) or spectrum
1500 * management (single channel) power changes "between" temperature
1501 * feedback compensation procedures.
1502 * don't force fit this reference index into gain table; it may be a
1503 * negative number. This will help avoid errors when we're at
1504 * the lower bounds (highest gains, for warmest temperatures)
1505 * of the table. */
1506
1507 /* don't exceed table bounds for "real" setting */
1508 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1509
1510 scan_power_info->power_table_index = power_index;
1511 scan_power_info->tpc.tx_gain =
1512 power_gain_table[band_index][power_index].tx_gain;
1513 scan_power_info->tpc.dsp_atten =
1514 power_gain_table[band_index][power_index].dsp_atten;
1515 }
1516
1517 /**
1518 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1519 *
1520 * Configures power settings for all rates for the current channel,
1521 * using values from channel info struct, and send to NIC
1522 */
1523 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1524 {
1525 int rate_idx, i;
1526 const struct iwl_channel_info *ch_info = NULL;
1527 struct iwl3945_txpowertable_cmd txpower = {
1528 .channel = priv->active_rxon.channel,
1529 };
1530
1531 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1532 ch_info = iwl_get_channel_info(priv,
1533 priv->band,
1534 le16_to_cpu(priv->active_rxon.channel));
1535 if (!ch_info) {
1536 IWL_ERR(priv,
1537 "Failed to get channel info for channel %d [%d]\n",
1538 le16_to_cpu(priv->active_rxon.channel), priv->band);
1539 return -EINVAL;
1540 }
1541
1542 if (!is_channel_valid(ch_info)) {
1543 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1544 "non-Tx channel.\n");
1545 return 0;
1546 }
1547
1548 /* fill cmd with power settings for all rates for current channel */
1549 /* Fill OFDM rate */
1550 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1551 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1552
1553 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1554 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1555
1556 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1557 le16_to_cpu(txpower.channel),
1558 txpower.band,
1559 txpower.power[i].tpc.tx_gain,
1560 txpower.power[i].tpc.dsp_atten,
1561 txpower.power[i].rate);
1562 }
1563 /* Fill CCK rates */
1564 for (rate_idx = IWL_FIRST_CCK_RATE;
1565 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1566 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1567 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1568
1569 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1570 le16_to_cpu(txpower.channel),
1571 txpower.band,
1572 txpower.power[i].tpc.tx_gain,
1573 txpower.power[i].tpc.dsp_atten,
1574 txpower.power[i].rate);
1575 }
1576
1577 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1578 sizeof(struct iwl3945_txpowertable_cmd),
1579 &txpower);
1580
1581 }
1582
1583 /**
1584 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1585 * @ch_info: Channel to update. Uses power_info.requested_power.
1586 *
1587 * Replace requested_power and base_power_index ch_info fields for
1588 * one channel.
1589 *
1590 * Called if user or spectrum management changes power preferences.
1591 * Takes into account h/w and modulation limitations (clip power).
1592 *
1593 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1594 *
1595 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1596 * properly fill out the scan powers, and actual h/w gain settings,
1597 * and send changes to NIC
1598 */
1599 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1600 struct iwl_channel_info *ch_info)
1601 {
1602 struct iwl3945_channel_power_info *power_info;
1603 int power_changed = 0;
1604 int i;
1605 const s8 *clip_pwrs;
1606 int power;
1607
1608 /* Get this chnlgrp's rate-to-max/clip-powers table */
1609 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1610
1611 /* Get this channel's rate-to-current-power settings table */
1612 power_info = ch_info->power_info;
1613
1614 /* update OFDM Txpower settings */
1615 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1616 i++, ++power_info) {
1617 int delta_idx;
1618
1619 /* limit new power to be no more than h/w capability */
1620 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1621 if (power == power_info->requested_power)
1622 continue;
1623
1624 /* find difference between old and new requested powers,
1625 * update base (non-temp-compensated) power index */
1626 delta_idx = (power - power_info->requested_power) * 2;
1627 power_info->base_power_index -= delta_idx;
1628
1629 /* save new requested power value */
1630 power_info->requested_power = power;
1631
1632 power_changed = 1;
1633 }
1634
1635 /* update CCK Txpower settings, based on OFDM 12M setting ...
1636 * ... all CCK power settings for a given channel are the *same*. */
1637 if (power_changed) {
1638 power =
1639 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1640 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1641
1642 /* do all CCK rates' iwl3945_channel_power_info structures */
1643 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1644 power_info->requested_power = power;
1645 power_info->base_power_index =
1646 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1647 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1648 ++power_info;
1649 }
1650 }
1651
1652 return 0;
1653 }
1654
1655 /**
1656 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1657 *
1658 * NOTE: Returned power limit may be less (but not more) than requested,
1659 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1660 * (no consideration for h/w clipping limitations).
1661 */
1662 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1663 {
1664 s8 max_power;
1665
1666 #if 0
1667 /* if we're using TGd limits, use lower of TGd or EEPROM */
1668 if (ch_info->tgd_data.max_power != 0)
1669 max_power = min(ch_info->tgd_data.max_power,
1670 ch_info->eeprom.max_power_avg);
1671
1672 /* else just use EEPROM limits */
1673 else
1674 #endif
1675 max_power = ch_info->eeprom.max_power_avg;
1676
1677 return min(max_power, ch_info->max_power_avg);
1678 }
1679
1680 /**
1681 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1682 *
1683 * Compensate txpower settings of *all* channels for temperature.
1684 * This only accounts for the difference between current temperature
1685 * and the factory calibration temperatures, and bases the new settings
1686 * on the channel's base_power_index.
1687 *
1688 * If RxOn is "associated", this sends the new Txpower to NIC!
1689 */
1690 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1691 {
1692 struct iwl_channel_info *ch_info = NULL;
1693 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1694 int delta_index;
1695 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1696 u8 a_band;
1697 u8 rate_index;
1698 u8 scan_tbl_index;
1699 u8 i;
1700 int ref_temp;
1701 int temperature = priv->temperature;
1702
1703 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1704 for (i = 0; i < priv->channel_count; i++) {
1705 ch_info = &priv->channel_info[i];
1706 a_band = is_channel_a_band(ch_info);
1707
1708 /* Get this chnlgrp's factory calibration temperature */
1709 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1710 temperature;
1711
1712 /* get power index adjustment based on current and factory
1713 * temps */
1714 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1715 ref_temp);
1716
1717 /* set tx power value for all rates, OFDM and CCK */
1718 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1719 rate_index++) {
1720 int power_idx =
1721 ch_info->power_info[rate_index].base_power_index;
1722
1723 /* temperature compensate */
1724 power_idx += delta_index;
1725
1726 /* stay within table range */
1727 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1728 ch_info->power_info[rate_index].
1729 power_table_index = (u8) power_idx;
1730 ch_info->power_info[rate_index].tpc =
1731 power_gain_table[a_band][power_idx];
1732 }
1733
1734 /* Get this chnlgrp's rate-to-max/clip-powers table */
1735 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1736
1737 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1738 for (scan_tbl_index = 0;
1739 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1740 s32 actual_index = (scan_tbl_index == 0) ?
1741 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1742 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1743 actual_index, clip_pwrs,
1744 ch_info, a_band);
1745 }
1746 }
1747
1748 /* send Txpower command for current channel to ucode */
1749 return priv->cfg->ops->lib->send_tx_power(priv);
1750 }
1751
1752 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1753 {
1754 struct iwl_channel_info *ch_info;
1755 s8 max_power;
1756 u8 a_band;
1757 u8 i;
1758
1759 if (priv->tx_power_user_lmt == power) {
1760 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1761 "limit: %ddBm.\n", power);
1762 return 0;
1763 }
1764
1765 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1766 priv->tx_power_user_lmt = power;
1767
1768 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1769
1770 for (i = 0; i < priv->channel_count; i++) {
1771 ch_info = &priv->channel_info[i];
1772 a_band = is_channel_a_band(ch_info);
1773
1774 /* find minimum power of all user and regulatory constraints
1775 * (does not consider h/w clipping limitations) */
1776 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1777 max_power = min(power, max_power);
1778 if (max_power != ch_info->curr_txpow) {
1779 ch_info->curr_txpow = max_power;
1780
1781 /* this considers the h/w clipping limitations */
1782 iwl3945_hw_reg_set_new_power(priv, ch_info);
1783 }
1784 }
1785
1786 /* update txpower settings for all channels,
1787 * send to NIC if associated. */
1788 is_temp_calib_needed(priv);
1789 iwl3945_hw_reg_comp_txpower_temp(priv);
1790
1791 return 0;
1792 }
1793
1794 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1795 {
1796 int rc = 0;
1797 struct iwl_rx_packet *pkt;
1798 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1799 struct iwl_host_cmd cmd = {
1800 .id = REPLY_RXON_ASSOC,
1801 .len = sizeof(rxon_assoc),
1802 .flags = CMD_WANT_SKB,
1803 .data = &rxon_assoc,
1804 };
1805 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1806 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1807
1808 if ((rxon1->flags == rxon2->flags) &&
1809 (rxon1->filter_flags == rxon2->filter_flags) &&
1810 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1811 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1812 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1813 return 0;
1814 }
1815
1816 rxon_assoc.flags = priv->staging_rxon.flags;
1817 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1818 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1819 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1820 rxon_assoc.reserved = 0;
1821
1822 rc = iwl_send_cmd_sync(priv, &cmd);
1823 if (rc)
1824 return rc;
1825
1826 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1827 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1828 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1829 rc = -EIO;
1830 }
1831
1832 iwl_free_pages(priv, cmd.reply_page);
1833
1834 return rc;
1835 }
1836
1837 /**
1838 * iwl3945_commit_rxon - commit staging_rxon to hardware
1839 *
1840 * The RXON command in staging_rxon is committed to the hardware and
1841 * the active_rxon structure is updated with the new data. This
1842 * function correctly transitions out of the RXON_ASSOC_MSK state if
1843 * a HW tune is required based on the RXON structure changes.
1844 */
1845 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1846 {
1847 /* cast away the const for active_rxon in this function */
1848 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1849 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1850 int rc = 0;
1851 bool new_assoc =
1852 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1853
1854 if (!iwl_is_alive(priv))
1855 return -1;
1856
1857 /* always get timestamp with Rx frame */
1858 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1859
1860 /* select antenna */
1861 staging_rxon->flags &=
1862 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1863 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1864
1865 rc = iwl_check_rxon_cmd(priv);
1866 if (rc) {
1867 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1868 return -EINVAL;
1869 }
1870
1871 /* If we don't need to send a full RXON, we can use
1872 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1873 * and other flags for the current radio configuration. */
1874 if (!iwl_full_rxon_required(priv)) {
1875 rc = iwl_send_rxon_assoc(priv);
1876 if (rc) {
1877 IWL_ERR(priv, "Error setting RXON_ASSOC "
1878 "configuration (%d).\n", rc);
1879 return rc;
1880 }
1881
1882 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1883
1884 return 0;
1885 }
1886
1887 /* If we are currently associated and the new config requires
1888 * an RXON_ASSOC and the new config wants the associated mask enabled,
1889 * we must clear the associated from the active configuration
1890 * before we apply the new config */
1891 if (iwl_is_associated(priv) && new_assoc) {
1892 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1893 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1894
1895 /*
1896 * reserved4 and 5 could have been filled by the iwlcore code.
1897 * Let's clear them before pushing to the 3945.
1898 */
1899 active_rxon->reserved4 = 0;
1900 active_rxon->reserved5 = 0;
1901 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1902 sizeof(struct iwl3945_rxon_cmd),
1903 &priv->active_rxon);
1904
1905 /* If the mask clearing failed then we set
1906 * active_rxon back to what it was previously */
1907 if (rc) {
1908 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1909 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1910 "configuration (%d).\n", rc);
1911 return rc;
1912 }
1913 }
1914
1915 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1916 "* with%s RXON_FILTER_ASSOC_MSK\n"
1917 "* channel = %d\n"
1918 "* bssid = %pM\n",
1919 (new_assoc ? "" : "out"),
1920 le16_to_cpu(staging_rxon->channel),
1921 staging_rxon->bssid_addr);
1922
1923 /*
1924 * reserved4 and 5 could have been filled by the iwlcore code.
1925 * Let's clear them before pushing to the 3945.
1926 */
1927 staging_rxon->reserved4 = 0;
1928 staging_rxon->reserved5 = 0;
1929
1930 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1931
1932 /* Apply the new configuration */
1933 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1934 sizeof(struct iwl3945_rxon_cmd),
1935 staging_rxon);
1936 if (rc) {
1937 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1938 return rc;
1939 }
1940
1941 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1942
1943 iwl_clear_stations_table(priv);
1944
1945 /* If we issue a new RXON command which required a tune then we must
1946 * send a new TXPOWER command or we won't be able to Tx any frames */
1947 rc = priv->cfg->ops->lib->send_tx_power(priv);
1948 if (rc) {
1949 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1950 return rc;
1951 }
1952
1953 /* Add the broadcast address so we can send broadcast frames */
1954 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1955 IWL_INVALID_STATION) {
1956 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1957 return -EIO;
1958 }
1959
1960 /* If we have set the ASSOC_MSK and we are in BSS mode then
1961 * add the IWL_AP_ID to the station rate table */
1962 if (iwl_is_associated(priv) &&
1963 (priv->iw_mode == NL80211_IFTYPE_STATION))
1964 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1965 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1966 IWL_ERR(priv, "Error adding AP address for transmit\n");
1967 return -EIO;
1968 }
1969
1970 /* Init the hardware's rate fallback order based on the band */
1971 rc = iwl3945_init_hw_rate_table(priv);
1972 if (rc) {
1973 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1974 return -EIO;
1975 }
1976
1977 return 0;
1978 }
1979
1980 /**
1981 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1982 *
1983 * -- reset periodic timer
1984 * -- see if temp has changed enough to warrant re-calibration ... if so:
1985 * -- correct coeffs for temp (can reset temp timer)
1986 * -- save this temp as "last",
1987 * -- send new set of gain settings to NIC
1988 * NOTE: This should continue working, even when we're not associated,
1989 * so we can keep our internal table of scan powers current. */
1990 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1991 {
1992 /* This will kick in the "brute force"
1993 * iwl3945_hw_reg_comp_txpower_temp() below */
1994 if (!is_temp_calib_needed(priv))
1995 goto reschedule;
1996
1997 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1998 * This is based *only* on current temperature,
1999 * ignoring any previous power measurements */
2000 iwl3945_hw_reg_comp_txpower_temp(priv);
2001
2002 reschedule:
2003 queue_delayed_work(priv->workqueue,
2004 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2005 }
2006
2007 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2008 {
2009 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2010 thermal_periodic.work);
2011
2012 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2013 return;
2014
2015 mutex_lock(&priv->mutex);
2016 iwl3945_reg_txpower_periodic(priv);
2017 mutex_unlock(&priv->mutex);
2018 }
2019
2020 /**
2021 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2022 * for the channel.
2023 *
2024 * This function is used when initializing channel-info structs.
2025 *
2026 * NOTE: These channel groups do *NOT* match the bands above!
2027 * These channel groups are based on factory-tested channels;
2028 * on A-band, EEPROM's "group frequency" entries represent the top
2029 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2030 */
2031 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2032 const struct iwl_channel_info *ch_info)
2033 {
2034 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2035 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2036 u8 group;
2037 u16 group_index = 0; /* based on factory calib frequencies */
2038 u8 grp_channel;
2039
2040 /* Find the group index for the channel ... don't use index 1(?) */
2041 if (is_channel_a_band(ch_info)) {
2042 for (group = 1; group < 5; group++) {
2043 grp_channel = ch_grp[group].group_channel;
2044 if (ch_info->channel <= grp_channel) {
2045 group_index = group;
2046 break;
2047 }
2048 }
2049 /* group 4 has a few channels *above* its factory cal freq */
2050 if (group == 5)
2051 group_index = 4;
2052 } else
2053 group_index = 0; /* 2.4 GHz, group 0 */
2054
2055 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2056 group_index);
2057 return group_index;
2058 }
2059
2060 /**
2061 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2062 *
2063 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2064 * into radio/DSP gain settings table for requested power.
2065 */
2066 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2067 s8 requested_power,
2068 s32 setting_index, s32 *new_index)
2069 {
2070 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2071 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2072 s32 index0, index1;
2073 s32 power = 2 * requested_power;
2074 s32 i;
2075 const struct iwl3945_eeprom_txpower_sample *samples;
2076 s32 gains0, gains1;
2077 s32 res;
2078 s32 denominator;
2079
2080 chnl_grp = &eeprom->groups[setting_index];
2081 samples = chnl_grp->samples;
2082 for (i = 0; i < 5; i++) {
2083 if (power == samples[i].power) {
2084 *new_index = samples[i].gain_index;
2085 return 0;
2086 }
2087 }
2088
2089 if (power > samples[1].power) {
2090 index0 = 0;
2091 index1 = 1;
2092 } else if (power > samples[2].power) {
2093 index0 = 1;
2094 index1 = 2;
2095 } else if (power > samples[3].power) {
2096 index0 = 2;
2097 index1 = 3;
2098 } else {
2099 index0 = 3;
2100 index1 = 4;
2101 }
2102
2103 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2104 if (denominator == 0)
2105 return -EINVAL;
2106 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2107 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2108 res = gains0 + (gains1 - gains0) *
2109 ((s32) power - (s32) samples[index0].power) / denominator +
2110 (1 << 18);
2111 *new_index = res >> 19;
2112 return 0;
2113 }
2114
2115 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2116 {
2117 u32 i;
2118 s32 rate_index;
2119 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2120 const struct iwl3945_eeprom_txpower_group *group;
2121
2122 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2123
2124 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2125 s8 *clip_pwrs; /* table of power levels for each rate */
2126 s8 satur_pwr; /* saturation power for each chnl group */
2127 group = &eeprom->groups[i];
2128
2129 /* sanity check on factory saturation power value */
2130 if (group->saturation_power < 40) {
2131 IWL_WARN(priv, "Error: saturation power is %d, "
2132 "less than minimum expected 40\n",
2133 group->saturation_power);
2134 return;
2135 }
2136
2137 /*
2138 * Derive requested power levels for each rate, based on
2139 * hardware capabilities (saturation power for band).
2140 * Basic value is 3dB down from saturation, with further
2141 * power reductions for highest 3 data rates. These
2142 * backoffs provide headroom for high rate modulation
2143 * power peaks, without too much distortion (clipping).
2144 */
2145 /* we'll fill in this array with h/w max power levels */
2146 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2147
2148 /* divide factory saturation power by 2 to find -3dB level */
2149 satur_pwr = (s8) (group->saturation_power >> 1);
2150
2151 /* fill in channel group's nominal powers for each rate */
2152 for (rate_index = 0;
2153 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2154 switch (rate_index) {
2155 case IWL_RATE_36M_INDEX_TABLE:
2156 if (i == 0) /* B/G */
2157 *clip_pwrs = satur_pwr;
2158 else /* A */
2159 *clip_pwrs = satur_pwr - 5;
2160 break;
2161 case IWL_RATE_48M_INDEX_TABLE:
2162 if (i == 0)
2163 *clip_pwrs = satur_pwr - 7;
2164 else
2165 *clip_pwrs = satur_pwr - 10;
2166 break;
2167 case IWL_RATE_54M_INDEX_TABLE:
2168 if (i == 0)
2169 *clip_pwrs = satur_pwr - 9;
2170 else
2171 *clip_pwrs = satur_pwr - 12;
2172 break;
2173 default:
2174 *clip_pwrs = satur_pwr;
2175 break;
2176 }
2177 }
2178 }
2179 }
2180
2181 /**
2182 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2183 *
2184 * Second pass (during init) to set up priv->channel_info
2185 *
2186 * Set up Tx-power settings in our channel info database for each VALID
2187 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2188 * and current temperature.
2189 *
2190 * Since this is based on current temperature (at init time), these values may
2191 * not be valid for very long, but it gives us a starting/default point,
2192 * and allows us to active (i.e. using Tx) scan.
2193 *
2194 * This does *not* write values to NIC, just sets up our internal table.
2195 */
2196 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2197 {
2198 struct iwl_channel_info *ch_info = NULL;
2199 struct iwl3945_channel_power_info *pwr_info;
2200 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2201 int delta_index;
2202 u8 rate_index;
2203 u8 scan_tbl_index;
2204 const s8 *clip_pwrs; /* array of power levels for each rate */
2205 u8 gain, dsp_atten;
2206 s8 power;
2207 u8 pwr_index, base_pwr_index, a_band;
2208 u8 i;
2209 int temperature;
2210
2211 /* save temperature reference,
2212 * so we can determine next time to calibrate */
2213 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2214 priv->last_temperature = temperature;
2215
2216 iwl3945_hw_reg_init_channel_groups(priv);
2217
2218 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2219 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2220 i++, ch_info++) {
2221 a_band = is_channel_a_band(ch_info);
2222 if (!is_channel_valid(ch_info))
2223 continue;
2224
2225 /* find this channel's channel group (*not* "band") index */
2226 ch_info->group_index =
2227 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2228
2229 /* Get this chnlgrp's rate->max/clip-powers table */
2230 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2231
2232 /* calculate power index *adjustment* value according to
2233 * diff between current temperature and factory temperature */
2234 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2235 eeprom->groups[ch_info->group_index].
2236 temperature);
2237
2238 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2239 ch_info->channel, delta_index, temperature +
2240 IWL_TEMP_CONVERT);
2241
2242 /* set tx power value for all OFDM rates */
2243 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2244 rate_index++) {
2245 s32 uninitialized_var(power_idx);
2246 int rc;
2247
2248 /* use channel group's clip-power table,
2249 * but don't exceed channel's max power */
2250 s8 pwr = min(ch_info->max_power_avg,
2251 clip_pwrs[rate_index]);
2252
2253 pwr_info = &ch_info->power_info[rate_index];
2254
2255 /* get base (i.e. at factory-measured temperature)
2256 * power table index for this rate's power */
2257 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2258 ch_info->group_index,
2259 &power_idx);
2260 if (rc) {
2261 IWL_ERR(priv, "Invalid power index\n");
2262 return rc;
2263 }
2264 pwr_info->base_power_index = (u8) power_idx;
2265
2266 /* temperature compensate */
2267 power_idx += delta_index;
2268
2269 /* stay within range of gain table */
2270 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2271
2272 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2273 pwr_info->requested_power = pwr;
2274 pwr_info->power_table_index = (u8) power_idx;
2275 pwr_info->tpc.tx_gain =
2276 power_gain_table[a_band][power_idx].tx_gain;
2277 pwr_info->tpc.dsp_atten =
2278 power_gain_table[a_band][power_idx].dsp_atten;
2279 }
2280
2281 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2282 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2283 power = pwr_info->requested_power +
2284 IWL_CCK_FROM_OFDM_POWER_DIFF;
2285 pwr_index = pwr_info->power_table_index +
2286 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2287 base_pwr_index = pwr_info->base_power_index +
2288 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2289
2290 /* stay within table range */
2291 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2292 gain = power_gain_table[a_band][pwr_index].tx_gain;
2293 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2294
2295 /* fill each CCK rate's iwl3945_channel_power_info structure
2296 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2297 * NOTE: CCK rates start at end of OFDM rates! */
2298 for (rate_index = 0;
2299 rate_index < IWL_CCK_RATES; rate_index++) {
2300 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2301 pwr_info->requested_power = power;
2302 pwr_info->power_table_index = pwr_index;
2303 pwr_info->base_power_index = base_pwr_index;
2304 pwr_info->tpc.tx_gain = gain;
2305 pwr_info->tpc.dsp_atten = dsp_atten;
2306 }
2307
2308 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2309 for (scan_tbl_index = 0;
2310 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2311 s32 actual_index = (scan_tbl_index == 0) ?
2312 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2313 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2314 actual_index, clip_pwrs, ch_info, a_band);
2315 }
2316 }
2317
2318 return 0;
2319 }
2320
2321 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2322 {
2323 int rc;
2324
2325 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2326 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2327 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2328 if (rc < 0)
2329 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2330
2331 return 0;
2332 }
2333
2334 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2335 {
2336 int txq_id = txq->q.id;
2337
2338 struct iwl3945_shared *shared_data = priv->shared_virt;
2339
2340 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2341
2342 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2343 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2344
2345 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2346 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2347 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2348 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2349 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2350 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2351
2352 /* fake read to flush all prev. writes */
2353 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2354
2355 return 0;
2356 }
2357
2358 /*
2359 * HCMD utils
2360 */
2361 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2362 {
2363 switch (cmd_id) {
2364 case REPLY_RXON:
2365 return sizeof(struct iwl3945_rxon_cmd);
2366 case POWER_TABLE_CMD:
2367 return sizeof(struct iwl3945_powertable_cmd);
2368 default:
2369 return len;
2370 }
2371 }
2372
2373
2374 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2375 {
2376 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2377 addsta->mode = cmd->mode;
2378 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2379 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2380 addsta->station_flags = cmd->station_flags;
2381 addsta->station_flags_msk = cmd->station_flags_msk;
2382 addsta->tid_disable_tx = cpu_to_le16(0);
2383 addsta->rate_n_flags = cmd->rate_n_flags;
2384 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2385 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2386 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2387
2388 return (u16)sizeof(struct iwl3945_addsta_cmd);
2389 }
2390
2391
2392 /**
2393 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2394 */
2395 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2396 {
2397 int rc, i, index, prev_index;
2398 struct iwl3945_rate_scaling_cmd rate_cmd = {
2399 .reserved = {0, 0, 0},
2400 };
2401 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2402
2403 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2404 index = iwl3945_rates[i].table_rs_index;
2405
2406 table[index].rate_n_flags =
2407 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2408 table[index].try_cnt = priv->retry_rate;
2409 prev_index = iwl3945_get_prev_ieee_rate(i);
2410 table[index].next_rate_index =
2411 iwl3945_rates[prev_index].table_rs_index;
2412 }
2413
2414 switch (priv->band) {
2415 case IEEE80211_BAND_5GHZ:
2416 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2417 /* If one of the following CCK rates is used,
2418 * have it fall back to the 6M OFDM rate */
2419 for (i = IWL_RATE_1M_INDEX_TABLE;
2420 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2421 table[i].next_rate_index =
2422 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2423
2424 /* Don't fall back to CCK rates */
2425 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2426 IWL_RATE_9M_INDEX_TABLE;
2427
2428 /* Don't drop out of OFDM rates */
2429 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2430 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2431 break;
2432
2433 case IEEE80211_BAND_2GHZ:
2434 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2435 /* If an OFDM rate is used, have it fall back to the
2436 * 1M CCK rates */
2437
2438 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2439 iwl_is_associated(priv)) {
2440
2441 index = IWL_FIRST_CCK_RATE;
2442 for (i = IWL_RATE_6M_INDEX_TABLE;
2443 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2444 table[i].next_rate_index =
2445 iwl3945_rates[index].table_rs_index;
2446
2447 index = IWL_RATE_11M_INDEX_TABLE;
2448 /* CCK shouldn't fall back to OFDM... */
2449 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2450 }
2451 break;
2452
2453 default:
2454 WARN_ON(1);
2455 break;
2456 }
2457
2458 /* Update the rate scaling for control frame Tx */
2459 rate_cmd.table_id = 0;
2460 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2461 &rate_cmd);
2462 if (rc)
2463 return rc;
2464
2465 /* Update the rate scaling for data frame Tx */
2466 rate_cmd.table_id = 1;
2467 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2468 &rate_cmd);
2469 }
2470
2471 /* Called when initializing driver */
2472 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2473 {
2474 memset((void *)&priv->hw_params, 0,
2475 sizeof(struct iwl_hw_params));
2476
2477 priv->shared_virt =
2478 pci_alloc_consistent(priv->pci_dev,
2479 sizeof(struct iwl3945_shared),
2480 &priv->shared_phys);
2481
2482 if (!priv->shared_virt) {
2483 IWL_ERR(priv, "failed to allocate pci memory\n");
2484 mutex_unlock(&priv->mutex);
2485 return -ENOMEM;
2486 }
2487
2488 /* Assign number of Usable TX queues */
2489 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2490
2491 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2492 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2493 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2494 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2495 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2496 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2497
2498 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2499 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2500
2501 return 0;
2502 }
2503
2504 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2505 struct iwl3945_frame *frame, u8 rate)
2506 {
2507 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2508 unsigned int frame_size;
2509
2510 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2511 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2512
2513 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2514 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2515
2516 frame_size = iwl3945_fill_beacon_frame(priv,
2517 tx_beacon_cmd->frame,
2518 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2519
2520 BUG_ON(frame_size > MAX_MPDU_SIZE);
2521 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2522
2523 tx_beacon_cmd->tx.rate = rate;
2524 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2525 TX_CMD_FLG_TSF_MSK);
2526
2527 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2528 tx_beacon_cmd->tx.supp_rates[0] =
2529 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2530
2531 tx_beacon_cmd->tx.supp_rates[1] =
2532 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2533
2534 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2535 }
2536
2537 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2538 {
2539 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2540 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2541 }
2542
2543 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2544 {
2545 INIT_DELAYED_WORK(&priv->thermal_periodic,
2546 iwl3945_bg_reg_txpower_periodic);
2547 }
2548
2549 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2550 {
2551 cancel_delayed_work(&priv->thermal_periodic);
2552 }
2553
2554 /* check contents of special bootstrap uCode SRAM */
2555 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2556 {
2557 __le32 *image = priv->ucode_boot.v_addr;
2558 u32 len = priv->ucode_boot.len;
2559 u32 reg;
2560 u32 val;
2561
2562 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2563
2564 /* verify BSM SRAM contents */
2565 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2566 for (reg = BSM_SRAM_LOWER_BOUND;
2567 reg < BSM_SRAM_LOWER_BOUND + len;
2568 reg += sizeof(u32), image++) {
2569 val = iwl_read_prph(priv, reg);
2570 if (val != le32_to_cpu(*image)) {
2571 IWL_ERR(priv, "BSM uCode verification failed at "
2572 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2573 BSM_SRAM_LOWER_BOUND,
2574 reg - BSM_SRAM_LOWER_BOUND, len,
2575 val, le32_to_cpu(*image));
2576 return -EIO;
2577 }
2578 }
2579
2580 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2581
2582 return 0;
2583 }
2584
2585
2586 /******************************************************************************
2587 *
2588 * EEPROM related functions
2589 *
2590 ******************************************************************************/
2591
2592 /*
2593 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2594 * embedded controller) as EEPROM reader; each read is a series of pulses
2595 * to/from the EEPROM chip, not a single event, so even reads could conflict
2596 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2597 * simply claims ownership, which should be safe when this function is called
2598 * (i.e. before loading uCode!).
2599 */
2600 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2601 {
2602 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2603 return 0;
2604 }
2605
2606
2607 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2608 {
2609 return;
2610 }
2611
2612 /**
2613 * iwl3945_load_bsm - Load bootstrap instructions
2614 *
2615 * BSM operation:
2616 *
2617 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2618 * in special SRAM that does not power down during RFKILL. When powering back
2619 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2620 * the bootstrap program into the on-board processor, and starts it.
2621 *
2622 * The bootstrap program loads (via DMA) instructions and data for a new
2623 * program from host DRAM locations indicated by the host driver in the
2624 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2625 * automatically.
2626 *
2627 * When initializing the NIC, the host driver points the BSM to the
2628 * "initialize" uCode image. This uCode sets up some internal data, then
2629 * notifies host via "initialize alive" that it is complete.
2630 *
2631 * The host then replaces the BSM_DRAM_* pointer values to point to the
2632 * normal runtime uCode instructions and a backup uCode data cache buffer
2633 * (filled initially with starting data values for the on-board processor),
2634 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2635 * which begins normal operation.
2636 *
2637 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2638 * the backup data cache in DRAM before SRAM is powered down.
2639 *
2640 * When powering back up, the BSM loads the bootstrap program. This reloads
2641 * the runtime uCode instructions and the backup data cache into SRAM,
2642 * and re-launches the runtime uCode from where it left off.
2643 */
2644 static int iwl3945_load_bsm(struct iwl_priv *priv)
2645 {
2646 __le32 *image = priv->ucode_boot.v_addr;
2647 u32 len = priv->ucode_boot.len;
2648 dma_addr_t pinst;
2649 dma_addr_t pdata;
2650 u32 inst_len;
2651 u32 data_len;
2652 int rc;
2653 int i;
2654 u32 done;
2655 u32 reg_offset;
2656
2657 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2658
2659 /* make sure bootstrap program is no larger than BSM's SRAM size */
2660 if (len > IWL39_MAX_BSM_SIZE)
2661 return -EINVAL;
2662
2663 /* Tell bootstrap uCode where to find the "Initialize" uCode
2664 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2665 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2666 * after the "initialize" uCode has run, to point to
2667 * runtime/protocol instructions and backup data cache. */
2668 pinst = priv->ucode_init.p_addr;
2669 pdata = priv->ucode_init_data.p_addr;
2670 inst_len = priv->ucode_init.len;
2671 data_len = priv->ucode_init_data.len;
2672
2673 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2674 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2675 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2676 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2677
2678 /* Fill BSM memory with bootstrap instructions */
2679 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2680 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2681 reg_offset += sizeof(u32), image++)
2682 _iwl_write_prph(priv, reg_offset,
2683 le32_to_cpu(*image));
2684
2685 rc = iwl3945_verify_bsm(priv);
2686 if (rc)
2687 return rc;
2688
2689 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2690 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2691 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2692 IWL39_RTC_INST_LOWER_BOUND);
2693 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2694
2695 /* Load bootstrap code into instruction SRAM now,
2696 * to prepare to load "initialize" uCode */
2697 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2698 BSM_WR_CTRL_REG_BIT_START);
2699
2700 /* Wait for load of bootstrap uCode to finish */
2701 for (i = 0; i < 100; i++) {
2702 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2703 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2704 break;
2705 udelay(10);
2706 }
2707 if (i < 100)
2708 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2709 else {
2710 IWL_ERR(priv, "BSM write did not complete!\n");
2711 return -EIO;
2712 }
2713
2714 /* Enable future boot loads whenever power management unit triggers it
2715 * (e.g. when powering back up after power-save shutdown) */
2716 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2717 BSM_WR_CTRL_REG_BIT_START_EN);
2718
2719 return 0;
2720 }
2721
2722 #define IWL3945_UCODE_GET(item) \
2723 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2724 u32 api_ver) \
2725 { \
2726 return le32_to_cpu(ucode->u.v1.item); \
2727 }
2728
2729 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2730 {
2731 return UCODE_HEADER_SIZE(1);
2732 }
2733 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2734 u32 api_ver)
2735 {
2736 return 0;
2737 }
2738 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2739 u32 api_ver)
2740 {
2741 return (u8 *) ucode->u.v1.data;
2742 }
2743
2744 IWL3945_UCODE_GET(inst_size);
2745 IWL3945_UCODE_GET(data_size);
2746 IWL3945_UCODE_GET(init_size);
2747 IWL3945_UCODE_GET(init_data_size);
2748 IWL3945_UCODE_GET(boot_size);
2749
2750 static struct iwl_hcmd_ops iwl3945_hcmd = {
2751 .rxon_assoc = iwl3945_send_rxon_assoc,
2752 .commit_rxon = iwl3945_commit_rxon,
2753 };
2754
2755 static struct iwl_ucode_ops iwl3945_ucode = {
2756 .get_header_size = iwl3945_ucode_get_header_size,
2757 .get_build = iwl3945_ucode_get_build,
2758 .get_inst_size = iwl3945_ucode_get_inst_size,
2759 .get_data_size = iwl3945_ucode_get_data_size,
2760 .get_init_size = iwl3945_ucode_get_init_size,
2761 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2762 .get_boot_size = iwl3945_ucode_get_boot_size,
2763 .get_data = iwl3945_ucode_get_data,
2764 };
2765
2766 static struct iwl_lib_ops iwl3945_lib = {
2767 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2768 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2769 .txq_init = iwl3945_hw_tx_queue_init,
2770 .load_ucode = iwl3945_load_bsm,
2771 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2772 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2773 .apm_ops = {
2774 .init = iwl3945_apm_init,
2775 .stop = iwl_apm_stop,
2776 .config = iwl3945_nic_config,
2777 .set_pwr_src = iwl3945_set_pwr_src,
2778 },
2779 .eeprom_ops = {
2780 .regulatory_bands = {
2781 EEPROM_REGULATORY_BAND_1_CHANNELS,
2782 EEPROM_REGULATORY_BAND_2_CHANNELS,
2783 EEPROM_REGULATORY_BAND_3_CHANNELS,
2784 EEPROM_REGULATORY_BAND_4_CHANNELS,
2785 EEPROM_REGULATORY_BAND_5_CHANNELS,
2786 EEPROM_REGULATORY_BAND_NO_HT40,
2787 EEPROM_REGULATORY_BAND_NO_HT40,
2788 },
2789 .verify_signature = iwlcore_eeprom_verify_signature,
2790 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2791 .release_semaphore = iwl3945_eeprom_release_semaphore,
2792 .query_addr = iwlcore_eeprom_query_addr,
2793 },
2794 .send_tx_power = iwl3945_send_tx_power,
2795 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2796 .post_associate = iwl3945_post_associate,
2797 .isr = iwl_isr_legacy,
2798 .config_ap = iwl3945_config_ap,
2799 };
2800
2801 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2802 .get_hcmd_size = iwl3945_get_hcmd_size,
2803 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2804 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2805 };
2806
2807 static struct iwl_ops iwl3945_ops = {
2808 .ucode = &iwl3945_ucode,
2809 .lib = &iwl3945_lib,
2810 .hcmd = &iwl3945_hcmd,
2811 .utils = &iwl3945_hcmd_utils,
2812 .led = &iwl3945_led_ops,
2813 };
2814
2815 static struct iwl_cfg iwl3945_bg_cfg = {
2816 .name = "3945BG",
2817 .fw_name_pre = IWL3945_FW_PRE,
2818 .ucode_api_max = IWL3945_UCODE_API_MAX,
2819 .ucode_api_min = IWL3945_UCODE_API_MIN,
2820 .sku = IWL_SKU_G,
2821 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2822 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2823 .ops = &iwl3945_ops,
2824 .num_of_queues = IWL39_NUM_QUEUES,
2825 .mod_params = &iwl3945_mod_params,
2826 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2827 .set_l0s = false,
2828 .use_bsm = true,
2829 .use_isr_legacy = true,
2830 .ht_greenfield_support = false,
2831 .led_compensation = 64,
2832 .broken_powersave = true,
2833 };
2834
2835 static struct iwl_cfg iwl3945_abg_cfg = {
2836 .name = "3945ABG",
2837 .fw_name_pre = IWL3945_FW_PRE,
2838 .ucode_api_max = IWL3945_UCODE_API_MAX,
2839 .ucode_api_min = IWL3945_UCODE_API_MIN,
2840 .sku = IWL_SKU_A|IWL_SKU_G,
2841 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2842 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2843 .ops = &iwl3945_ops,
2844 .num_of_queues = IWL39_NUM_QUEUES,
2845 .mod_params = &iwl3945_mod_params,
2846 .use_isr_legacy = true,
2847 .ht_greenfield_support = false,
2848 .led_compensation = 64,
2849 .broken_powersave = true,
2850 };
2851
2852 struct pci_device_id iwl3945_hw_card_ids[] = {
2853 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2854 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2855 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2856 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2857 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2858 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2859 {0}
2860 };
2861
2862 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
kernel source for telekom puls (alcatel/mediatek)