1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *****************************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/sched.h>
34 #include <linux/skbuff.h>
35 #include <linux/netdevice.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/etherdevice.h>
39 #include <asm/unaligned.h>
40 #include <net/mac80211.h>
43 #include "iwl-3945-fh.h"
44 #include "iwl-commands.h"
47 #include "iwl-eeprom.h"
49 #include "iwl-helpers.h"
51 #include "iwl-3945-led.h"
53 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
73 const struct iwl3945_rate_info iwl3945_rates
[IWL_RATE_COUNT_3945
] = {
74 IWL_DECLARE_RATE_INFO(1, INV
, 2, INV
, 2, INV
, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV
, 48, INV
, 48, INV
),/* 54mbps */
88 /* 1 = enable the iwl3945_disable_events() function */
89 #define IWL_EVT_DISABLE (0)
90 #define IWL_EVT_DISABLE_SIZE (1532/32)
93 * iwl3945_disable_events - Disable selected events in uCode event log
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
101 void iwl3945_disable_events(struct iwl_priv
*priv
)
104 u32 base
; /* SRAM address of event log header */
105 u32 disable_ptr
; /* SRAM address of event-disable bitmap array */
106 u32 array_size
; /* # of u32 entries in array */
107 u32 evt_disable
[IWL_EVT_DISABLE_SIZE
] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
157 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
158 if (!iwl3945_hw_valid_rtc_data_addr(base
)) {
159 IWL_ERR(priv
, "Invalid event log pointer 0x%08X\n", base
);
163 disable_ptr
= iwl_read_targ_mem(priv
, base
+ (4 * sizeof(u32
)));
164 array_size
= iwl_read_targ_mem(priv
, base
+ (5 * sizeof(u32
)));
166 if (IWL_EVT_DISABLE
&& (array_size
== IWL_EVT_DISABLE_SIZE
)) {
167 IWL_DEBUG_INFO(priv
, "Disabling selected uCode log events at 0x%x\n",
169 for (i
= 0; i
< IWL_EVT_DISABLE_SIZE
; i
++)
170 iwl_write_targ_mem(priv
,
171 disable_ptr
+ (i
* sizeof(u32
)),
175 IWL_DEBUG_INFO(priv
, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv
, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv
, " in SRAM at 0x%x, size %d u32s\n",
178 disable_ptr
, array_size
);
183 static int iwl3945_hwrate_to_plcp_idx(u8 plcp
)
187 for (idx
= 0; idx
< IWL_RATE_COUNT
; idx
++)
188 if (iwl3945_rates
[idx
].plcp
== plcp
)
193 #ifdef CONFIG_IWLWIFI_DEBUG
194 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
196 static const char *iwl3945_get_tx_fail_reason(u32 status
)
198 switch (status
& TX_STATUS_MSK
) {
199 case TX_STATUS_SUCCESS
:
201 TX_STATUS_ENTRY(SHORT_LIMIT
);
202 TX_STATUS_ENTRY(LONG_LIMIT
);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN
);
204 TX_STATUS_ENTRY(MGMNT_ABORT
);
205 TX_STATUS_ENTRY(NEXT_FRAG
);
206 TX_STATUS_ENTRY(LIFE_EXPIRE
);
207 TX_STATUS_ENTRY(DEST_PS
);
208 TX_STATUS_ENTRY(ABORTED
);
209 TX_STATUS_ENTRY(BT_RETRY
);
210 TX_STATUS_ENTRY(STA_INVALID
);
211 TX_STATUS_ENTRY(FRAG_DROPPED
);
212 TX_STATUS_ENTRY(TID_DISABLE
);
213 TX_STATUS_ENTRY(FRAME_FLUSHED
);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL
);
215 TX_STATUS_ENTRY(TX_LOCKED
);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR
);
222 static inline const char *iwl3945_get_tx_fail_reason(u32 status
)
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
233 int iwl3945_rs_next_rate(struct iwl_priv
*priv
, int rate
)
235 int next_rate
= iwl3945_get_prev_ieee_rate(rate
);
237 switch (priv
->band
) {
238 case IEEE80211_BAND_5GHZ
:
239 if (rate
== IWL_RATE_12M_INDEX
)
240 next_rate
= IWL_RATE_9M_INDEX
;
241 else if (rate
== IWL_RATE_6M_INDEX
)
242 next_rate
= IWL_RATE_6M_INDEX
;
244 case IEEE80211_BAND_2GHZ
:
245 if (!(priv
->sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
246 iwl_is_associated(priv
)) {
247 if (rate
== IWL_RATE_11M_INDEX
)
248 next_rate
= IWL_RATE_5M_INDEX
;
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
267 static void iwl3945_tx_queue_reclaim(struct iwl_priv
*priv
,
268 int txq_id
, int index
)
270 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
271 struct iwl_queue
*q
= &txq
->q
;
272 struct iwl_tx_info
*tx_info
;
274 BUG_ON(txq_id
== IWL_CMD_QUEUE_NUM
);
276 for (index
= iwl_queue_inc_wrap(index
, q
->n_bd
); q
->read_ptr
!= index
;
277 q
->read_ptr
= iwl_queue_inc_wrap(q
->read_ptr
, q
->n_bd
)) {
279 tx_info
= &txq
->txb
[txq
->q
.read_ptr
];
280 ieee80211_tx_status_irqsafe(priv
->hw
, tx_info
->skb
[0]);
281 tx_info
->skb
[0] = NULL
;
282 priv
->cfg
->ops
->lib
->txq_free_tfd(priv
, txq
);
285 if (iwl_queue_space(q
) > q
->low_mark
&& (txq_id
>= 0) &&
286 (txq_id
!= IWL_CMD_QUEUE_NUM
) &&
287 priv
->mac80211_registered
)
288 iwl_wake_queue(priv
, txq_id
);
292 * iwl3945_rx_reply_tx - Handle Tx response
294 static void iwl3945_rx_reply_tx(struct iwl_priv
*priv
,
295 struct iwl_rx_mem_buffer
*rxb
)
297 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
298 u16 sequence
= le16_to_cpu(pkt
->hdr
.sequence
);
299 int txq_id
= SEQ_TO_QUEUE(sequence
);
300 int index
= SEQ_TO_INDEX(sequence
);
301 struct iwl_tx_queue
*txq
= &priv
->txq
[txq_id
];
302 struct ieee80211_tx_info
*info
;
303 struct iwl3945_tx_resp
*tx_resp
= (void *)&pkt
->u
.raw
[0];
304 u32 status
= le32_to_cpu(tx_resp
->status
);
308 if ((index
>= txq
->q
.n_bd
) || (iwl_queue_used(&txq
->q
, index
) == 0)) {
309 IWL_ERR(priv
, "Read index for DMA queue txq_id (%d) index %d "
310 "is out of range [0-%d] %d %d\n", txq_id
,
311 index
, txq
->q
.n_bd
, txq
->q
.write_ptr
,
316 info
= IEEE80211_SKB_CB(txq
->txb
[txq
->q
.read_ptr
].skb
[0]);
317 ieee80211_tx_info_clear_status(info
);
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx
= iwl3945_hwrate_to_plcp_idx(tx_resp
->rate
);
321 if (info
->band
== IEEE80211_BAND_5GHZ
)
322 rate_idx
-= IWL_FIRST_OFDM_RATE
;
324 fail
= tx_resp
->failure_frame
;
326 info
->status
.rates
[0].idx
= rate_idx
;
327 info
->status
.rates
[0].count
= fail
+ 1; /* add final attempt */
329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
330 info
->flags
|= ((status
& TX_STATUS_MSK
) == TX_STATUS_SUCCESS
) ?
331 IEEE80211_TX_STAT_ACK
: 0;
333 IWL_DEBUG_TX(priv
, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
334 txq_id
, iwl3945_get_tx_fail_reason(status
), status
,
335 tx_resp
->rate
, tx_resp
->failure_frame
);
337 IWL_DEBUG_TX_REPLY(priv
, "Tx queue reclaim %d\n", index
);
338 iwl3945_tx_queue_reclaim(priv
, txq_id
, index
);
340 if (iwl_check_bits(status
, TX_ABORT_REQUIRED_MSK
))
341 IWL_ERR(priv
, "TODO: Implement Tx ABORT REQUIRED!!!\n");
346 /*****************************************************************************
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
350 * RX handler implementations
352 *****************************************************************************/
354 void iwl3945_hw_rx_statistics(struct iwl_priv
*priv
,
355 struct iwl_rx_mem_buffer
*rxb
)
357 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
358 IWL_DEBUG_RX(priv
, "Statistics notification received (%d vs %d).\n",
359 (int)sizeof(struct iwl3945_notif_statistics
),
360 le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
);
362 memcpy(&priv
->statistics_39
, pkt
->u
.raw
, sizeof(priv
->statistics_39
));
365 /******************************************************************************
367 * Misc. internal state and helper functions
369 ******************************************************************************/
370 #ifdef CONFIG_IWLWIFI_DEBUG
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
379 static void _iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
380 struct iwl_rx_packet
*pkt
,
381 struct ieee80211_hdr
*header
, int group100
)
384 u32 print_summary
= 0;
385 u32 print_dump
= 0; /* set to 1 to dump all frames' contents */
401 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
402 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
403 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
404 u8
*data
= IWL_RX_DATA(pkt
);
407 fc
= header
->frame_control
;
408 seq_ctl
= le16_to_cpu(header
->seq_ctrl
);
411 channel
= le16_to_cpu(rx_hdr
->channel
);
412 phy_flags
= le16_to_cpu(rx_hdr
->phy_flags
);
413 length
= le16_to_cpu(rx_hdr
->len
);
415 /* end-of-frame status and timestamp */
416 status
= le32_to_cpu(rx_end
->status
);
417 bcn_tmr
= le32_to_cpu(rx_end
->beacon_timestamp
);
418 tsf_low
= le64_to_cpu(rx_end
->timestamp
) & 0x0ffffffff;
419 tsf
= le64_to_cpu(rx_end
->timestamp
);
421 /* signal statistics */
422 rssi
= rx_stats
->rssi
;
424 sig_avg
= le16_to_cpu(rx_stats
->sig_avg
);
425 noise_diff
= le16_to_cpu(rx_stats
->noise_diff
);
427 to_us
= !compare_ether_addr(header
->addr1
, priv
->mac_addr
);
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
431 if (to_us
&& (fc
& ~cpu_to_le16(IEEE80211_FCTL_PROTECTED
)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS
| IEEE80211_FTYPE_DATA
)) {
435 print_summary
= 1; /* print each frame */
436 else if (priv
->framecnt_to_us
< 100) {
437 priv
->framecnt_to_us
++;
440 priv
->framecnt_to_us
= 0;
445 /* print summary for all other frames */
455 else if (ieee80211_has_retry(fc
))
457 else if (ieee80211_is_assoc_resp(fc
))
459 else if (ieee80211_is_reassoc_resp(fc
))
461 else if (ieee80211_is_probe_resp(fc
)) {
463 print_dump
= 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc
)) {
466 print_dump
= 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc
))
469 else if (ieee80211_is_auth(fc
))
471 else if (ieee80211_is_deauth(fc
))
473 else if (ieee80211_is_disassoc(fc
))
478 rate
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
482 rate
= iwl3945_rates
[rate
].ieee
/ 2;
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
488 IWL_DEBUG_RX(priv
, "%s: mhd=0x%04x, dst=0x%02x, "
489 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
490 title
, le16_to_cpu(fc
), header
->addr1
[5],
491 length
, rssi
, channel
, rate
);
493 /* src/dst addresses assume managed mode */
494 IWL_DEBUG_RX(priv
, "%s: 0x%04x, dst=0x%02x, "
495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
497 title
, le16_to_cpu(fc
), header
->addr1
[5],
498 header
->addr3
[5], rssi
,
499 tsf_low
- priv
->scan_start_tsf
,
504 iwl_print_hex_dump(priv
, IWL_DL_RX
, data
, length
);
507 static void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
508 struct iwl_rx_packet
*pkt
,
509 struct ieee80211_hdr
*header
, int group100
)
511 if (iwl_get_debug_level(priv
) & IWL_DL_RX
)
512 _iwl3945_dbg_report_frame(priv
, pkt
, header
, group100
);
516 static inline void iwl3945_dbg_report_frame(struct iwl_priv
*priv
,
517 struct iwl_rx_packet
*pkt
,
518 struct ieee80211_hdr
*header
, int group100
)
523 /* This is necessary only for a number of statistics, see the caller. */
524 static int iwl3945_is_network_packet(struct iwl_priv
*priv
,
525 struct ieee80211_hdr
*header
)
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv
->iw_mode
) {
530 case NL80211_IFTYPE_ADHOC
: /* Header: Dest. | Source | BSSID */
531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header
->addr3
, priv
->bssid
);
533 case NL80211_IFTYPE_STATION
: /* Header: Dest. | AP{BSSID} | Source */
534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header
->addr2
, priv
->bssid
);
541 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv
*priv
,
542 struct iwl_rx_mem_buffer
*rxb
,
543 struct ieee80211_rx_status
*stats
)
545 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
546 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
547 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
548 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
549 u16 len
= le16_to_cpu(rx_hdr
->len
);
552 __le16 fc
= hdr
->frame_control
;
554 /* We received data from the HW, so stop the watchdog */
555 if (unlikely(len
+ IWL39_RX_FRAME_SIZE
>
556 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
)) {
557 IWL_DEBUG_DROP(priv
, "Corruption detected!\n");
561 /* We only process data packets if the interface is open */
562 if (unlikely(!priv
->is_open
)) {
563 IWL_DEBUG_DROP_LIMIT(priv
,
564 "Dropping packet while interface is not open.\n");
568 skb
= alloc_skb(IWL_LINK_HDR_MAX
* 2, GFP_ATOMIC
);
570 IWL_ERR(priv
, "alloc_skb failed\n");
574 if (!iwl3945_mod_params
.sw_crypto
)
575 iwl_set_decrypted_flag(priv
,
576 (struct ieee80211_hdr
*)rxb_addr(rxb
),
577 le32_to_cpu(rx_end
->status
), stats
);
579 skb_reserve(skb
, IWL_LINK_HDR_MAX
);
580 skb_add_rx_frag(skb
, 0, rxb
->page
,
581 (void *)rx_hdr
->payload
- (void *)pkt
, len
);
583 /* mac80211 currently doesn't support paged SKB. Convert it to
584 * linear SKB for management frame and data frame requires
585 * software decryption or software defragementation. */
586 if (ieee80211_is_mgmt(fc
) ||
587 ieee80211_has_protected(fc
) ||
588 ieee80211_has_morefrags(fc
) ||
589 le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
)
590 ret
= skb_linearize(skb
);
592 ret
= __pskb_pull_tail(skb
, min_t(u16
, IWL_LINK_HDR_MAX
, len
)) ?
601 * XXX: We cannot touch the page and its virtual memory (pkt) after
602 * here. It might have already been freed by the above skb change.
605 iwl_update_stats(priv
, false, fc
, len
);
606 memcpy(IEEE80211_SKB_RXCB(skb
), stats
, sizeof(*stats
));
608 ieee80211_rx(priv
->hw
, skb
);
610 priv
->alloc_rxb_page
--;
614 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
616 static void iwl3945_rx_reply_rx(struct iwl_priv
*priv
,
617 struct iwl_rx_mem_buffer
*rxb
)
619 struct ieee80211_hdr
*header
;
620 struct ieee80211_rx_status rx_status
;
621 struct iwl_rx_packet
*pkt
= rxb_addr(rxb
);
622 struct iwl3945_rx_frame_stats
*rx_stats
= IWL_RX_STATS(pkt
);
623 struct iwl3945_rx_frame_hdr
*rx_hdr
= IWL_RX_HDR(pkt
);
624 struct iwl3945_rx_frame_end
*rx_end
= IWL_RX_END(pkt
);
626 u16 rx_stats_sig_avg
= le16_to_cpu(rx_stats
->sig_avg
);
627 u16 rx_stats_noise_diff
= le16_to_cpu(rx_stats
->noise_diff
);
631 rx_status
.mactime
= le64_to_cpu(rx_end
->timestamp
);
633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr
->channel
));
634 rx_status
.band
= (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_BAND_24_MSK
) ?
635 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
637 rx_status
.rate_idx
= iwl3945_hwrate_to_plcp_idx(rx_hdr
->rate
);
638 if (rx_status
.band
== IEEE80211_BAND_5GHZ
)
639 rx_status
.rate_idx
-= IWL_FIRST_OFDM_RATE
;
641 rx_status
.antenna
= (le16_to_cpu(rx_hdr
->phy_flags
) &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK
) >> 4;
644 /* set the preamble flag if appropriate */
645 if (rx_hdr
->phy_flags
& RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
)
646 rx_status
.flag
|= RX_FLAG_SHORTPRE
;
648 if ((unlikely(rx_stats
->phy_count
> 20))) {
649 IWL_DEBUG_DROP(priv
, "dsp size out of range [0,20]: %d/n",
650 rx_stats
->phy_count
);
654 if (!(rx_end
->status
& RX_RES_STATUS_NO_CRC32_ERROR
)
655 || !(rx_end
->status
& RX_RES_STATUS_NO_RXE_OVERFLOW
)) {
656 IWL_DEBUG_RX(priv
, "Bad CRC or FIFO: 0x%08X.\n", rx_end
->status
);
662 /* Convert 3945's rssi indicator to dBm */
663 rx_status
.signal
= rx_stats
->rssi
- IWL39_RSSI_OFFSET
;
665 /* Set default noise value to -127 */
666 if (priv
->last_rx_noise
== 0)
667 priv
->last_rx_noise
= IWL_NOISE_MEAS_NOT_AVAILABLE
;
669 /* 3945 provides noise info for OFDM frames only.
670 * sig_avg and noise_diff are measured by the 3945's digital signal
671 * processor (DSP), and indicate linear levels of signal level and
672 * distortion/noise within the packet preamble after
673 * automatic gain control (AGC). sig_avg should stay fairly
674 * constant if the radio's AGC is working well.
675 * Since these values are linear (not dB or dBm), linear
676 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
677 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
678 * to obtain noise level in dBm.
679 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
680 if (rx_stats_noise_diff
) {
681 snr
= rx_stats_sig_avg
/ rx_stats_noise_diff
;
682 rx_status
.noise
= rx_status
.signal
-
683 iwl3945_calc_db_from_ratio(snr
);
685 rx_status
.noise
= priv
->last_rx_noise
;
689 IWL_DEBUG_STATS(priv
, "Rssi %d noise %d sig_avg %d noise_diff %d\n",
690 rx_status
.signal
, rx_status
.noise
,
691 rx_stats_sig_avg
, rx_stats_noise_diff
);
693 header
= (struct ieee80211_hdr
*)IWL_RX_DATA(pkt
);
695 network_packet
= iwl3945_is_network_packet(priv
, header
);
697 IWL_DEBUG_STATS_LIMIT(priv
, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
698 network_packet
? '*' : ' ',
699 le16_to_cpu(rx_hdr
->channel
),
700 rx_status
.signal
, rx_status
.signal
,
701 rx_status
.noise
, rx_status
.rate_idx
);
703 /* Set "1" to report good data frames in groups of 100 */
704 iwl3945_dbg_report_frame(priv
, pkt
, header
, 1);
705 iwl_dbg_log_rx_data_frame(priv
, le16_to_cpu(rx_hdr
->len
), header
);
707 if (network_packet
) {
708 priv
->last_beacon_time
= le32_to_cpu(rx_end
->beacon_timestamp
);
709 priv
->last_tsf
= le64_to_cpu(rx_end
->timestamp
);
710 priv
->last_rx_rssi
= rx_status
.signal
;
711 priv
->last_rx_noise
= rx_status
.noise
;
714 iwl3945_pass_packet_to_mac80211(priv
, rxb
, &rx_status
);
717 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
718 struct iwl_tx_queue
*txq
,
719 dma_addr_t addr
, u16 len
, u8 reset
, u8 pad
)
723 struct iwl3945_tfd
*tfd
, *tfd_tmp
;
726 tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
727 tfd
= &tfd_tmp
[q
->write_ptr
];
730 memset(tfd
, 0, sizeof(*tfd
));
732 count
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
734 if ((count
>= NUM_TFD_CHUNKS
) || (count
< 0)) {
735 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
740 tfd
->tbs
[count
].addr
= cpu_to_le32(addr
);
741 tfd
->tbs
[count
].len
= cpu_to_le32(len
);
745 tfd
->control_flags
= cpu_to_le32(TFD_CTL_COUNT_SET(count
) |
746 TFD_CTL_PAD_SET(pad
));
752 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
754 * Does NOT advance any indexes
756 void iwl3945_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
758 struct iwl3945_tfd
*tfd_tmp
= (struct iwl3945_tfd
*)txq
->tfds
;
759 int index
= txq
->q
.read_ptr
;
760 struct iwl3945_tfd
*tfd
= &tfd_tmp
[index
];
761 struct pci_dev
*dev
= priv
->pci_dev
;
766 counter
= TFD_CTL_COUNT_GET(le32_to_cpu(tfd
->control_flags
));
767 if (counter
> NUM_TFD_CHUNKS
) {
768 IWL_ERR(priv
, "Too many chunks: %i\n", counter
);
769 /* @todo issue fatal error, it is quite serious situation */
775 pci_unmap_single(dev
,
776 pci_unmap_addr(&txq
->meta
[index
], mapping
),
777 pci_unmap_len(&txq
->meta
[index
], len
),
780 /* unmap chunks if any */
782 for (i
= 1; i
< counter
; i
++) {
783 pci_unmap_single(dev
, le32_to_cpu(tfd
->tbs
[i
].addr
),
784 le32_to_cpu(tfd
->tbs
[i
].len
), PCI_DMA_TODEVICE
);
785 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
786 struct sk_buff
*skb
= txq
->txb
[txq
->q
.read_ptr
].skb
[0];
787 if (txq
->txb
[txq
->q
.read_ptr
].skb
[0]) {
788 /* Can be called from interrupt context */
789 dev_kfree_skb_any(skb
);
790 txq
->txb
[txq
->q
.read_ptr
].skb
[0] = NULL
;
798 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
801 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv
*priv
,
802 struct iwl_device_cmd
*cmd
,
803 struct ieee80211_tx_info
*info
,
804 struct ieee80211_hdr
*hdr
,
805 int sta_id
, int tx_id
)
807 u16 hw_value
= ieee80211_get_tx_rate(priv
->hw
, info
)->hw_value
;
808 u16 rate_index
= min(hw_value
& 0xffff, IWL_RATE_COUNT
- 1);
814 __le16 fc
= hdr
->frame_control
;
815 struct iwl3945_tx_cmd
*tx_cmd
= (struct iwl3945_tx_cmd
*)cmd
->cmd
.payload
;
817 rate
= iwl3945_rates
[rate_index
].plcp
;
818 tx_flags
= tx_cmd
->tx_flags
;
820 /* We need to figure out how to get the sta->supp_rates while
821 * in this running context */
822 rate_mask
= IWL_RATES_MASK
;
825 /* Set retry limit on DATA packets and Probe Responses*/
826 if (ieee80211_is_probe_resp(fc
))
827 data_retry_limit
= 3;
829 data_retry_limit
= IWL_DEFAULT_TX_RETRY
;
830 tx_cmd
->data_retry_limit
= data_retry_limit
;
832 if (tx_id
>= IWL_CMD_QUEUE_NUM
)
837 if (data_retry_limit
< rts_retry_limit
)
838 rts_retry_limit
= data_retry_limit
;
839 tx_cmd
->rts_retry_limit
= rts_retry_limit
;
841 if (ieee80211_is_mgmt(fc
)) {
842 switch (fc
& cpu_to_le16(IEEE80211_FCTL_STYPE
)) {
843 case cpu_to_le16(IEEE80211_STYPE_AUTH
):
844 case cpu_to_le16(IEEE80211_STYPE_DEAUTH
):
845 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ
):
846 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ
):
847 if (tx_flags
& TX_CMD_FLG_RTS_MSK
) {
848 tx_flags
&= ~TX_CMD_FLG_RTS_MSK
;
849 tx_flags
|= TX_CMD_FLG_CTS_MSK
;
858 tx_cmd
->tx_flags
= tx_flags
;
861 tx_cmd
->supp_rates
[0] =
862 ((rate_mask
& IWL_OFDM_RATES_MASK
) >> IWL_FIRST_OFDM_RATE
) & 0xFF;
865 tx_cmd
->supp_rates
[1] = (rate_mask
& 0xF);
867 IWL_DEBUG_RATE(priv
, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
868 "cck/ofdm mask: 0x%x/0x%x\n", sta_id
,
869 tx_cmd
->rate
, le32_to_cpu(tx_cmd
->tx_flags
),
870 tx_cmd
->supp_rates
[1], tx_cmd
->supp_rates
[0]);
873 u8
iwl3945_sync_sta(struct iwl_priv
*priv
, int sta_id
, u16 tx_rate
, u8 flags
)
875 unsigned long flags_spin
;
876 struct iwl_station_entry
*station
;
878 if (sta_id
== IWL_INVALID_STATION
)
879 return IWL_INVALID_STATION
;
881 spin_lock_irqsave(&priv
->sta_lock
, flags_spin
);
882 station
= &priv
->stations
[sta_id
];
884 station
->sta
.sta
.modify_mask
= STA_MODIFY_TX_RATE_MSK
;
885 station
->sta
.rate_n_flags
= cpu_to_le16(tx_rate
);
886 station
->sta
.mode
= STA_CONTROL_MODIFY_MSK
;
888 spin_unlock_irqrestore(&priv
->sta_lock
, flags_spin
);
890 iwl_send_add_sta(priv
, &station
->sta
, flags
);
891 IWL_DEBUG_RATE(priv
, "SCALE sync station %d to rate %d\n",
896 static int iwl3945_set_pwr_src(struct iwl_priv
*priv
, enum iwl_pwr_src src
)
898 if (src
== IWL_PWR_SRC_VAUX
) {
899 if (pci_pme_capable(priv
->pci_dev
, PCI_D3cold
)) {
900 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
901 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
902 ~APMG_PS_CTRL_MSK_PWR_SRC
);
904 iwl_poll_bit(priv
, CSR_GPIO_IN
,
905 CSR_GPIO_IN_VAL_VAUX_PWR_SRC
,
906 CSR_GPIO_IN_BIT_AUX_POWER
, 5000);
909 iwl_set_bits_mask_prph(priv
, APMG_PS_CTRL_REG
,
910 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
911 ~APMG_PS_CTRL_MSK_PWR_SRC
);
913 iwl_poll_bit(priv
, CSR_GPIO_IN
, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC
,
914 CSR_GPIO_IN_BIT_AUX_POWER
, 5000); /* uS */
920 static int iwl3945_rx_init(struct iwl_priv
*priv
, struct iwl_rx_queue
*rxq
)
922 iwl_write_direct32(priv
, FH39_RCSR_RBD_BASE(0), rxq
->dma_addr
);
923 iwl_write_direct32(priv
, FH39_RCSR_RPTR_ADDR(0), rxq
->rb_stts_dma
);
924 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), 0);
925 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0),
926 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE
|
927 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE
|
928 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN
|
929 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128
|
930 (RX_QUEUE_SIZE_LOG
<< FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE
) |
931 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST
|
932 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH
) |
933 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH
);
935 /* fake read to flush all prev I/O */
936 iwl_read_direct32(priv
, FH39_RSSR_CTRL
);
941 static int iwl3945_tx_reset(struct iwl_priv
*priv
)
945 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0x2);
948 iwl_write_prph(priv
, ALM_SCD_ARASTAT_REG
, 0x01);
950 /* all 6 fifo are active */
951 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0x3f);
953 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_1_REG
, 0x010000);
954 iwl_write_prph(priv
, ALM_SCD_SBYP_MODE_2_REG
, 0x030002);
955 iwl_write_prph(priv
, ALM_SCD_TXF4MF_REG
, 0x000004);
956 iwl_write_prph(priv
, ALM_SCD_TXF5MF_REG
, 0x000005);
958 iwl_write_direct32(priv
, FH39_TSSR_CBB_BASE
,
961 iwl_write_direct32(priv
, FH39_TSSR_MSG_CONFIG
,
962 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON
|
963 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON
|
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B
|
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON
|
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON
|
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH
|
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH
);
975 * iwl3945_txq_ctx_reset - Reset TX queue context
977 * Destroys all DMA structures and initialize them again
979 static int iwl3945_txq_ctx_reset(struct iwl_priv
*priv
)
982 int txq_id
, slots_num
;
984 iwl3945_hw_txq_ctx_free(priv
);
986 /* allocate tx queue structure */
987 rc
= iwl_alloc_txq_mem(priv
);
992 rc
= iwl3945_tx_reset(priv
);
997 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
998 slots_num
= (txq_id
== IWL_CMD_QUEUE_NUM
) ?
999 TFD_CMD_SLOTS
: TFD_TX_CMD_SLOTS
;
1000 rc
= iwl_tx_queue_init(priv
, &priv
->txq
[txq_id
], slots_num
,
1003 IWL_ERR(priv
, "Tx %d queue init failed\n", txq_id
);
1011 iwl3945_hw_txq_ctx_free(priv
);
1017 * Start up 3945's basic functionality after it has been reset
1018 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1019 * NOTE: This does not load uCode nor start the embedded processor
1021 static int iwl3945_apm_init(struct iwl_priv
*priv
)
1023 int ret
= iwl_apm_init(priv
);
1025 /* Clear APMG (NIC's internal power management) interrupts */
1026 iwl_write_prph(priv
, APMG_RTC_INT_MSK_REG
, 0x0);
1027 iwl_write_prph(priv
, APMG_RTC_INT_STT_REG
, 0xFFFFFFFF);
1029 /* Reset radio chip */
1030 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
1032 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
, APMG_PS_CTRL_VAL_RESET_REQ
);
1037 static void iwl3945_nic_config(struct iwl_priv
*priv
)
1039 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1040 unsigned long flags
;
1043 spin_lock_irqsave(&priv
->lock
, flags
);
1045 /* Determine HW type */
1046 pci_read_config_byte(priv
->pci_dev
, PCI_REVISION_ID
, &rev_id
);
1048 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", rev_id
);
1050 if (rev_id
& PCI_CFG_REV_ID_BIT_RTP
)
1051 IWL_DEBUG_INFO(priv
, "RTP type \n");
1052 else if (rev_id
& PCI_CFG_REV_ID_BIT_BASIC_SKU
) {
1053 IWL_DEBUG_INFO(priv
, "3945 RADIO-MB type\n");
1054 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1055 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB
);
1057 IWL_DEBUG_INFO(priv
, "3945 RADIO-MM type\n");
1058 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1059 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM
);
1062 if (EEPROM_SKU_CAP_OP_MODE_MRC
== eeprom
->sku_cap
) {
1063 IWL_DEBUG_INFO(priv
, "SKU OP mode is mrc\n");
1064 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1065 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC
);
1067 IWL_DEBUG_INFO(priv
, "SKU OP mode is basic\n");
1069 if ((eeprom
->board_revision
& 0xF0) == 0xD0) {
1070 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1071 eeprom
->board_revision
);
1072 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1073 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1075 IWL_DEBUG_INFO(priv
, "3945ABG revision is 0x%X\n",
1076 eeprom
->board_revision
);
1077 iwl_clear_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1078 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE
);
1081 if (eeprom
->almgor_m_version
<= 1) {
1082 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1083 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A
);
1084 IWL_DEBUG_INFO(priv
, "Card M type A version is 0x%X\n",
1085 eeprom
->almgor_m_version
);
1087 IWL_DEBUG_INFO(priv
, "Card M type B version is 0x%X\n",
1088 eeprom
->almgor_m_version
);
1089 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
1090 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B
);
1092 spin_unlock_irqrestore(&priv
->lock
, flags
);
1094 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_SW_RF_KILL_ENABLE
)
1095 IWL_DEBUG_RF_KILL(priv
, "SW RF KILL supported in EEPROM.\n");
1097 if (eeprom
->sku_cap
& EEPROM_SKU_CAP_HW_RF_KILL_ENABLE
)
1098 IWL_DEBUG_RF_KILL(priv
, "HW RF KILL supported in EEPROM.\n");
1101 int iwl3945_hw_nic_init(struct iwl_priv
*priv
)
1104 unsigned long flags
;
1105 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
1107 spin_lock_irqsave(&priv
->lock
, flags
);
1108 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
1109 spin_unlock_irqrestore(&priv
->lock
, flags
);
1111 rc
= priv
->cfg
->ops
->lib
->apm_ops
.set_pwr_src(priv
, IWL_PWR_SRC_VMAIN
);
1115 priv
->cfg
->ops
->lib
->apm_ops
.config(priv
);
1117 /* Allocate the RX queue, or reset if it is already allocated */
1119 rc
= iwl_rx_queue_alloc(priv
);
1121 IWL_ERR(priv
, "Unable to initialize Rx queue\n");
1125 iwl3945_rx_queue_reset(priv
, rxq
);
1127 iwl3945_rx_replenish(priv
);
1129 iwl3945_rx_init(priv
, rxq
);
1132 /* Look at using this instead:
1133 rxq->need_update = 1;
1134 iwl_rx_queue_update_write_ptr(priv, rxq);
1137 iwl_write_direct32(priv
, FH39_RCSR_WPTR(0), rxq
->write
& ~7);
1139 rc
= iwl3945_txq_ctx_reset(priv
);
1143 set_bit(STATUS_INIT
, &priv
->status
);
1149 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1151 * Destroy all TX DMA queues and structures
1153 void iwl3945_hw_txq_ctx_free(struct iwl_priv
*priv
)
1159 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
;
1161 if (txq_id
== IWL_CMD_QUEUE_NUM
)
1162 iwl_cmd_queue_free(priv
);
1164 iwl_tx_queue_free(priv
, txq_id
);
1166 /* free tx queue structure */
1167 iwl_free_txq_mem(priv
);
1170 void iwl3945_hw_txq_ctx_stop(struct iwl_priv
*priv
)
1175 iwl_write_prph(priv
, ALM_SCD_MODE_REG
, 0);
1176 iwl_write_prph(priv
, ALM_SCD_TXFACT_REG
, 0);
1178 /* reset TFD queues */
1179 for (txq_id
= 0; txq_id
< priv
->hw_params
.max_txq_num
; txq_id
++) {
1180 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
), 0x0);
1181 iwl_poll_direct_bit(priv
, FH39_TSSR_TX_STATUS
,
1182 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id
),
1186 iwl3945_hw_txq_ctx_free(priv
);
1190 * iwl3945_hw_reg_adjust_power_by_temp
1191 * return index delta into power gain settings table
1193 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading
, int old_reading
)
1195 return (new_reading
- old_reading
) * (-11) / 100;
1199 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1201 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature
)
1203 return ((temperature
< -260) || (temperature
> 25)) ? 1 : 0;
1206 int iwl3945_hw_get_temperature(struct iwl_priv
*priv
)
1208 return iwl_read32(priv
, CSR_UCODE_DRV_GP2
);
1212 * iwl3945_hw_reg_txpower_get_temperature
1213 * get the current temperature by reading from NIC
1215 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv
*priv
)
1217 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1220 temperature
= iwl3945_hw_get_temperature(priv
);
1222 /* driver's okay range is -260 to +25.
1223 * human readable okay range is 0 to +285 */
1224 IWL_DEBUG_INFO(priv
, "Temperature: %d\n", temperature
+ IWL_TEMP_CONVERT
);
1226 /* handle insane temp reading */
1227 if (iwl3945_hw_reg_temp_out_of_range(temperature
)) {
1228 IWL_ERR(priv
, "Error bad temperature value %d\n", temperature
);
1230 /* if really really hot(?),
1231 * substitute the 3rd band/group's temp measured at factory */
1232 if (priv
->last_temperature
> 100)
1233 temperature
= eeprom
->groups
[2].temperature
;
1234 else /* else use most recent "sane" value from driver */
1235 temperature
= priv
->last_temperature
;
1238 return temperature
; /* raw, not "human readable" */
1241 /* Adjust Txpower only if temperature variance is greater than threshold.
1243 * Both are lower than older versions' 9 degrees */
1244 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1247 * is_temp_calib_needed - determines if new calibration is needed
1249 * records new temperature in tx_mgr->temperature.
1250 * replaces tx_mgr->last_temperature *only* if calib needed
1251 * (assumes caller will actually do the calibration!). */
1252 static int is_temp_calib_needed(struct iwl_priv
*priv
)
1256 priv
->temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
1257 temp_diff
= priv
->temperature
- priv
->last_temperature
;
1259 /* get absolute value */
1260 if (temp_diff
< 0) {
1261 IWL_DEBUG_POWER(priv
, "Getting cooler, delta %d,\n", temp_diff
);
1262 temp_diff
= -temp_diff
;
1263 } else if (temp_diff
== 0)
1264 IWL_DEBUG_POWER(priv
, "Same temp,\n");
1266 IWL_DEBUG_POWER(priv
, "Getting warmer, delta %d,\n", temp_diff
);
1268 /* if we don't need calibration, *don't* update last_temperature */
1269 if (temp_diff
< IWL_TEMPERATURE_LIMIT_TIMER
) {
1270 IWL_DEBUG_POWER(priv
, "Timed thermal calib not needed\n");
1274 IWL_DEBUG_POWER(priv
, "Timed thermal calib needed\n");
1276 /* assume that caller will actually do calib ...
1277 * update the "last temperature" value */
1278 priv
->last_temperature
= priv
->temperature
;
1282 #define IWL_MAX_GAIN_ENTRIES 78
1283 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1284 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1286 /* radio and DSP power table, each step is 1/2 dB.
1287 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1288 static struct iwl3945_tx_power power_gain_table
[2][IWL_MAX_GAIN_ENTRIES
] = {
1290 {251, 127}, /* 2.4 GHz, highest power */
1367 {3, 95} }, /* 2.4 GHz, lowest power */
1369 {251, 127}, /* 5.x GHz, highest power */
1446 {3, 120} } /* 5.x GHz, lowest power */
1449 static inline u8
iwl3945_hw_reg_fix_power_index(int index
)
1453 if (index
>= IWL_MAX_GAIN_ENTRIES
)
1454 return IWL_MAX_GAIN_ENTRIES
- 1;
1458 /* Kick off thermal recalibration check every 60 seconds */
1459 #define REG_RECALIB_PERIOD (60)
1462 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1464 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1465 * or 6 Mbit (OFDM) rates.
1467 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv
*priv
, u32 scan_tbl_index
,
1468 s32 rate_index
, const s8
*clip_pwrs
,
1469 struct iwl_channel_info
*ch_info
,
1472 struct iwl3945_scan_power_info
*scan_power_info
;
1476 scan_power_info
= &ch_info
->scan_pwr_info
[scan_tbl_index
];
1478 /* use this channel group's 6Mbit clipping/saturation pwr,
1479 * but cap at regulatory scan power restriction (set during init
1480 * based on eeprom channel data) for this channel. */
1481 power
= min(ch_info
->scan_power
, clip_pwrs
[IWL_RATE_6M_INDEX_TABLE
]);
1483 /* further limit to user's max power preference.
1484 * FIXME: Other spectrum management power limitations do not
1485 * seem to apply?? */
1486 power
= min(power
, priv
->tx_power_user_lmt
);
1487 scan_power_info
->requested_power
= power
;
1489 /* find difference between new scan *power* and current "normal"
1490 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1491 * current "normal" temperature-compensated Tx power *index* for
1492 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1494 power_index
= ch_info
->power_info
[rate_index
].power_table_index
1495 - (power
- ch_info
->power_info
1496 [IWL_RATE_6M_INDEX_TABLE
].requested_power
) * 2;
1498 /* store reference index that we use when adjusting *all* scan
1499 * powers. So we can accommodate user (all channel) or spectrum
1500 * management (single channel) power changes "between" temperature
1501 * feedback compensation procedures.
1502 * don't force fit this reference index into gain table; it may be a
1503 * negative number. This will help avoid errors when we're at
1504 * the lower bounds (highest gains, for warmest temperatures)
1507 /* don't exceed table bounds for "real" setting */
1508 power_index
= iwl3945_hw_reg_fix_power_index(power_index
);
1510 scan_power_info
->power_table_index
= power_index
;
1511 scan_power_info
->tpc
.tx_gain
=
1512 power_gain_table
[band_index
][power_index
].tx_gain
;
1513 scan_power_info
->tpc
.dsp_atten
=
1514 power_gain_table
[band_index
][power_index
].dsp_atten
;
1518 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1520 * Configures power settings for all rates for the current channel,
1521 * using values from channel info struct, and send to NIC
1523 static int iwl3945_send_tx_power(struct iwl_priv
*priv
)
1526 const struct iwl_channel_info
*ch_info
= NULL
;
1527 struct iwl3945_txpowertable_cmd txpower
= {
1528 .channel
= priv
->active_rxon
.channel
,
1531 txpower
.band
= (priv
->band
== IEEE80211_BAND_5GHZ
) ? 0 : 1;
1532 ch_info
= iwl_get_channel_info(priv
,
1534 le16_to_cpu(priv
->active_rxon
.channel
));
1537 "Failed to get channel info for channel %d [%d]\n",
1538 le16_to_cpu(priv
->active_rxon
.channel
), priv
->band
);
1542 if (!is_channel_valid(ch_info
)) {
1543 IWL_DEBUG_POWER(priv
, "Not calling TX_PWR_TABLE_CMD on "
1544 "non-Tx channel.\n");
1548 /* fill cmd with power settings for all rates for current channel */
1549 /* Fill OFDM rate */
1550 for (rate_idx
= IWL_FIRST_OFDM_RATE
, i
= 0;
1551 rate_idx
<= IWL39_LAST_OFDM_RATE
; rate_idx
++, i
++) {
1553 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1554 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1556 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1557 le16_to_cpu(txpower
.channel
),
1559 txpower
.power
[i
].tpc
.tx_gain
,
1560 txpower
.power
[i
].tpc
.dsp_atten
,
1561 txpower
.power
[i
].rate
);
1563 /* Fill CCK rates */
1564 for (rate_idx
= IWL_FIRST_CCK_RATE
;
1565 rate_idx
<= IWL_LAST_CCK_RATE
; rate_idx
++, i
++) {
1566 txpower
.power
[i
].tpc
= ch_info
->power_info
[i
].tpc
;
1567 txpower
.power
[i
].rate
= iwl3945_rates
[rate_idx
].plcp
;
1569 IWL_DEBUG_POWER(priv
, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1570 le16_to_cpu(txpower
.channel
),
1572 txpower
.power
[i
].tpc
.tx_gain
,
1573 txpower
.power
[i
].tpc
.dsp_atten
,
1574 txpower
.power
[i
].rate
);
1577 return iwl_send_cmd_pdu(priv
, REPLY_TX_PWR_TABLE_CMD
,
1578 sizeof(struct iwl3945_txpowertable_cmd
),
1584 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1585 * @ch_info: Channel to update. Uses power_info.requested_power.
1587 * Replace requested_power and base_power_index ch_info fields for
1590 * Called if user or spectrum management changes power preferences.
1591 * Takes into account h/w and modulation limitations (clip power).
1593 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1595 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1596 * properly fill out the scan powers, and actual h/w gain settings,
1597 * and send changes to NIC
1599 static int iwl3945_hw_reg_set_new_power(struct iwl_priv
*priv
,
1600 struct iwl_channel_info
*ch_info
)
1602 struct iwl3945_channel_power_info
*power_info
;
1603 int power_changed
= 0;
1605 const s8
*clip_pwrs
;
1608 /* Get this chnlgrp's rate-to-max/clip-powers table */
1609 clip_pwrs
= priv
->clip39_groups
[ch_info
->group_index
].clip_powers
;
1611 /* Get this channel's rate-to-current-power settings table */
1612 power_info
= ch_info
->power_info
;
1614 /* update OFDM Txpower settings */
1615 for (i
= IWL_RATE_6M_INDEX_TABLE
; i
<= IWL_RATE_54M_INDEX_TABLE
;
1616 i
++, ++power_info
) {
1619 /* limit new power to be no more than h/w capability */
1620 power
= min(ch_info
->curr_txpow
, clip_pwrs
[i
]);
1621 if (power
== power_info
->requested_power
)
1624 /* find difference between old and new requested powers,
1625 * update base (non-temp-compensated) power index */
1626 delta_idx
= (power
- power_info
->requested_power
) * 2;
1627 power_info
->base_power_index
-= delta_idx
;
1629 /* save new requested power value */
1630 power_info
->requested_power
= power
;
1635 /* update CCK Txpower settings, based on OFDM 12M setting ...
1636 * ... all CCK power settings for a given channel are the *same*. */
1637 if (power_changed
) {
1639 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1640 requested_power
+ IWL_CCK_FROM_OFDM_POWER_DIFF
;
1642 /* do all CCK rates' iwl3945_channel_power_info structures */
1643 for (i
= IWL_RATE_1M_INDEX_TABLE
; i
<= IWL_RATE_11M_INDEX_TABLE
; i
++) {
1644 power_info
->requested_power
= power
;
1645 power_info
->base_power_index
=
1646 ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
].
1647 base_power_index
+ IWL_CCK_FROM_OFDM_INDEX_DIFF
;
1656 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1658 * NOTE: Returned power limit may be less (but not more) than requested,
1659 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1660 * (no consideration for h/w clipping limitations).
1662 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info
*ch_info
)
1667 /* if we're using TGd limits, use lower of TGd or EEPROM */
1668 if (ch_info
->tgd_data
.max_power
!= 0)
1669 max_power
= min(ch_info
->tgd_data
.max_power
,
1670 ch_info
->eeprom
.max_power_avg
);
1672 /* else just use EEPROM limits */
1675 max_power
= ch_info
->eeprom
.max_power_avg
;
1677 return min(max_power
, ch_info
->max_power_avg
);
1681 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1683 * Compensate txpower settings of *all* channels for temperature.
1684 * This only accounts for the difference between current temperature
1685 * and the factory calibration temperatures, and bases the new settings
1686 * on the channel's base_power_index.
1688 * If RxOn is "associated", this sends the new Txpower to NIC!
1690 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv
*priv
)
1692 struct iwl_channel_info
*ch_info
= NULL
;
1693 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
1695 const s8
*clip_pwrs
; /* array of h/w max power levels for each rate */
1701 int temperature
= priv
->temperature
;
1703 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1704 for (i
= 0; i
< priv
->channel_count
; i
++) {
1705 ch_info
= &priv
->channel_info
[i
];
1706 a_band
= is_channel_a_band(ch_info
);
1708 /* Get this chnlgrp's factory calibration temperature */
1709 ref_temp
= (s16
)eeprom
->groups
[ch_info
->group_index
].
1712 /* get power index adjustment based on current and factory
1714 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
1717 /* set tx power value for all rates, OFDM and CCK */
1718 for (rate_index
= 0; rate_index
< IWL_RATE_COUNT
;
1721 ch_info
->power_info
[rate_index
].base_power_index
;
1723 /* temperature compensate */
1724 power_idx
+= delta_index
;
1726 /* stay within table range */
1727 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
1728 ch_info
->power_info
[rate_index
].
1729 power_table_index
= (u8
) power_idx
;
1730 ch_info
->power_info
[rate_index
].tpc
=
1731 power_gain_table
[a_band
][power_idx
];
1734 /* Get this chnlgrp's rate-to-max/clip-powers table */
1735 clip_pwrs
= priv
->clip39_groups
[ch_info
->group_index
].clip_powers
;
1737 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1738 for (scan_tbl_index
= 0;
1739 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
1740 s32 actual_index
= (scan_tbl_index
== 0) ?
1741 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
1742 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
1743 actual_index
, clip_pwrs
,
1748 /* send Txpower command for current channel to ucode */
1749 return priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1752 int iwl3945_hw_reg_set_txpower(struct iwl_priv
*priv
, s8 power
)
1754 struct iwl_channel_info
*ch_info
;
1759 if (priv
->tx_power_user_lmt
== power
) {
1760 IWL_DEBUG_POWER(priv
, "Requested Tx power same as current "
1761 "limit: %ddBm.\n", power
);
1765 IWL_DEBUG_POWER(priv
, "Setting upper limit clamp to %ddBm.\n", power
);
1766 priv
->tx_power_user_lmt
= power
;
1768 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1770 for (i
= 0; i
< priv
->channel_count
; i
++) {
1771 ch_info
= &priv
->channel_info
[i
];
1772 a_band
= is_channel_a_band(ch_info
);
1774 /* find minimum power of all user and regulatory constraints
1775 * (does not consider h/w clipping limitations) */
1776 max_power
= iwl3945_hw_reg_get_ch_txpower_limit(ch_info
);
1777 max_power
= min(power
, max_power
);
1778 if (max_power
!= ch_info
->curr_txpow
) {
1779 ch_info
->curr_txpow
= max_power
;
1781 /* this considers the h/w clipping limitations */
1782 iwl3945_hw_reg_set_new_power(priv
, ch_info
);
1786 /* update txpower settings for all channels,
1787 * send to NIC if associated. */
1788 is_temp_calib_needed(priv
);
1789 iwl3945_hw_reg_comp_txpower_temp(priv
);
1794 static int iwl3945_send_rxon_assoc(struct iwl_priv
*priv
)
1797 struct iwl_rx_packet
*pkt
;
1798 struct iwl3945_rxon_assoc_cmd rxon_assoc
;
1799 struct iwl_host_cmd cmd
= {
1800 .id
= REPLY_RXON_ASSOC
,
1801 .len
= sizeof(rxon_assoc
),
1802 .flags
= CMD_WANT_SKB
,
1803 .data
= &rxon_assoc
,
1805 const struct iwl_rxon_cmd
*rxon1
= &priv
->staging_rxon
;
1806 const struct iwl_rxon_cmd
*rxon2
= &priv
->active_rxon
;
1808 if ((rxon1
->flags
== rxon2
->flags
) &&
1809 (rxon1
->filter_flags
== rxon2
->filter_flags
) &&
1810 (rxon1
->cck_basic_rates
== rxon2
->cck_basic_rates
) &&
1811 (rxon1
->ofdm_basic_rates
== rxon2
->ofdm_basic_rates
)) {
1812 IWL_DEBUG_INFO(priv
, "Using current RXON_ASSOC. Not resending.\n");
1816 rxon_assoc
.flags
= priv
->staging_rxon
.flags
;
1817 rxon_assoc
.filter_flags
= priv
->staging_rxon
.filter_flags
;
1818 rxon_assoc
.ofdm_basic_rates
= priv
->staging_rxon
.ofdm_basic_rates
;
1819 rxon_assoc
.cck_basic_rates
= priv
->staging_rxon
.cck_basic_rates
;
1820 rxon_assoc
.reserved
= 0;
1822 rc
= iwl_send_cmd_sync(priv
, &cmd
);
1826 pkt
= (struct iwl_rx_packet
*)cmd
.reply_page
;
1827 if (pkt
->hdr
.flags
& IWL_CMD_FAILED_MSK
) {
1828 IWL_ERR(priv
, "Bad return from REPLY_RXON_ASSOC command\n");
1832 iwl_free_pages(priv
, cmd
.reply_page
);
1838 * iwl3945_commit_rxon - commit staging_rxon to hardware
1840 * The RXON command in staging_rxon is committed to the hardware and
1841 * the active_rxon structure is updated with the new data. This
1842 * function correctly transitions out of the RXON_ASSOC_MSK state if
1843 * a HW tune is required based on the RXON structure changes.
1845 static int iwl3945_commit_rxon(struct iwl_priv
*priv
)
1847 /* cast away the const for active_rxon in this function */
1848 struct iwl3945_rxon_cmd
*active_rxon
= (void *)&priv
->active_rxon
;
1849 struct iwl3945_rxon_cmd
*staging_rxon
= (void *)&priv
->staging_rxon
;
1852 !!(priv
->staging_rxon
.filter_flags
& RXON_FILTER_ASSOC_MSK
);
1854 if (!iwl_is_alive(priv
))
1857 /* always get timestamp with Rx frame */
1858 staging_rxon
->flags
|= RXON_FLG_TSF2HOST_MSK
;
1860 /* select antenna */
1861 staging_rxon
->flags
&=
1862 ~(RXON_FLG_DIS_DIV_MSK
| RXON_FLG_ANT_SEL_MSK
);
1863 staging_rxon
->flags
|= iwl3945_get_antenna_flags(priv
);
1865 rc
= iwl_check_rxon_cmd(priv
);
1867 IWL_ERR(priv
, "Invalid RXON configuration. Not committing.\n");
1871 /* If we don't need to send a full RXON, we can use
1872 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1873 * and other flags for the current radio configuration. */
1874 if (!iwl_full_rxon_required(priv
)) {
1875 rc
= iwl_send_rxon_assoc(priv
);
1877 IWL_ERR(priv
, "Error setting RXON_ASSOC "
1878 "configuration (%d).\n", rc
);
1882 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1887 /* If we are currently associated and the new config requires
1888 * an RXON_ASSOC and the new config wants the associated mask enabled,
1889 * we must clear the associated from the active configuration
1890 * before we apply the new config */
1891 if (iwl_is_associated(priv
) && new_assoc
) {
1892 IWL_DEBUG_INFO(priv
, "Toggling associated bit on current RXON\n");
1893 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
1896 * reserved4 and 5 could have been filled by the iwlcore code.
1897 * Let's clear them before pushing to the 3945.
1899 active_rxon
->reserved4
= 0;
1900 active_rxon
->reserved5
= 0;
1901 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1902 sizeof(struct iwl3945_rxon_cmd
),
1903 &priv
->active_rxon
);
1905 /* If the mask clearing failed then we set
1906 * active_rxon back to what it was previously */
1908 active_rxon
->filter_flags
|= RXON_FILTER_ASSOC_MSK
;
1909 IWL_ERR(priv
, "Error clearing ASSOC_MSK on current "
1910 "configuration (%d).\n", rc
);
1915 IWL_DEBUG_INFO(priv
, "Sending RXON\n"
1916 "* with%s RXON_FILTER_ASSOC_MSK\n"
1919 (new_assoc
? "" : "out"),
1920 le16_to_cpu(staging_rxon
->channel
),
1921 staging_rxon
->bssid_addr
);
1924 * reserved4 and 5 could have been filled by the iwlcore code.
1925 * Let's clear them before pushing to the 3945.
1927 staging_rxon
->reserved4
= 0;
1928 staging_rxon
->reserved5
= 0;
1930 iwl_set_rxon_hwcrypto(priv
, !iwl3945_mod_params
.sw_crypto
);
1932 /* Apply the new configuration */
1933 rc
= iwl_send_cmd_pdu(priv
, REPLY_RXON
,
1934 sizeof(struct iwl3945_rxon_cmd
),
1937 IWL_ERR(priv
, "Error setting new configuration (%d).\n", rc
);
1941 memcpy(active_rxon
, staging_rxon
, sizeof(*active_rxon
));
1943 iwl_clear_stations_table(priv
);
1945 /* If we issue a new RXON command which required a tune then we must
1946 * send a new TXPOWER command or we won't be able to Tx any frames */
1947 rc
= priv
->cfg
->ops
->lib
->send_tx_power(priv
);
1949 IWL_ERR(priv
, "Error setting Tx power (%d).\n", rc
);
1953 /* Add the broadcast address so we can send broadcast frames */
1954 priv
->cfg
->ops
->lib
->add_bcast_station(priv
);
1956 /* If we have set the ASSOC_MSK and we are in BSS mode then
1957 * add the IWL_AP_ID to the station rate table */
1958 if (iwl_is_associated(priv
) &&
1959 (priv
->iw_mode
== NL80211_IFTYPE_STATION
))
1960 if (iwl_add_station(priv
, priv
->active_rxon
.bssid_addr
,
1961 true, CMD_SYNC
, NULL
) == IWL_INVALID_STATION
) {
1962 IWL_ERR(priv
, "Error adding AP address for transmit\n");
1966 /* Init the hardware's rate fallback order based on the band */
1967 rc
= iwl3945_init_hw_rate_table(priv
);
1969 IWL_ERR(priv
, "Error setting HW rate table: %02X\n", rc
);
1977 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1979 * -- reset periodic timer
1980 * -- see if temp has changed enough to warrant re-calibration ... if so:
1981 * -- correct coeffs for temp (can reset temp timer)
1982 * -- save this temp as "last",
1983 * -- send new set of gain settings to NIC
1984 * NOTE: This should continue working, even when we're not associated,
1985 * so we can keep our internal table of scan powers current. */
1986 void iwl3945_reg_txpower_periodic(struct iwl_priv
*priv
)
1988 /* This will kick in the "brute force"
1989 * iwl3945_hw_reg_comp_txpower_temp() below */
1990 if (!is_temp_calib_needed(priv
))
1993 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1994 * This is based *only* on current temperature,
1995 * ignoring any previous power measurements */
1996 iwl3945_hw_reg_comp_txpower_temp(priv
);
1999 queue_delayed_work(priv
->workqueue
,
2000 &priv
->thermal_periodic
, REG_RECALIB_PERIOD
* HZ
);
2003 static void iwl3945_bg_reg_txpower_periodic(struct work_struct
*work
)
2005 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
2006 thermal_periodic
.work
);
2008 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2011 mutex_lock(&priv
->mutex
);
2012 iwl3945_reg_txpower_periodic(priv
);
2013 mutex_unlock(&priv
->mutex
);
2017 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2020 * This function is used when initializing channel-info structs.
2022 * NOTE: These channel groups do *NOT* match the bands above!
2023 * These channel groups are based on factory-tested channels;
2024 * on A-band, EEPROM's "group frequency" entries represent the top
2025 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2027 static u16
iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv
*priv
,
2028 const struct iwl_channel_info
*ch_info
)
2030 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2031 struct iwl3945_eeprom_txpower_group
*ch_grp
= &eeprom
->groups
[0];
2033 u16 group_index
= 0; /* based on factory calib frequencies */
2036 /* Find the group index for the channel ... don't use index 1(?) */
2037 if (is_channel_a_band(ch_info
)) {
2038 for (group
= 1; group
< 5; group
++) {
2039 grp_channel
= ch_grp
[group
].group_channel
;
2040 if (ch_info
->channel
<= grp_channel
) {
2041 group_index
= group
;
2045 /* group 4 has a few channels *above* its factory cal freq */
2049 group_index
= 0; /* 2.4 GHz, group 0 */
2051 IWL_DEBUG_POWER(priv
, "Chnl %d mapped to grp %d\n", ch_info
->channel
,
2057 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2059 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2060 * into radio/DSP gain settings table for requested power.
2062 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv
*priv
,
2064 s32 setting_index
, s32
*new_index
)
2066 const struct iwl3945_eeprom_txpower_group
*chnl_grp
= NULL
;
2067 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2069 s32 power
= 2 * requested_power
;
2071 const struct iwl3945_eeprom_txpower_sample
*samples
;
2076 chnl_grp
= &eeprom
->groups
[setting_index
];
2077 samples
= chnl_grp
->samples
;
2078 for (i
= 0; i
< 5; i
++) {
2079 if (power
== samples
[i
].power
) {
2080 *new_index
= samples
[i
].gain_index
;
2085 if (power
> samples
[1].power
) {
2088 } else if (power
> samples
[2].power
) {
2091 } else if (power
> samples
[3].power
) {
2099 denominator
= (s32
) samples
[index1
].power
- (s32
) samples
[index0
].power
;
2100 if (denominator
== 0)
2102 gains0
= (s32
) samples
[index0
].gain_index
* (1 << 19);
2103 gains1
= (s32
) samples
[index1
].gain_index
* (1 << 19);
2104 res
= gains0
+ (gains1
- gains0
) *
2105 ((s32
) power
- (s32
) samples
[index0
].power
) / denominator
+
2107 *new_index
= res
>> 19;
2111 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv
*priv
)
2115 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2116 const struct iwl3945_eeprom_txpower_group
*group
;
2118 IWL_DEBUG_POWER(priv
, "Initializing factory calib info from EEPROM\n");
2120 for (i
= 0; i
< IWL_NUM_TX_CALIB_GROUPS
; i
++) {
2121 s8
*clip_pwrs
; /* table of power levels for each rate */
2122 s8 satur_pwr
; /* saturation power for each chnl group */
2123 group
= &eeprom
->groups
[i
];
2125 /* sanity check on factory saturation power value */
2126 if (group
->saturation_power
< 40) {
2127 IWL_WARN(priv
, "Error: saturation power is %d, "
2128 "less than minimum expected 40\n",
2129 group
->saturation_power
);
2134 * Derive requested power levels for each rate, based on
2135 * hardware capabilities (saturation power for band).
2136 * Basic value is 3dB down from saturation, with further
2137 * power reductions for highest 3 data rates. These
2138 * backoffs provide headroom for high rate modulation
2139 * power peaks, without too much distortion (clipping).
2141 /* we'll fill in this array with h/w max power levels */
2142 clip_pwrs
= (s8
*) priv
->clip39_groups
[i
].clip_powers
;
2144 /* divide factory saturation power by 2 to find -3dB level */
2145 satur_pwr
= (s8
) (group
->saturation_power
>> 1);
2147 /* fill in channel group's nominal powers for each rate */
2148 for (rate_index
= 0;
2149 rate_index
< IWL_RATE_COUNT
; rate_index
++, clip_pwrs
++) {
2150 switch (rate_index
) {
2151 case IWL_RATE_36M_INDEX_TABLE
:
2152 if (i
== 0) /* B/G */
2153 *clip_pwrs
= satur_pwr
;
2155 *clip_pwrs
= satur_pwr
- 5;
2157 case IWL_RATE_48M_INDEX_TABLE
:
2159 *clip_pwrs
= satur_pwr
- 7;
2161 *clip_pwrs
= satur_pwr
- 10;
2163 case IWL_RATE_54M_INDEX_TABLE
:
2165 *clip_pwrs
= satur_pwr
- 9;
2167 *clip_pwrs
= satur_pwr
- 12;
2170 *clip_pwrs
= satur_pwr
;
2178 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2180 * Second pass (during init) to set up priv->channel_info
2182 * Set up Tx-power settings in our channel info database for each VALID
2183 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2184 * and current temperature.
2186 * Since this is based on current temperature (at init time), these values may
2187 * not be valid for very long, but it gives us a starting/default point,
2188 * and allows us to active (i.e. using Tx) scan.
2190 * This does *not* write values to NIC, just sets up our internal table.
2192 int iwl3945_txpower_set_from_eeprom(struct iwl_priv
*priv
)
2194 struct iwl_channel_info
*ch_info
= NULL
;
2195 struct iwl3945_channel_power_info
*pwr_info
;
2196 struct iwl3945_eeprom
*eeprom
= (struct iwl3945_eeprom
*)priv
->eeprom
;
2200 const s8
*clip_pwrs
; /* array of power levels for each rate */
2203 u8 pwr_index
, base_pwr_index
, a_band
;
2207 /* save temperature reference,
2208 * so we can determine next time to calibrate */
2209 temperature
= iwl3945_hw_reg_txpower_get_temperature(priv
);
2210 priv
->last_temperature
= temperature
;
2212 iwl3945_hw_reg_init_channel_groups(priv
);
2214 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2215 for (i
= 0, ch_info
= priv
->channel_info
; i
< priv
->channel_count
;
2217 a_band
= is_channel_a_band(ch_info
);
2218 if (!is_channel_valid(ch_info
))
2221 /* find this channel's channel group (*not* "band") index */
2222 ch_info
->group_index
=
2223 iwl3945_hw_reg_get_ch_grp_index(priv
, ch_info
);
2225 /* Get this chnlgrp's rate->max/clip-powers table */
2226 clip_pwrs
= priv
->clip39_groups
[ch_info
->group_index
].clip_powers
;
2228 /* calculate power index *adjustment* value according to
2229 * diff between current temperature and factory temperature */
2230 delta_index
= iwl3945_hw_reg_adjust_power_by_temp(temperature
,
2231 eeprom
->groups
[ch_info
->group_index
].
2234 IWL_DEBUG_POWER(priv
, "Delta index for channel %d: %d [%d]\n",
2235 ch_info
->channel
, delta_index
, temperature
+
2238 /* set tx power value for all OFDM rates */
2239 for (rate_index
= 0; rate_index
< IWL_OFDM_RATES
;
2241 s32
uninitialized_var(power_idx
);
2244 /* use channel group's clip-power table,
2245 * but don't exceed channel's max power */
2246 s8 pwr
= min(ch_info
->max_power_avg
,
2247 clip_pwrs
[rate_index
]);
2249 pwr_info
= &ch_info
->power_info
[rate_index
];
2251 /* get base (i.e. at factory-measured temperature)
2252 * power table index for this rate's power */
2253 rc
= iwl3945_hw_reg_get_matched_power_index(priv
, pwr
,
2254 ch_info
->group_index
,
2257 IWL_ERR(priv
, "Invalid power index\n");
2260 pwr_info
->base_power_index
= (u8
) power_idx
;
2262 /* temperature compensate */
2263 power_idx
+= delta_index
;
2265 /* stay within range of gain table */
2266 power_idx
= iwl3945_hw_reg_fix_power_index(power_idx
);
2268 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2269 pwr_info
->requested_power
= pwr
;
2270 pwr_info
->power_table_index
= (u8
) power_idx
;
2271 pwr_info
->tpc
.tx_gain
=
2272 power_gain_table
[a_band
][power_idx
].tx_gain
;
2273 pwr_info
->tpc
.dsp_atten
=
2274 power_gain_table
[a_band
][power_idx
].dsp_atten
;
2277 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2278 pwr_info
= &ch_info
->power_info
[IWL_RATE_12M_INDEX_TABLE
];
2279 power
= pwr_info
->requested_power
+
2280 IWL_CCK_FROM_OFDM_POWER_DIFF
;
2281 pwr_index
= pwr_info
->power_table_index
+
2282 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2283 base_pwr_index
= pwr_info
->base_power_index
+
2284 IWL_CCK_FROM_OFDM_INDEX_DIFF
;
2286 /* stay within table range */
2287 pwr_index
= iwl3945_hw_reg_fix_power_index(pwr_index
);
2288 gain
= power_gain_table
[a_band
][pwr_index
].tx_gain
;
2289 dsp_atten
= power_gain_table
[a_band
][pwr_index
].dsp_atten
;
2291 /* fill each CCK rate's iwl3945_channel_power_info structure
2292 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2293 * NOTE: CCK rates start at end of OFDM rates! */
2294 for (rate_index
= 0;
2295 rate_index
< IWL_CCK_RATES
; rate_index
++) {
2296 pwr_info
= &ch_info
->power_info
[rate_index
+IWL_OFDM_RATES
];
2297 pwr_info
->requested_power
= power
;
2298 pwr_info
->power_table_index
= pwr_index
;
2299 pwr_info
->base_power_index
= base_pwr_index
;
2300 pwr_info
->tpc
.tx_gain
= gain
;
2301 pwr_info
->tpc
.dsp_atten
= dsp_atten
;
2304 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2305 for (scan_tbl_index
= 0;
2306 scan_tbl_index
< IWL_NUM_SCAN_RATES
; scan_tbl_index
++) {
2307 s32 actual_index
= (scan_tbl_index
== 0) ?
2308 IWL_RATE_1M_INDEX_TABLE
: IWL_RATE_6M_INDEX_TABLE
;
2309 iwl3945_hw_reg_set_scan_power(priv
, scan_tbl_index
,
2310 actual_index
, clip_pwrs
, ch_info
, a_band
);
2317 int iwl3945_hw_rxq_stop(struct iwl_priv
*priv
)
2321 iwl_write_direct32(priv
, FH39_RCSR_CONFIG(0), 0);
2322 rc
= iwl_poll_direct_bit(priv
, FH39_RSSR_STATUS
,
2323 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE
, 1000);
2325 IWL_ERR(priv
, "Can't stop Rx DMA.\n");
2330 int iwl3945_hw_tx_queue_init(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
2332 int txq_id
= txq
->q
.id
;
2334 struct iwl3945_shared
*shared_data
= priv
->shared_virt
;
2336 shared_data
->tx_base_ptr
[txq_id
] = cpu_to_le32((u32
)txq
->q
.dma_addr
);
2338 iwl_write_direct32(priv
, FH39_CBCC_CTRL(txq_id
), 0);
2339 iwl_write_direct32(priv
, FH39_CBCC_BASE(txq_id
), 0);
2341 iwl_write_direct32(priv
, FH39_TCSR_CONFIG(txq_id
),
2342 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
|
2343 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
|
2344 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
|
2345 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
|
2346 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
);
2348 /* fake read to flush all prev. writes */
2349 iwl_read32(priv
, FH39_TSSR_CBB_BASE
);
2357 static u16
iwl3945_get_hcmd_size(u8 cmd_id
, u16 len
)
2361 return sizeof(struct iwl3945_rxon_cmd
);
2362 case POWER_TABLE_CMD
:
2363 return sizeof(struct iwl3945_powertable_cmd
);
2370 static u16
iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd
*cmd
, u8
*data
)
2372 struct iwl3945_addsta_cmd
*addsta
= (struct iwl3945_addsta_cmd
*)data
;
2373 addsta
->mode
= cmd
->mode
;
2374 memcpy(&addsta
->sta
, &cmd
->sta
, sizeof(struct sta_id_modify
));
2375 memcpy(&addsta
->key
, &cmd
->key
, sizeof(struct iwl4965_keyinfo
));
2376 addsta
->station_flags
= cmd
->station_flags
;
2377 addsta
->station_flags_msk
= cmd
->station_flags_msk
;
2378 addsta
->tid_disable_tx
= cpu_to_le16(0);
2379 addsta
->rate_n_flags
= cmd
->rate_n_flags
;
2380 addsta
->add_immediate_ba_tid
= cmd
->add_immediate_ba_tid
;
2381 addsta
->remove_immediate_ba_tid
= cmd
->remove_immediate_ba_tid
;
2382 addsta
->add_immediate_ba_ssn
= cmd
->add_immediate_ba_ssn
;
2384 return (u16
)sizeof(struct iwl3945_addsta_cmd
);
2389 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2391 int iwl3945_init_hw_rate_table(struct iwl_priv
*priv
)
2393 int rc
, i
, index
, prev_index
;
2394 struct iwl3945_rate_scaling_cmd rate_cmd
= {
2395 .reserved
= {0, 0, 0},
2397 struct iwl3945_rate_scaling_info
*table
= rate_cmd
.table
;
2399 for (i
= 0; i
< ARRAY_SIZE(iwl3945_rates
); i
++) {
2400 index
= iwl3945_rates
[i
].table_rs_index
;
2402 table
[index
].rate_n_flags
=
2403 iwl3945_hw_set_rate_n_flags(iwl3945_rates
[i
].plcp
, 0);
2404 table
[index
].try_cnt
= priv
->retry_rate
;
2405 prev_index
= iwl3945_get_prev_ieee_rate(i
);
2406 table
[index
].next_rate_index
=
2407 iwl3945_rates
[prev_index
].table_rs_index
;
2410 switch (priv
->band
) {
2411 case IEEE80211_BAND_5GHZ
:
2412 IWL_DEBUG_RATE(priv
, "Select A mode rate scale\n");
2413 /* If one of the following CCK rates is used,
2414 * have it fall back to the 6M OFDM rate */
2415 for (i
= IWL_RATE_1M_INDEX_TABLE
;
2416 i
<= IWL_RATE_11M_INDEX_TABLE
; i
++)
2417 table
[i
].next_rate_index
=
2418 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2420 /* Don't fall back to CCK rates */
2421 table
[IWL_RATE_12M_INDEX_TABLE
].next_rate_index
=
2422 IWL_RATE_9M_INDEX_TABLE
;
2424 /* Don't drop out of OFDM rates */
2425 table
[IWL_RATE_6M_INDEX_TABLE
].next_rate_index
=
2426 iwl3945_rates
[IWL_FIRST_OFDM_RATE
].table_rs_index
;
2429 case IEEE80211_BAND_2GHZ
:
2430 IWL_DEBUG_RATE(priv
, "Select B/G mode rate scale\n");
2431 /* If an OFDM rate is used, have it fall back to the
2434 if (!(priv
->sta_supp_rates
& IWL_OFDM_RATES_MASK
) &&
2435 iwl_is_associated(priv
)) {
2437 index
= IWL_FIRST_CCK_RATE
;
2438 for (i
= IWL_RATE_6M_INDEX_TABLE
;
2439 i
<= IWL_RATE_54M_INDEX_TABLE
; i
++)
2440 table
[i
].next_rate_index
=
2441 iwl3945_rates
[index
].table_rs_index
;
2443 index
= IWL_RATE_11M_INDEX_TABLE
;
2444 /* CCK shouldn't fall back to OFDM... */
2445 table
[index
].next_rate_index
= IWL_RATE_5M_INDEX_TABLE
;
2454 /* Update the rate scaling for control frame Tx */
2455 rate_cmd
.table_id
= 0;
2456 rc
= iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2461 /* Update the rate scaling for data frame Tx */
2462 rate_cmd
.table_id
= 1;
2463 return iwl_send_cmd_pdu(priv
, REPLY_RATE_SCALE
, sizeof(rate_cmd
),
2467 /* Called when initializing driver */
2468 int iwl3945_hw_set_hw_params(struct iwl_priv
*priv
)
2470 memset((void *)&priv
->hw_params
, 0,
2471 sizeof(struct iwl_hw_params
));
2473 priv
->shared_virt
= dma_alloc_coherent(&priv
->pci_dev
->dev
,
2474 sizeof(struct iwl3945_shared
),
2475 &priv
->shared_phys
, GFP_KERNEL
);
2476 if (!priv
->shared_virt
) {
2477 IWL_ERR(priv
, "failed to allocate pci memory\n");
2478 mutex_unlock(&priv
->mutex
);
2482 /* Assign number of Usable TX queues */
2483 priv
->hw_params
.max_txq_num
= priv
->cfg
->num_of_queues
;
2485 priv
->hw_params
.tfd_size
= sizeof(struct iwl3945_tfd
);
2486 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_3K
);
2487 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
2488 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
2489 priv
->hw_params
.max_stations
= IWL3945_STATION_COUNT
;
2490 priv
->hw_params
.bcast_sta_id
= IWL3945_BROADCAST_ID
;
2492 priv
->hw_params
.rx_wrt_ptr_reg
= FH39_RSCSR_CHNL0_WPTR
;
2493 priv
->hw_params
.max_beacon_itrvl
= IWL39_MAX_UCODE_BEACON_INTERVAL
;
2498 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv
*priv
,
2499 struct iwl3945_frame
*frame
, u8 rate
)
2501 struct iwl3945_tx_beacon_cmd
*tx_beacon_cmd
;
2502 unsigned int frame_size
;
2504 tx_beacon_cmd
= (struct iwl3945_tx_beacon_cmd
*)&frame
->u
;
2505 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
2507 tx_beacon_cmd
->tx
.sta_id
= priv
->hw_params
.bcast_sta_id
;
2508 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
2510 frame_size
= iwl3945_fill_beacon_frame(priv
,
2511 tx_beacon_cmd
->frame
,
2512 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
2514 BUG_ON(frame_size
> MAX_MPDU_SIZE
);
2515 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
2517 tx_beacon_cmd
->tx
.rate
= rate
;
2518 tx_beacon_cmd
->tx
.tx_flags
= (TX_CMD_FLG_SEQ_CTL_MSK
|
2519 TX_CMD_FLG_TSF_MSK
);
2521 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2522 tx_beacon_cmd
->tx
.supp_rates
[0] =
2523 (IWL_OFDM_BASIC_RATES_MASK
>> IWL_FIRST_OFDM_RATE
) & 0xFF;
2525 tx_beacon_cmd
->tx
.supp_rates
[1] =
2526 (IWL_CCK_BASIC_RATES_MASK
& 0xF);
2528 return sizeof(struct iwl3945_tx_beacon_cmd
) + frame_size
;
2531 void iwl3945_hw_rx_handler_setup(struct iwl_priv
*priv
)
2533 priv
->rx_handlers
[REPLY_TX
] = iwl3945_rx_reply_tx
;
2534 priv
->rx_handlers
[REPLY_3945_RX
] = iwl3945_rx_reply_rx
;
2537 void iwl3945_hw_setup_deferred_work(struct iwl_priv
*priv
)
2539 INIT_DELAYED_WORK(&priv
->thermal_periodic
,
2540 iwl3945_bg_reg_txpower_periodic
);
2543 void iwl3945_hw_cancel_deferred_work(struct iwl_priv
*priv
)
2545 cancel_delayed_work(&priv
->thermal_periodic
);
2548 /* check contents of special bootstrap uCode SRAM */
2549 static int iwl3945_verify_bsm(struct iwl_priv
*priv
)
2551 __le32
*image
= priv
->ucode_boot
.v_addr
;
2552 u32 len
= priv
->ucode_boot
.len
;
2556 IWL_DEBUG_INFO(priv
, "Begin verify bsm\n");
2558 /* verify BSM SRAM contents */
2559 val
= iwl_read_prph(priv
, BSM_WR_DWCOUNT_REG
);
2560 for (reg
= BSM_SRAM_LOWER_BOUND
;
2561 reg
< BSM_SRAM_LOWER_BOUND
+ len
;
2562 reg
+= sizeof(u32
), image
++) {
2563 val
= iwl_read_prph(priv
, reg
);
2564 if (val
!= le32_to_cpu(*image
)) {
2565 IWL_ERR(priv
, "BSM uCode verification failed at "
2566 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2567 BSM_SRAM_LOWER_BOUND
,
2568 reg
- BSM_SRAM_LOWER_BOUND
, len
,
2569 val
, le32_to_cpu(*image
));
2574 IWL_DEBUG_INFO(priv
, "BSM bootstrap uCode image OK\n");
2580 /******************************************************************************
2582 * EEPROM related functions
2584 ******************************************************************************/
2587 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2588 * embedded controller) as EEPROM reader; each read is a series of pulses
2589 * to/from the EEPROM chip, not a single event, so even reads could conflict
2590 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2591 * simply claims ownership, which should be safe when this function is called
2592 * (i.e. before loading uCode!).
2594 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv
*priv
)
2596 _iwl_clear_bit(priv
, CSR_EEPROM_GP
, CSR_EEPROM_GP_IF_OWNER_MSK
);
2601 static void iwl3945_eeprom_release_semaphore(struct iwl_priv
*priv
)
2607 * iwl3945_load_bsm - Load bootstrap instructions
2611 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2612 * in special SRAM that does not power down during RFKILL. When powering back
2613 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2614 * the bootstrap program into the on-board processor, and starts it.
2616 * The bootstrap program loads (via DMA) instructions and data for a new
2617 * program from host DRAM locations indicated by the host driver in the
2618 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2621 * When initializing the NIC, the host driver points the BSM to the
2622 * "initialize" uCode image. This uCode sets up some internal data, then
2623 * notifies host via "initialize alive" that it is complete.
2625 * The host then replaces the BSM_DRAM_* pointer values to point to the
2626 * normal runtime uCode instructions and a backup uCode data cache buffer
2627 * (filled initially with starting data values for the on-board processor),
2628 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2629 * which begins normal operation.
2631 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2632 * the backup data cache in DRAM before SRAM is powered down.
2634 * When powering back up, the BSM loads the bootstrap program. This reloads
2635 * the runtime uCode instructions and the backup data cache into SRAM,
2636 * and re-launches the runtime uCode from where it left off.
2638 static int iwl3945_load_bsm(struct iwl_priv
*priv
)
2640 __le32
*image
= priv
->ucode_boot
.v_addr
;
2641 u32 len
= priv
->ucode_boot
.len
;
2651 IWL_DEBUG_INFO(priv
, "Begin load bsm\n");
2653 /* make sure bootstrap program is no larger than BSM's SRAM size */
2654 if (len
> IWL39_MAX_BSM_SIZE
)
2657 /* Tell bootstrap uCode where to find the "Initialize" uCode
2658 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2659 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2660 * after the "initialize" uCode has run, to point to
2661 * runtime/protocol instructions and backup data cache. */
2662 pinst
= priv
->ucode_init
.p_addr
;
2663 pdata
= priv
->ucode_init_data
.p_addr
;
2664 inst_len
= priv
->ucode_init
.len
;
2665 data_len
= priv
->ucode_init_data
.len
;
2667 iwl_write_prph(priv
, BSM_DRAM_INST_PTR_REG
, pinst
);
2668 iwl_write_prph(priv
, BSM_DRAM_DATA_PTR_REG
, pdata
);
2669 iwl_write_prph(priv
, BSM_DRAM_INST_BYTECOUNT_REG
, inst_len
);
2670 iwl_write_prph(priv
, BSM_DRAM_DATA_BYTECOUNT_REG
, data_len
);
2672 /* Fill BSM memory with bootstrap instructions */
2673 for (reg_offset
= BSM_SRAM_LOWER_BOUND
;
2674 reg_offset
< BSM_SRAM_LOWER_BOUND
+ len
;
2675 reg_offset
+= sizeof(u32
), image
++)
2676 _iwl_write_prph(priv
, reg_offset
,
2677 le32_to_cpu(*image
));
2679 rc
= iwl3945_verify_bsm(priv
);
2683 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2684 iwl_write_prph(priv
, BSM_WR_MEM_SRC_REG
, 0x0);
2685 iwl_write_prph(priv
, BSM_WR_MEM_DST_REG
,
2686 IWL39_RTC_INST_LOWER_BOUND
);
2687 iwl_write_prph(priv
, BSM_WR_DWCOUNT_REG
, len
/ sizeof(u32
));
2689 /* Load bootstrap code into instruction SRAM now,
2690 * to prepare to load "initialize" uCode */
2691 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2692 BSM_WR_CTRL_REG_BIT_START
);
2694 /* Wait for load of bootstrap uCode to finish */
2695 for (i
= 0; i
< 100; i
++) {
2696 done
= iwl_read_prph(priv
, BSM_WR_CTRL_REG
);
2697 if (!(done
& BSM_WR_CTRL_REG_BIT_START
))
2702 IWL_DEBUG_INFO(priv
, "BSM write complete, poll %d iterations\n", i
);
2704 IWL_ERR(priv
, "BSM write did not complete!\n");
2708 /* Enable future boot loads whenever power management unit triggers it
2709 * (e.g. when powering back up after power-save shutdown) */
2710 iwl_write_prph(priv
, BSM_WR_CTRL_REG
,
2711 BSM_WR_CTRL_REG_BIT_START_EN
);
2716 #define IWL3945_UCODE_GET(item) \
2717 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2720 return le32_to_cpu(ucode->u.v1.item); \
2723 static u32
iwl3945_ucode_get_header_size(u32 api_ver
)
2725 return UCODE_HEADER_SIZE(1);
2727 static u32
iwl3945_ucode_get_build(const struct iwl_ucode_header
*ucode
,
2732 static u8
*iwl3945_ucode_get_data(const struct iwl_ucode_header
*ucode
,
2735 return (u8
*) ucode
->u
.v1
.data
;
2738 IWL3945_UCODE_GET(inst_size
);
2739 IWL3945_UCODE_GET(data_size
);
2740 IWL3945_UCODE_GET(init_size
);
2741 IWL3945_UCODE_GET(init_data_size
);
2742 IWL3945_UCODE_GET(boot_size
);
2744 static struct iwl_hcmd_ops iwl3945_hcmd
= {
2745 .rxon_assoc
= iwl3945_send_rxon_assoc
,
2746 .commit_rxon
= iwl3945_commit_rxon
,
2749 static struct iwl_ucode_ops iwl3945_ucode
= {
2750 .get_header_size
= iwl3945_ucode_get_header_size
,
2751 .get_build
= iwl3945_ucode_get_build
,
2752 .get_inst_size
= iwl3945_ucode_get_inst_size
,
2753 .get_data_size
= iwl3945_ucode_get_data_size
,
2754 .get_init_size
= iwl3945_ucode_get_init_size
,
2755 .get_init_data_size
= iwl3945_ucode_get_init_data_size
,
2756 .get_boot_size
= iwl3945_ucode_get_boot_size
,
2757 .get_data
= iwl3945_ucode_get_data
,
2760 static struct iwl_lib_ops iwl3945_lib
= {
2761 .txq_attach_buf_to_tfd
= iwl3945_hw_txq_attach_buf_to_tfd
,
2762 .txq_free_tfd
= iwl3945_hw_txq_free_tfd
,
2763 .txq_init
= iwl3945_hw_tx_queue_init
,
2764 .load_ucode
= iwl3945_load_bsm
,
2765 .dump_nic_event_log
= iwl3945_dump_nic_event_log
,
2766 .dump_nic_error_log
= iwl3945_dump_nic_error_log
,
2768 .init
= iwl3945_apm_init
,
2769 .stop
= iwl_apm_stop
,
2770 .config
= iwl3945_nic_config
,
2771 .set_pwr_src
= iwl3945_set_pwr_src
,
2774 .regulatory_bands
= {
2775 EEPROM_REGULATORY_BAND_1_CHANNELS
,
2776 EEPROM_REGULATORY_BAND_2_CHANNELS
,
2777 EEPROM_REGULATORY_BAND_3_CHANNELS
,
2778 EEPROM_REGULATORY_BAND_4_CHANNELS
,
2779 EEPROM_REGULATORY_BAND_5_CHANNELS
,
2780 EEPROM_REGULATORY_BAND_NO_HT40
,
2781 EEPROM_REGULATORY_BAND_NO_HT40
,
2783 .verify_signature
= iwlcore_eeprom_verify_signature
,
2784 .acquire_semaphore
= iwl3945_eeprom_acquire_semaphore
,
2785 .release_semaphore
= iwl3945_eeprom_release_semaphore
,
2786 .query_addr
= iwlcore_eeprom_query_addr
,
2788 .send_tx_power
= iwl3945_send_tx_power
,
2789 .is_valid_rtc_data_addr
= iwl3945_hw_valid_rtc_data_addr
,
2790 .post_associate
= iwl3945_post_associate
,
2791 .isr
= iwl_isr_legacy
,
2792 .config_ap
= iwl3945_config_ap
,
2793 .add_bcast_station
= iwl3945_add_bcast_station
,
2796 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils
= {
2797 .get_hcmd_size
= iwl3945_get_hcmd_size
,
2798 .build_addsta_hcmd
= iwl3945_build_addsta_hcmd
,
2799 .rts_tx_cmd_flag
= iwlcore_rts_tx_cmd_flag
,
2802 static const struct iwl_ops iwl3945_ops
= {
2803 .ucode
= &iwl3945_ucode
,
2804 .lib
= &iwl3945_lib
,
2805 .hcmd
= &iwl3945_hcmd
,
2806 .utils
= &iwl3945_hcmd_utils
,
2807 .led
= &iwl3945_led_ops
,
2810 static struct iwl_cfg iwl3945_bg_cfg
= {
2812 .fw_name_pre
= IWL3945_FW_PRE
,
2813 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2814 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2816 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2817 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2818 .ops
= &iwl3945_ops
,
2819 .num_of_queues
= IWL39_NUM_QUEUES
,
2820 .mod_params
= &iwl3945_mod_params
,
2821 .pll_cfg_val
= CSR39_ANA_PLL_CFG_VAL
,
2824 .use_isr_legacy
= true,
2825 .ht_greenfield_support
= false,
2826 .led_compensation
= 64,
2827 .broken_powersave
= true,
2828 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2831 static struct iwl_cfg iwl3945_abg_cfg
= {
2833 .fw_name_pre
= IWL3945_FW_PRE
,
2834 .ucode_api_max
= IWL3945_UCODE_API_MAX
,
2835 .ucode_api_min
= IWL3945_UCODE_API_MIN
,
2836 .sku
= IWL_SKU_A
|IWL_SKU_G
,
2837 .eeprom_size
= IWL3945_EEPROM_IMG_SIZE
,
2838 .eeprom_ver
= EEPROM_3945_EEPROM_VERSION
,
2839 .ops
= &iwl3945_ops
,
2840 .num_of_queues
= IWL39_NUM_QUEUES
,
2841 .mod_params
= &iwl3945_mod_params
,
2842 .use_isr_legacy
= true,
2843 .ht_greenfield_support
= false,
2844 .led_compensation
= 64,
2845 .broken_powersave
= true,
2846 .plcp_delta_threshold
= IWL_MAX_PLCP_ERR_THRESHOLD_DEF
,
2849 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids
) = {
2850 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg
)},
2851 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg
)},
2852 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg
)},
2853 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg
)},
2854 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2855 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID
, iwl3945_abg_cfg
)},
2859 MODULE_DEVICE_TABLE(pci
, iwl3945_hw_card_ids
);