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iwlegacy: remove struct il_tx_info
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / iwlegacy / 4965-mac.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/firmware.h>
44 #include <linux/etherdevice.h>
45 #include <linux/if_arp.h>
46
47 #include <net/mac80211.h>
48
49 #include <asm/div64.h>
50
51 #define DRV_NAME "iwl4965"
52
53 #include "common.h"
54 #include "4965.h"
55
56 /******************************************************************************
57 *
58 * module boiler plate
59 *
60 ******************************************************************************/
61
62 /*
63 * module name, copyright, version, etc.
64 */
65 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
66
67 #ifdef CONFIG_IWLEGACY_DEBUG
68 #define VD "d"
69 #else
70 #define VD
71 #endif
72
73 #define DRV_VERSION IWLWIFI_VERSION VD
74
75 MODULE_DESCRIPTION(DRV_DESCRIPTION);
76 MODULE_VERSION(DRV_VERSION);
77 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
78 MODULE_LICENSE("GPL");
79 MODULE_ALIAS("iwl4965");
80
81 void
82 il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status)
83 {
84 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
85 IL_ERR("Tx flush command to flush out all frames\n");
86 if (!test_bit(S_EXIT_PENDING, &il->status))
87 queue_work(il->workqueue, &il->tx_flush);
88 }
89 }
90
91 /*
92 * EEPROM
93 */
94 struct il_mod_params il4965_mod_params = {
95 .amsdu_size_8K = 1,
96 .restart_fw = 1,
97 /* the rest are 0 by default */
98 };
99
100 void
101 il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
102 {
103 unsigned long flags;
104 int i;
105 spin_lock_irqsave(&rxq->lock, flags);
106 INIT_LIST_HEAD(&rxq->rx_free);
107 INIT_LIST_HEAD(&rxq->rx_used);
108 /* Fill the rx_used queue with _all_ of the Rx buffers */
109 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
110 /* In the reset function, these buffers may have been allocated
111 * to an SKB, so we need to unmap and free potential storage */
112 if (rxq->pool[i].page != NULL) {
113 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
114 PAGE_SIZE << il->hw_params.rx_page_order,
115 PCI_DMA_FROMDEVICE);
116 __il_free_pages(il, rxq->pool[i].page);
117 rxq->pool[i].page = NULL;
118 }
119 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
120 }
121
122 for (i = 0; i < RX_QUEUE_SIZE; i++)
123 rxq->queue[i] = NULL;
124
125 /* Set us so that we have processed and used all buffers, but have
126 * not restocked the Rx queue with fresh buffers */
127 rxq->read = rxq->write = 0;
128 rxq->write_actual = 0;
129 rxq->free_count = 0;
130 spin_unlock_irqrestore(&rxq->lock, flags);
131 }
132
133 int
134 il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
135 {
136 u32 rb_size;
137 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
138 u32 rb_timeout = 0;
139
140 if (il->cfg->mod_params->amsdu_size_8K)
141 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
142 else
143 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
144
145 /* Stop Rx DMA */
146 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
147
148 /* Reset driver's Rx queue write idx */
149 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
150
151 /* Tell device where to find RBD circular buffer in DRAM */
152 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));
153
154 /* Tell device where in DRAM to update its Rx status */
155 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);
156
157 /* Enable Rx DMA
158 * Direct rx interrupts to hosts
159 * Rx buffer size 4 or 8k
160 * RB timeout 0x10
161 * 256 RBDs
162 */
163 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,
164 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
165 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
166 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
167 rb_size |
168 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
169 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
170
171 /* Set interrupt coalescing timer to default (2048 usecs) */
172 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
173
174 return 0;
175 }
176
177 static void
178 il4965_set_pwr_vmain(struct il_priv *il)
179 {
180 /*
181 * (for documentation purposes)
182 * to set power to V_AUX, do:
183
184 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
185 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
186 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
187 ~APMG_PS_CTRL_MSK_PWR_SRC);
188 */
189
190 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
191 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
192 ~APMG_PS_CTRL_MSK_PWR_SRC);
193 }
194
195 int
196 il4965_hw_nic_init(struct il_priv *il)
197 {
198 unsigned long flags;
199 struct il_rx_queue *rxq = &il->rxq;
200 int ret;
201
202 /* nic_init */
203 spin_lock_irqsave(&il->lock, flags);
204 il->ops->lib->apm_ops.init(il);
205
206 /* Set interrupt coalescing calibration timer to default (512 usecs) */
207 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
208
209 spin_unlock_irqrestore(&il->lock, flags);
210
211 il4965_set_pwr_vmain(il);
212
213 il->ops->lib->apm_ops.config(il);
214
215 /* Allocate the RX queue, or reset if it is already allocated */
216 if (!rxq->bd) {
217 ret = il_rx_queue_alloc(il);
218 if (ret) {
219 IL_ERR("Unable to initialize Rx queue\n");
220 return -ENOMEM;
221 }
222 } else
223 il4965_rx_queue_reset(il, rxq);
224
225 il4965_rx_replenish(il);
226
227 il4965_rx_init(il, rxq);
228
229 spin_lock_irqsave(&il->lock, flags);
230
231 rxq->need_update = 1;
232 il_rx_queue_update_write_ptr(il, rxq);
233
234 spin_unlock_irqrestore(&il->lock, flags);
235
236 /* Allocate or reset and init all Tx and Command queues */
237 if (!il->txq) {
238 ret = il4965_txq_ctx_alloc(il);
239 if (ret)
240 return ret;
241 } else
242 il4965_txq_ctx_reset(il);
243
244 set_bit(S_INIT, &il->status);
245
246 return 0;
247 }
248
249 /**
250 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
251 */
252 static inline __le32
253 il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
254 {
255 return cpu_to_le32((u32) (dma_addr >> 8));
256 }
257
258 /**
259 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
260 *
261 * If there are slots in the RX queue that need to be restocked,
262 * and we have free pre-allocated buffers, fill the ranks as much
263 * as we can, pulling from rx_free.
264 *
265 * This moves the 'write' idx forward to catch up with 'processed', and
266 * also updates the memory address in the firmware to reference the new
267 * target buffer.
268 */
269 void
270 il4965_rx_queue_restock(struct il_priv *il)
271 {
272 struct il_rx_queue *rxq = &il->rxq;
273 struct list_head *element;
274 struct il_rx_buf *rxb;
275 unsigned long flags;
276
277 spin_lock_irqsave(&rxq->lock, flags);
278 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
279 /* The overwritten rxb must be a used one */
280 rxb = rxq->queue[rxq->write];
281 BUG_ON(rxb && rxb->page);
282
283 /* Get next free Rx buffer, remove from free list */
284 element = rxq->rx_free.next;
285 rxb = list_entry(element, struct il_rx_buf, list);
286 list_del(element);
287
288 /* Point to Rx buffer via next RBD in circular buffer */
289 rxq->bd[rxq->write] =
290 il4965_dma_addr2rbd_ptr(il, rxb->page_dma);
291 rxq->queue[rxq->write] = rxb;
292 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
293 rxq->free_count--;
294 }
295 spin_unlock_irqrestore(&rxq->lock, flags);
296 /* If the pre-allocated buffer pool is dropping low, schedule to
297 * refill it */
298 if (rxq->free_count <= RX_LOW_WATERMARK)
299 queue_work(il->workqueue, &il->rx_replenish);
300
301 /* If we've added more space for the firmware to place data, tell it.
302 * Increment device's write pointer in multiples of 8. */
303 if (rxq->write_actual != (rxq->write & ~0x7)) {
304 spin_lock_irqsave(&rxq->lock, flags);
305 rxq->need_update = 1;
306 spin_unlock_irqrestore(&rxq->lock, flags);
307 il_rx_queue_update_write_ptr(il, rxq);
308 }
309 }
310
311 /**
312 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
313 *
314 * When moving to rx_free an SKB is allocated for the slot.
315 *
316 * Also restock the Rx queue via il_rx_queue_restock.
317 * This is called as a scheduled work item (except for during initialization)
318 */
319 static void
320 il4965_rx_allocate(struct il_priv *il, gfp_t priority)
321 {
322 struct il_rx_queue *rxq = &il->rxq;
323 struct list_head *element;
324 struct il_rx_buf *rxb;
325 struct page *page;
326 unsigned long flags;
327 gfp_t gfp_mask = priority;
328
329 while (1) {
330 spin_lock_irqsave(&rxq->lock, flags);
331 if (list_empty(&rxq->rx_used)) {
332 spin_unlock_irqrestore(&rxq->lock, flags);
333 return;
334 }
335 spin_unlock_irqrestore(&rxq->lock, flags);
336
337 if (rxq->free_count > RX_LOW_WATERMARK)
338 gfp_mask |= __GFP_NOWARN;
339
340 if (il->hw_params.rx_page_order > 0)
341 gfp_mask |= __GFP_COMP;
342
343 /* Alloc a new receive buffer */
344 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
345 if (!page) {
346 if (net_ratelimit())
347 D_INFO("alloc_pages failed, " "order: %d\n",
348 il->hw_params.rx_page_order);
349
350 if (rxq->free_count <= RX_LOW_WATERMARK &&
351 net_ratelimit())
352 IL_ERR("Failed to alloc_pages with %s. "
353 "Only %u free buffers remaining.\n",
354 priority ==
355 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
356 rxq->free_count);
357 /* We don't reschedule replenish work here -- we will
358 * call the restock method and if it still needs
359 * more buffers it will schedule replenish */
360 return;
361 }
362
363 spin_lock_irqsave(&rxq->lock, flags);
364
365 if (list_empty(&rxq->rx_used)) {
366 spin_unlock_irqrestore(&rxq->lock, flags);
367 __free_pages(page, il->hw_params.rx_page_order);
368 return;
369 }
370 element = rxq->rx_used.next;
371 rxb = list_entry(element, struct il_rx_buf, list);
372 list_del(element);
373
374 spin_unlock_irqrestore(&rxq->lock, flags);
375
376 BUG_ON(rxb->page);
377 rxb->page = page;
378 /* Get physical address of the RB */
379 rxb->page_dma =
380 pci_map_page(il->pci_dev, page, 0,
381 PAGE_SIZE << il->hw_params.rx_page_order,
382 PCI_DMA_FROMDEVICE);
383 /* dma address must be no more than 36 bits */
384 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
385 /* and also 256 byte aligned! */
386 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
387
388 spin_lock_irqsave(&rxq->lock, flags);
389
390 list_add_tail(&rxb->list, &rxq->rx_free);
391 rxq->free_count++;
392 il->alloc_rxb_page++;
393
394 spin_unlock_irqrestore(&rxq->lock, flags);
395 }
396 }
397
398 void
399 il4965_rx_replenish(struct il_priv *il)
400 {
401 unsigned long flags;
402
403 il4965_rx_allocate(il, GFP_KERNEL);
404
405 spin_lock_irqsave(&il->lock, flags);
406 il4965_rx_queue_restock(il);
407 spin_unlock_irqrestore(&il->lock, flags);
408 }
409
410 void
411 il4965_rx_replenish_now(struct il_priv *il)
412 {
413 il4965_rx_allocate(il, GFP_ATOMIC);
414
415 il4965_rx_queue_restock(il);
416 }
417
418 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
419 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
420 * This free routine walks the list of POOL entries and if SKB is set to
421 * non NULL it is unmapped and freed
422 */
423 void
424 il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
425 {
426 int i;
427 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
428 if (rxq->pool[i].page != NULL) {
429 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
430 PAGE_SIZE << il->hw_params.rx_page_order,
431 PCI_DMA_FROMDEVICE);
432 __il_free_pages(il, rxq->pool[i].page);
433 rxq->pool[i].page = NULL;
434 }
435 }
436
437 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
438 rxq->bd_dma);
439 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
440 rxq->rb_stts, rxq->rb_stts_dma);
441 rxq->bd = NULL;
442 rxq->rb_stts = NULL;
443 }
444
445 int
446 il4965_rxq_stop(struct il_priv *il)
447 {
448
449 /* stop Rx DMA */
450 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);
451 il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG,
452 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
453
454 return 0;
455 }
456
457 int
458 il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
459 {
460 int idx = 0;
461 int band_offset = 0;
462
463 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
464 if (rate_n_flags & RATE_MCS_HT_MSK) {
465 idx = (rate_n_flags & 0xff);
466 return idx;
467 /* Legacy rate format, search for match in table */
468 } else {
469 if (band == IEEE80211_BAND_5GHZ)
470 band_offset = IL_FIRST_OFDM_RATE;
471 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
472 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
473 return idx - band_offset;
474 }
475
476 return -1;
477 }
478
479 static int
480 il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp)
481 {
482 /* data from PHY/DSP regarding signal strength, etc.,
483 * contents are always there, not configurable by host. */
484 struct il4965_rx_non_cfg_phy *ncphy =
485 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
486 u32 agc =
487 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >>
488 IL49_AGC_DB_POS;
489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512 }
513
514 static u32
515 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
516 {
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |=
522 (RX_RES_STATUS_STATION_FOUND |
523 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
524
525 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
526
527 /* packet was not encrypted */
528 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
529 RX_RES_STATUS_SEC_TYPE_NONE)
530 return decrypt_out;
531
532 /* packet was encrypted with unknown alg */
533 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
534 RX_RES_STATUS_SEC_TYPE_ERR)
535 return decrypt_out;
536
537 /* decryption was not done in HW */
538 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
539 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
540 return decrypt_out;
541
542 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
543
544 case RX_RES_STATUS_SEC_TYPE_CCMP:
545 /* alg is CCM: check MIC only */
546 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
547 /* Bad MIC */
548 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
549 else
550 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
551
552 break;
553
554 case RX_RES_STATUS_SEC_TYPE_TKIP:
555 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
556 /* Bad TTAK */
557 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
558 break;
559 }
560 /* fall through if TTAK OK */
561 default:
562 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
563 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
564 else
565 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
566 break;
567 }
568
569 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out);
570
571 return decrypt_out;
572 }
573
574 static void
575 il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr,
576 u16 len, u32 ampdu_status, struct il_rx_buf *rxb,
577 struct ieee80211_rx_status *stats)
578 {
579 struct sk_buff *skb;
580 __le16 fc = hdr->frame_control;
581
582 /* We only process data packets if the interface is open */
583 if (unlikely(!il->is_open)) {
584 D_DROP("Dropping packet while interface is not open.\n");
585 return;
586 }
587
588 /* In case of HW accelerated crypto and bad decryption, drop */
589 if (!il->cfg->mod_params->sw_crypto &&
590 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
591 return;
592
593 skb = dev_alloc_skb(128);
594 if (!skb) {
595 IL_ERR("dev_alloc_skb failed\n");
596 return;
597 }
598
599 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
600
601 il_update_stats(il, false, fc, len);
602 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
603
604 ieee80211_rx(il->hw, skb);
605 il->alloc_rxb_page--;
606 rxb->page = NULL;
607 }
608
609 /* Called for N_RX (legacy ABG frames), or
610 * N_RX_MPDU (HT high-throughput N frames). */
611 void
612 il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb)
613 {
614 struct ieee80211_hdr *header;
615 struct ieee80211_rx_status rx_status;
616 struct il_rx_pkt *pkt = rxb_addr(rxb);
617 struct il_rx_phy_res *phy_res;
618 __le32 rx_pkt_status;
619 struct il_rx_mpdu_res_start *amsdu;
620 u32 len;
621 u32 ampdu_status;
622 u32 rate_n_flags;
623
624 /**
625 * N_RX and N_RX_MPDU are handled differently.
626 * N_RX: physical layer info is in this buffer
627 * N_RX_MPDU: physical layer info was sent in separate
628 * command and cached in il->last_phy_res
629 *
630 * Here we set up local variables depending on which command is
631 * received.
632 */
633 if (pkt->hdr.cmd == N_RX) {
634 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
635 header =
636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) +
637 phy_res->cfg_phy_cnt);
638
639 len = le16_to_cpu(phy_res->byte_count);
640 rx_pkt_status =
641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) +
642 phy_res->cfg_phy_cnt + len);
643 ampdu_status = le32_to_cpu(rx_pkt_status);
644 } else {
645 if (!il->_4965.last_phy_res_valid) {
646 IL_ERR("MPDU frame without cached PHY data\n");
647 return;
648 }
649 phy_res = &il->_4965.last_phy_res;
650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
652 len = le16_to_cpu(amsdu->byte_count);
653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len);
654 ampdu_status =
655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status));
656 }
657
658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
659 D_DROP("dsp size out of range [0,20]: %d/n",
660 phy_res->cfg_phy_cnt);
661 return;
662 }
663
664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status));
667 return;
668 }
669
670 /* This will be used in several places later */
671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
672
673 /* rx_status carries information about the packet to mac80211 */
674 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
675 rx_status.band =
676 (phy_res->
677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ :
678 IEEE80211_BAND_5GHZ;
679 rx_status.freq =
680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
681 rx_status.band);
682 rx_status.rate_idx =
683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
684 rx_status.flag = 0;
685
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */
689
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
691
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
694
695 il_dbg_log_rx_data_frame(il, len, header);
696 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal,
697 (unsigned long long)rx_status.mactime);
698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >>
714 RX_RES_PHY_FLAGS_ANTENNA_POS;
715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb,
729 &rx_status);
730 }
731
732 /* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY).
733 * This will be used later in il_hdl_rx() for N_RX_MPDU. */
734 void
735 il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb)
736 {
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741 }
742
743 static int
744 il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif,
745 enum ieee80211_band band, u8 is_active,
746 u8 n_probes, struct il_scan_channel *scan_ch)
747 {
748 struct ieee80211_channel *chan;
749 const struct ieee80211_supported_band *sband;
750 const struct il_channel_info *ch_info;
751 u16 passive_dwell = 0;
752 u16 active_dwell = 0;
753 int added, i;
754 u16 channel;
755
756 sband = il_get_hw_mode(il, band);
757 if (!sband)
758 return 0;
759
760 active_dwell = il_get_active_dwell_time(il, band, n_probes);
761 passive_dwell = il_get_passive_dwell_time(il, band, vif);
762
763 if (passive_dwell <= active_dwell)
764 passive_dwell = active_dwell + 1;
765
766 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
767 chan = il->scan_request->channels[i];
768
769 if (chan->band != band)
770 continue;
771
772 channel = chan->hw_value;
773 scan_ch->channel = cpu_to_le16(channel);
774
775 ch_info = il_get_channel_info(il, band, channel);
776 if (!il_is_channel_valid(ch_info)) {
777 D_SCAN("Channel %d is INVALID for this band.\n",
778 channel);
779 continue;
780 }
781
782 if (!is_active || il_is_channel_passive(ch_info) ||
783 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
784 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
785 else
786 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
787
788 if (n_probes)
789 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
790
791 scan_ch->active_dwell = cpu_to_le16(active_dwell);
792 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
793
794 /* Set txpower levels to defaults */
795 scan_ch->dsp_atten = 110;
796
797 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
798 * power level:
799 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
800 */
801 if (band == IEEE80211_BAND_5GHZ)
802 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
803 else
804 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
805
806 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel,
807 le32_to_cpu(scan_ch->type),
808 (scan_ch->
809 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE",
810 (scan_ch->
811 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell :
812 passive_dwell);
813
814 scan_ch++;
815 added++;
816 }
817
818 D_SCAN("total channels to scan %d\n", added);
819 return added;
820 }
821
822 static void
823 il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid)
824 {
825 int i;
826 u8 ind = *ant;
827
828 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
829 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
830 if (valid & BIT(ind)) {
831 *ant = ind;
832 return;
833 }
834 }
835 }
836
837 int
838 il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
839 {
840 struct il_host_cmd cmd = {
841 .id = C_SCAN,
842 .len = sizeof(struct il_scan_cmd),
843 .flags = CMD_SIZE_HUGE,
844 };
845 struct il_scan_cmd *scan;
846 u32 rate_flags = 0;
847 u16 cmd_len;
848 u16 rx_chain = 0;
849 enum ieee80211_band band;
850 u8 n_probes = 0;
851 u8 rx_ant = il->hw_params.valid_rx_ant;
852 u8 rate;
853 bool is_active = false;
854 int chan_mod;
855 u8 active_chains;
856 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
857 int ret;
858
859 lockdep_assert_held(&il->mutex);
860
861 if (!il->scan_cmd) {
862 il->scan_cmd =
863 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE,
864 GFP_KERNEL);
865 if (!il->scan_cmd) {
866 D_SCAN("fail to allocate memory for scan\n");
867 return -ENOMEM;
868 }
869 }
870 scan = il->scan_cmd;
871 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
872
873 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
874 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
875
876 if (il_is_any_associated(il)) {
877 u16 interval;
878 u32 extra;
879 u32 suspend_time = 100;
880 u32 scan_suspend_time = 100;
881
882 D_INFO("Scanning while associated...\n");
883 interval = vif->bss_conf.beacon_int;
884
885 scan->suspend_time = 0;
886 scan->max_out_time = cpu_to_le32(200 * 1024);
887 if (!interval)
888 interval = suspend_time;
889
890 extra = (suspend_time / interval) << 22;
891 scan_suspend_time =
892 (extra | ((suspend_time % interval) * 1024));
893 scan->suspend_time = cpu_to_le32(scan_suspend_time);
894 D_SCAN("suspend_time 0x%X beacon interval %d\n",
895 scan_suspend_time, interval);
896 }
897
898 if (il->scan_request->n_ssids) {
899 int i, p = 0;
900 D_SCAN("Kicking off active scan\n");
901 for (i = 0; i < il->scan_request->n_ssids; i++) {
902 /* always does wildcard anyway */
903 if (!il->scan_request->ssids[i].ssid_len)
904 continue;
905 scan->direct_scan[p].id = WLAN_EID_SSID;
906 scan->direct_scan[p].len =
907 il->scan_request->ssids[i].ssid_len;
908 memcpy(scan->direct_scan[p].ssid,
909 il->scan_request->ssids[i].ssid,
910 il->scan_request->ssids[i].ssid_len);
911 n_probes++;
912 p++;
913 }
914 is_active = true;
915 } else
916 D_SCAN("Start passive scan.\n");
917
918 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
919 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
920 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
921
922 switch (il->scan_band) {
923 case IEEE80211_BAND_2GHZ:
924 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
925 chan_mod =
926 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >>
927 RXON_FLG_CHANNEL_MODE_POS;
928 if (chan_mod == CHANNEL_MODE_PURE_40) {
929 rate = RATE_6M_PLCP;
930 } else {
931 rate = RATE_1M_PLCP;
932 rate_flags = RATE_MCS_CCK_MSK;
933 }
934 break;
935 case IEEE80211_BAND_5GHZ:
936 rate = RATE_6M_PLCP;
937 break;
938 default:
939 IL_WARN("Invalid scan band\n");
940 return -EIO;
941 }
942
943 /*
944 * If active scanning is requested but a certain channel is
945 * marked passive, we can do active scanning if we detect
946 * transmissions.
947 *
948 * There is an issue with some firmware versions that triggers
949 * a sysassert on a "good CRC threshold" of zero (== disabled),
950 * on a radar channel even though this means that we should NOT
951 * send probes.
952 *
953 * The "good CRC threshold" is the number of frames that we
954 * need to receive during our dwell time on a channel before
955 * sending out probes -- setting this to a huge value will
956 * mean we never reach it, but at the same time work around
957 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
958 * here instead of IL_GOOD_CRC_TH_DISABLED.
959 */
960 scan->good_CRC_th =
961 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
962
963 band = il->scan_band;
964
965 if (il->cfg->scan_rx_antennas[band])
966 rx_ant = il->cfg->scan_rx_antennas[band];
967
968 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas);
969 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS;
970 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags);
971
972 /* In power save mode use one chain, otherwise use all chains */
973 if (test_bit(S_POWER_PMI, &il->status)) {
974 /* rx_ant has been set to all valid chains previously */
975 active_chains =
976 rx_ant & ((u8) (il->chain_noise_data.active_chains));
977 if (!active_chains)
978 active_chains = rx_ant;
979
980 D_SCAN("chain_noise_data.active_chains: %u\n",
981 il->chain_noise_data.active_chains);
982
983 rx_ant = il4965_first_antenna(active_chains);
984 }
985
986 /* MIMO is not used here, but value is required */
987 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
988 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
989 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
990 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
991 scan->rx_chain = cpu_to_le16(rx_chain);
992
993 cmd_len =
994 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
995 vif->addr, il->scan_request->ie,
996 il->scan_request->ie_len,
997 IL_MAX_SCAN_SIZE - sizeof(*scan));
998 scan->tx_cmd.len = cpu_to_le16(cmd_len);
999
1000 scan->filter_flags |=
1001 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK);
1002
1003 scan->channel_count =
1004 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes,
1005 (void *)&scan->data[cmd_len]);
1006 if (scan->channel_count == 0) {
1007 D_SCAN("channel count %d\n", scan->channel_count);
1008 return -EIO;
1009 }
1010
1011 cmd.len +=
1012 le16_to_cpu(scan->tx_cmd.len) +
1013 scan->channel_count * sizeof(struct il_scan_channel);
1014 cmd.data = scan;
1015 scan->len = cpu_to_le16(cmd.len);
1016
1017 set_bit(S_SCAN_HW, &il->status);
1018
1019 ret = il_send_cmd_sync(il, &cmd);
1020 if (ret)
1021 clear_bit(S_SCAN_HW, &il->status);
1022
1023 return ret;
1024 }
1025
1026 int
1027 il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
1028 bool add)
1029 {
1030 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1031
1032 if (add)
1033 return il4965_add_bssid_station(il, vif->bss_conf.bssid,
1034 &vif_priv->ibss_bssid_sta_id);
1035 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1036 vif->bss_conf.bssid);
1037 }
1038
1039 void
1040 il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed)
1041 {
1042 lockdep_assert_held(&il->sta_lock);
1043
1044 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1045 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1046 else {
1047 D_TX("free more than tfds_in_queue (%u:%d)\n",
1048 il->stations[sta_id].tid[tid].tfds_in_queue, freed);
1049 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1050 }
1051 }
1052
1053 #define IL_TX_QUEUE_MSK 0xfffff
1054
1055 static bool
1056 il4965_is_single_rx_stream(struct il_priv *il)
1057 {
1058 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1059 il->current_ht_config.single_chain_sufficient;
1060 }
1061
1062 #define IL_NUM_RX_CHAINS_MULTIPLE 3
1063 #define IL_NUM_RX_CHAINS_SINGLE 2
1064 #define IL_NUM_IDLE_CHAINS_DUAL 2
1065 #define IL_NUM_IDLE_CHAINS_SINGLE 1
1066
1067 /*
1068 * Determine how many receiver/antenna chains to use.
1069 *
1070 * More provides better reception via diversity. Fewer saves power
1071 * at the expense of throughput, but only when not in powersave to
1072 * start with.
1073 *
1074 * MIMO (dual stream) requires at least 2, but works better with 3.
1075 * This does not determine *which* chains to use, just how many.
1076 */
1077 static int
1078 il4965_get_active_rx_chain_count(struct il_priv *il)
1079 {
1080 /* # of Rx chains to use when expecting MIMO. */
1081 if (il4965_is_single_rx_stream(il))
1082 return IL_NUM_RX_CHAINS_SINGLE;
1083 else
1084 return IL_NUM_RX_CHAINS_MULTIPLE;
1085 }
1086
1087 /*
1088 * When we are in power saving mode, unless device support spatial
1089 * multiplexing power save, use the active count for rx chain count.
1090 */
1091 static int
1092 il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1093 {
1094 /* # Rx chains when idling, depending on SMPS mode */
1095 switch (il->current_ht_config.smps) {
1096 case IEEE80211_SMPS_STATIC:
1097 case IEEE80211_SMPS_DYNAMIC:
1098 return IL_NUM_IDLE_CHAINS_SINGLE;
1099 case IEEE80211_SMPS_OFF:
1100 return active_cnt;
1101 default:
1102 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps);
1103 return active_cnt;
1104 }
1105 }
1106
1107 /* up to 4 chains */
1108 static u8
1109 il4965_count_chain_bitmap(u32 chain_bitmap)
1110 {
1111 u8 res;
1112 res = (chain_bitmap & BIT(0)) >> 0;
1113 res += (chain_bitmap & BIT(1)) >> 1;
1114 res += (chain_bitmap & BIT(2)) >> 2;
1115 res += (chain_bitmap & BIT(3)) >> 3;
1116 return res;
1117 }
1118
1119 /**
1120 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1121 *
1122 * Selects how many and which Rx receivers/antennas/chains to use.
1123 * This should not be used for scan command ... it puts data in wrong place.
1124 */
1125 void
1126 il4965_set_rxon_chain(struct il_priv *il)
1127 {
1128 bool is_single = il4965_is_single_rx_stream(il);
1129 bool is_cam = !test_bit(S_POWER_PMI, &il->status);
1130 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1131 u32 active_chains;
1132 u16 rx_chain;
1133
1134 /* Tell uCode which antennas are actually connected.
1135 * Before first association, we assume all antennas are connected.
1136 * Just after first association, il4965_chain_noise_calibration()
1137 * checks which antennas actually *are* connected. */
1138 if (il->chain_noise_data.active_chains)
1139 active_chains = il->chain_noise_data.active_chains;
1140 else
1141 active_chains = il->hw_params.valid_rx_ant;
1142
1143 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1144
1145 /* How many receivers should we use? */
1146 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1147 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1148
1149 /* correct rx chain count according hw settings
1150 * and chain noise calibration
1151 */
1152 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1153 if (valid_rx_cnt < active_rx_cnt)
1154 active_rx_cnt = valid_rx_cnt;
1155
1156 if (valid_rx_cnt < idle_rx_cnt)
1157 idle_rx_cnt = valid_rx_cnt;
1158
1159 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1160 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1161
1162 il->staging.rx_chain = cpu_to_le16(rx_chain);
1163
1164 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1165 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1166 else
1167 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1168
1169 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain,
1170 active_rx_cnt, idle_rx_cnt);
1171
1172 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1173 active_rx_cnt < idle_rx_cnt);
1174 }
1175
1176 static const char *
1177 il4965_get_fh_string(int cmd)
1178 {
1179 switch (cmd) {
1180 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG);
1181 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG);
1182 IL_CMD(FH49_RSCSR_CHNL0_WPTR);
1183 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG);
1184 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG);
1185 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG);
1186 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1187 IL_CMD(FH49_TSSR_TX_STATUS_REG);
1188 IL_CMD(FH49_TSSR_TX_ERROR_REG);
1189 default:
1190 return "UNKNOWN";
1191 }
1192 }
1193
1194 int
1195 il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1196 {
1197 int i;
1198 #ifdef CONFIG_IWLEGACY_DEBUG
1199 int pos = 0;
1200 size_t bufsz = 0;
1201 #endif
1202 static const u32 fh_tbl[] = {
1203 FH49_RSCSR_CHNL0_STTS_WPTR_REG,
1204 FH49_RSCSR_CHNL0_RBDCB_BASE_REG,
1205 FH49_RSCSR_CHNL0_WPTR,
1206 FH49_MEM_RCSR_CHNL0_CONFIG_REG,
1207 FH49_MEM_RSSR_SHARED_CTRL_REG,
1208 FH49_MEM_RSSR_RX_STATUS_REG,
1209 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1210 FH49_TSSR_TX_STATUS_REG,
1211 FH49_TSSR_TX_ERROR_REG
1212 };
1213 #ifdef CONFIG_IWLEGACY_DEBUG
1214 if (display) {
1215 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1216 *buf = kmalloc(bufsz, GFP_KERNEL);
1217 if (!*buf)
1218 return -ENOMEM;
1219 pos +=
1220 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n");
1221 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1222 pos +=
1223 scnprintf(*buf + pos, bufsz - pos,
1224 " %34s: 0X%08x\n",
1225 il4965_get_fh_string(fh_tbl[i]),
1226 il_rd(il, fh_tbl[i]));
1227 }
1228 return pos;
1229 }
1230 #endif
1231 IL_ERR("FH register values:\n");
1232 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1233 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]),
1234 il_rd(il, fh_tbl[i]));
1235 }
1236 return 0;
1237 }
1238
1239 void
1240 il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb)
1241 {
1242 struct il_rx_pkt *pkt = rxb_addr(rxb);
1243 struct il_missed_beacon_notif *missed_beacon;
1244
1245 missed_beacon = &pkt->u.missed_beacon;
1246 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
1247 il->missed_beacon_threshold) {
1248 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
1249 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
1250 le32_to_cpu(missed_beacon->total_missed_becons),
1251 le32_to_cpu(missed_beacon->num_recvd_beacons),
1252 le32_to_cpu(missed_beacon->num_expected_beacons));
1253 if (!test_bit(S_SCANNING, &il->status))
1254 il4965_init_sensitivity(il);
1255 }
1256 }
1257
1258 /* Calculate noise level, based on measurements during network silence just
1259 * before arriving beacon. This measurement can be done only if we know
1260 * exactly when to expect beacons, therefore only when we're associated. */
1261 static void
1262 il4965_rx_calc_noise(struct il_priv *il)
1263 {
1264 struct stats_rx_non_phy *rx_info;
1265 int num_active_rx = 0;
1266 int total_silence = 0;
1267 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
1268 int last_rx_noise;
1269
1270 rx_info = &(il->_4965.stats.rx.general);
1271 bcn_silence_a =
1272 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1273 bcn_silence_b =
1274 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1275 bcn_silence_c =
1276 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1277
1278 if (bcn_silence_a) {
1279 total_silence += bcn_silence_a;
1280 num_active_rx++;
1281 }
1282 if (bcn_silence_b) {
1283 total_silence += bcn_silence_b;
1284 num_active_rx++;
1285 }
1286 if (bcn_silence_c) {
1287 total_silence += bcn_silence_c;
1288 num_active_rx++;
1289 }
1290
1291 /* Average among active antennas */
1292 if (num_active_rx)
1293 last_rx_noise = (total_silence / num_active_rx) - 107;
1294 else
1295 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
1296
1297 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a,
1298 bcn_silence_b, bcn_silence_c, last_rx_noise);
1299 }
1300
1301 #ifdef CONFIG_IWLEGACY_DEBUGFS
1302 /*
1303 * based on the assumption of all stats counter are in DWORD
1304 * FIXME: This function is for debugging, do not deal with
1305 * the case of counters roll-over.
1306 */
1307 static void
1308 il4965_accumulative_stats(struct il_priv *il, __le32 * stats)
1309 {
1310 int i, size;
1311 __le32 *prev_stats;
1312 u32 *accum_stats;
1313 u32 *delta, *max_delta;
1314 struct stats_general_common *general, *accum_general;
1315 struct stats_tx *tx, *accum_tx;
1316
1317 prev_stats = (__le32 *) &il->_4965.stats;
1318 accum_stats = (u32 *) &il->_4965.accum_stats;
1319 size = sizeof(struct il_notif_stats);
1320 general = &il->_4965.stats.general.common;
1321 accum_general = &il->_4965.accum_stats.general.common;
1322 tx = &il->_4965.stats.tx;
1323 accum_tx = &il->_4965.accum_stats.tx;
1324 delta = (u32 *) &il->_4965.delta_stats;
1325 max_delta = (u32 *) &il->_4965.max_delta;
1326
1327 for (i = sizeof(__le32); i < size;
1328 i +=
1329 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++,
1330 accum_stats++) {
1331 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
1332 *delta =
1333 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats));
1334 *accum_stats += *delta;
1335 if (*delta > *max_delta)
1336 *max_delta = *delta;
1337 }
1338 }
1339
1340 /* reset accumulative stats for "no-counter" type stats */
1341 accum_general->temperature = general->temperature;
1342 accum_general->ttl_timestamp = general->ttl_timestamp;
1343 }
1344 #endif
1345
1346 #define REG_RECALIB_PERIOD (60)
1347
1348 void
1349 il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb)
1350 {
1351 int change;
1352 struct il_rx_pkt *pkt = rxb_addr(rxb);
1353
1354 D_RX("Statistics notification received (%d vs %d).\n",
1355 (int)sizeof(struct il_notif_stats),
1356 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK);
1357
1358 change =
1359 ((il->_4965.stats.general.common.temperature !=
1360 pkt->u.stats.general.common.temperature) ||
1361 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) !=
1362 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK)));
1363 #ifdef CONFIG_IWLEGACY_DEBUGFS
1364 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats);
1365 #endif
1366
1367 /* TODO: reading some of stats is unneeded */
1368 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats));
1369
1370 set_bit(S_STATS, &il->status);
1371
1372 /* Reschedule the stats timer to occur in
1373 * REG_RECALIB_PERIOD seconds to ensure we get a
1374 * thermal update even if the uCode doesn't give
1375 * us one */
1376 mod_timer(&il->stats_periodic,
1377 jiffies + msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
1378
1379 if (unlikely(!test_bit(S_SCANNING, &il->status)) &&
1380 (pkt->hdr.cmd == N_STATS)) {
1381 il4965_rx_calc_noise(il);
1382 queue_work(il->workqueue, &il->run_time_calib_work);
1383 }
1384 if (il->ops->lib->temp_ops.temperature && change)
1385 il->ops->lib->temp_ops.temperature(il);
1386 }
1387
1388 void
1389 il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb)
1390 {
1391 struct il_rx_pkt *pkt = rxb_addr(rxb);
1392
1393 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) {
1394 #ifdef CONFIG_IWLEGACY_DEBUGFS
1395 memset(&il->_4965.accum_stats, 0,
1396 sizeof(struct il_notif_stats));
1397 memset(&il->_4965.delta_stats, 0,
1398 sizeof(struct il_notif_stats));
1399 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats));
1400 #endif
1401 D_RX("Statistics have been cleared\n");
1402 }
1403 il4965_hdl_stats(il, rxb);
1404 }
1405
1406
1407 /*
1408 * mac80211 queues, ACs, hardware queues, FIFOs.
1409 *
1410 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
1411 *
1412 * Mac80211 uses the following numbers, which we get as from it
1413 * by way of skb_get_queue_mapping(skb):
1414 *
1415 * VO 0
1416 * VI 1
1417 * BE 2
1418 * BK 3
1419 *
1420 *
1421 * Regular (not A-MPDU) frames are put into hardware queues corresponding
1422 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
1423 * own queue per aggregation session (RA/TID combination), such queues are
1424 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
1425 * order to map frames to the right queue, we also need an AC->hw queue
1426 * mapping. This is implemented here.
1427 *
1428 * Due to the way hw queues are set up (by the hw specific modules like
1429 * 4965.c), the AC->hw queue mapping is the identity
1430 * mapping.
1431 */
1432
1433 static const u8 tid_to_ac[] = {
1434 IEEE80211_AC_BE,
1435 IEEE80211_AC_BK,
1436 IEEE80211_AC_BK,
1437 IEEE80211_AC_BE,
1438 IEEE80211_AC_VI,
1439 IEEE80211_AC_VI,
1440 IEEE80211_AC_VO,
1441 IEEE80211_AC_VO
1442 };
1443
1444 static inline int
1445 il4965_get_ac_from_tid(u16 tid)
1446 {
1447 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1448 return tid_to_ac[tid];
1449
1450 /* no support for TIDs 8-15 yet */
1451 return -EINVAL;
1452 }
1453
1454 static inline int
1455 il4965_get_fifo_from_tid(u16 tid)
1456 {
1457 const u8 ac_to_fifo[] = {
1458 IL_TX_FIFO_VO,
1459 IL_TX_FIFO_VI,
1460 IL_TX_FIFO_BE,
1461 IL_TX_FIFO_BK,
1462 };
1463
1464 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
1465 return ac_to_fifo[tid_to_ac[tid]];
1466
1467 /* no support for TIDs 8-15 yet */
1468 return -EINVAL;
1469 }
1470
1471 /*
1472 * handle build C_TX command notification.
1473 */
1474 static void
1475 il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb,
1476 struct il_tx_cmd *tx_cmd,
1477 struct ieee80211_tx_info *info,
1478 struct ieee80211_hdr *hdr, u8 std_id)
1479 {
1480 __le16 fc = hdr->frame_control;
1481 __le32 tx_flags = tx_cmd->tx_flags;
1482
1483 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1484 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
1485 tx_flags |= TX_CMD_FLG_ACK_MSK;
1486 if (ieee80211_is_mgmt(fc))
1487 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1488 if (ieee80211_is_probe_resp(fc) &&
1489 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
1490 tx_flags |= TX_CMD_FLG_TSF_MSK;
1491 } else {
1492 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
1493 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1494 }
1495
1496 if (ieee80211_is_back_req(fc))
1497 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
1498
1499 tx_cmd->sta_id = std_id;
1500 if (ieee80211_has_morefrags(fc))
1501 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
1502
1503 if (ieee80211_is_data_qos(fc)) {
1504 u8 *qc = ieee80211_get_qos_ctl(hdr);
1505 tx_cmd->tid_tspec = qc[0] & 0xf;
1506 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
1507 } else {
1508 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
1509 }
1510
1511 il_tx_cmd_protection(il, info, fc, &tx_flags);
1512
1513 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
1514 if (ieee80211_is_mgmt(fc)) {
1515 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
1516 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
1517 else
1518 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
1519 } else {
1520 tx_cmd->timeout.pm_frame_timeout = 0;
1521 }
1522
1523 tx_cmd->driver_txop = 0;
1524 tx_cmd->tx_flags = tx_flags;
1525 tx_cmd->next_frame_len = 0;
1526 }
1527
1528 static void
1529 il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd,
1530 struct ieee80211_tx_info *info, __le16 fc)
1531 {
1532 const u8 rts_retry_limit = 60;
1533 u32 rate_flags;
1534 int rate_idx;
1535 u8 data_retry_limit;
1536 u8 rate_plcp;
1537
1538 /* Set retry limit on DATA packets and Probe Responses */
1539 if (ieee80211_is_probe_resp(fc))
1540 data_retry_limit = 3;
1541 else
1542 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
1543 tx_cmd->data_retry_limit = data_retry_limit;
1544 /* Set retry limit on RTS packets */
1545 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit);
1546
1547 /* DATA packets will use the uCode station table for rate/antenna
1548 * selection */
1549 if (ieee80211_is_data(fc)) {
1550 tx_cmd->initial_rate_idx = 0;
1551 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
1552 return;
1553 }
1554
1555 /**
1556 * If the current TX rate stored in mac80211 has the MCS bit set, it's
1557 * not really a TX rate. Thus, we use the lowest supported rate for
1558 * this band. Also use the lowest supported rate if the stored rate
1559 * idx is invalid.
1560 */
1561 rate_idx = info->control.rates[0].idx;
1562 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0
1563 || rate_idx > RATE_COUNT_LEGACY)
1564 rate_idx =
1565 rate_lowest_index(&il->bands[info->band],
1566 info->control.sta);
1567 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
1568 if (info->band == IEEE80211_BAND_5GHZ)
1569 rate_idx += IL_FIRST_OFDM_RATE;
1570 /* Get PLCP rate for tx_cmd->rate_n_flags */
1571 rate_plcp = il_rates[rate_idx].plcp;
1572 /* Zero out flags for this packet */
1573 rate_flags = 0;
1574
1575 /* Set CCK flag as needed */
1576 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
1577 rate_flags |= RATE_MCS_CCK_MSK;
1578
1579 /* Set up antennas */
1580 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
1581 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
1582
1583 /* Set the rate in the TX cmd */
1584 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags);
1585 }
1586
1587 static void
1588 il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
1589 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag,
1590 int sta_id)
1591 {
1592 struct ieee80211_key_conf *keyconf = info->control.hw_key;
1593
1594 switch (keyconf->cipher) {
1595 case WLAN_CIPHER_SUITE_CCMP:
1596 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
1597 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
1598 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1599 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
1600 D_TX("tx_cmd with AES hwcrypto\n");
1601 break;
1602
1603 case WLAN_CIPHER_SUITE_TKIP:
1604 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
1605 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
1606 D_TX("tx_cmd with tkip hwcrypto\n");
1607 break;
1608
1609 case WLAN_CIPHER_SUITE_WEP104:
1610 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
1611 /* fall through */
1612 case WLAN_CIPHER_SUITE_WEP40:
1613 tx_cmd->sec_ctl |=
1614 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) <<
1615 TX_CMD_SEC_SHIFT);
1616
1617 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
1618
1619 D_TX("Configuring packet for WEP encryption " "with key %d\n",
1620 keyconf->keyidx);
1621 break;
1622
1623 default:
1624 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
1625 break;
1626 }
1627 }
1628
1629 /*
1630 * start C_TX command process
1631 */
1632 int
1633 il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
1634 {
1635 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1636 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1637 struct ieee80211_sta *sta = info->control.sta;
1638 struct il_station_priv *sta_priv = NULL;
1639 struct il_tx_queue *txq;
1640 struct il_queue *q;
1641 struct il_device_cmd *out_cmd;
1642 struct il_cmd_meta *out_meta;
1643 struct il_tx_cmd *tx_cmd;
1644 int txq_id;
1645 dma_addr_t phys_addr;
1646 dma_addr_t txcmd_phys;
1647 dma_addr_t scratch_phys;
1648 u16 len, firstlen, secondlen;
1649 u16 seq_number = 0;
1650 __le16 fc;
1651 u8 hdr_len;
1652 u8 sta_id;
1653 u8 wait_write_ptr = 0;
1654 u8 tid = 0;
1655 u8 *qc = NULL;
1656 unsigned long flags;
1657 bool is_agg = false;
1658
1659 spin_lock_irqsave(&il->lock, flags);
1660 if (il_is_rfkill(il)) {
1661 D_DROP("Dropping - RF KILL\n");
1662 goto drop_unlock;
1663 }
1664
1665 fc = hdr->frame_control;
1666
1667 #ifdef CONFIG_IWLEGACY_DEBUG
1668 if (ieee80211_is_auth(fc))
1669 D_TX("Sending AUTH frame\n");
1670 else if (ieee80211_is_assoc_req(fc))
1671 D_TX("Sending ASSOC frame\n");
1672 else if (ieee80211_is_reassoc_req(fc))
1673 D_TX("Sending REASSOC frame\n");
1674 #endif
1675
1676 hdr_len = ieee80211_hdrlen(fc);
1677
1678 /* For management frames use broadcast id to do not break aggregation */
1679 if (!ieee80211_is_data(fc))
1680 sta_id = il->hw_params.bcast_id;
1681 else {
1682 /* Find idx into station table for destination station */
1683 sta_id = il_sta_id_or_broadcast(il, info->control.sta);
1684
1685 if (sta_id == IL_INVALID_STATION) {
1686 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
1687 goto drop_unlock;
1688 }
1689 }
1690
1691 D_TX("station Id %d\n", sta_id);
1692
1693 if (sta)
1694 sta_priv = (void *)sta->drv_priv;
1695
1696 if (sta_priv && sta_priv->asleep &&
1697 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
1698 /*
1699 * This sends an asynchronous command to the device,
1700 * but we can rely on it being processed before the
1701 * next frame is processed -- and the next frame to
1702 * this station is the one that will consume this
1703 * counter.
1704 * For now set the counter to just 1 since we do not
1705 * support uAPSD yet.
1706 */
1707 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
1708 }
1709
1710 /* FIXME: remove me ? */
1711 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM);
1712
1713 /* Access category (AC) is also the queue number */
1714 txq_id = skb_get_queue_mapping(skb);
1715
1716 /* irqs already disabled/saved above when locking il->lock */
1717 spin_lock(&il->sta_lock);
1718
1719 if (ieee80211_is_data_qos(fc)) {
1720 qc = ieee80211_get_qos_ctl(hdr);
1721 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1722 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
1723 spin_unlock(&il->sta_lock);
1724 goto drop_unlock;
1725 }
1726 seq_number = il->stations[sta_id].tid[tid].seq_number;
1727 seq_number &= IEEE80211_SCTL_SEQ;
1728 hdr->seq_ctrl =
1729 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG);
1730 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1731 seq_number += 0x10;
1732 /* aggregation is on for this <sta,tid> */
1733 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
1734 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
1735 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
1736 is_agg = true;
1737 }
1738 }
1739
1740 txq = &il->txq[txq_id];
1741 q = &txq->q;
1742
1743 if (unlikely(il_queue_space(q) < q->high_mark)) {
1744 spin_unlock(&il->sta_lock);
1745 goto drop_unlock;
1746 }
1747
1748 if (ieee80211_is_data_qos(fc)) {
1749 il->stations[sta_id].tid[tid].tfds_in_queue++;
1750 if (!ieee80211_has_morefrags(fc))
1751 il->stations[sta_id].tid[tid].seq_number = seq_number;
1752 }
1753
1754 spin_unlock(&il->sta_lock);
1755
1756 txq->skbs[q->write_ptr] = skb;
1757
1758 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1759 out_cmd = txq->cmd[q->write_ptr];
1760 out_meta = &txq->meta[q->write_ptr];
1761 tx_cmd = &out_cmd->cmd.tx;
1762 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
1763 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
1764
1765 /*
1766 * Set up the Tx-command (not MAC!) header.
1767 * Store the chosen Tx queue and TFD idx within the sequence field;
1768 * after Tx, uCode's Tx response will return this value so driver can
1769 * locate the frame within the tx queue and do post-tx processing.
1770 */
1771 out_cmd->hdr.cmd = C_TX;
1772 out_cmd->hdr.sequence =
1773 cpu_to_le16((u16)
1774 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
1775
1776 /* Copy MAC header from skb into command buffer */
1777 memcpy(tx_cmd->hdr, hdr, hdr_len);
1778
1779 /* Total # bytes to be transmitted */
1780 len = (u16) skb->len;
1781 tx_cmd->len = cpu_to_le16(len);
1782
1783 if (info->control.hw_key)
1784 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
1785
1786 /* TODO need this for burst mode later on */
1787 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
1788 il_dbg_log_tx_data_frame(il, len, hdr);
1789
1790 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
1791
1792 il_update_stats(il, true, fc, len);
1793 /*
1794 * Use the first empty entry in this queue's command buffer array
1795 * to contain the Tx command and MAC header concatenated together
1796 * (payload data will be in another buffer).
1797 * Size of this varies, due to varying MAC header length.
1798 * If end is not dword aligned, we'll have 2 extra bytes at the end
1799 * of the MAC header (device reads on dword boundaries).
1800 * We'll tell device about this padding later.
1801 */
1802 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len;
1803 firstlen = (len + 3) & ~3;
1804
1805 /* Tell NIC about any 2-byte padding after MAC header */
1806 if (firstlen != len)
1807 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1808
1809 /* Physical address of this Tx command's header (not MAC header!),
1810 * within command buffer array. */
1811 txcmd_phys =
1812 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
1813 PCI_DMA_BIDIRECTIONAL);
1814 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1815 dma_unmap_len_set(out_meta, len, firstlen);
1816 /* Add buffer containing Tx command and MAC(!) header to TFD's
1817 * first entry */
1818 il->ops->lib->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
1819
1820 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1821 txq->need_update = 1;
1822 } else {
1823 wait_write_ptr = 1;
1824 txq->need_update = 0;
1825 }
1826
1827 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1828 * if any (802.11 null frames have no payload). */
1829 secondlen = skb->len - hdr_len;
1830 if (secondlen > 0) {
1831 phys_addr =
1832 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
1833 PCI_DMA_TODEVICE);
1834 il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr,
1835 secondlen, 0, 0);
1836 }
1837
1838 scratch_phys =
1839 txcmd_phys + sizeof(struct il_cmd_header) +
1840 offsetof(struct il_tx_cmd, scratch);
1841
1842 /* take back ownership of DMA buffer to enable update */
1843 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen,
1844 PCI_DMA_BIDIRECTIONAL);
1845 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1846 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
1847
1848 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
1849 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1850 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd));
1851 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len);
1852
1853 /* Set up entry for this TFD in Tx byte-count array */
1854 if (info->flags & IEEE80211_TX_CTL_AMPDU)
1855 il->ops->lib->txq_update_byte_cnt_tbl(il, txq,
1856 le16_to_cpu(tx_cmd->len));
1857
1858 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen,
1859 PCI_DMA_BIDIRECTIONAL);
1860
1861 /* Tell device the write idx *just past* this latest filled TFD */
1862 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
1863 il_txq_update_write_ptr(il, txq);
1864 spin_unlock_irqrestore(&il->lock, flags);
1865
1866 /*
1867 * At this point the frame is "transmitted" successfully
1868 * and we will get a TX status notification eventually,
1869 * regardless of the value of ret. "ret" only indicates
1870 * whether or not we should update the write pointer.
1871 */
1872
1873 /*
1874 * Avoid atomic ops if it isn't an associated client.
1875 * Also, if this is a packet for aggregation, don't
1876 * increase the counter because the ucode will stop
1877 * aggregation queues when their respective station
1878 * goes to sleep.
1879 */
1880 if (sta_priv && sta_priv->client && !is_agg)
1881 atomic_inc(&sta_priv->pending_frames);
1882
1883 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
1884 if (wait_write_ptr) {
1885 spin_lock_irqsave(&il->lock, flags);
1886 txq->need_update = 1;
1887 il_txq_update_write_ptr(il, txq);
1888 spin_unlock_irqrestore(&il->lock, flags);
1889 } else {
1890 il_stop_queue(il, txq);
1891 }
1892 }
1893
1894 return 0;
1895
1896 drop_unlock:
1897 spin_unlock_irqrestore(&il->lock, flags);
1898 return -1;
1899 }
1900
1901 static inline int
1902 il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size)
1903 {
1904 ptr->addr =
1905 dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL);
1906 if (!ptr->addr)
1907 return -ENOMEM;
1908 ptr->size = size;
1909 return 0;
1910 }
1911
1912 static inline void
1913 il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr)
1914 {
1915 if (unlikely(!ptr->addr))
1916 return;
1917
1918 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
1919 memset(ptr, 0, sizeof(*ptr));
1920 }
1921
1922 /**
1923 * il4965_hw_txq_ctx_free - Free TXQ Context
1924 *
1925 * Destroy all TX DMA queues and structures
1926 */
1927 void
1928 il4965_hw_txq_ctx_free(struct il_priv *il)
1929 {
1930 int txq_id;
1931
1932 /* Tx queues */
1933 if (il->txq) {
1934 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
1935 if (txq_id == il->cmd_queue)
1936 il_cmd_queue_free(il);
1937 else
1938 il_tx_queue_free(il, txq_id);
1939 }
1940 il4965_free_dma_ptr(il, &il->kw);
1941
1942 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
1943
1944 /* free tx queue structure */
1945 il_txq_mem(il);
1946 }
1947
1948 /**
1949 * il4965_txq_ctx_alloc - allocate TX queue context
1950 * Allocate all Tx DMA structures and initialize them
1951 *
1952 * @param il
1953 * @return error code
1954 */
1955 int
1956 il4965_txq_ctx_alloc(struct il_priv *il)
1957 {
1958 int ret;
1959 int txq_id, slots_num;
1960 unsigned long flags;
1961
1962 /* Free all tx/cmd queues and keep-warm buffer */
1963 il4965_hw_txq_ctx_free(il);
1964
1965 ret =
1966 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
1967 il->hw_params.scd_bc_tbls_size);
1968 if (ret) {
1969 IL_ERR("Scheduler BC Table allocation failed\n");
1970 goto error_bc_tbls;
1971 }
1972 /* Alloc keep-warm buffer */
1973 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
1974 if (ret) {
1975 IL_ERR("Keep Warm allocation failed\n");
1976 goto error_kw;
1977 }
1978
1979 /* allocate tx queue structure */
1980 ret = il_alloc_txq_mem(il);
1981 if (ret)
1982 goto error;
1983
1984 spin_lock_irqsave(&il->lock, flags);
1985
1986 /* Turn off all Tx DMA fifos */
1987 il4965_txq_set_sched(il, 0);
1988
1989 /* Tell NIC where to find the "keep warm" buffer */
1990 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
1991
1992 spin_unlock_irqrestore(&il->lock, flags);
1993
1994 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1995 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
1996 slots_num =
1997 (txq_id ==
1998 il->cmd_queue) ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1999 ret = il_tx_queue_init(il, &il->txq[txq_id], slots_num, txq_id);
2000 if (ret) {
2001 IL_ERR("Tx %d queue init failed\n", txq_id);
2002 goto error;
2003 }
2004 }
2005
2006 return ret;
2007
2008 error:
2009 il4965_hw_txq_ctx_free(il);
2010 il4965_free_dma_ptr(il, &il->kw);
2011 error_kw:
2012 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
2013 error_bc_tbls:
2014 return ret;
2015 }
2016
2017 void
2018 il4965_txq_ctx_reset(struct il_priv *il)
2019 {
2020 int txq_id, slots_num;
2021 unsigned long flags;
2022
2023 spin_lock_irqsave(&il->lock, flags);
2024
2025 /* Turn off all Tx DMA fifos */
2026 il4965_txq_set_sched(il, 0);
2027
2028 /* Tell NIC where to find the "keep warm" buffer */
2029 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);
2030
2031 spin_unlock_irqrestore(&il->lock, flags);
2032
2033 /* Alloc and init all Tx queues, including the command queue (#4) */
2034 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
2035 slots_num =
2036 txq_id == il->cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
2037 il_tx_queue_reset(il, &il->txq[txq_id], slots_num, txq_id);
2038 }
2039 }
2040
2041 /**
2042 * il4965_txq_ctx_stop - Stop all Tx DMA channels
2043 */
2044 void
2045 il4965_txq_ctx_stop(struct il_priv *il)
2046 {
2047 int ch, txq_id;
2048 unsigned long flags;
2049
2050 /* Turn off all Tx DMA fifos */
2051 spin_lock_irqsave(&il->lock, flags);
2052
2053 il4965_txq_set_sched(il, 0);
2054
2055 /* Stop each Tx DMA channel, and wait for it to be idle */
2056 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
2057 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
2058 if (il_poll_bit
2059 (il, FH49_TSSR_TX_STATUS_REG,
2060 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000))
2061 IL_ERR("Failing on timeout while stopping"
2062 " DMA channel %d [0x%08x]", ch,
2063 il_rd(il, FH49_TSSR_TX_STATUS_REG));
2064 }
2065 spin_unlock_irqrestore(&il->lock, flags);
2066
2067 if (!il->txq)
2068 return;
2069
2070 /* Unmap DMA from host system and free skb's */
2071 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2072 if (txq_id == il->cmd_queue)
2073 il_cmd_queue_unmap(il);
2074 else
2075 il_tx_queue_unmap(il, txq_id);
2076 }
2077
2078 /*
2079 * Find first available (lowest unused) Tx Queue, mark it "active".
2080 * Called only when finding queue for aggregation.
2081 * Should never return anything < 7, because they should already
2082 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
2083 */
2084 static int
2085 il4965_txq_ctx_activate_free(struct il_priv *il)
2086 {
2087 int txq_id;
2088
2089 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
2090 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
2091 return txq_id;
2092 return -1;
2093 }
2094
2095 /**
2096 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2097 */
2098 static void
2099 il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id)
2100 {
2101 /* Simply stop the queue, but don't change any configuration;
2102 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
2103 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
2104 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
2105 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
2106 }
2107
2108 /**
2109 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2110 */
2111 static int
2112 il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id)
2113 {
2114 u32 tbl_dw_addr;
2115 u32 tbl_dw;
2116 u16 scd_q2ratid;
2117
2118 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
2119
2120 tbl_dw_addr =
2121 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
2122
2123 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
2124
2125 if (txq_id & 0x1)
2126 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2127 else
2128 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2129
2130 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
2131
2132 return 0;
2133 }
2134
2135 /**
2136 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2137 *
2138 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
2139 * i.e. it must be one of the higher queues used for aggregation
2140 */
2141 static int
2142 il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id,
2143 int tid, u16 ssn_idx)
2144 {
2145 unsigned long flags;
2146 u16 ra_tid;
2147 int ret;
2148
2149 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2150 (IL49_FIRST_AMPDU_QUEUE +
2151 il->cfg->num_of_ampdu_queues <= txq_id)) {
2152 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2153 txq_id, IL49_FIRST_AMPDU_QUEUE,
2154 IL49_FIRST_AMPDU_QUEUE +
2155 il->cfg->num_of_ampdu_queues - 1);
2156 return -EINVAL;
2157 }
2158
2159 ra_tid = BUILD_RAxTID(sta_id, tid);
2160
2161 /* Modify device's station table to Tx this TID */
2162 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
2163 if (ret)
2164 return ret;
2165
2166 spin_lock_irqsave(&il->lock, flags);
2167
2168 /* Stop this Tx queue before configuring it */
2169 il4965_tx_queue_stop_scheduler(il, txq_id);
2170
2171 /* Map receiver-address / traffic-ID to this queue */
2172 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
2173
2174 /* Set this queue as a chain-building queue */
2175 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2176
2177 /* Place first TFD at idx corresponding to start sequence number.
2178 * Assumes that ssn_idx is valid (!= 0xFFF) */
2179 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2180 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2181 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2182
2183 /* Set up Tx win size and frame limit for this queue */
2184 il_write_targ_mem(il,
2185 il->scd_base_addr +
2186 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2187 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS)
2188 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
2189
2190 il_write_targ_mem(il,
2191 il->scd_base_addr +
2192 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2193 (SCD_FRAME_LIMIT <<
2194 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
2195 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
2196
2197 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2198
2199 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
2200 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
2201
2202 spin_unlock_irqrestore(&il->lock, flags);
2203
2204 return 0;
2205 }
2206
2207 int
2208 il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
2209 struct ieee80211_sta *sta, u16 tid, u16 * ssn)
2210 {
2211 int sta_id;
2212 int tx_fifo;
2213 int txq_id;
2214 int ret;
2215 unsigned long flags;
2216 struct il_tid_data *tid_data;
2217
2218 /* FIXME: warning if tx fifo not found ? */
2219 tx_fifo = il4965_get_fifo_from_tid(tid);
2220 if (unlikely(tx_fifo < 0))
2221 return tx_fifo;
2222
2223 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid);
2224
2225 sta_id = il_sta_id(sta);
2226 if (sta_id == IL_INVALID_STATION) {
2227 IL_ERR("Start AGG on invalid station\n");
2228 return -ENXIO;
2229 }
2230 if (unlikely(tid >= MAX_TID_COUNT))
2231 return -EINVAL;
2232
2233 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
2234 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
2235 return -ENXIO;
2236 }
2237
2238 txq_id = il4965_txq_ctx_activate_free(il);
2239 if (txq_id == -1) {
2240 IL_ERR("No free aggregation queue available\n");
2241 return -ENXIO;
2242 }
2243
2244 spin_lock_irqsave(&il->sta_lock, flags);
2245 tid_data = &il->stations[sta_id].tid[tid];
2246 *ssn = SEQ_TO_SN(tid_data->seq_number);
2247 tid_data->agg.txq_id = txq_id;
2248 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id);
2249 spin_unlock_irqrestore(&il->sta_lock, flags);
2250
2251 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn);
2252 if (ret)
2253 return ret;
2254
2255 spin_lock_irqsave(&il->sta_lock, flags);
2256 tid_data = &il->stations[sta_id].tid[tid];
2257 if (tid_data->tfds_in_queue == 0) {
2258 D_HT("HW queue is empty\n");
2259 tid_data->agg.state = IL_AGG_ON;
2260 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2261 } else {
2262 D_HT("HW queue is NOT empty: %d packets in HW queue\n",
2263 tid_data->tfds_in_queue);
2264 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
2265 }
2266 spin_unlock_irqrestore(&il->sta_lock, flags);
2267 return ret;
2268 }
2269
2270 /**
2271 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
2272 * il->lock must be held by the caller
2273 */
2274 static int
2275 il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo)
2276 {
2277 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
2278 (IL49_FIRST_AMPDU_QUEUE +
2279 il->cfg->num_of_ampdu_queues <= txq_id)) {
2280 IL_WARN("queue number out of range: %d, must be %d to %d\n",
2281 txq_id, IL49_FIRST_AMPDU_QUEUE,
2282 IL49_FIRST_AMPDU_QUEUE +
2283 il->cfg->num_of_ampdu_queues - 1);
2284 return -EINVAL;
2285 }
2286
2287 il4965_tx_queue_stop_scheduler(il, txq_id);
2288
2289 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
2290
2291 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2292 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2293 /* supposes that ssn_idx is valid (!= 0xFFF) */
2294 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
2295
2296 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
2297 il_txq_ctx_deactivate(il, txq_id);
2298 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
2299
2300 return 0;
2301 }
2302
2303 int
2304 il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
2305 struct ieee80211_sta *sta, u16 tid)
2306 {
2307 int tx_fifo_id, txq_id, sta_id, ssn;
2308 struct il_tid_data *tid_data;
2309 int write_ptr, read_ptr;
2310 unsigned long flags;
2311
2312 /* FIXME: warning if tx_fifo_id not found ? */
2313 tx_fifo_id = il4965_get_fifo_from_tid(tid);
2314 if (unlikely(tx_fifo_id < 0))
2315 return tx_fifo_id;
2316
2317 sta_id = il_sta_id(sta);
2318
2319 if (sta_id == IL_INVALID_STATION) {
2320 IL_ERR("Invalid station for AGG tid %d\n", tid);
2321 return -ENXIO;
2322 }
2323
2324 spin_lock_irqsave(&il->sta_lock, flags);
2325
2326 tid_data = &il->stations[sta_id].tid[tid];
2327 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
2328 txq_id = tid_data->agg.txq_id;
2329
2330 switch (il->stations[sta_id].tid[tid].agg.state) {
2331 case IL_EMPTYING_HW_QUEUE_ADDBA:
2332 /*
2333 * This can happen if the peer stops aggregation
2334 * again before we've had a chance to drain the
2335 * queue we selected previously, i.e. before the
2336 * session was really started completely.
2337 */
2338 D_HT("AGG stop before setup done\n");
2339 goto turn_off;
2340 case IL_AGG_ON:
2341 break;
2342 default:
2343 IL_WARN("Stopping AGG while state not ON or starting\n");
2344 }
2345
2346 write_ptr = il->txq[txq_id].q.write_ptr;
2347 read_ptr = il->txq[txq_id].q.read_ptr;
2348
2349 /* The queue is not empty */
2350 if (write_ptr != read_ptr) {
2351 D_HT("Stopping a non empty AGG HW QUEUE\n");
2352 il->stations[sta_id].tid[tid].agg.state =
2353 IL_EMPTYING_HW_QUEUE_DELBA;
2354 spin_unlock_irqrestore(&il->sta_lock, flags);
2355 return 0;
2356 }
2357
2358 D_HT("HW queue is empty\n");
2359 turn_off:
2360 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
2361
2362 /* do not restore/save irqs */
2363 spin_unlock(&il->sta_lock);
2364 spin_lock(&il->lock);
2365
2366 /*
2367 * the only reason this call can fail is queue number out of range,
2368 * which can happen if uCode is reloaded and all the station
2369 * information are lost. if it is outside the range, there is no need
2370 * to deactivate the uCode queue, just return "success" to allow
2371 * mac80211 to clean up it own data.
2372 */
2373 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
2374 spin_unlock_irqrestore(&il->lock, flags);
2375
2376 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
2377
2378 return 0;
2379 }
2380
2381 int
2382 il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id)
2383 {
2384 struct il_queue *q = &il->txq[txq_id].q;
2385 u8 *addr = il->stations[sta_id].sta.sta.addr;
2386 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
2387
2388 lockdep_assert_held(&il->sta_lock);
2389
2390 switch (il->stations[sta_id].tid[tid].agg.state) {
2391 case IL_EMPTYING_HW_QUEUE_DELBA:
2392 /* We are reclaiming the last packet of the */
2393 /* aggregated HW queue */
2394 if (txq_id == tid_data->agg.txq_id &&
2395 q->read_ptr == q->write_ptr) {
2396 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
2397 int tx_fifo = il4965_get_fifo_from_tid(tid);
2398 D_HT("HW queue empty: continue DELBA flow\n");
2399 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
2400 tid_data->agg.state = IL_AGG_OFF;
2401 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid);
2402 }
2403 break;
2404 case IL_EMPTYING_HW_QUEUE_ADDBA:
2405 /* We are reclaiming the last packet of the queue */
2406 if (tid_data->tfds_in_queue == 0) {
2407 D_HT("HW queue empty: continue ADDBA flow\n");
2408 tid_data->agg.state = IL_AGG_ON;
2409 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid);
2410 }
2411 break;
2412 }
2413
2414 return 0;
2415 }
2416
2417 static void
2418 il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1)
2419 {
2420 struct ieee80211_sta *sta;
2421 struct il_station_priv *sta_priv;
2422
2423 rcu_read_lock();
2424 sta = ieee80211_find_sta(il->vif, addr1);
2425 if (sta) {
2426 sta_priv = (void *)sta->drv_priv;
2427 /* avoid atomic ops if this isn't a client */
2428 if (sta_priv->client &&
2429 atomic_dec_return(&sta_priv->pending_frames) == 0)
2430 ieee80211_sta_block_awake(il->hw, sta, false);
2431 }
2432 rcu_read_unlock();
2433 }
2434
2435 static void
2436 il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg)
2437 {
2438 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2439
2440 if (!is_agg)
2441 il4965_non_agg_tx_status(il, hdr->addr1);
2442
2443 ieee80211_tx_status_irqsafe(il->hw, skb);
2444 }
2445
2446 int
2447 il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
2448 {
2449 struct il_tx_queue *txq = &il->txq[txq_id];
2450 struct il_queue *q = &txq->q;
2451 int nfreed = 0;
2452 struct ieee80211_hdr *hdr;
2453 struct sk_buff *skb;
2454
2455 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
2456 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
2457 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
2458 q->write_ptr, q->read_ptr);
2459 return 0;
2460 }
2461
2462 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
2463 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
2464
2465 skb = txq->skbs[txq->q.read_ptr];
2466
2467 if (WARN_ON_ONCE(skb == NULL))
2468 continue;
2469
2470 hdr = (struct ieee80211_hdr *) skb->data;
2471 if (ieee80211_is_data_qos(hdr->frame_control))
2472 nfreed++;
2473
2474 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE);
2475
2476 txq->skbs[txq->q.read_ptr] = NULL;
2477 il->ops->lib->txq_free_tfd(il, txq);
2478 }
2479 return nfreed;
2480 }
2481
2482 /**
2483 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2484 *
2485 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2486 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2487 */
2488 static int
2489 il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg,
2490 struct il_compressed_ba_resp *ba_resp)
2491 {
2492 int i, sh, ack;
2493 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2494 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2495 int successes = 0;
2496 struct ieee80211_tx_info *info;
2497 u64 bitmap, sent_bitmap;
2498
2499 if (unlikely(!agg->wait_for_ba)) {
2500 if (unlikely(ba_resp->bitmap))
2501 IL_ERR("Received BA when not expected\n");
2502 return -EINVAL;
2503 }
2504
2505 /* Mark that the expected block-ack response arrived */
2506 agg->wait_for_ba = 0;
2507 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
2508
2509 /* Calculate shift to align block-ack bits with our Tx win bits */
2510 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
2511 if (sh < 0) /* tbw something is wrong with indices */
2512 sh += 0x100;
2513
2514 if (agg->frame_count > (64 - sh)) {
2515 D_TX_REPLY("more frames than bitmap size");
2516 return -1;
2517 }
2518
2519 /* don't use 64-bit values for now */
2520 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
2521
2522 /* check for success or failure according to the
2523 * transmitted bitmap and block-ack bitmap */
2524 sent_bitmap = bitmap & agg->bitmap;
2525
2526 /* For each frame attempted in aggregation,
2527 * update driver's record of tx frame's status. */
2528 i = 0;
2529 while (sent_bitmap) {
2530 ack = sent_bitmap & 1ULL;
2531 successes += ack;
2532 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK",
2533 i, (agg->start_idx + i) & 0xff, agg->start_idx + i);
2534 sent_bitmap >>= 1;
2535 ++i;
2536 }
2537
2538 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
2539
2540 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]);
2541 memset(&info->status, 0, sizeof(info->status));
2542 info->flags |= IEEE80211_TX_STAT_ACK;
2543 info->flags |= IEEE80211_TX_STAT_AMPDU;
2544 info->status.ampdu_ack_len = successes;
2545 info->status.ampdu_len = agg->frame_count;
2546 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
2547
2548 return 0;
2549 }
2550
2551 /**
2552 * translate ucode response to mac80211 tx status control values
2553 */
2554 void
2555 il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
2556 struct ieee80211_tx_info *info)
2557 {
2558 struct ieee80211_tx_rate *r = &info->control.rates[0];
2559
2560 info->antenna_sel_tx =
2561 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
2562 if (rate_n_flags & RATE_MCS_HT_MSK)
2563 r->flags |= IEEE80211_TX_RC_MCS;
2564 if (rate_n_flags & RATE_MCS_GF_MSK)
2565 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
2566 if (rate_n_flags & RATE_MCS_HT40_MSK)
2567 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
2568 if (rate_n_flags & RATE_MCS_DUP_MSK)
2569 r->flags |= IEEE80211_TX_RC_DUP_DATA;
2570 if (rate_n_flags & RATE_MCS_SGI_MSK)
2571 r->flags |= IEEE80211_TX_RC_SHORT_GI;
2572 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
2573 }
2574
2575 /**
2576 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA
2577 *
2578 * Handles block-acknowledge notification from device, which reports success
2579 * of frames sent via aggregation.
2580 */
2581 void
2582 il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb)
2583 {
2584 struct il_rx_pkt *pkt = rxb_addr(rxb);
2585 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
2586 struct il_tx_queue *txq = NULL;
2587 struct il_ht_agg *agg;
2588 int idx;
2589 int sta_id;
2590 int tid;
2591 unsigned long flags;
2592
2593 /* "flow" corresponds to Tx queue */
2594 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2595
2596 /* "ssn" is start of block-ack Tx win, corresponds to idx
2597 * (in Tx queue's circular buffer) of first TFD/frame in win */
2598 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2599
2600 if (scd_flow >= il->hw_params.max_txq_num) {
2601 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n");
2602 return;
2603 }
2604
2605 txq = &il->txq[scd_flow];
2606 sta_id = ba_resp->sta_id;
2607 tid = ba_resp->tid;
2608 agg = &il->stations[sta_id].tid[tid].agg;
2609 if (unlikely(agg->txq_id != scd_flow)) {
2610 /*
2611 * FIXME: this is a uCode bug which need to be addressed,
2612 * log the information and return for now!
2613 * since it is possible happen very often and in order
2614 * not to fill the syslog, don't enable the logging by default
2615 */
2616 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n",
2617 scd_flow, agg->txq_id);
2618 return;
2619 }
2620
2621 /* Find idx just before block-ack win */
2622 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
2623
2624 spin_lock_irqsave(&il->sta_lock, flags);
2625
2626 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n",
2627 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32,
2628 ba_resp->sta_id);
2629 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = "
2630 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl,
2631 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
2632 ba_resp->scd_flow, ba_resp->scd_ssn);
2633 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx,
2634 (unsigned long long)agg->bitmap);
2635
2636 /* Update driver's record of ACK vs. not for each frame in win */
2637 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
2638
2639 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2640 * block-ack win (we assume that they've been successfully
2641 * transmitted ... if not, it's too late anyway). */
2642 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
2643 /* calculate mac80211 ampdu sw queue to wake */
2644 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
2645 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
2646
2647 if (il_queue_space(&txq->q) > txq->q.low_mark &&
2648 il->mac80211_registered &&
2649 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
2650 il_wake_queue(il, txq);
2651
2652 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
2653 }
2654
2655 spin_unlock_irqrestore(&il->sta_lock, flags);
2656 }
2657
2658 #ifdef CONFIG_IWLEGACY_DEBUG
2659 const char *
2660 il4965_get_tx_fail_reason(u32 status)
2661 {
2662 #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
2663 #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
2664
2665 switch (status & TX_STATUS_MSK) {
2666 case TX_STATUS_SUCCESS:
2667 return "SUCCESS";
2668 TX_STATUS_POSTPONE(DELAY);
2669 TX_STATUS_POSTPONE(FEW_BYTES);
2670 TX_STATUS_POSTPONE(QUIET_PERIOD);
2671 TX_STATUS_POSTPONE(CALC_TTAK);
2672 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
2673 TX_STATUS_FAIL(SHORT_LIMIT);
2674 TX_STATUS_FAIL(LONG_LIMIT);
2675 TX_STATUS_FAIL(FIFO_UNDERRUN);
2676 TX_STATUS_FAIL(DRAIN_FLOW);
2677 TX_STATUS_FAIL(RFKILL_FLUSH);
2678 TX_STATUS_FAIL(LIFE_EXPIRE);
2679 TX_STATUS_FAIL(DEST_PS);
2680 TX_STATUS_FAIL(HOST_ABORTED);
2681 TX_STATUS_FAIL(BT_RETRY);
2682 TX_STATUS_FAIL(STA_INVALID);
2683 TX_STATUS_FAIL(FRAG_DROPPED);
2684 TX_STATUS_FAIL(TID_DISABLE);
2685 TX_STATUS_FAIL(FIFO_FLUSHED);
2686 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
2687 TX_STATUS_FAIL(PASSIVE_NO_RX);
2688 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
2689 }
2690
2691 return "UNKNOWN";
2692
2693 #undef TX_STATUS_FAIL
2694 #undef TX_STATUS_POSTPONE
2695 }
2696 #endif /* CONFIG_IWLEGACY_DEBUG */
2697
2698 static struct il_link_quality_cmd *
2699 il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
2700 {
2701 int i, r;
2702 struct il_link_quality_cmd *link_cmd;
2703 u32 rate_flags = 0;
2704 __le32 rate_n_flags;
2705
2706 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL);
2707 if (!link_cmd) {
2708 IL_ERR("Unable to allocate memory for LQ cmd.\n");
2709 return NULL;
2710 }
2711 /* Set up the rate scaling to start at selected rate, fall back
2712 * all the way down to 1M in IEEE order, and then spin on 1M */
2713 if (il->band == IEEE80211_BAND_5GHZ)
2714 r = RATE_6M_IDX;
2715 else
2716 r = RATE_1M_IDX;
2717
2718 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE)
2719 rate_flags |= RATE_MCS_CCK_MSK;
2720
2721 rate_flags |=
2722 il4965_first_antenna(il->hw_params.
2723 valid_tx_ant) << RATE_MCS_ANT_POS;
2724 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags);
2725 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2726 link_cmd->rs_table[i].rate_n_flags = rate_n_flags;
2727
2728 link_cmd->general_params.single_stream_ant_msk =
2729 il4965_first_antenna(il->hw_params.valid_tx_ant);
2730
2731 link_cmd->general_params.dual_stream_ant_msk =
2732 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params.
2733 valid_tx_ant);
2734 if (!link_cmd->general_params.dual_stream_ant_msk) {
2735 link_cmd->general_params.dual_stream_ant_msk = ANT_AB;
2736 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) {
2737 link_cmd->general_params.dual_stream_ant_msk =
2738 il->hw_params.valid_tx_ant;
2739 }
2740
2741 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF;
2742 link_cmd->agg_params.agg_time_limit =
2743 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF);
2744
2745 link_cmd->sta_id = sta_id;
2746
2747 return link_cmd;
2748 }
2749
2750 /*
2751 * il4965_add_bssid_station - Add the special IBSS BSSID station
2752 *
2753 * Function sleeps.
2754 */
2755 int
2756 il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r)
2757 {
2758 int ret;
2759 u8 sta_id;
2760 struct il_link_quality_cmd *link_cmd;
2761 unsigned long flags;
2762
2763 if (sta_id_r)
2764 *sta_id_r = IL_INVALID_STATION;
2765
2766 ret = il_add_station_common(il, addr, 0, NULL, &sta_id);
2767 if (ret) {
2768 IL_ERR("Unable to add station %pM\n", addr);
2769 return ret;
2770 }
2771
2772 if (sta_id_r)
2773 *sta_id_r = sta_id;
2774
2775 spin_lock_irqsave(&il->sta_lock, flags);
2776 il->stations[sta_id].used |= IL_STA_LOCAL;
2777 spin_unlock_irqrestore(&il->sta_lock, flags);
2778
2779 /* Set up default rate scaling table in device's station table */
2780 link_cmd = il4965_sta_alloc_lq(il, sta_id);
2781 if (!link_cmd) {
2782 IL_ERR("Unable to initialize rate scaling for station %pM.\n",
2783 addr);
2784 return -ENOMEM;
2785 }
2786
2787 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true);
2788 if (ret)
2789 IL_ERR("Link quality command failed (%d)\n", ret);
2790
2791 spin_lock_irqsave(&il->sta_lock, flags);
2792 il->stations[sta_id].lq = link_cmd;
2793 spin_unlock_irqrestore(&il->sta_lock, flags);
2794
2795 return 0;
2796 }
2797
2798 static int
2799 il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty)
2800 {
2801 int i;
2802 u8 buff[sizeof(struct il_wep_cmd) +
2803 sizeof(struct il_wep_key) * WEP_KEYS_MAX];
2804 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff;
2805 size_t cmd_size = sizeof(struct il_wep_cmd);
2806 struct il_host_cmd cmd = {
2807 .id = C_WEPKEY,
2808 .data = wep_cmd,
2809 .flags = CMD_SYNC,
2810 };
2811 bool not_empty = false;
2812
2813 might_sleep();
2814
2815 memset(wep_cmd, 0,
2816 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX));
2817
2818 for (i = 0; i < WEP_KEYS_MAX; i++) {
2819 u8 key_size = il->_4965.wep_keys[i].key_size;
2820
2821 wep_cmd->key[i].key_idx = i;
2822 if (key_size) {
2823 wep_cmd->key[i].key_offset = i;
2824 not_empty = true;
2825 } else
2826 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET;
2827
2828 wep_cmd->key[i].key_size = key_size;
2829 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size);
2830 }
2831
2832 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE;
2833 wep_cmd->num_keys = WEP_KEYS_MAX;
2834
2835 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX;
2836 cmd.len = cmd_size;
2837
2838 if (not_empty || send_if_empty)
2839 return il_send_cmd(il, &cmd);
2840 else
2841 return 0;
2842 }
2843
2844 int
2845 il4965_restore_default_wep_keys(struct il_priv *il)
2846 {
2847 lockdep_assert_held(&il->mutex);
2848
2849 return il4965_static_wepkey_cmd(il, false);
2850 }
2851
2852 int
2853 il4965_remove_default_wep_key(struct il_priv *il,
2854 struct ieee80211_key_conf *keyconf)
2855 {
2856 int ret;
2857 int idx = keyconf->keyidx;
2858
2859 lockdep_assert_held(&il->mutex);
2860
2861 D_WEP("Removing default WEP key: idx=%d\n", idx);
2862
2863 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key));
2864 if (il_is_rfkill(il)) {
2865 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n");
2866 /* but keys in device are clear anyway so return success */
2867 return 0;
2868 }
2869 ret = il4965_static_wepkey_cmd(il, 1);
2870 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret);
2871
2872 return ret;
2873 }
2874
2875 int
2876 il4965_set_default_wep_key(struct il_priv *il,
2877 struct ieee80211_key_conf *keyconf)
2878 {
2879 int ret;
2880 int len = keyconf->keylen;
2881 int idx = keyconf->keyidx;
2882
2883 lockdep_assert_held(&il->mutex);
2884
2885 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) {
2886 D_WEP("Bad WEP key length %d\n", keyconf->keylen);
2887 return -EINVAL;
2888 }
2889
2890 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2891 keyconf->hw_key_idx = HW_KEY_DEFAULT;
2892 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher;
2893
2894 il->_4965.wep_keys[idx].key_size = len;
2895 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len);
2896
2897 ret = il4965_static_wepkey_cmd(il, false);
2898
2899 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret);
2900 return ret;
2901 }
2902
2903 static int
2904 il4965_set_wep_dynamic_key_info(struct il_priv *il,
2905 struct ieee80211_key_conf *keyconf, u8 sta_id)
2906 {
2907 unsigned long flags;
2908 __le16 key_flags = 0;
2909 struct il_addsta_cmd sta_cmd;
2910
2911 lockdep_assert_held(&il->mutex);
2912
2913 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV;
2914
2915 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK);
2916 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2917 key_flags &= ~STA_KEY_FLG_INVALID;
2918
2919 if (keyconf->keylen == WEP_KEY_LEN_128)
2920 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
2921
2922 if (sta_id == il->hw_params.bcast_id)
2923 key_flags |= STA_KEY_MULTICAST_MSK;
2924
2925 spin_lock_irqsave(&il->sta_lock, flags);
2926
2927 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2928 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2929 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
2930
2931 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
2932
2933 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key,
2934 keyconf->keylen);
2935
2936 if ((il->stations[sta_id].sta.key.
2937 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
2938 il->stations[sta_id].sta.key.key_offset =
2939 il_get_free_ucode_key_idx(il);
2940 /* else, we are overriding an existing key => no need to allocated room
2941 * in uCode. */
2942
2943 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
2944 "no space for a new key");
2945
2946 il->stations[sta_id].sta.key.key_flags = key_flags;
2947 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2948 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2949
2950 memcpy(&sta_cmd, &il->stations[sta_id].sta,
2951 sizeof(struct il_addsta_cmd));
2952 spin_unlock_irqrestore(&il->sta_lock, flags);
2953
2954 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2955 }
2956
2957 static int
2958 il4965_set_ccmp_dynamic_key_info(struct il_priv *il,
2959 struct ieee80211_key_conf *keyconf, u8 sta_id)
2960 {
2961 unsigned long flags;
2962 __le16 key_flags = 0;
2963 struct il_addsta_cmd sta_cmd;
2964
2965 lockdep_assert_held(&il->mutex);
2966
2967 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
2968 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
2969 key_flags &= ~STA_KEY_FLG_INVALID;
2970
2971 if (sta_id == il->hw_params.bcast_id)
2972 key_flags |= STA_KEY_MULTICAST_MSK;
2973
2974 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2975
2976 spin_lock_irqsave(&il->sta_lock, flags);
2977 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
2978 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
2979
2980 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
2981
2982 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
2983
2984 if ((il->stations[sta_id].sta.key.
2985 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
2986 il->stations[sta_id].sta.key.key_offset =
2987 il_get_free_ucode_key_idx(il);
2988 /* else, we are overriding an existing key => no need to allocated room
2989 * in uCode. */
2990
2991 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
2992 "no space for a new key");
2993
2994 il->stations[sta_id].sta.key.key_flags = key_flags;
2995 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
2996 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2997
2998 memcpy(&sta_cmd, &il->stations[sta_id].sta,
2999 sizeof(struct il_addsta_cmd));
3000 spin_unlock_irqrestore(&il->sta_lock, flags);
3001
3002 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3003 }
3004
3005 static int
3006 il4965_set_tkip_dynamic_key_info(struct il_priv *il,
3007 struct ieee80211_key_conf *keyconf, u8 sta_id)
3008 {
3009 unsigned long flags;
3010 int ret = 0;
3011 __le16 key_flags = 0;
3012
3013 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK);
3014 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
3015 key_flags &= ~STA_KEY_FLG_INVALID;
3016
3017 if (sta_id == il->hw_params.bcast_id)
3018 key_flags |= STA_KEY_MULTICAST_MSK;
3019
3020 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3021 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3022
3023 spin_lock_irqsave(&il->sta_lock, flags);
3024
3025 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
3026 il->stations[sta_id].keyinfo.keylen = 16;
3027
3028 if ((il->stations[sta_id].sta.key.
3029 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
3030 il->stations[sta_id].sta.key.key_offset =
3031 il_get_free_ucode_key_idx(il);
3032 /* else, we are overriding an existing key => no need to allocated room
3033 * in uCode. */
3034
3035 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
3036 "no space for a new key");
3037
3038 il->stations[sta_id].sta.key.key_flags = key_flags;
3039
3040 /* This copy is acutally not needed: we get the key with each TX */
3041 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16);
3042
3043 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16);
3044
3045 spin_unlock_irqrestore(&il->sta_lock, flags);
3046
3047 return ret;
3048 }
3049
3050 void
3051 il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3052 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
3053 {
3054 u8 sta_id;
3055 unsigned long flags;
3056 int i;
3057
3058 if (il_scan_cancel(il)) {
3059 /* cancel scan failed, just live w/ bad key and rely
3060 briefly on SW decryption */
3061 return;
3062 }
3063
3064 sta_id = il_sta_id_or_broadcast(il, sta);
3065 if (sta_id == IL_INVALID_STATION)
3066 return;
3067
3068 spin_lock_irqsave(&il->sta_lock, flags);
3069
3070 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
3071
3072 for (i = 0; i < 5; i++)
3073 il->stations[sta_id].sta.key.tkip_rx_ttak[i] =
3074 cpu_to_le16(phase1key[i]);
3075
3076 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3077 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3078
3079 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3080
3081 spin_unlock_irqrestore(&il->sta_lock, flags);
3082 }
3083
3084 int
3085 il4965_remove_dynamic_key(struct il_priv *il,
3086 struct ieee80211_key_conf *keyconf, u8 sta_id)
3087 {
3088 unsigned long flags;
3089 u16 key_flags;
3090 u8 keyidx;
3091 struct il_addsta_cmd sta_cmd;
3092
3093 lockdep_assert_held(&il->mutex);
3094
3095 il->_4965.key_mapping_keys--;
3096
3097 spin_lock_irqsave(&il->sta_lock, flags);
3098 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags);
3099 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
3100
3101 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id);
3102
3103 if (keyconf->keyidx != keyidx) {
3104 /* We need to remove a key with idx different that the one
3105 * in the uCode. This means that the key we need to remove has
3106 * been replaced by another one with different idx.
3107 * Don't do anything and return ok
3108 */
3109 spin_unlock_irqrestore(&il->sta_lock, flags);
3110 return 0;
3111 }
3112
3113 if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
3114 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx,
3115 key_flags);
3116 spin_unlock_irqrestore(&il->sta_lock, flags);
3117 return 0;
3118 }
3119
3120 if (!test_and_clear_bit
3121 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table))
3122 IL_ERR("idx %d not used in uCode key table.\n",
3123 il->stations[sta_id].sta.key.key_offset);
3124 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
3125 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
3126 il->stations[sta_id].sta.key.key_flags =
3127 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
3128 il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
3129 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
3130 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3131
3132 if (il_is_rfkill(il)) {
3133 D_WEP
3134 ("Not sending C_ADD_STA command because RFKILL enabled.\n");
3135 spin_unlock_irqrestore(&il->sta_lock, flags);
3136 return 0;
3137 }
3138 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3139 sizeof(struct il_addsta_cmd));
3140 spin_unlock_irqrestore(&il->sta_lock, flags);
3141
3142 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3143 }
3144
3145 int
3146 il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
3147 u8 sta_id)
3148 {
3149 int ret;
3150
3151 lockdep_assert_held(&il->mutex);
3152
3153 il->_4965.key_mapping_keys++;
3154 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
3155
3156 switch (keyconf->cipher) {
3157 case WLAN_CIPHER_SUITE_CCMP:
3158 ret =
3159 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
3160 break;
3161 case WLAN_CIPHER_SUITE_TKIP:
3162 ret =
3163 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id);
3164 break;
3165 case WLAN_CIPHER_SUITE_WEP40:
3166 case WLAN_CIPHER_SUITE_WEP104:
3167 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id);
3168 break;
3169 default:
3170 IL_ERR("Unknown alg: %s cipher = %x\n", __func__,
3171 keyconf->cipher);
3172 ret = -EINVAL;
3173 }
3174
3175 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n",
3176 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
3177
3178 return ret;
3179 }
3180
3181 /**
3182 * il4965_alloc_bcast_station - add broadcast station into driver's station table.
3183 *
3184 * This adds the broadcast station into the driver's station table
3185 * and marks it driver active, so that it will be restored to the
3186 * device at the next best time.
3187 */
3188 int
3189 il4965_alloc_bcast_station(struct il_priv *il)
3190 {
3191 struct il_link_quality_cmd *link_cmd;
3192 unsigned long flags;
3193 u8 sta_id;
3194
3195 spin_lock_irqsave(&il->sta_lock, flags);
3196 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
3197 if (sta_id == IL_INVALID_STATION) {
3198 IL_ERR("Unable to prepare broadcast station\n");
3199 spin_unlock_irqrestore(&il->sta_lock, flags);
3200
3201 return -EINVAL;
3202 }
3203
3204 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
3205 il->stations[sta_id].used |= IL_STA_BCAST;
3206 spin_unlock_irqrestore(&il->sta_lock, flags);
3207
3208 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3209 if (!link_cmd) {
3210 IL_ERR
3211 ("Unable to initialize rate scaling for bcast station.\n");
3212 return -ENOMEM;
3213 }
3214
3215 spin_lock_irqsave(&il->sta_lock, flags);
3216 il->stations[sta_id].lq = link_cmd;
3217 spin_unlock_irqrestore(&il->sta_lock, flags);
3218
3219 return 0;
3220 }
3221
3222 /**
3223 * il4965_update_bcast_station - update broadcast station's LQ command
3224 *
3225 * Only used by iwl4965. Placed here to have all bcast station management
3226 * code together.
3227 */
3228 static int
3229 il4965_update_bcast_station(struct il_priv *il)
3230 {
3231 unsigned long flags;
3232 struct il_link_quality_cmd *link_cmd;
3233 u8 sta_id = il->hw_params.bcast_id;
3234
3235 link_cmd = il4965_sta_alloc_lq(il, sta_id);
3236 if (!link_cmd) {
3237 IL_ERR("Unable to initialize rate scaling for bcast sta.\n");
3238 return -ENOMEM;
3239 }
3240
3241 spin_lock_irqsave(&il->sta_lock, flags);
3242 if (il->stations[sta_id].lq)
3243 kfree(il->stations[sta_id].lq);
3244 else
3245 D_INFO("Bcast sta rate scaling has not been initialized.\n");
3246 il->stations[sta_id].lq = link_cmd;
3247 spin_unlock_irqrestore(&il->sta_lock, flags);
3248
3249 return 0;
3250 }
3251
3252 int
3253 il4965_update_bcast_stations(struct il_priv *il)
3254 {
3255 return il4965_update_bcast_station(il);
3256 }
3257
3258 /**
3259 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table
3260 */
3261 int
3262 il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid)
3263 {
3264 unsigned long flags;
3265 struct il_addsta_cmd sta_cmd;
3266
3267 lockdep_assert_held(&il->mutex);
3268
3269 /* Remove "disable" flag, to enable Tx for this TID */
3270 spin_lock_irqsave(&il->sta_lock, flags);
3271 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3272 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3273 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3274 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3275 sizeof(struct il_addsta_cmd));
3276 spin_unlock_irqrestore(&il->sta_lock, flags);
3277
3278 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3279 }
3280
3281 int
3282 il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid,
3283 u16 ssn)
3284 {
3285 unsigned long flags;
3286 int sta_id;
3287 struct il_addsta_cmd sta_cmd;
3288
3289 lockdep_assert_held(&il->mutex);
3290
3291 sta_id = il_sta_id(sta);
3292 if (sta_id == IL_INVALID_STATION)
3293 return -ENXIO;
3294
3295 spin_lock_irqsave(&il->sta_lock, flags);
3296 il->stations[sta_id].sta.station_flags_msk = 0;
3297 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3298 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid;
3299 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3300 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3301 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3302 sizeof(struct il_addsta_cmd));
3303 spin_unlock_irqrestore(&il->sta_lock, flags);
3304
3305 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3306 }
3307
3308 int
3309 il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid)
3310 {
3311 unsigned long flags;
3312 int sta_id;
3313 struct il_addsta_cmd sta_cmd;
3314
3315 lockdep_assert_held(&il->mutex);
3316
3317 sta_id = il_sta_id(sta);
3318 if (sta_id == IL_INVALID_STATION) {
3319 IL_ERR("Invalid station for AGG tid %d\n", tid);
3320 return -ENXIO;
3321 }
3322
3323 spin_lock_irqsave(&il->sta_lock, flags);
3324 il->stations[sta_id].sta.station_flags_msk = 0;
3325 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3326 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid;
3327 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3328 memcpy(&sta_cmd, &il->stations[sta_id].sta,
3329 sizeof(struct il_addsta_cmd));
3330 spin_unlock_irqrestore(&il->sta_lock, flags);
3331
3332 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
3333 }
3334
3335 void
3336 il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt)
3337 {
3338 unsigned long flags;
3339
3340 spin_lock_irqsave(&il->sta_lock, flags);
3341 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK;
3342 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3343 il->stations[sta_id].sta.sta.modify_mask =
3344 STA_MODIFY_SLEEP_TX_COUNT_MSK;
3345 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt);
3346 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3347 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
3348 spin_unlock_irqrestore(&il->sta_lock, flags);
3349
3350 }
3351
3352 void
3353 il4965_update_chain_flags(struct il_priv *il)
3354 {
3355 if (il->ops->hcmd->set_rxon_chain) {
3356 il->ops->hcmd->set_rxon_chain(il);
3357 if (il->active.rx_chain != il->staging.rx_chain)
3358 il_commit_rxon(il);
3359 }
3360 }
3361
3362 static void
3363 il4965_clear_free_frames(struct il_priv *il)
3364 {
3365 struct list_head *element;
3366
3367 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
3368
3369 while (!list_empty(&il->free_frames)) {
3370 element = il->free_frames.next;
3371 list_del(element);
3372 kfree(list_entry(element, struct il_frame, list));
3373 il->frames_count--;
3374 }
3375
3376 if (il->frames_count) {
3377 IL_WARN("%d frames still in use. Did we lose one?\n",
3378 il->frames_count);
3379 il->frames_count = 0;
3380 }
3381 }
3382
3383 static struct il_frame *
3384 il4965_get_free_frame(struct il_priv *il)
3385 {
3386 struct il_frame *frame;
3387 struct list_head *element;
3388 if (list_empty(&il->free_frames)) {
3389 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
3390 if (!frame) {
3391 IL_ERR("Could not allocate frame!\n");
3392 return NULL;
3393 }
3394
3395 il->frames_count++;
3396 return frame;
3397 }
3398
3399 element = il->free_frames.next;
3400 list_del(element);
3401 return list_entry(element, struct il_frame, list);
3402 }
3403
3404 static void
3405 il4965_free_frame(struct il_priv *il, struct il_frame *frame)
3406 {
3407 memset(frame, 0, sizeof(*frame));
3408 list_add(&frame->list, &il->free_frames);
3409 }
3410
3411 static u32
3412 il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
3413 int left)
3414 {
3415 lockdep_assert_held(&il->mutex);
3416
3417 if (!il->beacon_skb)
3418 return 0;
3419
3420 if (il->beacon_skb->len > left)
3421 return 0;
3422
3423 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
3424
3425 return il->beacon_skb->len;
3426 }
3427
3428 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
3429 static void
3430 il4965_set_beacon_tim(struct il_priv *il,
3431 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon,
3432 u32 frame_size)
3433 {
3434 u16 tim_idx;
3435 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
3436
3437 /*
3438 * The idx is relative to frame start but we start looking at the
3439 * variable-length part of the beacon.
3440 */
3441 tim_idx = mgmt->u.beacon.variable - beacon;
3442
3443 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
3444 while ((tim_idx < (frame_size - 2)) &&
3445 (beacon[tim_idx] != WLAN_EID_TIM))
3446 tim_idx += beacon[tim_idx + 1] + 2;
3447
3448 /* If TIM field was found, set variables */
3449 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
3450 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
3451 tx_beacon_cmd->tim_size = beacon[tim_idx + 1];
3452 } else
3453 IL_WARN("Unable to find TIM Element in beacon\n");
3454 }
3455
3456 static unsigned int
3457 il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame)
3458 {
3459 struct il_tx_beacon_cmd *tx_beacon_cmd;
3460 u32 frame_size;
3461 u32 rate_flags;
3462 u32 rate;
3463 /*
3464 * We have to set up the TX command, the TX Beacon command, and the
3465 * beacon contents.
3466 */
3467
3468 lockdep_assert_held(&il->mutex);
3469
3470 if (!il->beacon_enabled) {
3471 IL_ERR("Trying to build beacon without beaconing enabled\n");
3472 return 0;
3473 }
3474
3475 /* Initialize memory */
3476 tx_beacon_cmd = &frame->u.beacon;
3477 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3478
3479 /* Set up TX beacon contents */
3480 frame_size =
3481 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame,
3482 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3483 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
3484 return 0;
3485 if (!frame_size)
3486 return 0;
3487
3488 /* Set up TX command fields */
3489 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size);
3490 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id;
3491 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3492 tx_beacon_cmd->tx.tx_flags =
3493 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK |
3494 TX_CMD_FLG_STA_RATE_MSK;
3495
3496 /* Set up TX beacon command fields */
3497 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame,
3498 frame_size);
3499
3500 /* Set up packet rate and flags */
3501 rate = il_get_lowest_plcp(il);
3502 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant);
3503 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS;
3504 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE))
3505 rate_flags |= RATE_MCS_CCK_MSK;
3506 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags);
3507
3508 return sizeof(*tx_beacon_cmd) + frame_size;
3509 }
3510
3511 int
3512 il4965_send_beacon_cmd(struct il_priv *il)
3513 {
3514 struct il_frame *frame;
3515 unsigned int frame_size;
3516 int rc;
3517
3518 frame = il4965_get_free_frame(il);
3519 if (!frame) {
3520 IL_ERR("Could not obtain free frame buffer for beacon "
3521 "command.\n");
3522 return -ENOMEM;
3523 }
3524
3525 frame_size = il4965_hw_get_beacon_cmd(il, frame);
3526 if (!frame_size) {
3527 IL_ERR("Error configuring the beacon command\n");
3528 il4965_free_frame(il, frame);
3529 return -EINVAL;
3530 }
3531
3532 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
3533
3534 il4965_free_frame(il, frame);
3535
3536 return rc;
3537 }
3538
3539 static inline dma_addr_t
3540 il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx)
3541 {
3542 struct il_tfd_tb *tb = &tfd->tbs[idx];
3543
3544 dma_addr_t addr = get_unaligned_le32(&tb->lo);
3545 if (sizeof(dma_addr_t) > sizeof(u32))
3546 addr |=
3547 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) <<
3548 16;
3549
3550 return addr;
3551 }
3552
3553 static inline u16
3554 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx)
3555 {
3556 struct il_tfd_tb *tb = &tfd->tbs[idx];
3557
3558 return le16_to_cpu(tb->hi_n_len) >> 4;
3559 }
3560
3561 static inline void
3562 il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len)
3563 {
3564 struct il_tfd_tb *tb = &tfd->tbs[idx];
3565 u16 hi_n_len = len << 4;
3566
3567 put_unaligned_le32(addr, &tb->lo);
3568 if (sizeof(dma_addr_t) > sizeof(u32))
3569 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
3570
3571 tb->hi_n_len = cpu_to_le16(hi_n_len);
3572
3573 tfd->num_tbs = idx + 1;
3574 }
3575
3576 static inline u8
3577 il4965_tfd_get_num_tbs(struct il_tfd *tfd)
3578 {
3579 return tfd->num_tbs & 0x1f;
3580 }
3581
3582 /**
3583 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
3584 * @il - driver ilate data
3585 * @txq - tx queue
3586 *
3587 * Does NOT advance any TFD circular buffer read/write idxes
3588 * Does NOT free the TFD itself (which is within circular buffer)
3589 */
3590 void
3591 il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq)
3592 {
3593 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds;
3594 struct il_tfd *tfd;
3595 struct pci_dev *dev = il->pci_dev;
3596 int idx = txq->q.read_ptr;
3597 int i;
3598 int num_tbs;
3599
3600 tfd = &tfd_tmp[idx];
3601
3602 /* Sanity check on number of chunks */
3603 num_tbs = il4965_tfd_get_num_tbs(tfd);
3604
3605 if (num_tbs >= IL_NUM_OF_TBS) {
3606 IL_ERR("Too many chunks: %i\n", num_tbs);
3607 /* @todo issue fatal error, it is quite serious situation */
3608 return;
3609 }
3610
3611 /* Unmap tx_cmd */
3612 if (num_tbs)
3613 pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping),
3614 dma_unmap_len(&txq->meta[idx], len),
3615 PCI_DMA_BIDIRECTIONAL);
3616
3617 /* Unmap chunks, if any. */
3618 for (i = 1; i < num_tbs; i++)
3619 pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i),
3620 il4965_tfd_tb_get_len(tfd, i),
3621 PCI_DMA_TODEVICE);
3622
3623 /* free SKB */
3624 if (txq->skbs) {
3625 struct sk_buff *skb = txq->skbs[txq->q.read_ptr];
3626
3627 /* can be called from irqs-disabled context */
3628 if (skb) {
3629 dev_kfree_skb_any(skb);
3630 txq->skbs[txq->q.read_ptr] = NULL;
3631 }
3632 }
3633 }
3634
3635 int
3636 il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
3637 dma_addr_t addr, u16 len, u8 reset, u8 pad)
3638 {
3639 struct il_queue *q;
3640 struct il_tfd *tfd, *tfd_tmp;
3641 u32 num_tbs;
3642
3643 q = &txq->q;
3644 tfd_tmp = (struct il_tfd *)txq->tfds;
3645 tfd = &tfd_tmp[q->write_ptr];
3646
3647 if (reset)
3648 memset(tfd, 0, sizeof(*tfd));
3649
3650 num_tbs = il4965_tfd_get_num_tbs(tfd);
3651
3652 /* Each TFD can point to a maximum 20 Tx buffers */
3653 if (num_tbs >= IL_NUM_OF_TBS) {
3654 IL_ERR("Error can not send more than %d chunks\n",
3655 IL_NUM_OF_TBS);
3656 return -EINVAL;
3657 }
3658
3659 BUG_ON(addr & ~DMA_BIT_MASK(36));
3660 if (unlikely(addr & ~IL_TX_DMA_MASK))
3661 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr);
3662
3663 il4965_tfd_set_tb(tfd, num_tbs, addr, len);
3664
3665 return 0;
3666 }
3667
3668 /*
3669 * Tell nic where to find circular buffer of Tx Frame Descriptors for
3670 * given Tx queue, and enable the DMA channel used for that queue.
3671 *
3672 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3673 * channels supported in hardware.
3674 */
3675 int
3676 il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq)
3677 {
3678 int txq_id = txq->q.id;
3679
3680 /* Circular buffer (TFD queue in DRAM) physical base address */
3681 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);
3682
3683 return 0;
3684 }
3685
3686 /******************************************************************************
3687 *
3688 * Generic RX handler implementations
3689 *
3690 ******************************************************************************/
3691 static void
3692 il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
3693 {
3694 struct il_rx_pkt *pkt = rxb_addr(rxb);
3695 struct il_alive_resp *palive;
3696 struct delayed_work *pwork;
3697
3698 palive = &pkt->u.alive_frame;
3699
3700 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
3701 palive->is_valid, palive->ver_type, palive->ver_subtype);
3702
3703 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
3704 D_INFO("Initialization Alive received.\n");
3705 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
3706 sizeof(struct il_init_alive_resp));
3707 pwork = &il->init_alive_start;
3708 } else {
3709 D_INFO("Runtime Alive received.\n");
3710 memcpy(&il->card_alive, &pkt->u.alive_frame,
3711 sizeof(struct il_alive_resp));
3712 pwork = &il->alive_start;
3713 }
3714
3715 /* We delay the ALIVE response by 5ms to
3716 * give the HW RF Kill time to activate... */
3717 if (palive->is_valid == UCODE_VALID_OK)
3718 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
3719 else
3720 IL_WARN("uCode did not respond OK.\n");
3721 }
3722
3723 /**
3724 * il4965_bg_stats_periodic - Timer callback to queue stats
3725 *
3726 * This callback is provided in order to send a stats request.
3727 *
3728 * This timer function is continually reset to execute within
3729 * REG_RECALIB_PERIOD seconds since the last N_STATS
3730 * was received. We need to ensure we receive the stats in order
3731 * to update the temperature used for calibrating the TXPOWER.
3732 */
3733 static void
3734 il4965_bg_stats_periodic(unsigned long data)
3735 {
3736 struct il_priv *il = (struct il_priv *)data;
3737
3738 if (test_bit(S_EXIT_PENDING, &il->status))
3739 return;
3740
3741 /* dont send host command if rf-kill is on */
3742 if (!il_is_ready_rf(il))
3743 return;
3744
3745 il_send_stats_request(il, CMD_ASYNC, false);
3746 }
3747
3748 static void
3749 il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
3750 {
3751 struct il_rx_pkt *pkt = rxb_addr(rxb);
3752 struct il4965_beacon_notif *beacon =
3753 (struct il4965_beacon_notif *)pkt->u.raw;
3754 #ifdef CONFIG_IWLEGACY_DEBUG
3755 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
3756
3757 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n",
3758 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
3759 beacon->beacon_notify_hdr.failure_frame,
3760 le32_to_cpu(beacon->ibss_mgr_status),
3761 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
3762 #endif
3763 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
3764 }
3765
3766 static void
3767 il4965_perform_ct_kill_task(struct il_priv *il)
3768 {
3769 unsigned long flags;
3770
3771 D_POWER("Stop all queues\n");
3772
3773 if (il->mac80211_registered)
3774 ieee80211_stop_queues(il->hw);
3775
3776 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
3777 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3778 _il_rd(il, CSR_UCODE_DRV_GP1);
3779
3780 spin_lock_irqsave(&il->reg_lock, flags);
3781 if (!_il_grab_nic_access(il))
3782 _il_release_nic_access(il);
3783 spin_unlock_irqrestore(&il->reg_lock, flags);
3784 }
3785
3786 /* Handle notification from uCode that card's power state is changing
3787 * due to software, hardware, or critical temperature RFKILL */
3788 static void
3789 il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
3790 {
3791 struct il_rx_pkt *pkt = rxb_addr(rxb);
3792 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
3793 unsigned long status = il->status;
3794
3795 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n",
3796 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3797 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
3798 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached");
3799
3800 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) {
3801
3802 _il_wr(il, CSR_UCODE_DRV_GP1_SET,
3803 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3804
3805 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3806
3807 if (!(flags & RXON_CARD_DISABLED)) {
3808 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
3809 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3810 il_wr(il, HBUS_TARG_MBX_C,
3811 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
3812 }
3813 }
3814
3815 if (flags & CT_CARD_DISABLED)
3816 il4965_perform_ct_kill_task(il);
3817
3818 if (flags & HW_CARD_DISABLED)
3819 set_bit(S_RF_KILL_HW, &il->status);
3820 else
3821 clear_bit(S_RF_KILL_HW, &il->status);
3822
3823 if (!(flags & RXON_CARD_DISABLED))
3824 il_scan_cancel(il);
3825
3826 if ((test_bit(S_RF_KILL_HW, &status) !=
3827 test_bit(S_RF_KILL_HW, &il->status)))
3828 wiphy_rfkill_set_hw_state(il->hw->wiphy,
3829 test_bit(S_RF_KILL_HW, &il->status));
3830 else
3831 wake_up(&il->wait_command_queue);
3832 }
3833
3834 /**
3835 * il4965_setup_handlers - Initialize Rx handler callbacks
3836 *
3837 * Setup the RX handlers for each of the reply types sent from the uCode
3838 * to the host.
3839 *
3840 * This function chains into the hardware specific files for them to setup
3841 * any hardware specific handlers as well.
3842 */
3843 static void
3844 il4965_setup_handlers(struct il_priv *il)
3845 {
3846 il->handlers[N_ALIVE] = il4965_hdl_alive;
3847 il->handlers[N_ERROR] = il_hdl_error;
3848 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
3849 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
3850 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
3851 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
3852 il->handlers[N_BEACON] = il4965_hdl_beacon;
3853
3854 /*
3855 * The same handler is used for both the REPLY to a discrete
3856 * stats request from the host as well as for the periodic
3857 * stats notifications (after received beacons) from the uCode.
3858 */
3859 il->handlers[C_STATS] = il4965_hdl_c_stats;
3860 il->handlers[N_STATS] = il4965_hdl_stats;
3861
3862 il_setup_rx_scan_handlers(il);
3863
3864 /* status change handler */
3865 il->handlers[N_CARD_STATE] = il4965_hdl_card_state;
3866
3867 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon;
3868 /* Rx handlers */
3869 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy;
3870 il->handlers[N_RX_MPDU] = il4965_hdl_rx;
3871 /* block ack */
3872 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba;
3873 /* Set up hardware specific Rx handlers */
3874 il->ops->lib->handler_setup(il);
3875 }
3876
3877 /**
3878 * il4965_rx_handle - Main entry function for receiving responses from uCode
3879 *
3880 * Uses the il->handlers callback function array to invoke
3881 * the appropriate handlers, including command responses,
3882 * frame-received notifications, and other notifications.
3883 */
3884 void
3885 il4965_rx_handle(struct il_priv *il)
3886 {
3887 struct il_rx_buf *rxb;
3888 struct il_rx_pkt *pkt;
3889 struct il_rx_queue *rxq = &il->rxq;
3890 u32 r, i;
3891 int reclaim;
3892 unsigned long flags;
3893 u8 fill_rx = 0;
3894 u32 count = 8;
3895 int total_empty;
3896
3897 /* uCode's read idx (stored in shared DRAM) indicates the last Rx
3898 * buffer that the driver may process (last buffer filled by ucode). */
3899 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
3900 i = rxq->read;
3901
3902 /* Rx interrupt, but nothing sent from uCode */
3903 if (i == r)
3904 D_RX("r = %d, i = %d\n", r, i);
3905
3906 /* calculate total frames need to be restock after handling RX */
3907 total_empty = r - rxq->write_actual;
3908 if (total_empty < 0)
3909 total_empty += RX_QUEUE_SIZE;
3910
3911 if (total_empty > (RX_QUEUE_SIZE / 2))
3912 fill_rx = 1;
3913
3914 while (i != r) {
3915 int len;
3916
3917 rxb = rxq->queue[i];
3918
3919 /* If an RXB doesn't have a Rx queue slot associated with it,
3920 * then a bug has been introduced in the queue refilling
3921 * routines -- catch it here */
3922 BUG_ON(rxb == NULL);
3923
3924 rxq->queue[i] = NULL;
3925
3926 pci_unmap_page(il->pci_dev, rxb->page_dma,
3927 PAGE_SIZE << il->hw_params.rx_page_order,
3928 PCI_DMA_FROMDEVICE);
3929 pkt = rxb_addr(rxb);
3930
3931 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
3932 len += sizeof(u32); /* account for status word */
3933
3934 /* Reclaim a command buffer only if this packet is a response
3935 * to a (driver-originated) command.
3936 * If the packet (e.g. Rx frame) originated from uCode,
3937 * there is no command buffer to reclaim.
3938 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
3939 * but apparently a few don't get set; catch them here. */
3940 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
3941 (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) &&
3942 (pkt->hdr.cmd != N_RX_MPDU) &&
3943 (pkt->hdr.cmd != N_COMPRESSED_BA) &&
3944 (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX);
3945
3946 /* Based on type of command response or notification,
3947 * handle those that need handling via function in
3948 * handlers table. See il4965_setup_handlers() */
3949 if (il->handlers[pkt->hdr.cmd]) {
3950 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
3951 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3952 il->isr_stats.handlers[pkt->hdr.cmd]++;
3953 il->handlers[pkt->hdr.cmd] (il, rxb);
3954 } else {
3955 /* No handling needed */
3956 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
3957 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
3958 }
3959
3960 /*
3961 * XXX: After here, we should always check rxb->page
3962 * against NULL before touching it or its virtual
3963 * memory (pkt). Because some handler might have
3964 * already taken or freed the pages.
3965 */
3966
3967 if (reclaim) {
3968 /* Invoke any callbacks, transfer the buffer to caller,
3969 * and fire off the (possibly) blocking il_send_cmd()
3970 * as we reclaim the driver command queue */
3971 if (rxb->page)
3972 il_tx_cmd_complete(il, rxb);
3973 else
3974 IL_WARN("Claim null rxb?\n");
3975 }
3976
3977 /* Reuse the page if possible. For notification packets and
3978 * SKBs that fail to Rx correctly, add them back into the
3979 * rx_free list for reuse later. */
3980 spin_lock_irqsave(&rxq->lock, flags);
3981 if (rxb->page != NULL) {
3982 rxb->page_dma =
3983 pci_map_page(il->pci_dev, rxb->page, 0,
3984 PAGE_SIZE << il->hw_params.
3985 rx_page_order, PCI_DMA_FROMDEVICE);
3986 list_add_tail(&rxb->list, &rxq->rx_free);
3987 rxq->free_count++;
3988 } else
3989 list_add_tail(&rxb->list, &rxq->rx_used);
3990
3991 spin_unlock_irqrestore(&rxq->lock, flags);
3992
3993 i = (i + 1) & RX_QUEUE_MASK;
3994 /* If there are a lot of unused frames,
3995 * restock the Rx queue so ucode wont assert. */
3996 if (fill_rx) {
3997 count++;
3998 if (count >= 8) {
3999 rxq->read = i;
4000 il4965_rx_replenish_now(il);
4001 count = 0;
4002 }
4003 }
4004 }
4005
4006 /* Backtrack one entry */
4007 rxq->read = i;
4008 if (fill_rx)
4009 il4965_rx_replenish_now(il);
4010 else
4011 il4965_rx_queue_restock(il);
4012 }
4013
4014 /* call this function to flush any scheduled tasklet */
4015 static inline void
4016 il4965_synchronize_irq(struct il_priv *il)
4017 {
4018 /* wait to make sure we flush pending tasklet */
4019 synchronize_irq(il->pci_dev->irq);
4020 tasklet_kill(&il->irq_tasklet);
4021 }
4022
4023 static void
4024 il4965_irq_tasklet(struct il_priv *il)
4025 {
4026 u32 inta, handled = 0;
4027 u32 inta_fh;
4028 unsigned long flags;
4029 u32 i;
4030 #ifdef CONFIG_IWLEGACY_DEBUG
4031 u32 inta_mask;
4032 #endif
4033
4034 spin_lock_irqsave(&il->lock, flags);
4035
4036 /* Ack/clear/reset pending uCode interrupts.
4037 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
4038 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
4039 inta = _il_rd(il, CSR_INT);
4040 _il_wr(il, CSR_INT, inta);
4041
4042 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
4043 * Any new interrupts that happen after this, either while we're
4044 * in this tasklet, or later, will show up in next ISR/tasklet. */
4045 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4046 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
4047
4048 #ifdef CONFIG_IWLEGACY_DEBUG
4049 if (il_get_debug_level(il) & IL_DL_ISR) {
4050 /* just for debug */
4051 inta_mask = _il_rd(il, CSR_INT_MASK);
4052 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
4053 inta_mask, inta_fh);
4054 }
4055 #endif
4056
4057 spin_unlock_irqrestore(&il->lock, flags);
4058
4059 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
4060 * atomic, make sure that inta covers all the interrupts that
4061 * we've discovered, even if FH interrupt came in just after
4062 * reading CSR_INT. */
4063 if (inta_fh & CSR49_FH_INT_RX_MASK)
4064 inta |= CSR_INT_BIT_FH_RX;
4065 if (inta_fh & CSR49_FH_INT_TX_MASK)
4066 inta |= CSR_INT_BIT_FH_TX;
4067
4068 /* Now service all interrupt bits discovered above. */
4069 if (inta & CSR_INT_BIT_HW_ERR) {
4070 IL_ERR("Hardware error detected. Restarting.\n");
4071
4072 /* Tell the device to stop sending interrupts */
4073 il_disable_interrupts(il);
4074
4075 il->isr_stats.hw++;
4076 il_irq_handle_error(il);
4077
4078 handled |= CSR_INT_BIT_HW_ERR;
4079
4080 return;
4081 }
4082 #ifdef CONFIG_IWLEGACY_DEBUG
4083 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4084 /* NIC fires this, but we don't use it, redundant with WAKEUP */
4085 if (inta & CSR_INT_BIT_SCD) {
4086 D_ISR("Scheduler finished to transmit "
4087 "the frame/frames.\n");
4088 il->isr_stats.sch++;
4089 }
4090
4091 /* Alive notification via Rx interrupt will do the real work */
4092 if (inta & CSR_INT_BIT_ALIVE) {
4093 D_ISR("Alive interrupt\n");
4094 il->isr_stats.alive++;
4095 }
4096 }
4097 #endif
4098 /* Safely ignore these bits for debug checks below */
4099 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
4100
4101 /* HW RF KILL switch toggled */
4102 if (inta & CSR_INT_BIT_RF_KILL) {
4103 int hw_rf_kill = 0;
4104 if (!
4105 (_il_rd(il, CSR_GP_CNTRL) &
4106 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4107 hw_rf_kill = 1;
4108
4109 IL_WARN("RF_KILL bit toggled to %s.\n",
4110 hw_rf_kill ? "disable radio" : "enable radio");
4111
4112 il->isr_stats.rfkill++;
4113
4114 /* driver only loads ucode once setting the interface up.
4115 * the driver allows loading the ucode even if the radio
4116 * is killed. Hence update the killswitch state here. The
4117 * rfkill handler will care about restarting if needed.
4118 */
4119 if (!test_bit(S_ALIVE, &il->status)) {
4120 if (hw_rf_kill)
4121 set_bit(S_RF_KILL_HW, &il->status);
4122 else
4123 clear_bit(S_RF_KILL_HW, &il->status);
4124 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill);
4125 }
4126
4127 handled |= CSR_INT_BIT_RF_KILL;
4128 }
4129
4130 /* Chip got too hot and stopped itself */
4131 if (inta & CSR_INT_BIT_CT_KILL) {
4132 IL_ERR("Microcode CT kill error detected.\n");
4133 il->isr_stats.ctkill++;
4134 handled |= CSR_INT_BIT_CT_KILL;
4135 }
4136
4137 /* Error detected by uCode */
4138 if (inta & CSR_INT_BIT_SW_ERR) {
4139 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n",
4140 inta);
4141 il->isr_stats.sw++;
4142 il_irq_handle_error(il);
4143 handled |= CSR_INT_BIT_SW_ERR;
4144 }
4145
4146 /*
4147 * uCode wakes up after power-down sleep.
4148 * Tell device about any new tx or host commands enqueued,
4149 * and about any Rx buffers made available while asleep.
4150 */
4151 if (inta & CSR_INT_BIT_WAKEUP) {
4152 D_ISR("Wakeup interrupt\n");
4153 il_rx_queue_update_write_ptr(il, &il->rxq);
4154 for (i = 0; i < il->hw_params.max_txq_num; i++)
4155 il_txq_update_write_ptr(il, &il->txq[i]);
4156 il->isr_stats.wakeup++;
4157 handled |= CSR_INT_BIT_WAKEUP;
4158 }
4159
4160 /* All uCode command responses, including Tx command responses,
4161 * Rx "responses" (frame-received notification), and other
4162 * notifications from uCode come through here*/
4163 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
4164 il4965_rx_handle(il);
4165 il->isr_stats.rx++;
4166 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
4167 }
4168
4169 /* This "Tx" DMA channel is used only for loading uCode */
4170 if (inta & CSR_INT_BIT_FH_TX) {
4171 D_ISR("uCode load interrupt\n");
4172 il->isr_stats.tx++;
4173 handled |= CSR_INT_BIT_FH_TX;
4174 /* Wake up uCode load routine, now that load is complete */
4175 il->ucode_write_complete = 1;
4176 wake_up(&il->wait_command_queue);
4177 }
4178
4179 if (inta & ~handled) {
4180 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
4181 il->isr_stats.unhandled++;
4182 }
4183
4184 if (inta & ~(il->inta_mask)) {
4185 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
4186 inta & ~il->inta_mask);
4187 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh);
4188 }
4189
4190 /* Re-enable all interrupts */
4191 /* only Re-enable if disabled by irq */
4192 if (test_bit(S_INT_ENABLED, &il->status))
4193 il_enable_interrupts(il);
4194 /* Re-enable RF_KILL if it occurred */
4195 else if (handled & CSR_INT_BIT_RF_KILL)
4196 il_enable_rfkill_int(il);
4197
4198 #ifdef CONFIG_IWLEGACY_DEBUG
4199 if (il_get_debug_level(il) & (IL_DL_ISR)) {
4200 inta = _il_rd(il, CSR_INT);
4201 inta_mask = _il_rd(il, CSR_INT_MASK);
4202 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
4203 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
4204 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
4205 }
4206 #endif
4207 }
4208
4209 /*****************************************************************************
4210 *
4211 * sysfs attributes
4212 *
4213 *****************************************************************************/
4214
4215 #ifdef CONFIG_IWLEGACY_DEBUG
4216
4217 /*
4218 * The following adds a new attribute to the sysfs representation
4219 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
4220 * used for controlling the debug level.
4221 *
4222 * See the level definitions in iwl for details.
4223 *
4224 * The debug_level being managed using sysfs below is a per device debug
4225 * level that is used instead of the global debug level if it (the per
4226 * device debug level) is set.
4227 */
4228 static ssize_t
4229 il4965_show_debug_level(struct device *d, struct device_attribute *attr,
4230 char *buf)
4231 {
4232 struct il_priv *il = dev_get_drvdata(d);
4233 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
4234 }
4235
4236 static ssize_t
4237 il4965_store_debug_level(struct device *d, struct device_attribute *attr,
4238 const char *buf, size_t count)
4239 {
4240 struct il_priv *il = dev_get_drvdata(d);
4241 unsigned long val;
4242 int ret;
4243
4244 ret = strict_strtoul(buf, 0, &val);
4245 if (ret)
4246 IL_ERR("%s is not in hex or decimal form.\n", buf);
4247 else {
4248 il->debug_level = val;
4249 if (il_alloc_traffic_mem(il))
4250 IL_ERR("Not enough memory to generate traffic log\n");
4251 }
4252 return strnlen(buf, count);
4253 }
4254
4255 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level,
4256 il4965_store_debug_level);
4257
4258 #endif /* CONFIG_IWLEGACY_DEBUG */
4259
4260 static ssize_t
4261 il4965_show_temperature(struct device *d, struct device_attribute *attr,
4262 char *buf)
4263 {
4264 struct il_priv *il = dev_get_drvdata(d);
4265
4266 if (!il_is_alive(il))
4267 return -EAGAIN;
4268
4269 return sprintf(buf, "%d\n", il->temperature);
4270 }
4271
4272 static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL);
4273
4274 static ssize_t
4275 il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
4276 {
4277 struct il_priv *il = dev_get_drvdata(d);
4278
4279 if (!il_is_ready_rf(il))
4280 return sprintf(buf, "off\n");
4281 else
4282 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
4283 }
4284
4285 static ssize_t
4286 il4965_store_tx_power(struct device *d, struct device_attribute *attr,
4287 const char *buf, size_t count)
4288 {
4289 struct il_priv *il = dev_get_drvdata(d);
4290 unsigned long val;
4291 int ret;
4292
4293 ret = strict_strtoul(buf, 10, &val);
4294 if (ret)
4295 IL_INFO("%s is not in decimal form.\n", buf);
4296 else {
4297 ret = il_set_tx_power(il, val, false);
4298 if (ret)
4299 IL_ERR("failed setting tx power (0x%d).\n", ret);
4300 else
4301 ret = count;
4302 }
4303 return ret;
4304 }
4305
4306 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power,
4307 il4965_store_tx_power);
4308
4309 static struct attribute *il_sysfs_entries[] = {
4310 &dev_attr_temperature.attr,
4311 &dev_attr_tx_power.attr,
4312 #ifdef CONFIG_IWLEGACY_DEBUG
4313 &dev_attr_debug_level.attr,
4314 #endif
4315 NULL
4316 };
4317
4318 static struct attribute_group il_attribute_group = {
4319 .name = NULL, /* put in device directory */
4320 .attrs = il_sysfs_entries,
4321 };
4322
4323 /******************************************************************************
4324 *
4325 * uCode download functions
4326 *
4327 ******************************************************************************/
4328
4329 static void
4330 il4965_dealloc_ucode_pci(struct il_priv *il)
4331 {
4332 il_free_fw_desc(il->pci_dev, &il->ucode_code);
4333 il_free_fw_desc(il->pci_dev, &il->ucode_data);
4334 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
4335 il_free_fw_desc(il->pci_dev, &il->ucode_init);
4336 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
4337 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
4338 }
4339
4340 static void
4341 il4965_nic_start(struct il_priv *il)
4342 {
4343 /* Remove all resets to allow NIC to operate */
4344 _il_wr(il, CSR_RESET, 0);
4345 }
4346
4347 static void il4965_ucode_callback(const struct firmware *ucode_raw,
4348 void *context);
4349 static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length);
4350
4351 static int __must_check
4352 il4965_request_firmware(struct il_priv *il, bool first)
4353 {
4354 const char *name_pre = il->cfg->fw_name_pre;
4355 char tag[8];
4356
4357 if (first) {
4358 il->fw_idx = il->cfg->ucode_api_max;
4359 sprintf(tag, "%d", il->fw_idx);
4360 } else {
4361 il->fw_idx--;
4362 sprintf(tag, "%d", il->fw_idx);
4363 }
4364
4365 if (il->fw_idx < il->cfg->ucode_api_min) {
4366 IL_ERR("no suitable firmware found!\n");
4367 return -ENOENT;
4368 }
4369
4370 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
4371
4372 D_INFO("attempting to load firmware '%s'\n", il->firmware_name);
4373
4374 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name,
4375 &il->pci_dev->dev, GFP_KERNEL, il,
4376 il4965_ucode_callback);
4377 }
4378
4379 struct il4965_firmware_pieces {
4380 const void *inst, *data, *init, *init_data, *boot;
4381 size_t inst_size, data_size, init_size, init_data_size, boot_size;
4382 };
4383
4384 static int
4385 il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw,
4386 struct il4965_firmware_pieces *pieces)
4387 {
4388 struct il_ucode_header *ucode = (void *)ucode_raw->data;
4389 u32 api_ver, hdr_size;
4390 const u8 *src;
4391
4392 il->ucode_ver = le32_to_cpu(ucode->ver);
4393 api_ver = IL_UCODE_API(il->ucode_ver);
4394
4395 switch (api_ver) {
4396 default:
4397 case 0:
4398 case 1:
4399 case 2:
4400 hdr_size = 24;
4401 if (ucode_raw->size < hdr_size) {
4402 IL_ERR("File size too small!\n");
4403 return -EINVAL;
4404 }
4405 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
4406 pieces->data_size = le32_to_cpu(ucode->v1.data_size);
4407 pieces->init_size = le32_to_cpu(ucode->v1.init_size);
4408 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size);
4409 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
4410 src = ucode->v1.data;
4411 break;
4412 }
4413
4414 /* Verify size of file vs. image size info in file's header */
4415 if (ucode_raw->size !=
4416 hdr_size + pieces->inst_size + pieces->data_size +
4417 pieces->init_size + pieces->init_data_size + pieces->boot_size) {
4418
4419 IL_ERR("uCode file size %d does not match expected size\n",
4420 (int)ucode_raw->size);
4421 return -EINVAL;
4422 }
4423
4424 pieces->inst = src;
4425 src += pieces->inst_size;
4426 pieces->data = src;
4427 src += pieces->data_size;
4428 pieces->init = src;
4429 src += pieces->init_size;
4430 pieces->init_data = src;
4431 src += pieces->init_data_size;
4432 pieces->boot = src;
4433 src += pieces->boot_size;
4434
4435 return 0;
4436 }
4437
4438 /**
4439 * il4965_ucode_callback - callback when firmware was loaded
4440 *
4441 * If loaded successfully, copies the firmware into buffers
4442 * for the card to fetch (via DMA).
4443 */
4444 static void
4445 il4965_ucode_callback(const struct firmware *ucode_raw, void *context)
4446 {
4447 struct il_priv *il = context;
4448 struct il_ucode_header *ucode;
4449 int err;
4450 struct il4965_firmware_pieces pieces;
4451 const unsigned int api_max = il->cfg->ucode_api_max;
4452 const unsigned int api_min = il->cfg->ucode_api_min;
4453 u32 api_ver;
4454
4455 u32 max_probe_length = 200;
4456 u32 standard_phy_calibration_size =
4457 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
4458
4459 memset(&pieces, 0, sizeof(pieces));
4460
4461 if (!ucode_raw) {
4462 if (il->fw_idx <= il->cfg->ucode_api_max)
4463 IL_ERR("request for firmware file '%s' failed.\n",
4464 il->firmware_name);
4465 goto try_again;
4466 }
4467
4468 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name,
4469 ucode_raw->size);
4470
4471 /* Make sure that we got at least the API version number */
4472 if (ucode_raw->size < 4) {
4473 IL_ERR("File size way too small!\n");
4474 goto try_again;
4475 }
4476
4477 /* Data from ucode file: header followed by uCode images */
4478 ucode = (struct il_ucode_header *)ucode_raw->data;
4479
4480 err = il4965_load_firmware(il, ucode_raw, &pieces);
4481
4482 if (err)
4483 goto try_again;
4484
4485 api_ver = IL_UCODE_API(il->ucode_ver);
4486
4487 /*
4488 * api_ver should match the api version forming part of the
4489 * firmware filename ... but we don't check for that and only rely
4490 * on the API version read from firmware header from here on forward
4491 */
4492 if (api_ver < api_min || api_ver > api_max) {
4493 IL_ERR("Driver unable to support your firmware API. "
4494 "Driver supports v%u, firmware is v%u.\n", api_max,
4495 api_ver);
4496 goto try_again;
4497 }
4498
4499 if (api_ver != api_max)
4500 IL_ERR("Firmware has old API version. Expected v%u, "
4501 "got v%u. New firmware can be obtained "
4502 "from http://www.intellinuxwireless.org.\n", api_max,
4503 api_ver);
4504
4505 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
4506 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
4507 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
4508
4509 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
4510 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
4511 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
4512 IL_UCODE_SERIAL(il->ucode_ver));
4513
4514 /*
4515 * For any of the failures below (before allocating pci memory)
4516 * we will try to load a version with a smaller API -- maybe the
4517 * user just got a corrupted version of the latest API.
4518 */
4519
4520 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
4521 D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size);
4522 D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size);
4523 D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size);
4524 D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size);
4525 D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size);
4526
4527 /* Verify that uCode images will fit in card's SRAM */
4528 if (pieces.inst_size > il->hw_params.max_inst_size) {
4529 IL_ERR("uCode instr len %Zd too large to fit in\n",
4530 pieces.inst_size);
4531 goto try_again;
4532 }
4533
4534 if (pieces.data_size > il->hw_params.max_data_size) {
4535 IL_ERR("uCode data len %Zd too large to fit in\n",
4536 pieces.data_size);
4537 goto try_again;
4538 }
4539
4540 if (pieces.init_size > il->hw_params.max_inst_size) {
4541 IL_ERR("uCode init instr len %Zd too large to fit in\n",
4542 pieces.init_size);
4543 goto try_again;
4544 }
4545
4546 if (pieces.init_data_size > il->hw_params.max_data_size) {
4547 IL_ERR("uCode init data len %Zd too large to fit in\n",
4548 pieces.init_data_size);
4549 goto try_again;
4550 }
4551
4552 if (pieces.boot_size > il->hw_params.max_bsm_size) {
4553 IL_ERR("uCode boot instr len %Zd too large to fit in\n",
4554 pieces.boot_size);
4555 goto try_again;
4556 }
4557
4558 /* Allocate ucode buffers for card's bus-master loading ... */
4559
4560 /* Runtime instructions and 2 copies of data:
4561 * 1) unmodified from disk
4562 * 2) backup cache for save/restore during power-downs */
4563 il->ucode_code.len = pieces.inst_size;
4564 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
4565
4566 il->ucode_data.len = pieces.data_size;
4567 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
4568
4569 il->ucode_data_backup.len = pieces.data_size;
4570 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
4571
4572 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
4573 !il->ucode_data_backup.v_addr)
4574 goto err_pci_alloc;
4575
4576 /* Initialization instructions and data */
4577 if (pieces.init_size && pieces.init_data_size) {
4578 il->ucode_init.len = pieces.init_size;
4579 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
4580
4581 il->ucode_init_data.len = pieces.init_data_size;
4582 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
4583
4584 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
4585 goto err_pci_alloc;
4586 }
4587
4588 /* Bootstrap (instructions only, no data) */
4589 if (pieces.boot_size) {
4590 il->ucode_boot.len = pieces.boot_size;
4591 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
4592
4593 if (!il->ucode_boot.v_addr)
4594 goto err_pci_alloc;
4595 }
4596
4597 /* Now that we can no longer fail, copy information */
4598
4599 il->sta_key_max_num = STA_KEY_MAX_NUM;
4600
4601 /* Copy images into buffers for card's bus-master reads ... */
4602
4603 /* Runtime instructions (first block of data in file) */
4604 D_INFO("Copying (but not loading) uCode instr len %Zd\n",
4605 pieces.inst_size);
4606 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size);
4607
4608 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
4609 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
4610
4611 /*
4612 * Runtime data
4613 * NOTE: Copy into backup buffer will be done in il_up()
4614 */
4615 D_INFO("Copying (but not loading) uCode data len %Zd\n",
4616 pieces.data_size);
4617 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size);
4618 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
4619
4620 /* Initialization instructions */
4621 if (pieces.init_size) {
4622 D_INFO("Copying (but not loading) init instr len %Zd\n",
4623 pieces.init_size);
4624 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size);
4625 }
4626
4627 /* Initialization data */
4628 if (pieces.init_data_size) {
4629 D_INFO("Copying (but not loading) init data len %Zd\n",
4630 pieces.init_data_size);
4631 memcpy(il->ucode_init_data.v_addr, pieces.init_data,
4632 pieces.init_data_size);
4633 }
4634
4635 /* Bootstrap instructions */
4636 D_INFO("Copying (but not loading) boot instr len %Zd\n",
4637 pieces.boot_size);
4638 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
4639
4640 /*
4641 * figure out the offset of chain noise reset and gain commands
4642 * base on the size of standard phy calibration commands table size
4643 */
4644 il->_4965.phy_calib_chain_noise_reset_cmd =
4645 standard_phy_calibration_size;
4646 il->_4965.phy_calib_chain_noise_gain_cmd =
4647 standard_phy_calibration_size + 1;
4648
4649 /**************************************************
4650 * This is still part of probe() in a sense...
4651 *
4652 * 9. Setup and register with mac80211 and debugfs
4653 **************************************************/
4654 err = il4965_mac_setup_register(il, max_probe_length);
4655 if (err)
4656 goto out_unbind;
4657
4658 err = il_dbgfs_register(il, DRV_NAME);
4659 if (err)
4660 IL_ERR("failed to create debugfs files. Ignoring error: %d\n",
4661 err);
4662
4663 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group);
4664 if (err) {
4665 IL_ERR("failed to create sysfs device attributes\n");
4666 goto out_unbind;
4667 }
4668
4669 /* We have our copies now, allow OS release its copies */
4670 release_firmware(ucode_raw);
4671 complete(&il->_4965.firmware_loading_complete);
4672 return;
4673
4674 try_again:
4675 /* try next, if any */
4676 if (il4965_request_firmware(il, false))
4677 goto out_unbind;
4678 release_firmware(ucode_raw);
4679 return;
4680
4681 err_pci_alloc:
4682 IL_ERR("failed to allocate pci memory\n");
4683 il4965_dealloc_ucode_pci(il);
4684 out_unbind:
4685 complete(&il->_4965.firmware_loading_complete);
4686 device_release_driver(&il->pci_dev->dev);
4687 release_firmware(ucode_raw);
4688 }
4689
4690 static const char *const desc_lookup_text[] = {
4691 "OK",
4692 "FAIL",
4693 "BAD_PARAM",
4694 "BAD_CHECKSUM",
4695 "NMI_INTERRUPT_WDG",
4696 "SYSASSERT",
4697 "FATAL_ERROR",
4698 "BAD_COMMAND",
4699 "HW_ERROR_TUNE_LOCK",
4700 "HW_ERROR_TEMPERATURE",
4701 "ILLEGAL_CHAN_FREQ",
4702 "VCC_NOT_STBL",
4703 "FH49_ERROR",
4704 "NMI_INTERRUPT_HOST",
4705 "NMI_INTERRUPT_ACTION_PT",
4706 "NMI_INTERRUPT_UNKNOWN",
4707 "UCODE_VERSION_MISMATCH",
4708 "HW_ERROR_ABS_LOCK",
4709 "HW_ERROR_CAL_LOCK_FAIL",
4710 "NMI_INTERRUPT_INST_ACTION_PT",
4711 "NMI_INTERRUPT_DATA_ACTION_PT",
4712 "NMI_TRM_HW_ER",
4713 "NMI_INTERRUPT_TRM",
4714 "NMI_INTERRUPT_BREAK_POINT",
4715 "DEBUG_0",
4716 "DEBUG_1",
4717 "DEBUG_2",
4718 "DEBUG_3",
4719 };
4720
4721 static struct {
4722 char *name;
4723 u8 num;
4724 } advanced_lookup[] = {
4725 {
4726 "NMI_INTERRUPT_WDG", 0x34}, {
4727 "SYSASSERT", 0x35}, {
4728 "UCODE_VERSION_MISMATCH", 0x37}, {
4729 "BAD_COMMAND", 0x38}, {
4730 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, {
4731 "FATAL_ERROR", 0x3D}, {
4732 "NMI_TRM_HW_ERR", 0x46}, {
4733 "NMI_INTERRUPT_TRM", 0x4C}, {
4734 "NMI_INTERRUPT_BREAK_POINT", 0x54}, {
4735 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, {
4736 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, {
4737 "NMI_INTERRUPT_HOST", 0x66}, {
4738 "NMI_INTERRUPT_ACTION_PT", 0x7C}, {
4739 "NMI_INTERRUPT_UNKNOWN", 0x84}, {
4740 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, {
4741 "ADVANCED_SYSASSERT", 0},};
4742
4743 static const char *
4744 il4965_desc_lookup(u32 num)
4745 {
4746 int i;
4747 int max = ARRAY_SIZE(desc_lookup_text);
4748
4749 if (num < max)
4750 return desc_lookup_text[num];
4751
4752 max = ARRAY_SIZE(advanced_lookup) - 1;
4753 for (i = 0; i < max; i++) {
4754 if (advanced_lookup[i].num == num)
4755 break;
4756 }
4757 return advanced_lookup[i].name;
4758 }
4759
4760 #define ERROR_START_OFFSET (1 * sizeof(u32))
4761 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
4762
4763 void
4764 il4965_dump_nic_error_log(struct il_priv *il)
4765 {
4766 u32 data2, line;
4767 u32 desc, time, count, base, data1;
4768 u32 blink1, blink2, ilink1, ilink2;
4769 u32 pc, hcmd;
4770
4771 if (il->ucode_type == UCODE_INIT)
4772 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr);
4773 else
4774 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
4775
4776 if (!il->ops->lib->is_valid_rtc_data_addr(base)) {
4777 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n",
4778 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT");
4779 return;
4780 }
4781
4782 count = il_read_targ_mem(il, base);
4783
4784 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
4785 IL_ERR("Start IWL Error Log Dump:\n");
4786 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
4787 }
4788
4789 desc = il_read_targ_mem(il, base + 1 * sizeof(u32));
4790 il->isr_stats.err_code = desc;
4791 pc = il_read_targ_mem(il, base + 2 * sizeof(u32));
4792 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32));
4793 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32));
4794 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32));
4795 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32));
4796 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32));
4797 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32));
4798 line = il_read_targ_mem(il, base + 9 * sizeof(u32));
4799 time = il_read_targ_mem(il, base + 11 * sizeof(u32));
4800 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32));
4801
4802 IL_ERR("Desc Time "
4803 "data1 data2 line\n");
4804 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
4805 il4965_desc_lookup(desc), desc, time, data1, data2, line);
4806 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n");
4807 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1,
4808 blink2, ilink1, ilink2, hcmd);
4809 }
4810
4811 static void
4812 il4965_rf_kill_ct_config(struct il_priv *il)
4813 {
4814 struct il_ct_kill_config cmd;
4815 unsigned long flags;
4816 int ret = 0;
4817
4818 spin_lock_irqsave(&il->lock, flags);
4819 _il_wr(il, CSR_UCODE_DRV_GP1_CLR,
4820 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
4821 spin_unlock_irqrestore(&il->lock, flags);
4822
4823 cmd.critical_temperature_R =
4824 cpu_to_le32(il->hw_params.ct_kill_threshold);
4825
4826 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd);
4827 if (ret)
4828 IL_ERR("C_CT_KILL_CONFIG failed\n");
4829 else
4830 D_INFO("C_CT_KILL_CONFIG " "succeeded, "
4831 "critical temperature is %d\n",
4832 il->hw_params.ct_kill_threshold);
4833 }
4834
4835 static const s8 default_queue_to_tx_fifo[] = {
4836 IL_TX_FIFO_VO,
4837 IL_TX_FIFO_VI,
4838 IL_TX_FIFO_BE,
4839 IL_TX_FIFO_BK,
4840 IL49_CMD_FIFO_NUM,
4841 IL_TX_FIFO_UNUSED,
4842 IL_TX_FIFO_UNUSED,
4843 };
4844
4845 #define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
4846
4847 static int
4848 il4965_alive_notify(struct il_priv *il)
4849 {
4850 u32 a;
4851 unsigned long flags;
4852 int i, chan;
4853 u32 reg_val;
4854
4855 spin_lock_irqsave(&il->lock, flags);
4856
4857 /* Clear 4965's internal Tx Scheduler data base */
4858 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR);
4859 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET;
4860 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
4861 il_write_targ_mem(il, a, 0);
4862 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
4863 il_write_targ_mem(il, a, 0);
4864 for (;
4865 a <
4866 il->scd_base_addr +
4867 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num);
4868 a += 4)
4869 il_write_targ_mem(il, a, 0);
4870
4871 /* Tel 4965 where to find Tx byte count tables */
4872 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10);
4873
4874 /* Enable DMA channel */
4875 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++)
4876 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),
4877 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
4878 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
4879
4880 /* Update FH chicken bits */
4881 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG);
4882 il_wr(il, FH49_TX_CHICKEN_BITS_REG,
4883 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
4884
4885 /* Disable chain mode for all queues */
4886 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0);
4887
4888 /* Initialize each Tx queue (including the command queue) */
4889 for (i = 0; i < il->hw_params.max_txq_num; i++) {
4890
4891 /* TFD circular buffer read/write idxes */
4892 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0);
4893 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));
4894
4895 /* Max Tx Window size for Scheduler-ACK mode */
4896 il_write_targ_mem(il,
4897 il->scd_base_addr +
4898 IL49_SCD_CONTEXT_QUEUE_OFFSET(i),
4899 (SCD_WIN_SIZE <<
4900 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4901 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4902
4903 /* Frame limit */
4904 il_write_targ_mem(il,
4905 il->scd_base_addr +
4906 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
4907 sizeof(u32),
4908 (SCD_FRAME_LIMIT <<
4909 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
4910 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4911
4912 }
4913 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK,
4914 (1 << il->hw_params.max_txq_num) - 1);
4915
4916 /* Activate all Tx DMA/FIFO channels */
4917 il4965_txq_set_sched(il, IL_MASK(0, 6));
4918
4919 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0);
4920
4921 /* make sure all queue are not stopped */
4922 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped));
4923 for (i = 0; i < 4; i++)
4924 atomic_set(&il->queue_stop_count[i], 0);
4925
4926 /* reset to 0 to enable all the queue first */
4927 il->txq_ctx_active_msk = 0;
4928 /* Map each Tx/cmd queue to its corresponding fifo */
4929 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
4930
4931 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
4932 int ac = default_queue_to_tx_fifo[i];
4933
4934 il_txq_ctx_activate(il, i);
4935
4936 if (ac == IL_TX_FIFO_UNUSED)
4937 continue;
4938
4939 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0);
4940 }
4941
4942 spin_unlock_irqrestore(&il->lock, flags);
4943
4944 return 0;
4945 }
4946
4947 /**
4948 * il4965_alive_start - called after N_ALIVE notification received
4949 * from protocol/runtime uCode (initialization uCode's
4950 * Alive gets handled by il_init_alive_start()).
4951 */
4952 static void
4953 il4965_alive_start(struct il_priv *il)
4954 {
4955 int ret = 0;
4956
4957 D_INFO("Runtime Alive received.\n");
4958
4959 if (il->card_alive.is_valid != UCODE_VALID_OK) {
4960 /* We had an error bringing up the hardware, so take it
4961 * all the way back down so we can try again */
4962 D_INFO("Alive failed.\n");
4963 goto restart;
4964 }
4965
4966 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
4967 * This is a paranoid check, because we would not have gotten the
4968 * "runtime" alive if code weren't properly loaded. */
4969 if (il4965_verify_ucode(il)) {
4970 /* Runtime instruction load was bad;
4971 * take it all the way back down so we can try again */
4972 D_INFO("Bad runtime uCode load.\n");
4973 goto restart;
4974 }
4975
4976 ret = il4965_alive_notify(il);
4977 if (ret) {
4978 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret);
4979 goto restart;
4980 }
4981
4982 /* After the ALIVE response, we can send host commands to the uCode */
4983 set_bit(S_ALIVE, &il->status);
4984
4985 /* Enable watchdog to monitor the driver tx queues */
4986 il_setup_watchdog(il);
4987
4988 if (il_is_rfkill(il))
4989 return;
4990
4991 ieee80211_wake_queues(il->hw);
4992
4993 il->active_rate = RATES_MASK;
4994
4995 if (il_is_associated(il)) {
4996 struct il_rxon_cmd *active_rxon =
4997 (struct il_rxon_cmd *)&il->active;
4998 /* apply any changes in staging */
4999 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
5000 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5001 } else {
5002 /* Initialize our rx_config data */
5003 il_connection_init_rx_config(il);
5004
5005 if (il->ops->hcmd->set_rxon_chain)
5006 il->ops->hcmd->set_rxon_chain(il);
5007 }
5008
5009 /* Configure bluetooth coexistence if enabled */
5010 il_send_bt_config(il);
5011
5012 il4965_reset_run_time_calib(il);
5013
5014 set_bit(S_READY, &il->status);
5015
5016 /* Configure the adapter for unassociated operation */
5017 il_commit_rxon(il);
5018
5019 /* At this point, the NIC is initialized and operational */
5020 il4965_rf_kill_ct_config(il);
5021
5022 D_INFO("ALIVE processing complete.\n");
5023 wake_up(&il->wait_command_queue);
5024
5025 il_power_update_mode(il, true);
5026 D_INFO("Updated power mode\n");
5027
5028 return;
5029
5030 restart:
5031 queue_work(il->workqueue, &il->restart);
5032 }
5033
5034 static void il4965_cancel_deferred_work(struct il_priv *il);
5035
5036 static void
5037 __il4965_down(struct il_priv *il)
5038 {
5039 unsigned long flags;
5040 int exit_pending;
5041
5042 D_INFO(DRV_NAME " is going down\n");
5043
5044 il_scan_cancel_timeout(il, 200);
5045
5046 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
5047
5048 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set
5049 * to prevent rearm timer */
5050 del_timer_sync(&il->watchdog);
5051
5052 il_clear_ucode_stations(il);
5053
5054 /* FIXME: race conditions ? */
5055 spin_lock_irq(&il->sta_lock);
5056 /*
5057 * Remove all key information that is not stored as part
5058 * of station information since mac80211 may not have had
5059 * a chance to remove all the keys. When device is
5060 * reconfigured by mac80211 after an error all keys will
5061 * be reconfigured.
5062 */
5063 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys));
5064 il->_4965.key_mapping_keys = 0;
5065 spin_unlock_irq(&il->sta_lock);
5066
5067 il_dealloc_bcast_stations(il);
5068 il_clear_driver_stations(il);
5069
5070 /* Unblock any waiting calls */
5071 wake_up_all(&il->wait_command_queue);
5072
5073 /* Wipe out the EXIT_PENDING status bit if we are not actually
5074 * exiting the module */
5075 if (!exit_pending)
5076 clear_bit(S_EXIT_PENDING, &il->status);
5077
5078 /* stop and reset the on-board processor */
5079 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
5080
5081 /* tell the device to stop sending interrupts */
5082 spin_lock_irqsave(&il->lock, flags);
5083 il_disable_interrupts(il);
5084 spin_unlock_irqrestore(&il->lock, flags);
5085 il4965_synchronize_irq(il);
5086
5087 if (il->mac80211_registered)
5088 ieee80211_stop_queues(il->hw);
5089
5090 /* If we have not previously called il_init() then
5091 * clear all bits but the RF Kill bit and return */
5092 if (!il_is_init(il)) {
5093 il->status =
5094 test_bit(S_RF_KILL_HW,
5095 &il->
5096 status) << S_RF_KILL_HW |
5097 test_bit(S_GEO_CONFIGURED,
5098 &il->
5099 status) << S_GEO_CONFIGURED |
5100 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5101 goto exit;
5102 }
5103
5104 /* ...otherwise clear out all the status bits but the RF Kill
5105 * bit and continue taking the NIC down. */
5106 il->status &=
5107 test_bit(S_RF_KILL_HW,
5108 &il->status) << S_RF_KILL_HW | test_bit(S_GEO_CONFIGURED,
5109 &il->
5110 status) <<
5111 S_GEO_CONFIGURED | test_bit(S_FW_ERROR,
5112 &il->
5113 status) << S_FW_ERROR |
5114 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
5115
5116 il4965_txq_ctx_stop(il);
5117 il4965_rxq_stop(il);
5118
5119 /* Power-down device's busmaster DMA clocks */
5120 il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
5121 udelay(5);
5122
5123 /* Make sure (redundant) we've released our request to stay awake */
5124 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
5125
5126 /* Stop the device, and put it in low power state */
5127 il_apm_stop(il);
5128
5129 exit:
5130 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
5131
5132 dev_kfree_skb(il->beacon_skb);
5133 il->beacon_skb = NULL;
5134
5135 /* clear out any free frames */
5136 il4965_clear_free_frames(il);
5137 }
5138
5139 static void
5140 il4965_down(struct il_priv *il)
5141 {
5142 mutex_lock(&il->mutex);
5143 __il4965_down(il);
5144 mutex_unlock(&il->mutex);
5145
5146 il4965_cancel_deferred_work(il);
5147 }
5148
5149 #define HW_READY_TIMEOUT (50)
5150
5151 static int
5152 il4965_set_hw_ready(struct il_priv *il)
5153 {
5154 int ret = 0;
5155
5156 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
5157 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
5158
5159 /* See if we got it */
5160 ret =
5161 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5162 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
5163 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, HW_READY_TIMEOUT);
5164 if (ret != -ETIMEDOUT)
5165 il->hw_ready = true;
5166 else
5167 il->hw_ready = false;
5168
5169 D_INFO("hardware %s\n", (il->hw_ready == 1) ? "ready" : "not ready");
5170 return ret;
5171 }
5172
5173 static int
5174 il4965_prepare_card_hw(struct il_priv *il)
5175 {
5176 int ret = 0;
5177
5178 D_INFO("il4965_prepare_card_hw enter\n");
5179
5180 ret = il4965_set_hw_ready(il);
5181 if (il->hw_ready)
5182 return ret;
5183
5184 /* If HW is not ready, prepare the conditions to check again */
5185 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE);
5186
5187 ret =
5188 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG,
5189 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
5190 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
5191
5192 /* HW should be ready by now, check again. */
5193 if (ret != -ETIMEDOUT)
5194 il4965_set_hw_ready(il);
5195
5196 return ret;
5197 }
5198
5199 #define MAX_HW_RESTARTS 5
5200
5201 static int
5202 __il4965_up(struct il_priv *il)
5203 {
5204 int i;
5205 int ret;
5206
5207 if (test_bit(S_EXIT_PENDING, &il->status)) {
5208 IL_WARN("Exit pending; will not bring the NIC up\n");
5209 return -EIO;
5210 }
5211
5212 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
5213 IL_ERR("ucode not available for device bringup\n");
5214 return -EIO;
5215 }
5216
5217 ret = il4965_alloc_bcast_station(il);
5218 if (ret) {
5219 il_dealloc_bcast_stations(il);
5220 return ret;
5221 }
5222
5223 il4965_prepare_card_hw(il);
5224
5225 if (!il->hw_ready) {
5226 IL_WARN("Exit HW not ready\n");
5227 return -EIO;
5228 }
5229
5230 /* If platform's RF_KILL switch is NOT set to KILL */
5231 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
5232 clear_bit(S_RF_KILL_HW, &il->status);
5233 else
5234 set_bit(S_RF_KILL_HW, &il->status);
5235
5236 if (il_is_rfkill(il)) {
5237 wiphy_rfkill_set_hw_state(il->hw->wiphy, true);
5238
5239 il_enable_interrupts(il);
5240 IL_WARN("Radio disabled by HW RF Kill switch\n");
5241 return 0;
5242 }
5243
5244 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5245
5246 /* must be initialised before il_hw_nic_init */
5247 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM;
5248
5249 ret = il4965_hw_nic_init(il);
5250 if (ret) {
5251 IL_ERR("Unable to init nic\n");
5252 return ret;
5253 }
5254
5255 /* make sure rfkill handshake bits are cleared */
5256 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5257 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
5258
5259 /* clear (again), then enable host interrupts */
5260 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5261 il_enable_interrupts(il);
5262
5263 /* really make sure rfkill handshake bits are cleared */
5264 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5265 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
5266
5267 /* Copy original ucode data image from disk into backup cache.
5268 * This will be used to initialize the on-board processor's
5269 * data SRAM for a clean start when the runtime program first loads. */
5270 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
5271 il->ucode_data.len);
5272
5273 for (i = 0; i < MAX_HW_RESTARTS; i++) {
5274
5275 /* load bootstrap state machine,
5276 * load bootstrap program into processor's memory,
5277 * prepare to load the "initialize" uCode */
5278 ret = il->ops->lib->load_ucode(il);
5279
5280 if (ret) {
5281 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret);
5282 continue;
5283 }
5284
5285 /* start card; "initialize" will load runtime ucode */
5286 il4965_nic_start(il);
5287
5288 D_INFO(DRV_NAME " is coming up\n");
5289
5290 return 0;
5291 }
5292
5293 set_bit(S_EXIT_PENDING, &il->status);
5294 __il4965_down(il);
5295 clear_bit(S_EXIT_PENDING, &il->status);
5296
5297 /* tried to restart and config the device for as long as our
5298 * patience could withstand */
5299 IL_ERR("Unable to initialize device after %d attempts.\n", i);
5300 return -EIO;
5301 }
5302
5303 /*****************************************************************************
5304 *
5305 * Workqueue callbacks
5306 *
5307 *****************************************************************************/
5308
5309 static void
5310 il4965_bg_init_alive_start(struct work_struct *data)
5311 {
5312 struct il_priv *il =
5313 container_of(data, struct il_priv, init_alive_start.work);
5314
5315 mutex_lock(&il->mutex);
5316 if (test_bit(S_EXIT_PENDING, &il->status))
5317 goto out;
5318
5319 il->ops->lib->init_alive_start(il);
5320 out:
5321 mutex_unlock(&il->mutex);
5322 }
5323
5324 static void
5325 il4965_bg_alive_start(struct work_struct *data)
5326 {
5327 struct il_priv *il =
5328 container_of(data, struct il_priv, alive_start.work);
5329
5330 mutex_lock(&il->mutex);
5331 if (test_bit(S_EXIT_PENDING, &il->status))
5332 goto out;
5333
5334 il4965_alive_start(il);
5335 out:
5336 mutex_unlock(&il->mutex);
5337 }
5338
5339 static void
5340 il4965_bg_run_time_calib_work(struct work_struct *work)
5341 {
5342 struct il_priv *il = container_of(work, struct il_priv,
5343 run_time_calib_work);
5344
5345 mutex_lock(&il->mutex);
5346
5347 if (test_bit(S_EXIT_PENDING, &il->status) ||
5348 test_bit(S_SCANNING, &il->status)) {
5349 mutex_unlock(&il->mutex);
5350 return;
5351 }
5352
5353 if (il->start_calib) {
5354 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats);
5355 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats);
5356 }
5357
5358 mutex_unlock(&il->mutex);
5359 }
5360
5361 static void
5362 il4965_bg_restart(struct work_struct *data)
5363 {
5364 struct il_priv *il = container_of(data, struct il_priv, restart);
5365
5366 if (test_bit(S_EXIT_PENDING, &il->status))
5367 return;
5368
5369 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
5370 mutex_lock(&il->mutex);
5371 /* FIXME: do we dereference vif without mutex locked ? */
5372 il->vif = NULL;
5373 il->is_open = 0;
5374
5375 __il4965_down(il);
5376
5377 mutex_unlock(&il->mutex);
5378 il4965_cancel_deferred_work(il);
5379 ieee80211_restart_hw(il->hw);
5380 } else {
5381 il4965_down(il);
5382
5383 mutex_lock(&il->mutex);
5384 if (test_bit(S_EXIT_PENDING, &il->status)) {
5385 mutex_unlock(&il->mutex);
5386 return;
5387 }
5388
5389 __il4965_up(il);
5390 mutex_unlock(&il->mutex);
5391 }
5392 }
5393
5394 static void
5395 il4965_bg_rx_replenish(struct work_struct *data)
5396 {
5397 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
5398
5399 if (test_bit(S_EXIT_PENDING, &il->status))
5400 return;
5401
5402 mutex_lock(&il->mutex);
5403 il4965_rx_replenish(il);
5404 mutex_unlock(&il->mutex);
5405 }
5406
5407 /*****************************************************************************
5408 *
5409 * mac80211 entry point functions
5410 *
5411 *****************************************************************************/
5412
5413 #define UCODE_READY_TIMEOUT (4 * HZ)
5414
5415 /*
5416 * Not a mac80211 entry point function, but it fits in with all the
5417 * other mac80211 functions grouped here.
5418 */
5419 static int
5420 il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length)
5421 {
5422 int ret;
5423 struct ieee80211_hw *hw = il->hw;
5424
5425 hw->rate_control_algorithm = "iwl-4965-rs";
5426
5427 /* Tell mac80211 our characteristics */
5428 hw->flags =
5429 IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION |
5430 IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT |
5431 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5432
5433 if (il->cfg->sku & IL_SKU_N)
5434 hw->flags |=
5435 IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
5436 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
5437
5438 hw->sta_data_size = sizeof(struct il_station_priv);
5439 hw->vif_data_size = sizeof(struct il_vif_priv);
5440
5441 hw->wiphy->interface_modes =
5442 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
5443
5444 hw->wiphy->flags |=
5445 WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS;
5446
5447 /*
5448 * For now, disable PS by default because it affects
5449 * RX performance significantly.
5450 */
5451 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5452
5453 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
5454 /* we create the 802.11 header and a zero-length SSID element */
5455 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
5456
5457 /* Default value; 4 EDCA QOS priorities */
5458 hw->queues = 4;
5459
5460 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL;
5461
5462 if (il->bands[IEEE80211_BAND_2GHZ].n_channels)
5463 il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
5464 &il->bands[IEEE80211_BAND_2GHZ];
5465 if (il->bands[IEEE80211_BAND_5GHZ].n_channels)
5466 il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
5467 &il->bands[IEEE80211_BAND_5GHZ];
5468
5469 il_leds_init(il);
5470
5471 ret = ieee80211_register_hw(il->hw);
5472 if (ret) {
5473 IL_ERR("Failed to register hw (error %d)\n", ret);
5474 return ret;
5475 }
5476 il->mac80211_registered = 1;
5477
5478 return 0;
5479 }
5480
5481 int
5482 il4965_mac_start(struct ieee80211_hw *hw)
5483 {
5484 struct il_priv *il = hw->priv;
5485 int ret;
5486
5487 D_MAC80211("enter\n");
5488
5489 /* we should be verifying the device is ready to be opened */
5490 mutex_lock(&il->mutex);
5491 ret = __il4965_up(il);
5492 mutex_unlock(&il->mutex);
5493
5494 if (ret)
5495 return ret;
5496
5497 if (il_is_rfkill(il))
5498 goto out;
5499
5500 D_INFO("Start UP work done.\n");
5501
5502 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5503 * mac80211 will not be run successfully. */
5504 ret = wait_event_timeout(il->wait_command_queue,
5505 test_bit(S_READY, &il->status),
5506 UCODE_READY_TIMEOUT);
5507 if (!ret) {
5508 if (!test_bit(S_READY, &il->status)) {
5509 IL_ERR("START_ALIVE timeout after %dms.\n",
5510 jiffies_to_msecs(UCODE_READY_TIMEOUT));
5511 return -ETIMEDOUT;
5512 }
5513 }
5514
5515 il4965_led_enable(il);
5516
5517 out:
5518 il->is_open = 1;
5519 D_MAC80211("leave\n");
5520 return 0;
5521 }
5522
5523 void
5524 il4965_mac_stop(struct ieee80211_hw *hw)
5525 {
5526 struct il_priv *il = hw->priv;
5527
5528 D_MAC80211("enter\n");
5529
5530 if (!il->is_open)
5531 return;
5532
5533 il->is_open = 0;
5534
5535 il4965_down(il);
5536
5537 flush_workqueue(il->workqueue);
5538
5539 /* User space software may expect getting rfkill changes
5540 * even if interface is down */
5541 _il_wr(il, CSR_INT, 0xFFFFFFFF);
5542 il_enable_rfkill_int(il);
5543
5544 D_MAC80211("leave\n");
5545 }
5546
5547 void
5548 il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
5549 {
5550 struct il_priv *il = hw->priv;
5551
5552 D_MACDUMP("enter\n");
5553
5554 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
5555 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
5556
5557 if (il4965_tx_skb(il, skb))
5558 dev_kfree_skb_any(skb);
5559
5560 D_MACDUMP("leave\n");
5561 }
5562
5563 void
5564 il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5565 struct ieee80211_key_conf *keyconf,
5566 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key)
5567 {
5568 struct il_priv *il = hw->priv;
5569
5570 D_MAC80211("enter\n");
5571
5572 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key);
5573
5574 D_MAC80211("leave\n");
5575 }
5576
5577 int
5578 il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5579 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
5580 struct ieee80211_key_conf *key)
5581 {
5582 struct il_priv *il = hw->priv;
5583 int ret;
5584 u8 sta_id;
5585 bool is_default_wep_key = false;
5586
5587 D_MAC80211("enter\n");
5588
5589 if (il->cfg->mod_params->sw_crypto) {
5590 D_MAC80211("leave - hwcrypto disabled\n");
5591 return -EOPNOTSUPP;
5592 }
5593
5594 sta_id = il_sta_id_or_broadcast(il, sta);
5595 if (sta_id == IL_INVALID_STATION)
5596 return -EINVAL;
5597
5598 mutex_lock(&il->mutex);
5599 il_scan_cancel_timeout(il, 100);
5600
5601 /*
5602 * If we are getting WEP group key and we didn't receive any key mapping
5603 * so far, we are in legacy wep mode (group key only), otherwise we are
5604 * in 1X mode.
5605 * In legacy wep mode, we use another host command to the uCode.
5606 */
5607 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
5608 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
5609 if (cmd == SET_KEY)
5610 is_default_wep_key = !il->_4965.key_mapping_keys;
5611 else
5612 is_default_wep_key =
5613 (key->hw_key_idx == HW_KEY_DEFAULT);
5614 }
5615
5616 switch (cmd) {
5617 case SET_KEY:
5618 if (is_default_wep_key)
5619 ret = il4965_set_default_wep_key(il, key);
5620 else
5621 ret = il4965_set_dynamic_key(il, key, sta_id);
5622
5623 D_MAC80211("enable hwcrypto key\n");
5624 break;
5625 case DISABLE_KEY:
5626 if (is_default_wep_key)
5627 ret = il4965_remove_default_wep_key(il, key);
5628 else
5629 ret = il4965_remove_dynamic_key(il, key, sta_id);
5630
5631 D_MAC80211("disable hwcrypto key\n");
5632 break;
5633 default:
5634 ret = -EINVAL;
5635 }
5636
5637 mutex_unlock(&il->mutex);
5638 D_MAC80211("leave\n");
5639
5640 return ret;
5641 }
5642
5643 int
5644 il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5645 enum ieee80211_ampdu_mlme_action action,
5646 struct ieee80211_sta *sta, u16 tid, u16 * ssn,
5647 u8 buf_size)
5648 {
5649 struct il_priv *il = hw->priv;
5650 int ret = -EINVAL;
5651
5652 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid);
5653
5654 if (!(il->cfg->sku & IL_SKU_N))
5655 return -EACCES;
5656
5657 mutex_lock(&il->mutex);
5658
5659 switch (action) {
5660 case IEEE80211_AMPDU_RX_START:
5661 D_HT("start Rx\n");
5662 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn);
5663 break;
5664 case IEEE80211_AMPDU_RX_STOP:
5665 D_HT("stop Rx\n");
5666 ret = il4965_sta_rx_agg_stop(il, sta, tid);
5667 if (test_bit(S_EXIT_PENDING, &il->status))
5668 ret = 0;
5669 break;
5670 case IEEE80211_AMPDU_TX_START:
5671 D_HT("start Tx\n");
5672 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn);
5673 break;
5674 case IEEE80211_AMPDU_TX_STOP:
5675 D_HT("stop Tx\n");
5676 ret = il4965_tx_agg_stop(il, vif, sta, tid);
5677 if (test_bit(S_EXIT_PENDING, &il->status))
5678 ret = 0;
5679 break;
5680 case IEEE80211_AMPDU_TX_OPERATIONAL:
5681 ret = 0;
5682 break;
5683 }
5684 mutex_unlock(&il->mutex);
5685
5686 return ret;
5687 }
5688
5689 int
5690 il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5691 struct ieee80211_sta *sta)
5692 {
5693 struct il_priv *il = hw->priv;
5694 struct il_station_priv *sta_priv = (void *)sta->drv_priv;
5695 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
5696 int ret;
5697 u8 sta_id;
5698
5699 D_INFO("received request to add station %pM\n", sta->addr);
5700 mutex_lock(&il->mutex);
5701 D_INFO("proceeding to add station %pM\n", sta->addr);
5702 sta_priv->common.sta_id = IL_INVALID_STATION;
5703
5704 atomic_set(&sta_priv->pending_frames, 0);
5705
5706 ret =
5707 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
5708 if (ret) {
5709 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
5710 /* Should we return success if return code is EEXIST ? */
5711 mutex_unlock(&il->mutex);
5712 return ret;
5713 }
5714
5715 sta_priv->common.sta_id = sta_id;
5716
5717 /* Initialize rate scaling */
5718 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
5719 il4965_rs_rate_init(il, sta, sta_id);
5720 mutex_unlock(&il->mutex);
5721
5722 return 0;
5723 }
5724
5725 void
5726 il4965_mac_channel_switch(struct ieee80211_hw *hw,
5727 struct ieee80211_channel_switch *ch_switch)
5728 {
5729 struct il_priv *il = hw->priv;
5730 const struct il_channel_info *ch_info;
5731 struct ieee80211_conf *conf = &hw->conf;
5732 struct ieee80211_channel *channel = ch_switch->channel;
5733 struct il_ht_config *ht_conf = &il->current_ht_config;
5734 u16 ch;
5735
5736 D_MAC80211("enter\n");
5737
5738 mutex_lock(&il->mutex);
5739
5740 if (il_is_rfkill(il))
5741 goto out;
5742
5743 if (test_bit(S_EXIT_PENDING, &il->status) ||
5744 test_bit(S_SCANNING, &il->status) ||
5745 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
5746 goto out;
5747
5748 if (!il_is_associated(il))
5749 goto out;
5750
5751 if (!il->ops->lib->set_channel_switch)
5752 goto out;
5753
5754 ch = channel->hw_value;
5755 if (le16_to_cpu(il->active.channel) == ch)
5756 goto out;
5757
5758 ch_info = il_get_channel_info(il, channel->band, ch);
5759 if (!il_is_channel_valid(ch_info)) {
5760 D_MAC80211("invalid channel\n");
5761 goto out;
5762 }
5763
5764 spin_lock_irq(&il->lock);
5765
5766 il->current_ht_config.smps = conf->smps_mode;
5767
5768 /* Configure HT40 channels */
5769 il->ht.enabled = conf_is_ht(conf);
5770 if (il->ht.enabled) {
5771 if (conf_is_ht40_minus(conf)) {
5772 il->ht.extension_chan_offset =
5773 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
5774 il->ht.is_40mhz = true;
5775 } else if (conf_is_ht40_plus(conf)) {
5776 il->ht.extension_chan_offset =
5777 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
5778 il->ht.is_40mhz = true;
5779 } else {
5780 il->ht.extension_chan_offset =
5781 IEEE80211_HT_PARAM_CHA_SEC_NONE;
5782 il->ht.is_40mhz = false;
5783 }
5784 } else
5785 il->ht.is_40mhz = false;
5786
5787 if ((le16_to_cpu(il->staging.channel) != ch))
5788 il->staging.flags = 0;
5789
5790 il_set_rxon_channel(il, channel);
5791 il_set_rxon_ht(il, ht_conf);
5792 il_set_flags_for_band(il, channel->band, il->vif);
5793
5794 spin_unlock_irq(&il->lock);
5795
5796 il_set_rate(il);
5797 /*
5798 * at this point, staging_rxon has the
5799 * configuration for channel switch
5800 */
5801 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
5802 il->switch_channel = cpu_to_le16(ch);
5803 if (il->ops->lib->set_channel_switch(il, ch_switch)) {
5804 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status);
5805 il->switch_channel = 0;
5806 ieee80211_chswitch_done(il->vif, false);
5807 }
5808
5809 out:
5810 mutex_unlock(&il->mutex);
5811 D_MAC80211("leave\n");
5812 }
5813
5814 void
5815 il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
5816 unsigned int *total_flags, u64 multicast)
5817 {
5818 struct il_priv *il = hw->priv;
5819 __le32 filter_or = 0, filter_nand = 0;
5820
5821 #define CHK(test, flag) do { \
5822 if (*total_flags & (test)) \
5823 filter_or |= (flag); \
5824 else \
5825 filter_nand |= (flag); \
5826 } while (0)
5827
5828 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
5829 *total_flags);
5830
5831 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
5832 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
5833 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
5834 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
5835
5836 #undef CHK
5837
5838 mutex_lock(&il->mutex);
5839
5840 il->staging.filter_flags &= ~filter_nand;
5841 il->staging.filter_flags |= filter_or;
5842
5843 /*
5844 * Not committing directly because hardware can perform a scan,
5845 * but we'll eventually commit the filter flags change anyway.
5846 */
5847
5848 mutex_unlock(&il->mutex);
5849
5850 /*
5851 * Receiving all multicast frames is always enabled by the
5852 * default flags setup in il_connection_init_rx_config()
5853 * since we currently do not support programming multicast
5854 * filters into the device.
5855 */
5856 *total_flags &=
5857 FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
5858 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
5859 }
5860
5861 /*****************************************************************************
5862 *
5863 * driver setup and teardown
5864 *
5865 *****************************************************************************/
5866
5867 static void
5868 il4965_bg_txpower_work(struct work_struct *work)
5869 {
5870 struct il_priv *il = container_of(work, struct il_priv,
5871 txpower_work);
5872
5873 mutex_lock(&il->mutex);
5874
5875 /* If a scan happened to start before we got here
5876 * then just return; the stats notification will
5877 * kick off another scheduled work to compensate for
5878 * any temperature delta we missed here. */
5879 if (test_bit(S_EXIT_PENDING, &il->status) ||
5880 test_bit(S_SCANNING, &il->status))
5881 goto out;
5882
5883 /* Regardless of if we are associated, we must reconfigure the
5884 * TX power since frames can be sent on non-radar channels while
5885 * not associated */
5886 il->ops->lib->send_tx_power(il);
5887
5888 /* Update last_temperature to keep is_calib_needed from running
5889 * when it isn't needed... */
5890 il->last_temperature = il->temperature;
5891 out:
5892 mutex_unlock(&il->mutex);
5893 }
5894
5895 static void
5896 il4965_setup_deferred_work(struct il_priv *il)
5897 {
5898 il->workqueue = create_singlethread_workqueue(DRV_NAME);
5899
5900 init_waitqueue_head(&il->wait_command_queue);
5901
5902 INIT_WORK(&il->restart, il4965_bg_restart);
5903 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish);
5904 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work);
5905 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start);
5906 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start);
5907
5908 il_setup_scan_deferred_work(il);
5909
5910 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work);
5911
5912 init_timer(&il->stats_periodic);
5913 il->stats_periodic.data = (unsigned long)il;
5914 il->stats_periodic.function = il4965_bg_stats_periodic;
5915
5916 init_timer(&il->watchdog);
5917 il->watchdog.data = (unsigned long)il;
5918 il->watchdog.function = il_bg_watchdog;
5919
5920 tasklet_init(&il->irq_tasklet,
5921 (void (*)(unsigned long))il4965_irq_tasklet,
5922 (unsigned long)il);
5923 }
5924
5925 static void
5926 il4965_cancel_deferred_work(struct il_priv *il)
5927 {
5928 cancel_work_sync(&il->txpower_work);
5929 cancel_delayed_work_sync(&il->init_alive_start);
5930 cancel_delayed_work(&il->alive_start);
5931 cancel_work_sync(&il->run_time_calib_work);
5932
5933 il_cancel_scan_deferred_work(il);
5934
5935 del_timer_sync(&il->stats_periodic);
5936 }
5937
5938 static void
5939 il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
5940 {
5941 int i;
5942
5943 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
5944 rates[i].bitrate = il_rates[i].ieee * 5;
5945 rates[i].hw_value = i; /* Rate scaling will work on idxes */
5946 rates[i].hw_value_short = i;
5947 rates[i].flags = 0;
5948 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) {
5949 /*
5950 * If CCK != 1M then set short preamble rate flag.
5951 */
5952 rates[i].flags |=
5953 (il_rates[i].plcp ==
5954 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
5955 }
5956 }
5957 }
5958
5959 /*
5960 * Acquire il->lock before calling this function !
5961 */
5962 void
5963 il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx)
5964 {
5965 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));
5966 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx);
5967 }
5968
5969 void
5970 il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
5971 int tx_fifo_id, int scd_retry)
5972 {
5973 int txq_id = txq->q.id;
5974
5975 /* Find out whether to activate Tx queue */
5976 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0;
5977
5978 /* Set up and activate */
5979 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id),
5980 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
5981 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) |
5982 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) |
5983 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
5984 IL49_SCD_QUEUE_STTS_REG_MSK);
5985
5986 txq->sched_retry = scd_retry;
5987
5988 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate",
5989 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
5990 }
5991
5992 const struct ieee80211_ops il4965_mac_ops = {
5993 .tx = il4965_mac_tx,
5994 .start = il4965_mac_start,
5995 .stop = il4965_mac_stop,
5996 .add_interface = il_mac_add_interface,
5997 .remove_interface = il_mac_remove_interface,
5998 .change_interface = il_mac_change_interface,
5999 .config = il_mac_config,
6000 .configure_filter = il4965_configure_filter,
6001 .set_key = il4965_mac_set_key,
6002 .update_tkip_key = il4965_mac_update_tkip_key,
6003 .conf_tx = il_mac_conf_tx,
6004 .reset_tsf = il_mac_reset_tsf,
6005 .bss_info_changed = il_mac_bss_info_changed,
6006 .ampdu_action = il4965_mac_ampdu_action,
6007 .hw_scan = il_mac_hw_scan,
6008 .sta_add = il4965_mac_sta_add,
6009 .sta_remove = il_mac_sta_remove,
6010 .channel_switch = il4965_mac_channel_switch,
6011 .tx_last_beacon = il_mac_tx_last_beacon,
6012 };
6013
6014 static int
6015 il4965_init_drv(struct il_priv *il)
6016 {
6017 int ret;
6018
6019 spin_lock_init(&il->sta_lock);
6020 spin_lock_init(&il->hcmd_lock);
6021
6022 INIT_LIST_HEAD(&il->free_frames);
6023
6024 mutex_init(&il->mutex);
6025
6026 il->ieee_channels = NULL;
6027 il->ieee_rates = NULL;
6028 il->band = IEEE80211_BAND_2GHZ;
6029
6030 il->iw_mode = NL80211_IFTYPE_STATION;
6031 il->current_ht_config.smps = IEEE80211_SMPS_STATIC;
6032 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
6033
6034 /* initialize force reset */
6035 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
6036
6037 /* Choose which receivers/antennas to use */
6038 if (il->ops->hcmd->set_rxon_chain)
6039 il->ops->hcmd->set_rxon_chain(il);
6040
6041 il_init_scan_params(il);
6042
6043 ret = il_init_channel_map(il);
6044 if (ret) {
6045 IL_ERR("initializing regulatory failed: %d\n", ret);
6046 goto err;
6047 }
6048
6049 ret = il_init_geos(il);
6050 if (ret) {
6051 IL_ERR("initializing geos failed: %d\n", ret);
6052 goto err_free_channel_map;
6053 }
6054 il4965_init_hw_rates(il, il->ieee_rates);
6055
6056 return 0;
6057
6058 err_free_channel_map:
6059 il_free_channel_map(il);
6060 err:
6061 return ret;
6062 }
6063
6064 static void
6065 il4965_uninit_drv(struct il_priv *il)
6066 {
6067 il4965_calib_free_results(il);
6068 il_free_geos(il);
6069 il_free_channel_map(il);
6070 kfree(il->scan_cmd);
6071 }
6072
6073 static void
6074 il4965_hw_detect(struct il_priv *il)
6075 {
6076 il->hw_rev = _il_rd(il, CSR_HW_REV);
6077 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG);
6078 il->rev_id = il->pci_dev->revision;
6079 D_INFO("HW Revision ID = 0x%X\n", il->rev_id);
6080 }
6081
6082 static int
6083 il4965_set_hw_params(struct il_priv *il)
6084 {
6085 il->hw_params.bcast_id = IL4965_BROADCAST_ID;
6086 il->hw_params.max_rxq_size = RX_QUEUE_SIZE;
6087 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
6088 if (il->cfg->mod_params->amsdu_size_8K)
6089 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K);
6090 else
6091 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K);
6092
6093 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL;
6094
6095 if (il->cfg->mod_params->disable_11n)
6096 il->cfg->sku &= ~IL_SKU_N;
6097
6098 /* Device-specific setup */
6099 return il->ops->lib->set_hw_params(il);
6100 }
6101
6102 static int
6103 il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
6104 {
6105 int err = 0;
6106 struct il_priv *il;
6107 struct ieee80211_hw *hw;
6108 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
6109 unsigned long flags;
6110 u16 pci_cmd;
6111
6112 /************************
6113 * 1. Allocating HW data
6114 ************************/
6115
6116 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops);
6117 if (!hw) {
6118 err = -ENOMEM;
6119 goto out;
6120 }
6121 il = hw->priv;
6122 il->hw = hw;
6123 SET_IEEE80211_DEV(hw, &pdev->dev);
6124
6125 D_INFO("*** LOAD DRIVER ***\n");
6126 il->cfg = cfg;
6127 il->ops = &il4965_ops;
6128 il->pci_dev = pdev;
6129 il->inta_mask = CSR_INI_SET_MASK;
6130
6131 if (il_alloc_traffic_mem(il))
6132 IL_ERR("Not enough memory to generate traffic log\n");
6133
6134 /**************************
6135 * 2. Initializing PCI bus
6136 **************************/
6137 pci_disable_link_state(pdev,
6138 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
6139 PCIE_LINK_STATE_CLKPM);
6140
6141 if (pci_enable_device(pdev)) {
6142 err = -ENODEV;
6143 goto out_ieee80211_free_hw;
6144 }
6145
6146 pci_set_master(pdev);
6147
6148 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
6149 if (!err)
6150 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
6151 if (err) {
6152 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6153 if (!err)
6154 err =
6155 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6156 /* both attempts failed: */
6157 if (err) {
6158 IL_WARN("No suitable DMA available.\n");
6159 goto out_pci_disable_device;
6160 }
6161 }
6162
6163 err = pci_request_regions(pdev, DRV_NAME);
6164 if (err)
6165 goto out_pci_disable_device;
6166
6167 pci_set_drvdata(pdev, il);
6168
6169 /***********************
6170 * 3. Read REV register
6171 ***********************/
6172 il->hw_base = pci_iomap(pdev, 0, 0);
6173 if (!il->hw_base) {
6174 err = -ENODEV;
6175 goto out_pci_release_regions;
6176 }
6177
6178 D_INFO("pci_resource_len = 0x%08llx\n",
6179 (unsigned long long)pci_resource_len(pdev, 0));
6180 D_INFO("pci_resource_base = %p\n", il->hw_base);
6181
6182 /* these spin locks will be used in apm_ops.init and EEPROM access
6183 * we should init now
6184 */
6185 spin_lock_init(&il->reg_lock);
6186 spin_lock_init(&il->lock);
6187
6188 /*
6189 * stop and reset the on-board processor just in case it is in a
6190 * strange state ... like being left stranded by a primary kernel
6191 * and this is now the kdump kernel trying to start up
6192 */
6193 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
6194
6195 il4965_hw_detect(il);
6196 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev);
6197
6198 /* We disable the RETRY_TIMEOUT register (0x41) to keep
6199 * PCI Tx retries from interfering with C3 CPU state */
6200 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
6201
6202 il4965_prepare_card_hw(il);
6203 if (!il->hw_ready) {
6204 IL_WARN("Failed, HW not ready\n");
6205 goto out_iounmap;
6206 }
6207
6208 /*****************
6209 * 4. Read EEPROM
6210 *****************/
6211 /* Read the EEPROM */
6212 err = il_eeprom_init(il);
6213 if (err) {
6214 IL_ERR("Unable to init EEPROM\n");
6215 goto out_iounmap;
6216 }
6217 err = il4965_eeprom_check_version(il);
6218 if (err)
6219 goto out_free_eeprom;
6220
6221 if (err)
6222 goto out_free_eeprom;
6223
6224 /* extract MAC Address */
6225 il4965_eeprom_get_mac(il, il->addresses[0].addr);
6226 D_INFO("MAC address: %pM\n", il->addresses[0].addr);
6227 il->hw->wiphy->addresses = il->addresses;
6228 il->hw->wiphy->n_addresses = 1;
6229
6230 /************************
6231 * 5. Setup HW constants
6232 ************************/
6233 if (il4965_set_hw_params(il)) {
6234 IL_ERR("failed to set hw parameters\n");
6235 goto out_free_eeprom;
6236 }
6237
6238 /*******************
6239 * 6. Setup il
6240 *******************/
6241
6242 err = il4965_init_drv(il);
6243 if (err)
6244 goto out_free_eeprom;
6245 /* At this point both hw and il are initialized. */
6246
6247 /********************
6248 * 7. Setup services
6249 ********************/
6250 spin_lock_irqsave(&il->lock, flags);
6251 il_disable_interrupts(il);
6252 spin_unlock_irqrestore(&il->lock, flags);
6253
6254 pci_enable_msi(il->pci_dev);
6255
6256 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
6257 if (err) {
6258 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
6259 goto out_disable_msi;
6260 }
6261
6262 il4965_setup_deferred_work(il);
6263 il4965_setup_handlers(il);
6264
6265 /*********************************************
6266 * 8. Enable interrupts and read RFKILL state
6267 *********************************************/
6268
6269 /* enable rfkill interrupt: hw bug w/a */
6270 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd);
6271 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
6272 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
6273 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd);
6274 }
6275
6276 il_enable_rfkill_int(il);
6277
6278 /* If platform's RF_KILL switch is NOT set to KILL */
6279 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
6280 clear_bit(S_RF_KILL_HW, &il->status);
6281 else
6282 set_bit(S_RF_KILL_HW, &il->status);
6283
6284 wiphy_rfkill_set_hw_state(il->hw->wiphy,
6285 test_bit(S_RF_KILL_HW, &il->status));
6286
6287 il_power_initialize(il);
6288
6289 init_completion(&il->_4965.firmware_loading_complete);
6290
6291 err = il4965_request_firmware(il, true);
6292 if (err)
6293 goto out_destroy_workqueue;
6294
6295 return 0;
6296
6297 out_destroy_workqueue:
6298 destroy_workqueue(il->workqueue);
6299 il->workqueue = NULL;
6300 free_irq(il->pci_dev->irq, il);
6301 out_disable_msi:
6302 pci_disable_msi(il->pci_dev);
6303 il4965_uninit_drv(il);
6304 out_free_eeprom:
6305 il_eeprom_free(il);
6306 out_iounmap:
6307 pci_iounmap(pdev, il->hw_base);
6308 out_pci_release_regions:
6309 pci_set_drvdata(pdev, NULL);
6310 pci_release_regions(pdev);
6311 out_pci_disable_device:
6312 pci_disable_device(pdev);
6313 out_ieee80211_free_hw:
6314 il_free_traffic_mem(il);
6315 ieee80211_free_hw(il->hw);
6316 out:
6317 return err;
6318 }
6319
6320 static void __devexit
6321 il4965_pci_remove(struct pci_dev *pdev)
6322 {
6323 struct il_priv *il = pci_get_drvdata(pdev);
6324 unsigned long flags;
6325
6326 if (!il)
6327 return;
6328
6329 wait_for_completion(&il->_4965.firmware_loading_complete);
6330
6331 D_INFO("*** UNLOAD DRIVER ***\n");
6332
6333 il_dbgfs_unregister(il);
6334 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group);
6335
6336 /* ieee80211_unregister_hw call wil cause il_mac_stop to
6337 * to be called and il4965_down since we are removing the device
6338 * we need to set S_EXIT_PENDING bit.
6339 */
6340 set_bit(S_EXIT_PENDING, &il->status);
6341
6342 il_leds_exit(il);
6343
6344 if (il->mac80211_registered) {
6345 ieee80211_unregister_hw(il->hw);
6346 il->mac80211_registered = 0;
6347 } else {
6348 il4965_down(il);
6349 }
6350
6351 /*
6352 * Make sure device is reset to low power before unloading driver.
6353 * This may be redundant with il4965_down(), but there are paths to
6354 * run il4965_down() without calling apm_ops.stop(), and there are
6355 * paths to avoid running il4965_down() at all before leaving driver.
6356 * This (inexpensive) call *makes sure* device is reset.
6357 */
6358 il_apm_stop(il);
6359
6360 /* make sure we flush any pending irq or
6361 * tasklet for the driver
6362 */
6363 spin_lock_irqsave(&il->lock, flags);
6364 il_disable_interrupts(il);
6365 spin_unlock_irqrestore(&il->lock, flags);
6366
6367 il4965_synchronize_irq(il);
6368
6369 il4965_dealloc_ucode_pci(il);
6370
6371 if (il->rxq.bd)
6372 il4965_rx_queue_free(il, &il->rxq);
6373 il4965_hw_txq_ctx_free(il);
6374
6375 il_eeprom_free(il);
6376
6377 /*netif_stop_queue(dev); */
6378 flush_workqueue(il->workqueue);
6379
6380 /* ieee80211_unregister_hw calls il_mac_stop, which flushes
6381 * il->workqueue... so we can't take down the workqueue
6382 * until now... */
6383 destroy_workqueue(il->workqueue);
6384 il->workqueue = NULL;
6385 il_free_traffic_mem(il);
6386
6387 free_irq(il->pci_dev->irq, il);
6388 pci_disable_msi(il->pci_dev);
6389 pci_iounmap(pdev, il->hw_base);
6390 pci_release_regions(pdev);
6391 pci_disable_device(pdev);
6392 pci_set_drvdata(pdev, NULL);
6393
6394 il4965_uninit_drv(il);
6395
6396 dev_kfree_skb(il->beacon_skb);
6397
6398 ieee80211_free_hw(il->hw);
6399 }
6400
6401 /*
6402 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
6403 * must be called under il->lock and mac access
6404 */
6405 void
6406 il4965_txq_set_sched(struct il_priv *il, u32 mask)
6407 {
6408 il_wr_prph(il, IL49_SCD_TXFACT, mask);
6409 }
6410
6411 /*****************************************************************************
6412 *
6413 * driver and module entry point
6414 *
6415 *****************************************************************************/
6416
6417 /* Hardware specific file defines the PCI IDs table for that hardware module */
6418 static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = {
6419 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)},
6420 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)},
6421 {0}
6422 };
6423 MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids);
6424
6425 static struct pci_driver il4965_driver = {
6426 .name = DRV_NAME,
6427 .id_table = il4965_hw_card_ids,
6428 .probe = il4965_pci_probe,
6429 .remove = __devexit_p(il4965_pci_remove),
6430 .driver.pm = IL_LEGACY_PM_OPS,
6431 };
6432
6433 static int __init
6434 il4965_init(void)
6435 {
6436
6437 int ret;
6438 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
6439 pr_info(DRV_COPYRIGHT "\n");
6440
6441 ret = il4965_rate_control_register();
6442 if (ret) {
6443 pr_err("Unable to register rate control algorithm: %d\n", ret);
6444 return ret;
6445 }
6446
6447 ret = pci_register_driver(&il4965_driver);
6448 if (ret) {
6449 pr_err("Unable to initialize PCI module\n");
6450 goto error_register;
6451 }
6452
6453 return ret;
6454
6455 error_register:
6456 il4965_rate_control_unregister();
6457 return ret;
6458 }
6459
6460 static void __exit
6461 il4965_exit(void)
6462 {
6463 pci_unregister_driver(&il4965_driver);
6464 il4965_rate_control_unregister();
6465 }
6466
6467 module_exit(il4965_exit);
6468 module_init(il4965_init);
6469
6470 #ifdef CONFIG_IWLEGACY_DEBUG
6471 module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR);
6472 MODULE_PARM_DESC(debug, "debug output mask");
6473 #endif
6474
6475 module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO);
6476 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
6477 module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO);
6478 MODULE_PARM_DESC(queues_num, "number of hw queues.");
6479 module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO);
6480 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
6481 module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int,
6482 S_IRUGO);
6483 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
6484 module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO);
6485 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
kernel source for telekom puls (alcatel/mediatek)