drivers/net/wireless/b43legacy/b43legacy.h

   1 #ifndef B43legacy_H_
   2 #define B43legacy_H_
   3
   4 #include <linux/hw_random.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/stringify.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/pci.h>
  11 #include <asm/atomic.h>
  12 #include <linux/io.h>
  13
  14 #include <linux/ssb/ssb.h>
  15 #include <linux/ssb/ssb_driver_chipcommon.h>
  16
  17 #include <linux/wireless.h>
  18 #include <net/mac80211.h>
  19
  20 #include "debugfs.h"
  21 #include "leds.h"
  22 #include "rfkill.h"
  23 #include "phy.h"
  24
  25
  26 #define B43legacy_IRQWAIT_MAX_RETRIES   20
  27
  28 #define B43legacy_RX_MAX_SSI            60 /* best guess at max ssi */
  29
  30 /* MMIO offsets */
  31 #define B43legacy_MMIO_DMA0_REASON      0x20
  32 #define B43legacy_MMIO_DMA0_IRQ_MASK    0x24
  33 #define B43legacy_MMIO_DMA1_REASON      0x28
  34 #define B43legacy_MMIO_DMA1_IRQ_MASK    0x2C
  35 #define B43legacy_MMIO_DMA2_REASON      0x30
  36 #define B43legacy_MMIO_DMA2_IRQ_MASK    0x34
  37 #define B43legacy_MMIO_DMA3_REASON      0x38
  38 #define B43legacy_MMIO_DMA3_IRQ_MASK    0x3C
  39 #define B43legacy_MMIO_DMA4_REASON      0x40
  40 #define B43legacy_MMIO_DMA4_IRQ_MASK    0x44
  41 #define B43legacy_MMIO_DMA5_REASON      0x48
  42 #define B43legacy_MMIO_DMA5_IRQ_MASK    0x4C
  43 #define B43legacy_MMIO_MACCTL           0x120   /* MAC control */
  44 #define B43legacy_MMIO_MACCMD           0x124   /* MAC command */
  45 #define B43legacy_MMIO_GEN_IRQ_REASON   0x128
  46 #define B43legacy_MMIO_GEN_IRQ_MASK     0x12C
  47 #define B43legacy_MMIO_RAM_CONTROL      0x130
  48 #define B43legacy_MMIO_RAM_DATA         0x134
  49 #define B43legacy_MMIO_PS_STATUS                0x140
  50 #define B43legacy_MMIO_RADIO_HWENABLED_HI       0x158
  51 #define B43legacy_MMIO_SHM_CONTROL      0x160
  52 #define B43legacy_MMIO_SHM_DATA         0x164
  53 #define B43legacy_MMIO_SHM_DATA_UNALIGNED       0x166
  54 #define B43legacy_MMIO_XMITSTAT_0               0x170
  55 #define B43legacy_MMIO_XMITSTAT_1               0x174
  56 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
  57 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH        0x184 /* core rev >= 3 only */
  58
  59 /* 32-bit DMA */
  60 #define B43legacy_MMIO_DMA32_BASE0      0x200
  61 #define B43legacy_MMIO_DMA32_BASE1      0x220
  62 #define B43legacy_MMIO_DMA32_BASE2      0x240
  63 #define B43legacy_MMIO_DMA32_BASE3      0x260
  64 #define B43legacy_MMIO_DMA32_BASE4      0x280
  65 #define B43legacy_MMIO_DMA32_BASE5      0x2A0
  66 /* 64-bit DMA */
  67 #define B43legacy_MMIO_DMA64_BASE0      0x200
  68 #define B43legacy_MMIO_DMA64_BASE1      0x240
  69 #define B43legacy_MMIO_DMA64_BASE2      0x280
  70 #define B43legacy_MMIO_DMA64_BASE3      0x2C0
  71 #define B43legacy_MMIO_DMA64_BASE4      0x300
  72 #define B43legacy_MMIO_DMA64_BASE5      0x340
  73 /* PIO */
  74 #define B43legacy_MMIO_PIO1_BASE                0x300
  75 #define B43legacy_MMIO_PIO2_BASE                0x310
  76 #define B43legacy_MMIO_PIO3_BASE                0x320
  77 #define B43legacy_MMIO_PIO4_BASE                0x330
  78
  79 #define B43legacy_MMIO_PHY_VER          0x3E0
  80 #define B43legacy_MMIO_PHY_RADIO                0x3E2
  81 #define B43legacy_MMIO_PHY0             0x3E6
  82 #define B43legacy_MMIO_ANTENNA          0x3E8
  83 #define B43legacy_MMIO_CHANNEL          0x3F0
  84 #define B43legacy_MMIO_CHANNEL_EXT      0x3F4
  85 #define B43legacy_MMIO_RADIO_CONTROL    0x3F6
  86 #define B43legacy_MMIO_RADIO_DATA_HIGH  0x3F8
  87 #define B43legacy_MMIO_RADIO_DATA_LOW   0x3FA
  88 #define B43legacy_MMIO_PHY_CONTROL      0x3FC
  89 #define B43legacy_MMIO_PHY_DATA         0x3FE
  90 #define B43legacy_MMIO_MACFILTER_CONTROL        0x420
  91 #define B43legacy_MMIO_MACFILTER_DATA   0x422
  92 #define B43legacy_MMIO_RCMTA_COUNT      0x43C /* Receive Match Transmitter Addr */
  93 #define B43legacy_MMIO_RADIO_HWENABLED_LO       0x49A
  94 #define B43legacy_MMIO_GPIO_CONTROL     0x49C
  95 #define B43legacy_MMIO_GPIO_MASK                0x49E
  96 #define B43legacy_MMIO_TSF_0            0x632 /* core rev < 3 only */
  97 #define B43legacy_MMIO_TSF_1            0x634 /* core rev < 3 only */
  98 #define B43legacy_MMIO_TSF_2            0x636 /* core rev < 3 only */
  99 #define B43legacy_MMIO_TSF_3            0x638 /* core rev < 3 only */
 100 #define B43legacy_MMIO_RNG              0x65A
 101 #define B43legacy_MMIO_POWERUP_DELAY    0x6A8
 102
 103 /* SPROM boardflags_lo values */
 104 #define B43legacy_BFL_PACTRL            0x0002
 105 #define B43legacy_BFL_RSSI              0x0008
 106 #define B43legacy_BFL_EXTLNA            0x1000
 107
 108 /* GPIO register offset, in both ChipCommon and PCI core. */
 109 #define B43legacy_GPIO_CONTROL          0x6c
 110
 111 /* SHM Routing */
 112 #define B43legacy_SHM_SHARED            0x0001
 113 #define B43legacy_SHM_WIRELESS          0x0002
 114 #define B43legacy_SHM_HW                0x0004
 115 #define B43legacy_SHM_UCODE             0x0300
 116
 117 /* SHM Routing modifiers */
 118 #define B43legacy_SHM_AUTOINC_R         0x0200 /* Read Auto-increment */
 119 #define B43legacy_SHM_AUTOINC_W         0x0100 /* Write Auto-increment */
 120 #define B43legacy_SHM_AUTOINC_RW        (B43legacy_SHM_AUTOINC_R | \
 121                                          B43legacy_SHM_AUTOINC_W)
 122
 123 /* Misc SHM_SHARED offsets */
 124 #define B43legacy_SHM_SH_WLCOREREV      0x0016 /* 802.11 core revision */
 125 #define B43legacy_SHM_SH_HOSTFLO        0x005E /* Hostflags ucode opts (low) */
 126 #define B43legacy_SHM_SH_HOSTFHI        0x0060 /* Hostflags ucode opts (high) */
 127 /* SHM_SHARED crypto engine */
 128 #define B43legacy_SHM_SH_KEYIDXBLOCK    0x05D4 /* Key index/algorithm block */
 129 /* SHM_SHARED beacon variables */
 130 #define B43legacy_SHM_SH_BEACPHYCTL     0x0054 /* Beacon PHY TX control word */
 131 /* SHM_SHARED ACK/CTS control */
 132 #define B43legacy_SHM_SH_ACKCTSPHYCTL   0x0022 /* ACK/CTS PHY control word */
 133 /* SHM_SHARED probe response variables */
 134 #define B43legacy_SHM_SH_PRPHYCTL       0x0188 /* Probe Resp PHY TX control */
 135 #define B43legacy_SHM_SH_PRMAXTIME      0x0074 /* Probe Response max time */
 136 /* SHM_SHARED rate tables */
 137 /* SHM_SHARED microcode soft registers */
 138 #define B43legacy_SHM_SH_UCODEREV       0x0000 /* Microcode revision */
 139 #define B43legacy_SHM_SH_UCODEPATCH     0x0002 /* Microcode patchlevel */
 140 #define B43legacy_SHM_SH_UCODEDATE      0x0004 /* Microcode date */
 141 #define B43legacy_SHM_SH_UCODETIME      0x0006 /* Microcode time */
 142
 143 #define B43legacy_UCODEFLAGS_OFFSET     0x005E
 144
 145 /* Hardware Radio Enable masks */
 146 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 147 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 148
 149 /* HostFlags. See b43legacy_hf_read/write() */
 150 #define B43legacy_HF_SYMW               0x00000002 /* G-PHY SYM workaround */
 151 #define B43legacy_HF_GDCW               0x00000020 /* G-PHY DV cancel filter */
 152 #define B43legacy_HF_OFDMPABOOST        0x00000040 /* Enable PA boost OFDM */
 153 #define B43legacy_HF_EDCF               0x00000100 /* on if WME/MAC suspended */
 154
 155 /* MacFilter offsets. */
 156 #define B43legacy_MACFILTER_SELF        0x0000
 157 #define B43legacy_MACFILTER_BSSID       0x0003
 158 #define B43legacy_MACFILTER_MAC         0x0010
 159
 160 /* PHYVersioning */
 161 #define B43legacy_PHYTYPE_B             0x01
 162 #define B43legacy_PHYTYPE_G             0x02
 163
 164 /* PHYRegisters */
 165 #define B43legacy_PHY_G_LO_CONTROL      0x0810
 166 #define B43legacy_PHY_ILT_G_CTRL        0x0472
 167 #define B43legacy_PHY_ILT_G_DATA1       0x0473
 168 #define B43legacy_PHY_ILT_G_DATA2       0x0474
 169 #define B43legacy_PHY_G_PCTL            0x0029
 170 #define B43legacy_PHY_RADIO_BITFIELD    0x0401
 171 #define B43legacy_PHY_G_CRS             0x0429
 172 #define B43legacy_PHY_NRSSILT_CTRL      0x0803
 173 #define B43legacy_PHY_NRSSILT_DATA      0x0804
 174
 175 /* RadioRegisters */
 176 #define B43legacy_RADIOCTL_ID           0x01
 177
 178 /* MAC Control bitfield */
 179 #define B43legacy_MACCTL_ENABLED        0x00000001 /* MAC Enabled */
 180 #define B43legacy_MACCTL_PSM_RUN        0x00000002 /* Run Microcode */
 181 #define B43legacy_MACCTL_PSM_JMP0       0x00000004 /* Microcode jump to 0 */
 182 #define B43legacy_MACCTL_SHM_ENABLED    0x00000100 /* SHM Enabled */
 183 #define B43legacy_MACCTL_IHR_ENABLED    0x00000400 /* IHR Region Enabled */
 184 #define B43legacy_MACCTL_BE             0x00010000 /* Big Endian mode */
 185 #define B43legacy_MACCTL_INFRA          0x00020000 /* Infrastructure mode */
 186 #define B43legacy_MACCTL_AP             0x00040000 /* AccessPoint mode */
 187 #define B43legacy_MACCTL_RADIOLOCK      0x00080000 /* Radio lock */
 188 #define B43legacy_MACCTL_BEACPROMISC    0x00100000 /* Beacon Promiscuous */
 189 #define B43legacy_MACCTL_KEEP_BADPLCP   0x00200000 /* Keep bad PLCP frames */
 190 #define B43legacy_MACCTL_KEEP_CTL       0x00400000 /* Keep control frames */
 191 #define B43legacy_MACCTL_KEEP_BAD       0x00800000 /* Keep bad frames (FCS) */
 192 #define B43legacy_MACCTL_PROMISC        0x01000000 /* Promiscuous mode */
 193 #define B43legacy_MACCTL_HWPS           0x02000000 /* Hardware Power Saving */
 194 #define B43legacy_MACCTL_AWAKE          0x04000000 /* Device is awake */
 195 #define B43legacy_MACCTL_TBTTHOLD       0x10000000 /* TBTT Hold */
 196 #define B43legacy_MACCTL_GMODE          0x80000000 /* G Mode */
 197
 198 /* 802.11 core specific TM State Low flags */
 199 #define B43legacy_TMSLOW_GMODE          0x20000000 /* G Mode Enable */
 200 #define B43legacy_TMSLOW_PLLREFSEL      0x00200000 /* PLL Freq Ref Select */
 201 #define B43legacy_TMSLOW_MACPHYCLKEN    0x00100000 /* MAC PHY Clock Ctrl Enbl */
 202 #define B43legacy_TMSLOW_PHYRESET       0x00080000 /* PHY Reset */
 203 #define B43legacy_TMSLOW_PHYCLKEN       0x00040000 /* PHY Clock Enable */
 204
 205 /* 802.11 core specific TM State High flags */
 206 #define B43legacy_TMSHIGH_FCLOCK        0x00040000 /* Fast Clock Available */
 207 #define B43legacy_TMSHIGH_GPHY          0x00010000 /* G-PHY avail (rev >= 5) */
 208
 209 #define B43legacy_UCODEFLAG_AUTODIV       0x0001
 210
 211 /* Generic-Interrupt reasons. */
 212 #define B43legacy_IRQ_MAC_SUSPENDED     0x00000001
 213 #define B43legacy_IRQ_BEACON            0x00000002
 214 #define B43legacy_IRQ_TBTT_INDI         0x00000004 /* Target Beacon Transmit Time */
 215 #define B43legacy_IRQ_BEACON_TX_OK      0x00000008
 216 #define B43legacy_IRQ_BEACON_CANCEL     0x00000010
 217 #define B43legacy_IRQ_ATIM_END          0x00000020
 218 #define B43legacy_IRQ_PMQ               0x00000040
 219 #define B43legacy_IRQ_PIO_WORKAROUND    0x00000100
 220 #define B43legacy_IRQ_MAC_TXERR         0x00000200
 221 #define B43legacy_IRQ_PHY_TXERR         0x00000800
 222 #define B43legacy_IRQ_PMEVENT           0x00001000
 223 #define B43legacy_IRQ_TIMER0            0x00002000
 224 #define B43legacy_IRQ_TIMER1            0x00004000
 225 #define B43legacy_IRQ_DMA               0x00008000
 226 #define B43legacy_IRQ_TXFIFO_FLUSH_OK   0x00010000
 227 #define B43legacy_IRQ_CCA_MEASURE_OK    0x00020000
 228 #define B43legacy_IRQ_NOISESAMPLE_OK    0x00040000
 229 #define B43legacy_IRQ_UCODE_DEBUG       0x08000000
 230 #define B43legacy_IRQ_RFKILL            0x10000000
 231 #define B43legacy_IRQ_TX_OK             0x20000000
 232 #define B43legacy_IRQ_PHY_G_CHANGED     0x40000000
 233 #define B43legacy_IRQ_TIMEOUT           0x80000000
 234
 235 #define B43legacy_IRQ_ALL               0xFFFFFFFF
 236 #define B43legacy_IRQ_MASKTEMPLATE      (B43legacy_IRQ_MAC_SUSPENDED |  \
 237                                          B43legacy_IRQ_BEACON |         \
 238                                          B43legacy_IRQ_TBTT_INDI |      \
 239                                          B43legacy_IRQ_ATIM_END |       \
 240                                          B43legacy_IRQ_PMQ |            \
 241                                          B43legacy_IRQ_MAC_TXERR |      \
 242                                          B43legacy_IRQ_PHY_TXERR |      \
 243                                          B43legacy_IRQ_DMA |            \
 244                                          B43legacy_IRQ_TXFIFO_FLUSH_OK | \
 245                                          B43legacy_IRQ_NOISESAMPLE_OK | \
 246                                          B43legacy_IRQ_UCODE_DEBUG |    \
 247                                          B43legacy_IRQ_RFKILL |         \
 248                                          B43legacy_IRQ_TX_OK)
 249
 250 /* Device specific rate values.
 251  * The actual values defined here are (rate_in_mbps * 2).
 252  * Some code depends on this. Don't change it. */
 253 #define B43legacy_CCK_RATE_1MB          2
 254 #define B43legacy_CCK_RATE_2MB          4
 255 #define B43legacy_CCK_RATE_5MB          11
 256 #define B43legacy_CCK_RATE_11MB         22
 257 #define B43legacy_OFDM_RATE_6MB         12
 258 #define B43legacy_OFDM_RATE_9MB         18
 259 #define B43legacy_OFDM_RATE_12MB        24
 260 #define B43legacy_OFDM_RATE_18MB        36
 261 #define B43legacy_OFDM_RATE_24MB        48
 262 #define B43legacy_OFDM_RATE_36MB        72
 263 #define B43legacy_OFDM_RATE_48MB        96
 264 #define B43legacy_OFDM_RATE_54MB        108
 265 /* Convert a b43legacy rate value to a rate in 100kbps */
 266 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
 267
 268
 269 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT     7
 270 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT      4
 271
 272 #define B43legacy_PHY_TX_BADNESS_LIMIT          1000
 273
 274 /* Max size of a security key */
 275 #define B43legacy_SEC_KEYSIZE           16
 276 /* Security algorithms. */
 277 enum {
 278         B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 279         B43legacy_SEC_ALGO_WEP40,
 280         B43legacy_SEC_ALGO_TKIP,
 281         B43legacy_SEC_ALGO_AES,
 282         B43legacy_SEC_ALGO_WEP104,
 283         B43legacy_SEC_ALGO_AES_LEGACY,
 284 };
 285
 286 /* Core Information Registers */
 287 #define B43legacy_CIR_BASE                0xf00
 288 #define B43legacy_CIR_SBTPSFLAG           (B43legacy_CIR_BASE + 0x18)
 289 #define B43legacy_CIR_SBIMSTATE           (B43legacy_CIR_BASE + 0x90)
 290 #define B43legacy_CIR_SBINTVEC            (B43legacy_CIR_BASE + 0x94)
 291 #define B43legacy_CIR_SBTMSTATELOW        (B43legacy_CIR_BASE + 0x98)
 292 #define B43legacy_CIR_SBTMSTATEHIGH       (B43legacy_CIR_BASE + 0x9c)
 293 #define B43legacy_CIR_SBIMCONFIGLOW       (B43legacy_CIR_BASE + 0xa8)
 294 #define B43legacy_CIR_SB_ID_HI            (B43legacy_CIR_BASE + 0xfc)
 295
 296 /* sbtmstatehigh state flags */
 297 #define B43legacy_SBTMSTATEHIGH_SERROR          0x00000001
 298 #define B43legacy_SBTMSTATEHIGH_BUSY            0x00000004
 299 #define B43legacy_SBTMSTATEHIGH_TIMEOUT         0x00000020
 300 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL     0x00010000
 301 #define B43legacy_SBTMSTATEHIGH_COREFLAGS       0x1FFF0000
 302 #define B43legacy_SBTMSTATEHIGH_DMA64BIT        0x10000000
 303 #define B43legacy_SBTMSTATEHIGH_GATEDCLK        0x20000000
 304 #define B43legacy_SBTMSTATEHIGH_BISTFAILED      0x40000000
 305 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE    0x80000000
 306
 307 /* sbimstate flags */
 308 #define B43legacy_SBIMSTATE_IB_ERROR            0x20000
 309 #define B43legacy_SBIMSTATE_TIMEOUT             0x40000
 310
 311 #define PFX             KBUILD_MODNAME ": "
 312 #ifdef assert
 313 # undef assert
 314 #endif
 315 #ifdef CONFIG_B43LEGACY_DEBUG
 316 # define B43legacy_WARN_ON(expr)                                        \
 317         do {                                                            \
 318                 if (unlikely((expr))) {                                 \
 319                         printk(KERN_INFO PFX "Test (%s) failed at:"     \
 320                                               " %s:%d:%s()\n",          \
 321                                               #expr, __FILE__,          \
 322                                               __LINE__, __FUNCTION__);  \
 323                 }                                                       \
 324         } while (0)
 325 # define B43legacy_BUG_ON(expr)                                         \
 326         do {                                                            \
 327                 if (unlikely((expr))) {                                 \
 328                         printk(KERN_INFO PFX "Test (%s) failed\n",      \
 329                                               #expr);                   \
 330                         BUG_ON(expr);                                   \
 331                 }                                                       \
 332         } while (0)
 333 # define B43legacy_DEBUG        1
 334 #else
 335 # define B43legacy_WARN_ON(x)   do { /* nothing */ } while (0)
 336 # define B43legacy_BUG_ON(x)    do { /* nothing */ } while (0)
 337 # define B43legacy_DEBUG        0
 338 #endif
 339
 340
 341 struct net_device;
 342 struct pci_dev;
 343 struct b43legacy_dmaring;
 344 struct b43legacy_pioqueue;
 345
 346 /* The firmware file header */
 347 #define B43legacy_FW_TYPE_UCODE 'u'
 348 #define B43legacy_FW_TYPE_PCM   'p'
 349 #define B43legacy_FW_TYPE_IV    'i'
 350 struct b43legacy_fw_header {
 351         /* File type */
 352         u8 type;
 353         /* File format version */
 354         u8 ver;
 355         u8 __padding[2];
 356         /* Size of the data. For ucode and PCM this is in bytes.
 357          * For IV this is number-of-ivs. */
 358         __be32 size;
 359 } __attribute__((__packed__));
 360
 361 /* Initial Value file format */
 362 #define B43legacy_IV_OFFSET_MASK        0x7FFF
 363 #define B43legacy_IV_32BIT              0x8000
 364 struct b43legacy_iv {
 365         __be16 offset_size;
 366         union {
 367                 __be16 d16;
 368                 __be32 d32;
 369         } data __attribute__((__packed__));
 370 } __attribute__((__packed__));
 371
 372 #define B43legacy_PHYMODE(phytype)      (1 << (phytype))
 373 #define B43legacy_PHYMODE_B             B43legacy_PHYMODE       \
 374                                         ((B43legacy_PHYTYPE_B))
 375 #define B43legacy_PHYMODE_G             B43legacy_PHYMODE       \
 376                                         ((B43legacy_PHYTYPE_G))
 377
 378 /* Value pair to measure the LocalOscillator. */
 379 struct b43legacy_lopair {
 380         s8 low;
 381         s8 high;
 382         u8 used:1;
 383 };
 384 #define B43legacy_LO_COUNT      (14*4)
 385
 386 struct b43legacy_phy {
 387         /* Possible PHYMODEs on this PHY */
 388         u8 possible_phymodes;
 389         /* GMODE bit enabled in MACCTL? */
 390         bool gmode;
 391         /* Possible ieee80211 subsystem hwmodes for this PHY.
 392          * Which mode is selected, depends on thr GMODE enabled bit */
 393 #define B43legacy_MAX_PHYHWMODES        2
 394         struct ieee80211_hw_mode hwmodes[B43legacy_MAX_PHYHWMODES];
 395
 396         /* Analog Type */
 397         u8 analog;
 398         /* B43legacy_PHYTYPE_ */
 399         u8 type;
 400         /* PHY revision number. */
 401         u8 rev;
 402
 403         u16 antenna_diversity;
 404         u16 savedpctlreg;
 405         /* Radio versioning */
 406         u16 radio_manuf;        /* Radio manufacturer */
 407         u16 radio_ver;          /* Radio version */
 408         u8 calibrated:1;
 409         u8 radio_rev;           /* Radio revision */
 410
 411         bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 412
 413         /* ACI (adjacent channel interference) flags. */
 414         bool aci_enable;
 415         bool aci_wlan_automatic;
 416         bool aci_hw_rssi;
 417
 418         /* Radio switched on/off */
 419         bool radio_on;
 420         struct {
 421                 /* Values saved when turning the radio off.
 422                  * They are needed when turning it on again. */
 423                 bool valid;
 424                 u16 rfover;
 425                 u16 rfoverval;
 426         } radio_off_context;
 427
 428         u16 minlowsig[2];
 429         u16 minlowsigpos[2];
 430
 431         /* LO Measurement Data.
 432          * Use b43legacy_get_lopair() to get a value.
 433          */
 434         struct b43legacy_lopair *_lo_pairs;
 435         /* TSSI to dBm table in use */
 436         const s8 *tssi2dbm;
 437         /* idle TSSI value */
 438         s8 idle_tssi;
 439         /* Target idle TSSI */
 440         int tgt_idle_tssi;
 441         /* Current idle TSSI */
 442         int cur_idle_tssi;
 443
 444         /* LocalOscillator control values. */
 445         struct b43legacy_txpower_lo_control *lo_control;
 446         /* Values from b43legacy_calc_loopback_gain() */
 447         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 448         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 449         s16 lna_lod_gain;       /* LNA lod */
 450         s16 lna_gain;           /* LNA */
 451         s16 pga_gain;           /* PGA */
 452
 453         /* Desired TX power level (in dBm). This is set by the user and
 454          * adjusted in b43legacy_phy_xmitpower(). */
 455         u8 power_level;
 456
 457         /* Values from b43legacy_calc_loopback_gain() */
 458         u16 loopback_gain[2];
 459
 460         /* TX Power control values. */
 461         /* B/G PHY */
 462         struct {
 463                 /* Current Radio Attenuation for TXpower recalculation. */
 464                 u16 rfatt;
 465                 /* Current Baseband Attenuation for TXpower recalculation. */
 466                 u16 bbatt;
 467                 /* Current TXpower control value for TXpower recalculation. */
 468                 u16 txctl1;
 469                 u16 txctl2;
 470         };
 471         /* A PHY */
 472         struct {
 473                 u16 txpwr_offset;
 474         };
 475
 476         /* Current Interference Mitigation mode */
 477         int interfmode;
 478         /* Stack of saved values from the Interference Mitigation code.
 479          * Each value in the stack is layed out as follows:
 480          * bit 0-11:  offset
 481          * bit 12-15: register ID
 482          * bit 16-32: value
 483          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 484          */
 485 #define B43legacy_INTERFSTACK_SIZE      26
 486         u32 interfstack[B43legacy_INTERFSTACK_SIZE];
 487
 488         /* Saved values from the NRSSI Slope calculation */
 489         s16 nrssi[2];
 490         s32 nrssislope;
 491         /* In memory nrssi lookup table. */
 492         s8 nrssi_lt[64];
 493
 494         /* current channel */
 495         u8 channel;
 496
 497         u16 lofcal;
 498
 499         u16 initval;
 500
 501         /* PHY TX errors counter. */
 502         atomic_t txerr_cnt;
 503
 504 #if B43legacy_DEBUG
 505         /* Manual TX-power control enabled? */
 506         bool manual_txpower_control;
 507         /* PHY registers locked by b43legacy_phy_lock()? */
 508         bool phy_locked;
 509 #endif /* B43legacy_DEBUG */
 510 };
 511
 512 /* Data structures for DMA transmission, per 80211 core. */
 513 struct b43legacy_dma {
 514         struct b43legacy_dmaring *tx_ring0;
 515         struct b43legacy_dmaring *tx_ring1;
 516         struct b43legacy_dmaring *tx_ring2;
 517         struct b43legacy_dmaring *tx_ring3;
 518         struct b43legacy_dmaring *tx_ring4;
 519         struct b43legacy_dmaring *tx_ring5;
 520
 521         struct b43legacy_dmaring *rx_ring0;
 522         struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
 523 };
 524
 525 /* Data structures for PIO transmission, per 80211 core. */
 526 struct b43legacy_pio {
 527         struct b43legacy_pioqueue *queue0;
 528         struct b43legacy_pioqueue *queue1;
 529         struct b43legacy_pioqueue *queue2;
 530         struct b43legacy_pioqueue *queue3;
 531 };
 532
 533 /* Context information for a noise calculation (Link Quality). */
 534 struct b43legacy_noise_calculation {
 535         u8 channel_at_start;
 536         bool calculation_running;
 537         u8 nr_samples;
 538         s8 samples[8][4];
 539 };
 540
 541 struct b43legacy_stats {
 542         u8 link_noise;
 543         /* Store the last TX/RX times here for updating the leds. */
 544         unsigned long last_tx;
 545         unsigned long last_rx;
 546 };
 547
 548 struct b43legacy_key {
 549         void *keyconf;
 550         bool enabled;
 551         u8 algorithm;
 552 };
 553
 554 struct b43legacy_wldev;
 555
 556 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
 557 struct b43legacy_wl {
 558         /* Pointer to the active wireless device on this chip */
 559         struct b43legacy_wldev *current_dev;
 560         /* Pointer to the ieee80211 hardware data structure */
 561         struct ieee80211_hw *hw;
 562
 563         spinlock_t irq_lock;            /* locks IRQ */
 564         struct mutex mutex;             /* locks wireless core state */
 565         spinlock_t leds_lock;           /* lock for leds */
 566
 567         /* We can only have one operating interface (802.11 core)
 568          * at a time. General information about this interface follows.
 569          */
 570
 571         struct ieee80211_vif *vif;
 572         /* MAC address (can be NULL). */
 573         u8 mac_addr[ETH_ALEN];
 574         /* Current BSSID (can be NULL). */
 575         u8 bssid[ETH_ALEN];
 576         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 577         int if_type;
 578         /* Is the card operating in AP, STA or IBSS mode? */
 579         bool operating;
 580         /* filter flags */
 581         unsigned int filter_flags;
 582         /* Stats about the wireless interface */
 583         struct ieee80211_low_level_stats ieee_stats;
 584
 585         struct hwrng rng;
 586         u8 rng_initialized;
 587         char rng_name[30 + 1];
 588
 589         /* The RF-kill button */
 590         struct b43legacy_rfkill rfkill;
 591
 592         /* List of all wireless devices on this chip */
 593         struct list_head devlist;
 594         u8 nr_devs;
 595
 596         bool radiotap_enabled;
 597 };
 598
 599 /* Pointers to the firmware data and meta information about it. */
 600 struct b43legacy_firmware {
 601         /* Microcode */
 602         const struct firmware *ucode;
 603         /* PCM code */
 604         const struct firmware *pcm;
 605         /* Initial MMIO values for the firmware */
 606         const struct firmware *initvals;
 607         /* Initial MMIO values for the firmware, band-specific */
 608         const struct firmware *initvals_band;
 609         /* Firmware revision */
 610         u16 rev;
 611         /* Firmware patchlevel */
 612         u16 patch;
 613 };
 614
 615 /* Device (802.11 core) initialization status. */
 616 enum {
 617         B43legacy_STAT_UNINIT           = 0, /* Uninitialized. */
 618         B43legacy_STAT_INITIALIZED      = 1, /* Initialized, not yet started. */
 619         B43legacy_STAT_STARTED  = 2, /* Up and running. */
 620 };
 621 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
 622 #define b43legacy_set_status(wldev, stat)       do {            \
 623                 atomic_set(&(wldev)->__init_status, (stat));    \
 624                 smp_wmb();                                      \
 625                                         } while (0)
 626
 627 /* *** ---   HOW LOCKING WORKS IN B43legacy   --- ***
 628  *
 629  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 630  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 631  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 632  *   and packet TX path (and _ONLY_ there.)
 633  */
 634
 635 /* Data structure for one wireless device (802.11 core) */
 636 struct b43legacy_wldev {
 637         struct ssb_device *dev;
 638         struct b43legacy_wl *wl;
 639
 640         /* The device initialization status.
 641          * Use b43legacy_status() to query. */
 642         atomic_t __init_status;
 643         /* Saved init status for handling suspend. */
 644         int suspend_init_status;
 645
 646         bool __using_pio;       /* Using pio rather than dma. */
 647         bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
 648         bool reg124_set_0x4;    /* Variable to keep track of IRQ. */
 649         bool short_preamble;    /* TRUE if using short preamble. */
 650         bool short_slot;        /* TRUE if using short slot timing. */
 651         bool radio_hw_enable;   /* State of radio hardware enable bit. */
 652
 653         /* PHY/Radio device. */
 654         struct b43legacy_phy phy;
 655         union {
 656                 /* DMA engines. */
 657                 struct b43legacy_dma dma;
 658                 /* PIO engines. */
 659                 struct b43legacy_pio pio;
 660         };
 661
 662         /* Various statistics about the physical device. */
 663         struct b43legacy_stats stats;
 664
 665         /* The device LEDs. */
 666         struct b43legacy_led led_tx;
 667         struct b43legacy_led led_rx;
 668         struct b43legacy_led led_assoc;
 669         struct b43legacy_led led_radio;
 670
 671         /* Reason code of the last interrupt. */
 672         u32 irq_reason;
 673         u32 dma_reason[6];
 674         /* saved irq enable/disable state bitfield. */
 675         u32 irq_savedstate;
 676         /* Link Quality calculation context. */
 677         struct b43legacy_noise_calculation noisecalc;
 678         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 679         int mac_suspended;
 680
 681         /* Interrupt Service Routine tasklet (bottom-half) */
 682         struct tasklet_struct isr_tasklet;
 683
 684         /* Periodic tasks */
 685         struct delayed_work periodic_work;
 686         unsigned int periodic_state;
 687
 688         struct work_struct restart_work;
 689
 690         /* encryption/decryption */
 691         u16 ktp; /* Key table pointer */
 692         u8 max_nr_keys;
 693         struct b43legacy_key key[58];
 694
 695         /* Cached beacon template while uploading the template. */
 696         struct sk_buff *cached_beacon;
 697
 698         /* Firmware data */
 699         struct b43legacy_firmware fw;
 700
 701         /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
 702         struct list_head list;
 703
 704         /* Debugging stuff follows. */
 705 #ifdef CONFIG_B43LEGACY_DEBUG
 706         struct b43legacy_dfsentry *dfsentry;
 707 #endif
 708 };
 709
 710
 711 static inline
 712 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
 713 {
 714         return hw->priv;
 715 }
 716
 717 /* Helper function, which returns a boolean.
 718  * TRUE, if PIO is used; FALSE, if DMA is used.
 719  */
 720 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
 721 static inline
 722 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 723 {
 724         return dev->__using_pio;
 725 }
 726 #elif defined(CONFIG_B43LEGACY_DMA)
 727 static inline
 728 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 729 {
 730         return 0;
 731 }
 732 #elif defined(CONFIG_B43LEGACY_PIO)
 733 static inline
 734 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 735 {
 736         return 1;
 737 }
 738 #else
 739 # error "Using neither DMA nor PIO? Confused..."
 740 #endif
 741
 742
 743 static inline
 744 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
 745 {
 746         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 747         return ssb_get_drvdata(ssb_dev);
 748 }
 749
 750 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 751 static inline
 752 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
 753 {
 754         return (wl->operating &&
 755                 wl->if_type == type);
 756 }
 757
 758 static inline
 759 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
 760 {
 761         return  (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
 762 }
 763
 764 static inline
 765 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
 766 {
 767         return ssb_read16(dev->dev, offset);
 768 }
 769
 770 static inline
 771 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
 772 {
 773         ssb_write16(dev->dev, offset, value);
 774 }
 775
 776 static inline
 777 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
 778 {
 779         return ssb_read32(dev->dev, offset);
 780 }
 781
 782 static inline
 783 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
 784 {
 785         ssb_write32(dev->dev, offset, value);
 786 }
 787
 788 static inline
 789 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
 790                                               u16 radio_attenuation,
 791                                               u16 baseband_attenuation)
 792 {
 793         return phy->_lo_pairs + (radio_attenuation
 794                         + 14 * (baseband_attenuation / 2));
 795 }
 796
 797
 798
 799 /* Message printing */
 800 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 801                 __attribute__((format(printf, 2, 3)));
 802 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 803                 __attribute__((format(printf, 2, 3)));
 804 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 805                 __attribute__((format(printf, 2, 3)));
 806 #if B43legacy_DEBUG
 807 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 808                 __attribute__((format(printf, 2, 3)));
 809 #else /* DEBUG */
 810 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
 811 #endif /* DEBUG */
 812
 813
 814 /** Limit a value between two limits */
 815 #ifdef limit_value
 816 # undef limit_value
 817 #endif
 818 #define limit_value(value, min, max)  \
 819         ({                                              \
 820                 typeof(value) __value = (value);        \
 821                 typeof(value) __min = (min);            \
 822                 typeof(value) __max = (max);            \
 823                 if (__value < __min)                    \
 824                         __value = __min;                \
 825                 else if (__value > __max)               \
 826                         __value = __max;                \
 827                 __value;                                \
 828         })
 829
 830 /* Macros for printing a value in Q5.2 format */
 831 #define Q52_FMT         "%u.%u"
 832 #define Q52_ARG(q52)    ((q52) / 4), (((q52) & 3) * 100 / 4)
 833
 834 #endif /* B43legacy_H_ */