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ath5k: more RF2413 stuff
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath5k / phy.c
1 /*
2 * PHY functions
3 *
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 #include <linux/delay.h>
23
24 #include "ath5k.h"
25 #include "reg.h"
26 #include "base.h"
27
28 /* Struct to hold initial RF register values (RF Banks) */
29 struct ath5k_ini_rf {
30 u8 rf_bank; /* check out ath5k_reg.h */
31 u16 rf_register; /* register address */
32 u32 rf_value[5]; /* register value for different modes (above) */
33 };
34
35 /*
36 * Mode-specific RF Gain table (64bytes) for RF5111/5112
37 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
38 * RF Gain values are included in AR5K_AR5210_INI)
39 */
40 struct ath5k_ini_rfgain {
41 u16 rfg_register; /* RF Gain register address */
42 u32 rfg_value[2]; /* [freq (see below)] */
43 };
44
45 struct ath5k_gain_opt {
46 u32 go_default;
47 u32 go_steps_count;
48 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
49 };
50
51 /* RF5111 mode-specific init registers */
52 static const struct ath5k_ini_rf rfregs_5111[] = {
53 { 0, 0x989c,
54 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
55 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
56 { 0, 0x989c,
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58 { 0, 0x989c,
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60 { 0, 0x989c,
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62 { 0, 0x989c,
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64 { 0, 0x989c,
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66 { 0, 0x989c,
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68 { 0, 0x989c,
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70 { 0, 0x989c,
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72 { 0, 0x989c,
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74 { 0, 0x989c,
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76 { 0, 0x989c,
77 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
78 { 0, 0x989c,
79 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
80 { 0, 0x989c,
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82 { 0, 0x989c,
83 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
84 { 0, 0x989c,
85 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
86 { 0, 0x98d4,
87 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
88 { 1, 0x98d4,
89 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
90 { 2, 0x98d4,
91 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
92 { 3, 0x98d8,
93 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
94 { 6, 0x989c,
95 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
96 { 6, 0x989c,
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98 { 6, 0x989c,
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100 { 6, 0x989c,
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102 { 6, 0x989c,
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104 { 6, 0x989c,
105 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
106 { 6, 0x989c,
107 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
108 { 6, 0x989c,
109 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
110 { 6, 0x989c,
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112 { 6, 0x989c,
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114 { 6, 0x989c,
115 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
116 { 6, 0x989c,
117 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
118 { 6, 0x989c,
119 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
120 { 6, 0x989c,
121 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
122 { 6, 0x989c,
123 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
124 { 6, 0x989c,
125 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
126 { 6, 0x98d4,
127 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
128 { 7, 0x989c,
129 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
130 { 7, 0x989c,
131 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
132 { 7, 0x989c,
133 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
134 { 7, 0x989c,
135 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
136 { 7, 0x989c,
137 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
138 { 7, 0x989c,
139 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
140 { 7, 0x989c,
141 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
142 { 7, 0x98cc,
143 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
144 };
145
146 /* Initial RF Gain settings for RF5111 */
147 static const struct ath5k_ini_rfgain rfgain_5111[] = {
148 /* 5Ghz 2Ghz */
149 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
150 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
151 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
152 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
153 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
154 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
155 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
156 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
157 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
158 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
159 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
160 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
161 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
162 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
163 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
164 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
165 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
166 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
167 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
168 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
169 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
170 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
171 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
172 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
173 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
174 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
175 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
176 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
177 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
178 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
179 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
180 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
181 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
182 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
183 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
184 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
185 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
186 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
187 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
188 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
189 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
190 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
191 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
192 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
193 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
194 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
195 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
196 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
197 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
198 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
199 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
200 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
201 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
213 };
214
215 static const struct ath5k_gain_opt rfgain_opt_5111 = {
216 4,
217 9,
218 {
219 { { 4, 1, 1, 1 }, 6 },
220 { { 4, 0, 1, 1 }, 4 },
221 { { 3, 1, 1, 1 }, 3 },
222 { { 4, 0, 0, 1 }, 1 },
223 { { 4, 1, 1, 0 }, 0 },
224 { { 4, 0, 1, 0 }, -2 },
225 { { 3, 1, 1, 0 }, -3 },
226 { { 4, 0, 0, 0 }, -4 },
227 { { 2, 1, 1, 0 }, -6 }
228 }
229 };
230
231 /* RF5112 mode-specific init registers */
232 static const struct ath5k_ini_rf rfregs_5112[] = {
233 { 1, 0x98d4,
234 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
235 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
236 { 2, 0x98d0,
237 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
238 { 3, 0x98dc,
239 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
240 { 6, 0x989c,
241 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
242 { 6, 0x989c,
243 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
244 { 6, 0x989c,
245 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
246 { 6, 0x989c,
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248 { 6, 0x989c,
249 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
250 { 6, 0x989c,
251 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
252 { 6, 0x989c,
253 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
254 { 6, 0x989c,
255 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
256 { 6, 0x989c,
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258 { 6, 0x989c,
259 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
260 { 6, 0x989c,
261 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
262 { 6, 0x989c,
263 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
264 { 6, 0x989c,
265 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
266 { 6, 0x989c,
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268 { 6, 0x989c,
269 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
270 { 6, 0x989c,
271 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
272 { 6, 0x989c,
273 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
274 { 6, 0x989c,
275 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
276 { 6, 0x989c,
277 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
278 { 6, 0x989c,
279 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
280 { 6, 0x989c,
281 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
282 { 6, 0x989c,
283 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
284 { 6, 0x989c,
285 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
286 { 6, 0x989c,
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288 { 6, 0x989c,
289 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
290 { 6, 0x989c,
291 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
292 { 6, 0x989c,
293 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
294 { 6, 0x989c,
295 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
296 { 6, 0x989c,
297 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
298 { 6, 0x989c,
299 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
300 { 6, 0x989c,
301 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
302 { 6, 0x989c,
303 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
304 { 6, 0x989c,
305 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
306 { 6, 0x989c,
307 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
308 { 6, 0x989c,
309 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
310 { 6, 0x989c,
311 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
312 { 6, 0x989c,
313 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
314 { 6, 0x98d0,
315 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
316 { 7, 0x989c,
317 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
318 { 7, 0x989c,
319 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
320 { 7, 0x989c,
321 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
322 { 7, 0x989c,
323 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
324 { 7, 0x989c,
325 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
326 { 7, 0x989c,
327 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
328 { 7, 0x989c,
329 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
330 { 7, 0x989c,
331 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
332 { 7, 0x989c,
333 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
334 { 7, 0x989c,
335 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
336 { 7, 0x989c,
337 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
338 { 7, 0x989c,
339 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
340 { 7, 0x98c4,
341 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
342 };
343
344 /* RF5112A mode-specific init registers */
345 static const struct ath5k_ini_rf rfregs_5112a[] = {
346 { 1, 0x98d4,
347 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
348 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
349 { 2, 0x98d0,
350 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
351 { 3, 0x98dc,
352 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
353 { 6, 0x989c,
354 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
355 { 6, 0x989c,
356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
357 { 6, 0x989c,
358 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
359 { 6, 0x989c,
360 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
361 { 6, 0x989c,
362 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
363 { 6, 0x989c,
364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
365 { 6, 0x989c,
366 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
367 { 6, 0x989c,
368 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
369 { 6, 0x989c,
370 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
371 { 6, 0x989c,
372 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
373 { 6, 0x989c,
374 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
375 { 6, 0x989c,
376 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
377 { 6, 0x989c,
378 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
379 { 6, 0x989c,
380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
381 { 6, 0x989c,
382 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
383 { 6, 0x989c,
384 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
385 { 6, 0x989c,
386 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
387 { 6, 0x989c,
388 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
389 { 6, 0x989c,
390 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
391 { 6, 0x989c,
392 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
393 { 6, 0x989c,
394 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
395 { 6, 0x989c,
396 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
397 { 6, 0x989c,
398 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
399 { 6, 0x989c,
400 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
401 { 6, 0x989c,
402 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
403 { 6, 0x989c,
404 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
405 { 6, 0x989c,
406 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
407 { 6, 0x989c,
408 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
409 { 6, 0x989c,
410 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
411 { 6, 0x989c,
412 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
413 { 6, 0x989c,
414 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
415 { 6, 0x989c,
416 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
417 { 6, 0x989c,
418 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
419 { 6, 0x989c,
420 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
421 { 6, 0x989c,
422 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
423 { 6, 0x989c,
424 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
425 { 6, 0x989c,
426 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
427 { 6, 0x989c,
428 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
429 { 6, 0x989c,
430 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
431 { 6, 0x98d8,
432 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
433 { 7, 0x989c,
434 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
435 { 7, 0x989c,
436 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
437 { 7, 0x989c,
438 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
439 { 7, 0x989c,
440 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
441 { 7, 0x989c,
442 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
443 { 7, 0x989c,
444 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
445 { 7, 0x989c,
446 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
447 { 7, 0x989c,
448 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
449 { 7, 0x989c,
450 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
451 { 7, 0x989c,
452 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
453 { 7, 0x989c,
454 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
455 { 7, 0x989c,
456 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
457 { 7, 0x98c4,
458 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
459 };
460
461
462 static const struct ath5k_ini_rf rfregs_2112a[] = {
463 { 1, AR5K_RF_BUFFER_CONTROL_4,
464 /* mode b mode g mode gTurbo */
465 { 0x00000020, 0x00000020, 0x00000020 } },
466 { 2, AR5K_RF_BUFFER_CONTROL_3,
467 { 0x03060408, 0x03060408, 0x03070408 } },
468 { 3, AR5K_RF_BUFFER_CONTROL_6,
469 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
470 { 6, AR5K_RF_BUFFER,
471 { 0x0a000000, 0x0a000000, 0x0a000000 } },
472 { 6, AR5K_RF_BUFFER,
473 { 0x00000000, 0x00000000, 0x00000000 } },
474 { 6, AR5K_RF_BUFFER,
475 { 0x00800000, 0x00800000, 0x00800000 } },
476 { 6, AR5K_RF_BUFFER,
477 { 0x002a0000, 0x002a0000, 0x002a0000 } },
478 { 6, AR5K_RF_BUFFER,
479 { 0x00010000, 0x00010000, 0x00010000 } },
480 { 6, AR5K_RF_BUFFER,
481 { 0x00000000, 0x00000000, 0x00000000 } },
482 { 6, AR5K_RF_BUFFER,
483 { 0x00180000, 0x00180000, 0x00180000 } },
484 { 6, AR5K_RF_BUFFER,
485 { 0x006e0000, 0x006e0000, 0x006e0000 } },
486 { 6, AR5K_RF_BUFFER,
487 { 0x00c70000, 0x00c70000, 0x00c70000 } },
488 { 6, AR5K_RF_BUFFER,
489 { 0x004b0000, 0x004b0000, 0x004b0000 } },
490 { 6, AR5K_RF_BUFFER,
491 { 0x04480000, 0x04480000, 0x04480000 } },
492 { 6, AR5K_RF_BUFFER,
493 { 0x002a0000, 0x002a0000, 0x002a0000 } },
494 { 6, AR5K_RF_BUFFER,
495 { 0x00e40000, 0x00e40000, 0x00e40000 } },
496 { 6, AR5K_RF_BUFFER,
497 { 0x00000000, 0x00000000, 0x00000000 } },
498 { 6, AR5K_RF_BUFFER,
499 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
500 { 6, AR5K_RF_BUFFER,
501 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
502 { 6, AR5K_RF_BUFFER,
503 { 0x043f0000, 0x043f0000, 0x043f0000 } },
504 { 6, AR5K_RF_BUFFER,
505 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
506 { 6, AR5K_RF_BUFFER,
507 { 0x02190000, 0x02190000, 0x02190000 } },
508 { 6, AR5K_RF_BUFFER,
509 { 0x00240000, 0x00240000, 0x00240000 } },
510 { 6, AR5K_RF_BUFFER,
511 { 0x00b40000, 0x00b40000, 0x00b40000 } },
512 { 6, AR5K_RF_BUFFER,
513 { 0x00990000, 0x00990000, 0x00990000 } },
514 { 6, AR5K_RF_BUFFER,
515 { 0x00500000, 0x00500000, 0x00500000 } },
516 { 6, AR5K_RF_BUFFER,
517 { 0x002a0000, 0x002a0000, 0x002a0000 } },
518 { 6, AR5K_RF_BUFFER,
519 { 0x00120000, 0x00120000, 0x00120000 } },
520 { 6, AR5K_RF_BUFFER,
521 { 0xc0320000, 0xc0320000, 0xc0320000 } },
522 { 6, AR5K_RF_BUFFER,
523 { 0x01740000, 0x01740000, 0x01740000 } },
524 { 6, AR5K_RF_BUFFER,
525 { 0x00110000, 0x00110000, 0x00110000 } },
526 { 6, AR5K_RF_BUFFER,
527 { 0x86280000, 0x86280000, 0x86280000 } },
528 { 6, AR5K_RF_BUFFER,
529 { 0x31840000, 0x31840000, 0x31840000 } },
530 { 6, AR5K_RF_BUFFER,
531 { 0x00f20080, 0x00f20080, 0x00f20080 } },
532 { 6, AR5K_RF_BUFFER,
533 { 0x00070019, 0x00070019, 0x00070019 } },
534 { 6, AR5K_RF_BUFFER,
535 { 0x00000000, 0x00000000, 0x00000000 } },
536 { 6, AR5K_RF_BUFFER,
537 { 0x00000000, 0x00000000, 0x00000000 } },
538 { 6, AR5K_RF_BUFFER,
539 { 0x000000b2, 0x000000b2, 0x000000b2 } },
540 { 6, AR5K_RF_BUFFER,
541 { 0x00b02184, 0x00b02184, 0x00b02184 } },
542 { 6, AR5K_RF_BUFFER,
543 { 0x004125a4, 0x004125a4, 0x004125a4 } },
544 { 6, AR5K_RF_BUFFER,
545 { 0x00119220, 0x00119220, 0x00119220 } },
546 { 6, AR5K_RF_BUFFER,
547 { 0x001a4800, 0x001a4800, 0x001a4800 } },
548 { 6, AR5K_RF_BUFFER_CONTROL_5,
549 { 0x000b0230, 0x000b0230, 0x000b0230 } },
550 { 7, AR5K_RF_BUFFER,
551 { 0x00000094, 0x00000094, 0x00000094 } },
552 { 7, AR5K_RF_BUFFER,
553 { 0x00000091, 0x00000091, 0x00000091 } },
554 { 7, AR5K_RF_BUFFER,
555 { 0x00000012, 0x00000012, 0x00000012 } },
556 { 7, AR5K_RF_BUFFER,
557 { 0x00000080, 0x00000080, 0x00000080 } },
558 { 7, AR5K_RF_BUFFER,
559 { 0x000000d9, 0x000000d9, 0x000000d9 } },
560 { 7, AR5K_RF_BUFFER,
561 { 0x00000060, 0x00000060, 0x00000060 } },
562 { 7, AR5K_RF_BUFFER,
563 { 0x000000f0, 0x000000f0, 0x000000f0 } },
564 { 7, AR5K_RF_BUFFER,
565 { 0x000000a2, 0x000000a2, 0x000000a2 } },
566 { 7, AR5K_RF_BUFFER,
567 { 0x00000052, 0x00000052, 0x00000052 } },
568 { 7, AR5K_RF_BUFFER,
569 { 0x000000d4, 0x000000d4, 0x000000d4 } },
570 { 7, AR5K_RF_BUFFER,
571 { 0x000014cc, 0x000014cc, 0x000014cc } },
572 { 7, AR5K_RF_BUFFER,
573 { 0x0000048c, 0x0000048c, 0x0000048c } },
574 { 7, AR5K_RF_BUFFER_CONTROL_1,
575 { 0x00000003, 0x00000003, 0x00000003 } },
576 };
577
578 /* RF5413/5414 mode-specific init registers */
579 static const struct ath5k_ini_rf rfregs_5413[] = {
580 { 1, 0x98d4,
581 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
582 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
583 { 2, 0x98d0,
584 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
585 { 3, 0x98dc,
586 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
587 { 6, 0x989c,
588 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
589 { 6, 0x989c,
590 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
591 { 6, 0x989c,
592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
593 { 6, 0x989c,
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595 { 6, 0x989c,
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597 { 6, 0x989c,
598 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
599 { 6, 0x989c,
600 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
601 { 6, 0x989c,
602 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
603 { 6, 0x989c,
604 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
605 { 6, 0x989c,
606 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
607 { 6, 0x989c,
608 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
609 { 6, 0x989c,
610 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
611 { 6, 0x989c,
612 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
613 { 6, 0x989c,
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615 { 6, 0x989c,
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617 { 6, 0x989c,
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619 { 6, 0x989c,
620 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
621 { 6, 0x989c,
622 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
623 { 6, 0x989c,
624 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
625 { 6, 0x989c,
626 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
627 { 6, 0x989c,
628 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
629 { 6, 0x989c,
630 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
631 { 6, 0x989c,
632 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
633 { 6, 0x989c,
634 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
635 { 6, 0x989c,
636 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
637 { 6, 0x989c,
638 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
639 { 6, 0x989c,
640 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
641 { 6, 0x989c,
642 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
643 { 6, 0x989c,
644 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
645 { 6, 0x989c,
646 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
647 { 6, 0x989c,
648 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
649 { 6, 0x989c,
650 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
651 { 6, 0x989c,
652 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
653 { 6, 0x989c,
654 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
655 { 6, 0x989c,
656 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
657 { 6, 0x989c,
658 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
659 { 6, 0x98c8,
660 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
661 { 7, 0x989c,
662 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
663 { 7, 0x989c,
664 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
665 { 7, 0x98cc,
666 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
667 };
668
669 /* RF2413/2414 mode-specific init registers */
670 static const struct ath5k_ini_rf rfregs_2413[] = {
671 { 1, AR5K_RF_BUFFER_CONTROL_4,
672 { 0x00000020, 0x00000020, 0x00000020 } },
673 { 2, AR5K_RF_BUFFER_CONTROL_3,
674 { 0x02001408, 0x02001408, 0x02001408 } },
675 { 3, AR5K_RF_BUFFER_CONTROL_6,
676 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
677 { 6, AR5K_RF_BUFFER,
678 { 0xf0000000, 0xf0000000, 0xf0000000 } },
679 { 6, AR5K_RF_BUFFER,
680 { 0x00000000, 0x00000000, 0x00000000 } },
681 { 6, AR5K_RF_BUFFER,
682 { 0x03000000, 0x03000000, 0x03000000 } },
683 { 6, AR5K_RF_BUFFER,
684 { 0x00000000, 0x00000000, 0x00000000 } },
685 { 6, AR5K_RF_BUFFER,
686 { 0x00000000, 0x00000000, 0x00000000 } },
687 { 6, AR5K_RF_BUFFER,
688 { 0x00000000, 0x00000000, 0x00000000 } },
689 { 6, AR5K_RF_BUFFER,
690 { 0x00000000, 0x00000000, 0x00000000 } },
691 { 6, AR5K_RF_BUFFER,
692 { 0x00000000, 0x00000000, 0x00000000 } },
693 { 6, AR5K_RF_BUFFER,
694 { 0x40400000, 0x40400000, 0x40400000 } },
695 { 6, AR5K_RF_BUFFER,
696 { 0x65050000, 0x65050000, 0x65050000 } },
697 { 6, AR5K_RF_BUFFER,
698 { 0x00000000, 0x00000000, 0x00000000 } },
699 { 6, AR5K_RF_BUFFER,
700 { 0x00000000, 0x00000000, 0x00000000 } },
701 { 6, AR5K_RF_BUFFER,
702 { 0x00420000, 0x00420000, 0x00420000 } },
703 { 6, AR5K_RF_BUFFER,
704 { 0x00b50000, 0x00b50000, 0x00b50000 } },
705 { 6, AR5K_RF_BUFFER,
706 { 0x00030000, 0x00030000, 0x00030000 } },
707 { 6, AR5K_RF_BUFFER,
708 { 0x00f70000, 0x00f70000, 0x00f70000 } },
709 { 6, AR5K_RF_BUFFER,
710 { 0x009d0000, 0x009d0000, 0x009d0000 } },
711 { 6, AR5K_RF_BUFFER,
712 { 0x00220000, 0x00220000, 0x00220000 } },
713 { 6, AR5K_RF_BUFFER,
714 { 0x04220000, 0x04220000, 0x04220000 } },
715 { 6, AR5K_RF_BUFFER,
716 { 0x00230018, 0x00230018, 0x00230018 } },
717 { 6, AR5K_RF_BUFFER,
718 { 0x00280050, 0x00280050, 0x00280050 } },
719 { 6, AR5K_RF_BUFFER,
720 { 0x005000c3, 0x005000c3, 0x005000c3 } },
721 { 6, AR5K_RF_BUFFER,
722 { 0x0004007f, 0x0004007f, 0x0004007f } },
723 { 6, AR5K_RF_BUFFER,
724 { 0x00000458, 0x00000458, 0x00000458 } },
725 { 6, AR5K_RF_BUFFER,
726 { 0x00000000, 0x00000000, 0x00000000 } },
727 { 6, AR5K_RF_BUFFER,
728 { 0x0000c000, 0x0000c000, 0x0000c000 } },
729 { 6, AR5K_RF_BUFFER_CONTROL_5,
730 { 0x00400230, 0x00400230, 0x00400230 } },
731 { 7, AR5K_RF_BUFFER,
732 { 0x00006400, 0x00006400, 0x00006400 } },
733 { 7, AR5K_RF_BUFFER,
734 { 0x00000800, 0x00000800, 0x00000800 } },
735 { 7, AR5K_RF_BUFFER_CONTROL_2,
736 { 0x0000000e, 0x0000000e, 0x0000000e } },
737 };
738
739 /* Initial RF Gain settings for RF5112 */
740 static const struct ath5k_ini_rfgain rfgain_5112[] = {
741 /* 5Ghz 2Ghz */
742 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
743 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
744 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
745 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
746 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
747 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
748 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
749 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
750 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
751 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
752 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
753 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
754 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
755 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
756 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
757 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
758 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
759 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
760 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
761 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
762 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
763 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
764 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
765 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
766 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
767 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
768 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
769 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
770 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
771 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
772 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
773 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
774 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
775 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
776 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
777 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
778 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
779 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
780 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
781 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
782 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
783 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
784 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
785 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
786 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
787 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
788 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
789 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
790 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
791 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
792 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
793 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
794 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
795 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
796 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
797 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
798 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
799 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
800 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
801 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
802 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
803 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
804 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
805 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
806 };
807
808 /* Initial RF Gain settings for RF5413 */
809 static const struct ath5k_ini_rfgain rfgain_5413[] = {
810 /* 5Ghz 2Ghz */
811 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
812 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
813 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
814 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
815 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
816 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
817 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
818 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
819 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
820 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
821 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
822 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
823 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
824 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
825 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
826 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
827 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
828 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
829 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
830 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
831 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
832 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
833 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
834 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
835 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
836 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
837 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
838 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
839 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
840 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
841 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
842 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
843 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
844 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
845 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
846 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
847 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
848 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
849 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
850 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
851 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
852 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
853 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
854 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
855 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
856 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
857 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
858 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
859 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
860 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
861 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
862 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
863 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
864 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
865 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
866 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
867 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
868 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
869 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
870 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
871 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
872 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
873 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
874 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
875 };
876
877 /* Initial RF Gain settings for RF2413 */
878 static const struct ath5k_ini_rfgain rfgain_2413[] = {
879 { AR5K_RF_GAIN(0), { 0x00000000 } },
880 { AR5K_RF_GAIN(1), { 0x00000040 } },
881 { AR5K_RF_GAIN(2), { 0x00000080 } },
882 { AR5K_RF_GAIN(3), { 0x00000181 } },
883 { AR5K_RF_GAIN(4), { 0x000001c1 } },
884 { AR5K_RF_GAIN(5), { 0x00000001 } },
885 { AR5K_RF_GAIN(6), { 0x00000041 } },
886 { AR5K_RF_GAIN(7), { 0x00000081 } },
887 { AR5K_RF_GAIN(8), { 0x00000168 } },
888 { AR5K_RF_GAIN(9), { 0x000001a8 } },
889 { AR5K_RF_GAIN(10), { 0x000001e8 } },
890 { AR5K_RF_GAIN(11), { 0x00000028 } },
891 { AR5K_RF_GAIN(12), { 0x00000068 } },
892 { AR5K_RF_GAIN(13), { 0x00000189 } },
893 { AR5K_RF_GAIN(14), { 0x000001c9 } },
894 { AR5K_RF_GAIN(15), { 0x00000009 } },
895 { AR5K_RF_GAIN(16), { 0x00000049 } },
896 { AR5K_RF_GAIN(17), { 0x00000089 } },
897 { AR5K_RF_GAIN(18), { 0x00000190 } },
898 { AR5K_RF_GAIN(19), { 0x000001d0 } },
899 { AR5K_RF_GAIN(20), { 0x00000010 } },
900 { AR5K_RF_GAIN(21), { 0x00000050 } },
901 { AR5K_RF_GAIN(22), { 0x00000090 } },
902 { AR5K_RF_GAIN(23), { 0x00000191 } },
903 { AR5K_RF_GAIN(24), { 0x000001d1 } },
904 { AR5K_RF_GAIN(25), { 0x00000011 } },
905 { AR5K_RF_GAIN(26), { 0x00000051 } },
906 { AR5K_RF_GAIN(27), { 0x00000091 } },
907 { AR5K_RF_GAIN(28), { 0x00000178 } },
908 { AR5K_RF_GAIN(29), { 0x000001b8 } },
909 { AR5K_RF_GAIN(30), { 0x000001f8 } },
910 { AR5K_RF_GAIN(31), { 0x00000038 } },
911 { AR5K_RF_GAIN(32), { 0x00000078 } },
912 { AR5K_RF_GAIN(33), { 0x00000199 } },
913 { AR5K_RF_GAIN(34), { 0x000001d9 } },
914 { AR5K_RF_GAIN(35), { 0x00000019 } },
915 { AR5K_RF_GAIN(36), { 0x00000059 } },
916 { AR5K_RF_GAIN(37), { 0x00000099 } },
917 { AR5K_RF_GAIN(38), { 0x000000d9 } },
918 { AR5K_RF_GAIN(39), { 0x000000f9 } },
919 { AR5K_RF_GAIN(40), { 0x000000f9 } },
920 { AR5K_RF_GAIN(41), { 0x000000f9 } },
921 { AR5K_RF_GAIN(42), { 0x000000f9 } },
922 { AR5K_RF_GAIN(43), { 0x000000f9 } },
923 { AR5K_RF_GAIN(44), { 0x000000f9 } },
924 { AR5K_RF_GAIN(45), { 0x000000f9 } },
925 { AR5K_RF_GAIN(46), { 0x000000f9 } },
926 { AR5K_RF_GAIN(47), { 0x000000f9 } },
927 { AR5K_RF_GAIN(48), { 0x000000f9 } },
928 { AR5K_RF_GAIN(49), { 0x000000f9 } },
929 { AR5K_RF_GAIN(50), { 0x000000f9 } },
930 { AR5K_RF_GAIN(51), { 0x000000f9 } },
931 { AR5K_RF_GAIN(52), { 0x000000f9 } },
932 { AR5K_RF_GAIN(53), { 0x000000f9 } },
933 { AR5K_RF_GAIN(54), { 0x000000f9 } },
934 { AR5K_RF_GAIN(55), { 0x000000f9 } },
935 { AR5K_RF_GAIN(56), { 0x000000f9 } },
936 { AR5K_RF_GAIN(57), { 0x000000f9 } },
937 { AR5K_RF_GAIN(58), { 0x000000f9 } },
938 { AR5K_RF_GAIN(59), { 0x000000f9 } },
939 { AR5K_RF_GAIN(60), { 0x000000f9 } },
940 { AR5K_RF_GAIN(61), { 0x000000f9 } },
941 { AR5K_RF_GAIN(62), { 0x000000f9 } },
942 { AR5K_RF_GAIN(63), { 0x000000f9 } },
943 };
944
945 static const struct ath5k_gain_opt rfgain_opt_5112 = {
946 1,
947 8,
948 {
949 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
950 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
951 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
952 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
953 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
954 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
955 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
956 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
957 }
958 };
959
960 /*
961 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
962 */
963 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
964 u32 first, u32 col, bool set)
965 {
966 u32 mask, entry, last, data, shift, position;
967 s32 left;
968 int i;
969
970 data = 0;
971
972 if (rf == NULL)
973 /* should not happen */
974 return 0;
975
976 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
977 ATH5K_PRINTF("invalid values at offset %u\n", offset);
978 return 0;
979 }
980
981 entry = ((first - 1) / 8) + offset;
982 position = (first - 1) % 8;
983
984 if (set == true)
985 data = ath5k_hw_bitswap(reg, bits);
986
987 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
988 last = (position + left > 8) ? 8 : position + left;
989 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
990
991 if (set == true) {
992 rf[entry] &= ~mask;
993 rf[entry] |= ((data << position) << (col * 8)) & mask;
994 data >>= (8 - position);
995 } else {
996 data = (((rf[entry] & mask) >> (col * 8)) >> position)
997 << shift;
998 shift += last - position;
999 }
1000
1001 left -= 8 - position;
1002 }
1003
1004 data = set == true ? 1 : ath5k_hw_bitswap(data, bits);
1005
1006 return data;
1007 }
1008
1009 static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1010 {
1011 u32 mix, step;
1012 u32 *rf;
1013
1014 if (ah->ah_rf_banks == NULL)
1015 return 0;
1016
1017 rf = ah->ah_rf_banks;
1018 ah->ah_gain.g_f_corr = 0;
1019
1020 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1021 return 0;
1022
1023 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1024 mix = ah->ah_gain.g_step->gos_param[0];
1025
1026 switch (mix) {
1027 case 3:
1028 ah->ah_gain.g_f_corr = step * 2;
1029 break;
1030 case 2:
1031 ah->ah_gain.g_f_corr = (step - 5) * 2;
1032 break;
1033 case 1:
1034 ah->ah_gain.g_f_corr = step;
1035 break;
1036 default:
1037 ah->ah_gain.g_f_corr = 0;
1038 break;
1039 }
1040
1041 return ah->ah_gain.g_f_corr;
1042 }
1043
1044 static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1045 {
1046 u32 step, mix, level[4];
1047 u32 *rf;
1048
1049 if (ah->ah_rf_banks == NULL)
1050 return false;
1051
1052 rf = ah->ah_rf_banks;
1053
1054 if (ah->ah_radio == AR5K_RF5111) {
1055 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1056 false);
1057 level[0] = 0;
1058 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1059 level[2] = (step != 0x3f) ? 0x40 : level[0];
1060 level[3] = level[2] + 0x32;
1061
1062 ah->ah_gain.g_high = level[3] -
1063 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1064 ah->ah_gain.g_low = level[0] +
1065 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1066 } else {
1067 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1068 false);
1069 level[0] = level[2] = 0;
1070
1071 if (mix == 1) {
1072 level[1] = level[3] = 83;
1073 } else {
1074 level[1] = level[3] = 107;
1075 ah->ah_gain.g_high = 55;
1076 }
1077 }
1078
1079 return (ah->ah_gain.g_current >= level[0] &&
1080 ah->ah_gain.g_current <= level[1]) ||
1081 (ah->ah_gain.g_current >= level[2] &&
1082 ah->ah_gain.g_current <= level[3]);
1083 }
1084
1085 static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1086 {
1087 const struct ath5k_gain_opt *go;
1088 int ret = 0;
1089
1090 switch (ah->ah_radio) {
1091 case AR5K_RF5111:
1092 go = &rfgain_opt_5111;
1093 break;
1094 case AR5K_RF5112:
1095 case AR5K_RF5413: /* ??? */
1096 go = &rfgain_opt_5112;
1097 break;
1098 default:
1099 return 0;
1100 }
1101
1102 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1103
1104 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1105 if (ah->ah_gain.g_step_idx == 0)
1106 return -1;
1107 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1108 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
1109 ah->ah_gain.g_step_idx > 0;
1110 ah->ah_gain.g_step =
1111 &go->go_step[ah->ah_gain.g_step_idx])
1112 ah->ah_gain.g_target -= 2 *
1113 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1114 ah->ah_gain.g_step->gos_gain);
1115
1116 ret = 1;
1117 goto done;
1118 }
1119
1120 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1121 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1122 return -2;
1123 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1124 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1125 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1126 ah->ah_gain.g_step =
1127 &go->go_step[ah->ah_gain.g_step_idx])
1128 ah->ah_gain.g_target -= 2 *
1129 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1130 ah->ah_gain.g_step->gos_gain);
1131
1132 ret = 2;
1133 goto done;
1134 }
1135
1136 done:
1137 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1138 "ret %d, gain step %u, current gain %u, target gain %u\n",
1139 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1140 ah->ah_gain.g_target);
1141
1142 return ret;
1143 }
1144
1145 /*
1146 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1147 */
1148 static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1149 struct ieee80211_channel *channel, unsigned int mode)
1150 {
1151 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1152 u32 *rf;
1153 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1154 unsigned int i;
1155 int obdb = -1, bank = -1;
1156 u32 ee_mode;
1157
1158 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1159
1160 rf = ah->ah_rf_banks;
1161
1162 /* Copy values to modify them */
1163 for (i = 0; i < rf_size; i++) {
1164 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1165 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1166 return -EINVAL;
1167 }
1168
1169 if (bank != rfregs_5111[i].rf_bank) {
1170 bank = rfregs_5111[i].rf_bank;
1171 ah->ah_offset[bank] = i;
1172 }
1173
1174 rf[i] = rfregs_5111[i].rf_value[mode];
1175 }
1176
1177 /* Modify bank 0 */
1178 if (channel->hw_value & CHANNEL_2GHZ) {
1179 if (channel->hw_value & CHANNEL_CCK)
1180 ee_mode = AR5K_EEPROM_MODE_11B;
1181 else
1182 ee_mode = AR5K_EEPROM_MODE_11G;
1183 obdb = 0;
1184
1185 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1186 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1187 return -EINVAL;
1188
1189 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1190 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1191 return -EINVAL;
1192
1193 obdb = 1;
1194 /* Modify bank 6 */
1195 } else {
1196 /* For 11a, Turbo and XR */
1197 ee_mode = AR5K_EEPROM_MODE_11A;
1198 obdb = channel->center_freq >= 5725 ? 3 :
1199 (channel->center_freq >= 5500 ? 2 :
1200 (channel->center_freq >= 5260 ? 1 :
1201 (channel->center_freq > 4000 ? 0 : -1)));
1202
1203 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1204 ee->ee_pwd_84, 1, 51, 3, true))
1205 return -EINVAL;
1206
1207 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1208 ee->ee_pwd_90, 1, 45, 3, true))
1209 return -EINVAL;
1210 }
1211
1212 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1213 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1214 return -EINVAL;
1215
1216 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1217 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1218 return -EINVAL;
1219
1220 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1221 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1222 return -EINVAL;
1223
1224 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1225 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1226 return -EINVAL;
1227
1228 /* Modify bank 7 */
1229 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1230 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1231 return -EINVAL;
1232
1233 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1234 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1235 return -EINVAL;
1236
1237 /* Write RF values */
1238 for (i = 0; i < rf_size; i++) {
1239 AR5K_REG_WAIT(i);
1240 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1241 }
1242
1243 return 0;
1244 }
1245
1246 /*
1247 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1248 */
1249 static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1250 struct ieee80211_channel *channel, unsigned int mode)
1251 {
1252 const struct ath5k_ini_rf *rf_ini;
1253 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1254 u32 *rf;
1255 unsigned int rf_size, i;
1256 int obdb = -1, bank = -1;
1257 u32 ee_mode;
1258
1259 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1260
1261 rf = ah->ah_rf_banks;
1262
1263 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
1264 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
1265 rf_ini = rfregs_2112a;
1266 rf_size = ARRAY_SIZE(rfregs_5112a);
1267 if (mode < 2) {
1268 ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1269 return -EINVAL;
1270 }
1271 mode = mode - 2; /*no a/turboa modes for 2112*/
1272 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1273 rf_ini = rfregs_5112a;
1274 rf_size = ARRAY_SIZE(rfregs_5112a);
1275 } else {
1276 rf_ini = rfregs_5112;
1277 rf_size = ARRAY_SIZE(rfregs_5112);
1278 }
1279
1280 /* Copy values to modify them */
1281 for (i = 0; i < rf_size; i++) {
1282 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1283 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1284 return -EINVAL;
1285 }
1286
1287 if (bank != rf_ini[i].rf_bank) {
1288 bank = rf_ini[i].rf_bank;
1289 ah->ah_offset[bank] = i;
1290 }
1291
1292 rf[i] = rf_ini[i].rf_value[mode];
1293 }
1294
1295 /* Modify bank 6 */
1296 if (channel->hw_value & CHANNEL_2GHZ) {
1297 if (channel->hw_value & CHANNEL_OFDM)
1298 ee_mode = AR5K_EEPROM_MODE_11G;
1299 else
1300 ee_mode = AR5K_EEPROM_MODE_11B;
1301 obdb = 0;
1302
1303 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1304 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1305 return -EINVAL;
1306
1307 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1308 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1309 return -EINVAL;
1310 } else {
1311 /* For 11a, Turbo and XR */
1312 ee_mode = AR5K_EEPROM_MODE_11A;
1313 obdb = channel->center_freq >= 5725 ? 3 :
1314 (channel->center_freq >= 5500 ? 2 :
1315 (channel->center_freq >= 5260 ? 1 :
1316 (channel->center_freq > 4000 ? 0 : -1)));
1317
1318 if (obdb == -1)
1319 return -EINVAL;
1320
1321 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1322 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1323 return -EINVAL;
1324
1325 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1326 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1327 return -EINVAL;
1328 }
1329
1330 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1331 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1332 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1333 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1334
1335 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1336 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1337 return -EINVAL;
1338
1339 /* Modify bank 7 */
1340 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1341 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1342 return -EINVAL;
1343
1344 /* Write RF values */
1345 for (i = 0; i < rf_size; i++)
1346 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1347
1348 return 0;
1349 }
1350
1351 /*
1352 * Initialize RF5413/5414
1353 */
1354 static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1355 struct ieee80211_channel *channel, unsigned int mode)
1356 {
1357 const struct ath5k_ini_rf *rf_ini;
1358 u32 *rf;
1359 unsigned int rf_size, i;
1360 int bank = -1;
1361
1362 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1363
1364 rf = ah->ah_rf_banks;
1365
1366 if (ah->ah_radio == AR5K_RF5413) {
1367 rf_ini = rfregs_5413;
1368 rf_size = ARRAY_SIZE(rfregs_5413);
1369 } else if (ah->ah_radio == AR5K_RF2413) {
1370 rf_ini = rfregs_2413;
1371 rf_size = ARRAY_SIZE(rfregs_2413);
1372 if (mode < 2) {
1373 ATH5K_ERR(ah->ah_sc,
1374 "invalid channel mode: %i\n", mode);
1375 return -EINVAL;
1376 }
1377 mode = mode - 2;
1378 } else {
1379 return -EINVAL;
1380 }
1381
1382 /* Copy values to modify them */
1383 for (i = 0; i < rf_size; i++) {
1384 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1385 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1386 return -EINVAL;
1387 }
1388
1389 if (bank != rf_ini[i].rf_bank) {
1390 bank = rf_ini[i].rf_bank;
1391 ah->ah_offset[bank] = i;
1392 }
1393
1394 rf[i] = rf_ini[i].rf_value[mode];
1395 }
1396
1397 /*
1398 * After compairing dumps from different cards
1399 * we get the same RF_BUFFER settings (diff returns
1400 * 0 lines). It seems that RF_BUFFER settings are static
1401 * and are written unmodified (no EEPROM stuff
1402 * is used because calibration data would be
1403 * different between different cards and would result
1404 * different RF_BUFFER settings)
1405 */
1406
1407 /* Write RF values */
1408 for (i = 0; i < rf_size; i++)
1409 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1410
1411 return 0;
1412 }
1413
1414 /*
1415 * Initialize RF
1416 */
1417 int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1418 unsigned int mode)
1419 {
1420 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1421 int ret;
1422
1423 switch (ah->ah_radio) {
1424 case AR5K_RF5111:
1425 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1426 func = ath5k_hw_rf5111_rfregs;
1427 break;
1428 case AR5K_RF5112:
1429 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1430 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1431 else
1432 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1433 func = ath5k_hw_rf5112_rfregs;
1434 break;
1435 case AR5K_RF5413:
1436 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1437 func = ath5k_hw_rf5413_rfregs;
1438 break;
1439 case AR5K_RF2413:
1440 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1441 func = ath5k_hw_rf5413_rfregs;
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446
1447 if (ah->ah_rf_banks == NULL) {
1448 /* XXX do extra checks? */
1449 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1450 if (ah->ah_rf_banks == NULL) {
1451 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1452 return -ENOMEM;
1453 }
1454 }
1455
1456 ret = func(ah, channel, mode);
1457 if (!ret)
1458 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1459
1460 return ret;
1461 }
1462
1463 int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1464 {
1465 const struct ath5k_ini_rfgain *ath5k_rfg;
1466 unsigned int i, size;
1467
1468 switch (ah->ah_radio) {
1469 case AR5K_RF5111:
1470 ath5k_rfg = rfgain_5111;
1471 size = ARRAY_SIZE(rfgain_5111);
1472 break;
1473 case AR5K_RF5112:
1474 ath5k_rfg = rfgain_5112;
1475 size = ARRAY_SIZE(rfgain_5112);
1476 break;
1477 case AR5K_RF5413:
1478 ath5k_rfg = rfgain_5413;
1479 size = ARRAY_SIZE(rfgain_5413);
1480 break;
1481 case AR5K_RF2413:
1482 ath5k_rfg = rfgain_2413;
1483 size = ARRAY_SIZE(rfgain_2413);
1484 freq = 0; /* only 2Ghz */
1485 break;
1486 default:
1487 return -EINVAL;
1488 }
1489
1490 switch (freq) {
1491 case AR5K_INI_RFGAIN_2GHZ:
1492 case AR5K_INI_RFGAIN_5GHZ:
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497
1498 for (i = 0; i < size; i++) {
1499 AR5K_REG_WAIT(i);
1500 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1501 (u32)ath5k_rfg[i].rfg_register);
1502 }
1503
1504 return 0;
1505 }
1506
1507 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1508 {
1509 u32 data, type;
1510
1511 ATH5K_TRACE(ah->ah_sc);
1512
1513 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1514 ah->ah_version <= AR5K_AR5211)
1515 return AR5K_RFGAIN_INACTIVE;
1516
1517 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1518 goto done;
1519
1520 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1521
1522 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1523 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1524 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1525
1526 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1527 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1528
1529 if (ah->ah_radio >= AR5K_RF5112) {
1530 ath5k_hw_rfregs_gainf_corr(ah);
1531 ah->ah_gain.g_current =
1532 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1533 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1534 0;
1535 }
1536
1537 if (ath5k_hw_rfregs_gain_readback(ah) &&
1538 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1539 ath5k_hw_rfregs_gain_adjust(ah))
1540 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1541 }
1542
1543 done:
1544 return ah->ah_rf_gain;
1545 }
1546
1547 int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1548 {
1549 /* Initialize the gain optimization values */
1550 switch (ah->ah_radio) {
1551 case AR5K_RF5111:
1552 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1553 ah->ah_gain.g_step =
1554 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1555 ah->ah_gain.g_low = 20;
1556 ah->ah_gain.g_high = 35;
1557 ah->ah_gain.g_active = 1;
1558 break;
1559 case AR5K_RF5112:
1560 case AR5K_RF5413: /* ??? */
1561 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1562 ah->ah_gain.g_step =
1563 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1564 ah->ah_gain.g_low = 20;
1565 ah->ah_gain.g_high = 85;
1566 ah->ah_gain.g_active = 1;
1567 break;
1568 default:
1569 return -EINVAL;
1570 }
1571
1572 return 0;
1573 }
1574
1575 /**************************\
1576 PHY/RF channel functions
1577 \**************************/
1578
1579 /*
1580 * Check if a channel is supported
1581 */
1582 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1583 {
1584 /* Check if the channel is in our supported range */
1585 if (flags & CHANNEL_2GHZ) {
1586 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1587 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1588 return true;
1589 } else if (flags & CHANNEL_5GHZ)
1590 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1591 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1592 return true;
1593
1594 return false;
1595 }
1596
1597 /*
1598 * Convertion needed for RF5110
1599 */
1600 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1601 {
1602 u32 athchan;
1603
1604 /*
1605 * Convert IEEE channel/MHz to an internal channel value used
1606 * by the AR5210 chipset. This has not been verified with
1607 * newer chipsets like the AR5212A who have a completely
1608 * different RF/PHY part.
1609 */
1610 athchan = (ath5k_hw_bitswap(
1611 (ieee80211_frequency_to_channel(
1612 channel->center_freq) - 24) / 2, 5)
1613 << 1) | (1 << 6) | 0x1;
1614 return athchan;
1615 }
1616
1617 /*
1618 * Set channel on RF5110
1619 */
1620 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1621 struct ieee80211_channel *channel)
1622 {
1623 u32 data;
1624
1625 /*
1626 * Set the channel and wait
1627 */
1628 data = ath5k_hw_rf5110_chan2athchan(channel);
1629 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1630 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1631 mdelay(1);
1632
1633 return 0;
1634 }
1635
1636 /*
1637 * Convertion needed for 5111
1638 */
1639 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1640 struct ath5k_athchan_2ghz *athchan)
1641 {
1642 int channel;
1643
1644 /* Cast this value to catch negative channel numbers (>= -19) */
1645 channel = (int)ieee;
1646
1647 /*
1648 * Map 2GHz IEEE channel to 5GHz Atheros channel
1649 */
1650 if (channel <= 13) {
1651 athchan->a2_athchan = 115 + channel;
1652 athchan->a2_flags = 0x46;
1653 } else if (channel == 14) {
1654 athchan->a2_athchan = 124;
1655 athchan->a2_flags = 0x44;
1656 } else if (channel >= 15 && channel <= 26) {
1657 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1658 athchan->a2_flags = 0x46;
1659 } else
1660 return -EINVAL;
1661
1662 return 0;
1663 }
1664
1665 /*
1666 * Set channel on 5111
1667 */
1668 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1669 struct ieee80211_channel *channel)
1670 {
1671 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1672 unsigned int ath5k_channel =
1673 ieee80211_frequency_to_channel(channel->center_freq);
1674 u32 data0, data1, clock;
1675 int ret;
1676
1677 /*
1678 * Set the channel on the RF5111 radio
1679 */
1680 data0 = data1 = 0;
1681
1682 if (channel->hw_value & CHANNEL_2GHZ) {
1683 /* Map 2GHz channel to 5GHz Atheros channel ID */
1684 ret = ath5k_hw_rf5111_chan2athchan(
1685 ieee80211_frequency_to_channel(channel->center_freq),
1686 &ath5k_channel_2ghz);
1687 if (ret)
1688 return ret;
1689
1690 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1691 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1692 << 5) | (1 << 4);
1693 }
1694
1695 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1696 clock = 1;
1697 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1698 (clock << 1) | (1 << 10) | 1;
1699 } else {
1700 clock = 0;
1701 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1702 << 2) | (clock << 1) | (1 << 10) | 1;
1703 }
1704
1705 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1706 AR5K_RF_BUFFER);
1707 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1708 AR5K_RF_BUFFER_CONTROL_3);
1709
1710 return 0;
1711 }
1712
1713 /*
1714 * Set channel on 5112 and newer
1715 */
1716 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1717 struct ieee80211_channel *channel)
1718 {
1719 u32 data, data0, data1, data2;
1720 u16 c;
1721
1722 data = data0 = data1 = data2 = 0;
1723 c = channel->center_freq;
1724
1725 /*
1726 * Set the channel on the RF5112 or newer
1727 */
1728 if (c < 4800) {
1729 if (!((c - 2224) % 5)) {
1730 data0 = ((2 * (c - 704)) - 3040) / 10;
1731 data1 = 1;
1732 } else if (!((c - 2192) % 5)) {
1733 data0 = ((2 * (c - 672)) - 3040) / 10;
1734 data1 = 0;
1735 } else
1736 return -EINVAL;
1737
1738 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1739 } else {
1740 if (!(c % 20) && c >= 5120) {
1741 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1742 data2 = ath5k_hw_bitswap(3, 2);
1743 } else if (!(c % 10)) {
1744 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1745 data2 = ath5k_hw_bitswap(2, 2);
1746 } else if (!(c % 5)) {
1747 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1748 data2 = ath5k_hw_bitswap(1, 2);
1749 } else
1750 return -EINVAL;
1751 }
1752
1753 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1754
1755 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1756 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1757
1758 return 0;
1759 }
1760
1761 /*
1762 * Set a channel on the radio chip
1763 */
1764 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1765 {
1766 int ret;
1767 /*
1768 * Check bounds supported by the PHY (we don't care about regultory
1769 * restrictions at this point). Note: hw_value already has the band
1770 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1771 * of the band by that */
1772 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1773 ATH5K_ERR(ah->ah_sc,
1774 "channel frequency (%u MHz) out of supported "
1775 "band range\n",
1776 channel->center_freq);
1777 return -EINVAL;
1778 }
1779
1780 /*
1781 * Set the channel and wait
1782 */
1783 switch (ah->ah_radio) {
1784 case AR5K_RF5110:
1785 ret = ath5k_hw_rf5110_channel(ah, channel);
1786 break;
1787 case AR5K_RF5111:
1788 ret = ath5k_hw_rf5111_channel(ah, channel);
1789 break;
1790 default:
1791 ret = ath5k_hw_rf5112_channel(ah, channel);
1792 break;
1793 }
1794
1795 if (ret)
1796 return ret;
1797
1798 ah->ah_current_channel.center_freq = channel->center_freq;
1799 ah->ah_current_channel.hw_value = channel->hw_value;
1800 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
1801
1802 return 0;
1803 }
1804
1805 /*****************\
1806 PHY calibration
1807 \*****************/
1808
1809 /**
1810 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1811 *
1812 * @ah: struct ath5k_hw pointer we are operating on
1813 * @freq: the channel frequency, just used for error logging
1814 *
1815 * This function performs a noise floor calibration of the PHY and waits for
1816 * it to complete. Then the noise floor value is compared to some maximum
1817 * noise floor we consider valid.
1818 *
1819 * Note that this is different from what the madwifi HAL does: it reads the
1820 * noise floor and afterwards initiates the calibration. Since the noise floor
1821 * calibration can take some time to finish, depending on the current channel
1822 * use, that avoids the occasional timeout warnings we are seeing now.
1823 *
1824 * See the following link for an Atheros patent on noise floor calibration:
1825 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1826 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1827 *
1828 */
1829 int
1830 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1831 {
1832 int ret;
1833 unsigned int i;
1834 s32 noise_floor;
1835
1836 /*
1837 * Enable noise floor calibration and wait until completion
1838 */
1839 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1840 AR5K_PHY_AGCCTL_NF);
1841
1842 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1843 AR5K_PHY_AGCCTL_NF, 0, false);
1844 if (ret) {
1845 ATH5K_ERR(ah->ah_sc,
1846 "noise floor calibration timeout (%uMHz)\n", freq);
1847 return ret;
1848 }
1849
1850 /* Wait until the noise floor is calibrated and read the value */
1851 for (i = 20; i > 0; i--) {
1852 mdelay(1);
1853 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1854 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1855 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1856 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1857
1858 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1859 break;
1860 }
1861 }
1862
1863 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1864 "noise floor %d\n", noise_floor);
1865
1866 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1867 ATH5K_ERR(ah->ah_sc,
1868 "noise floor calibration failed (%uMHz)\n", freq);
1869 return -EIO;
1870 }
1871
1872 ah->ah_noise_floor = noise_floor;
1873
1874 return 0;
1875 }
1876
1877 /*
1878 * Perform a PHY calibration on RF5110
1879 * -Fix BPSK/QAM Constellation (I/Q correction)
1880 * -Calculate Noise Floor
1881 */
1882 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1883 struct ieee80211_channel *channel)
1884 {
1885 u32 phy_sig, phy_agc, phy_sat, beacon;
1886 int ret;
1887
1888 /*
1889 * Disable beacons and RX/TX queues, wait
1890 */
1891 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1892 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1893 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1894 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1895
1896 udelay(2300);
1897
1898 /*
1899 * Set the channel (with AGC turned off)
1900 */
1901 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1902 udelay(10);
1903 ret = ath5k_hw_channel(ah, channel);
1904
1905 /*
1906 * Activate PHY and wait
1907 */
1908 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1909 mdelay(1);
1910
1911 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1912
1913 if (ret)
1914 return ret;
1915
1916 /*
1917 * Calibrate the radio chip
1918 */
1919
1920 /* Remember normal state */
1921 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1922 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1923 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1924
1925 /* Update radio registers */
1926 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1927 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1928
1929 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1930 AR5K_PHY_AGCCOARSE_LO)) |
1931 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1932 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1933
1934 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1935 AR5K_PHY_ADCSAT_THR)) |
1936 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1937 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1938
1939 udelay(20);
1940
1941 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1942 udelay(10);
1943 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1944 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1945
1946 mdelay(1);
1947
1948 /*
1949 * Enable calibration and wait until completion
1950 */
1951 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1952
1953 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1954 AR5K_PHY_AGCCTL_CAL, 0, false);
1955
1956 /* Reset to normal state */
1957 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1958 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1959 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1960
1961 if (ret) {
1962 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1963 channel->center_freq);
1964 return ret;
1965 }
1966
1967 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1968 if (ret)
1969 return ret;
1970
1971 /*
1972 * Re-enable RX/TX and beacons
1973 */
1974 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1975 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1976 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1977
1978 return 0;
1979 }
1980
1981 /*
1982 * Perform a PHY calibration on RF5111/5112
1983 */
1984 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1985 struct ieee80211_channel *channel)
1986 {
1987 u32 i_pwr, q_pwr;
1988 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1989 ATH5K_TRACE(ah->ah_sc);
1990
1991 if (ah->ah_calibration == false ||
1992 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1993 goto done;
1994
1995 ah->ah_calibration = false;
1996
1997 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1998 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1999 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2000 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
2001 q_coffd = q_pwr >> 6;
2002
2003 if (i_coffd == 0 || q_coffd == 0)
2004 goto done;
2005
2006 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2007 q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
2008
2009 /* Commit new IQ value */
2010 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2011 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2012
2013 done:
2014 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2015
2016 /* Request RF gain */
2017 if (channel->hw_value & CHANNEL_5GHZ) {
2018 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2019 AR5K_PHY_PAPD_PROBE_TXPOWER) |
2020 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2021 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2022 }
2023
2024 return 0;
2025 }
2026
2027 /*
2028 * Perform a PHY calibration
2029 */
2030 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2031 struct ieee80211_channel *channel)
2032 {
2033 int ret;
2034
2035 if (ah->ah_radio == AR5K_RF5110)
2036 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2037 else
2038 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2039
2040 return ret;
2041 }
2042
2043 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2044 {
2045 ATH5K_TRACE(ah->ah_sc);
2046 /*Just a try M.F.*/
2047 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2048
2049 return 0;
2050 }
2051
2052 /********************\
2053 Misc PHY functions
2054 \********************/
2055
2056 /*
2057 * Get the PHY Chip revision
2058 */
2059 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2060 {
2061 unsigned int i;
2062 u32 srev;
2063 u16 ret;
2064
2065 ATH5K_TRACE(ah->ah_sc);
2066
2067 /*
2068 * Set the radio chip access register
2069 */
2070 switch (chan) {
2071 case CHANNEL_2GHZ:
2072 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2073 break;
2074 case CHANNEL_5GHZ:
2075 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2076 break;
2077 default:
2078 return 0;
2079 }
2080
2081 mdelay(2);
2082
2083 /* ...wait until PHY is ready and read the selected radio revision */
2084 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2085
2086 for (i = 0; i < 8; i++)
2087 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2088
2089 if (ah->ah_version == AR5K_AR5210) {
2090 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2091 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2092 } else {
2093 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2094 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2095 ((srev & 0x0f) << 4), 8);
2096 }
2097
2098 /* Reset to the 5GHz mode */
2099 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2100
2101 return ret;
2102 }
2103
2104 void /*TODO:Boundary check*/
2105 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2106 {
2107 ATH5K_TRACE(ah->ah_sc);
2108 /*Just a try M.F.*/
2109 if (ah->ah_version != AR5K_AR5210)
2110 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2111 }
2112
2113 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2114 {
2115 ATH5K_TRACE(ah->ah_sc);
2116 /*Just a try M.F.*/
2117 if (ah->ah_version != AR5K_AR5210)
2118 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2119
2120 return false; /*XXX: What do we return for 5210 ?*/
2121 }
2122
2123 /*
2124 * TX power setup
2125 */
2126
2127 /*
2128 * Initialize the tx power table (not fully implemented)
2129 */
2130 static void ath5k_txpower_table(struct ath5k_hw *ah,
2131 struct ieee80211_channel *channel, s16 max_power)
2132 {
2133 unsigned int i, min, max, n;
2134 u16 txpower, *rates;
2135
2136 rates = ah->ah_txpower.txp_rates;
2137
2138 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2139 if (max_power > txpower)
2140 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2141 AR5K_TUNE_MAX_TXPOWER : max_power;
2142
2143 for (i = 0; i < AR5K_MAX_RATES; i++)
2144 rates[i] = txpower;
2145
2146 /* XXX setup target powers by rate */
2147
2148 ah->ah_txpower.txp_min = rates[7];
2149 ah->ah_txpower.txp_max = rates[0];
2150 ah->ah_txpower.txp_ofdm = rates[0];
2151
2152 /* Calculate the power table */
2153 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2154 min = AR5K_EEPROM_PCDAC_START;
2155 max = AR5K_EEPROM_PCDAC_STOP;
2156 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2157 ah->ah_txpower.txp_pcdac[i] =
2158 #ifdef notyet
2159 min + ((i * (max - min)) / n);
2160 #else
2161 min;
2162 #endif
2163 }
2164
2165 /*
2166 * Set transmition power
2167 */
2168 int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2169 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2170 unsigned int txpower)
2171 {
2172 bool tpc = ah->ah_txpower.txp_tpc;
2173 unsigned int i;
2174
2175 ATH5K_TRACE(ah->ah_sc);
2176 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2177 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2178 return -EINVAL;
2179 }
2180
2181 /*
2182 * RF2413 for some reason can't
2183 * transmit anything if we call
2184 * this funtion, so we skip it
2185 * until we fix txpower.
2186 */
2187 if (ah->ah_radio == AR5K_RF2413)
2188 return 0;
2189
2190 /* Reset TX power values */
2191 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2192 ah->ah_txpower.txp_tpc = tpc;
2193
2194 /* Initialize TX power table */
2195 ath5k_txpower_table(ah, channel, txpower);
2196
2197 /*
2198 * Write TX power values
2199 */
2200 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2201 ath5k_hw_reg_write(ah,
2202 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2203 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2204 AR5K_PHY_PCDAC_TXPOWER(i));
2205 }
2206
2207 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2208 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2209 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2210
2211 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2212 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2213 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2214
2215 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2216 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2217 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2218
2219 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2220 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2221 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2222
2223 if (ah->ah_txpower.txp_tpc == true)
2224 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2225 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2226 else
2227 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2228 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2229
2230 return 0;
2231 }
2232
2233 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2234 {
2235 /*Just a try M.F.*/
2236 struct ieee80211_channel *channel = &ah->ah_current_channel;
2237
2238 ATH5K_TRACE(ah->ah_sc);
2239 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2240 "changing txpower to %d\n", power);
2241
2242 return ath5k_hw_txpower(ah, channel, power);
2243 }
kernel source for telekom puls (alcatel/mediatek)