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ath9k: Parse DTIM period from mac80211
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / init.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/slab.h>
18
19 #include "ath9k.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29 module_param_named(debug, ath9k_debug, uint, 0);
30 MODULE_PARM_DESC(debug, "Debugging mask");
31
32 int modparam_nohwcrypt;
33 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
34 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
35
36 int led_blink;
37 module_param_named(blink, led_blink, int, 0444);
38 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
39
40 static int ath9k_btcoex_enable;
41 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
42 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
43
44 /* We use the hw_value as an index into our private channel structure */
45
46 #define CHAN2G(_freq, _idx) { \
47 .center_freq = (_freq), \
48 .hw_value = (_idx), \
49 .max_power = 20, \
50 }
51
52 #define CHAN5G(_freq, _idx) { \
53 .band = IEEE80211_BAND_5GHZ, \
54 .center_freq = (_freq), \
55 .hw_value = (_idx), \
56 .max_power = 20, \
57 }
58
59 /* Some 2 GHz radios are actually tunable on 2312-2732
60 * on 5 MHz steps, we support the channels which we know
61 * we have calibration data for all cards though to make
62 * this static */
63 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
64 CHAN2G(2412, 0), /* Channel 1 */
65 CHAN2G(2417, 1), /* Channel 2 */
66 CHAN2G(2422, 2), /* Channel 3 */
67 CHAN2G(2427, 3), /* Channel 4 */
68 CHAN2G(2432, 4), /* Channel 5 */
69 CHAN2G(2437, 5), /* Channel 6 */
70 CHAN2G(2442, 6), /* Channel 7 */
71 CHAN2G(2447, 7), /* Channel 8 */
72 CHAN2G(2452, 8), /* Channel 9 */
73 CHAN2G(2457, 9), /* Channel 10 */
74 CHAN2G(2462, 10), /* Channel 11 */
75 CHAN2G(2467, 11), /* Channel 12 */
76 CHAN2G(2472, 12), /* Channel 13 */
77 CHAN2G(2484, 13), /* Channel 14 */
78 };
79
80 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
81 * on 5 MHz steps, we support the channels which we know
82 * we have calibration data for all cards though to make
83 * this static */
84 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
85 /* _We_ call this UNII 1 */
86 CHAN5G(5180, 14), /* Channel 36 */
87 CHAN5G(5200, 15), /* Channel 40 */
88 CHAN5G(5220, 16), /* Channel 44 */
89 CHAN5G(5240, 17), /* Channel 48 */
90 /* _We_ call this UNII 2 */
91 CHAN5G(5260, 18), /* Channel 52 */
92 CHAN5G(5280, 19), /* Channel 56 */
93 CHAN5G(5300, 20), /* Channel 60 */
94 CHAN5G(5320, 21), /* Channel 64 */
95 /* _We_ call this "Middle band" */
96 CHAN5G(5500, 22), /* Channel 100 */
97 CHAN5G(5520, 23), /* Channel 104 */
98 CHAN5G(5540, 24), /* Channel 108 */
99 CHAN5G(5560, 25), /* Channel 112 */
100 CHAN5G(5580, 26), /* Channel 116 */
101 CHAN5G(5600, 27), /* Channel 120 */
102 CHAN5G(5620, 28), /* Channel 124 */
103 CHAN5G(5640, 29), /* Channel 128 */
104 CHAN5G(5660, 30), /* Channel 132 */
105 CHAN5G(5680, 31), /* Channel 136 */
106 CHAN5G(5700, 32), /* Channel 140 */
107 /* _We_ call this UNII 3 */
108 CHAN5G(5745, 33), /* Channel 149 */
109 CHAN5G(5765, 34), /* Channel 153 */
110 CHAN5G(5785, 35), /* Channel 157 */
111 CHAN5G(5805, 36), /* Channel 161 */
112 CHAN5G(5825, 37), /* Channel 165 */
113 };
114
115 /* Atheros hardware rate code addition for short premble */
116 #define SHPCHECK(__hw_rate, __flags) \
117 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
118
119 #define RATE(_bitrate, _hw_rate, _flags) { \
120 .bitrate = (_bitrate), \
121 .flags = (_flags), \
122 .hw_value = (_hw_rate), \
123 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
124 }
125
126 static struct ieee80211_rate ath9k_legacy_rates[] = {
127 RATE(10, 0x1b, 0),
128 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
129 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
130 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
131 RATE(60, 0x0b, 0),
132 RATE(90, 0x0f, 0),
133 RATE(120, 0x0a, 0),
134 RATE(180, 0x0e, 0),
135 RATE(240, 0x09, 0),
136 RATE(360, 0x0d, 0),
137 RATE(480, 0x08, 0),
138 RATE(540, 0x0c, 0),
139 };
140
141 static void ath9k_deinit_softc(struct ath_softc *sc);
142
143 /*
144 * Read and write, they both share the same lock. We do this to serialize
145 * reads and writes on Atheros 802.11n PCI devices only. This is required
146 * as the FIFO on these devices can only accept sanely 2 requests.
147 */
148
149 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
150 {
151 struct ath_hw *ah = (struct ath_hw *) hw_priv;
152 struct ath_common *common = ath9k_hw_common(ah);
153 struct ath_softc *sc = (struct ath_softc *) common->priv;
154
155 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
156 unsigned long flags;
157 spin_lock_irqsave(&sc->sc_serial_rw, flags);
158 iowrite32(val, sc->mem + reg_offset);
159 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
160 } else
161 iowrite32(val, sc->mem + reg_offset);
162 }
163
164 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
165 {
166 struct ath_hw *ah = (struct ath_hw *) hw_priv;
167 struct ath_common *common = ath9k_hw_common(ah);
168 struct ath_softc *sc = (struct ath_softc *) common->priv;
169 u32 val;
170
171 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
172 unsigned long flags;
173 spin_lock_irqsave(&sc->sc_serial_rw, flags);
174 val = ioread32(sc->mem + reg_offset);
175 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
176 } else
177 val = ioread32(sc->mem + reg_offset);
178 return val;
179 }
180
181 static const struct ath_ops ath9k_common_ops = {
182 .read = ath9k_ioread32,
183 .write = ath9k_iowrite32,
184 };
185
186 /**************************/
187 /* Initialization */
188 /**************************/
189
190 static void setup_ht_cap(struct ath_softc *sc,
191 struct ieee80211_sta_ht_cap *ht_info)
192 {
193 struct ath_hw *ah = sc->sc_ah;
194 struct ath_common *common = ath9k_hw_common(ah);
195 u8 tx_streams, rx_streams;
196 int i, max_streams;
197
198 ht_info->ht_supported = true;
199 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
200 IEEE80211_HT_CAP_SM_PS |
201 IEEE80211_HT_CAP_SGI_40 |
202 IEEE80211_HT_CAP_DSSSCCK40;
203
204 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
205 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
206
207 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
208 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
209
210 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
211 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
212
213 if (AR_SREV_9485(ah))
214 max_streams = 1;
215 else if (AR_SREV_9300_20_OR_LATER(ah))
216 max_streams = 3;
217 else
218 max_streams = 2;
219
220 if (AR_SREV_9280_20_OR_LATER(ah)) {
221 if (max_streams >= 2)
222 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
223 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
224 }
225
226 /* set up supported mcs set */
227 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
228 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
229 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
230
231 ath_dbg(common, ATH_DBG_CONFIG,
232 "TX streams %d, RX streams: %d\n",
233 tx_streams, rx_streams);
234
235 if (tx_streams != rx_streams) {
236 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
237 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
238 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
239 }
240
241 for (i = 0; i < rx_streams; i++)
242 ht_info->mcs.rx_mask[i] = 0xff;
243
244 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
245 }
246
247 static int ath9k_reg_notifier(struct wiphy *wiphy,
248 struct regulatory_request *request)
249 {
250 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
251 struct ath_wiphy *aphy = hw->priv;
252 struct ath_softc *sc = aphy->sc;
253 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
254
255 return ath_reg_notifier_apply(wiphy, request, reg);
256 }
257
258 /*
259 * This function will allocate both the DMA descriptor structure, and the
260 * buffers it contains. These are used to contain the descriptors used
261 * by the system.
262 */
263 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
264 struct list_head *head, const char *name,
265 int nbuf, int ndesc, bool is_tx)
266 {
267 #define DS2PHYS(_dd, _ds) \
268 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
269 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
270 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
271 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
272 u8 *ds;
273 struct ath_buf *bf;
274 int i, bsize, error, desc_len;
275
276 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
277 name, nbuf, ndesc);
278
279 INIT_LIST_HEAD(head);
280
281 if (is_tx)
282 desc_len = sc->sc_ah->caps.tx_desc_len;
283 else
284 desc_len = sizeof(struct ath_desc);
285
286 /* ath_desc must be a multiple of DWORDs */
287 if ((desc_len % 4) != 0) {
288 ath_err(common, "ath_desc not DWORD aligned\n");
289 BUG_ON((desc_len % 4) != 0);
290 error = -ENOMEM;
291 goto fail;
292 }
293
294 dd->dd_desc_len = desc_len * nbuf * ndesc;
295
296 /*
297 * Need additional DMA memory because we can't use
298 * descriptors that cross the 4K page boundary. Assume
299 * one skipped descriptor per 4K page.
300 */
301 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
302 u32 ndesc_skipped =
303 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
304 u32 dma_len;
305
306 while (ndesc_skipped) {
307 dma_len = ndesc_skipped * desc_len;
308 dd->dd_desc_len += dma_len;
309
310 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
311 }
312 }
313
314 /* allocate descriptors */
315 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
316 &dd->dd_desc_paddr, GFP_KERNEL);
317 if (dd->dd_desc == NULL) {
318 error = -ENOMEM;
319 goto fail;
320 }
321 ds = (u8 *) dd->dd_desc;
322 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
323 name, ds, (u32) dd->dd_desc_len,
324 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
325
326 /* allocate buffers */
327 bsize = sizeof(struct ath_buf) * nbuf;
328 bf = kzalloc(bsize, GFP_KERNEL);
329 if (bf == NULL) {
330 error = -ENOMEM;
331 goto fail2;
332 }
333 dd->dd_bufptr = bf;
334
335 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
336 bf->bf_desc = ds;
337 bf->bf_daddr = DS2PHYS(dd, ds);
338
339 if (!(sc->sc_ah->caps.hw_caps &
340 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
341 /*
342 * Skip descriptor addresses which can cause 4KB
343 * boundary crossing (addr + length) with a 32 dword
344 * descriptor fetch.
345 */
346 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
347 BUG_ON((caddr_t) bf->bf_desc >=
348 ((caddr_t) dd->dd_desc +
349 dd->dd_desc_len));
350
351 ds += (desc_len * ndesc);
352 bf->bf_desc = ds;
353 bf->bf_daddr = DS2PHYS(dd, ds);
354 }
355 }
356 list_add_tail(&bf->list, head);
357 }
358 return 0;
359 fail2:
360 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
361 dd->dd_desc_paddr);
362 fail:
363 memset(dd, 0, sizeof(*dd));
364 return error;
365 #undef ATH_DESC_4KB_BOUND_CHECK
366 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
367 #undef DS2PHYS
368 }
369
370 static void ath9k_init_crypto(struct ath_softc *sc)
371 {
372 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
373 int i = 0;
374
375 /* Get the hardware key cache size. */
376 common->keymax = sc->sc_ah->caps.keycache_size;
377 if (common->keymax > ATH_KEYMAX) {
378 ath_dbg(common, ATH_DBG_ANY,
379 "Warning, using only %u entries in %u key cache\n",
380 ATH_KEYMAX, common->keymax);
381 common->keymax = ATH_KEYMAX;
382 }
383
384 /*
385 * Reset the key cache since some parts do not
386 * reset the contents on initial power up.
387 */
388 for (i = 0; i < common->keymax; i++)
389 ath_hw_keyreset(common, (u16) i);
390
391 /*
392 * Check whether the separate key cache entries
393 * are required to handle both tx+rx MIC keys.
394 * With split mic keys the number of stations is limited
395 * to 27 otherwise 59.
396 */
397 if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
398 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
399 }
400
401 static int ath9k_init_btcoex(struct ath_softc *sc)
402 {
403 struct ath_txq *txq;
404 int r;
405
406 switch (sc->sc_ah->btcoex_hw.scheme) {
407 case ATH_BTCOEX_CFG_NONE:
408 break;
409 case ATH_BTCOEX_CFG_2WIRE:
410 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
411 break;
412 case ATH_BTCOEX_CFG_3WIRE:
413 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
414 r = ath_init_btcoex_timer(sc);
415 if (r)
416 return -1;
417 txq = sc->tx.txq_map[WME_AC_BE];
418 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
419 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
420 break;
421 default:
422 WARN_ON(1);
423 break;
424 }
425
426 return 0;
427 }
428
429 static int ath9k_init_queues(struct ath_softc *sc)
430 {
431 int i = 0;
432
433 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
434 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
435
436 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
437 ath_cabq_update(sc);
438
439 for (i = 0; i < WME_NUM_AC; i++)
440 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
441
442 return 0;
443 }
444
445 static int ath9k_init_channels_rates(struct ath_softc *sc)
446 {
447 void *channels;
448
449 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
450 ARRAY_SIZE(ath9k_5ghz_chantable) !=
451 ATH9K_NUM_CHANNELS);
452
453 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
454 channels = kmemdup(ath9k_2ghz_chantable,
455 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
456 if (!channels)
457 return -ENOMEM;
458
459 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
460 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
461 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
462 ARRAY_SIZE(ath9k_2ghz_chantable);
463 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
464 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
465 ARRAY_SIZE(ath9k_legacy_rates);
466 }
467
468 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
469 channels = kmemdup(ath9k_5ghz_chantable,
470 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
471 if (!channels) {
472 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
473 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
474 return -ENOMEM;
475 }
476
477 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
478 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
479 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
480 ARRAY_SIZE(ath9k_5ghz_chantable);
481 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
482 ath9k_legacy_rates + 4;
483 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
484 ARRAY_SIZE(ath9k_legacy_rates) - 4;
485 }
486 return 0;
487 }
488
489 static void ath9k_init_misc(struct ath_softc *sc)
490 {
491 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
492 int i = 0;
493
494 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
495
496 sc->config.txpowlimit = ATH_TXPOWER_MAX;
497
498 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
499 sc->sc_flags |= SC_OP_TXAGGR;
500 sc->sc_flags |= SC_OP_RXAGGR;
501 }
502
503 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
504 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
505
506 ath9k_hw_set_diversity(sc->sc_ah, true);
507 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
508
509 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
510
511 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
512
513 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
514 sc->beacon.bslot[i] = NULL;
515 sc->beacon.bslot_aphy[i] = NULL;
516 }
517
518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
519 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
520 }
521
522 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
523 const struct ath_bus_ops *bus_ops)
524 {
525 struct ath_hw *ah = NULL;
526 struct ath_common *common;
527 int ret = 0, i;
528 int csz = 0;
529
530 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
531 if (!ah)
532 return -ENOMEM;
533
534 ah->hw_version.devid = devid;
535 ah->hw_version.subsysid = subsysid;
536 sc->sc_ah = ah;
537
538 if (!sc->dev->platform_data)
539 ah->ah_flags |= AH_USE_EEPROM;
540
541 common = ath9k_hw_common(ah);
542 common->ops = &ath9k_common_ops;
543 common->bus_ops = bus_ops;
544 common->ah = ah;
545 common->hw = sc->hw;
546 common->priv = sc;
547 common->debug_mask = ath9k_debug;
548 common->btcoex_enabled = ath9k_btcoex_enable == 1;
549 spin_lock_init(&common->cc_lock);
550
551 spin_lock_init(&sc->wiphy_lock);
552 spin_lock_init(&sc->sc_serial_rw);
553 spin_lock_init(&sc->sc_pm_lock);
554 mutex_init(&sc->mutex);
555 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
556 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
557 (unsigned long)sc);
558
559 /*
560 * Cache line size is used to size and align various
561 * structures used to communicate with the hardware.
562 */
563 ath_read_cachesize(common, &csz);
564 common->cachelsz = csz << 2; /* convert to bytes */
565
566 /* Initializes the hardware for all supported chipsets */
567 ret = ath9k_hw_init(ah);
568 if (ret)
569 goto err_hw;
570
571 ret = ath9k_init_queues(sc);
572 if (ret)
573 goto err_queues;
574
575 ret = ath9k_init_btcoex(sc);
576 if (ret)
577 goto err_btcoex;
578
579 ret = ath9k_init_channels_rates(sc);
580 if (ret)
581 goto err_btcoex;
582
583 ath9k_init_crypto(sc);
584 ath9k_init_misc(sc);
585
586 return 0;
587
588 err_btcoex:
589 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
590 if (ATH_TXQ_SETUP(sc, i))
591 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
592 err_queues:
593 ath9k_hw_deinit(ah);
594 err_hw:
595 tasklet_kill(&sc->intr_tq);
596 tasklet_kill(&sc->bcon_tasklet);
597
598 kfree(ah);
599 sc->sc_ah = NULL;
600
601 return ret;
602 }
603
604 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
605 {
606 struct ieee80211_supported_band *sband;
607 struct ieee80211_channel *chan;
608 struct ath_hw *ah = sc->sc_ah;
609 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
610 int i;
611
612 sband = &sc->sbands[band];
613 for (i = 0; i < sband->n_channels; i++) {
614 chan = &sband->channels[i];
615 ah->curchan = &ah->channels[chan->hw_value];
616 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
617 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
618 chan->max_power = reg->max_power_level / 2;
619 }
620 }
621
622 static void ath9k_init_txpower_limits(struct ath_softc *sc)
623 {
624 struct ath_hw *ah = sc->sc_ah;
625 struct ath9k_channel *curchan = ah->curchan;
626
627 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
628 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
629 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
630 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
631
632 ah->curchan = curchan;
633 }
634
635 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
636 {
637 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
638
639 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
640 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
641 IEEE80211_HW_SIGNAL_DBM |
642 IEEE80211_HW_SUPPORTS_PS |
643 IEEE80211_HW_PS_NULLFUNC_STACK |
644 IEEE80211_HW_SPECTRUM_MGMT |
645 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
646 IEEE80211_HW_NEED_DTIM_PERIOD;
647
648 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
649 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
650
651 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
652 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
653
654 hw->wiphy->interface_modes =
655 BIT(NL80211_IFTYPE_P2P_GO) |
656 BIT(NL80211_IFTYPE_P2P_CLIENT) |
657 BIT(NL80211_IFTYPE_AP) |
658 BIT(NL80211_IFTYPE_WDS) |
659 BIT(NL80211_IFTYPE_STATION) |
660 BIT(NL80211_IFTYPE_ADHOC) |
661 BIT(NL80211_IFTYPE_MESH_POINT);
662
663 if (AR_SREV_5416(sc->sc_ah))
664 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
665
666 hw->queues = 4;
667 hw->max_rates = 4;
668 hw->channel_change_time = 5000;
669 hw->max_listen_interval = 10;
670 hw->max_rate_tries = 10;
671 hw->sta_data_size = sizeof(struct ath_node);
672 hw->vif_data_size = sizeof(struct ath_vif);
673
674 #ifdef CONFIG_ATH9K_RATE_CONTROL
675 hw->rate_control_algorithm = "ath9k_rate_control";
676 #endif
677
678 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
679 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
680 &sc->sbands[IEEE80211_BAND_2GHZ];
681 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
682 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
683 &sc->sbands[IEEE80211_BAND_5GHZ];
684
685 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
686 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
687 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
688 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
689 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
690 }
691
692 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
693 }
694
695 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
696 const struct ath_bus_ops *bus_ops)
697 {
698 struct ieee80211_hw *hw = sc->hw;
699 struct ath_wiphy *aphy = hw->priv;
700 struct ath_common *common;
701 struct ath_hw *ah;
702 int error = 0;
703 struct ath_regulatory *reg;
704
705 /* Bring up device */
706 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
707 if (error != 0)
708 goto error_init;
709
710 ah = sc->sc_ah;
711 common = ath9k_hw_common(ah);
712 ath9k_set_hw_capab(sc, hw);
713
714 /* Initialize regulatory */
715 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
716 ath9k_reg_notifier);
717 if (error)
718 goto error_regd;
719
720 reg = &common->regulatory;
721
722 /* Setup TX DMA */
723 error = ath_tx_init(sc, ATH_TXBUF);
724 if (error != 0)
725 goto error_tx;
726
727 /* Setup RX DMA */
728 error = ath_rx_init(sc, ATH_RXBUF);
729 if (error != 0)
730 goto error_rx;
731
732 ath9k_init_txpower_limits(sc);
733
734 /* Register with mac80211 */
735 error = ieee80211_register_hw(hw);
736 if (error)
737 goto error_register;
738
739 error = ath9k_init_debug(ah);
740 if (error) {
741 ath_err(common, "Unable to create debugfs files\n");
742 goto error_world;
743 }
744
745 /* Handle world regulatory */
746 if (!ath_is_world_regd(reg)) {
747 error = regulatory_hint(hw->wiphy, reg->alpha2);
748 if (error)
749 goto error_world;
750 }
751
752 INIT_WORK(&sc->hw_check_work, ath_hw_check);
753 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
754 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
755 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
756 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
757 aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
758
759 ath_init_leds(sc);
760 ath_start_rfkill_poll(sc);
761
762 pm_qos_add_request(&sc->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
763 PM_QOS_DEFAULT_VALUE);
764
765 return 0;
766
767 error_world:
768 ieee80211_unregister_hw(hw);
769 error_register:
770 ath_rx_cleanup(sc);
771 error_rx:
772 ath_tx_cleanup(sc);
773 error_tx:
774 /* Nothing */
775 error_regd:
776 ath9k_deinit_softc(sc);
777 error_init:
778 return error;
779 }
780
781 /*****************************/
782 /* De-Initialization */
783 /*****************************/
784
785 static void ath9k_deinit_softc(struct ath_softc *sc)
786 {
787 int i = 0;
788
789 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
790 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
791
792 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
793 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
794
795 if ((sc->btcoex.no_stomp_timer) &&
796 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
797 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
798
799 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
800 if (ATH_TXQ_SETUP(sc, i))
801 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
802
803 ath9k_hw_deinit(sc->sc_ah);
804
805 tasklet_kill(&sc->intr_tq);
806 tasklet_kill(&sc->bcon_tasklet);
807
808 kfree(sc->sc_ah);
809 sc->sc_ah = NULL;
810 }
811
812 void ath9k_deinit_device(struct ath_softc *sc)
813 {
814 struct ieee80211_hw *hw = sc->hw;
815 int i = 0;
816
817 ath9k_ps_wakeup(sc);
818
819 wiphy_rfkill_stop_polling(sc->hw->wiphy);
820 ath_deinit_leds(sc);
821
822 for (i = 0; i < sc->num_sec_wiphy; i++) {
823 struct ath_wiphy *aphy = sc->sec_wiphy[i];
824 if (aphy == NULL)
825 continue;
826 sc->sec_wiphy[i] = NULL;
827 ieee80211_unregister_hw(aphy->hw);
828 ieee80211_free_hw(aphy->hw);
829 }
830
831 ieee80211_unregister_hw(hw);
832 pm_qos_remove_request(&sc->pm_qos_req);
833 ath_rx_cleanup(sc);
834 ath_tx_cleanup(sc);
835 ath9k_deinit_softc(sc);
836 kfree(sc->sec_wiphy);
837 }
838
839 void ath_descdma_cleanup(struct ath_softc *sc,
840 struct ath_descdma *dd,
841 struct list_head *head)
842 {
843 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
844 dd->dd_desc_paddr);
845
846 INIT_LIST_HEAD(head);
847 kfree(dd->dd_bufptr);
848 memset(dd, 0, sizeof(*dd));
849 }
850
851 /************************/
852 /* Module Hooks */
853 /************************/
854
855 static int __init ath9k_init(void)
856 {
857 int error;
858
859 /* Register rate control algorithm */
860 error = ath_rate_control_register();
861 if (error != 0) {
862 printk(KERN_ERR
863 "ath9k: Unable to register rate control "
864 "algorithm: %d\n",
865 error);
866 goto err_out;
867 }
868
869 error = ath_pci_init();
870 if (error < 0) {
871 printk(KERN_ERR
872 "ath9k: No PCI devices found, driver not installed.\n");
873 error = -ENODEV;
874 goto err_rate_unregister;
875 }
876
877 error = ath_ahb_init();
878 if (error < 0) {
879 error = -ENODEV;
880 goto err_pci_exit;
881 }
882
883 return 0;
884
885 err_pci_exit:
886 ath_pci_exit();
887
888 err_rate_unregister:
889 ath_rate_control_unregister();
890 err_out:
891 return error;
892 }
893 module_init(ath9k_init);
894
895 static void __exit ath9k_exit(void)
896 {
897 ath_ahb_exit();
898 ath_pci_exit();
899 ath_rate_control_unregister();
900 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
901 }
902 module_exit(ath9k_exit);
kernel source for telekom puls (alcatel/mediatek)