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ath9k_hw: add a new API for setting tx descriptors
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / hw.h
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33
34 #define ATHEROS_VENDOR_ID 0x168c
35
36 #define AR5416_DEVID_PCI 0x0023
37 #define AR5416_DEVID_PCIE 0x0024
38 #define AR9160_DEVID_PCI 0x0027
39 #define AR9280_DEVID_PCI 0x0029
40 #define AR9280_DEVID_PCIE 0x002a
41 #define AR9285_DEVID_PCIE 0x002b
42 #define AR2427_DEVID_PCIE 0x002c
43 #define AR9287_DEVID_PCI 0x002d
44 #define AR9287_DEVID_PCIE 0x002e
45 #define AR9300_DEVID_PCIE 0x0030
46 #define AR9300_DEVID_AR9340 0x0031
47 #define AR9300_DEVID_AR9485_PCIE 0x0032
48 #define AR9300_DEVID_AR9580 0x0033
49 #define AR9300_DEVID_AR9480 0x0034
50 #define AR9300_DEVID_AR9330 0x0035
51
52 #define AR5416_AR9100_DEVID 0x000b
53
54 #define AR_SUBVENDOR_ID_NOG 0x0e11
55 #define AR_SUBVENDOR_ID_NEW_A 0x7065
56 #define AR5416_MAGIC 0x19641014
57
58 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
59 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
61
62 #define AR9300_NUM_BT_WEIGHTS 4
63 #define AR9300_NUM_WLAN_WEIGHTS 4
64
65 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
66
67 #define ATH_DEFAULT_NOISE_FLOOR -95
68
69 #define ATH9K_RSSI_BAD -128
70
71 #define ATH9K_NUM_CHANNELS 38
72
73 /* Register read/write primitives */
74 #define REG_WRITE(_ah, _reg, _val) \
75 (_ah)->reg_ops.write((_ah), (_val), (_reg))
76
77 #define REG_READ(_ah, _reg) \
78 (_ah)->reg_ops.read((_ah), (_reg))
79
80 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
81 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
82
83 #define REG_RMW(_ah, _reg, _set, _clr) \
84 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
85
86 #define ENABLE_REGWRITE_BUFFER(_ah) \
87 do { \
88 if ((_ah)->reg_ops.enable_write_buffer) \
89 (_ah)->reg_ops.enable_write_buffer((_ah)); \
90 } while (0)
91
92 #define REGWRITE_BUFFER_FLUSH(_ah) \
93 do { \
94 if ((_ah)->reg_ops.write_flush) \
95 (_ah)->reg_ops.write_flush((_ah)); \
96 } while (0)
97
98 #define PR_EEP(_s, _val) \
99 do { \
100 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
101 _s, (_val)); \
102 } while (0)
103
104 #define SM(_v, _f) (((_v) << _f##_S) & _f)
105 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
106 #define REG_RMW_FIELD(_a, _r, _f, _v) \
107 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
108 #define REG_READ_FIELD(_a, _r, _f) \
109 (((REG_READ(_a, _r) & _f) >> _f##_S))
110 #define REG_SET_BIT(_a, _r, _f) \
111 REG_RMW(_a, _r, (_f), 0)
112 #define REG_CLR_BIT(_a, _r, _f) \
113 REG_RMW(_a, _r, 0, (_f))
114
115 #define DO_DELAY(x) do { \
116 if (((++(x) % 64) == 0) && \
117 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
118 != ATH_USB)) \
119 udelay(1); \
120 } while (0)
121
122 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
123 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
124
125 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
126 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
127 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
128 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
129 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
130 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
131 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
132
133 #define AR_GPIOD_MASK 0x00001FFF
134 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
135
136 #define BASE_ACTIVATE_DELAY 100
137 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
138 #define COEF_SCALE_S 24
139 #define HT40_CHANNEL_CENTER_SHIFT 10
140
141 #define ATH9K_ANTENNA0_CHAINMASK 0x1
142 #define ATH9K_ANTENNA1_CHAINMASK 0x2
143
144 #define ATH9K_NUM_DMA_DEBUG_REGS 8
145 #define ATH9K_NUM_QUEUES 10
146
147 #define MAX_RATE_POWER 63
148 #define AH_WAIT_TIMEOUT 100000 /* (us) */
149 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
150 #define AH_TIME_QUANTUM 10
151 #define AR_KEYTABLE_SIZE 128
152 #define POWER_UP_TIME 10000
153 #define SPUR_RSSI_THRESH 40
154 #define UPPER_5G_SUB_BAND_START 5700
155 #define MID_5G_SUB_BAND_START 5400
156
157 #define CAB_TIMEOUT_VAL 10
158 #define BEACON_TIMEOUT_VAL 10
159 #define MIN_BEACON_TIMEOUT_VAL 1
160 #define SLEEP_SLOP 3
161
162 #define INIT_CONFIG_STATUS 0x00000000
163 #define INIT_RSSI_THR 0x00000700
164 #define INIT_BCON_CNTRL_REG 0x00000000
165
166 #define TU_TO_USEC(_tu) ((_tu) << 10)
167
168 #define ATH9K_HW_RX_HP_QDEPTH 16
169 #define ATH9K_HW_RX_LP_QDEPTH 128
170
171 #define PAPRD_GAIN_TABLE_ENTRIES 32
172 #define PAPRD_TABLE_SZ 24
173 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
174
175 enum ath_hw_txq_subtype {
176 ATH_TXQ_AC_BE = 0,
177 ATH_TXQ_AC_BK = 1,
178 ATH_TXQ_AC_VI = 2,
179 ATH_TXQ_AC_VO = 3,
180 };
181
182 enum ath_ini_subsys {
183 ATH_INI_PRE = 0,
184 ATH_INI_CORE,
185 ATH_INI_POST,
186 ATH_INI_NUM_SPLIT,
187 };
188
189 enum ath9k_hw_caps {
190 ATH9K_HW_CAP_HT = BIT(0),
191 ATH9K_HW_CAP_RFSILENT = BIT(1),
192 ATH9K_HW_CAP_CST = BIT(2),
193 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
194 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
195 ATH9K_HW_CAP_EDMA = BIT(6),
196 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
197 ATH9K_HW_CAP_LDPC = BIT(8),
198 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
199 ATH9K_HW_CAP_SGI_20 = BIT(10),
200 ATH9K_HW_CAP_PAPRD = BIT(11),
201 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
202 ATH9K_HW_CAP_2GHZ = BIT(13),
203 ATH9K_HW_CAP_5GHZ = BIT(14),
204 ATH9K_HW_CAP_APM = BIT(15),
205 };
206
207 struct ath9k_hw_capabilities {
208 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
209 u16 rts_aggr_limit;
210 u8 tx_chainmask;
211 u8 rx_chainmask;
212 u8 max_txchains;
213 u8 max_rxchains;
214 u8 num_gpio_pins;
215 u8 rx_hp_qdepth;
216 u8 rx_lp_qdepth;
217 u8 rx_status_len;
218 u8 tx_desc_len;
219 u8 txs_len;
220 u16 pcie_lcr_offset;
221 bool pcie_lcr_extsync_en;
222 };
223
224 struct ath9k_ops_config {
225 int dma_beacon_response_time;
226 int sw_beacon_response_time;
227 int additional_swba_backoff;
228 int ack_6mb;
229 u32 cwm_ignore_extcca;
230 bool pcieSerDesWrite;
231 u8 pcie_clock_req;
232 u32 pcie_waen;
233 u8 analog_shiftreg;
234 u8 paprd_disable;
235 u32 ofdm_trig_low;
236 u32 ofdm_trig_high;
237 u32 cck_trig_high;
238 u32 cck_trig_low;
239 u32 enable_ani;
240 int serialize_regmode;
241 bool rx_intr_mitigation;
242 bool tx_intr_mitigation;
243 #define SPUR_DISABLE 0
244 #define SPUR_ENABLE_IOCTL 1
245 #define SPUR_ENABLE_EEPROM 2
246 #define AR_SPUR_5413_1 1640
247 #define AR_SPUR_5413_2 1200
248 #define AR_NO_SPUR 0x8000
249 #define AR_BASE_FREQ_2GHZ 2300
250 #define AR_BASE_FREQ_5GHZ 4900
251 #define AR_SPUR_FEEQ_BOUND_HT40 19
252 #define AR_SPUR_FEEQ_BOUND_HT20 10
253 int spurmode;
254 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
255 u8 max_txtrig_level;
256 u16 ani_poll_interval; /* ANI poll interval in ms */
257 };
258
259 enum ath9k_int {
260 ATH9K_INT_RX = 0x00000001,
261 ATH9K_INT_RXDESC = 0x00000002,
262 ATH9K_INT_RXHP = 0x00000001,
263 ATH9K_INT_RXLP = 0x00000002,
264 ATH9K_INT_RXNOFRM = 0x00000008,
265 ATH9K_INT_RXEOL = 0x00000010,
266 ATH9K_INT_RXORN = 0x00000020,
267 ATH9K_INT_TX = 0x00000040,
268 ATH9K_INT_TXDESC = 0x00000080,
269 ATH9K_INT_TIM_TIMER = 0x00000100,
270 ATH9K_INT_BB_WATCHDOG = 0x00000400,
271 ATH9K_INT_TXURN = 0x00000800,
272 ATH9K_INT_MIB = 0x00001000,
273 ATH9K_INT_RXPHY = 0x00004000,
274 ATH9K_INT_RXKCM = 0x00008000,
275 ATH9K_INT_SWBA = 0x00010000,
276 ATH9K_INT_BMISS = 0x00040000,
277 ATH9K_INT_BNR = 0x00100000,
278 ATH9K_INT_TIM = 0x00200000,
279 ATH9K_INT_DTIM = 0x00400000,
280 ATH9K_INT_DTIMSYNC = 0x00800000,
281 ATH9K_INT_GPIO = 0x01000000,
282 ATH9K_INT_CABEND = 0x02000000,
283 ATH9K_INT_TSFOOR = 0x04000000,
284 ATH9K_INT_GENTIMER = 0x08000000,
285 ATH9K_INT_CST = 0x10000000,
286 ATH9K_INT_GTT = 0x20000000,
287 ATH9K_INT_FATAL = 0x40000000,
288 ATH9K_INT_GLOBAL = 0x80000000,
289 ATH9K_INT_BMISC = ATH9K_INT_TIM |
290 ATH9K_INT_DTIM |
291 ATH9K_INT_DTIMSYNC |
292 ATH9K_INT_TSFOOR |
293 ATH9K_INT_CABEND,
294 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
295 ATH9K_INT_RXDESC |
296 ATH9K_INT_RXEOL |
297 ATH9K_INT_RXORN |
298 ATH9K_INT_TXURN |
299 ATH9K_INT_TXDESC |
300 ATH9K_INT_MIB |
301 ATH9K_INT_RXPHY |
302 ATH9K_INT_RXKCM |
303 ATH9K_INT_SWBA |
304 ATH9K_INT_BMISS |
305 ATH9K_INT_GPIO,
306 ATH9K_INT_NOCARD = 0xffffffff
307 };
308
309 #define CHANNEL_CW_INT 0x00002
310 #define CHANNEL_CCK 0x00020
311 #define CHANNEL_OFDM 0x00040
312 #define CHANNEL_2GHZ 0x00080
313 #define CHANNEL_5GHZ 0x00100
314 #define CHANNEL_PASSIVE 0x00200
315 #define CHANNEL_DYN 0x00400
316 #define CHANNEL_HALF 0x04000
317 #define CHANNEL_QUARTER 0x08000
318 #define CHANNEL_HT20 0x10000
319 #define CHANNEL_HT40PLUS 0x20000
320 #define CHANNEL_HT40MINUS 0x40000
321
322 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
323 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
324 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
325 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
326 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
327 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
328 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
329 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
330 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
331 #define CHANNEL_ALL \
332 (CHANNEL_OFDM| \
333 CHANNEL_CCK| \
334 CHANNEL_2GHZ | \
335 CHANNEL_5GHZ | \
336 CHANNEL_HT20 | \
337 CHANNEL_HT40PLUS | \
338 CHANNEL_HT40MINUS)
339
340 struct ath9k_hw_cal_data {
341 u16 channel;
342 u32 channelFlags;
343 int32_t CalValid;
344 int8_t iCoff;
345 int8_t qCoff;
346 bool paprd_done;
347 bool nfcal_pending;
348 bool nfcal_interference;
349 u16 small_signal_gain[AR9300_MAX_CHAINS];
350 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
351 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
352 };
353
354 struct ath9k_channel {
355 struct ieee80211_channel *chan;
356 struct ar5416AniState ani;
357 u16 channel;
358 u32 channelFlags;
359 u32 chanmode;
360 s16 noisefloor;
361 };
362
363 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
364 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
365 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
367 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
368 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
369 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
370 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
371 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
372 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
373 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
374 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
375
376 /* These macros check chanmode and not channelFlags */
377 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
378 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
379 ((_c)->chanmode == CHANNEL_G_HT20))
380 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
381 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
382 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
384 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
385
386 enum ath9k_power_mode {
387 ATH9K_PM_AWAKE = 0,
388 ATH9K_PM_FULL_SLEEP,
389 ATH9K_PM_NETWORK_SLEEP,
390 ATH9K_PM_UNDEFINED
391 };
392
393 enum ath9k_tp_scale {
394 ATH9K_TP_SCALE_MAX = 0,
395 ATH9K_TP_SCALE_50,
396 ATH9K_TP_SCALE_25,
397 ATH9K_TP_SCALE_12,
398 ATH9K_TP_SCALE_MIN
399 };
400
401 enum ser_reg_mode {
402 SER_REG_MODE_OFF = 0,
403 SER_REG_MODE_ON = 1,
404 SER_REG_MODE_AUTO = 2,
405 };
406
407 enum ath9k_rx_qtype {
408 ATH9K_RX_QUEUE_HP,
409 ATH9K_RX_QUEUE_LP,
410 ATH9K_RX_QUEUE_MAX,
411 };
412
413 struct ath9k_beacon_state {
414 u32 bs_nexttbtt;
415 u32 bs_nextdtim;
416 u32 bs_intval;
417 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
418 u32 bs_dtimperiod;
419 u16 bs_cfpperiod;
420 u16 bs_cfpmaxduration;
421 u32 bs_cfpnext;
422 u16 bs_timoffset;
423 u16 bs_bmissthreshold;
424 u32 bs_sleepduration;
425 u32 bs_tsfoor_threshold;
426 };
427
428 struct chan_centers {
429 u16 synth_center;
430 u16 ctl_center;
431 u16 ext_center;
432 };
433
434 enum {
435 ATH9K_RESET_POWER_ON,
436 ATH9K_RESET_WARM,
437 ATH9K_RESET_COLD,
438 };
439
440 struct ath9k_hw_version {
441 u32 magic;
442 u16 devid;
443 u16 subvendorid;
444 u32 macVersion;
445 u16 macRev;
446 u16 phyRev;
447 u16 analog5GhzRev;
448 u16 analog2GhzRev;
449 enum ath_usb_dev usbdev;
450 };
451
452 /* Generic TSF timer definitions */
453
454 #define ATH_MAX_GEN_TIMER 16
455
456 #define AR_GENTMR_BIT(_index) (1 << (_index))
457
458 /*
459 * Using de Bruijin sequence to look up 1's index in a 32 bit number
460 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
461 */
462 #define debruijn32 0x077CB531U
463
464 struct ath_gen_timer_configuration {
465 u32 next_addr;
466 u32 period_addr;
467 u32 mode_addr;
468 u32 mode_mask;
469 };
470
471 struct ath_gen_timer {
472 void (*trigger)(void *arg);
473 void (*overflow)(void *arg);
474 void *arg;
475 u8 index;
476 };
477
478 struct ath_gen_timer_table {
479 u32 gen_timer_index[32];
480 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
481 union {
482 unsigned long timer_bits;
483 u16 val;
484 } timer_mask;
485 };
486
487 struct ath_hw_antcomb_conf {
488 u8 main_lna_conf;
489 u8 alt_lna_conf;
490 u8 fast_div_bias;
491 u8 main_gaintb;
492 u8 alt_gaintb;
493 int lna1_lna2_delta;
494 u8 div_group;
495 };
496
497 /**
498 * struct ath_hw_radar_conf - radar detection initialization parameters
499 *
500 * @pulse_inband: threshold for checking the ratio of in-band power
501 * to total power for short radar pulses (half dB steps)
502 * @pulse_inband_step: threshold for checking an in-band power to total
503 * power ratio increase for short radar pulses (half dB steps)
504 * @pulse_height: threshold for detecting the beginning of a short
505 * radar pulse (dB step)
506 * @pulse_rssi: threshold for detecting if a short radar pulse is
507 * gone (dB step)
508 * @pulse_maxlen: maximum pulse length (0.8 us steps)
509 *
510 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
511 * @radar_inband: threshold for checking the ratio of in-band power
512 * to total power for long radar pulses (half dB steps)
513 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
514 *
515 * @ext_channel: enable extension channel radar detection
516 */
517 struct ath_hw_radar_conf {
518 unsigned int pulse_inband;
519 unsigned int pulse_inband_step;
520 unsigned int pulse_height;
521 unsigned int pulse_rssi;
522 unsigned int pulse_maxlen;
523
524 unsigned int radar_rssi;
525 unsigned int radar_inband;
526 int fir_power;
527
528 bool ext_channel;
529 };
530
531 /**
532 * struct ath_hw_private_ops - callbacks used internally by hardware code
533 *
534 * This structure contains private callbacks designed to only be used internally
535 * by the hardware core.
536 *
537 * @init_cal_settings: setup types of calibrations supported
538 * @init_cal: starts actual calibration
539 *
540 * @init_mode_regs: Initializes mode registers
541 * @init_mode_gain_regs: Initialize TX/RX gain registers
542 *
543 * @rf_set_freq: change frequency
544 * @spur_mitigate_freq: spur mitigation
545 * @rf_alloc_ext_banks:
546 * @rf_free_ext_banks:
547 * @set_rf_regs:
548 * @compute_pll_control: compute the PLL control value to use for
549 * AR_RTC_PLL_CONTROL for a given channel
550 * @setup_calibration: set up calibration
551 * @iscal_supported: used to query if a type of calibration is supported
552 *
553 * @ani_cache_ini_regs: cache the values for ANI from the initial
554 * register settings through the register initialization.
555 */
556 struct ath_hw_private_ops {
557 /* Calibration ops */
558 void (*init_cal_settings)(struct ath_hw *ah);
559 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
560
561 void (*init_mode_regs)(struct ath_hw *ah);
562 void (*init_mode_gain_regs)(struct ath_hw *ah);
563 void (*setup_calibration)(struct ath_hw *ah,
564 struct ath9k_cal_list *currCal);
565
566 /* PHY ops */
567 int (*rf_set_freq)(struct ath_hw *ah,
568 struct ath9k_channel *chan);
569 void (*spur_mitigate_freq)(struct ath_hw *ah,
570 struct ath9k_channel *chan);
571 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
572 void (*rf_free_ext_banks)(struct ath_hw *ah);
573 bool (*set_rf_regs)(struct ath_hw *ah,
574 struct ath9k_channel *chan,
575 u16 modesIndex);
576 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
577 void (*init_bb)(struct ath_hw *ah,
578 struct ath9k_channel *chan);
579 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
580 void (*olc_init)(struct ath_hw *ah);
581 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
582 void (*mark_phy_inactive)(struct ath_hw *ah);
583 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
584 bool (*rfbus_req)(struct ath_hw *ah);
585 void (*rfbus_done)(struct ath_hw *ah);
586 void (*restore_chainmask)(struct ath_hw *ah);
587 void (*set_diversity)(struct ath_hw *ah, bool value);
588 u32 (*compute_pll_control)(struct ath_hw *ah,
589 struct ath9k_channel *chan);
590 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
591 int param);
592 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
593 void (*set_radar_params)(struct ath_hw *ah,
594 struct ath_hw_radar_conf *conf);
595
596 /* ANI */
597 void (*ani_cache_ini_regs)(struct ath_hw *ah);
598 };
599
600 /**
601 * struct ath_hw_ops - callbacks used by hardware code and driver code
602 *
603 * This structure contains callbacks designed to to be used internally by
604 * hardware code and also by the lower level driver.
605 *
606 * @config_pci_powersave:
607 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
608 */
609 struct ath_hw_ops {
610 void (*config_pci_powersave)(struct ath_hw *ah,
611 bool power_off);
612 void (*rx_enable)(struct ath_hw *ah);
613 void (*set_desc_link)(void *ds, u32 link);
614 bool (*calibrate)(struct ath_hw *ah,
615 struct ath9k_channel *chan,
616 u8 rxchainmask,
617 bool longcal);
618 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
619 void (*set_txdesc)(struct ath_hw *ah, void *ds,
620 struct ath_tx_info *i);
621 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
622 bool is_firstseg, bool is_is_lastseg,
623 const void *ds0, dma_addr_t buf_addr,
624 unsigned int qcu);
625 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
626 struct ath_tx_status *ts);
627 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
628 u32 pktLen, enum ath9k_pkt_type type,
629 u32 txPower, u8 keyIx,
630 enum ath9k_key_type keyType,
631 u32 flags);
632 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
633 void *lastds,
634 u32 durUpdateEn, u32 rtsctsRate,
635 u32 rtsctsDuration,
636 struct ath9k_11n_rate_series series[],
637 u32 nseries, u32 flags);
638 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
639 u32 aggrLen);
640 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
641 u32 numDelims);
642 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
643 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
644 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
645 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
646 struct ath_hw_antcomb_conf *antconf);
647 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
648 struct ath_hw_antcomb_conf *antconf);
649
650 };
651
652 struct ath_nf_limits {
653 s16 max;
654 s16 min;
655 s16 nominal;
656 };
657
658 /* ah_flags */
659 #define AH_USE_EEPROM 0x1
660 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
661
662 struct ath_hw {
663 struct ath_ops reg_ops;
664
665 struct ieee80211_hw *hw;
666 struct ath_common common;
667 struct ath9k_hw_version hw_version;
668 struct ath9k_ops_config config;
669 struct ath9k_hw_capabilities caps;
670 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
671 struct ath9k_channel *curchan;
672
673 union {
674 struct ar5416_eeprom_def def;
675 struct ar5416_eeprom_4k map4k;
676 struct ar9287_eeprom map9287;
677 struct ar9300_eeprom ar9300_eep;
678 } eeprom;
679 const struct eeprom_ops *eep_ops;
680
681 bool sw_mgmt_crypto;
682 bool is_pciexpress;
683 bool aspm_enabled;
684 bool is_monitoring;
685 bool need_an_top2_fixup;
686 u16 tx_trig_level;
687
688 u32 nf_regs[6];
689 struct ath_nf_limits nf_2g;
690 struct ath_nf_limits nf_5g;
691 u16 rfsilent;
692 u32 rfkill_gpio;
693 u32 rfkill_polarity;
694 u32 ah_flags;
695
696 bool htc_reset_init;
697
698 enum nl80211_iftype opmode;
699 enum ath9k_power_mode power_mode;
700
701 s8 noise;
702 struct ath9k_hw_cal_data *caldata;
703 struct ath9k_pacal_info pacal_info;
704 struct ar5416Stats stats;
705 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
706
707 int16_t curchan_rad_index;
708 enum ath9k_int imask;
709 u32 imrs2_reg;
710 u32 txok_interrupt_mask;
711 u32 txerr_interrupt_mask;
712 u32 txdesc_interrupt_mask;
713 u32 txeol_interrupt_mask;
714 u32 txurn_interrupt_mask;
715 atomic_t intr_ref_cnt;
716 bool chip_fullsleep;
717 u32 atim_window;
718
719 /* Calibration */
720 u32 supp_cals;
721 struct ath9k_cal_list iq_caldata;
722 struct ath9k_cal_list adcgain_caldata;
723 struct ath9k_cal_list adcdc_caldata;
724 struct ath9k_cal_list tempCompCalData;
725 struct ath9k_cal_list *cal_list;
726 struct ath9k_cal_list *cal_list_last;
727 struct ath9k_cal_list *cal_list_curr;
728 #define totalPowerMeasI meas0.unsign
729 #define totalPowerMeasQ meas1.unsign
730 #define totalIqCorrMeas meas2.sign
731 #define totalAdcIOddPhase meas0.unsign
732 #define totalAdcIEvenPhase meas1.unsign
733 #define totalAdcQOddPhase meas2.unsign
734 #define totalAdcQEvenPhase meas3.unsign
735 #define totalAdcDcOffsetIOddPhase meas0.sign
736 #define totalAdcDcOffsetIEvenPhase meas1.sign
737 #define totalAdcDcOffsetQOddPhase meas2.sign
738 #define totalAdcDcOffsetQEvenPhase meas3.sign
739 union {
740 u32 unsign[AR5416_MAX_CHAINS];
741 int32_t sign[AR5416_MAX_CHAINS];
742 } meas0;
743 union {
744 u32 unsign[AR5416_MAX_CHAINS];
745 int32_t sign[AR5416_MAX_CHAINS];
746 } meas1;
747 union {
748 u32 unsign[AR5416_MAX_CHAINS];
749 int32_t sign[AR5416_MAX_CHAINS];
750 } meas2;
751 union {
752 u32 unsign[AR5416_MAX_CHAINS];
753 int32_t sign[AR5416_MAX_CHAINS];
754 } meas3;
755 u16 cal_samples;
756
757 u32 sta_id1_defaults;
758 u32 misc_mode;
759 enum {
760 AUTO_32KHZ,
761 USE_32KHZ,
762 DONT_USE_32KHZ,
763 } enable_32kHz_clock;
764
765 /* Private to hardware code */
766 struct ath_hw_private_ops private_ops;
767 /* Accessed by the lower level driver */
768 struct ath_hw_ops ops;
769
770 /* Used to program the radio on non single-chip devices */
771 u32 *analogBank0Data;
772 u32 *analogBank1Data;
773 u32 *analogBank2Data;
774 u32 *analogBank3Data;
775 u32 *analogBank6Data;
776 u32 *analogBank6TPCData;
777 u32 *analogBank7Data;
778 u32 *addac5416_21;
779 u32 *bank6Temp;
780
781 u8 txpower_limit;
782 int coverage_class;
783 u32 slottime;
784 u32 globaltxtimeout;
785
786 /* ANI */
787 u32 proc_phyerr;
788 u32 aniperiod;
789 int totalSizeDesired[5];
790 int coarse_high[5];
791 int coarse_low[5];
792 int firpwr[5];
793 enum ath9k_ani_cmd ani_function;
794
795 /* Bluetooth coexistance */
796 struct ath_btcoex_hw btcoex_hw;
797 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
798 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
799
800 u32 intr_txqs;
801 u8 txchainmask;
802 u8 rxchainmask;
803
804 struct ath_hw_radar_conf radar_conf;
805
806 u32 originalGain[22];
807 int initPDADC;
808 int PDADCdelta;
809 int led_pin;
810 u32 gpio_mask;
811 u32 gpio_val;
812
813 struct ar5416IniArray iniModes;
814 struct ar5416IniArray iniCommon;
815 struct ar5416IniArray iniBank0;
816 struct ar5416IniArray iniBB_RfGain;
817 struct ar5416IniArray iniBank1;
818 struct ar5416IniArray iniBank2;
819 struct ar5416IniArray iniBank3;
820 struct ar5416IniArray iniBank6;
821 struct ar5416IniArray iniBank6TPC;
822 struct ar5416IniArray iniBank7;
823 struct ar5416IniArray iniAddac;
824 struct ar5416IniArray iniPcieSerdes;
825 struct ar5416IniArray iniPcieSerdesLowPower;
826 struct ar5416IniArray iniModesAdditional;
827 struct ar5416IniArray iniModesAdditional_40M;
828 struct ar5416IniArray iniModesRxGain;
829 struct ar5416IniArray iniModesTxGain;
830 struct ar5416IniArray iniModes_9271_1_0_only;
831 struct ar5416IniArray iniCckfirNormal;
832 struct ar5416IniArray iniCckfirJapan2484;
833 struct ar5416IniArray ini_japan2484;
834 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
835 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
836 struct ar5416IniArray iniModes_9271_ANI_reg;
837 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
838 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
839 struct ar5416IniArray ini_radio_post_sys2ant;
840 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
841
842 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
843 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
844 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
845 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
846
847 u32 intr_gen_timer_trigger;
848 u32 intr_gen_timer_thresh;
849 struct ath_gen_timer_table hw_gen_timers;
850
851 struct ar9003_txs *ts_ring;
852 void *ts_start;
853 u32 ts_paddr_start;
854 u32 ts_paddr_end;
855 u16 ts_tail;
856 u8 ts_size;
857
858 u32 bb_watchdog_last_status;
859 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
860 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
861
862 unsigned int paprd_target_power;
863 unsigned int paprd_training_power;
864 unsigned int paprd_ratemask;
865 unsigned int paprd_ratemask_ht40;
866 bool paprd_table_write_done;
867 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
868 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
869 /*
870 * Store the permanent value of Reg 0x4004in WARegVal
871 * so we dont have to R/M/W. We should not be reading
872 * this register when in sleep states.
873 */
874 u32 WARegVal;
875
876 /* Enterprise mode cap */
877 u32 ent_mode;
878
879 bool is_clk_25mhz;
880 int (*get_mac_revision)(void);
881 int (*external_reset)(void);
882 };
883
884 struct ath_bus_ops {
885 enum ath_bus_type ath_bus_type;
886 void (*read_cachesize)(struct ath_common *common, int *csz);
887 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
888 void (*bt_coex_prep)(struct ath_common *common);
889 void (*extn_synch_en)(struct ath_common *common);
890 void (*aspm_init)(struct ath_common *common);
891 };
892
893 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
894 {
895 return &ah->common;
896 }
897
898 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
899 {
900 return &(ath9k_hw_common(ah)->regulatory);
901 }
902
903 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
904 {
905 return &ah->private_ops;
906 }
907
908 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
909 {
910 return &ah->ops;
911 }
912
913 static inline u8 get_streams(int mask)
914 {
915 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
916 }
917
918 /* Initialization, Detach, Reset */
919 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
920 void ath9k_hw_deinit(struct ath_hw *ah);
921 int ath9k_hw_init(struct ath_hw *ah);
922 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
923 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
924 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
925 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
926
927 /* GPIO / RFKILL / Antennae */
928 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
929 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
930 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
931 u32 ah_signal_type);
932 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
933 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
934 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
935
936 /* General Operation */
937 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
938 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
939 int column, unsigned int *writecnt);
940 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
941 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
942 u8 phy, int kbps,
943 u32 frameLen, u16 rateix, bool shortPreamble);
944 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
945 struct ath9k_channel *chan,
946 struct chan_centers *centers);
947 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
948 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
949 bool ath9k_hw_phy_disable(struct ath_hw *ah);
950 bool ath9k_hw_disable(struct ath_hw *ah);
951 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
952 void ath9k_hw_setopmode(struct ath_hw *ah);
953 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
954 void ath9k_hw_setbssidmask(struct ath_hw *ah);
955 void ath9k_hw_write_associd(struct ath_hw *ah);
956 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
957 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
958 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
959 void ath9k_hw_reset_tsf(struct ath_hw *ah);
960 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
961 void ath9k_hw_init_global_settings(struct ath_hw *ah);
962 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
963 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
964 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
965 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
966 const struct ath9k_beacon_state *bs);
967 bool ath9k_hw_check_alive(struct ath_hw *ah);
968
969 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
970
971 /* Generic hw timer primitives */
972 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
973 void (*trigger)(void *),
974 void (*overflow)(void *),
975 void *arg,
976 u8 timer_index);
977 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
978 struct ath_gen_timer *timer,
979 u32 timer_next,
980 u32 timer_period);
981 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
982
983 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
984 void ath_gen_timer_isr(struct ath_hw *hw);
985
986 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
987
988 /* HTC */
989 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
990
991 /* PHY */
992 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
993 u32 *coef_mantissa, u32 *coef_exponent);
994
995 /*
996 * Code Specific to AR5008, AR9001 or AR9002,
997 * we stuff these here to avoid callbacks for AR9003.
998 */
999 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
1000 int ar9002_hw_rf_claim(struct ath_hw *ah);
1001 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1002
1003 /*
1004 * Code specific to AR9003, we stuff these here to avoid callbacks
1005 * for older families
1006 */
1007 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1008 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1009 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1010 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1011 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1012 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1013 struct ath9k_hw_cal_data *caldata,
1014 int chain);
1015 int ar9003_paprd_create_curve(struct ath_hw *ah,
1016 struct ath9k_hw_cal_data *caldata, int chain);
1017 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1018 int ar9003_paprd_init_table(struct ath_hw *ah);
1019 bool ar9003_paprd_is_done(struct ath_hw *ah);
1020 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
1021
1022 /* Hardware family op attach helpers */
1023 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1024 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1025 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1026
1027 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1028 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1029
1030 void ar9002_hw_attach_ops(struct ath_hw *ah);
1031 void ar9003_hw_attach_ops(struct ath_hw *ah);
1032
1033 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1034 /*
1035 * ANI work can be shared between all families but a next
1036 * generation implementation of ANI will be used only for AR9003 only
1037 * for now as the other families still need to be tested with the same
1038 * next generation ANI. Feel free to start testing it though for the
1039 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
1040 */
1041 extern int modparam_force_new_ani;
1042 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1043 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
1044 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1045
1046 #define ATH9K_CLOCK_RATE_CCK 22
1047 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1048 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1049 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1050
1051 #endif
kernel source for telekom puls (alcatel/mediatek)