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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
96 else
97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
103 }
104
105 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
106 {
107 struct ath_common *common = ath9k_hw_common(ah);
108
109 return usecs * common->clockrate;
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135 {
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145 }
146
147 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148 {
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157 }
158
159 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
160 u8 phy, int kbps,
161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
163 {
164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
165
166 if (kbps == 0)
167 return 0;
168
169 switch (phy) {
170 case WLAN_RC_PHY_CCK:
171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
172 if (shortPreamble)
173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
177 case WLAN_RC_PHY_OFDM:
178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
204 txTime = 0;
205 break;
206 }
207
208 return txTime;
209 }
210 EXPORT_SYMBOL(ath9k_hw_computetxtime);
211
212 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
215 {
216 int8_t extoff;
217
218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
222 }
223
224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
234
235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
237 /* 25 MHz spacing is supported by hw but not on upper layers */
238 centers->ext_center =
239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
240 }
241
242 /******************/
243 /* Chip Revisions */
244 /******************/
245
246 static void ath9k_hw_read_revisions(struct ath_hw *ah)
247 {
248 u32 val;
249
250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
258 return;
259 }
260
261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
262
263 if (val == 0xFF) {
264 val = REG_READ(ah, AR_SREV);
265 ah->hw_version.macVersion =
266 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
268 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
269 } else {
270 if (!AR_SREV_9100(ah))
271 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
272
273 ah->hw_version.macRev = val & AR_SREV_REVISION;
274
275 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
276 ah->is_pciexpress = true;
277 }
278 }
279
280 /************************************/
281 /* HW Attach, Detach, Init Routines */
282 /************************************/
283
284 static void ath9k_hw_disablepcie(struct ath_hw *ah)
285 {
286 if (!AR_SREV_5416(ah))
287 return;
288
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
298
299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
300 }
301
302 /* This should work for all families including legacy */
303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
304 {
305 struct ath_common *common = ath9k_hw_common(ah);
306 u32 regAddr[2] = { AR_STA_ID0 };
307 u32 regHold[2];
308 static const u32 patternData[4] = {
309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
310 };
311 int i, j, loop_max;
312
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
320 u32 addr = regAddr[i];
321 u32 wrData, rdData;
322
323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
329 ath_err(common,
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
332 return false;
333 }
334 }
335 for (j = 0; j < 4; j++) {
336 wrData = patternData[j];
337 REG_WRITE(ah, addr, wrData);
338 rdData = REG_READ(ah, addr);
339 if (wrData != rdData) {
340 ath_err(common,
341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
342 addr, wrData, rdData);
343 return false;
344 }
345 }
346 REG_WRITE(ah, regAddr[i], regHold[i]);
347 }
348 udelay(100);
349
350 return true;
351 }
352
353 static void ath9k_hw_init_config(struct ath_hw *ah)
354 {
355 int i;
356
357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
363 ah->config.pcie_clock_req = 0;
364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
366 ah->config.enable_ani = true;
367
368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
369 ah->config.spurchans[i][0] = AR_NO_SPUR;
370 ah->config.spurchans[i][1] = AR_NO_SPUR;
371 }
372
373 /* PAPRD needs some more work to be enabled */
374 ah->config.paprd_disable = 1;
375
376 ah->config.rx_intr_mitigation = true;
377 ah->config.pcieSerDesWrite = true;
378
379 /*
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
384 *
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
391 *
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
394 */
395 if (num_possible_cpus() > 1)
396 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
397 }
398
399 static void ath9k_hw_init_defaults(struct ath_hw *ah)
400 {
401 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
402
403 regulatory->country_code = CTRY_DEFAULT;
404 regulatory->power_limit = MAX_RATE_POWER;
405 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
406
407 ah->hw_version.magic = AR5416_MAGIC;
408 ah->hw_version.subvendorid = 0;
409
410 ah->atim_window = 0;
411 ah->sta_id1_defaults =
412 AR_STA_ID1_CRPT_MIC_ENABLE |
413 AR_STA_ID1_MCAST_KSRCH;
414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
417 ah->slottime = 20;
418 ah->globaltxtimeout = (u32) -1;
419 ah->power_mode = ATH9K_PM_UNDEFINED;
420 }
421
422 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
423 {
424 struct ath_common *common = ath9k_hw_common(ah);
425 u32 sum;
426 int i;
427 u16 eeval;
428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
429
430 sum = 0;
431 for (i = 0; i < 3; i++) {
432 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
433 sum += eeval;
434 common->macaddr[2 * i] = eeval >> 8;
435 common->macaddr[2 * i + 1] = eeval & 0xff;
436 }
437 if (sum == 0 || sum == 0xffff * 3)
438 return -EADDRNOTAVAIL;
439
440 return 0;
441 }
442
443 static int ath9k_hw_post_init(struct ath_hw *ah)
444 {
445 struct ath_common *common = ath9k_hw_common(ah);
446 int ecode;
447
448 if (common->bus_ops->ath_bus_type != ATH_USB) {
449 if (!ath9k_hw_chip_test(ah))
450 return -ENODEV;
451 }
452
453 if (!AR_SREV_9300_20_OR_LATER(ah)) {
454 ecode = ar9002_hw_rf_claim(ah);
455 if (ecode != 0)
456 return ecode;
457 }
458
459 ecode = ath9k_hw_eeprom_init(ah);
460 if (ecode != 0)
461 return ecode;
462
463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
464 "Eeprom VER: %d, REV: %d\n",
465 ah->eep_ops->get_eeprom_ver(ah),
466 ah->eep_ops->get_eeprom_rev(ah));
467
468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
469 if (ecode) {
470 ath_err(ath9k_hw_common(ah),
471 "Failed allocating banks for external radio\n");
472 ath9k_hw_rf_free_ext_banks(ah);
473 return ecode;
474 }
475
476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
477 ath9k_hw_ani_setup(ah);
478 ath9k_hw_ani_init(ah);
479 }
480
481 return 0;
482 }
483
484 static void ath9k_hw_attach_ops(struct ath_hw *ah)
485 {
486 if (AR_SREV_9300_20_OR_LATER(ah))
487 ar9003_hw_attach_ops(ah);
488 else
489 ar9002_hw_attach_ops(ah);
490 }
491
492 /* Called for all hardware families */
493 static int __ath9k_hw_init(struct ath_hw *ah)
494 {
495 struct ath_common *common = ath9k_hw_common(ah);
496 int r = 0;
497
498 ath9k_hw_read_revisions(ah);
499
500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
510 ath_err(common, "Couldn't reset chip\n");
511 return -EIO;
512 }
513
514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
517 ath9k_hw_attach_ops(ah);
518
519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
520 ath_err(common, "Couldn't wakeup chip\n");
521 return -EIO;
522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
537 ah->config.serialize_regmode);
538
539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340:
556 break;
557 default:
558 ath_err(common,
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
561 return -EOPNOTSUPP;
562 }
563
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
565 ah->is_pciexpress = false;
566
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
573 if (!AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
575
576 ath9k_hw_init_mode_regs(ah);
577
578
579 if (ah->is_pciexpress)
580 ath9k_hw_configpcipowersave(ah, 0, 0);
581 else
582 ath9k_hw_disablepcie(ah);
583
584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ar9002_hw_cck_chan14_spread(ah);
586
587 r = ath9k_hw_post_init(ah);
588 if (r)
589 return r;
590
591 ath9k_hw_init_mode_gain_regs(ah);
592 r = ath9k_hw_fill_cap_info(ah);
593 if (r)
594 return r;
595
596 r = ath9k_hw_init_macaddr(ah);
597 if (r) {
598 ath_err(common, "Failed to initialize MAC address\n");
599 return r;
600 }
601
602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
604 else
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
606
607 ah->bb_watchdog_timeout_ms = 25;
608
609 common->state = ATH_HW_INITIALIZED;
610
611 return 0;
612 }
613
614 int ath9k_hw_init(struct ath_hw *ah)
615 {
616 int ret;
617 struct ath_common *common = ath9k_hw_common(ah);
618
619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
630 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE:
633 case AR9300_DEVID_AR9340:
634 break;
635 default:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
637 break;
638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
640 return -EOPNOTSUPP;
641 }
642
643 ret = __ath9k_hw_init(ah);
644 if (ret) {
645 ath_err(common,
646 "Unable to initialize hardware; initialization status: %d\n",
647 ret);
648 return ret;
649 }
650
651 return 0;
652 }
653 EXPORT_SYMBOL(ath9k_hw_init);
654
655 static void ath9k_hw_init_qos(struct ath_hw *ah)
656 {
657 ENABLE_REGWRITE_BUFFER(ah);
658
659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
661
662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
666
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
672
673 REGWRITE_BUFFER_FLUSH(ah);
674 }
675
676 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
677 {
678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 udelay(100);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681
682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
683 udelay(100);
684
685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
686 }
687 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
688
689 static void ath9k_hw_init_pll(struct ath_hw *ah,
690 struct ath9k_channel *chan)
691 {
692 u32 pll;
693
694 if (AR_SREV_9485(ah)) {
695
696 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
697 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
698 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
699 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
700 AR_CH0_DPLL2_KD, 0x40);
701 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
702 AR_CH0_DPLL2_KI, 0x4);
703
704 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
705 AR_CH0_BB_DPLL1_REFDIV, 0x5);
706 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
707 AR_CH0_BB_DPLL1_NINI, 0x58);
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
709 AR_CH0_BB_DPLL1_NFRAC, 0x0);
710
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
713 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
714 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
716 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
717
718 /* program BB PLL phase_shift to 0x6 */
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
720 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
721
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
724 udelay(1000);
725 } else if (AR_SREV_9340(ah)) {
726 u32 regval, pll2_divint, pll2_divfrac, refdiv;
727
728 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
729 udelay(1000);
730
731 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
732 udelay(100);
733
734 if (ah->is_clk_25mhz) {
735 pll2_divint = 0x54;
736 pll2_divfrac = 0x1eb85;
737 refdiv = 3;
738 } else {
739 pll2_divint = 88;
740 pll2_divfrac = 0;
741 refdiv = 5;
742 }
743
744 regval = REG_READ(ah, AR_PHY_PLL_MODE);
745 regval |= (0x1 << 16);
746 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
747 udelay(100);
748
749 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
750 (pll2_divint << 18) | pll2_divfrac);
751 udelay(100);
752
753 regval = REG_READ(ah, AR_PHY_PLL_MODE);
754 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
755 (0x4 << 26) | (0x18 << 19);
756 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
757 REG_WRITE(ah, AR_PHY_PLL_MODE,
758 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
759 udelay(1000);
760 }
761
762 pll = ath9k_hw_compute_pll_control(ah, chan);
763
764 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
765
766 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
767 udelay(1000);
768
769 /* Switch the core clock for ar9271 to 117Mhz */
770 if (AR_SREV_9271(ah)) {
771 udelay(500);
772 REG_WRITE(ah, 0x50040, 0x304);
773 }
774
775 udelay(RTC_PLL_SETTLE_DELAY);
776
777 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
778
779 if (AR_SREV_9340(ah)) {
780 if (ah->is_clk_25mhz) {
781 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
782 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
783 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
784 } else {
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
788 }
789 udelay(100);
790 }
791 }
792
793 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
794 enum nl80211_iftype opmode)
795 {
796 u32 sync_default = AR_INTR_SYNC_DEFAULT;
797 u32 imr_reg = AR_IMR_TXERR |
798 AR_IMR_TXURN |
799 AR_IMR_RXERR |
800 AR_IMR_RXORN |
801 AR_IMR_BCNMISC;
802
803 if (AR_SREV_9340(ah))
804 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
805
806 if (AR_SREV_9300_20_OR_LATER(ah)) {
807 imr_reg |= AR_IMR_RXOK_HP;
808 if (ah->config.rx_intr_mitigation)
809 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
810 else
811 imr_reg |= AR_IMR_RXOK_LP;
812
813 } else {
814 if (ah->config.rx_intr_mitigation)
815 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
816 else
817 imr_reg |= AR_IMR_RXOK;
818 }
819
820 if (ah->config.tx_intr_mitigation)
821 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
822 else
823 imr_reg |= AR_IMR_TXOK;
824
825 if (opmode == NL80211_IFTYPE_AP)
826 imr_reg |= AR_IMR_MIB;
827
828 ENABLE_REGWRITE_BUFFER(ah);
829
830 REG_WRITE(ah, AR_IMR, imr_reg);
831 ah->imrs2_reg |= AR_IMR_S2_GTT;
832 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
833
834 if (!AR_SREV_9100(ah)) {
835 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
836 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
837 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
838 }
839
840 REGWRITE_BUFFER_FLUSH(ah);
841
842 if (AR_SREV_9300_20_OR_LATER(ah)) {
843 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
844 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
845 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
846 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
847 }
848 }
849
850 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
851 {
852 u32 val = ath9k_hw_mac_to_clks(ah, us);
853 val = min(val, (u32) 0xFFFF);
854 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
855 }
856
857 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
858 {
859 u32 val = ath9k_hw_mac_to_clks(ah, us);
860 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
861 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
862 }
863
864 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
865 {
866 u32 val = ath9k_hw_mac_to_clks(ah, us);
867 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
868 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
869 }
870
871 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
872 {
873 if (tu > 0xFFFF) {
874 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
875 "bad global tx timeout %u\n", tu);
876 ah->globaltxtimeout = (u32) -1;
877 return false;
878 } else {
879 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
880 ah->globaltxtimeout = tu;
881 return true;
882 }
883 }
884
885 void ath9k_hw_init_global_settings(struct ath_hw *ah)
886 {
887 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
888 int acktimeout;
889 int slottime;
890 int sifstime;
891
892 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
893 ah->misc_mode);
894
895 if (ah->misc_mode != 0)
896 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
897
898 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
899 sifstime = 16;
900 else
901 sifstime = 10;
902
903 /* As defined by IEEE 802.11-2007 17.3.8.6 */
904 slottime = ah->slottime + 3 * ah->coverage_class;
905 acktimeout = slottime + sifstime;
906
907 /*
908 * Workaround for early ACK timeouts, add an offset to match the
909 * initval's 64us ack timeout value.
910 * This was initially only meant to work around an issue with delayed
911 * BA frames in some implementations, but it has been found to fix ACK
912 * timeout issues in other cases as well.
913 */
914 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
915 acktimeout += 64 - sifstime - ah->slottime;
916
917 ath9k_hw_setslottime(ah, ah->slottime);
918 ath9k_hw_set_ack_timeout(ah, acktimeout);
919 ath9k_hw_set_cts_timeout(ah, acktimeout);
920 if (ah->globaltxtimeout != (u32) -1)
921 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
922 }
923 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
924
925 void ath9k_hw_deinit(struct ath_hw *ah)
926 {
927 struct ath_common *common = ath9k_hw_common(ah);
928
929 if (common->state < ATH_HW_INITIALIZED)
930 goto free_hw;
931
932 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
933
934 free_hw:
935 ath9k_hw_rf_free_ext_banks(ah);
936 }
937 EXPORT_SYMBOL(ath9k_hw_deinit);
938
939 /*******/
940 /* INI */
941 /*******/
942
943 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
944 {
945 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
946
947 if (IS_CHAN_B(chan))
948 ctl |= CTL_11B;
949 else if (IS_CHAN_G(chan))
950 ctl |= CTL_11G;
951 else
952 ctl |= CTL_11A;
953
954 return ctl;
955 }
956
957 /****************************************/
958 /* Reset and Channel Switching Routines */
959 /****************************************/
960
961 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
962 {
963 struct ath_common *common = ath9k_hw_common(ah);
964
965 ENABLE_REGWRITE_BUFFER(ah);
966
967 /*
968 * set AHB_MODE not to do cacheline prefetches
969 */
970 if (!AR_SREV_9300_20_OR_LATER(ah))
971 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
972
973 /*
974 * let mac dma reads be in 128 byte chunks
975 */
976 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
977
978 REGWRITE_BUFFER_FLUSH(ah);
979
980 /*
981 * Restore TX Trigger Level to its pre-reset value.
982 * The initial value depends on whether aggregation is enabled, and is
983 * adjusted whenever underruns are detected.
984 */
985 if (!AR_SREV_9300_20_OR_LATER(ah))
986 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
987
988 ENABLE_REGWRITE_BUFFER(ah);
989
990 /*
991 * let mac dma writes be in 128 byte chunks
992 */
993 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
994
995 /*
996 * Setup receive FIFO threshold to hold off TX activities
997 */
998 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
999
1000 if (AR_SREV_9300_20_OR_LATER(ah)) {
1001 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1002 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1003
1004 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1005 ah->caps.rx_status_len);
1006 }
1007
1008 /*
1009 * reduce the number of usable entries in PCU TXBUF to avoid
1010 * wrap around issues.
1011 */
1012 if (AR_SREV_9285(ah)) {
1013 /* For AR9285 the number of Fifos are reduced to half.
1014 * So set the usable tx buf size also to half to
1015 * avoid data/delimiter underruns
1016 */
1017 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1018 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1019 } else if (!AR_SREV_9271(ah)) {
1020 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1021 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1022 }
1023
1024 REGWRITE_BUFFER_FLUSH(ah);
1025
1026 if (AR_SREV_9300_20_OR_LATER(ah))
1027 ath9k_hw_reset_txstatus_ring(ah);
1028 }
1029
1030 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1031 {
1032 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1033 u32 set = AR_STA_ID1_KSRCH_MODE;
1034
1035 switch (opmode) {
1036 case NL80211_IFTYPE_ADHOC:
1037 case NL80211_IFTYPE_MESH_POINT:
1038 set |= AR_STA_ID1_ADHOC;
1039 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1040 break;
1041 case NL80211_IFTYPE_AP:
1042 set |= AR_STA_ID1_STA_AP;
1043 /* fall through */
1044 case NL80211_IFTYPE_STATION:
1045 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1046 break;
1047 default:
1048 if (!ah->is_monitoring)
1049 set = 0;
1050 break;
1051 }
1052 REG_RMW(ah, AR_STA_ID1, set, mask);
1053 }
1054
1055 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1056 u32 *coef_mantissa, u32 *coef_exponent)
1057 {
1058 u32 coef_exp, coef_man;
1059
1060 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1061 if ((coef_scaled >> coef_exp) & 0x1)
1062 break;
1063
1064 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1065
1066 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1067
1068 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1069 *coef_exponent = coef_exp - 16;
1070 }
1071
1072 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1073 {
1074 u32 rst_flags;
1075 u32 tmpReg;
1076
1077 if (AR_SREV_9100(ah)) {
1078 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1079 AR_RTC_DERIVED_CLK_PERIOD, 1);
1080 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1081 }
1082
1083 ENABLE_REGWRITE_BUFFER(ah);
1084
1085 if (AR_SREV_9300_20_OR_LATER(ah)) {
1086 REG_WRITE(ah, AR_WA, ah->WARegVal);
1087 udelay(10);
1088 }
1089
1090 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1091 AR_RTC_FORCE_WAKE_ON_INT);
1092
1093 if (AR_SREV_9100(ah)) {
1094 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1095 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1096 } else {
1097 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1098 if (tmpReg &
1099 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1100 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1101 u32 val;
1102 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1103
1104 val = AR_RC_HOSTIF;
1105 if (!AR_SREV_9300_20_OR_LATER(ah))
1106 val |= AR_RC_AHB;
1107 REG_WRITE(ah, AR_RC, val);
1108
1109 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1110 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1111
1112 rst_flags = AR_RTC_RC_MAC_WARM;
1113 if (type == ATH9K_RESET_COLD)
1114 rst_flags |= AR_RTC_RC_MAC_COLD;
1115 }
1116
1117 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1118
1119 REGWRITE_BUFFER_FLUSH(ah);
1120
1121 udelay(50);
1122
1123 REG_WRITE(ah, AR_RTC_RC, 0);
1124 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1126 "RTC stuck in MAC reset\n");
1127 return false;
1128 }
1129
1130 if (!AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_RC, 0);
1132
1133 if (AR_SREV_9100(ah))
1134 udelay(50);
1135
1136 return true;
1137 }
1138
1139 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1140 {
1141 ENABLE_REGWRITE_BUFFER(ah);
1142
1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_WRITE(ah, AR_WA, ah->WARegVal);
1145 udelay(10);
1146 }
1147
1148 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1149 AR_RTC_FORCE_WAKE_ON_INT);
1150
1151 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1152 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1153
1154 REG_WRITE(ah, AR_RTC_RESET, 0);
1155
1156 REGWRITE_BUFFER_FLUSH(ah);
1157
1158 if (!AR_SREV_9300_20_OR_LATER(ah))
1159 udelay(2);
1160
1161 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1162 REG_WRITE(ah, AR_RC, 0);
1163
1164 REG_WRITE(ah, AR_RTC_RESET, 1);
1165
1166 if (!ath9k_hw_wait(ah,
1167 AR_RTC_STATUS,
1168 AR_RTC_STATUS_M,
1169 AR_RTC_STATUS_ON,
1170 AH_WAIT_TIMEOUT)) {
1171 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1172 "RTC not waking up\n");
1173 return false;
1174 }
1175
1176 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1177 }
1178
1179 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1180 {
1181 if (AR_SREV_9300_20_OR_LATER(ah)) {
1182 REG_WRITE(ah, AR_WA, ah->WARegVal);
1183 udelay(10);
1184 }
1185
1186 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1187 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1188
1189 switch (type) {
1190 case ATH9K_RESET_POWER_ON:
1191 return ath9k_hw_set_reset_power_on(ah);
1192 case ATH9K_RESET_WARM:
1193 case ATH9K_RESET_COLD:
1194 return ath9k_hw_set_reset(ah, type);
1195 default:
1196 return false;
1197 }
1198 }
1199
1200 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1201 struct ath9k_channel *chan)
1202 {
1203 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1204 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1205 return false;
1206 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1207 return false;
1208
1209 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1210 return false;
1211
1212 ah->chip_fullsleep = false;
1213 ath9k_hw_init_pll(ah, chan);
1214 ath9k_hw_set_rfmode(ah, chan);
1215
1216 return true;
1217 }
1218
1219 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1220 struct ath9k_channel *chan)
1221 {
1222 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1223 struct ath_common *common = ath9k_hw_common(ah);
1224 struct ieee80211_channel *channel = chan->chan;
1225 u32 qnum;
1226 int r;
1227
1228 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1229 if (ath9k_hw_numtxpending(ah, qnum)) {
1230 ath_dbg(common, ATH_DBG_QUEUE,
1231 "Transmit frames pending on queue %d\n", qnum);
1232 return false;
1233 }
1234 }
1235
1236 if (!ath9k_hw_rfbus_req(ah)) {
1237 ath_err(common, "Could not kill baseband RX\n");
1238 return false;
1239 }
1240
1241 ath9k_hw_set_channel_regs(ah, chan);
1242
1243 r = ath9k_hw_rf_set_freq(ah, chan);
1244 if (r) {
1245 ath_err(common, "Failed to set channel\n");
1246 return false;
1247 }
1248 ath9k_hw_set_clockrate(ah);
1249
1250 ah->eep_ops->set_txpower(ah, chan,
1251 ath9k_regd_get_ctl(regulatory, chan),
1252 channel->max_antenna_gain * 2,
1253 channel->max_power * 2,
1254 min((u32) MAX_RATE_POWER,
1255 (u32) regulatory->power_limit), false);
1256
1257 ath9k_hw_rfbus_done(ah);
1258
1259 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1260 ath9k_hw_set_delta_slope(ah, chan);
1261
1262 ath9k_hw_spur_mitigate_freq(ah, chan);
1263
1264 return true;
1265 }
1266
1267 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1268 {
1269 u32 gpio_mask = ah->gpio_mask;
1270 int i;
1271
1272 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1273 if (!(gpio_mask & 1))
1274 continue;
1275
1276 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1277 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1278 }
1279 }
1280
1281 bool ath9k_hw_check_alive(struct ath_hw *ah)
1282 {
1283 int count = 50;
1284 u32 reg;
1285
1286 if (AR_SREV_9285_12_OR_LATER(ah))
1287 return true;
1288
1289 do {
1290 reg = REG_READ(ah, AR_OBS_BUS_1);
1291
1292 if ((reg & 0x7E7FFFEF) == 0x00702400)
1293 continue;
1294
1295 switch (reg & 0x7E000B00) {
1296 case 0x1E000000:
1297 case 0x52000B00:
1298 case 0x18000B00:
1299 continue;
1300 default:
1301 return true;
1302 }
1303 } while (count-- > 0);
1304
1305 return false;
1306 }
1307 EXPORT_SYMBOL(ath9k_hw_check_alive);
1308
1309 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1310 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1311 {
1312 struct ath_common *common = ath9k_hw_common(ah);
1313 u32 saveLedState;
1314 struct ath9k_channel *curchan = ah->curchan;
1315 u32 saveDefAntenna;
1316 u32 macStaId1;
1317 u64 tsf = 0;
1318 int i, r;
1319
1320 ah->txchainmask = common->tx_chainmask;
1321 ah->rxchainmask = common->rx_chainmask;
1322
1323 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1324 return -EIO;
1325
1326 if (curchan && !ah->chip_fullsleep)
1327 ath9k_hw_getnf(ah, curchan);
1328
1329 ah->caldata = caldata;
1330 if (caldata &&
1331 (chan->channel != caldata->channel ||
1332 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1333 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1334 /* Operating channel changed, reset channel calibration data */
1335 memset(caldata, 0, sizeof(*caldata));
1336 ath9k_init_nfcal_hist_buffer(ah, chan);
1337 }
1338
1339 if (bChannelChange &&
1340 (ah->chip_fullsleep != true) &&
1341 (ah->curchan != NULL) &&
1342 (chan->channel != ah->curchan->channel) &&
1343 ((chan->channelFlags & CHANNEL_ALL) ==
1344 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1345 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1346
1347 if (ath9k_hw_channel_change(ah, chan)) {
1348 ath9k_hw_loadnf(ah, ah->curchan);
1349 ath9k_hw_start_nfcal(ah, true);
1350 if (AR_SREV_9271(ah))
1351 ar9002_hw_load_ani_reg(ah, chan);
1352 return 0;
1353 }
1354 }
1355
1356 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1357 if (saveDefAntenna == 0)
1358 saveDefAntenna = 1;
1359
1360 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1361
1362 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1363 if (AR_SREV_9100(ah) ||
1364 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1365 tsf = ath9k_hw_gettsf64(ah);
1366
1367 saveLedState = REG_READ(ah, AR_CFG_LED) &
1368 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1369 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1370
1371 ath9k_hw_mark_phy_inactive(ah);
1372
1373 ah->paprd_table_write_done = false;
1374
1375 /* Only required on the first reset */
1376 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1377 REG_WRITE(ah,
1378 AR9271_RESET_POWER_DOWN_CONTROL,
1379 AR9271_RADIO_RF_RST);
1380 udelay(50);
1381 }
1382
1383 if (!ath9k_hw_chip_reset(ah, chan)) {
1384 ath_err(common, "Chip reset failed\n");
1385 return -EINVAL;
1386 }
1387
1388 /* Only required on the first reset */
1389 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1390 ah->htc_reset_init = false;
1391 REG_WRITE(ah,
1392 AR9271_RESET_POWER_DOWN_CONTROL,
1393 AR9271_GATE_MAC_CTL);
1394 udelay(50);
1395 }
1396
1397 /* Restore TSF */
1398 if (tsf)
1399 ath9k_hw_settsf64(ah, tsf);
1400
1401 if (AR_SREV_9280_20_OR_LATER(ah))
1402 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1403
1404 if (!AR_SREV_9300_20_OR_LATER(ah))
1405 ar9002_hw_enable_async_fifo(ah);
1406
1407 r = ath9k_hw_process_ini(ah, chan);
1408 if (r)
1409 return r;
1410
1411 /*
1412 * Some AR91xx SoC devices frequently fail to accept TSF writes
1413 * right after the chip reset. When that happens, write a new
1414 * value after the initvals have been applied, with an offset
1415 * based on measured time difference
1416 */
1417 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1418 tsf += 1500;
1419 ath9k_hw_settsf64(ah, tsf);
1420 }
1421
1422 /* Setup MFP options for CCMP */
1423 if (AR_SREV_9280_20_OR_LATER(ah)) {
1424 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1425 * frames when constructing CCMP AAD. */
1426 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1427 0xc7ff);
1428 ah->sw_mgmt_crypto = false;
1429 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1430 /* Disable hardware crypto for management frames */
1431 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1432 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1433 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1434 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1435 ah->sw_mgmt_crypto = true;
1436 } else
1437 ah->sw_mgmt_crypto = true;
1438
1439 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1440 ath9k_hw_set_delta_slope(ah, chan);
1441
1442 ath9k_hw_spur_mitigate_freq(ah, chan);
1443 ah->eep_ops->set_board_values(ah, chan);
1444
1445 ENABLE_REGWRITE_BUFFER(ah);
1446
1447 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1448 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1449 | macStaId1
1450 | AR_STA_ID1_RTS_USE_DEF
1451 | (ah->config.
1452 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1453 | ah->sta_id1_defaults);
1454 ath_hw_setbssidmask(common);
1455 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1456 ath9k_hw_write_associd(ah);
1457 REG_WRITE(ah, AR_ISR, ~0);
1458 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1459
1460 REGWRITE_BUFFER_FLUSH(ah);
1461
1462 ath9k_hw_set_operating_mode(ah, ah->opmode);
1463
1464 r = ath9k_hw_rf_set_freq(ah, chan);
1465 if (r)
1466 return r;
1467
1468 ath9k_hw_set_clockrate(ah);
1469
1470 ENABLE_REGWRITE_BUFFER(ah);
1471
1472 for (i = 0; i < AR_NUM_DCU; i++)
1473 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1474
1475 REGWRITE_BUFFER_FLUSH(ah);
1476
1477 ah->intr_txqs = 0;
1478 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1479 ath9k_hw_resettxqueue(ah, i);
1480
1481 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1482 ath9k_hw_ani_cache_ini_regs(ah);
1483 ath9k_hw_init_qos(ah);
1484
1485 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1486 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1487
1488 ath9k_hw_init_global_settings(ah);
1489
1490 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1491 ar9002_hw_update_async_fifo(ah);
1492 ar9002_hw_enable_wep_aggregation(ah);
1493 }
1494
1495 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1496
1497 ath9k_hw_set_dma(ah);
1498
1499 REG_WRITE(ah, AR_OBS, 8);
1500
1501 if (ah->config.rx_intr_mitigation) {
1502 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1503 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1504 }
1505
1506 if (ah->config.tx_intr_mitigation) {
1507 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1508 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1509 }
1510
1511 ath9k_hw_init_bb(ah, chan);
1512
1513 if (!ath9k_hw_init_cal(ah, chan))
1514 return -EIO;
1515
1516 ENABLE_REGWRITE_BUFFER(ah);
1517
1518 ath9k_hw_restore_chainmask(ah);
1519 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1520
1521 REGWRITE_BUFFER_FLUSH(ah);
1522
1523 /*
1524 * For big endian systems turn on swapping for descriptors
1525 */
1526 if (AR_SREV_9100(ah)) {
1527 u32 mask;
1528 mask = REG_READ(ah, AR_CFG);
1529 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1530 ath_dbg(common, ATH_DBG_RESET,
1531 "CFG Byte Swap Set 0x%x\n", mask);
1532 } else {
1533 mask =
1534 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1535 REG_WRITE(ah, AR_CFG, mask);
1536 ath_dbg(common, ATH_DBG_RESET,
1537 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1538 }
1539 } else {
1540 if (common->bus_ops->ath_bus_type == ATH_USB) {
1541 /* Configure AR9271 target WLAN */
1542 if (AR_SREV_9271(ah))
1543 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1544 else
1545 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1546 }
1547 #ifdef __BIG_ENDIAN
1548 else if (AR_SREV_9340(ah))
1549 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1550 else
1551 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1552 #endif
1553 }
1554
1555 if (ah->btcoex_hw.enabled)
1556 ath9k_hw_btcoex_enable(ah);
1557
1558 if (AR_SREV_9300_20_OR_LATER(ah)) {
1559 ar9003_hw_bb_watchdog_config(ah);
1560
1561 ar9003_hw_disable_phy_restart(ah);
1562 }
1563
1564 ath9k_hw_apply_gpio_override(ah);
1565
1566 return 0;
1567 }
1568 EXPORT_SYMBOL(ath9k_hw_reset);
1569
1570 /******************************/
1571 /* Power Management (Chipset) */
1572 /******************************/
1573
1574 /*
1575 * Notify Power Mgt is disabled in self-generated frames.
1576 * If requested, force chip to sleep.
1577 */
1578 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1579 {
1580 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1581 if (setChip) {
1582 /*
1583 * Clear the RTC force wake bit to allow the
1584 * mac to go to sleep.
1585 */
1586 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1587 AR_RTC_FORCE_WAKE_EN);
1588 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1589 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1590
1591 /* Shutdown chip. Active low */
1592 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1593 REG_CLR_BIT(ah, (AR_RTC_RESET),
1594 AR_RTC_RESET_EN);
1595 }
1596
1597 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1598 if (AR_SREV_9300_20_OR_LATER(ah))
1599 REG_WRITE(ah, AR_WA,
1600 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1601 }
1602
1603 /*
1604 * Notify Power Management is enabled in self-generating
1605 * frames. If request, set power mode of chip to
1606 * auto/normal. Duration in units of 128us (1/8 TU).
1607 */
1608 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1609 {
1610 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1611 if (setChip) {
1612 struct ath9k_hw_capabilities *pCap = &ah->caps;
1613
1614 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1615 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1616 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1617 AR_RTC_FORCE_WAKE_ON_INT);
1618 } else {
1619 /*
1620 * Clear the RTC force wake bit to allow the
1621 * mac to go to sleep.
1622 */
1623 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1624 AR_RTC_FORCE_WAKE_EN);
1625 }
1626 }
1627
1628 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1629 if (AR_SREV_9300_20_OR_LATER(ah))
1630 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1631 }
1632
1633 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1634 {
1635 u32 val;
1636 int i;
1637
1638 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1639 if (AR_SREV_9300_20_OR_LATER(ah)) {
1640 REG_WRITE(ah, AR_WA, ah->WARegVal);
1641 udelay(10);
1642 }
1643
1644 if (setChip) {
1645 if ((REG_READ(ah, AR_RTC_STATUS) &
1646 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1647 if (ath9k_hw_set_reset_reg(ah,
1648 ATH9K_RESET_POWER_ON) != true) {
1649 return false;
1650 }
1651 if (!AR_SREV_9300_20_OR_LATER(ah))
1652 ath9k_hw_init_pll(ah, NULL);
1653 }
1654 if (AR_SREV_9100(ah))
1655 REG_SET_BIT(ah, AR_RTC_RESET,
1656 AR_RTC_RESET_EN);
1657
1658 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1659 AR_RTC_FORCE_WAKE_EN);
1660 udelay(50);
1661
1662 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1663 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1664 if (val == AR_RTC_STATUS_ON)
1665 break;
1666 udelay(50);
1667 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1668 AR_RTC_FORCE_WAKE_EN);
1669 }
1670 if (i == 0) {
1671 ath_err(ath9k_hw_common(ah),
1672 "Failed to wakeup in %uus\n",
1673 POWER_UP_TIME / 20);
1674 return false;
1675 }
1676 }
1677
1678 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1679
1680 return true;
1681 }
1682
1683 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1684 {
1685 struct ath_common *common = ath9k_hw_common(ah);
1686 int status = true, setChip = true;
1687 static const char *modes[] = {
1688 "AWAKE",
1689 "FULL-SLEEP",
1690 "NETWORK SLEEP",
1691 "UNDEFINED"
1692 };
1693
1694 if (ah->power_mode == mode)
1695 return status;
1696
1697 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1698 modes[ah->power_mode], modes[mode]);
1699
1700 switch (mode) {
1701 case ATH9K_PM_AWAKE:
1702 status = ath9k_hw_set_power_awake(ah, setChip);
1703 break;
1704 case ATH9K_PM_FULL_SLEEP:
1705 ath9k_set_power_sleep(ah, setChip);
1706 ah->chip_fullsleep = true;
1707 break;
1708 case ATH9K_PM_NETWORK_SLEEP:
1709 ath9k_set_power_network_sleep(ah, setChip);
1710 break;
1711 default:
1712 ath_err(common, "Unknown power mode %u\n", mode);
1713 return false;
1714 }
1715 ah->power_mode = mode;
1716
1717 /*
1718 * XXX: If this warning never comes up after a while then
1719 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1720 * ath9k_hw_setpower() return type void.
1721 */
1722
1723 if (!(ah->ah_flags & AH_UNPLUGGED))
1724 ATH_DBG_WARN_ON_ONCE(!status);
1725
1726 return status;
1727 }
1728 EXPORT_SYMBOL(ath9k_hw_setpower);
1729
1730 /*******************/
1731 /* Beacon Handling */
1732 /*******************/
1733
1734 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1735 {
1736 int flags = 0;
1737
1738 ENABLE_REGWRITE_BUFFER(ah);
1739
1740 switch (ah->opmode) {
1741 case NL80211_IFTYPE_ADHOC:
1742 case NL80211_IFTYPE_MESH_POINT:
1743 REG_SET_BIT(ah, AR_TXCFG,
1744 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1745 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1746 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1747 flags |= AR_NDP_TIMER_EN;
1748 case NL80211_IFTYPE_AP:
1749 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1750 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1751 TU_TO_USEC(ah->config.dma_beacon_response_time));
1752 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1753 TU_TO_USEC(ah->config.sw_beacon_response_time));
1754 flags |=
1755 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1756 break;
1757 default:
1758 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1759 "%s: unsupported opmode: %d\n",
1760 __func__, ah->opmode);
1761 return;
1762 break;
1763 }
1764
1765 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1766 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1767 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1768 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1769
1770 REGWRITE_BUFFER_FLUSH(ah);
1771
1772 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1773 }
1774 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1775
1776 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1777 const struct ath9k_beacon_state *bs)
1778 {
1779 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1780 struct ath9k_hw_capabilities *pCap = &ah->caps;
1781 struct ath_common *common = ath9k_hw_common(ah);
1782
1783 ENABLE_REGWRITE_BUFFER(ah);
1784
1785 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1786
1787 REG_WRITE(ah, AR_BEACON_PERIOD,
1788 TU_TO_USEC(bs->bs_intval));
1789 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1790 TU_TO_USEC(bs->bs_intval));
1791
1792 REGWRITE_BUFFER_FLUSH(ah);
1793
1794 REG_RMW_FIELD(ah, AR_RSSI_THR,
1795 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1796
1797 beaconintval = bs->bs_intval;
1798
1799 if (bs->bs_sleepduration > beaconintval)
1800 beaconintval = bs->bs_sleepduration;
1801
1802 dtimperiod = bs->bs_dtimperiod;
1803 if (bs->bs_sleepduration > dtimperiod)
1804 dtimperiod = bs->bs_sleepduration;
1805
1806 if (beaconintval == dtimperiod)
1807 nextTbtt = bs->bs_nextdtim;
1808 else
1809 nextTbtt = bs->bs_nexttbtt;
1810
1811 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1812 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1813 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1814 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1815
1816 ENABLE_REGWRITE_BUFFER(ah);
1817
1818 REG_WRITE(ah, AR_NEXT_DTIM,
1819 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1820 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1821
1822 REG_WRITE(ah, AR_SLEEP1,
1823 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1824 | AR_SLEEP1_ASSUME_DTIM);
1825
1826 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1827 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1828 else
1829 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1830
1831 REG_WRITE(ah, AR_SLEEP2,
1832 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1833
1834 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1835 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1836
1837 REGWRITE_BUFFER_FLUSH(ah);
1838
1839 REG_SET_BIT(ah, AR_TIMER_MODE,
1840 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1841 AR_DTIM_TIMER_EN);
1842
1843 /* TSF Out of Range Threshold */
1844 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1845 }
1846 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1847
1848 /*******************/
1849 /* HW Capabilities */
1850 /*******************/
1851
1852 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1853 {
1854 struct ath9k_hw_capabilities *pCap = &ah->caps;
1855 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1856 struct ath_common *common = ath9k_hw_common(ah);
1857 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1858
1859 u16 eeval;
1860 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
1861
1862 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1863 regulatory->current_rd = eeval;
1864
1865 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1866 if (AR_SREV_9285_12_OR_LATER(ah))
1867 eeval |= AR9285_RDEXT_DEFAULT;
1868 regulatory->current_rd_ext = eeval;
1869
1870 if (ah->opmode != NL80211_IFTYPE_AP &&
1871 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1872 if (regulatory->current_rd == 0x64 ||
1873 regulatory->current_rd == 0x65)
1874 regulatory->current_rd += 5;
1875 else if (regulatory->current_rd == 0x41)
1876 regulatory->current_rd = 0x43;
1877 ath_dbg(common, ATH_DBG_REGULATORY,
1878 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1879 }
1880
1881 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1882 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1883 ath_err(common,
1884 "no band has been marked as supported in EEPROM\n");
1885 return -EINVAL;
1886 }
1887
1888 if (eeval & AR5416_OPFLAGS_11A)
1889 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1890
1891 if (eeval & AR5416_OPFLAGS_11G)
1892 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1893
1894 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1895 /*
1896 * For AR9271 we will temporarilly uses the rx chainmax as read from
1897 * the EEPROM.
1898 */
1899 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1900 !(eeval & AR5416_OPFLAGS_11A) &&
1901 !(AR_SREV_9271(ah)))
1902 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1903 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1904 else if (AR_SREV_9100(ah))
1905 pCap->rx_chainmask = 0x7;
1906 else
1907 /* Use rx_chainmask from EEPROM. */
1908 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1909
1910 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1911
1912 /* enable key search for every frame in an aggregate */
1913 if (AR_SREV_9300_20_OR_LATER(ah))
1914 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1915
1916 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1917
1918 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
1919 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1920 else
1921 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1922
1923 if (AR_SREV_9271(ah))
1924 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1925 else if (AR_DEVID_7010(ah))
1926 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1927 else if (AR_SREV_9285_12_OR_LATER(ah))
1928 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1929 else if (AR_SREV_9280_20_OR_LATER(ah))
1930 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1931 else
1932 pCap->num_gpio_pins = AR_NUM_GPIO;
1933
1934 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1935 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1936 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1937 } else {
1938 pCap->rts_aggr_limit = (8 * 1024);
1939 }
1940
1941 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1942 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1943 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1944 ah->rfkill_gpio =
1945 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1946 ah->rfkill_polarity =
1947 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1948
1949 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1950 }
1951 #endif
1952 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1953 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1954 else
1955 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1956
1957 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1958 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1959 else
1960 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1961
1962 if (common->btcoex_enabled) {
1963 if (AR_SREV_9300_20_OR_LATER(ah)) {
1964 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1965 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
1966 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
1967 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
1968 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1969 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
1970 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
1971
1972 if (AR_SREV_9285(ah)) {
1973 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1974 btcoex_hw->btpriority_gpio =
1975 ATH_BTPRIORITY_GPIO_9285;
1976 } else {
1977 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1978 }
1979 }
1980 } else {
1981 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1982 }
1983
1984 if (AR_SREV_9300_20_OR_LATER(ah)) {
1985 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1986 if (!AR_SREV_9485(ah))
1987 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1988
1989 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1990 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1991 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1992 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1993 pCap->txs_len = sizeof(struct ar9003_txs);
1994 if (!ah->config.paprd_disable &&
1995 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1996 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1997 } else {
1998 pCap->tx_desc_len = sizeof(struct ath_desc);
1999 if (AR_SREV_9280_20(ah) &&
2000 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2001 AR5416_EEP_MINOR_VER_16) ||
2002 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2003 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2004 }
2005
2006 if (AR_SREV_9300_20_OR_LATER(ah))
2007 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2008
2009 if (AR_SREV_9300_20_OR_LATER(ah))
2010 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2011
2012 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2013 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2014
2015 if (AR_SREV_9285(ah))
2016 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2017 ant_div_ctl1 =
2018 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2019 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2020 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2021 }
2022 if (AR_SREV_9300_20_OR_LATER(ah)) {
2023 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2024 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2025 }
2026
2027
2028 if (AR_SREV_9485(ah)) {
2029 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2030 /*
2031 * enable the diversity-combining algorithm only when
2032 * both enable_lna_div and enable_fast_div are set
2033 * Table for Diversity
2034 * ant_div_alt_lnaconf bit 0-1
2035 * ant_div_main_lnaconf bit 2-3
2036 * ant_div_alt_gaintb bit 4
2037 * ant_div_main_gaintb bit 5
2038 * enable_ant_div_lnadiv bit 6
2039 * enable_ant_fast_div bit 7
2040 */
2041 if ((ant_div_ctl1 >> 0x6) == 0x3)
2042 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2043 }
2044
2045 if (AR_SREV_9485_10(ah)) {
2046 pCap->pcie_lcr_extsync_en = true;
2047 pCap->pcie_lcr_offset = 0x80;
2048 }
2049
2050 tx_chainmask = pCap->tx_chainmask;
2051 rx_chainmask = pCap->rx_chainmask;
2052 while (tx_chainmask || rx_chainmask) {
2053 if (tx_chainmask & BIT(0))
2054 pCap->max_txchains++;
2055 if (rx_chainmask & BIT(0))
2056 pCap->max_rxchains++;
2057
2058 tx_chainmask >>= 1;
2059 rx_chainmask >>= 1;
2060 }
2061
2062 return 0;
2063 }
2064
2065 /****************************/
2066 /* GPIO / RFKILL / Antennae */
2067 /****************************/
2068
2069 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2070 u32 gpio, u32 type)
2071 {
2072 int addr;
2073 u32 gpio_shift, tmp;
2074
2075 if (gpio > 11)
2076 addr = AR_GPIO_OUTPUT_MUX3;
2077 else if (gpio > 5)
2078 addr = AR_GPIO_OUTPUT_MUX2;
2079 else
2080 addr = AR_GPIO_OUTPUT_MUX1;
2081
2082 gpio_shift = (gpio % 6) * 5;
2083
2084 if (AR_SREV_9280_20_OR_LATER(ah)
2085 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2086 REG_RMW(ah, addr, (type << gpio_shift),
2087 (0x1f << gpio_shift));
2088 } else {
2089 tmp = REG_READ(ah, addr);
2090 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2091 tmp &= ~(0x1f << gpio_shift);
2092 tmp |= (type << gpio_shift);
2093 REG_WRITE(ah, addr, tmp);
2094 }
2095 }
2096
2097 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2098 {
2099 u32 gpio_shift;
2100
2101 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2102
2103 if (AR_DEVID_7010(ah)) {
2104 gpio_shift = gpio;
2105 REG_RMW(ah, AR7010_GPIO_OE,
2106 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2107 (AR7010_GPIO_OE_MASK << gpio_shift));
2108 return;
2109 }
2110
2111 gpio_shift = gpio << 1;
2112 REG_RMW(ah,
2113 AR_GPIO_OE_OUT,
2114 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2115 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2116 }
2117 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2118
2119 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2120 {
2121 #define MS_REG_READ(x, y) \
2122 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2123
2124 if (gpio >= ah->caps.num_gpio_pins)
2125 return 0xffffffff;
2126
2127 if (AR_DEVID_7010(ah)) {
2128 u32 val;
2129 val = REG_READ(ah, AR7010_GPIO_IN);
2130 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2131 } else if (AR_SREV_9300_20_OR_LATER(ah))
2132 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2133 AR_GPIO_BIT(gpio)) != 0;
2134 else if (AR_SREV_9271(ah))
2135 return MS_REG_READ(AR9271, gpio) != 0;
2136 else if (AR_SREV_9287_11_OR_LATER(ah))
2137 return MS_REG_READ(AR9287, gpio) != 0;
2138 else if (AR_SREV_9285_12_OR_LATER(ah))
2139 return MS_REG_READ(AR9285, gpio) != 0;
2140 else if (AR_SREV_9280_20_OR_LATER(ah))
2141 return MS_REG_READ(AR928X, gpio) != 0;
2142 else
2143 return MS_REG_READ(AR, gpio) != 0;
2144 }
2145 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2146
2147 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2148 u32 ah_signal_type)
2149 {
2150 u32 gpio_shift;
2151
2152 if (AR_DEVID_7010(ah)) {
2153 gpio_shift = gpio;
2154 REG_RMW(ah, AR7010_GPIO_OE,
2155 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2156 (AR7010_GPIO_OE_MASK << gpio_shift));
2157 return;
2158 }
2159
2160 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2161 gpio_shift = 2 * gpio;
2162 REG_RMW(ah,
2163 AR_GPIO_OE_OUT,
2164 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2165 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2166 }
2167 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2168
2169 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2170 {
2171 if (AR_DEVID_7010(ah)) {
2172 val = val ? 0 : 1;
2173 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2174 AR_GPIO_BIT(gpio));
2175 return;
2176 }
2177
2178 if (AR_SREV_9271(ah))
2179 val = ~val;
2180
2181 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2182 AR_GPIO_BIT(gpio));
2183 }
2184 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2185
2186 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2187 {
2188 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2189 }
2190 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2191
2192 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2193 {
2194 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2195 }
2196 EXPORT_SYMBOL(ath9k_hw_setantenna);
2197
2198 /*********************/
2199 /* General Operation */
2200 /*********************/
2201
2202 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2203 {
2204 u32 bits = REG_READ(ah, AR_RX_FILTER);
2205 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2206
2207 if (phybits & AR_PHY_ERR_RADAR)
2208 bits |= ATH9K_RX_FILTER_PHYRADAR;
2209 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2210 bits |= ATH9K_RX_FILTER_PHYERR;
2211
2212 return bits;
2213 }
2214 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2215
2216 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2217 {
2218 u32 phybits;
2219
2220 ENABLE_REGWRITE_BUFFER(ah);
2221
2222 REG_WRITE(ah, AR_RX_FILTER, bits);
2223
2224 phybits = 0;
2225 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2226 phybits |= AR_PHY_ERR_RADAR;
2227 if (bits & ATH9K_RX_FILTER_PHYERR)
2228 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2229 REG_WRITE(ah, AR_PHY_ERR, phybits);
2230
2231 if (phybits)
2232 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2233 else
2234 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2235
2236 REGWRITE_BUFFER_FLUSH(ah);
2237 }
2238 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2239
2240 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2241 {
2242 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2243 return false;
2244
2245 ath9k_hw_init_pll(ah, NULL);
2246 return true;
2247 }
2248 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2249
2250 bool ath9k_hw_disable(struct ath_hw *ah)
2251 {
2252 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2253 return false;
2254
2255 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2256 return false;
2257
2258 ath9k_hw_init_pll(ah, NULL);
2259 return true;
2260 }
2261 EXPORT_SYMBOL(ath9k_hw_disable);
2262
2263 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2264 {
2265 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2266 struct ath9k_channel *chan = ah->curchan;
2267 struct ieee80211_channel *channel = chan->chan;
2268
2269 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2270
2271 ah->eep_ops->set_txpower(ah, chan,
2272 ath9k_regd_get_ctl(regulatory, chan),
2273 channel->max_antenna_gain * 2,
2274 channel->max_power * 2,
2275 min((u32) MAX_RATE_POWER,
2276 (u32) regulatory->power_limit), test);
2277 }
2278 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2279
2280 void ath9k_hw_setopmode(struct ath_hw *ah)
2281 {
2282 ath9k_hw_set_operating_mode(ah, ah->opmode);
2283 }
2284 EXPORT_SYMBOL(ath9k_hw_setopmode);
2285
2286 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2287 {
2288 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2289 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2290 }
2291 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2292
2293 void ath9k_hw_write_associd(struct ath_hw *ah)
2294 {
2295 struct ath_common *common = ath9k_hw_common(ah);
2296
2297 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2298 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2299 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2300 }
2301 EXPORT_SYMBOL(ath9k_hw_write_associd);
2302
2303 #define ATH9K_MAX_TSF_READ 10
2304
2305 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2306 {
2307 u32 tsf_lower, tsf_upper1, tsf_upper2;
2308 int i;
2309
2310 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2311 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2312 tsf_lower = REG_READ(ah, AR_TSF_L32);
2313 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2314 if (tsf_upper2 == tsf_upper1)
2315 break;
2316 tsf_upper1 = tsf_upper2;
2317 }
2318
2319 WARN_ON( i == ATH9K_MAX_TSF_READ );
2320
2321 return (((u64)tsf_upper1 << 32) | tsf_lower);
2322 }
2323 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2324
2325 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2326 {
2327 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2328 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2329 }
2330 EXPORT_SYMBOL(ath9k_hw_settsf64);
2331
2332 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2333 {
2334 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2335 AH_TSF_WRITE_TIMEOUT))
2336 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2337 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2338
2339 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2340 }
2341 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2342
2343 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2344 {
2345 if (setting)
2346 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2347 else
2348 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2349 }
2350 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2351
2352 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2353 {
2354 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2355 u32 macmode;
2356
2357 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2358 macmode = AR_2040_JOINED_RX_CLEAR;
2359 else
2360 macmode = 0;
2361
2362 REG_WRITE(ah, AR_2040_MODE, macmode);
2363 }
2364
2365 /* HW Generic timers configuration */
2366
2367 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2368 {
2369 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2370 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2371 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2372 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2373 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2374 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2375 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2376 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2377 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2378 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2379 AR_NDP2_TIMER_MODE, 0x0002},
2380 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2381 AR_NDP2_TIMER_MODE, 0x0004},
2382 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2383 AR_NDP2_TIMER_MODE, 0x0008},
2384 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2385 AR_NDP2_TIMER_MODE, 0x0010},
2386 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2387 AR_NDP2_TIMER_MODE, 0x0020},
2388 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2389 AR_NDP2_TIMER_MODE, 0x0040},
2390 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2391 AR_NDP2_TIMER_MODE, 0x0080}
2392 };
2393
2394 /* HW generic timer primitives */
2395
2396 /* compute and clear index of rightmost 1 */
2397 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2398 {
2399 u32 b;
2400
2401 b = *mask;
2402 b &= (0-b);
2403 *mask &= ~b;
2404 b *= debruijn32;
2405 b >>= 27;
2406
2407 return timer_table->gen_timer_index[b];
2408 }
2409
2410 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2411 {
2412 return REG_READ(ah, AR_TSF_L32);
2413 }
2414 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2415
2416 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2417 void (*trigger)(void *),
2418 void (*overflow)(void *),
2419 void *arg,
2420 u8 timer_index)
2421 {
2422 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2423 struct ath_gen_timer *timer;
2424
2425 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2426
2427 if (timer == NULL) {
2428 ath_err(ath9k_hw_common(ah),
2429 "Failed to allocate memory for hw timer[%d]\n",
2430 timer_index);
2431 return NULL;
2432 }
2433
2434 /* allocate a hardware generic timer slot */
2435 timer_table->timers[timer_index] = timer;
2436 timer->index = timer_index;
2437 timer->trigger = trigger;
2438 timer->overflow = overflow;
2439 timer->arg = arg;
2440
2441 return timer;
2442 }
2443 EXPORT_SYMBOL(ath_gen_timer_alloc);
2444
2445 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2446 struct ath_gen_timer *timer,
2447 u32 trig_timeout,
2448 u32 timer_period)
2449 {
2450 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2451 u32 tsf, timer_next;
2452
2453 BUG_ON(!timer_period);
2454
2455 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2456
2457 tsf = ath9k_hw_gettsf32(ah);
2458
2459 timer_next = tsf + trig_timeout;
2460
2461 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2462 "current tsf %x period %x timer_next %x\n",
2463 tsf, timer_period, timer_next);
2464
2465 /*
2466 * Program generic timer registers
2467 */
2468 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2469 timer_next);
2470 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2471 timer_period);
2472 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2473 gen_tmr_configuration[timer->index].mode_mask);
2474
2475 /* Enable both trigger and thresh interrupt masks */
2476 REG_SET_BIT(ah, AR_IMR_S5,
2477 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2478 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2479 }
2480 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2481
2482 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2483 {
2484 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2485
2486 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2487 (timer->index >= ATH_MAX_GEN_TIMER)) {
2488 return;
2489 }
2490
2491 /* Clear generic timer enable bits. */
2492 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2493 gen_tmr_configuration[timer->index].mode_mask);
2494
2495 /* Disable both trigger and thresh interrupt masks */
2496 REG_CLR_BIT(ah, AR_IMR_S5,
2497 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2498 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2499
2500 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2501 }
2502 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2503
2504 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2505 {
2506 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2507
2508 /* free the hardware generic timer slot */
2509 timer_table->timers[timer->index] = NULL;
2510 kfree(timer);
2511 }
2512 EXPORT_SYMBOL(ath_gen_timer_free);
2513
2514 /*
2515 * Generic Timer Interrupts handling
2516 */
2517 void ath_gen_timer_isr(struct ath_hw *ah)
2518 {
2519 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2520 struct ath_gen_timer *timer;
2521 struct ath_common *common = ath9k_hw_common(ah);
2522 u32 trigger_mask, thresh_mask, index;
2523
2524 /* get hardware generic timer interrupt status */
2525 trigger_mask = ah->intr_gen_timer_trigger;
2526 thresh_mask = ah->intr_gen_timer_thresh;
2527 trigger_mask &= timer_table->timer_mask.val;
2528 thresh_mask &= timer_table->timer_mask.val;
2529
2530 trigger_mask &= ~thresh_mask;
2531
2532 while (thresh_mask) {
2533 index = rightmost_index(timer_table, &thresh_mask);
2534 timer = timer_table->timers[index];
2535 BUG_ON(!timer);
2536 ath_dbg(common, ATH_DBG_HWTIMER,
2537 "TSF overflow for Gen timer %d\n", index);
2538 timer->overflow(timer->arg);
2539 }
2540
2541 while (trigger_mask) {
2542 index = rightmost_index(timer_table, &trigger_mask);
2543 timer = timer_table->timers[index];
2544 BUG_ON(!timer);
2545 ath_dbg(common, ATH_DBG_HWTIMER,
2546 "Gen timer[%d] trigger\n", index);
2547 timer->trigger(timer->arg);
2548 }
2549 }
2550 EXPORT_SYMBOL(ath_gen_timer_isr);
2551
2552 /********/
2553 /* HTC */
2554 /********/
2555
2556 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2557 {
2558 ah->htc_reset_init = true;
2559 }
2560 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2561
2562 static struct {
2563 u32 version;
2564 const char * name;
2565 } ath_mac_bb_names[] = {
2566 /* Devices with external radios */
2567 { AR_SREV_VERSION_5416_PCI, "5416" },
2568 { AR_SREV_VERSION_5416_PCIE, "5418" },
2569 { AR_SREV_VERSION_9100, "9100" },
2570 { AR_SREV_VERSION_9160, "9160" },
2571 /* Single-chip solutions */
2572 { AR_SREV_VERSION_9280, "9280" },
2573 { AR_SREV_VERSION_9285, "9285" },
2574 { AR_SREV_VERSION_9287, "9287" },
2575 { AR_SREV_VERSION_9271, "9271" },
2576 { AR_SREV_VERSION_9300, "9300" },
2577 { AR_SREV_VERSION_9485, "9485" },
2578 };
2579
2580 /* For devices with external radios */
2581 static struct {
2582 u16 version;
2583 const char * name;
2584 } ath_rf_names[] = {
2585 { 0, "5133" },
2586 { AR_RAD5133_SREV_MAJOR, "5133" },
2587 { AR_RAD5122_SREV_MAJOR, "5122" },
2588 { AR_RAD2133_SREV_MAJOR, "2133" },
2589 { AR_RAD2122_SREV_MAJOR, "2122" }
2590 };
2591
2592 /*
2593 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2594 */
2595 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2596 {
2597 int i;
2598
2599 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2600 if (ath_mac_bb_names[i].version == mac_bb_version) {
2601 return ath_mac_bb_names[i].name;
2602 }
2603 }
2604
2605 return "????";
2606 }
2607
2608 /*
2609 * Return the RF name. "????" is returned if the RF is unknown.
2610 * Used for devices with external radios.
2611 */
2612 static const char *ath9k_hw_rf_name(u16 rf_version)
2613 {
2614 int i;
2615
2616 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2617 if (ath_rf_names[i].version == rf_version) {
2618 return ath_rf_names[i].name;
2619 }
2620 }
2621
2622 return "????";
2623 }
2624
2625 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2626 {
2627 int used;
2628
2629 /* chipsets >= AR9280 are single-chip */
2630 if (AR_SREV_9280_20_OR_LATER(ah)) {
2631 used = snprintf(hw_name, len,
2632 "Atheros AR%s Rev:%x",
2633 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2634 ah->hw_version.macRev);
2635 }
2636 else {
2637 used = snprintf(hw_name, len,
2638 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2639 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2640 ah->hw_version.macRev,
2641 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2642 AR_RADIO_SREV_MAJOR)),
2643 ah->hw_version.phyRev);
2644 }
2645
2646 hw_name[used] = '\0';
2647 }
2648 EXPORT_SYMBOL(ath9k_hw_name);
kernel source for telekom puls (alcatel/mediatek)