drivers/net/wireless/ath/ath9k/hw-ops.h

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_HW_OPS_H
  18 #define ATH9K_HW_OPS_H
  19
  20 #include "hw.h"
  21
  22 /* Hardware core and driver accessible callbacks */
  23
  24 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
  25                                                bool power_off)
  26 {
  27         if (ah->aspm_enabled != true)
  28                 return;
  29
  30         ath9k_hw_ops(ah)->config_pci_powersave(ah, power_off);
  31 }
  32
  33 static inline void ath9k_hw_rxena(struct ath_hw *ah)
  34 {
  35         ath9k_hw_ops(ah)->rx_enable(ah);
  36 }
  37
  38 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
  39                                           u32 link)
  40 {
  41         ath9k_hw_ops(ah)->set_desc_link(ds, link);
  42 }
  43
  44 static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
  45                                       struct ath9k_channel *chan,
  46                                       u8 rxchainmask,
  47                                       bool longcal)
  48 {
  49         return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
  50 }
  51
  52 static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
  53 {
  54         return ath9k_hw_ops(ah)->get_isr(ah, masked);
  55 }
  56
  57 static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
  58                                   bool is_firstseg, bool is_lastseg,
  59                                   const void *ds0, dma_addr_t buf_addr,
  60                                   unsigned int qcu)
  61 {
  62         ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
  63                                       ds0, buf_addr, qcu);
  64 }
  65
  66 static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
  67                                       struct ath_tx_status *ts)
  68 {
  69         return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
  70 }
  71
  72 static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
  73                                           u32 pktLen, enum ath9k_pkt_type type,
  74                                           u32 txPower, u32 keyIx,
  75                                           enum ath9k_key_type keyType,
  76                                           u32 flags)
  77 {
  78         ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
  79                                       keyType, flags);
  80 }
  81
  82 static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
  83                                         void *lastds,
  84                                         u32 durUpdateEn, u32 rtsctsRate,
  85                                         u32 rtsctsDuration,
  86                                         struct ath9k_11n_rate_series series[],
  87                                         u32 nseries, u32 flags)
  88 {
  89         ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
  90                                             rtsctsRate, rtsctsDuration, series,
  91                                             nseries, flags);
  92 }
  93
  94 static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
  95                                         u32 aggrLen)
  96 {
  97         ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
  98 }
  99
 100 static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
 101                                                u32 numDelims)
 102 {
 103         ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
 104 }
 105
 106 static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
 107 {
 108         ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
 109 }
 110
 111 static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
 112 {
 113         ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
 114 }
 115
 116 static inline void ath9k_hw_set_clrdmask(struct ath_hw *ah, void *ds, bool val)
 117 {
 118         ath9k_hw_ops(ah)->set_clrdmask(ah, ds, val);
 119 }
 120
 121 static inline void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
 122                 struct ath_hw_antcomb_conf *antconf)
 123 {
 124         ath9k_hw_ops(ah)->antdiv_comb_conf_get(ah, antconf);
 125 }
 126
 127 static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
 128                 struct ath_hw_antcomb_conf *antconf)
 129 {
 130         ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);
 131 }
 132
 133 /* Private hardware call ops */
 134
 135 /* PHY ops */
 136
 137 static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
 138                                        struct ath9k_channel *chan)
 139 {
 140         return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
 141 }
 142
 143 static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
 144                                                struct ath9k_channel *chan)
 145 {
 146         ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
 147 }
 148
 149 static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 150 {
 151         if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
 152                 return 0;
 153
 154         return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
 155 }
 156
 157 static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
 158 {
 159         if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
 160                 return;
 161
 162         ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
 163 }
 164
 165 static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
 166                                         struct ath9k_channel *chan,
 167                                         u16 modesIndex)
 168 {
 169         if (!ath9k_hw_private_ops(ah)->set_rf_regs)
 170                 return true;
 171
 172         return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
 173 }
 174
 175 static inline void ath9k_hw_init_bb(struct ath_hw *ah,
 176                                     struct ath9k_channel *chan)
 177 {
 178         return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
 179 }
 180
 181 static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
 182                                              struct ath9k_channel *chan)
 183 {
 184         return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
 185 }
 186
 187 static inline int ath9k_hw_process_ini(struct ath_hw *ah,
 188                                         struct ath9k_channel *chan)
 189 {
 190         return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
 191 }
 192
 193 static inline void ath9k_olc_init(struct ath_hw *ah)
 194 {
 195         if (!ath9k_hw_private_ops(ah)->olc_init)
 196                 return;
 197
 198         return ath9k_hw_private_ops(ah)->olc_init(ah);
 199 }
 200
 201 static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
 202                                        struct ath9k_channel *chan)
 203 {
 204         return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
 205 }
 206
 207 static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
 208 {
 209         return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
 210 }
 211
 212 static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
 213                                             struct ath9k_channel *chan)
 214 {
 215         return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
 216 }
 217
 218 static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
 219 {
 220         return ath9k_hw_private_ops(ah)->rfbus_req(ah);
 221 }
 222
 223 static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
 224 {
 225         return ath9k_hw_private_ops(ah)->rfbus_done(ah);
 226 }
 227
 228 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
 229 {
 230         if (!ath9k_hw_private_ops(ah)->restore_chainmask)
 231                 return;
 232
 233         return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
 234 }
 235
 236 static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
 237 {
 238         return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
 239 }
 240
 241 static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
 242                                         enum ath9k_ani_cmd cmd, int param)
 243 {
 244         return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
 245 }
 246
 247 static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
 248                                      int16_t nfarray[NUM_NF_READINGS])
 249 {
 250         ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
 251 }
 252
 253 static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
 254                                      struct ath9k_channel *chan)
 255 {
 256         return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
 257 }
 258
 259 static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
 260                                               struct ath9k_cal_list *currCal)
 261 {
 262         ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
 263 }
 264
 265 #endif /* ATH9K_HW_OPS_H */