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eb9ac5ea61802cc330adbb9117eadcf28a226be6
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath9k / eeprom.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18
19 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
20 {
21 REG_WRITE(ah, reg, val);
22
23 if (ah->config.analog_shiftreg)
24 udelay(100);
25 }
26
27 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
28 u32 shift, u32 val)
29 {
30 u32 regVal;
31
32 regVal = REG_READ(ah, reg) & ~mask;
33 regVal |= (val << shift) & mask;
34
35 REG_WRITE(ah, reg, regVal);
36
37 if (ah->config.analog_shiftreg)
38 udelay(100);
39 }
40
41 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
42 int16_t targetLeft, int16_t targetRight)
43 {
44 int16_t rv;
45
46 if (srcRight == srcLeft) {
47 rv = targetLeft;
48 } else {
49 rv = (int16_t) (((target - srcLeft) * targetRight +
50 (srcRight - target) * targetLeft) /
51 (srcRight - srcLeft));
52 }
53 return rv;
54 }
55
56 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
57 u16 *indexL, u16 *indexR)
58 {
59 u16 i;
60
61 if (target <= pList[0]) {
62 *indexL = *indexR = 0;
63 return true;
64 }
65 if (target >= pList[listSize - 1]) {
66 *indexL = *indexR = (u16) (listSize - 1);
67 return true;
68 }
69
70 for (i = 0; i < listSize - 1; i++) {
71 if (pList[i] == target) {
72 *indexL = *indexR = i;
73 return true;
74 }
75 if (target < pList[i + 1]) {
76 *indexL = i;
77 *indexR = (u16) (i + 1);
78 return false;
79 }
80 }
81 return false;
82 }
83
84 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
85 int eep_start_loc, int size)
86 {
87 int i = 0, j, addr;
88 u32 addrdata[8];
89 u32 data[8];
90
91 for (addr = 0; addr < size; addr++) {
92 addrdata[i] = AR5416_EEPROM_OFFSET +
93 ((addr + eep_start_loc) << AR5416_EEPROM_S);
94 i++;
95 if (i == 8) {
96 REG_READ_MULTI(ah, addrdata, data, i);
97
98 for (j = 0; j < i; j++) {
99 *eep_data = data[j];
100 eep_data++;
101 }
102 i = 0;
103 }
104 }
105
106 if (i != 0) {
107 REG_READ_MULTI(ah, addrdata, data, i);
108
109 for (j = 0; j < i; j++) {
110 *eep_data = data[j];
111 eep_data++;
112 }
113 }
114 }
115
116 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
117 {
118 struct ath_common *common = ath9k_hw_common(ah);
119 bool ret;
120
121 ret = common->bus_ops->eeprom_read(common, off, data);
122 if (!ret)
123 ath_dbg(common, EEPROM,
124 "unable to read eeprom region at offset %u\n", off);
125
126 return ret;
127 }
128
129 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
130 u8 *pVpdList, u16 numIntercepts,
131 u8 *pRetVpdList)
132 {
133 u16 i, k;
134 u8 currPwr = pwrMin;
135 u16 idxL = 0, idxR = 0;
136
137 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
138 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
139 numIntercepts, &(idxL),
140 &(idxR));
141 if (idxR < 1)
142 idxR = 1;
143 if (idxL == numIntercepts - 1)
144 idxL = (u16) (numIntercepts - 2);
145 if (pPwrList[idxL] == pPwrList[idxR])
146 k = pVpdList[idxL];
147 else
148 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
149 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
150 (pPwrList[idxR] - pPwrList[idxL]));
151 pRetVpdList[i] = (u8) k;
152 currPwr += 2;
153 }
154 }
155
156 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
157 struct ath9k_channel *chan,
158 struct cal_target_power_leg *powInfo,
159 u16 numChannels,
160 struct cal_target_power_leg *pNewPower,
161 u16 numRates, bool isExtTarget)
162 {
163 struct chan_centers centers;
164 u16 clo, chi;
165 int i;
166 int matchIndex = -1, lowIndex = -1;
167 u16 freq;
168
169 ath9k_hw_get_channel_centers(ah, chan, &centers);
170 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
171
172 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
173 IS_CHAN_2GHZ(chan))) {
174 matchIndex = 0;
175 } else {
176 for (i = 0; (i < numChannels) &&
177 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
178 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
179 IS_CHAN_2GHZ(chan))) {
180 matchIndex = i;
181 break;
182 } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
183 IS_CHAN_2GHZ(chan)) && i > 0 &&
184 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
185 IS_CHAN_2GHZ(chan))) {
186 lowIndex = i - 1;
187 break;
188 }
189 }
190 if ((matchIndex == -1) && (lowIndex == -1))
191 matchIndex = i - 1;
192 }
193
194 if (matchIndex != -1) {
195 *pNewPower = powInfo[matchIndex];
196 } else {
197 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
198 IS_CHAN_2GHZ(chan));
199 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
200 IS_CHAN_2GHZ(chan));
201
202 for (i = 0; i < numRates; i++) {
203 pNewPower->tPow2x[i] =
204 (u8)ath9k_hw_interpolate(freq, clo, chi,
205 powInfo[lowIndex].tPow2x[i],
206 powInfo[lowIndex + 1].tPow2x[i]);
207 }
208 }
209 }
210
211 void ath9k_hw_get_target_powers(struct ath_hw *ah,
212 struct ath9k_channel *chan,
213 struct cal_target_power_ht *powInfo,
214 u16 numChannels,
215 struct cal_target_power_ht *pNewPower,
216 u16 numRates, bool isHt40Target)
217 {
218 struct chan_centers centers;
219 u16 clo, chi;
220 int i;
221 int matchIndex = -1, lowIndex = -1;
222 u16 freq;
223
224 ath9k_hw_get_channel_centers(ah, chan, &centers);
225 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
226
227 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
228 matchIndex = 0;
229 } else {
230 for (i = 0; (i < numChannels) &&
231 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
232 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
233 IS_CHAN_2GHZ(chan))) {
234 matchIndex = i;
235 break;
236 } else
237 if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
238 IS_CHAN_2GHZ(chan)) && i > 0 &&
239 freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
240 IS_CHAN_2GHZ(chan))) {
241 lowIndex = i - 1;
242 break;
243 }
244 }
245 if ((matchIndex == -1) && (lowIndex == -1))
246 matchIndex = i - 1;
247 }
248
249 if (matchIndex != -1) {
250 *pNewPower = powInfo[matchIndex];
251 } else {
252 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
253 IS_CHAN_2GHZ(chan));
254 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
255 IS_CHAN_2GHZ(chan));
256
257 for (i = 0; i < numRates; i++) {
258 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
259 clo, chi,
260 powInfo[lowIndex].tPow2x[i],
261 powInfo[lowIndex + 1].tPow2x[i]);
262 }
263 }
264 }
265
266 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
267 bool is2GHz, int num_band_edges)
268 {
269 u16 twiceMaxEdgePower = MAX_RATE_POWER;
270 int i;
271
272 for (i = 0; (i < num_band_edges) &&
273 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
274 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
275 twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
276 break;
277 } else if ((i > 0) &&
278 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
279 is2GHz))) {
280 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
281 is2GHz) < freq &&
282 CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
283 twiceMaxEdgePower =
284 CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
285 }
286 break;
287 }
288 }
289
290 return twiceMaxEdgePower;
291 }
292
293 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
294 u8 antenna_reduction)
295 {
296 u16 reduction = antenna_reduction;
297
298 /*
299 * Reduce scaled Power by number of chains active
300 * to get the per chain tx power level.
301 */
302 switch (ar5416_get_ntxchains(ah->txchainmask)) {
303 case 1:
304 break;
305 case 2:
306 reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
307 break;
308 case 3:
309 reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
310 break;
311 }
312
313 if (power_limit > reduction)
314 power_limit -= reduction;
315 else
316 power_limit = 0;
317
318 return power_limit;
319 }
320
321 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
322 {
323 struct ath_common *common = ath9k_hw_common(ah);
324 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
325
326 switch (ar5416_get_ntxchains(ah->txchainmask)) {
327 case 1:
328 break;
329 case 2:
330 regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
331 break;
332 case 3:
333 regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
334 break;
335 default:
336 ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
337 break;
338 }
339 }
340
341 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
342 struct ath9k_channel *chan,
343 void *pRawDataSet,
344 u8 *bChans, u16 availPiers,
345 u16 tPdGainOverlap,
346 u16 *pPdGainBoundaries, u8 *pPDADCValues,
347 u16 numXpdGains)
348 {
349 int i, j, k;
350 int16_t ss;
351 u16 idxL = 0, idxR = 0, numPiers;
352 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
353 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
354 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
355 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
356 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
357 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
358
359 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
360 u8 minPwrT4[AR5416_NUM_PD_GAINS];
361 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
362 int16_t vpdStep;
363 int16_t tmpVal;
364 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
365 bool match;
366 int16_t minDelta = 0;
367 struct chan_centers centers;
368 int pdgain_boundary_default;
369 struct cal_data_per_freq *data_def = pRawDataSet;
370 struct cal_data_per_freq_4k *data_4k = pRawDataSet;
371 struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
372 bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
373 int intercepts;
374
375 if (AR_SREV_9287(ah))
376 intercepts = AR9287_PD_GAIN_ICEPTS;
377 else
378 intercepts = AR5416_PD_GAIN_ICEPTS;
379
380 memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
381 ath9k_hw_get_channel_centers(ah, chan, &centers);
382
383 for (numPiers = 0; numPiers < availPiers; numPiers++) {
384 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
385 break;
386 }
387
388 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
389 IS_CHAN_2GHZ(chan)),
390 bChans, numPiers, &idxL, &idxR);
391
392 if (match) {
393 if (AR_SREV_9287(ah)) {
394 /* FIXME: array overrun? */
395 for (i = 0; i < numXpdGains; i++) {
396 minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
397 maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
398 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
399 data_9287[idxL].pwrPdg[i],
400 data_9287[idxL].vpdPdg[i],
401 intercepts,
402 vpdTableI[i]);
403 }
404 } else if (eeprom_4k) {
405 for (i = 0; i < numXpdGains; i++) {
406 minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
407 maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
408 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
409 data_4k[idxL].pwrPdg[i],
410 data_4k[idxL].vpdPdg[i],
411 intercepts,
412 vpdTableI[i]);
413 }
414 } else {
415 for (i = 0; i < numXpdGains; i++) {
416 minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
417 maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
418 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
419 data_def[idxL].pwrPdg[i],
420 data_def[idxL].vpdPdg[i],
421 intercepts,
422 vpdTableI[i]);
423 }
424 }
425 } else {
426 for (i = 0; i < numXpdGains; i++) {
427 if (AR_SREV_9287(ah)) {
428 pVpdL = data_9287[idxL].vpdPdg[i];
429 pPwrL = data_9287[idxL].pwrPdg[i];
430 pVpdR = data_9287[idxR].vpdPdg[i];
431 pPwrR = data_9287[idxR].pwrPdg[i];
432 } else if (eeprom_4k) {
433 pVpdL = data_4k[idxL].vpdPdg[i];
434 pPwrL = data_4k[idxL].pwrPdg[i];
435 pVpdR = data_4k[idxR].vpdPdg[i];
436 pPwrR = data_4k[idxR].pwrPdg[i];
437 } else {
438 pVpdL = data_def[idxL].vpdPdg[i];
439 pPwrL = data_def[idxL].pwrPdg[i];
440 pVpdR = data_def[idxR].vpdPdg[i];
441 pPwrR = data_def[idxR].pwrPdg[i];
442 }
443
444 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
445
446 maxPwrT4[i] =
447 min(pPwrL[intercepts - 1],
448 pPwrR[intercepts - 1]);
449
450
451 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
452 pPwrL, pVpdL,
453 intercepts,
454 vpdTableL[i]);
455 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
456 pPwrR, pVpdR,
457 intercepts,
458 vpdTableR[i]);
459
460 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
461 vpdTableI[i][j] =
462 (u8)(ath9k_hw_interpolate((u16)
463 FREQ2FBIN(centers.
464 synth_center,
465 IS_CHAN_2GHZ
466 (chan)),
467 bChans[idxL], bChans[idxR],
468 vpdTableL[i][j], vpdTableR[i][j]));
469 }
470 }
471 }
472
473 k = 0;
474
475 for (i = 0; i < numXpdGains; i++) {
476 if (i == (numXpdGains - 1))
477 pPdGainBoundaries[i] =
478 (u16)(maxPwrT4[i] / 2);
479 else
480 pPdGainBoundaries[i] =
481 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
482
483 pPdGainBoundaries[i] =
484 min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
485
486 minDelta = 0;
487
488 if (i == 0) {
489 if (AR_SREV_9280_20_OR_LATER(ah))
490 ss = (int16_t)(0 - (minPwrT4[i] / 2));
491 else
492 ss = 0;
493 } else {
494 ss = (int16_t)((pPdGainBoundaries[i - 1] -
495 (minPwrT4[i] / 2)) -
496 tPdGainOverlap + 1 + minDelta);
497 }
498 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
499 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
500
501 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
502 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
503 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
504 ss++;
505 }
506
507 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
508 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
509 (minPwrT4[i] / 2));
510 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
511 tgtIndex : sizeCurrVpdTable;
512
513 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
514 pPDADCValues[k++] = vpdTableI[i][ss++];
515 }
516
517 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
518 vpdTableI[i][sizeCurrVpdTable - 2]);
519 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
520
521 if (tgtIndex >= maxIndex) {
522 while ((ss <= tgtIndex) &&
523 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
524 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
525 (ss - maxIndex + 1) * vpdStep));
526 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
527 255 : tmpVal);
528 ss++;
529 }
530 }
531 }
532
533 if (eeprom_4k)
534 pdgain_boundary_default = 58;
535 else
536 pdgain_boundary_default = pPdGainBoundaries[i - 1];
537
538 while (i < AR5416_PD_GAINS_IN_MASK) {
539 pPdGainBoundaries[i] = pdgain_boundary_default;
540 i++;
541 }
542
543 while (k < AR5416_NUM_PDADC_VALUES) {
544 pPDADCValues[k] = pPDADCValues[k - 1];
545 k++;
546 }
547 }
548
549 int ath9k_hw_eeprom_init(struct ath_hw *ah)
550 {
551 int status;
552
553 if (AR_SREV_9300_20_OR_LATER(ah))
554 ah->eep_ops = &eep_ar9300_ops;
555 else if (AR_SREV_9287(ah)) {
556 ah->eep_ops = &eep_ar9287_ops;
557 } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
558 ah->eep_ops = &eep_4k_ops;
559 } else {
560 ah->eep_ops = &eep_def_ops;
561 }
562
563 if (!ah->eep_ops->fill_eeprom(ah))
564 return -EIO;
565
566 status = ah->eep_ops->check_eeprom(ah);
567
568 return status;
569 }
kernel source for telekom puls (alcatel/mediatek)