drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "dfs_debug.h"
  23
  24 struct ath_txq;
  25 struct ath_buf;
  26
  27 #ifdef CONFIG_ATH9K_DEBUGFS
  28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  29 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  30 #else
  31 #define TX_STAT_INC(q, c) do { } while (0)
  32 #define RESET_STAT_INC(sc, type) do { } while (0)
  33 #endif
  34
  35 enum ath_reset_type {
  36         RESET_TYPE_BB_HANG,
  37         RESET_TYPE_BB_WATCHDOG,
  38         RESET_TYPE_FATAL_INT,
  39         RESET_TYPE_TX_ERROR,
  40         RESET_TYPE_TX_HANG,
  41         RESET_TYPE_PLL_HANG,
  42         RESET_TYPE_MAC_HANG,
  43         RESET_TYPE_BEACON_STUCK,
  44         RESET_TYPE_MCI,
  45         __RESET_TYPE_MAX
  46 };
  47
  48 #ifdef CONFIG_ATH9K_DEBUGFS
  49
  50 /**
  51  * struct ath_interrupt_stats - Contains statistics about interrupts
  52  * @total: Total no. of interrupts generated so far
  53  * @rxok: RX with no errors
  54  * @rxlp: RX with low priority RX
  55  * @rxhp: RX with high priority, uapsd only
  56  * @rxeol: RX with no more RXDESC available
  57  * @rxorn: RX FIFO overrun
  58  * @txok: TX completed at the requested rate
  59  * @txurn: TX FIFO underrun
  60  * @mib: MIB regs reaching its threshold
  61  * @rxphyerr: RX with phy errors
  62  * @rx_keycache_miss: RX with key cache misses
  63  * @swba: Software Beacon Alert
  64  * @bmiss: Beacon Miss
  65  * @bnr: Beacon Not Ready
  66  * @cst: Carrier Sense TImeout
  67  * @gtt: Global TX Timeout
  68  * @tim: RX beacon TIM occurrence
  69  * @cabend: RX End of CAB traffic
  70  * @dtimsync: DTIM sync lossage
  71  * @dtim: RX Beacon with DTIM
  72  * @bb_watchdog: Baseband watchdog
  73  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  74  * from a beacon differs from the PCU's internal TSF by more than a
  75  * (programmable) threshold
  76  * @local_timeout: Internal bus timeout.
  77  * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
  78  * @gen_timer: Generic hardware timer interrupt
  79  */
  80 struct ath_interrupt_stats {
  81         u32 total;
  82         u32 rxok;
  83         u32 rxlp;
  84         u32 rxhp;
  85         u32 rxeol;
  86         u32 rxorn;
  87         u32 txok;
  88         u32 txeol;
  89         u32 txurn;
  90         u32 mib;
  91         u32 rxphyerr;
  92         u32 rx_keycache_miss;
  93         u32 swba;
  94         u32 bmiss;
  95         u32 bnr;
  96         u32 cst;
  97         u32 gtt;
  98         u32 tim;
  99         u32 cabend;
 100         u32 dtimsync;
 101         u32 dtim;
 102         u32 bb_watchdog;
 103         u32 tsfoor;
 104         u32 mci;
 105         u32 gen_timer;
 106
 107         /* Sync-cause stats */
 108         u32 sync_cause_all;
 109         u32 sync_rtc_irq;
 110         u32 sync_mac_irq;
 111         u32 eeprom_illegal_access;
 112         u32 apb_timeout;
 113         u32 pci_mode_conflict;
 114         u32 host1_fatal;
 115         u32 host1_perr;
 116         u32 trcv_fifo_perr;
 117         u32 radm_cpl_ep;
 118         u32 radm_cpl_dllp_abort;
 119         u32 radm_cpl_tlp_abort;
 120         u32 radm_cpl_ecrc_err;
 121         u32 radm_cpl_timeout;
 122         u32 local_timeout;
 123         u32 pm_access;
 124         u32 mac_awake;
 125         u32 mac_asleep;
 126         u32 mac_sleep_access;
 127 };
 128
 129
 130 /**
 131  * struct ath_tx_stats - Statistics about TX
 132  * @tx_pkts_all:  No. of total frames transmitted, including ones that
 133         may have had errors.
 134  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
 135         may have had errors.
 136  * @queued: Total MPDUs (non-aggr) queued
 137  * @completed: Total MPDUs (non-aggr) completed
 138  * @a_aggr: Total no. of aggregates queued
 139  * @a_queued_hw: Total AMPDUs queued to hardware
 140  * @a_queued_sw: Total AMPDUs queued to software queues
 141  * @a_completed: Total AMPDUs completed
 142  * @a_retries: No. of AMPDUs retried (SW)
 143  * @a_xretries: No. of AMPDUs dropped due to xretries
 144  * @fifo_underrun: FIFO underrun occurrences
 145         Valid only for:
 146                 - non-aggregate condition.
 147                 - first packet of aggregate.
 148  * @xtxop: No. of frames filtered because of TXOP limit
 149  * @timer_exp: Transmit timer expiry
 150  * @desc_cfg_err: Descriptor configuration errors
 151  * @data_urn: TX data underrun errors
 152  * @delim_urn: TX delimiter underrun errors
 153  * @puttxbuf: Number of times hardware was given txbuf to write.
 154  * @txstart:  Number of times hardware was told to start tx.
 155  * @txprocdesc:  Number of times tx descriptor was processed
 156  * @txfailed:  Out-of-memory or other errors in xmit path.
 157  */
 158 struct ath_tx_stats {
 159         u32 tx_pkts_all;
 160         u32 tx_bytes_all;
 161         u32 queued;
 162         u32 completed;
 163         u32 xretries;
 164         u32 a_aggr;
 165         u32 a_queued_hw;
 166         u32 a_queued_sw;
 167         u32 a_completed;
 168         u32 a_retries;
 169         u32 a_xretries;
 170         u32 fifo_underrun;
 171         u32 xtxop;
 172         u32 timer_exp;
 173         u32 desc_cfg_err;
 174         u32 data_underrun;
 175         u32 delim_underrun;
 176         u32 puttxbuf;
 177         u32 txstart;
 178         u32 txprocdesc;
 179         u32 txfailed;
 180 };
 181
 182 /*
 183  * Various utility macros to print TX/Queue counters.
 184  */
 185 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
 186 #define TXSTATS sc->debug.stats.txstats
 187 #define PR(str, elem)                                                   \
 188         do {                                                            \
 189                 len += snprintf(buf + len, size - len,                  \
 190                                 "%s%13u%11u%10u%10u\n", str,            \
 191                                 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem, \
 192                                 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem, \
 193                                 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem, \
 194                                 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
 195         } while(0)
 196
 197 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
 198
 199 /**
 200  * struct ath_rx_stats - RX Statistics
 201  * @rx_pkts_all:  No. of total frames received, including ones that
 202         may have had errors.
 203  * @rx_bytes_all:  No. of total bytes received, including ones that
 204         may have had errors.
 205  * @crc_err: No. of frames with incorrect CRC value
 206  * @decrypt_crc_err: No. of frames whose CRC check failed after
 207         decryption process completed
 208  * @phy_err: No. of frames whose reception failed because the PHY
 209         encountered an error
 210  * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 211  * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 212  * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 213  * @decrypt_busy_err: Decryption interruptions counter
 214  * @phy_err_stats: Individual PHY error statistics
 215  * @rx_len_err:  No. of frames discarded due to bad length.
 216  * @rx_oom_err:  No. of frames dropped due to OOM issues.
 217  * @rx_rate_err:  No. of frames dropped due to rate errors.
 218  * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 219  * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
 220  * @rx_beacons:  No. of beacons received.
 221  * @rx_frags:  No. of rx-fragements received.
 222  */
 223 struct ath_rx_stats {
 224         u32 rx_pkts_all;
 225         u32 rx_bytes_all;
 226         u32 crc_err;
 227         u32 decrypt_crc_err;
 228         u32 phy_err;
 229         u32 mic_err;
 230         u32 pre_delim_crc_err;
 231         u32 post_delim_crc_err;
 232         u32 decrypt_busy_err;
 233         u32 phy_err_stats[ATH9K_PHYERR_MAX];
 234         u32 rx_len_err;
 235         u32 rx_oom_err;
 236         u32 rx_rate_err;
 237         u32 rx_too_many_frags_err;
 238         u32 rx_drop_rxflush;
 239         u32 rx_beacons;
 240         u32 rx_frags;
 241 };
 242
 243 struct ath_stats {
 244         struct ath_interrupt_stats istats;
 245         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 246         struct ath_rx_stats rxstats;
 247         struct ath_dfs_stats dfs_stats;
 248         u32 reset[__RESET_TYPE_MAX];
 249 };
 250
 251 #define ATH_DBG_MAX_SAMPLES     10
 252 struct ath_dbg_bb_mac_samp {
 253         u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
 254         u32 pcu_obs, pcu_cr, noise;
 255         struct {
 256                 u64 jiffies;
 257                 int8_t rssi_ctl0;
 258                 int8_t rssi_ctl1;
 259                 int8_t rssi_ctl2;
 260                 int8_t rssi_ext0;
 261                 int8_t rssi_ext1;
 262                 int8_t rssi_ext2;
 263                 int8_t rssi;
 264                 bool isok;
 265                 u8 rts_fail_cnt;
 266                 u8 data_fail_cnt;
 267                 u8 rateindex;
 268                 u8 qid;
 269                 u8 tid;
 270                 u32 ba_low;
 271                 u32 ba_high;
 272         } ts[ATH_DBG_MAX_SAMPLES];
 273         struct {
 274                 u64 jiffies;
 275                 int8_t rssi_ctl0;
 276                 int8_t rssi_ctl1;
 277                 int8_t rssi_ctl2;
 278                 int8_t rssi_ext0;
 279                 int8_t rssi_ext1;
 280                 int8_t rssi_ext2;
 281                 int8_t rssi;
 282                 bool is_mybeacon;
 283                 u8 antenna;
 284                 u8 rate;
 285         } rs[ATH_DBG_MAX_SAMPLES];
 286         struct ath_cycle_counters cc;
 287         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 288 };
 289
 290 struct ath9k_debug {
 291         struct dentry *debugfs_phy;
 292         u32 regidx;
 293         struct ath_stats stats;
 294 #ifdef CONFIG_ATH9K_MAC_DEBUG
 295         spinlock_t samp_lock;
 296         struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
 297         u8 sampidx;
 298         u8 tsidx;
 299         u8 rsidx;
 300 #endif
 301 };
 302
 303 int ath9k_init_debug(struct ath_hw *ah);
 304
 305 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 306 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 307                        struct ath_tx_status *ts, struct ath_txq *txq,
 308                        unsigned int flags);
 309 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 310 int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
 311                             struct ieee80211_vif *vif, int sset);
 312 void ath9k_get_et_stats(struct ieee80211_hw *hw,
 313                         struct ieee80211_vif *vif,
 314                         struct ethtool_stats *stats, u64 *data);
 315 void ath9k_get_et_strings(struct ieee80211_hw *hw,
 316                           struct ieee80211_vif *vif,
 317                           u32 sset, u8 *data);
 318 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
 319                            struct ieee80211_vif *vif,
 320                            struct ieee80211_sta *sta,
 321                            struct dentry *dir);
 322 void ath9k_sta_remove_debugfs(struct ieee80211_hw *hw,
 323                               struct ieee80211_vif *vif,
 324                               struct ieee80211_sta *sta,
 325                               struct dentry *dir);
 326 #else
 327
 328 #define RX_STAT_INC(c) /* NOP */
 329
 330 static inline int ath9k_init_debug(struct ath_hw *ah)
 331 {
 332         return 0;
 333 }
 334
 335 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 336                                             enum ath9k_int status)
 337 {
 338 }
 339
 340 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 341                                      struct ath_buf *bf,
 342                                      struct ath_tx_status *ts,
 343                                      struct ath_txq *txq,
 344                                      unsigned int flags)
 345 {
 346 }
 347
 348 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 349                                      struct ath_rx_status *rs)
 350 {
 351 }
 352
 353 #endif /* CONFIG_ATH9K_DEBUGFS */
 354
 355 #ifdef CONFIG_ATH9K_MAC_DEBUG
 356
 357 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
 358
 359 #else
 360
 361 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
 362 {
 363 }
 364
 365 #endif
 366
 367
 368 #endif /* DEBUG_H */