drivers/net/wireless/ath/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/etherdevice.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/leds.h>
  24 #include <linux/completion.h>
  25
  26 #include "debug.h"
  27 #include "common.h"
  28
  29 /*
  30  * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
  31  * should rely on this file or its contents.
  32  */
  33
  34 struct ath_node;
  35
  36 /* Macro to expand scalars to 64-bit objects */
  37
  38 #define ito64(x) (sizeof(x) == 1) ?                     \
  39         (((unsigned long long int)(x)) & (0xff)) :      \
  40         (sizeof(x) == 2) ?                              \
  41         (((unsigned long long int)(x)) & 0xffff) :      \
  42         ((sizeof(x) == 4) ?                             \
  43          (((unsigned long long int)(x)) & 0xffffffff) : \
  44          (unsigned long long int)(x))
  45
  46 /* increment with wrap-around */
  47 #define INCR(_l, _sz)   do {                    \
  48                 (_l)++;                         \
  49                 (_l) &= ((_sz) - 1);            \
  50         } while (0)
  51
  52 /* decrement with wrap-around */
  53 #define DECR(_l,  _sz)  do {                    \
  54                 (_l)--;                         \
  55                 (_l) &= ((_sz) - 1);            \
  56         } while (0)
  57
  58 #define TSF_TO_TU(_h,_l) \
  59         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
  60
  61 #define ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))
  62
  63 struct ath_config {
  64         u16 txpowlimit;
  65         u8 cabqReadytime;
  66 };
  67
  68 /*************************/
  69 /* Descriptor Management */
  70 /*************************/
  71
  72 #define ATH_TXBUF_RESET(_bf) do {                               \
  73                 (_bf)->bf_stale = false;                        \
  74                 (_bf)->bf_lastbf = NULL;                        \
  75                 (_bf)->bf_next = NULL;                          \
  76                 memset(&((_bf)->bf_state), 0,                   \
  77                        sizeof(struct ath_buf_state));           \
  78         } while (0)
  79
  80 #define ATH_RXBUF_RESET(_bf) do {               \
  81                 (_bf)->bf_stale = false;        \
  82         } while (0)
  83
  84 /**
  85  * enum buffer_type - Buffer type flags
  86  *
  87  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  88  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  89  *      (used in aggregation scheduling)
  90  */
  91 enum buffer_type {
  92         BUF_AMPDU               = BIT(0),
  93         BUF_AGGR                = BIT(1),
  94 };
  95
  96 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
  97 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
  98
  99 #define ATH_TXSTATUS_RING_SIZE 64
 100
 101 #define DS2PHYS(_dd, _ds)                                               \
 102         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
 103 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
 104 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
 105
 106 struct ath_descdma {
 107         void *dd_desc;
 108         dma_addr_t dd_desc_paddr;
 109         u32 dd_desc_len;
 110         struct ath_buf *dd_bufptr;
 111 };
 112
 113 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 114                       struct list_head *head, const char *name,
 115                       int nbuf, int ndesc, bool is_tx);
 116 void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 117                          struct list_head *head);
 118
 119 /***********/
 120 /* RX / TX */
 121 /***********/
 122
 123 #define ATH_RXBUF               512
 124 #define ATH_TXBUF               512
 125 #define ATH_TXBUF_RESERVE       5
 126 #define ATH_MAX_QDEPTH          (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
 127 #define ATH_TXMAXTRY            13
 128
 129 #define TID_TO_WME_AC(_tid)                             \
 130         ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
 131          (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
 132          (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
 133          WME_AC_VO)
 134
 135 #define ATH_AGGR_DELIM_SZ          4
 136 #define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
 137 /* number of delimiters for encryption padding */
 138 #define ATH_AGGR_ENCRYPTDELIM      10
 139 /* minimum h/w qdepth to be sustained to maximize aggregation */
 140 #define ATH_AGGR_MIN_QDEPTH        2
 141 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
 142
 143 #define IEEE80211_SEQ_SEQ_SHIFT    4
 144 #define IEEE80211_SEQ_MAX          4096
 145 #define IEEE80211_WEP_IVLEN        3
 146 #define IEEE80211_WEP_KIDLEN       1
 147 #define IEEE80211_WEP_CRCLEN       4
 148 #define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +            \
 149                                     (IEEE80211_WEP_IVLEN +      \
 150                                      IEEE80211_WEP_KIDLEN +     \
 151                                      IEEE80211_WEP_CRCLEN))
 152
 153 /* return whether a bit at index _n in bitmap _bm is set
 154  * _sz is the size of the bitmap  */
 155 #define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&           \
 156                                 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
 157
 158 /* return block-ack bitmap index given sequence and starting sequence */
 159 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
 160
 161 /* returns delimiter padding required given the packet length */
 162 #define ATH_AGGR_GET_NDELIM(_len)                                       \
 163        (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
 164         DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 165
 166 #define BAW_WITHIN(_start, _bawsz, _seqno) \
 167         ((((_seqno) - (_start)) & 4095) < (_bawsz))
 168
 169 #define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])
 170
 171 #define ATH_TX_COMPLETE_POLL_INT        1000
 172
 173 enum ATH_AGGR_STATUS {
 174         ATH_AGGR_DONE,
 175         ATH_AGGR_BAW_CLOSED,
 176         ATH_AGGR_LIMITED,
 177 };
 178
 179 #define ATH_TXFIFO_DEPTH 8
 180 struct ath_txq {
 181         int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
 182         u32 axq_qnum; /* ath9k hardware queue number */
 183         void *axq_link;
 184         struct list_head axq_q;
 185         spinlock_t axq_lock;
 186         u32 axq_depth;
 187         u32 axq_ampdu_depth;
 188         bool stopped;
 189         bool axq_tx_inprogress;
 190         struct list_head axq_acq;
 191         struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
 192         u8 txq_headidx;
 193         u8 txq_tailidx;
 194         int pending_frames;
 195 };
 196
 197 struct ath_atx_ac {
 198         struct ath_txq *txq;
 199         int sched;
 200         struct list_head list;
 201         struct list_head tid_q;
 202         bool clear_ps_filter;
 203 };
 204
 205 struct ath_frame_info {
 206         struct ath_buf *bf;
 207         int framelen;
 208         enum ath9k_key_type keytype;
 209         u8 keyix;
 210         u8 retries;
 211 };
 212
 213 struct ath_buf_state {
 214         u8 bf_type;
 215         u8 bfs_paprd;
 216         u8 ndelim;
 217         u16 seqno;
 218         unsigned long bfs_paprd_timestamp;
 219 };
 220
 221 struct ath_buf {
 222         struct list_head list;
 223         struct ath_buf *bf_lastbf;      /* last buf of this unit (a frame or
 224                                            an aggregate) */
 225         struct ath_buf *bf_next;        /* next subframe in the aggregate */
 226         struct sk_buff *bf_mpdu;        /* enclosing frame structure */
 227         void *bf_desc;                  /* virtual addr of desc */
 228         dma_addr_t bf_daddr;            /* physical addr of desc */
 229         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
 230         bool bf_stale;
 231         struct ath_buf_state bf_state;
 232 };
 233
 234 struct ath_atx_tid {
 235         struct list_head list;
 236         struct sk_buff_head buf_q;
 237         struct ath_node *an;
 238         struct ath_atx_ac *ac;
 239         unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
 240         u16 seq_start;
 241         u16 seq_next;
 242         u16 baw_size;
 243         int tidno;
 244         int baw_head;   /* first un-acked tx buffer */
 245         int baw_tail;   /* next unused tx buffer slot */
 246         int sched;
 247         int paused;
 248         u8 state;
 249 };
 250
 251 struct ath_node {
 252 #ifdef CONFIG_ATH9K_DEBUGFS
 253         struct list_head list; /* for sc->nodes */
 254         struct ieee80211_sta *sta; /* station struct we're part of */
 255 #endif
 256         struct ath_atx_tid tid[WME_NUM_TID];
 257         struct ath_atx_ac ac[WME_NUM_AC];
 258         int ps_key;
 259
 260         u16 maxampdu;
 261         u8 mpdudensity;
 262
 263         bool sleeping;
 264 };
 265
 266 #define AGGR_CLEANUP         BIT(1)
 267 #define AGGR_ADDBA_COMPLETE  BIT(2)
 268 #define AGGR_ADDBA_PROGRESS  BIT(3)
 269
 270 struct ath_tx_control {
 271         struct ath_txq *txq;
 272         struct ath_node *an;
 273         u8 paprd;
 274 };
 275
 276 #define ATH_TX_ERROR        0x01
 277 #define ATH_TX_BAR          0x02
 278
 279 /**
 280  * @txq_map:  Index is mac80211 queue number.  This is
 281  *  not necessarily the same as the hardware queue number
 282  *  (axq_qnum).
 283  */
 284 struct ath_tx {
 285         u16 seq_no;
 286         u32 txqsetup;
 287         spinlock_t txbuflock;
 288         struct list_head txbuf;
 289         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
 290         struct ath_descdma txdma;
 291         struct ath_txq *txq_map[WME_NUM_AC];
 292 };
 293
 294 struct ath_rx_edma {
 295         struct sk_buff_head rx_fifo;
 296         struct sk_buff_head rx_buffers;
 297         u32 rx_fifo_hwsize;
 298 };
 299
 300 struct ath_rx {
 301         u8 defant;
 302         u8 rxotherant;
 303         u32 *rxlink;
 304         unsigned int rxfilter;
 305         spinlock_t rxbuflock;
 306         struct list_head rxbuf;
 307         struct ath_descdma rxdma;
 308         struct ath_buf *rx_bufptr;
 309         struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
 310
 311         struct sk_buff *frag;
 312 };
 313
 314 int ath_startrecv(struct ath_softc *sc);
 315 bool ath_stoprecv(struct ath_softc *sc);
 316 void ath_flushrecv(struct ath_softc *sc);
 317 u32 ath_calcrxfilter(struct ath_softc *sc);
 318 int ath_rx_init(struct ath_softc *sc, int nbufs);
 319 void ath_rx_cleanup(struct ath_softc *sc);
 320 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 321 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 322 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
 323 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 324 void ath_draintxq(struct ath_softc *sc,
 325                      struct ath_txq *txq, bool retry_tx);
 326 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
 327 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
 328 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
 329 int ath_tx_init(struct ath_softc *sc, int nbufs);
 330 void ath_tx_cleanup(struct ath_softc *sc);
 331 int ath_txq_update(struct ath_softc *sc, int qnum,
 332                    struct ath9k_tx_queue_info *q);
 333 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
 334                  struct ath_tx_control *txctl);
 335 void ath_tx_tasklet(struct ath_softc *sc);
 336 void ath_tx_edma_tasklet(struct ath_softc *sc);
 337 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
 338                       u16 tid, u16 *ssn);
 339 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 340 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 341
 342 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
 343 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
 344
 345 /********/
 346 /* VIFs */
 347 /********/
 348
 349 struct ath_vif {
 350         int av_bslot;
 351         bool is_bslot_active, primary_sta_vif;
 352         __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
 353         struct ath_buf *av_bcbuf;
 354 };
 355
 356 /*******************/
 357 /* Beacon Handling */
 358 /*******************/
 359
 360 /*
 361  * Regardless of the number of beacons we stagger, (i.e. regardless of the
 362  * number of BSSIDs) if a given beacon does not go out even after waiting this
 363  * number of beacon intervals, the game's up.
 364  */
 365 #define BSTUCK_THRESH                   9
 366 #define ATH_BCBUF                       4
 367 #define ATH_DEFAULT_BINTVAL             100 /* TU */
 368 #define ATH_DEFAULT_BMISS_LIMIT         10
 369 #define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)
 370
 371 struct ath_beacon_config {
 372         int beacon_interval;
 373         u16 listen_interval;
 374         u16 dtim_period;
 375         u16 bmiss_timeout;
 376         u8 dtim_count;
 377 };
 378
 379 struct ath_beacon {
 380         enum {
 381                 OK,             /* no change needed */
 382                 UPDATE,         /* update pending */
 383                 COMMIT          /* beacon sent, commit change */
 384         } updateslot;           /* slot time update fsm */
 385
 386         u32 beaconq;
 387         u32 bmisscnt;
 388         u32 ast_be_xmit;
 389         u32 bc_tstamp;
 390         struct ieee80211_vif *bslot[ATH_BCBUF];
 391         int slottime;
 392         int slotupdate;
 393         struct ath9k_tx_queue_info beacon_qi;
 394         struct ath_descdma bdma;
 395         struct ath_txq *cabq;
 396         struct list_head bbuf;
 397
 398         bool tx_processed;
 399         bool tx_last;
 400 };
 401
 402 void ath_beacon_tasklet(unsigned long data);
 403 void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
 404 int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
 405 void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
 406 int ath_beaconq_config(struct ath_softc *sc);
 407 void ath_set_beacon(struct ath_softc *sc);
 408 void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
 409
 410 /*******/
 411 /* ANI */
 412 /*******/
 413
 414 #define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
 415 #define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
 416 #define ATH_ANI_POLLINTERVAL_OLD  100     /* 100 ms */
 417 #define ATH_ANI_POLLINTERVAL_NEW  1000    /* 1000 ms */
 418 #define ATH_LONG_CALINTERVAL_INT  1000    /* 1000 ms */
 419 #define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
 420 #define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */
 421
 422 #define ATH_PAPRD_TIMEOUT       100 /* msecs */
 423
 424 void ath_reset_work(struct work_struct *work);
 425 void ath_hw_check(struct work_struct *work);
 426 void ath_hw_pll_work(struct work_struct *work);
 427 void ath_paprd_calibrate(struct work_struct *work);
 428 void ath_ani_calibrate(unsigned long data);
 429 void ath_start_ani(struct ath_common *common);
 430
 431 /**********/
 432 /* BTCOEX */
 433 /**********/
 434
 435 struct ath_btcoex {
 436         bool hw_timer_enabled;
 437         spinlock_t btcoex_lock;
 438         struct timer_list period_timer; /* Timer for BT period */
 439         u32 bt_priority_cnt;
 440         unsigned long bt_priority_time;
 441         int bt_stomp_type; /* Types of BT stomping */
 442         u32 btcoex_no_stomp; /* in usec */
 443         u32 btcoex_period; /* in usec */
 444         u32 btscan_no_stomp; /* in usec */
 445         struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
 446 };
 447
 448 int ath_init_btcoex_timer(struct ath_softc *sc);
 449 void ath9k_btcoex_timer_resume(struct ath_softc *sc);
 450 void ath9k_btcoex_timer_pause(struct ath_softc *sc);
 451
 452 /********************/
 453 /*   LED Control    */
 454 /********************/
 455
 456 #define ATH_LED_PIN_DEF                 1
 457 #define ATH_LED_PIN_9287                8
 458 #define ATH_LED_PIN_9300                10
 459 #define ATH_LED_PIN_9485                6
 460 #define ATH_LED_PIN_9480                0
 461
 462 #ifdef CONFIG_MAC80211_LEDS
 463 void ath_init_leds(struct ath_softc *sc);
 464 void ath_deinit_leds(struct ath_softc *sc);
 465 #else
 466 static inline void ath_init_leds(struct ath_softc *sc)
 467 {
 468 }
 469
 470 static inline void ath_deinit_leds(struct ath_softc *sc)
 471 {
 472 }
 473 #endif
 474
 475
 476 /* Antenna diversity/combining */
 477 #define ATH_ANT_RX_CURRENT_SHIFT 4
 478 #define ATH_ANT_RX_MAIN_SHIFT 2
 479 #define ATH_ANT_RX_MASK 0x3
 480
 481 #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
 482 #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
 483 #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
 484 #define ATH_ANT_DIV_COMB_INIT_COUNT 95
 485 #define ATH_ANT_DIV_COMB_MAX_COUNT 100
 486 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
 487 #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
 488
 489 #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
 490 #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
 491 #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
 492 #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
 493
 494 enum ath9k_ant_div_comb_lna_conf {
 495         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
 496         ATH_ANT_DIV_COMB_LNA2,
 497         ATH_ANT_DIV_COMB_LNA1,
 498         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
 499 };
 500
 501 struct ath_ant_comb {
 502         u16 count;
 503         u16 total_pkt_count;
 504         bool scan;
 505         bool scan_not_start;
 506         int main_total_rssi;
 507         int alt_total_rssi;
 508         int alt_recv_cnt;
 509         int main_recv_cnt;
 510         int rssi_lna1;
 511         int rssi_lna2;
 512         int rssi_add;
 513         int rssi_sub;
 514         int rssi_first;
 515         int rssi_second;
 516         int rssi_third;
 517         bool alt_good;
 518         int quick_scan_cnt;
 519         int main_conf;
 520         enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
 521         enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
 522         int first_bias;
 523         int second_bias;
 524         bool first_ratio;
 525         bool second_ratio;
 526         unsigned long scan_start_time;
 527 };
 528
 529 /********************/
 530 /* Main driver core */
 531 /********************/
 532
 533 /*
 534  * Default cache line size, in bytes.
 535  * Used when PCI device not fully initialized by bootrom/BIOS
 536 */
 537 #define DEFAULT_CACHELINE       32
 538 #define ATH_REGCLASSIDS_MAX     10
 539 #define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
 540 #define ATH_MAX_SW_RETRIES      10
 541 #define ATH_CHAN_MAX            255
 542
 543 #define ATH_TXPOWER_MAX         100     /* .5 dBm units */
 544 #define ATH_RATE_DUMMY_MARKER   0
 545
 546 #define SC_OP_INVALID                BIT(0)
 547 #define SC_OP_BEACONS                BIT(1)
 548 #define SC_OP_RXAGGR                 BIT(2)
 549 #define SC_OP_TXAGGR                 BIT(3)
 550 #define SC_OP_OFFCHANNEL             BIT(4)
 551 #define SC_OP_PREAMBLE_SHORT         BIT(5)
 552 #define SC_OP_PROTECT_ENABLE         BIT(6)
 553 #define SC_OP_RXFLUSH                BIT(7)
 554 #define SC_OP_LED_ASSOCIATED         BIT(8)
 555 #define SC_OP_LED_ON                 BIT(9)
 556 #define SC_OP_TSF_RESET              BIT(11)
 557 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 558 #define SC_OP_BT_SCAN                BIT(13)
 559 #define SC_OP_ANI_RUN                BIT(14)
 560 #define SC_OP_PRIM_STA_VIF           BIT(15)
 561
 562 /* Powersave flags */
 563 #define PS_WAIT_FOR_BEACON        BIT(0)
 564 #define PS_WAIT_FOR_CAB           BIT(1)
 565 #define PS_WAIT_FOR_PSPOLL_DATA   BIT(2)
 566 #define PS_WAIT_FOR_TX_ACK        BIT(3)
 567 #define PS_BEACON_SYNC            BIT(4)
 568
 569 struct ath_rate_table;
 570
 571 struct ath9k_vif_iter_data {
 572         const u8 *hw_macaddr; /* phy's hardware address, set
 573                                * before starting iteration for
 574                                * valid bssid mask.
 575                                */
 576         u8 mask[ETH_ALEN]; /* bssid mask */
 577         int naps;      /* number of AP vifs */
 578         int nmeshes;   /* number of mesh vifs */
 579         int nstations; /* number of station vifs */
 580         int nwds;      /* number of WDS vifs */
 581         int nadhocs;   /* number of adhoc vifs */
 582         int nothers;   /* number of vifs not specified above. */
 583 };
 584
 585 struct ath_softc {
 586         struct ieee80211_hw *hw;
 587         struct device *dev;
 588
 589         int chan_idx;
 590         int chan_is_ht;
 591         struct survey_info *cur_survey;
 592         struct survey_info survey[ATH9K_NUM_CHANNELS];
 593
 594         struct tasklet_struct intr_tq;
 595         struct tasklet_struct bcon_tasklet;
 596         struct ath_hw *sc_ah;
 597         void __iomem *mem;
 598         int irq;
 599         spinlock_t sc_serial_rw;
 600         spinlock_t sc_pm_lock;
 601         spinlock_t sc_pcu_lock;
 602         struct mutex mutex;
 603         struct work_struct paprd_work;
 604         struct work_struct hw_check_work;
 605         struct work_struct hw_reset_work;
 606         struct completion paprd_complete;
 607
 608         unsigned int hw_busy_count;
 609
 610         u32 intrstatus;
 611         u32 sc_flags; /* SC_OP_* */
 612         u16 ps_flags; /* PS_* */
 613         u16 curtxpow;
 614         bool ps_enabled;
 615         bool ps_idle;
 616         short nbcnvifs;
 617         short nvifs;
 618         unsigned long ps_usecount;
 619
 620         struct ath_config config;
 621         struct ath_rx rx;
 622         struct ath_tx tx;
 623         struct ath_beacon beacon;
 624         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 625
 626 #ifdef CONFIG_MAC80211_LEDS
 627         bool led_registered;
 628         char led_name[32];
 629         struct led_classdev led_cdev;
 630 #endif
 631
 632         struct ath9k_hw_cal_data caldata;
 633         int last_rssi;
 634
 635 #ifdef CONFIG_ATH9K_DEBUGFS
 636         struct ath9k_debug debug;
 637         spinlock_t nodes_lock;
 638         struct list_head nodes; /* basically, stations */
 639         unsigned int tx_complete_poll_work_seen;
 640 #endif
 641         struct ath_beacon_config cur_beacon_conf;
 642         struct delayed_work tx_complete_work;
 643         struct delayed_work hw_pll_work;
 644         struct ath_btcoex btcoex;
 645
 646         struct ath_descdma txsdma;
 647
 648         struct ath_ant_comb ant_comb;
 649         u8 ant_tx, ant_rx;
 650 };
 651
 652 void ath9k_tasklet(unsigned long data);
 653 int ath_cabq_update(struct ath_softc *);
 654
 655 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 656 {
 657         common->bus_ops->read_cachesize(common, csz);
 658 }
 659
 660 extern struct ieee80211_ops ath9k_ops;
 661 extern int ath9k_modparam_nohwcrypt;
 662 extern int led_blink;
 663 extern bool is_ath9k_unloaded;
 664
 665 irqreturn_t ath_isr(int irq, void *dev);
 666 int ath9k_init_device(u16 devid, struct ath_softc *sc,
 667                     const struct ath_bus_ops *bus_ops);
 668 void ath9k_deinit_device(struct ath_softc *sc);
 669 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 670 void ath9k_reload_chainmask_settings(struct ath_softc *sc);
 671
 672 void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
 673 bool ath9k_uses_beacons(int type);
 674
 675 #ifdef CONFIG_ATH9K_PCI
 676 int ath_pci_init(void);
 677 void ath_pci_exit(void);
 678 #else
 679 static inline int ath_pci_init(void) { return 0; };
 680 static inline void ath_pci_exit(void) {};
 681 #endif
 682
 683 #ifdef CONFIG_ATH9K_AHB
 684 int ath_ahb_init(void);
 685 void ath_ahb_exit(void);
 686 #else
 687 static inline int ath_ahb_init(void) { return 0; };
 688 static inline void ath_ahb_exit(void) {};
 689 #endif
 690
 691 void ath9k_ps_wakeup(struct ath_softc *sc);
 692 void ath9k_ps_restore(struct ath_softc *sc);
 693
 694 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
 695
 696 void ath_start_rfkill_poll(struct ath_softc *sc);
 697 extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
 698 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
 699                                struct ieee80211_vif *vif,
 700                                struct ath9k_vif_iter_data *iter_data);
 701
 702
 703 #endif /* ATH9K_H */