2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
24 #include "ar9580_1p0_initvals.h"
26 /* General hardware code for the AR9003 hadware family */
29 * The AR9003 family uses a new INI format (pre, core, post
30 * arrays per subsystem). This provides support for the
31 * AR9003 2.2 chipsets.
33 static void ar9003_hw_init_mode_regs(struct ath_hw
*ah
)
35 if (AR_SREV_9330_11(ah
)) {
37 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
38 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
40 ARRAY_SIZE(ar9331_1p1_mac_core
), 2);
41 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
42 ar9331_1p1_mac_postamble
,
43 ARRAY_SIZE(ar9331_1p1_mac_postamble
), 5);
46 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], NULL
, 0, 0);
47 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
48 ar9331_1p1_baseband_core
,
49 ARRAY_SIZE(ar9331_1p1_baseband_core
), 2);
50 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
51 ar9331_1p1_baseband_postamble
,
52 ARRAY_SIZE(ar9331_1p1_baseband_postamble
), 5);
55 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
56 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
57 ar9331_1p1_radio_core
,
58 ARRAY_SIZE(ar9331_1p1_radio_core
), 2);
59 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
], NULL
, 0, 0);
62 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
63 ar9331_1p1_soc_preamble
,
64 ARRAY_SIZE(ar9331_1p1_soc_preamble
), 2);
65 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
66 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
],
67 ar9331_1p1_soc_postamble
,
68 ARRAY_SIZE(ar9331_1p1_soc_postamble
), 2);
71 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
72 ar9331_common_rx_gain_1p1
,
73 ARRAY_SIZE(ar9331_common_rx_gain_1p1
), 2);
74 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
75 ar9331_modes_lowest_ob_db_tx_gain_1p1
,
76 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1
),
79 /* additional clock settings */
81 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
83 ARRAY_SIZE(ar9331_1p1_xtal_25M
), 2);
85 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
87 ARRAY_SIZE(ar9331_1p1_xtal_40M
), 2);
88 } else if (AR_SREV_9330_12(ah
)) {
90 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
91 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
93 ARRAY_SIZE(ar9331_1p2_mac_core
), 2);
94 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
95 ar9331_1p2_mac_postamble
,
96 ARRAY_SIZE(ar9331_1p2_mac_postamble
), 5);
99 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], NULL
, 0, 0);
100 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
101 ar9331_1p2_baseband_core
,
102 ARRAY_SIZE(ar9331_1p2_baseband_core
), 2);
103 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
104 ar9331_1p2_baseband_postamble
,
105 ARRAY_SIZE(ar9331_1p2_baseband_postamble
), 5);
108 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
109 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
110 ar9331_1p2_radio_core
,
111 ARRAY_SIZE(ar9331_1p2_radio_core
), 2);
112 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
], NULL
, 0, 0);
115 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
116 ar9331_1p2_soc_preamble
,
117 ARRAY_SIZE(ar9331_1p2_soc_preamble
), 2);
118 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
119 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
],
120 ar9331_1p2_soc_postamble
,
121 ARRAY_SIZE(ar9331_1p2_soc_postamble
), 2);
124 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
125 ar9331_common_rx_gain_1p2
,
126 ARRAY_SIZE(ar9331_common_rx_gain_1p2
), 2);
127 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
128 ar9331_modes_lowest_ob_db_tx_gain_1p2
,
129 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2
),
132 /* additional clock settings */
133 if (ah
->is_clk_25mhz
)
134 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
136 ARRAY_SIZE(ar9331_1p2_xtal_25M
), 2);
138 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
140 ARRAY_SIZE(ar9331_1p2_xtal_40M
), 2);
141 } else if (AR_SREV_9340(ah
)) {
143 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
144 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
146 ARRAY_SIZE(ar9340_1p0_mac_core
), 2);
147 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
148 ar9340_1p0_mac_postamble
,
149 ARRAY_SIZE(ar9340_1p0_mac_postamble
), 5);
152 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], NULL
, 0, 0);
153 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
154 ar9340_1p0_baseband_core
,
155 ARRAY_SIZE(ar9340_1p0_baseband_core
), 2);
156 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
157 ar9340_1p0_baseband_postamble
,
158 ARRAY_SIZE(ar9340_1p0_baseband_postamble
), 5);
161 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
162 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
163 ar9340_1p0_radio_core
,
164 ARRAY_SIZE(ar9340_1p0_radio_core
), 2);
165 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
],
166 ar9340_1p0_radio_postamble
,
167 ARRAY_SIZE(ar9340_1p0_radio_postamble
), 5);
170 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
171 ar9340_1p0_soc_preamble
,
172 ARRAY_SIZE(ar9340_1p0_soc_preamble
), 2);
173 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
174 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
],
175 ar9340_1p0_soc_postamble
,
176 ARRAY_SIZE(ar9340_1p0_soc_postamble
), 5);
179 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
180 ar9340Common_wo_xlna_rx_gain_table_1p0
,
181 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0
),
183 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
184 ar9340Modes_high_ob_db_tx_gain_table_1p0
,
185 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0
),
188 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
189 ar9340Modes_fast_clock_1p0
,
190 ARRAY_SIZE(ar9340Modes_fast_clock_1p0
),
193 INIT_INI_ARRAY(&ah
->iniModesAdditional_40M
,
194 ar9340_1p0_radio_core_40M
,
195 ARRAY_SIZE(ar9340_1p0_radio_core_40M
),
197 } else if (AR_SREV_9485_11(ah
)) {
199 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
200 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
202 ARRAY_SIZE(ar9485_1_1_mac_core
), 2);
203 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
204 ar9485_1_1_mac_postamble
,
205 ARRAY_SIZE(ar9485_1_1_mac_postamble
), 5);
208 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], ar9485_1_1
,
209 ARRAY_SIZE(ar9485_1_1
), 2);
210 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
211 ar9485_1_1_baseband_core
,
212 ARRAY_SIZE(ar9485_1_1_baseband_core
), 2);
213 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
214 ar9485_1_1_baseband_postamble
,
215 ARRAY_SIZE(ar9485_1_1_baseband_postamble
), 5);
218 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
219 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
220 ar9485_1_1_radio_core
,
221 ARRAY_SIZE(ar9485_1_1_radio_core
), 2);
222 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
],
223 ar9485_1_1_radio_postamble
,
224 ARRAY_SIZE(ar9485_1_1_radio_postamble
), 2);
227 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
228 ar9485_1_1_soc_preamble
,
229 ARRAY_SIZE(ar9485_1_1_soc_preamble
), 2);
230 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
231 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
], NULL
, 0, 0);
234 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
235 ar9485Common_wo_xlna_rx_gain_1_1
,
236 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1
), 2);
237 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
238 ar9485_modes_lowest_ob_db_tx_gain_1_1
,
239 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1
),
242 /* Load PCIE SERDES settings from INI */
246 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
247 ar9485_1_1_pcie_phy_clkreq_disable_L1
,
248 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1
),
253 INIT_INI_ARRAY(&ah
->iniPcieSerdesLowPower
,
254 ar9485_1_1_pcie_phy_clkreq_disable_L1
,
255 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1
),
257 } else if (AR_SREV_9580(ah
)) {
259 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
260 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
262 ARRAY_SIZE(ar9580_1p0_mac_core
), 2);
263 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
264 ar9580_1p0_mac_postamble
,
265 ARRAY_SIZE(ar9580_1p0_mac_postamble
), 5);
268 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], NULL
, 0, 0);
269 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
270 ar9580_1p0_baseband_core
,
271 ARRAY_SIZE(ar9580_1p0_baseband_core
), 2);
272 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
273 ar9580_1p0_baseband_postamble
,
274 ARRAY_SIZE(ar9580_1p0_baseband_postamble
), 5);
277 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
278 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
279 ar9580_1p0_radio_core
,
280 ARRAY_SIZE(ar9580_1p0_radio_core
), 2);
281 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
],
282 ar9580_1p0_radio_postamble
,
283 ARRAY_SIZE(ar9580_1p0_radio_postamble
), 5);
286 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
287 ar9580_1p0_soc_preamble
,
288 ARRAY_SIZE(ar9580_1p0_soc_preamble
), 2);
289 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
290 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
],
291 ar9580_1p0_soc_postamble
,
292 ARRAY_SIZE(ar9580_1p0_soc_postamble
), 5);
295 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
296 ar9580_1p0_rx_gain_table
,
297 ARRAY_SIZE(ar9580_1p0_rx_gain_table
), 2);
298 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
299 ar9580_1p0_low_ob_db_tx_gain_table
,
300 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table
),
303 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
304 ar9580_1p0_modes_fast_clock
,
305 ARRAY_SIZE(ar9580_1p0_modes_fast_clock
),
309 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_PRE
], NULL
, 0, 0);
310 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_CORE
],
312 ARRAY_SIZE(ar9300_2p2_mac_core
), 2);
313 INIT_INI_ARRAY(&ah
->iniMac
[ATH_INI_POST
],
314 ar9300_2p2_mac_postamble
,
315 ARRAY_SIZE(ar9300_2p2_mac_postamble
), 5);
318 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_PRE
], NULL
, 0, 0);
319 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_CORE
],
320 ar9300_2p2_baseband_core
,
321 ARRAY_SIZE(ar9300_2p2_baseband_core
), 2);
322 INIT_INI_ARRAY(&ah
->iniBB
[ATH_INI_POST
],
323 ar9300_2p2_baseband_postamble
,
324 ARRAY_SIZE(ar9300_2p2_baseband_postamble
), 5);
327 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_PRE
], NULL
, 0, 0);
328 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_CORE
],
329 ar9300_2p2_radio_core
,
330 ARRAY_SIZE(ar9300_2p2_radio_core
), 2);
331 INIT_INI_ARRAY(&ah
->iniRadio
[ATH_INI_POST
],
332 ar9300_2p2_radio_postamble
,
333 ARRAY_SIZE(ar9300_2p2_radio_postamble
), 5);
336 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_PRE
],
337 ar9300_2p2_soc_preamble
,
338 ARRAY_SIZE(ar9300_2p2_soc_preamble
), 2);
339 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_CORE
], NULL
, 0, 0);
340 INIT_INI_ARRAY(&ah
->iniSOC
[ATH_INI_POST
],
341 ar9300_2p2_soc_postamble
,
342 ARRAY_SIZE(ar9300_2p2_soc_postamble
), 5);
345 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
346 ar9300Common_rx_gain_table_2p2
,
347 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2
), 2);
348 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
349 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
,
350 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2
),
353 /* Load PCIE SERDES settings from INI */
357 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
358 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
,
359 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
),
364 INIT_INI_ARRAY(&ah
->iniPcieSerdesLowPower
,
365 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
,
366 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
),
369 /* Fast clock modal settings */
370 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
371 ar9300Modes_fast_clock_2p2
,
372 ARRAY_SIZE(ar9300Modes_fast_clock_2p2
),
377 static void ar9003_tx_gain_table_mode0(struct ath_hw
*ah
)
379 if (AR_SREV_9330_12(ah
))
380 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
381 ar9331_modes_lowest_ob_db_tx_gain_1p2
,
382 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2
),
384 else if (AR_SREV_9330_11(ah
))
385 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
386 ar9331_modes_lowest_ob_db_tx_gain_1p1
,
387 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1
),
389 else if (AR_SREV_9340(ah
))
390 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
391 ar9340Modes_lowest_ob_db_tx_gain_table_1p0
,
392 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0
),
394 else if (AR_SREV_9485_11(ah
))
395 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
396 ar9485_modes_lowest_ob_db_tx_gain_1_1
,
397 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1
),
399 else if (AR_SREV_9580(ah
))
400 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
401 ar9580_1p0_lowest_ob_db_tx_gain_table
,
402 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table
),
405 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
406 ar9300Modes_lowest_ob_db_tx_gain_table_2p2
,
407 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2
),
411 static void ar9003_tx_gain_table_mode1(struct ath_hw
*ah
)
413 if (AR_SREV_9330_12(ah
))
414 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
415 ar9331_modes_high_ob_db_tx_gain_1p2
,
416 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2
),
418 else if (AR_SREV_9330_11(ah
))
419 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
420 ar9331_modes_high_ob_db_tx_gain_1p1
,
421 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1
),
423 else if (AR_SREV_9340(ah
))
424 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
425 ar9340Modes_lowest_ob_db_tx_gain_table_1p0
,
426 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0
),
428 else if (AR_SREV_9485_11(ah
))
429 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
430 ar9485Modes_high_ob_db_tx_gain_1_1
,
431 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1
),
433 else if (AR_SREV_9580(ah
))
434 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
435 ar9580_1p0_high_ob_db_tx_gain_table
,
436 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table
),
439 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
440 ar9300Modes_high_ob_db_tx_gain_table_2p2
,
441 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2
),
445 static void ar9003_tx_gain_table_mode2(struct ath_hw
*ah
)
447 if (AR_SREV_9330_12(ah
))
448 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
449 ar9331_modes_low_ob_db_tx_gain_1p2
,
450 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2
),
452 else if (AR_SREV_9330_11(ah
))
453 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
454 ar9331_modes_low_ob_db_tx_gain_1p1
,
455 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1
),
457 else if (AR_SREV_9340(ah
))
458 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
459 ar9340Modes_lowest_ob_db_tx_gain_table_1p0
,
460 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0
),
462 else if (AR_SREV_9485_11(ah
))
463 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
464 ar9485Modes_low_ob_db_tx_gain_1_1
,
465 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1
),
467 else if (AR_SREV_9580(ah
))
468 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
469 ar9580_1p0_low_ob_db_tx_gain_table
,
470 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table
),
473 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
474 ar9300Modes_low_ob_db_tx_gain_table_2p2
,
475 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2
),
479 static void ar9003_tx_gain_table_mode3(struct ath_hw
*ah
)
481 if (AR_SREV_9330_12(ah
))
482 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
483 ar9331_modes_high_power_tx_gain_1p2
,
484 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2
),
486 else if (AR_SREV_9330_11(ah
))
487 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
488 ar9331_modes_high_power_tx_gain_1p1
,
489 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1
),
491 else if (AR_SREV_9340(ah
))
492 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
493 ar9340Modes_lowest_ob_db_tx_gain_table_1p0
,
494 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0
),
496 else if (AR_SREV_9485_11(ah
))
497 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
498 ar9485Modes_high_power_tx_gain_1_1
,
499 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1
),
501 else if (AR_SREV_9580(ah
))
502 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
503 ar9580_1p0_high_power_tx_gain_table
,
504 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table
),
507 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
508 ar9300Modes_high_power_tx_gain_table_2p2
,
509 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2
),
513 static void ar9003_tx_gain_table_apply(struct ath_hw
*ah
)
515 switch (ar9003_hw_get_tx_gain_idx(ah
)) {
518 ar9003_tx_gain_table_mode0(ah
);
521 ar9003_tx_gain_table_mode1(ah
);
524 ar9003_tx_gain_table_mode2(ah
);
527 ar9003_tx_gain_table_mode3(ah
);
532 static void ar9003_rx_gain_table_mode0(struct ath_hw
*ah
)
534 if (AR_SREV_9330_12(ah
))
535 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
536 ar9331_common_rx_gain_1p2
,
537 ARRAY_SIZE(ar9331_common_rx_gain_1p2
),
539 else if (AR_SREV_9330_11(ah
))
540 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
541 ar9331_common_rx_gain_1p1
,
542 ARRAY_SIZE(ar9331_common_rx_gain_1p1
),
544 else if (AR_SREV_9340(ah
))
545 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
546 ar9340Common_rx_gain_table_1p0
,
547 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0
),
549 else if (AR_SREV_9485_11(ah
))
550 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
551 ar9485Common_wo_xlna_rx_gain_1_1
,
552 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1
),
554 else if (AR_SREV_9580(ah
))
555 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
556 ar9580_1p0_rx_gain_table
,
557 ARRAY_SIZE(ar9580_1p0_rx_gain_table
),
560 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
561 ar9300Common_rx_gain_table_2p2
,
562 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2
),
566 static void ar9003_rx_gain_table_mode1(struct ath_hw
*ah
)
568 if (AR_SREV_9330_12(ah
))
569 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
570 ar9331_common_wo_xlna_rx_gain_1p2
,
571 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2
),
573 else if (AR_SREV_9330_11(ah
))
574 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
575 ar9331_common_wo_xlna_rx_gain_1p1
,
576 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1
),
578 else if (AR_SREV_9340(ah
))
579 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
580 ar9340Common_wo_xlna_rx_gain_table_1p0
,
581 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0
),
583 else if (AR_SREV_9485_11(ah
))
584 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
585 ar9485Common_wo_xlna_rx_gain_1_1
,
586 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1
),
588 else if (AR_SREV_9580(ah
))
589 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
590 ar9580_1p0_wo_xlna_rx_gain_table
,
591 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table
),
594 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
595 ar9300Common_wo_xlna_rx_gain_table_2p2
,
596 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2
),
600 static void ar9003_rx_gain_table_apply(struct ath_hw
*ah
)
602 switch (ar9003_hw_get_rx_gain_idx(ah
)) {
605 ar9003_rx_gain_table_mode0(ah
);
608 ar9003_rx_gain_table_mode1(ah
);
613 /* set gain table pointers according to values read from the eeprom */
614 static void ar9003_hw_init_mode_gain_regs(struct ath_hw
*ah
)
616 ar9003_tx_gain_table_apply(ah
);
617 ar9003_rx_gain_table_apply(ah
);
621 * Helper for ASPM support.
623 * Disable PLL when in L0s as well as receiver clock when in L1.
624 * This power saving option must be enabled through the SerDes.
626 * Programming the SerDes must go through the same 288 bit serial shift
627 * register as the other analog registers. Hence the 9 writes.
629 static void ar9003_hw_configpcipowersave(struct ath_hw
*ah
,
632 /* Nothing to do on restore for 11N */
633 if (!power_off
/* !restore */) {
634 /* set bit 19 to allow forcing of pcie core into L1 state */
635 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
637 /* Several PCIe massages to ensure proper behaviour */
638 if (ah
->config
.pcie_waen
)
639 REG_WRITE(ah
, AR_WA
, ah
->config
.pcie_waen
);
641 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
645 * Configire PCIE after Ini init. SERDES values now come from ini file
646 * This enables PCIe low power mode.
648 if (ah
->config
.pcieSerDesWrite
) {
650 struct ar5416IniArray
*array
;
652 array
= power_off
? &ah
->iniPcieSerdes
:
653 &ah
->iniPcieSerdesLowPower
;
655 for (i
= 0; i
< array
->ia_rows
; i
++) {
658 INI_RA(array
, i
, 1));
663 /* Sets up the AR9003 hardware familiy callbacks */
664 void ar9003_hw_attach_ops(struct ath_hw
*ah
)
666 struct ath_hw_private_ops
*priv_ops
= ath9k_hw_private_ops(ah
);
667 struct ath_hw_ops
*ops
= ath9k_hw_ops(ah
);
669 priv_ops
->init_mode_regs
= ar9003_hw_init_mode_regs
;
670 priv_ops
->init_mode_gain_regs
= ar9003_hw_init_mode_gain_regs
;
672 ops
->config_pci_powersave
= ar9003_hw_configpcipowersave
;
674 ar9003_hw_attach_phy_ops(ah
);
675 ar9003_hw_attach_calib_ops(ah
);
676 ar9003_hw_attach_mac_ops(ah
);