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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath5k / reset.c
1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 /*****************************\
23 Reset functions and helpers
24 \*****************************/
25
26 #include <asm/unaligned.h>
27
28 #include <linux/pci.h> /* To determine if a card is pci-e */
29 #include <linux/log2.h>
30 #include "ath5k.h"
31 #include "reg.h"
32 #include "base.h"
33 #include "debug.h"
34
35
36 /******************\
37 * Helper functions *
38 \******************/
39
40 /*
41 * Check if a register write has been completed
42 */
43 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
44 bool is_set)
45 {
46 int i;
47 u32 data;
48
49 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
50 data = ath5k_hw_reg_read(ah, reg);
51 if (is_set && (data & flag))
52 break;
53 else if ((data & flag) == val)
54 break;
55 udelay(15);
56 }
57
58 return (i <= 0) ? -EAGAIN : 0;
59 }
60
61
62 /*************************\
63 * Clock related functions *
64 \*************************/
65
66 /**
67 * ath5k_hw_htoclock - Translate usec to hw clock units
68 *
69 * @ah: The &struct ath5k_hw
70 * @usec: value in microseconds
71 */
72 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
73 {
74 struct ath_common *common = ath5k_hw_common(ah);
75 return usec * common->clockrate;
76 }
77
78 /**
79 * ath5k_hw_clocktoh - Translate hw clock units to usec
80 * @clock: value in hw clock units
81 */
82 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
83 {
84 struct ath_common *common = ath5k_hw_common(ah);
85 return clock / common->clockrate;
86 }
87
88 /**
89 * ath5k_hw_init_core_clock - Initialize core clock
90 *
91 * @ah The &struct ath5k_hw
92 *
93 * Initialize core clock parameters (usec, usec32, latencies etc).
94 */
95 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
96 {
97 struct ieee80211_channel *channel = ah->ah_current_channel;
98 struct ath_common *common = ath5k_hw_common(ah);
99 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
100
101 /*
102 * Set core clock frequency
103 */
104 if (channel->hw_value & CHANNEL_5GHZ)
105 clock = 40; /* 802.11a */
106 else if (channel->hw_value & CHANNEL_CCK)
107 clock = 22; /* 802.11b */
108 else
109 clock = 44; /* 802.11g */
110
111 /* Use clock multiplier for non-default
112 * bwmode */
113 switch (ah->ah_bwmode) {
114 case AR5K_BWMODE_40MHZ:
115 clock *= 2;
116 break;
117 case AR5K_BWMODE_10MHZ:
118 clock /= 2;
119 break;
120 case AR5K_BWMODE_5MHZ:
121 clock /= 4;
122 break;
123 default:
124 break;
125 }
126
127 common->clockrate = clock;
128
129 /*
130 * Set USEC parameters
131 */
132 /* Set USEC counter on PCU*/
133 usec = clock - 1;
134 usec = AR5K_REG_SM(usec, AR5K_USEC_1);
135
136 /* Set usec duration on DCU */
137 if (ah->ah_version != AR5K_AR5210)
138 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
139 AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
140 clock);
141
142 /* Set 32MHz USEC counter */
143 if ((ah->ah_radio == AR5K_RF5112) ||
144 (ah->ah_radio == AR5K_RF5413))
145 /* Remain on 40MHz clock ? */
146 sclock = 40 - 1;
147 else
148 sclock = 32 - 1;
149 sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
150
151 /*
152 * Set tx/rx latencies
153 */
154 usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
155 txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
156 rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
157
158 /*
159 * 5210 initvals don't include usec settings
160 * so we need to use magic values here for
161 * tx/rx latencies
162 */
163 if (ah->ah_version == AR5K_AR5210) {
164 /* same for turbo */
165 txlat = AR5K_INIT_TX_LATENCY_5210;
166 rxlat = AR5K_INIT_RX_LATENCY_5210;
167 }
168
169 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
170 /* 5311 has different tx/rx latency masks
171 * from 5211, since we deal 5311 the same
172 * as 5211 when setting initvals, shift
173 * values here to their proper locations
174 *
175 * Note: Initvals indicate tx/rx/ latencies
176 * are the same for turbo mode */
177 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
178 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
179 } else
180 switch (ah->ah_bwmode) {
181 case AR5K_BWMODE_10MHZ:
182 txlat = AR5K_REG_SM(txlat * 2,
183 AR5K_USEC_TX_LATENCY_5211);
184 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
185 AR5K_USEC_RX_LATENCY_5211);
186 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
187 break;
188 case AR5K_BWMODE_5MHZ:
189 txlat = AR5K_REG_SM(txlat * 4,
190 AR5K_USEC_TX_LATENCY_5211);
191 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
192 AR5K_USEC_RX_LATENCY_5211);
193 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
194 break;
195 case AR5K_BWMODE_40MHZ:
196 txlat = AR5K_INIT_TX_LAT_MIN;
197 rxlat = AR5K_REG_SM(rxlat / 2,
198 AR5K_USEC_RX_LATENCY_5211);
199 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
200 break;
201 default:
202 break;
203 }
204
205 usec_reg = (usec | sclock | txlat | rxlat);
206 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
207
208 /* On 5112 set tx frane to tx data start delay */
209 if (ah->ah_radio == AR5K_RF5112) {
210 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
211 AR5K_PHY_RF_CTL2_TXF2TXD_START,
212 txf2txs);
213 }
214 }
215
216 /*
217 * If there is an external 32KHz crystal available, use it
218 * as ref. clock instead of 32/40MHz clock and baseband clocks
219 * to save power during sleep or restore normal 32/40MHz
220 * operation.
221 *
222 * XXX: When operating on 32KHz certain PHY registers (27 - 31,
223 * 123 - 127) require delay on access.
224 */
225 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
226 {
227 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
228 u32 scal, spending;
229
230 /* Only set 32KHz settings if we have an external
231 * 32KHz crystal present */
232 if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
233 AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
234 enable) {
235
236 /* 1 usec/cycle */
237 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
238 /* Set up tsf increment on each cycle */
239 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
240
241 /* Set baseband sleep control registers
242 * and sleep control rate */
243 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
244
245 if ((ah->ah_radio == AR5K_RF5112) ||
246 (ah->ah_radio == AR5K_RF5413) ||
247 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
248 spending = 0x14;
249 else
250 spending = 0x18;
251 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
252
253 if ((ah->ah_radio == AR5K_RF5112) ||
254 (ah->ah_radio == AR5K_RF5413) ||
255 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
256 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
257 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
258 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
259 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
260 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
261 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
262 } else {
263 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
264 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
265 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
266 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
267 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
268 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
269 }
270
271 /* Enable sleep clock operation */
272 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
273 AR5K_PCICFG_SLEEP_CLOCK_EN);
274
275 } else {
276
277 /* Disable sleep clock operation and
278 * restore default parameters */
279 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
280 AR5K_PCICFG_SLEEP_CLOCK_EN);
281
282 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
283 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
284
285 /* Set DAC/ADC delays */
286 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
287 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
288
289 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
290 scal = AR5K_PHY_SCAL_32MHZ_2417;
291 else if (ee->ee_is_hb63)
292 scal = AR5K_PHY_SCAL_32MHZ_HB63;
293 else
294 scal = AR5K_PHY_SCAL_32MHZ;
295 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
296
297 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
298 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
299
300 if ((ah->ah_radio == AR5K_RF5112) ||
301 (ah->ah_radio == AR5K_RF5413) ||
302 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
303 spending = 0x14;
304 else
305 spending = 0x18;
306 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
307
308 /* Set up tsf increment on each cycle */
309 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
310 }
311 }
312
313
314 /*********************\
315 * Reset/Sleep control *
316 \*********************/
317
318 /*
319 * Reset chipset
320 */
321 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
322 {
323 int ret;
324 u32 mask = val ? val : ~0U;
325
326 /* Read-and-clear RX Descriptor Pointer*/
327 ath5k_hw_reg_read(ah, AR5K_RXDP);
328
329 /*
330 * Reset the device and wait until success
331 */
332 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
333
334 /* Wait at least 128 PCI clocks */
335 udelay(15);
336
337 if (ah->ah_version == AR5K_AR5210) {
338 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
339 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
340 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
341 | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
342 } else {
343 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
344 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
345 }
346
347 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
348
349 /*
350 * Reset configuration register (for hw byte-swap). Note that this
351 * is only set for big endian. We do the necessary magic in
352 * AR5K_INIT_CFG.
353 */
354 if ((val & AR5K_RESET_CTL_PCU) == 0)
355 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
356
357 return ret;
358 }
359
360 /*
361 * Sleep control
362 */
363 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
364 bool set_chip, u16 sleep_duration)
365 {
366 unsigned int i;
367 u32 staid, data;
368
369 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
370
371 switch (mode) {
372 case AR5K_PM_AUTO:
373 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
374 /* fallthrough */
375 case AR5K_PM_NETWORK_SLEEP:
376 if (set_chip)
377 ath5k_hw_reg_write(ah,
378 AR5K_SLEEP_CTL_SLE_ALLOW |
379 sleep_duration,
380 AR5K_SLEEP_CTL);
381
382 staid |= AR5K_STA_ID1_PWR_SV;
383 break;
384
385 case AR5K_PM_FULL_SLEEP:
386 if (set_chip)
387 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
388 AR5K_SLEEP_CTL);
389
390 staid |= AR5K_STA_ID1_PWR_SV;
391 break;
392
393 case AR5K_PM_AWAKE:
394
395 staid &= ~AR5K_STA_ID1_PWR_SV;
396
397 if (!set_chip)
398 goto commit;
399
400 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
401
402 /* If card is down we 'll get 0xffff... so we
403 * need to clean this up before we write the register
404 */
405 if (data & 0xffc00000)
406 data = 0;
407 else
408 /* Preserve sleep duration etc */
409 data = data & ~AR5K_SLEEP_CTL_SLE;
410
411 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
412 AR5K_SLEEP_CTL);
413 udelay(15);
414
415 for (i = 200; i > 0; i--) {
416 /* Check if the chip did wake up */
417 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
418 AR5K_PCICFG_SPWR_DN) == 0)
419 break;
420
421 /* Wait a bit and retry */
422 udelay(50);
423 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
424 AR5K_SLEEP_CTL);
425 }
426
427 /* Fail if the chip didn't wake up */
428 if (i == 0)
429 return -EIO;
430
431 break;
432
433 default:
434 return -EINVAL;
435 }
436
437 commit:
438 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
439
440 return 0;
441 }
442
443 /*
444 * Put device on hold
445 *
446 * Put MAC and Baseband on warm reset and
447 * keep that state (don't clean sleep control
448 * register). After this MAC and Baseband are
449 * disabled and a full reset is needed to come
450 * back. This way we save as much power as possible
451 * without putting the card on full sleep.
452 */
453 int ath5k_hw_on_hold(struct ath5k_hw *ah)
454 {
455 struct pci_dev *pdev = ah->ah_sc->pdev;
456 u32 bus_flags;
457 int ret;
458
459 /* Make sure device is awake */
460 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
461 if (ret) {
462 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
463 return ret;
464 }
465
466 /*
467 * Put chipset on warm reset...
468 *
469 * Note: putting PCI core on warm reset on PCI-E cards
470 * results card to hang and always return 0xffff... so
471 * we ingore that flag for PCI-E cards. On PCI cards
472 * this flag gets cleared after 64 PCI clocks.
473 */
474 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
475
476 if (ah->ah_version == AR5K_AR5210) {
477 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
478 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
479 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
480 mdelay(2);
481 } else {
482 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
483 AR5K_RESET_CTL_BASEBAND | bus_flags);
484 }
485
486 if (ret) {
487 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
488 return -EIO;
489 }
490
491 /* ...wakeup again!*/
492 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
493 if (ret) {
494 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
495 return ret;
496 }
497
498 return ret;
499 }
500
501 /*
502 * Bring up MAC + PHY Chips and program PLL
503 */
504 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
505 {
506 struct pci_dev *pdev = ah->ah_sc->pdev;
507 u32 turbo, mode, clock, bus_flags;
508 int ret;
509
510 turbo = 0;
511 mode = 0;
512 clock = 0;
513
514 /* Wakeup the device */
515 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
516 if (ret) {
517 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
518 return ret;
519 }
520
521 /*
522 * Put chipset on warm reset...
523 *
524 * Note: putting PCI core on warm reset on PCI-E cards
525 * results card to hang and always return 0xffff... so
526 * we ingore that flag for PCI-E cards. On PCI cards
527 * this flag gets cleared after 64 PCI clocks.
528 */
529 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
530
531 if (ah->ah_version == AR5K_AR5210) {
532 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
533 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
534 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
535 mdelay(2);
536 } else {
537 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
538 AR5K_RESET_CTL_BASEBAND | bus_flags);
539 }
540
541 if (ret) {
542 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
543 return -EIO;
544 }
545
546 /* ...wakeup again!...*/
547 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
548 if (ret) {
549 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
550 return ret;
551 }
552
553 /* ...clear reset control register and pull device out of
554 * warm reset */
555 if (ath5k_hw_nic_reset(ah, 0)) {
556 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
557 return -EIO;
558 }
559
560 /* On initialization skip PLL programming since we don't have
561 * a channel / mode set yet */
562 if (initial)
563 return 0;
564
565 if (ah->ah_version != AR5K_AR5210) {
566 /*
567 * Get channel mode flags
568 */
569
570 if (ah->ah_radio >= AR5K_RF5112) {
571 mode = AR5K_PHY_MODE_RAD_RF5112;
572 clock = AR5K_PHY_PLL_RF5112;
573 } else {
574 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
575 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
576 }
577
578 if (flags & CHANNEL_2GHZ) {
579 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
580 clock |= AR5K_PHY_PLL_44MHZ;
581
582 if (flags & CHANNEL_CCK) {
583 mode |= AR5K_PHY_MODE_MOD_CCK;
584 } else if (flags & CHANNEL_OFDM) {
585 /* XXX Dynamic OFDM/CCK is not supported by the
586 * AR5211 so we set MOD_OFDM for plain g (no
587 * CCK headers) operation. We need to test
588 * this, 5211 might support ofdm-only g after
589 * all, there are also initial register values
590 * in the code for g mode (see initvals.c).
591 */
592 if (ah->ah_version == AR5K_AR5211)
593 mode |= AR5K_PHY_MODE_MOD_OFDM;
594 else
595 mode |= AR5K_PHY_MODE_MOD_DYN;
596 } else {
597 ATH5K_ERR(ah->ah_sc,
598 "invalid radio modulation mode\n");
599 return -EINVAL;
600 }
601 } else if (flags & CHANNEL_5GHZ) {
602 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
603
604 /* Different PLL setting for 5413 */
605 if (ah->ah_radio == AR5K_RF5413)
606 clock = AR5K_PHY_PLL_40MHZ_5413;
607 else
608 clock |= AR5K_PHY_PLL_40MHZ;
609
610 if (flags & CHANNEL_OFDM)
611 mode |= AR5K_PHY_MODE_MOD_OFDM;
612 else {
613 ATH5K_ERR(ah->ah_sc,
614 "invalid radio modulation mode\n");
615 return -EINVAL;
616 }
617 } else {
618 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
619 return -EINVAL;
620 }
621
622 /*XXX: Can bwmode be used with dynamic mode ?
623 * (I don't think it supports 44MHz) */
624 /* On 2425 initvals TURBO_SHORT is not pressent */
625 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
626 turbo = AR5K_PHY_TURBO_MODE |
627 (ah->ah_radio == AR5K_RF2425) ? 0 :
628 AR5K_PHY_TURBO_SHORT;
629 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
630 if (ah->ah_radio == AR5K_RF5413) {
631 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
632 AR5K_PHY_MODE_HALF_RATE :
633 AR5K_PHY_MODE_QUARTER_RATE;
634 } else if (ah->ah_version == AR5K_AR5212) {
635 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
636 AR5K_PHY_PLL_HALF_RATE :
637 AR5K_PHY_PLL_QUARTER_RATE;
638 }
639 }
640
641 } else { /* Reset the device */
642
643 /* ...enable Atheros turbo mode if requested */
644 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
645 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
646 AR5K_PHY_TURBO);
647 }
648
649 if (ah->ah_version != AR5K_AR5210) {
650
651 /* ...update PLL if needed */
652 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
653 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
654 udelay(300);
655 }
656
657 /* ...set the PHY operating mode */
658 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
659 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
660 }
661
662 return 0;
663 }
664
665
666 /**************************************\
667 * Post-initvals register modifications *
668 \**************************************/
669
670 /* TODO: Half/Quarter rate */
671 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
672 struct ieee80211_channel *channel)
673 {
674 if (ah->ah_version == AR5K_AR5212 &&
675 ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
676
677 /* Setup ADC control */
678 ath5k_hw_reg_write(ah,
679 (AR5K_REG_SM(2,
680 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
681 AR5K_REG_SM(2,
682 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
683 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
684 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
685 AR5K_PHY_ADC_CTL);
686
687
688
689 /* Disable barker RSSI threshold */
690 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
691 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
692
693 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
694 AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
695
696 /* Set the mute mask */
697 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
698 }
699
700 /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
701 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
702 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
703
704 /* Enable DCU double buffering */
705 if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
706 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
707 AR5K_TXCFG_DCU_DBL_BUF_DIS);
708
709 /* Set fast ADC */
710 if ((ah->ah_radio == AR5K_RF5413) ||
711 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
712 u32 fast_adc = true;
713
714 if (channel->center_freq == 2462 ||
715 channel->center_freq == 2467)
716 fast_adc = 0;
717
718 /* Only update if needed */
719 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
720 ath5k_hw_reg_write(ah, fast_adc,
721 AR5K_PHY_FAST_ADC);
722 }
723
724 /* Fix for first revision of the RF5112 RF chipset */
725 if (ah->ah_radio == AR5K_RF5112 &&
726 ah->ah_radio_5ghz_revision <
727 AR5K_SREV_RAD_5112A) {
728 u32 data;
729 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
730 AR5K_PHY_CCKTXCTL);
731 if (channel->hw_value & CHANNEL_5GHZ)
732 data = 0xffb81020;
733 else
734 data = 0xffb80d20;
735 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
736 }
737
738 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
739 /* Clear QCU/DCU clock gating register */
740 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
741 /* Set DAC/ADC delays */
742 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
743 AR5K_PHY_SCAL);
744 /* Enable PCU FIFO corruption ECO */
745 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
746 AR5K_DIAG_SW_ECO_ENABLE);
747 }
748
749 if (ah->ah_bwmode) {
750 /* Increase PHY switch and AGC settling time
751 * on turbo mode (ath5k_hw_commit_eeprom_settings
752 * will override settling time if available) */
753 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
754
755 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
756 AR5K_PHY_SETTLING_AGC,
757 AR5K_AGC_SETTLING_TURBO);
758
759 /* XXX: Initvals indicate we only increase
760 * switch time on AR5212, 5211 and 5210
761 * only change agc time (bug?) */
762 if (ah->ah_version == AR5K_AR5212)
763 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
764 AR5K_PHY_SETTLING_SWITCH,
765 AR5K_SWITCH_SETTLING_TURBO);
766
767 if (ah->ah_version == AR5K_AR5210) {
768 /* Set Frame Control Register */
769 ath5k_hw_reg_write(ah,
770 (AR5K_PHY_FRAME_CTL_INI |
771 AR5K_PHY_TURBO_MODE |
772 AR5K_PHY_TURBO_SHORT | 0x2020),
773 AR5K_PHY_FRAME_CTL_5210);
774 }
775 /* On 5413 PHY force window length for half/quarter rate*/
776 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
777 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
778 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
779 AR5K_PHY_FRAME_CTL_WIN_LEN,
780 3);
781 }
782 } else if (ah->ah_version == AR5K_AR5210) {
783 /* Set Frame Control Register for normal operation */
784 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
785 AR5K_PHY_FRAME_CTL_5210);
786 }
787 }
788
789 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
790 struct ieee80211_channel *channel, u8 ee_mode)
791 {
792 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
793 s16 cck_ofdm_pwr_delta;
794
795 /* TODO: Add support for AR5210 EEPROM */
796 if (ah->ah_version == AR5K_AR5210)
797 return;
798
799 /* Adjust power delta for channel 14 */
800 if (channel->center_freq == 2484)
801 cck_ofdm_pwr_delta =
802 ((ee->ee_cck_ofdm_power_delta -
803 ee->ee_scaled_cck_delta) * 2) / 10;
804 else
805 cck_ofdm_pwr_delta =
806 (ee->ee_cck_ofdm_power_delta * 2) / 10;
807
808 /* Set CCK to OFDM power delta on tx power
809 * adjustment register */
810 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
811 if (channel->hw_value == CHANNEL_G)
812 ath5k_hw_reg_write(ah,
813 AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
814 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
815 AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
816 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
817 AR5K_PHY_TX_PWR_ADJ);
818 else
819 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
820 } else {
821 /* For older revs we scale power on sw during tx power
822 * setup */
823 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
824 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
825 ee->ee_cck_ofdm_gain_delta;
826 }
827
828 /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
829 * too */
830 ath5k_hw_set_antenna_switch(ah, ee_mode);
831
832 /* Noise floor threshold */
833 ath5k_hw_reg_write(ah,
834 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
835 AR5K_PHY_NFTHRES);
836
837 if ((channel->hw_value & CHANNEL_TURBO) &&
838 (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
839 /* Switch settling time (Turbo) */
840 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
841 AR5K_PHY_SETTLING_SWITCH,
842 ee->ee_switch_settling_turbo[ee_mode]);
843
844 /* Tx/Rx attenuation (Turbo) */
845 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
846 AR5K_PHY_GAIN_TXRX_ATTEN,
847 ee->ee_atn_tx_rx_turbo[ee_mode]);
848
849 /* ADC/PGA desired size (Turbo) */
850 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
851 AR5K_PHY_DESIRED_SIZE_ADC,
852 ee->ee_adc_desired_size_turbo[ee_mode]);
853
854 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
855 AR5K_PHY_DESIRED_SIZE_PGA,
856 ee->ee_pga_desired_size_turbo[ee_mode]);
857
858 /* Tx/Rx margin (Turbo) */
859 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
860 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
861 ee->ee_margin_tx_rx_turbo[ee_mode]);
862
863 } else {
864 /* Switch settling time */
865 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
866 AR5K_PHY_SETTLING_SWITCH,
867 ee->ee_switch_settling[ee_mode]);
868
869 /* Tx/Rx attenuation */
870 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
871 AR5K_PHY_GAIN_TXRX_ATTEN,
872 ee->ee_atn_tx_rx[ee_mode]);
873
874 /* ADC/PGA desired size */
875 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
876 AR5K_PHY_DESIRED_SIZE_ADC,
877 ee->ee_adc_desired_size[ee_mode]);
878
879 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
880 AR5K_PHY_DESIRED_SIZE_PGA,
881 ee->ee_pga_desired_size[ee_mode]);
882
883 /* Tx/Rx margin */
884 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
885 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
886 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
887 ee->ee_margin_tx_rx[ee_mode]);
888 }
889
890 /* XPA delays */
891 ath5k_hw_reg_write(ah,
892 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
893 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
894 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
895 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
896
897 /* XLNA delay */
898 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
899 AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
900 ee->ee_tx_end2xlna_enable[ee_mode]);
901
902 /* Thresh64 (ANI) */
903 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
904 AR5K_PHY_NF_THRESH62,
905 ee->ee_thr_62[ee_mode]);
906
907 /* False detect backoff for channels
908 * that have spur noise. Write the new
909 * cyclic power RSSI threshold. */
910 if (ath5k_hw_chan_has_spur_noise(ah, channel))
911 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
912 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
913 AR5K_INIT_CYCRSSI_THR1 +
914 ee->ee_false_detect[ee_mode]);
915 else
916 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
917 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
918 AR5K_INIT_CYCRSSI_THR1);
919
920 /* I/Q correction (set enable bit last to match HAL sources) */
921 /* TODO: Per channel i/q infos ? */
922 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
923 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
924 ee->ee_i_cal[ee_mode]);
925 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
926 ee->ee_q_cal[ee_mode]);
927 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
928 }
929
930 /* Heavy clipping -disable for now */
931 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
932 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
933 }
934
935
936 /*********************\
937 * Main reset function *
938 \*********************/
939
940 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
941 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
942 {
943 struct ath_common *common = ath5k_hw_common(ah);
944 u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
945 u8 mode, freq, ee_mode;
946 int i, ret;
947
948 ee_mode = 0;
949 staid1_flags = 0;
950 tsf_up = 0;
951 tsf_lo = 0;
952 freq = 0;
953 mode = 0;
954
955 /*
956 * Sanity check for fast flag
957 * Fast channel change only available
958 * on AR2413/AR5413.
959 */
960 if (fast && (ah->ah_radio != AR5K_RF2413) &&
961 (ah->ah_radio != AR5K_RF5413))
962 fast = 0;
963
964 /* Disable sleep clock operation
965 * to avoid register access delay on certain
966 * PHY registers */
967 if (ah->ah_version == AR5K_AR5212)
968 ath5k_hw_set_sleep_clock(ah, false);
969
970 /*
971 * Stop PCU
972 */
973 ath5k_hw_stop_rx_pcu(ah);
974
975 /*
976 * Stop DMA
977 *
978 * Note: If DMA didn't stop continue
979 * since only a reset will fix it.
980 */
981 ret = ath5k_hw_dma_stop(ah);
982
983 /* RF Bus grant won't work if we have pending
984 * frames */
985 if (ret && fast) {
986 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
987 "DMA didn't stop, falling back to normal reset\n");
988 fast = 0;
989 /* Non fatal, just continue with
990 * normal reset */
991 ret = 0;
992 }
993
994 switch (channel->hw_value & CHANNEL_MODES) {
995 case CHANNEL_A:
996 mode = AR5K_MODE_11A;
997 freq = AR5K_INI_RFGAIN_5GHZ;
998 ee_mode = AR5K_EEPROM_MODE_11A;
999 break;
1000 case CHANNEL_G:
1001
1002 if (ah->ah_version <= AR5K_AR5211) {
1003 ATH5K_ERR(ah->ah_sc,
1004 "G mode not available on 5210/5211");
1005 return -EINVAL;
1006 }
1007
1008 mode = AR5K_MODE_11G;
1009 freq = AR5K_INI_RFGAIN_2GHZ;
1010 ee_mode = AR5K_EEPROM_MODE_11G;
1011 break;
1012 case CHANNEL_B:
1013
1014 if (ah->ah_version < AR5K_AR5211) {
1015 ATH5K_ERR(ah->ah_sc,
1016 "B mode not available on 5210");
1017 return -EINVAL;
1018 }
1019
1020 mode = AR5K_MODE_11B;
1021 freq = AR5K_INI_RFGAIN_2GHZ;
1022 ee_mode = AR5K_EEPROM_MODE_11B;
1023 break;
1024 case CHANNEL_T:
1025 mode = AR5K_MODE_11A_TURBO;
1026 freq = AR5K_INI_RFGAIN_5GHZ;
1027 ee_mode = AR5K_EEPROM_MODE_11A;
1028 break;
1029 case CHANNEL_TG:
1030 if (ah->ah_version == AR5K_AR5211) {
1031 ATH5K_ERR(ah->ah_sc,
1032 "TurboG mode not available on 5211");
1033 return -EINVAL;
1034 }
1035 mode = AR5K_MODE_11G_TURBO;
1036 freq = AR5K_INI_RFGAIN_2GHZ;
1037 ee_mode = AR5K_EEPROM_MODE_11G;
1038 break;
1039 case CHANNEL_XR:
1040 if (ah->ah_version == AR5K_AR5211) {
1041 ATH5K_ERR(ah->ah_sc,
1042 "XR mode not available on 5211");
1043 return -EINVAL;
1044 }
1045 mode = AR5K_MODE_XR;
1046 freq = AR5K_INI_RFGAIN_5GHZ;
1047 ee_mode = AR5K_EEPROM_MODE_11A;
1048 break;
1049 default:
1050 ATH5K_ERR(ah->ah_sc,
1051 "invalid channel: %d\n", channel->center_freq);
1052 return -EINVAL;
1053 }
1054
1055 /*
1056 * If driver requested fast channel change and DMA has stopped
1057 * go on. If it fails continue with a normal reset.
1058 */
1059 if (fast) {
1060 ret = ath5k_hw_phy_init(ah, channel, mode,
1061 ee_mode, freq, true);
1062 if (ret) {
1063 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1064 "fast chan change failed, falling back to normal reset\n");
1065 /* Non fatal, can happen eg.
1066 * on mode change */
1067 ret = 0;
1068 } else
1069 return 0;
1070 }
1071
1072 /*
1073 * Save some registers before a reset
1074 */
1075 if (ah->ah_version != AR5K_AR5210) {
1076 /*
1077 * Save frame sequence count
1078 * For revs. after Oahu, only save
1079 * seq num for DCU 0 (Global seq num)
1080 */
1081 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1082
1083 for (i = 0; i < 10; i++)
1084 s_seq[i] = ath5k_hw_reg_read(ah,
1085 AR5K_QUEUE_DCU_SEQNUM(i));
1086
1087 } else {
1088 s_seq[0] = ath5k_hw_reg_read(ah,
1089 AR5K_QUEUE_DCU_SEQNUM(0));
1090 }
1091
1092 /* TSF accelerates on AR5211 during reset
1093 * As a workaround save it here and restore
1094 * it later so that it's back in time after
1095 * reset. This way it'll get re-synced on the
1096 * next beacon without breaking ad-hoc.
1097 *
1098 * On AR5212 TSF is almost preserved across a
1099 * reset so it stays back in time anyway and
1100 * we don't have to save/restore it.
1101 *
1102 * XXX: Since this breaks power saving we have
1103 * to disable power saving until we receive the
1104 * next beacon, so we can resync beacon timers */
1105 if (ah->ah_version == AR5K_AR5211) {
1106 tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1107 tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1108 }
1109 }
1110
1111
1112 /*GPIOs*/
1113 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1114 AR5K_PCICFG_LEDSTATE;
1115 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1116 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1117
1118 /* AR5K_STA_ID1 flags, only preserve antenna
1119 * settings and ack/cts rate mode */
1120 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
1121 (AR5K_STA_ID1_DEFAULT_ANTENNA |
1122 AR5K_STA_ID1_DESC_ANTENNA |
1123 AR5K_STA_ID1_RTS_DEF_ANTENNA |
1124 AR5K_STA_ID1_ACKCTS_6MB |
1125 AR5K_STA_ID1_BASE_RATE_11B |
1126 AR5K_STA_ID1_SELFGEN_DEF_ANT);
1127
1128 /*
1129 * Since we are going to write rf buffer
1130 * check if we have any pending gain_F
1131 * optimization settings
1132 */
1133 if (ah->ah_version == AR5K_AR5212 &&
1134 (ah->ah_radio <= AR5K_RF5112)) {
1135 if (!fast && ah->ah_rf_banks != NULL)
1136 ath5k_hw_gainf_calibrate(ah);
1137 }
1138
1139 /* Wakeup the device */
1140 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1141 if (ret)
1142 return ret;
1143
1144 /* PHY access enable */
1145 if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1146 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1147 else
1148 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1149 AR5K_PHY(0));
1150
1151 /* Write initial settings */
1152 ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1153 if (ret)
1154 return ret;
1155
1156 /* Initialize core clock settings */
1157 ath5k_hw_init_core_clock(ah);
1158
1159 /*
1160 * Tweak initval settings for revised
1161 * chipsets and add some more config
1162 * bits
1163 */
1164 ath5k_hw_tweak_initval_settings(ah, channel);
1165
1166 /* Commit values from EEPROM */
1167 ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
1168
1169
1170 /*
1171 * Restore saved values
1172 */
1173
1174 /* Seqnum, TSF */
1175 if (ah->ah_version != AR5K_AR5210) {
1176 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1177 for (i = 0; i < 10; i++)
1178 ath5k_hw_reg_write(ah, s_seq[i],
1179 AR5K_QUEUE_DCU_SEQNUM(i));
1180 } else {
1181 ath5k_hw_reg_write(ah, s_seq[0],
1182 AR5K_QUEUE_DCU_SEQNUM(0));
1183 }
1184
1185 if (ah->ah_version == AR5K_AR5211) {
1186 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1187 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1188 }
1189 }
1190
1191 /* Ledstate */
1192 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1193
1194 /* Gpio settings */
1195 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1196 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1197
1198 /* Restore sta_id flags and preserve our mac address*/
1199 ath5k_hw_reg_write(ah,
1200 get_unaligned_le32(common->macaddr),
1201 AR5K_STA_ID0);
1202 ath5k_hw_reg_write(ah,
1203 staid1_flags | get_unaligned_le16(common->macaddr + 4),
1204 AR5K_STA_ID1);
1205
1206
1207 /*
1208 * Initialize PCU
1209 */
1210 ath5k_hw_pcu_init(ah, op_mode, mode);
1211
1212 /*
1213 * Initialize PHY
1214 */
1215 ret = ath5k_hw_phy_init(ah, channel, mode, ee_mode, freq, false);
1216 if (ret) {
1217 ATH5K_ERR(ah->ah_sc,
1218 "failed to initialize PHY (%i) !\n", ret);
1219 return ret;
1220 }
1221
1222 /*
1223 * Configure QCUs/DCUs
1224 */
1225 ret = ath5k_hw_init_queues(ah);
1226 if (ret)
1227 return ret;
1228
1229
1230 /*
1231 * Initialize DMA/Interrupts
1232 */
1233 ath5k_hw_dma_init(ah);
1234
1235
1236 /* Enable 32KHz clock function for AR5212+ chips
1237 * Set clocks to 32KHz operation and use an
1238 * external 32KHz crystal when sleeping if one
1239 * exists */
1240 if (ah->ah_version == AR5K_AR5212 &&
1241 op_mode != NL80211_IFTYPE_AP)
1242 ath5k_hw_set_sleep_clock(ah, true);
1243
1244 /*
1245 * Disable beacons and reset the TSF
1246 */
1247 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1248 ath5k_hw_reset_tsf(ah);
1249 return 0;
1250 }
kernel source for telekom puls (alcatel/mediatek)