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ath5k: Remove unused sc->curmode
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
52 #include <linux/slab.h>
53 #include <linux/etherdevice.h>
54
55 #include <net/ieee80211_radiotap.h>
56
57 #include <asm/unaligned.h>
58
59 #include "base.h"
60 #include "reg.h"
61 #include "debug.h"
62 #include "ani.h"
63
64 int ath5k_modparam_nohwcrypt;
65 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
66 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67
68 static int modparam_all_channels;
69 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
70 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
72 /* Module info */
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 static int ath5k_init(struct ieee80211_hw *hw);
80 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
81 bool skip_pcu);
82 int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
83 void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
84
85 /* Known SREVs */
86 static const struct ath5k_srev_name srev_names[] = {
87 #ifdef CONFIG_ATHEROS_AR231X
88 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
89 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
90 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
91 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
92 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
93 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
94 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
95 #else
96 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
97 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
98 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
99 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
100 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
101 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
102 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
103 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
104 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
105 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
106 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
107 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
108 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
109 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
110 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
111 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
112 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
113 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
114 #endif
115 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
116 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
117 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
118 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
119 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
120 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
121 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
122 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
123 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
124 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
125 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
126 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
127 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
128 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
129 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
130 #ifdef CONFIG_ATHEROS_AR231X
131 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
132 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
133 #endif
134 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
135 };
136
137 static const struct ieee80211_rate ath5k_rates[] = {
138 { .bitrate = 10,
139 .hw_value = ATH5K_RATE_CODE_1M, },
140 { .bitrate = 20,
141 .hw_value = ATH5K_RATE_CODE_2M,
142 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
143 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
144 { .bitrate = 55,
145 .hw_value = ATH5K_RATE_CODE_5_5M,
146 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 110,
149 .hw_value = ATH5K_RATE_CODE_11M,
150 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 60,
153 .hw_value = ATH5K_RATE_CODE_6M,
154 .flags = 0 },
155 { .bitrate = 90,
156 .hw_value = ATH5K_RATE_CODE_9M,
157 .flags = 0 },
158 { .bitrate = 120,
159 .hw_value = ATH5K_RATE_CODE_12M,
160 .flags = 0 },
161 { .bitrate = 180,
162 .hw_value = ATH5K_RATE_CODE_18M,
163 .flags = 0 },
164 { .bitrate = 240,
165 .hw_value = ATH5K_RATE_CODE_24M,
166 .flags = 0 },
167 { .bitrate = 360,
168 .hw_value = ATH5K_RATE_CODE_36M,
169 .flags = 0 },
170 { .bitrate = 480,
171 .hw_value = ATH5K_RATE_CODE_48M,
172 .flags = 0 },
173 { .bitrate = 540,
174 .hw_value = ATH5K_RATE_CODE_54M,
175 .flags = 0 },
176 /* XR missing */
177 };
178
179 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
180 {
181 u64 tsf = ath5k_hw_get_tsf64(ah);
182
183 if ((tsf & 0x7fff) < rstamp)
184 tsf -= 0x8000;
185
186 return (tsf & ~0x7fff) | rstamp;
187 }
188
189 const char *
190 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
191 {
192 const char *name = "xxxxx";
193 unsigned int i;
194
195 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
196 if (srev_names[i].sr_type != type)
197 continue;
198
199 if ((val & 0xf0) == srev_names[i].sr_val)
200 name = srev_names[i].sr_name;
201
202 if ((val & 0xff) == srev_names[i].sr_val) {
203 name = srev_names[i].sr_name;
204 break;
205 }
206 }
207
208 return name;
209 }
210 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
211 {
212 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
213 return ath5k_hw_reg_read(ah, reg_offset);
214 }
215
216 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
217 {
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 ath5k_hw_reg_write(ah, val, reg_offset);
220 }
221
222 static const struct ath_ops ath5k_common_ops = {
223 .read = ath5k_ioread32,
224 .write = ath5k_iowrite32,
225 };
226
227 /***********************\
228 * Driver Initialization *
229 \***********************/
230
231 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
232 {
233 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
234 struct ath5k_softc *sc = hw->priv;
235 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
236
237 return ath_reg_notifier_apply(wiphy, request, regulatory);
238 }
239
240 /********************\
241 * Channel/mode setup *
242 \********************/
243
244 /*
245 * Returns true for the channel numbers used without all_channels modparam.
246 */
247 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
248 {
249 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
250 return true;
251
252 return /* UNII 1,2 */
253 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
254 /* midband */
255 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
256 /* UNII-3 */
257 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
258 /* 802.11j 5.030-5.080 GHz (20MHz) */
259 (chan == 8 || chan == 12 || chan == 16) ||
260 /* 802.11j 4.9GHz (20MHz) */
261 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
262 }
263
264 static unsigned int
265 ath5k_setup_channels(struct ath5k_hw *ah,
266 struct ieee80211_channel *channels,
267 unsigned int mode,
268 unsigned int max)
269 {
270 unsigned int i, count, size, chfreq, freq, ch;
271 enum ieee80211_band band;
272
273 if (!test_bit(mode, ah->ah_modes))
274 return 0;
275
276 switch (mode) {
277 case AR5K_MODE_11A:
278 /* 1..220, but 2GHz frequencies are filtered by check_channel */
279 size = 220 ;
280 chfreq = CHANNEL_5GHZ;
281 band = IEEE80211_BAND_5GHZ;
282 break;
283 case AR5K_MODE_11B:
284 case AR5K_MODE_11G:
285 size = 26;
286 chfreq = CHANNEL_2GHZ;
287 band = IEEE80211_BAND_2GHZ;
288 break;
289 default:
290 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
291 return 0;
292 }
293
294 for (i = 0, count = 0; i < size && max > 0; i++) {
295 ch = i + 1 ;
296 freq = ieee80211_channel_to_frequency(ch, band);
297
298 if (freq == 0) /* mapping failed - not a standard channel */
299 continue;
300
301 /* Check if channel is supported by the chipset */
302 if (!ath5k_channel_ok(ah, freq, chfreq))
303 continue;
304
305 if (!modparam_all_channels &&
306 !ath5k_is_standard_channel(ch, band))
307 continue;
308
309 /* Write channel info and increment counter */
310 channels[count].center_freq = freq;
311 channels[count].band = band;
312 switch (mode) {
313 case AR5K_MODE_11A:
314 case AR5K_MODE_11G:
315 channels[count].hw_value = chfreq | CHANNEL_OFDM;
316 break;
317 case AR5K_MODE_11B:
318 channels[count].hw_value = CHANNEL_B;
319 }
320
321 count++;
322 max--;
323 }
324
325 return count;
326 }
327
328 static void
329 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
330 {
331 u8 i;
332
333 for (i = 0; i < AR5K_MAX_RATES; i++)
334 sc->rate_idx[b->band][i] = -1;
335
336 for (i = 0; i < b->n_bitrates; i++) {
337 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
338 if (b->bitrates[i].hw_value_short)
339 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
340 }
341 }
342
343 static int
344 ath5k_setup_bands(struct ieee80211_hw *hw)
345 {
346 struct ath5k_softc *sc = hw->priv;
347 struct ath5k_hw *ah = sc->ah;
348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
351
352 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(sc->channels);
354
355 /* 2GHz band */
356 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
357 sband->band = IEEE80211_BAND_2GHZ;
358 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
359
360 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
365
366 sband->channels = sc->channels;
367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
368 AR5K_MODE_11G, max_c);
369
370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
373 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
378
379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
389 }
390 }
391
392 sband->channels = sc->channels;
393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
394 AR5K_MODE_11B, max_c);
395
396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
400 ath5k_setup_rate_idx(sc, sband);
401
402 /* 5GHz band, A mode */
403 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
404 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
405 sband->band = IEEE80211_BAND_5GHZ;
406 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
407
408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
411
412 sband->channels = &sc->channels[count_c];
413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
414 AR5K_MODE_11A, max_c);
415
416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
418 ath5k_setup_rate_idx(sc, sband);
419
420 ath5k_debug_dump_bands(sc);
421
422 return 0;
423 }
424
425 /*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
430 * Called with sc->lock.
431 */
432 int
433 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
434 {
435 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
436 "channel set, resetting (%u -> %u MHz)\n",
437 sc->curchan->center_freq, chan->center_freq);
438
439 /*
440 * To switch channels clear any pending DMA operations;
441 * wait long enough for the RX fifo to drain, reset the
442 * hardware at the new frequency, and then re-enable
443 * the relevant bits of the h/w.
444 */
445 return ath5k_reset(sc, chan, true);
446 }
447
448 struct ath_vif_iter_data {
449 const u8 *hw_macaddr;
450 u8 mask[ETH_ALEN];
451 u8 active_mac[ETH_ALEN]; /* first active MAC */
452 bool need_set_hw_addr;
453 bool found_active;
454 bool any_assoc;
455 enum nl80211_iftype opmode;
456 };
457
458 static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
459 {
460 struct ath_vif_iter_data *iter_data = data;
461 int i;
462 struct ath5k_vif *avf = (void *)vif->drv_priv;
463
464 if (iter_data->hw_macaddr)
465 for (i = 0; i < ETH_ALEN; i++)
466 iter_data->mask[i] &=
467 ~(iter_data->hw_macaddr[i] ^ mac[i]);
468
469 if (!iter_data->found_active) {
470 iter_data->found_active = true;
471 memcpy(iter_data->active_mac, mac, ETH_ALEN);
472 }
473
474 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
475 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
476 iter_data->need_set_hw_addr = false;
477
478 if (!iter_data->any_assoc) {
479 if (avf->assoc)
480 iter_data->any_assoc = true;
481 }
482
483 /* Calculate combined mode - when APs are active, operate in AP mode.
484 * Otherwise use the mode of the new interface. This can currently
485 * only deal with combinations of APs and STAs. Only one ad-hoc
486 * interfaces is allowed.
487 */
488 if (avf->opmode == NL80211_IFTYPE_AP)
489 iter_data->opmode = NL80211_IFTYPE_AP;
490 else
491 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
492 iter_data->opmode = avf->opmode;
493 }
494
495 void
496 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
497 struct ieee80211_vif *vif)
498 {
499 struct ath_common *common = ath5k_hw_common(sc->ah);
500 struct ath_vif_iter_data iter_data;
501
502 /*
503 * Use the hardware MAC address as reference, the hardware uses it
504 * together with the BSSID mask when matching addresses.
505 */
506 iter_data.hw_macaddr = common->macaddr;
507 memset(&iter_data.mask, 0xff, ETH_ALEN);
508 iter_data.found_active = false;
509 iter_data.need_set_hw_addr = true;
510 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
511
512 if (vif)
513 ath_vif_iter(&iter_data, vif->addr, vif);
514
515 /* Get list of all active MAC addresses */
516 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
517 &iter_data);
518 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
519
520 sc->opmode = iter_data.opmode;
521 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
522 /* Nothing active, default to station mode */
523 sc->opmode = NL80211_IFTYPE_STATION;
524
525 ath5k_hw_set_opmode(sc->ah, sc->opmode);
526 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
527 sc->opmode, ath_opmode_to_string(sc->opmode));
528
529 if (iter_data.need_set_hw_addr && iter_data.found_active)
530 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
531
532 if (ath5k_hw_hasbssidmask(sc->ah))
533 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
534 }
535
536 void
537 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
538 {
539 struct ath5k_hw *ah = sc->ah;
540 u32 rfilt;
541
542 /* configure rx filter */
543 rfilt = sc->filter_flags;
544 ath5k_hw_set_rx_filter(ah, rfilt);
545 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
546
547 ath5k_update_bssid_mask_and_opmode(sc, vif);
548 }
549
550 static inline int
551 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
552 {
553 int rix;
554
555 /* return base rate on errors */
556 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
557 "hw_rix out of bounds: %x\n", hw_rix))
558 return 0;
559
560 rix = sc->rate_idx[sc->curband->band][hw_rix];
561 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
562 rix = 0;
563
564 return rix;
565 }
566
567 /***************\
568 * Buffers setup *
569 \***************/
570
571 static
572 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
573 {
574 struct ath_common *common = ath5k_hw_common(sc->ah);
575 struct sk_buff *skb;
576
577 /*
578 * Allocate buffer with headroom_needed space for the
579 * fake physical layer header at the start.
580 */
581 skb = ath_rxbuf_alloc(common,
582 common->rx_bufsize,
583 GFP_ATOMIC);
584
585 if (!skb) {
586 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
587 common->rx_bufsize);
588 return NULL;
589 }
590
591 *skb_addr = dma_map_single(sc->dev,
592 skb->data, common->rx_bufsize,
593 DMA_FROM_DEVICE);
594
595 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
596 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
597 dev_kfree_skb(skb);
598 return NULL;
599 }
600 return skb;
601 }
602
603 static int
604 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
605 {
606 struct ath5k_hw *ah = sc->ah;
607 struct sk_buff *skb = bf->skb;
608 struct ath5k_desc *ds;
609 int ret;
610
611 if (!skb) {
612 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
613 if (!skb)
614 return -ENOMEM;
615 bf->skb = skb;
616 }
617
618 /*
619 * Setup descriptors. For receive we always terminate
620 * the descriptor list with a self-linked entry so we'll
621 * not get overrun under high load (as can happen with a
622 * 5212 when ANI processing enables PHY error frames).
623 *
624 * To ensure the last descriptor is self-linked we create
625 * each descriptor as self-linked and add it to the end. As
626 * each additional descriptor is added the previous self-linked
627 * entry is "fixed" naturally. This should be safe even
628 * if DMA is happening. When processing RX interrupts we
629 * never remove/process the last, self-linked, entry on the
630 * descriptor list. This ensures the hardware always has
631 * someplace to write a new frame.
632 */
633 ds = bf->desc;
634 ds->ds_link = bf->daddr; /* link to self */
635 ds->ds_data = bf->skbaddr;
636 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
637 if (ret) {
638 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
639 return ret;
640 }
641
642 if (sc->rxlink != NULL)
643 *sc->rxlink = bf->daddr;
644 sc->rxlink = &ds->ds_link;
645 return 0;
646 }
647
648 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
649 {
650 struct ieee80211_hdr *hdr;
651 enum ath5k_pkt_type htype;
652 __le16 fc;
653
654 hdr = (struct ieee80211_hdr *)skb->data;
655 fc = hdr->frame_control;
656
657 if (ieee80211_is_beacon(fc))
658 htype = AR5K_PKT_TYPE_BEACON;
659 else if (ieee80211_is_probe_resp(fc))
660 htype = AR5K_PKT_TYPE_PROBE_RESP;
661 else if (ieee80211_is_atim(fc))
662 htype = AR5K_PKT_TYPE_ATIM;
663 else if (ieee80211_is_pspoll(fc))
664 htype = AR5K_PKT_TYPE_PSPOLL;
665 else
666 htype = AR5K_PKT_TYPE_NORMAL;
667
668 return htype;
669 }
670
671 static int
672 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
673 struct ath5k_txq *txq, int padsize)
674 {
675 struct ath5k_hw *ah = sc->ah;
676 struct ath5k_desc *ds = bf->desc;
677 struct sk_buff *skb = bf->skb;
678 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
679 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
680 struct ieee80211_rate *rate;
681 unsigned int mrr_rate[3], mrr_tries[3];
682 int i, ret;
683 u16 hw_rate;
684 u16 cts_rate = 0;
685 u16 duration = 0;
686 u8 rc_flags;
687
688 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
689
690 /* XXX endianness */
691 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
692 DMA_TO_DEVICE);
693
694 rate = ieee80211_get_tx_rate(sc->hw, info);
695 if (!rate) {
696 ret = -EINVAL;
697 goto err_unmap;
698 }
699
700 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
701 flags |= AR5K_TXDESC_NOACK;
702
703 rc_flags = info->control.rates[0].flags;
704 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
705 rate->hw_value_short : rate->hw_value;
706
707 pktlen = skb->len;
708
709 /* FIXME: If we are in g mode and rate is a CCK rate
710 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
711 * from tx power (value is in dB units already) */
712 if (info->control.hw_key) {
713 keyidx = info->control.hw_key->hw_key_idx;
714 pktlen += info->control.hw_key->icv_len;
715 }
716 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
717 flags |= AR5K_TXDESC_RTSENA;
718 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
719 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
720 info->control.vif, pktlen, info));
721 }
722 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
723 flags |= AR5K_TXDESC_CTSENA;
724 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
725 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
726 info->control.vif, pktlen, info));
727 }
728 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
729 ieee80211_get_hdrlen_from_skb(skb), padsize,
730 get_hw_packet_type(skb),
731 (sc->power_level * 2),
732 hw_rate,
733 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
734 cts_rate, duration);
735 if (ret)
736 goto err_unmap;
737
738 memset(mrr_rate, 0, sizeof(mrr_rate));
739 memset(mrr_tries, 0, sizeof(mrr_tries));
740 for (i = 0; i < 3; i++) {
741 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
742 if (!rate)
743 break;
744
745 mrr_rate[i] = rate->hw_value;
746 mrr_tries[i] = info->control.rates[i + 1].count;
747 }
748
749 ath5k_hw_setup_mrr_tx_desc(ah, ds,
750 mrr_rate[0], mrr_tries[0],
751 mrr_rate[1], mrr_tries[1],
752 mrr_rate[2], mrr_tries[2]);
753
754 ds->ds_link = 0;
755 ds->ds_data = bf->skbaddr;
756
757 spin_lock_bh(&txq->lock);
758 list_add_tail(&bf->list, &txq->q);
759 txq->txq_len++;
760 if (txq->link == NULL) /* is this first packet? */
761 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
762 else /* no, so only link it */
763 *txq->link = bf->daddr;
764
765 txq->link = &ds->ds_link;
766 ath5k_hw_start_tx_dma(ah, txq->qnum);
767 mmiowb();
768 spin_unlock_bh(&txq->lock);
769
770 return 0;
771 err_unmap:
772 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
773 return ret;
774 }
775
776 /*******************\
777 * Descriptors setup *
778 \*******************/
779
780 static int
781 ath5k_desc_alloc(struct ath5k_softc *sc)
782 {
783 struct ath5k_desc *ds;
784 struct ath5k_buf *bf;
785 dma_addr_t da;
786 unsigned int i;
787 int ret;
788
789 /* allocate descriptors */
790 sc->desc_len = sizeof(struct ath5k_desc) *
791 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
792
793 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
794 &sc->desc_daddr, GFP_KERNEL);
795 if (sc->desc == NULL) {
796 ATH5K_ERR(sc, "can't allocate descriptors\n");
797 ret = -ENOMEM;
798 goto err;
799 }
800 ds = sc->desc;
801 da = sc->desc_daddr;
802 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
803 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
804
805 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
806 sizeof(struct ath5k_buf), GFP_KERNEL);
807 if (bf == NULL) {
808 ATH5K_ERR(sc, "can't allocate bufptr\n");
809 ret = -ENOMEM;
810 goto err_free;
811 }
812 sc->bufptr = bf;
813
814 INIT_LIST_HEAD(&sc->rxbuf);
815 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
816 bf->desc = ds;
817 bf->daddr = da;
818 list_add_tail(&bf->list, &sc->rxbuf);
819 }
820
821 INIT_LIST_HEAD(&sc->txbuf);
822 sc->txbuf_len = ATH_TXBUF;
823 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
824 da += sizeof(*ds)) {
825 bf->desc = ds;
826 bf->daddr = da;
827 list_add_tail(&bf->list, &sc->txbuf);
828 }
829
830 /* beacon buffers */
831 INIT_LIST_HEAD(&sc->bcbuf);
832 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
833 bf->desc = ds;
834 bf->daddr = da;
835 list_add_tail(&bf->list, &sc->bcbuf);
836 }
837
838 return 0;
839 err_free:
840 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
841 err:
842 sc->desc = NULL;
843 return ret;
844 }
845
846 void
847 ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
848 {
849 BUG_ON(!bf);
850 if (!bf->skb)
851 return;
852 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
853 DMA_TO_DEVICE);
854 dev_kfree_skb_any(bf->skb);
855 bf->skb = NULL;
856 bf->skbaddr = 0;
857 bf->desc->ds_data = 0;
858 }
859
860 void
861 ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
862 {
863 struct ath5k_hw *ah = sc->ah;
864 struct ath_common *common = ath5k_hw_common(ah);
865
866 BUG_ON(!bf);
867 if (!bf->skb)
868 return;
869 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
870 DMA_FROM_DEVICE);
871 dev_kfree_skb_any(bf->skb);
872 bf->skb = NULL;
873 bf->skbaddr = 0;
874 bf->desc->ds_data = 0;
875 }
876
877 static void
878 ath5k_desc_free(struct ath5k_softc *sc)
879 {
880 struct ath5k_buf *bf;
881
882 list_for_each_entry(bf, &sc->txbuf, list)
883 ath5k_txbuf_free_skb(sc, bf);
884 list_for_each_entry(bf, &sc->rxbuf, list)
885 ath5k_rxbuf_free_skb(sc, bf);
886 list_for_each_entry(bf, &sc->bcbuf, list)
887 ath5k_txbuf_free_skb(sc, bf);
888
889 /* Free memory associated with all descriptors */
890 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
891 sc->desc = NULL;
892 sc->desc_daddr = 0;
893
894 kfree(sc->bufptr);
895 sc->bufptr = NULL;
896 }
897
898
899 /**************\
900 * Queues setup *
901 \**************/
902
903 static struct ath5k_txq *
904 ath5k_txq_setup(struct ath5k_softc *sc,
905 int qtype, int subtype)
906 {
907 struct ath5k_hw *ah = sc->ah;
908 struct ath5k_txq *txq;
909 struct ath5k_txq_info qi = {
910 .tqi_subtype = subtype,
911 /* XXX: default values not correct for B and XR channels,
912 * but who cares? */
913 .tqi_aifs = AR5K_TUNE_AIFS,
914 .tqi_cw_min = AR5K_TUNE_CWMIN,
915 .tqi_cw_max = AR5K_TUNE_CWMAX
916 };
917 int qnum;
918
919 /*
920 * Enable interrupts only for EOL and DESC conditions.
921 * We mark tx descriptors to receive a DESC interrupt
922 * when a tx queue gets deep; otherwise we wait for the
923 * EOL to reap descriptors. Note that this is done to
924 * reduce interrupt load and this only defers reaping
925 * descriptors, never transmitting frames. Aside from
926 * reducing interrupts this also permits more concurrency.
927 * The only potential downside is if the tx queue backs
928 * up in which case the top half of the kernel may backup
929 * due to a lack of tx descriptors.
930 */
931 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
932 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
933 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
934 if (qnum < 0) {
935 /*
936 * NB: don't print a message, this happens
937 * normally on parts with too few tx queues
938 */
939 return ERR_PTR(qnum);
940 }
941 if (qnum >= ARRAY_SIZE(sc->txqs)) {
942 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
943 qnum, ARRAY_SIZE(sc->txqs));
944 ath5k_hw_release_tx_queue(ah, qnum);
945 return ERR_PTR(-EINVAL);
946 }
947 txq = &sc->txqs[qnum];
948 if (!txq->setup) {
949 txq->qnum = qnum;
950 txq->link = NULL;
951 INIT_LIST_HEAD(&txq->q);
952 spin_lock_init(&txq->lock);
953 txq->setup = true;
954 txq->txq_len = 0;
955 txq->txq_poll_mark = false;
956 txq->txq_stuck = 0;
957 }
958 return &sc->txqs[qnum];
959 }
960
961 static int
962 ath5k_beaconq_setup(struct ath5k_hw *ah)
963 {
964 struct ath5k_txq_info qi = {
965 /* XXX: default values not correct for B and XR channels,
966 * but who cares? */
967 .tqi_aifs = AR5K_TUNE_AIFS,
968 .tqi_cw_min = AR5K_TUNE_CWMIN,
969 .tqi_cw_max = AR5K_TUNE_CWMAX,
970 /* NB: for dynamic turbo, don't enable any other interrupts */
971 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
972 };
973
974 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
975 }
976
977 static int
978 ath5k_beaconq_config(struct ath5k_softc *sc)
979 {
980 struct ath5k_hw *ah = sc->ah;
981 struct ath5k_txq_info qi;
982 int ret;
983
984 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
985 if (ret)
986 goto err;
987
988 if (sc->opmode == NL80211_IFTYPE_AP ||
989 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
990 /*
991 * Always burst out beacon and CAB traffic
992 * (aifs = cwmin = cwmax = 0)
993 */
994 qi.tqi_aifs = 0;
995 qi.tqi_cw_min = 0;
996 qi.tqi_cw_max = 0;
997 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
998 /*
999 * Adhoc mode; backoff between 0 and (2 * cw_min).
1000 */
1001 qi.tqi_aifs = 0;
1002 qi.tqi_cw_min = 0;
1003 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1004 }
1005
1006 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1007 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1008 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1009
1010 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1011 if (ret) {
1012 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1013 "hardware queue!\n", __func__);
1014 goto err;
1015 }
1016 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1017 if (ret)
1018 goto err;
1019
1020 /* reconfigure cabq with ready time to 80% of beacon_interval */
1021 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1022 if (ret)
1023 goto err;
1024
1025 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1026 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1027 if (ret)
1028 goto err;
1029
1030 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1031 err:
1032 return ret;
1033 }
1034
1035 /**
1036 * ath5k_drain_tx_buffs - Empty tx buffers
1037 *
1038 * @sc The &struct ath5k_softc
1039 *
1040 * Empty tx buffers from all queues in preparation
1041 * of a reset or during shutdown.
1042 *
1043 * NB: this assumes output has been stopped and
1044 * we do not need to block ath5k_tx_tasklet
1045 */
1046 static void
1047 ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1048 {
1049 struct ath5k_txq *txq;
1050 struct ath5k_buf *bf, *bf0;
1051 int i;
1052
1053 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1054 if (sc->txqs[i].setup) {
1055 txq = &sc->txqs[i];
1056 spin_lock_bh(&txq->lock);
1057 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1058 ath5k_debug_printtxbuf(sc, bf);
1059
1060 ath5k_txbuf_free_skb(sc, bf);
1061
1062 spin_lock_bh(&sc->txbuflock);
1063 list_move_tail(&bf->list, &sc->txbuf);
1064 sc->txbuf_len++;
1065 txq->txq_len--;
1066 spin_unlock_bh(&sc->txbuflock);
1067 }
1068 txq->link = NULL;
1069 txq->txq_poll_mark = false;
1070 spin_unlock_bh(&txq->lock);
1071 }
1072 }
1073 }
1074
1075 static void
1076 ath5k_txq_release(struct ath5k_softc *sc)
1077 {
1078 struct ath5k_txq *txq = sc->txqs;
1079 unsigned int i;
1080
1081 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1082 if (txq->setup) {
1083 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1084 txq->setup = false;
1085 }
1086 }
1087
1088
1089 /*************\
1090 * RX Handling *
1091 \*************/
1092
1093 /*
1094 * Enable the receive h/w following a reset.
1095 */
1096 static int
1097 ath5k_rx_start(struct ath5k_softc *sc)
1098 {
1099 struct ath5k_hw *ah = sc->ah;
1100 struct ath_common *common = ath5k_hw_common(ah);
1101 struct ath5k_buf *bf;
1102 int ret;
1103
1104 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1105
1106 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1107 common->cachelsz, common->rx_bufsize);
1108
1109 spin_lock_bh(&sc->rxbuflock);
1110 sc->rxlink = NULL;
1111 list_for_each_entry(bf, &sc->rxbuf, list) {
1112 ret = ath5k_rxbuf_setup(sc, bf);
1113 if (ret != 0) {
1114 spin_unlock_bh(&sc->rxbuflock);
1115 goto err;
1116 }
1117 }
1118 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1119 ath5k_hw_set_rxdp(ah, bf->daddr);
1120 spin_unlock_bh(&sc->rxbuflock);
1121
1122 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1123 ath5k_mode_setup(sc, NULL); /* set filters, etc. */
1124 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1125
1126 return 0;
1127 err:
1128 return ret;
1129 }
1130
1131 /*
1132 * Disable the receive logic on PCU (DRU)
1133 * In preparation for a shutdown.
1134 *
1135 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1136 * does.
1137 */
1138 static void
1139 ath5k_rx_stop(struct ath5k_softc *sc)
1140 {
1141 struct ath5k_hw *ah = sc->ah;
1142
1143 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1144 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1145
1146 ath5k_debug_printrxbuffs(sc, ah);
1147 }
1148
1149 static unsigned int
1150 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1151 struct ath5k_rx_status *rs)
1152 {
1153 struct ath5k_hw *ah = sc->ah;
1154 struct ath_common *common = ath5k_hw_common(ah);
1155 struct ieee80211_hdr *hdr = (void *)skb->data;
1156 unsigned int keyix, hlen;
1157
1158 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1159 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1160 return RX_FLAG_DECRYPTED;
1161
1162 /* Apparently when a default key is used to decrypt the packet
1163 the hw does not set the index used to decrypt. In such cases
1164 get the index from the packet. */
1165 hlen = ieee80211_hdrlen(hdr->frame_control);
1166 if (ieee80211_has_protected(hdr->frame_control) &&
1167 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1168 skb->len >= hlen + 4) {
1169 keyix = skb->data[hlen + 3] >> 6;
1170
1171 if (test_bit(keyix, common->keymap))
1172 return RX_FLAG_DECRYPTED;
1173 }
1174
1175 return 0;
1176 }
1177
1178
1179 static void
1180 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1181 struct ieee80211_rx_status *rxs)
1182 {
1183 struct ath_common *common = ath5k_hw_common(sc->ah);
1184 u64 tsf, bc_tstamp;
1185 u32 hw_tu;
1186 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1187
1188 if (ieee80211_is_beacon(mgmt->frame_control) &&
1189 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1190 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1191 /*
1192 * Received an IBSS beacon with the same BSSID. Hardware *must*
1193 * have updated the local TSF. We have to work around various
1194 * hardware bugs, though...
1195 */
1196 tsf = ath5k_hw_get_tsf64(sc->ah);
1197 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1198 hw_tu = TSF_TO_TU(tsf);
1199
1200 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1201 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1202 (unsigned long long)bc_tstamp,
1203 (unsigned long long)rxs->mactime,
1204 (unsigned long long)(rxs->mactime - bc_tstamp),
1205 (unsigned long long)tsf);
1206
1207 /*
1208 * Sometimes the HW will give us a wrong tstamp in the rx
1209 * status, causing the timestamp extension to go wrong.
1210 * (This seems to happen especially with beacon frames bigger
1211 * than 78 byte (incl. FCS))
1212 * But we know that the receive timestamp must be later than the
1213 * timestamp of the beacon since HW must have synced to that.
1214 *
1215 * NOTE: here we assume mactime to be after the frame was
1216 * received, not like mac80211 which defines it at the start.
1217 */
1218 if (bc_tstamp > rxs->mactime) {
1219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1220 "fixing mactime from %llx to %llx\n",
1221 (unsigned long long)rxs->mactime,
1222 (unsigned long long)tsf);
1223 rxs->mactime = tsf;
1224 }
1225
1226 /*
1227 * Local TSF might have moved higher than our beacon timers,
1228 * in that case we have to update them to continue sending
1229 * beacons. This also takes care of synchronizing beacon sending
1230 * times with other stations.
1231 */
1232 if (hw_tu >= sc->nexttbtt)
1233 ath5k_beacon_update_timers(sc, bc_tstamp);
1234
1235 /* Check if the beacon timers are still correct, because a TSF
1236 * update might have created a window between them - for a
1237 * longer description see the comment of this function: */
1238 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1239 ath5k_beacon_update_timers(sc, bc_tstamp);
1240 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1241 "fixed beacon timers after beacon receive\n");
1242 }
1243 }
1244 }
1245
1246 static void
1247 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1248 {
1249 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1250 struct ath5k_hw *ah = sc->ah;
1251 struct ath_common *common = ath5k_hw_common(ah);
1252
1253 /* only beacons from our BSSID */
1254 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1255 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1256 return;
1257
1258 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
1259
1260 /* in IBSS mode we should keep RSSI statistics per neighbour */
1261 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1262 }
1263
1264 /*
1265 * Compute padding position. skb must contain an IEEE 802.11 frame
1266 */
1267 static int ath5k_common_padpos(struct sk_buff *skb)
1268 {
1269 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1270 __le16 frame_control = hdr->frame_control;
1271 int padpos = 24;
1272
1273 if (ieee80211_has_a4(frame_control)) {
1274 padpos += ETH_ALEN;
1275 }
1276 if (ieee80211_is_data_qos(frame_control)) {
1277 padpos += IEEE80211_QOS_CTL_LEN;
1278 }
1279
1280 return padpos;
1281 }
1282
1283 /*
1284 * This function expects an 802.11 frame and returns the number of
1285 * bytes added, or -1 if we don't have enough header room.
1286 */
1287 static int ath5k_add_padding(struct sk_buff *skb)
1288 {
1289 int padpos = ath5k_common_padpos(skb);
1290 int padsize = padpos & 3;
1291
1292 if (padsize && skb->len>padpos) {
1293
1294 if (skb_headroom(skb) < padsize)
1295 return -1;
1296
1297 skb_push(skb, padsize);
1298 memmove(skb->data, skb->data+padsize, padpos);
1299 return padsize;
1300 }
1301
1302 return 0;
1303 }
1304
1305 /*
1306 * The MAC header is padded to have 32-bit boundary if the
1307 * packet payload is non-zero. The general calculation for
1308 * padsize would take into account odd header lengths:
1309 * padsize = 4 - (hdrlen & 3); however, since only
1310 * even-length headers are used, padding can only be 0 or 2
1311 * bytes and we can optimize this a bit. We must not try to
1312 * remove padding from short control frames that do not have a
1313 * payload.
1314 *
1315 * This function expects an 802.11 frame and returns the number of
1316 * bytes removed.
1317 */
1318 static int ath5k_remove_padding(struct sk_buff *skb)
1319 {
1320 int padpos = ath5k_common_padpos(skb);
1321 int padsize = padpos & 3;
1322
1323 if (padsize && skb->len>=padpos+padsize) {
1324 memmove(skb->data + padsize, skb->data, padpos);
1325 skb_pull(skb, padsize);
1326 return padsize;
1327 }
1328
1329 return 0;
1330 }
1331
1332 static void
1333 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1334 struct ath5k_rx_status *rs)
1335 {
1336 struct ieee80211_rx_status *rxs;
1337
1338 ath5k_remove_padding(skb);
1339
1340 rxs = IEEE80211_SKB_RXCB(skb);
1341
1342 rxs->flag = 0;
1343 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1344 rxs->flag |= RX_FLAG_MMIC_ERROR;
1345
1346 /*
1347 * always extend the mac timestamp, since this information is
1348 * also needed for proper IBSS merging.
1349 *
1350 * XXX: it might be too late to do it here, since rs_tstamp is
1351 * 15bit only. that means TSF extension has to be done within
1352 * 32768usec (about 32ms). it might be necessary to move this to
1353 * the interrupt handler, like it is done in madwifi.
1354 *
1355 * Unfortunately we don't know when the hardware takes the rx
1356 * timestamp (beginning of phy frame, data frame, end of rx?).
1357 * The only thing we know is that it is hardware specific...
1358 * On AR5213 it seems the rx timestamp is at the end of the
1359 * frame, but i'm not sure.
1360 *
1361 * NOTE: mac80211 defines mactime at the beginning of the first
1362 * data symbol. Since we don't have any time references it's
1363 * impossible to comply to that. This affects IBSS merge only
1364 * right now, so it's not too bad...
1365 */
1366 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1367 rxs->flag |= RX_FLAG_TSFT;
1368
1369 rxs->freq = sc->curchan->center_freq;
1370 rxs->band = sc->curband->band;
1371
1372 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1373
1374 rxs->antenna = rs->rs_antenna;
1375
1376 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1377 sc->stats.antenna_rx[rs->rs_antenna]++;
1378 else
1379 sc->stats.antenna_rx[0]++; /* invalid */
1380
1381 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1382 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1383
1384 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1385 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1386 rxs->flag |= RX_FLAG_SHORTPRE;
1387
1388 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1389
1390 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1391
1392 /* check beacons in IBSS mode */
1393 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1394 ath5k_check_ibss_tsf(sc, skb, rxs);
1395
1396 ieee80211_rx(sc->hw, skb);
1397 }
1398
1399 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1400 *
1401 * Check if we want to further process this frame or not. Also update
1402 * statistics. Return true if we want this frame, false if not.
1403 */
1404 static bool
1405 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1406 {
1407 sc->stats.rx_all_count++;
1408 sc->stats.rx_bytes_count += rs->rs_datalen;
1409
1410 if (unlikely(rs->rs_status)) {
1411 if (rs->rs_status & AR5K_RXERR_CRC)
1412 sc->stats.rxerr_crc++;
1413 if (rs->rs_status & AR5K_RXERR_FIFO)
1414 sc->stats.rxerr_fifo++;
1415 if (rs->rs_status & AR5K_RXERR_PHY) {
1416 sc->stats.rxerr_phy++;
1417 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1418 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1419 return false;
1420 }
1421 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1422 /*
1423 * Decrypt error. If the error occurred
1424 * because there was no hardware key, then
1425 * let the frame through so the upper layers
1426 * can process it. This is necessary for 5210
1427 * parts which have no way to setup a ``clear''
1428 * key cache entry.
1429 *
1430 * XXX do key cache faulting
1431 */
1432 sc->stats.rxerr_decrypt++;
1433 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1434 !(rs->rs_status & AR5K_RXERR_CRC))
1435 return true;
1436 }
1437 if (rs->rs_status & AR5K_RXERR_MIC) {
1438 sc->stats.rxerr_mic++;
1439 return true;
1440 }
1441
1442 /* reject any frames with non-crypto errors */
1443 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1444 return false;
1445 }
1446
1447 if (unlikely(rs->rs_more)) {
1448 sc->stats.rxerr_jumbo++;
1449 return false;
1450 }
1451 return true;
1452 }
1453
1454 static void
1455 ath5k_tasklet_rx(unsigned long data)
1456 {
1457 struct ath5k_rx_status rs = {};
1458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
1460 struct ath5k_softc *sc = (void *)data;
1461 struct ath5k_hw *ah = sc->ah;
1462 struct ath_common *common = ath5k_hw_common(ah);
1463 struct ath5k_buf *bf;
1464 struct ath5k_desc *ds;
1465 int ret;
1466
1467 spin_lock(&sc->rxbuflock);
1468 if (list_empty(&sc->rxbuf)) {
1469 ATH5K_WARN(sc, "empty rx buf pool\n");
1470 goto unlock;
1471 }
1472 do {
1473 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1474 BUG_ON(bf->skb == NULL);
1475 skb = bf->skb;
1476 ds = bf->desc;
1477
1478 /* bail if HW is still using self-linked descriptor */
1479 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1480 break;
1481
1482 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1483 if (unlikely(ret == -EINPROGRESS))
1484 break;
1485 else if (unlikely(ret)) {
1486 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1487 sc->stats.rxerr_proc++;
1488 break;
1489 }
1490
1491 if (ath5k_receive_frame_ok(sc, &rs)) {
1492 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1493
1494 /*
1495 * If we can't replace bf->skb with a new skb under
1496 * memory pressure, just skip this packet
1497 */
1498 if (!next_skb)
1499 goto next;
1500
1501 dma_unmap_single(sc->dev, bf->skbaddr,
1502 common->rx_bufsize,
1503 DMA_FROM_DEVICE);
1504
1505 skb_put(skb, rs.rs_datalen);
1506
1507 ath5k_receive_frame(sc, skb, &rs);
1508
1509 bf->skb = next_skb;
1510 bf->skbaddr = next_skb_addr;
1511 }
1512 next:
1513 list_move_tail(&bf->list, &sc->rxbuf);
1514 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1515 unlock:
1516 spin_unlock(&sc->rxbuflock);
1517 }
1518
1519
1520 /*************\
1521 * TX Handling *
1522 \*************/
1523
1524 int
1525 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1526 struct ath5k_txq *txq)
1527 {
1528 struct ath5k_softc *sc = hw->priv;
1529 struct ath5k_buf *bf;
1530 unsigned long flags;
1531 int padsize;
1532
1533 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
1534
1535 /*
1536 * The hardware expects the header padded to 4 byte boundaries.
1537 * If this is not the case, we add the padding after the header.
1538 */
1539 padsize = ath5k_add_padding(skb);
1540 if (padsize < 0) {
1541 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1542 " headroom to pad");
1543 goto drop_packet;
1544 }
1545
1546 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1547 ieee80211_stop_queue(hw, txq->qnum);
1548
1549 spin_lock_irqsave(&sc->txbuflock, flags);
1550 if (list_empty(&sc->txbuf)) {
1551 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1552 spin_unlock_irqrestore(&sc->txbuflock, flags);
1553 ieee80211_stop_queues(hw);
1554 goto drop_packet;
1555 }
1556 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1557 list_del(&bf->list);
1558 sc->txbuf_len--;
1559 if (list_empty(&sc->txbuf))
1560 ieee80211_stop_queues(hw);
1561 spin_unlock_irqrestore(&sc->txbuflock, flags);
1562
1563 bf->skb = skb;
1564
1565 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1566 bf->skb = NULL;
1567 spin_lock_irqsave(&sc->txbuflock, flags);
1568 list_add_tail(&bf->list, &sc->txbuf);
1569 sc->txbuf_len++;
1570 spin_unlock_irqrestore(&sc->txbuflock, flags);
1571 goto drop_packet;
1572 }
1573 return NETDEV_TX_OK;
1574
1575 drop_packet:
1576 dev_kfree_skb_any(skb);
1577 return NETDEV_TX_OK;
1578 }
1579
1580 static void
1581 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1582 struct ath5k_tx_status *ts)
1583 {
1584 struct ieee80211_tx_info *info;
1585 int i;
1586
1587 sc->stats.tx_all_count++;
1588 sc->stats.tx_bytes_count += skb->len;
1589 info = IEEE80211_SKB_CB(skb);
1590
1591 ieee80211_tx_info_clear_status(info);
1592 for (i = 0; i < 4; i++) {
1593 struct ieee80211_tx_rate *r =
1594 &info->status.rates[i];
1595
1596 if (ts->ts_rate[i]) {
1597 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1598 r->count = ts->ts_retry[i];
1599 } else {
1600 r->idx = -1;
1601 r->count = 0;
1602 }
1603 }
1604
1605 /* count the successful attempt as well */
1606 info->status.rates[ts->ts_final_idx].count++;
1607
1608 if (unlikely(ts->ts_status)) {
1609 sc->stats.ack_fail++;
1610 if (ts->ts_status & AR5K_TXERR_FILT) {
1611 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1612 sc->stats.txerr_filt++;
1613 }
1614 if (ts->ts_status & AR5K_TXERR_XRETRY)
1615 sc->stats.txerr_retry++;
1616 if (ts->ts_status & AR5K_TXERR_FIFO)
1617 sc->stats.txerr_fifo++;
1618 } else {
1619 info->flags |= IEEE80211_TX_STAT_ACK;
1620 info->status.ack_signal = ts->ts_rssi;
1621 }
1622
1623 /*
1624 * Remove MAC header padding before giving the frame
1625 * back to mac80211.
1626 */
1627 ath5k_remove_padding(skb);
1628
1629 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1630 sc->stats.antenna_tx[ts->ts_antenna]++;
1631 else
1632 sc->stats.antenna_tx[0]++; /* invalid */
1633
1634 ieee80211_tx_status(sc->hw, skb);
1635 }
1636
1637 static void
1638 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1639 {
1640 struct ath5k_tx_status ts = {};
1641 struct ath5k_buf *bf, *bf0;
1642 struct ath5k_desc *ds;
1643 struct sk_buff *skb;
1644 int ret;
1645
1646 spin_lock(&txq->lock);
1647 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1648
1649 txq->txq_poll_mark = false;
1650
1651 /* skb might already have been processed last time. */
1652 if (bf->skb != NULL) {
1653 ds = bf->desc;
1654
1655 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1656 if (unlikely(ret == -EINPROGRESS))
1657 break;
1658 else if (unlikely(ret)) {
1659 ATH5K_ERR(sc,
1660 "error %d while processing "
1661 "queue %u\n", ret, txq->qnum);
1662 break;
1663 }
1664
1665 skb = bf->skb;
1666 bf->skb = NULL;
1667
1668 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1669 DMA_TO_DEVICE);
1670 ath5k_tx_frame_completed(sc, skb, &ts);
1671 }
1672
1673 /*
1674 * It's possible that the hardware can say the buffer is
1675 * completed when it hasn't yet loaded the ds_link from
1676 * host memory and moved on.
1677 * Always keep the last descriptor to avoid HW races...
1678 */
1679 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1680 spin_lock(&sc->txbuflock);
1681 list_move_tail(&bf->list, &sc->txbuf);
1682 sc->txbuf_len++;
1683 txq->txq_len--;
1684 spin_unlock(&sc->txbuflock);
1685 }
1686 }
1687 spin_unlock(&txq->lock);
1688 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1689 ieee80211_wake_queue(sc->hw, txq->qnum);
1690 }
1691
1692 static void
1693 ath5k_tasklet_tx(unsigned long data)
1694 {
1695 int i;
1696 struct ath5k_softc *sc = (void *)data;
1697
1698 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1699 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1700 ath5k_tx_processq(sc, &sc->txqs[i]);
1701 }
1702
1703
1704 /*****************\
1705 * Beacon handling *
1706 \*****************/
1707
1708 /*
1709 * Setup the beacon frame for transmit.
1710 */
1711 static int
1712 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1713 {
1714 struct sk_buff *skb = bf->skb;
1715 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1716 struct ath5k_hw *ah = sc->ah;
1717 struct ath5k_desc *ds;
1718 int ret = 0;
1719 u8 antenna;
1720 u32 flags;
1721 const int padsize = 0;
1722
1723 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1724 DMA_TO_DEVICE);
1725 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1726 "skbaddr %llx\n", skb, skb->data, skb->len,
1727 (unsigned long long)bf->skbaddr);
1728
1729 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
1730 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1731 return -EIO;
1732 }
1733
1734 ds = bf->desc;
1735 antenna = ah->ah_tx_ant;
1736
1737 flags = AR5K_TXDESC_NOACK;
1738 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1739 ds->ds_link = bf->daddr; /* self-linked */
1740 flags |= AR5K_TXDESC_VEOL;
1741 } else
1742 ds->ds_link = 0;
1743
1744 /*
1745 * If we use multiple antennas on AP and use
1746 * the Sectored AP scenario, switch antenna every
1747 * 4 beacons to make sure everybody hears our AP.
1748 * When a client tries to associate, hw will keep
1749 * track of the tx antenna to be used for this client
1750 * automaticaly, based on ACKed packets.
1751 *
1752 * Note: AP still listens and transmits RTS on the
1753 * default antenna which is supposed to be an omni.
1754 *
1755 * Note2: On sectored scenarios it's possible to have
1756 * multiple antennas (1 omni -- the default -- and 14
1757 * sectors), so if we choose to actually support this
1758 * mode, we need to allow the user to set how many antennas
1759 * we have and tweak the code below to send beacons
1760 * on all of them.
1761 */
1762 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1763 antenna = sc->bsent & 4 ? 2 : 1;
1764
1765
1766 /* FIXME: If we are in g mode and rate is a CCK rate
1767 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1768 * from tx power (value is in dB units already) */
1769 ds->ds_data = bf->skbaddr;
1770 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1771 ieee80211_get_hdrlen_from_skb(skb), padsize,
1772 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1773 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1774 1, AR5K_TXKEYIX_INVALID,
1775 antenna, flags, 0, 0);
1776 if (ret)
1777 goto err_unmap;
1778
1779 return 0;
1780 err_unmap:
1781 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1782 return ret;
1783 }
1784
1785 /*
1786 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1787 * this is called only once at config_bss time, for AP we do it every
1788 * SWBA interrupt so that the TIM will reflect buffered frames.
1789 *
1790 * Called with the beacon lock.
1791 */
1792 int
1793 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1794 {
1795 int ret;
1796 struct ath5k_softc *sc = hw->priv;
1797 struct ath5k_vif *avf = (void *)vif->drv_priv;
1798 struct sk_buff *skb;
1799
1800 if (WARN_ON(!vif)) {
1801 ret = -EINVAL;
1802 goto out;
1803 }
1804
1805 skb = ieee80211_beacon_get(hw, vif);
1806
1807 if (!skb) {
1808 ret = -ENOMEM;
1809 goto out;
1810 }
1811
1812 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1813
1814 ath5k_txbuf_free_skb(sc, avf->bbuf);
1815 avf->bbuf->skb = skb;
1816 ret = ath5k_beacon_setup(sc, avf->bbuf);
1817 if (ret)
1818 avf->bbuf->skb = NULL;
1819 out:
1820 return ret;
1821 }
1822
1823 /*
1824 * Transmit a beacon frame at SWBA. Dynamic updates to the
1825 * frame contents are done as needed and the slot time is
1826 * also adjusted based on current state.
1827 *
1828 * This is called from software irq context (beacontq tasklets)
1829 * or user context from ath5k_beacon_config.
1830 */
1831 static void
1832 ath5k_beacon_send(struct ath5k_softc *sc)
1833 {
1834 struct ath5k_hw *ah = sc->ah;
1835 struct ieee80211_vif *vif;
1836 struct ath5k_vif *avf;
1837 struct ath5k_buf *bf;
1838 struct sk_buff *skb;
1839
1840 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1841
1842 /*
1843 * Check if the previous beacon has gone out. If
1844 * not, don't don't try to post another: skip this
1845 * period and wait for the next. Missed beacons
1846 * indicate a problem and should not occur. If we
1847 * miss too many consecutive beacons reset the device.
1848 */
1849 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1850 sc->bmisscount++;
1851 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1852 "missed %u consecutive beacons\n", sc->bmisscount);
1853 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
1854 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1855 "stuck beacon time (%u missed)\n",
1856 sc->bmisscount);
1857 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1858 "stuck beacon, resetting\n");
1859 ieee80211_queue_work(sc->hw, &sc->reset_work);
1860 }
1861 return;
1862 }
1863 if (unlikely(sc->bmisscount != 0)) {
1864 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1865 "resume beacon xmit after %u misses\n",
1866 sc->bmisscount);
1867 sc->bmisscount = 0;
1868 }
1869
1870 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1871 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1872 u64 tsf = ath5k_hw_get_tsf64(ah);
1873 u32 tsftu = TSF_TO_TU(tsf);
1874 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1875 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1876 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1877 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1878 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1879 } else /* only one interface */
1880 vif = sc->bslot[0];
1881
1882 if (!vif)
1883 return;
1884
1885 avf = (void *)vif->drv_priv;
1886 bf = avf->bbuf;
1887 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1888 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1889 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1890 return;
1891 }
1892
1893 /*
1894 * Stop any current dma and put the new frame on the queue.
1895 * This should never fail since we check above that no frames
1896 * are still pending on the queue.
1897 */
1898 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
1899 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
1900 /* NB: hw still stops DMA, so proceed */
1901 }
1902
1903 /* refresh the beacon for AP or MESH mode */
1904 if (sc->opmode == NL80211_IFTYPE_AP ||
1905 sc->opmode == NL80211_IFTYPE_MESH_POINT)
1906 ath5k_beacon_update(sc->hw, vif);
1907
1908 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1909 ath5k_hw_start_tx_dma(ah, sc->bhalq);
1910 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1911 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1912
1913 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1914 while (skb) {
1915 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1916 skb = ieee80211_get_buffered_bc(sc->hw, vif);
1917 }
1918
1919 sc->bsent++;
1920 }
1921
1922 /**
1923 * ath5k_beacon_update_timers - update beacon timers
1924 *
1925 * @sc: struct ath5k_softc pointer we are operating on
1926 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1927 * beacon timer update based on the current HW TSF.
1928 *
1929 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1930 * of a received beacon or the current local hardware TSF and write it to the
1931 * beacon timer registers.
1932 *
1933 * This is called in a variety of situations, e.g. when a beacon is received,
1934 * when a TSF update has been detected, but also when an new IBSS is created or
1935 * when we otherwise know we have to update the timers, but we keep it in this
1936 * function to have it all together in one place.
1937 */
1938 void
1939 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1940 {
1941 struct ath5k_hw *ah = sc->ah;
1942 u32 nexttbtt, intval, hw_tu, bc_tu;
1943 u64 hw_tsf;
1944
1945 intval = sc->bintval & AR5K_BEACON_PERIOD;
1946 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1947 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1948 if (intval < 15)
1949 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1950 intval);
1951 }
1952 if (WARN_ON(!intval))
1953 return;
1954
1955 /* beacon TSF converted to TU */
1956 bc_tu = TSF_TO_TU(bc_tsf);
1957
1958 /* current TSF converted to TU */
1959 hw_tsf = ath5k_hw_get_tsf64(ah);
1960 hw_tu = TSF_TO_TU(hw_tsf);
1961
1962 #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1963 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1964 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1965 * configuration we need to make sure it is bigger than that. */
1966
1967 if (bc_tsf == -1) {
1968 /*
1969 * no beacons received, called internally.
1970 * just need to refresh timers based on HW TSF.
1971 */
1972 nexttbtt = roundup(hw_tu + FUDGE, intval);
1973 } else if (bc_tsf == 0) {
1974 /*
1975 * no beacon received, probably called by ath5k_reset_tsf().
1976 * reset TSF to start with 0.
1977 */
1978 nexttbtt = intval;
1979 intval |= AR5K_BEACON_RESET_TSF;
1980 } else if (bc_tsf > hw_tsf) {
1981 /*
1982 * beacon received, SW merge happend but HW TSF not yet updated.
1983 * not possible to reconfigure timers yet, but next time we
1984 * receive a beacon with the same BSSID, the hardware will
1985 * automatically update the TSF and then we need to reconfigure
1986 * the timers.
1987 */
1988 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1989 "need to wait for HW TSF sync\n");
1990 return;
1991 } else {
1992 /*
1993 * most important case for beacon synchronization between STA.
1994 *
1995 * beacon received and HW TSF has been already updated by HW.
1996 * update next TBTT based on the TSF of the beacon, but make
1997 * sure it is ahead of our local TSF timer.
1998 */
1999 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2000 }
2001 #undef FUDGE
2002
2003 sc->nexttbtt = nexttbtt;
2004
2005 intval |= AR5K_BEACON_ENA;
2006 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2007
2008 /*
2009 * debugging output last in order to preserve the time critical aspect
2010 * of this function
2011 */
2012 if (bc_tsf == -1)
2013 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2014 "reconfigured timers based on HW TSF\n");
2015 else if (bc_tsf == 0)
2016 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2017 "reset HW TSF and timers\n");
2018 else
2019 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2020 "updated timers based on beacon TSF\n");
2021
2022 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2023 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2024 (unsigned long long) bc_tsf,
2025 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2026 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2027 intval & AR5K_BEACON_PERIOD,
2028 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2029 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2030 }
2031
2032 /**
2033 * ath5k_beacon_config - Configure the beacon queues and interrupts
2034 *
2035 * @sc: struct ath5k_softc pointer we are operating on
2036 *
2037 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2038 * interrupts to detect TSF updates only.
2039 */
2040 void
2041 ath5k_beacon_config(struct ath5k_softc *sc)
2042 {
2043 struct ath5k_hw *ah = sc->ah;
2044 unsigned long flags;
2045
2046 spin_lock_irqsave(&sc->block, flags);
2047 sc->bmisscount = 0;
2048 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2049
2050 if (sc->enable_beacon) {
2051 /*
2052 * In IBSS mode we use a self-linked tx descriptor and let the
2053 * hardware send the beacons automatically. We have to load it
2054 * only once here.
2055 * We use the SWBA interrupt only to keep track of the beacon
2056 * timers in order to detect automatic TSF updates.
2057 */
2058 ath5k_beaconq_config(sc);
2059
2060 sc->imask |= AR5K_INT_SWBA;
2061
2062 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2063 if (ath5k_hw_hasveol(ah))
2064 ath5k_beacon_send(sc);
2065 } else
2066 ath5k_beacon_update_timers(sc, -1);
2067 } else {
2068 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
2069 }
2070
2071 ath5k_hw_set_imr(ah, sc->imask);
2072 mmiowb();
2073 spin_unlock_irqrestore(&sc->block, flags);
2074 }
2075
2076 static void ath5k_tasklet_beacon(unsigned long data)
2077 {
2078 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2079
2080 /*
2081 * Software beacon alert--time to send a beacon.
2082 *
2083 * In IBSS mode we use this interrupt just to
2084 * keep track of the next TBTT (target beacon
2085 * transmission time) in order to detect wether
2086 * automatic TSF updates happened.
2087 */
2088 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2089 /* XXX: only if VEOL suppported */
2090 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2091 sc->nexttbtt += sc->bintval;
2092 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2093 "SWBA nexttbtt: %x hw_tu: %x "
2094 "TSF: %llx\n",
2095 sc->nexttbtt,
2096 TSF_TO_TU(tsf),
2097 (unsigned long long) tsf);
2098 } else {
2099 spin_lock(&sc->block);
2100 ath5k_beacon_send(sc);
2101 spin_unlock(&sc->block);
2102 }
2103 }
2104
2105
2106 /********************\
2107 * Interrupt handling *
2108 \********************/
2109
2110 static void
2111 ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2112 {
2113 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2114 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2115 /* run ANI only when full calibration is not active */
2116 ah->ah_cal_next_ani = jiffies +
2117 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2118 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2119
2120 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2121 ah->ah_cal_next_full = jiffies +
2122 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2123 tasklet_schedule(&ah->ah_sc->calib);
2124 }
2125 /* we could use SWI to generate enough interrupts to meet our
2126 * calibration interval requirements, if necessary:
2127 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2128 }
2129
2130 irqreturn_t
2131 ath5k_intr(int irq, void *dev_id)
2132 {
2133 struct ath5k_softc *sc = dev_id;
2134 struct ath5k_hw *ah = sc->ah;
2135 enum ath5k_int status;
2136 unsigned int counter = 1000;
2137
2138 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2139 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2140 !ath5k_hw_is_intr_pending(ah))))
2141 return IRQ_NONE;
2142
2143 do {
2144 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2145 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2146 status, sc->imask);
2147 if (unlikely(status & AR5K_INT_FATAL)) {
2148 /*
2149 * Fatal errors are unrecoverable.
2150 * Typically these are caused by DMA errors.
2151 */
2152 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2153 "fatal int, resetting\n");
2154 ieee80211_queue_work(sc->hw, &sc->reset_work);
2155 } else if (unlikely(status & AR5K_INT_RXORN)) {
2156 /*
2157 * Receive buffers are full. Either the bus is busy or
2158 * the CPU is not fast enough to process all received
2159 * frames.
2160 * Older chipsets need a reset to come out of this
2161 * condition, but we treat it as RX for newer chips.
2162 * We don't know exactly which versions need a reset -
2163 * this guess is copied from the HAL.
2164 */
2165 sc->stats.rxorn_intr++;
2166 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2167 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2168 "rx overrun, resetting\n");
2169 ieee80211_queue_work(sc->hw, &sc->reset_work);
2170 }
2171 else
2172 tasklet_schedule(&sc->rxtq);
2173 } else {
2174 if (status & AR5K_INT_SWBA) {
2175 tasklet_hi_schedule(&sc->beacontq);
2176 }
2177 if (status & AR5K_INT_RXEOL) {
2178 /*
2179 * NB: the hardware should re-read the link when
2180 * RXE bit is written, but it doesn't work at
2181 * least on older hardware revs.
2182 */
2183 sc->stats.rxeol_intr++;
2184 }
2185 if (status & AR5K_INT_TXURN) {
2186 /* bump tx trigger level */
2187 ath5k_hw_update_tx_triglevel(ah, true);
2188 }
2189 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2190 tasklet_schedule(&sc->rxtq);
2191 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2192 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2193 tasklet_schedule(&sc->txtq);
2194 if (status & AR5K_INT_BMISS) {
2195 /* TODO */
2196 }
2197 if (status & AR5K_INT_MIB) {
2198 sc->stats.mib_intr++;
2199 ath5k_hw_update_mib_counters(ah);
2200 ath5k_ani_mib_intr(ah);
2201 }
2202 if (status & AR5K_INT_GPIO)
2203 tasklet_schedule(&sc->rf_kill.toggleq);
2204
2205 }
2206
2207 if (ath5k_get_bus_type(ah) == ATH_AHB)
2208 break;
2209
2210 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2211
2212 if (unlikely(!counter))
2213 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2214
2215 ath5k_intr_calibration_poll(ah);
2216
2217 return IRQ_HANDLED;
2218 }
2219
2220 /*
2221 * Periodically recalibrate the PHY to account
2222 * for temperature/environment changes.
2223 */
2224 static void
2225 ath5k_tasklet_calibrate(unsigned long data)
2226 {
2227 struct ath5k_softc *sc = (void *)data;
2228 struct ath5k_hw *ah = sc->ah;
2229
2230 /* Only full calibration for now */
2231 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2232
2233 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2234 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2235 sc->curchan->hw_value);
2236
2237 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2238 /*
2239 * Rfgain is out of bounds, reset the chip
2240 * to load new gain values.
2241 */
2242 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2243 ieee80211_queue_work(sc->hw, &sc->reset_work);
2244 }
2245 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2246 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2247 ieee80211_frequency_to_channel(
2248 sc->curchan->center_freq));
2249
2250 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2251 * doesn't.
2252 * TODO: We should stop TX here, so that it doesn't interfere.
2253 * Note that stopping the queues is not enough to stop TX! */
2254 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2255 ah->ah_cal_next_nf = jiffies +
2256 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2257 ath5k_hw_update_noise_floor(ah);
2258 }
2259
2260 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
2261 }
2262
2263
2264 static void
2265 ath5k_tasklet_ani(unsigned long data)
2266 {
2267 struct ath5k_softc *sc = (void *)data;
2268 struct ath5k_hw *ah = sc->ah;
2269
2270 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2271 ath5k_ani_calibration(ah);
2272 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
2273 }
2274
2275
2276 static void
2277 ath5k_tx_complete_poll_work(struct work_struct *work)
2278 {
2279 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2280 tx_complete_work.work);
2281 struct ath5k_txq *txq;
2282 int i;
2283 bool needreset = false;
2284
2285 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2286 if (sc->txqs[i].setup) {
2287 txq = &sc->txqs[i];
2288 spin_lock_bh(&txq->lock);
2289 if (txq->txq_len > 1) {
2290 if (txq->txq_poll_mark) {
2291 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2292 "TX queue stuck %d\n",
2293 txq->qnum);
2294 needreset = true;
2295 txq->txq_stuck++;
2296 spin_unlock_bh(&txq->lock);
2297 break;
2298 } else {
2299 txq->txq_poll_mark = true;
2300 }
2301 }
2302 spin_unlock_bh(&txq->lock);
2303 }
2304 }
2305
2306 if (needreset) {
2307 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2308 "TX queues stuck, resetting\n");
2309 ath5k_reset(sc, NULL, true);
2310 }
2311
2312 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2313 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2314 }
2315
2316
2317 /*************************\
2318 * Initialization routines *
2319 \*************************/
2320
2321 int
2322 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2323 {
2324 struct ieee80211_hw *hw = sc->hw;
2325 struct ath_common *common;
2326 int ret;
2327 int csz;
2328
2329 /* Initialize driver private data */
2330 SET_IEEE80211_DEV(hw, sc->dev);
2331 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2332 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2333 IEEE80211_HW_SIGNAL_DBM |
2334 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2335
2336 hw->wiphy->interface_modes =
2337 BIT(NL80211_IFTYPE_AP) |
2338 BIT(NL80211_IFTYPE_STATION) |
2339 BIT(NL80211_IFTYPE_ADHOC) |
2340 BIT(NL80211_IFTYPE_MESH_POINT);
2341
2342 /* both antennas can be configured as RX or TX */
2343 hw->wiphy->available_antennas_tx = 0x3;
2344 hw->wiphy->available_antennas_rx = 0x3;
2345
2346 hw->extra_tx_headroom = 2;
2347 hw->channel_change_time = 5000;
2348
2349 /*
2350 * Mark the device as detached to avoid processing
2351 * interrupts until setup is complete.
2352 */
2353 __set_bit(ATH_STAT_INVALID, sc->status);
2354
2355 sc->opmode = NL80211_IFTYPE_STATION;
2356 sc->bintval = 1000;
2357 mutex_init(&sc->lock);
2358 spin_lock_init(&sc->rxbuflock);
2359 spin_lock_init(&sc->txbuflock);
2360 spin_lock_init(&sc->block);
2361
2362
2363 /* Setup interrupt handler */
2364 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2365 if (ret) {
2366 ATH5K_ERR(sc, "request_irq failed\n");
2367 goto err;
2368 }
2369
2370 /* If we passed the test, malloc an ath5k_hw struct */
2371 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2372 if (!sc->ah) {
2373 ret = -ENOMEM;
2374 ATH5K_ERR(sc, "out of memory\n");
2375 goto err_irq;
2376 }
2377
2378 sc->ah->ah_sc = sc;
2379 sc->ah->ah_iobase = sc->iobase;
2380 common = ath5k_hw_common(sc->ah);
2381 common->ops = &ath5k_common_ops;
2382 common->bus_ops = bus_ops;
2383 common->ah = sc->ah;
2384 common->hw = hw;
2385 common->priv = sc;
2386
2387 /*
2388 * Cache line size is used to size and align various
2389 * structures used to communicate with the hardware.
2390 */
2391 ath5k_read_cachesize(common, &csz);
2392 common->cachelsz = csz << 2; /* convert to bytes */
2393
2394 spin_lock_init(&common->cc_lock);
2395
2396 /* Initialize device */
2397 ret = ath5k_hw_init(sc);
2398 if (ret)
2399 goto err_free_ah;
2400
2401 /* set up multi-rate retry capabilities */
2402 if (sc->ah->ah_version == AR5K_AR5212) {
2403 hw->max_rates = 4;
2404 hw->max_rate_tries = 11;
2405 }
2406
2407 hw->vif_data_size = sizeof(struct ath5k_vif);
2408
2409 /* Finish private driver data initialization */
2410 ret = ath5k_init(hw);
2411 if (ret)
2412 goto err_ah;
2413
2414 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2415 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2416 sc->ah->ah_mac_srev,
2417 sc->ah->ah_phy_revision);
2418
2419 if (!sc->ah->ah_single_chip) {
2420 /* Single chip radio (!RF5111) */
2421 if (sc->ah->ah_radio_5ghz_revision &&
2422 !sc->ah->ah_radio_2ghz_revision) {
2423 /* No 5GHz support -> report 2GHz radio */
2424 if (!test_bit(AR5K_MODE_11A,
2425 sc->ah->ah_capabilities.cap_mode)) {
2426 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2427 ath5k_chip_name(AR5K_VERSION_RAD,
2428 sc->ah->ah_radio_5ghz_revision),
2429 sc->ah->ah_radio_5ghz_revision);
2430 /* No 2GHz support (5110 and some
2431 * 5Ghz only cards) -> report 5Ghz radio */
2432 } else if (!test_bit(AR5K_MODE_11B,
2433 sc->ah->ah_capabilities.cap_mode)) {
2434 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2435 ath5k_chip_name(AR5K_VERSION_RAD,
2436 sc->ah->ah_radio_5ghz_revision),
2437 sc->ah->ah_radio_5ghz_revision);
2438 /* Multiband radio */
2439 } else {
2440 ATH5K_INFO(sc, "RF%s multiband radio found"
2441 " (0x%x)\n",
2442 ath5k_chip_name(AR5K_VERSION_RAD,
2443 sc->ah->ah_radio_5ghz_revision),
2444 sc->ah->ah_radio_5ghz_revision);
2445 }
2446 }
2447 /* Multi chip radio (RF5111 - RF2111) ->
2448 * report both 2GHz/5GHz radios */
2449 else if (sc->ah->ah_radio_5ghz_revision &&
2450 sc->ah->ah_radio_2ghz_revision){
2451 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2452 ath5k_chip_name(AR5K_VERSION_RAD,
2453 sc->ah->ah_radio_5ghz_revision),
2454 sc->ah->ah_radio_5ghz_revision);
2455 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2456 ath5k_chip_name(AR5K_VERSION_RAD,
2457 sc->ah->ah_radio_2ghz_revision),
2458 sc->ah->ah_radio_2ghz_revision);
2459 }
2460 }
2461
2462 ath5k_debug_init_device(sc);
2463
2464 /* ready to process interrupts */
2465 __clear_bit(ATH_STAT_INVALID, sc->status);
2466
2467 return 0;
2468 err_ah:
2469 ath5k_hw_deinit(sc->ah);
2470 err_free_ah:
2471 kfree(sc->ah);
2472 err_irq:
2473 free_irq(sc->irq, sc);
2474 err:
2475 return ret;
2476 }
2477
2478 static int
2479 ath5k_stop_locked(struct ath5k_softc *sc)
2480 {
2481 struct ath5k_hw *ah = sc->ah;
2482
2483 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2484 test_bit(ATH_STAT_INVALID, sc->status));
2485
2486 /*
2487 * Shutdown the hardware and driver:
2488 * stop output from above
2489 * disable interrupts
2490 * turn off timers
2491 * turn off the radio
2492 * clear transmit machinery
2493 * clear receive machinery
2494 * drain and release tx queues
2495 * reclaim beacon resources
2496 * power down hardware
2497 *
2498 * Note that some of this work is not possible if the
2499 * hardware is gone (invalid).
2500 */
2501 ieee80211_stop_queues(sc->hw);
2502
2503 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2504 ath5k_led_off(sc);
2505 ath5k_hw_set_imr(ah, 0);
2506 synchronize_irq(sc->irq);
2507 ath5k_rx_stop(sc);
2508 ath5k_hw_dma_stop(ah);
2509 ath5k_drain_tx_buffs(sc);
2510 ath5k_hw_phy_disable(ah);
2511 }
2512
2513 return 0;
2514 }
2515
2516 int
2517 ath5k_init_hw(struct ath5k_softc *sc)
2518 {
2519 struct ath5k_hw *ah = sc->ah;
2520 struct ath_common *common = ath5k_hw_common(ah);
2521 int ret, i;
2522
2523 mutex_lock(&sc->lock);
2524
2525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2526
2527 /*
2528 * Stop anything previously setup. This is safe
2529 * no matter this is the first time through or not.
2530 */
2531 ath5k_stop_locked(sc);
2532
2533 /*
2534 * The basic interface to setting the hardware in a good
2535 * state is ``reset''. On return the hardware is known to
2536 * be powered up and with interrupts disabled. This must
2537 * be followed by initialization of the appropriate bits
2538 * and then setup of the interrupt mask.
2539 */
2540 sc->curchan = sc->hw->conf.channel;
2541 sc->curband = &sc->sbands[sc->curchan->band];
2542 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2543 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2544 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2545
2546 ret = ath5k_reset(sc, NULL, false);
2547 if (ret)
2548 goto done;
2549
2550 ath5k_rfkill_hw_start(ah);
2551
2552 /*
2553 * Reset the key cache since some parts do not reset the
2554 * contents on initial power up or resume from suspend.
2555 */
2556 for (i = 0; i < common->keymax; i++)
2557 ath_hw_keyreset(common, (u16) i);
2558
2559 /* Use higher rates for acks instead of base
2560 * rate */
2561 ah->ah_ack_bitrate_high = true;
2562
2563 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2564 sc->bslot[i] = NULL;
2565
2566 ret = 0;
2567 done:
2568 mmiowb();
2569 mutex_unlock(&sc->lock);
2570
2571 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2572 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2573
2574 return ret;
2575 }
2576
2577 static void stop_tasklets(struct ath5k_softc *sc)
2578 {
2579 tasklet_kill(&sc->rxtq);
2580 tasklet_kill(&sc->txtq);
2581 tasklet_kill(&sc->calib);
2582 tasklet_kill(&sc->beacontq);
2583 tasklet_kill(&sc->ani_tasklet);
2584 }
2585
2586 /*
2587 * Stop the device, grabbing the top-level lock to protect
2588 * against concurrent entry through ath5k_init (which can happen
2589 * if another thread does a system call and the thread doing the
2590 * stop is preempted).
2591 */
2592 int
2593 ath5k_stop_hw(struct ath5k_softc *sc)
2594 {
2595 int ret;
2596
2597 mutex_lock(&sc->lock);
2598 ret = ath5k_stop_locked(sc);
2599 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2600 /*
2601 * Don't set the card in full sleep mode!
2602 *
2603 * a) When the device is in this state it must be carefully
2604 * woken up or references to registers in the PCI clock
2605 * domain may freeze the bus (and system). This varies
2606 * by chip and is mostly an issue with newer parts
2607 * (madwifi sources mentioned srev >= 0x78) that go to
2608 * sleep more quickly.
2609 *
2610 * b) On older chips full sleep results a weird behaviour
2611 * during wakeup. I tested various cards with srev < 0x78
2612 * and they don't wake up after module reload, a second
2613 * module reload is needed to bring the card up again.
2614 *
2615 * Until we figure out what's going on don't enable
2616 * full chip reset on any chip (this is what Legacy HAL
2617 * and Sam's HAL do anyway). Instead Perform a full reset
2618 * on the device (same as initial state after attach) and
2619 * leave it idle (keep MAC/BB on warm reset) */
2620 ret = ath5k_hw_on_hold(sc->ah);
2621
2622 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2623 "putting device to sleep\n");
2624 }
2625
2626 mmiowb();
2627 mutex_unlock(&sc->lock);
2628
2629 stop_tasklets(sc);
2630
2631 cancel_delayed_work_sync(&sc->tx_complete_work);
2632
2633 ath5k_rfkill_hw_stop(sc->ah);
2634
2635 return ret;
2636 }
2637
2638 /*
2639 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2640 * and change to the given channel.
2641 *
2642 * This should be called with sc->lock.
2643 */
2644 static int
2645 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2646 bool skip_pcu)
2647 {
2648 struct ath5k_hw *ah = sc->ah;
2649 struct ath_common *common = ath5k_hw_common(ah);
2650 int ret, ani_mode;
2651
2652 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2653
2654 ath5k_hw_set_imr(ah, 0);
2655 synchronize_irq(sc->irq);
2656 stop_tasklets(sc);
2657
2658 /* Save ani mode and disable ANI durring
2659 * reset. If we don't we might get false
2660 * PHY error interrupts. */
2661 ani_mode = ah->ah_sc->ani_state.ani_mode;
2662 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2663
2664 /* We are going to empty hw queues
2665 * so we should also free any remaining
2666 * tx buffers */
2667 ath5k_drain_tx_buffs(sc);
2668 if (chan) {
2669 sc->curchan = chan;
2670 sc->curband = &sc->sbands[chan->band];
2671 }
2672 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2673 skip_pcu);
2674 if (ret) {
2675 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2676 goto err;
2677 }
2678
2679 ret = ath5k_rx_start(sc);
2680 if (ret) {
2681 ATH5K_ERR(sc, "can't start recv logic\n");
2682 goto err;
2683 }
2684
2685 ath5k_ani_init(ah, ani_mode);
2686
2687 ah->ah_cal_next_full = jiffies;
2688 ah->ah_cal_next_ani = jiffies;
2689 ah->ah_cal_next_nf = jiffies;
2690 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2691
2692 /* clear survey data and cycle counters */
2693 memset(&sc->survey, 0, sizeof(sc->survey));
2694 spin_lock_bh(&common->cc_lock);
2695 ath_hw_cycle_counters_update(common);
2696 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2697 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
2698 spin_unlock_bh(&common->cc_lock);
2699
2700 /*
2701 * Change channels and update the h/w rate map if we're switching;
2702 * e.g. 11a to 11b/g.
2703 *
2704 * We may be doing a reset in response to an ioctl that changes the
2705 * channel so update any state that might change as a result.
2706 *
2707 * XXX needed?
2708 */
2709 /* ath5k_chan_change(sc, c); */
2710
2711 ath5k_beacon_config(sc);
2712 /* intrs are enabled by ath5k_beacon_config */
2713
2714 ieee80211_wake_queues(sc->hw);
2715
2716 return 0;
2717 err:
2718 return ret;
2719 }
2720
2721 static void ath5k_reset_work(struct work_struct *work)
2722 {
2723 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2724 reset_work);
2725
2726 mutex_lock(&sc->lock);
2727 ath5k_reset(sc, NULL, true);
2728 mutex_unlock(&sc->lock);
2729 }
2730
2731 static int
2732 ath5k_init(struct ieee80211_hw *hw)
2733 {
2734
2735 struct ath5k_softc *sc = hw->priv;
2736 struct ath5k_hw *ah = sc->ah;
2737 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2738 struct ath5k_txq *txq;
2739 u8 mac[ETH_ALEN] = {};
2740 int ret;
2741
2742
2743 /*
2744 * Check if the MAC has multi-rate retry support.
2745 * We do this by trying to setup a fake extended
2746 * descriptor. MACs that don't have support will
2747 * return false w/o doing anything. MACs that do
2748 * support it will return true w/o doing anything.
2749 */
2750 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
2751
2752 if (ret < 0)
2753 goto err;
2754 if (ret > 0)
2755 __set_bit(ATH_STAT_MRRETRY, sc->status);
2756
2757 /*
2758 * Collect the channel list. The 802.11 layer
2759 * is resposible for filtering this list based
2760 * on settings like the phy mode and regulatory
2761 * domain restrictions.
2762 */
2763 ret = ath5k_setup_bands(hw);
2764 if (ret) {
2765 ATH5K_ERR(sc, "can't get channels\n");
2766 goto err;
2767 }
2768
2769 /*
2770 * Allocate tx+rx descriptors and populate the lists.
2771 */
2772 ret = ath5k_desc_alloc(sc);
2773 if (ret) {
2774 ATH5K_ERR(sc, "can't allocate descriptors\n");
2775 goto err;
2776 }
2777
2778 /*
2779 * Allocate hardware transmit queues: one queue for
2780 * beacon frames and one data queue for each QoS
2781 * priority. Note that hw functions handle resetting
2782 * these queues at the needed time.
2783 */
2784 ret = ath5k_beaconq_setup(ah);
2785 if (ret < 0) {
2786 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2787 goto err_desc;
2788 }
2789 sc->bhalq = ret;
2790 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2791 if (IS_ERR(sc->cabq)) {
2792 ATH5K_ERR(sc, "can't setup cab queue\n");
2793 ret = PTR_ERR(sc->cabq);
2794 goto err_bhal;
2795 }
2796
2797 /* 5211 and 5212 usually support 10 queues but we better rely on the
2798 * capability information */
2799 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2800 /* This order matches mac80211's queue priority, so we can
2801 * directly use the mac80211 queue number without any mapping */
2802 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2803 if (IS_ERR(txq)) {
2804 ATH5K_ERR(sc, "can't setup xmit queue\n");
2805 ret = PTR_ERR(txq);
2806 goto err_queues;
2807 }
2808 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2809 if (IS_ERR(txq)) {
2810 ATH5K_ERR(sc, "can't setup xmit queue\n");
2811 ret = PTR_ERR(txq);
2812 goto err_queues;
2813 }
2814 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2815 if (IS_ERR(txq)) {
2816 ATH5K_ERR(sc, "can't setup xmit queue\n");
2817 ret = PTR_ERR(txq);
2818 goto err_queues;
2819 }
2820 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2821 if (IS_ERR(txq)) {
2822 ATH5K_ERR(sc, "can't setup xmit queue\n");
2823 ret = PTR_ERR(txq);
2824 goto err_queues;
2825 }
2826 hw->queues = 4;
2827 } else {
2828 /* older hardware (5210) can only support one data queue */
2829 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2830 if (IS_ERR(txq)) {
2831 ATH5K_ERR(sc, "can't setup xmit queue\n");
2832 ret = PTR_ERR(txq);
2833 goto err_queues;
2834 }
2835 hw->queues = 1;
2836 }
2837
2838 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2839 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2840 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2841 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2842 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
2843
2844 INIT_WORK(&sc->reset_work, ath5k_reset_work);
2845 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
2846
2847 ret = ath5k_eeprom_read_mac(ah, mac);
2848 if (ret) {
2849 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
2850 goto err_queues;
2851 }
2852
2853 SET_IEEE80211_PERM_ADDR(hw, mac);
2854 memcpy(&sc->lladdr, mac, ETH_ALEN);
2855 /* All MAC address bits matter for ACKs */
2856 ath5k_update_bssid_mask_and_opmode(sc, NULL);
2857
2858 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2859 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2860 if (ret) {
2861 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2862 goto err_queues;
2863 }
2864
2865 ret = ieee80211_register_hw(hw);
2866 if (ret) {
2867 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2868 goto err_queues;
2869 }
2870
2871 if (!ath_is_world_regd(regulatory))
2872 regulatory_hint(hw->wiphy, regulatory->alpha2);
2873
2874 ath5k_init_leds(sc);
2875
2876 ath5k_sysfs_register(sc);
2877
2878 return 0;
2879 err_queues:
2880 ath5k_txq_release(sc);
2881 err_bhal:
2882 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2883 err_desc:
2884 ath5k_desc_free(sc);
2885 err:
2886 return ret;
2887 }
2888
2889 void
2890 ath5k_deinit_softc(struct ath5k_softc *sc)
2891 {
2892 struct ieee80211_hw *hw = sc->hw;
2893
2894 /*
2895 * NB: the order of these is important:
2896 * o call the 802.11 layer before detaching ath5k_hw to
2897 * ensure callbacks into the driver to delete global
2898 * key cache entries can be handled
2899 * o reclaim the tx queue data structures after calling
2900 * the 802.11 layer as we'll get called back to reclaim
2901 * node state and potentially want to use them
2902 * o to cleanup the tx queues the hal is called, so detach
2903 * it last
2904 * XXX: ??? detach ath5k_hw ???
2905 * Other than that, it's straightforward...
2906 */
2907 ath5k_debug_finish_device(sc);
2908 ieee80211_unregister_hw(hw);
2909 ath5k_desc_free(sc);
2910 ath5k_txq_release(sc);
2911 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2912 ath5k_unregister_leds(sc);
2913
2914 ath5k_sysfs_unregister(sc);
2915 /*
2916 * NB: can't reclaim these until after ieee80211_ifdetach
2917 * returns because we'll get called back to reclaim node
2918 * state and potentially want to use them.
2919 */
2920 ath5k_hw_deinit(sc->ah);
2921 free_irq(sc->irq, sc);
2922 }
2923
2924 bool
2925 ath_any_vif_assoc(struct ath5k_softc *sc)
2926 {
2927 struct ath_vif_iter_data iter_data;
2928 iter_data.hw_macaddr = NULL;
2929 iter_data.any_assoc = false;
2930 iter_data.need_set_hw_addr = false;
2931 iter_data.found_active = true;
2932
2933 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter,
2934 &iter_data);
2935 return iter_data.any_assoc;
2936 }
2937
2938 void
2939 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2940 {
2941 struct ath5k_softc *sc = hw->priv;
2942 struct ath5k_hw *ah = sc->ah;
2943 u32 rfilt;
2944 rfilt = ath5k_hw_get_rx_filter(ah);
2945 if (enable)
2946 rfilt |= AR5K_RX_FILTER_BEACON;
2947 else
2948 rfilt &= ~AR5K_RX_FILTER_BEACON;
2949 ath5k_hw_set_rx_filter(ah, rfilt);
2950 sc->filter_flags = rfilt;
2951 }
kernel source for telekom puls (alcatel/mediatek)