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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wan / dscc4.c
1 /*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83 #include <linux/module.h>
84 #include <linux/types.h>
85 #include <linux/errno.h>
86 #include <linux/list.h>
87 #include <linux/ioport.h>
88 #include <linux/pci.h>
89 #include <linux/kernel.h>
90 #include <linux/mm.h>
91
92 #include <asm/system.h>
93 #include <asm/cache.h>
94 #include <asm/byteorder.h>
95 #include <asm/uaccess.h>
96 #include <asm/io.h>
97 #include <asm/irq.h>
98
99 #include <linux/init.h>
100 #include <linux/string.h>
101
102 #include <linux/if_arp.h>
103 #include <linux/netdevice.h>
104 #include <linux/skbuff.h>
105 #include <linux/delay.h>
106 #include <net/syncppp.h>
107 #include <linux/hdlc.h>
108 #include <linux/mutex.h>
109
110 /* Version */
111 static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
112 static int debug;
113 static int quartz;
114
115 #ifdef CONFIG_DSCC4_PCI_RST
116 static DEFINE_MUTEX(dscc4_mutex);
117 static u32 dscc4_pci_config_store[16];
118 #endif
119
120 #define DRV_NAME "dscc4"
121
122 #undef DSCC4_POLLING
123
124 /* Module parameters */
125
126 MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
127 MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
128 MODULE_LICENSE("GPL");
129 module_param(debug, int, 0);
130 MODULE_PARM_DESC(debug,"Enable/disable extra messages");
131 module_param(quartz, int, 0);
132 MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
133
134 /* Structures */
135
136 struct thingie {
137 int define;
138 u32 bits;
139 };
140
141 struct TxFD {
142 u32 state;
143 u32 next;
144 u32 data;
145 u32 complete;
146 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
147 };
148
149 struct RxFD {
150 u32 state1;
151 u32 next;
152 u32 data;
153 u32 state2;
154 u32 end;
155 };
156
157 #define DUMMY_SKB_SIZE 64
158 #define TX_LOW 8
159 #define TX_RING_SIZE 32
160 #define RX_RING_SIZE 32
161 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
162 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
163 #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
164 #define TX_TIMEOUT (HZ/10)
165 #define DSCC4_HZ_MAX 33000000
166 #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
167 #define dev_per_card 4
168 #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
169
170 #define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
171 #define TO_SIZE(state) (((state) >> 16) & 0x1fff)
172
173 /*
174 * Given the operating range of Linux HDLC, the 2 defines below could be
175 * made simpler. However they are a fine reminder for the limitations of
176 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
177 */
178 #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
179 #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
180 #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
181 #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
182
183 struct dscc4_pci_priv {
184 u32 *iqcfg;
185 int cfg_cur;
186 spinlock_t lock;
187 struct pci_dev *pdev;
188
189 struct dscc4_dev_priv *root;
190 dma_addr_t iqcfg_dma;
191 u32 xtal_hz;
192 };
193
194 struct dscc4_dev_priv {
195 struct sk_buff *rx_skbuff[RX_RING_SIZE];
196 struct sk_buff *tx_skbuff[TX_RING_SIZE];
197
198 struct RxFD *rx_fd;
199 struct TxFD *tx_fd;
200 u32 *iqrx;
201 u32 *iqtx;
202
203 /* FIXME: check all the volatile are required */
204 volatile u32 tx_current;
205 u32 rx_current;
206 u32 iqtx_current;
207 u32 iqrx_current;
208
209 volatile u32 tx_dirty;
210 volatile u32 ltda;
211 u32 rx_dirty;
212 u32 lrda;
213
214 dma_addr_t tx_fd_dma;
215 dma_addr_t rx_fd_dma;
216 dma_addr_t iqtx_dma;
217 dma_addr_t iqrx_dma;
218
219 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
220
221 struct timer_list timer;
222
223 struct dscc4_pci_priv *pci_priv;
224 spinlock_t lock;
225
226 int dev_id;
227 volatile u32 flags;
228 u32 timer_help;
229
230 unsigned short encoding;
231 unsigned short parity;
232 struct net_device *dev;
233 sync_serial_settings settings;
234 void __iomem *base_addr;
235 u32 __pad __attribute__ ((aligned (4)));
236 };
237
238 /* GLOBAL registers definitions */
239 #define GCMDR 0x00
240 #define GSTAR 0x04
241 #define GMODE 0x08
242 #define IQLENR0 0x0C
243 #define IQLENR1 0x10
244 #define IQRX0 0x14
245 #define IQTX0 0x24
246 #define IQCFG 0x3c
247 #define FIFOCR1 0x44
248 #define FIFOCR2 0x48
249 #define FIFOCR3 0x4c
250 #define FIFOCR4 0x34
251 #define CH0CFG 0x50
252 #define CH0BRDA 0x54
253 #define CH0BTDA 0x58
254 #define CH0FRDA 0x98
255 #define CH0FTDA 0xb0
256 #define CH0LRDA 0xc8
257 #define CH0LTDA 0xe0
258
259 /* SCC registers definitions */
260 #define SCC_START 0x0100
261 #define SCC_OFFSET 0x80
262 #define CMDR 0x00
263 #define STAR 0x04
264 #define CCR0 0x08
265 #define CCR1 0x0c
266 #define CCR2 0x10
267 #define BRR 0x2C
268 #define RLCR 0x40
269 #define IMR 0x54
270 #define ISR 0x58
271
272 #define GPDIR 0x0400
273 #define GPDATA 0x0404
274 #define GPIM 0x0408
275
276 /* Bit masks */
277 #define EncodingMask 0x00700000
278 #define CrcMask 0x00000003
279
280 #define IntRxScc0 0x10000000
281 #define IntTxScc0 0x01000000
282
283 #define TxPollCmd 0x00000400
284 #define RxActivate 0x08000000
285 #define MTFi 0x04000000
286 #define Rdr 0x00400000
287 #define Rdt 0x00200000
288 #define Idr 0x00100000
289 #define Idt 0x00080000
290 #define TxSccRes 0x01000000
291 #define RxSccRes 0x00010000
292 #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
293 #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
294
295 #define Ccr0ClockMask 0x0000003f
296 #define Ccr1LoopMask 0x00000200
297 #define IsrMask 0x000fffff
298 #define BrrExpMask 0x00000f00
299 #define BrrMultMask 0x0000003f
300 #define EncodingMask 0x00700000
301 #define Hold 0x40000000
302 #define SccBusy 0x10000000
303 #define PowerUp 0x80000000
304 #define Vis 0x00001000
305 #define FrameOk (FrameVfr | FrameCrc)
306 #define FrameVfr 0x80
307 #define FrameRdo 0x40
308 #define FrameCrc 0x20
309 #define FrameRab 0x10
310 #define FrameAborted 0x00000200
311 #define FrameEnd 0x80000000
312 #define DataComplete 0x40000000
313 #define LengthCheck 0x00008000
314 #define SccEvt 0x02000000
315 #define NoAck 0x00000200
316 #define Action 0x00000001
317 #define HiDesc 0x20000000
318
319 /* SCC events */
320 #define RxEvt 0xf0000000
321 #define TxEvt 0x0f000000
322 #define Alls 0x00040000
323 #define Xdu 0x00010000
324 #define Cts 0x00004000
325 #define Xmr 0x00002000
326 #define Xpr 0x00001000
327 #define Rdo 0x00000080
328 #define Rfs 0x00000040
329 #define Cd 0x00000004
330 #define Rfo 0x00000002
331 #define Flex 0x00000001
332
333 /* DMA core events */
334 #define Cfg 0x00200000
335 #define Hi 0x00040000
336 #define Fi 0x00020000
337 #define Err 0x00010000
338 #define Arf 0x00000002
339 #define ArAck 0x00000001
340
341 /* State flags */
342 #define Ready 0x00000000
343 #define NeedIDR 0x00000001
344 #define NeedIDT 0x00000002
345 #define RdoSet 0x00000004
346 #define FakeReset 0x00000008
347
348 /* Don't mask RDO. Ever. */
349 #ifdef DSCC4_POLLING
350 #define EventsMask 0xfffeef7f
351 #else
352 #define EventsMask 0xfffa8f7a
353 #endif
354
355 /* Functions prototypes */
356 static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
357 static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358 static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
359 static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
360 static int dscc4_open(struct net_device *);
361 static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
362 static int dscc4_close(struct net_device *);
363 static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
364 static int dscc4_init_ring(struct net_device *);
365 static void dscc4_release_ring(struct dscc4_dev_priv *);
366 static void dscc4_timer(unsigned long);
367 static void dscc4_tx_timeout(struct net_device *);
368 static irqreturn_t dscc4_irq(int irq, void *dev_id);
369 static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
370 static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
371 #ifdef DSCC4_POLLING
372 static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
373 #endif
374
375 static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
376 {
377 return dev_to_hdlc(dev)->priv;
378 }
379
380 static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
381 {
382 return p->dev;
383 }
384
385 static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
386 struct net_device *dev, int offset)
387 {
388 u32 state;
389
390 /* Cf scc_writel for concern regarding thread-safety */
391 state = dpriv->scc_regs[offset >> 2];
392 state &= ~mask;
393 state |= value;
394 dpriv->scc_regs[offset >> 2] = state;
395 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
396 }
397
398 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
399 struct net_device *dev, int offset)
400 {
401 /*
402 * Thread-UNsafe.
403 * As of 2002/02/16, there are no thread racing for access.
404 */
405 dpriv->scc_regs[offset >> 2] = bits;
406 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
407 }
408
409 static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
410 {
411 return dpriv->scc_regs[offset >> 2];
412 }
413
414 static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
415 {
416 /* Cf errata DS5 p.4 */
417 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
418 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
419 }
420
421 static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
422 struct net_device *dev)
423 {
424 dpriv->ltda = dpriv->tx_fd_dma +
425 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
426 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
427 /* Flush posted writes *NOW* */
428 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
429 }
430
431 static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
432 struct net_device *dev)
433 {
434 dpriv->lrda = dpriv->rx_fd_dma +
435 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
436 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
437 }
438
439 static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
440 {
441 return dpriv->tx_current == dpriv->tx_dirty;
442 }
443
444 static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
445 struct net_device *dev)
446 {
447 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
448 }
449
450 static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
451 struct net_device *dev, const char *msg)
452 {
453 int ret = 0;
454
455 if (debug > 1) {
456 if (SOURCE_ID(state) != dpriv->dev_id) {
457 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
458 dev->name, msg, SOURCE_ID(state), state );
459 ret = -1;
460 }
461 if (state & 0x0df80c00) {
462 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
463 dev->name, msg, state);
464 ret = -1;
465 }
466 }
467 return ret;
468 }
469
470 static void dscc4_tx_print(struct net_device *dev,
471 struct dscc4_dev_priv *dpriv,
472 char *msg)
473 {
474 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
475 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
476 }
477
478 static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
479 {
480 struct pci_dev *pdev = dpriv->pci_priv->pdev;
481 struct TxFD *tx_fd = dpriv->tx_fd;
482 struct RxFD *rx_fd = dpriv->rx_fd;
483 struct sk_buff **skbuff;
484 int i;
485
486 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
487 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
488
489 skbuff = dpriv->tx_skbuff;
490 for (i = 0; i < TX_RING_SIZE; i++) {
491 if (*skbuff) {
492 pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len,
493 PCI_DMA_TODEVICE);
494 dev_kfree_skb(*skbuff);
495 }
496 skbuff++;
497 tx_fd++;
498 }
499
500 skbuff = dpriv->rx_skbuff;
501 for (i = 0; i < RX_RING_SIZE; i++) {
502 if (*skbuff) {
503 pci_unmap_single(pdev, rx_fd->data,
504 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
505 dev_kfree_skb(*skbuff);
506 }
507 skbuff++;
508 rx_fd++;
509 }
510 }
511
512 static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
513 struct net_device *dev)
514 {
515 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
516 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
517 const int len = RX_MAX(HDLC_MAX_MRU);
518 struct sk_buff *skb;
519 int ret = 0;
520
521 skb = dev_alloc_skb(len);
522 dpriv->rx_skbuff[dirty] = skb;
523 if (skb) {
524 skb->protocol = hdlc_type_trans(skb, dev);
525 rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
526 len, PCI_DMA_FROMDEVICE);
527 } else {
528 rx_fd->data = (u32) NULL;
529 ret = -1;
530 }
531 return ret;
532 }
533
534 /*
535 * IRQ/thread/whatever safe
536 */
537 static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
538 struct net_device *dev, char *msg)
539 {
540 s8 i = 0;
541
542 do {
543 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
544 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
545 msg, i);
546 goto done;
547 }
548 schedule_timeout_uninterruptible(10);
549 rmb();
550 } while (++i > 0);
551 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
552 done:
553 return (i >= 0) ? i : -EAGAIN;
554 }
555
556 static int dscc4_do_action(struct net_device *dev, char *msg)
557 {
558 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
559 s16 i = 0;
560
561 writel(Action, ioaddr + GCMDR);
562 ioaddr += GSTAR;
563 do {
564 u32 state = readl(ioaddr);
565
566 if (state & ArAck) {
567 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
568 writel(ArAck, ioaddr);
569 goto done;
570 } else if (state & Arf) {
571 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
572 writel(Arf, ioaddr);
573 i = -1;
574 goto done;
575 }
576 rmb();
577 } while (++i > 0);
578 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
579 done:
580 return i;
581 }
582
583 static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
584 {
585 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
586 s8 i = 0;
587
588 do {
589 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
590 (dpriv->iqtx[cur] & Xpr))
591 break;
592 smp_rmb();
593 schedule_timeout_uninterruptible(10);
594 } while (++i > 0);
595
596 return (i >= 0 ) ? i : -EAGAIN;
597 }
598
599 #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
600 static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
601 {
602 unsigned long flags;
603
604 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
605 /* Cf errata DS5 p.6 */
606 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
607 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
608 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
609 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
610 writel(Action, dpriv->base_addr + GCMDR);
611 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
612 }
613
614 #endif
615
616 #if 0
617 static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
618 {
619 u16 i = 0;
620
621 /* Cf errata DS5 p.7 */
622 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
623 scc_writel(0x00050000, dpriv, dev, CCR2);
624 /*
625 * Must be longer than the time required to fill the fifo.
626 */
627 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
628 udelay(1);
629 wmb();
630 }
631
632 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
633 if (dscc4_do_action(dev, "Rdt") < 0)
634 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
635 }
636 #endif
637
638 /* TODO: (ab)use this function to refill a completely depleted RX ring. */
639 static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
640 struct net_device *dev)
641 {
642 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
643 struct net_device_stats *stats = hdlc_stats(dev);
644 struct pci_dev *pdev = dpriv->pci_priv->pdev;
645 struct sk_buff *skb;
646 int pkt_len;
647
648 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
649 if (!skb) {
650 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
651 goto refill;
652 }
653 pkt_len = TO_SIZE(rx_fd->state2);
654 pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
655 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
656 stats->rx_packets++;
657 stats->rx_bytes += pkt_len;
658 skb_put(skb, pkt_len);
659 if (netif_running(dev))
660 skb->protocol = hdlc_type_trans(skb, dev);
661 skb->dev->last_rx = jiffies;
662 netif_rx(skb);
663 } else {
664 if (skb->data[pkt_len] & FrameRdo)
665 stats->rx_fifo_errors++;
666 else if (!(skb->data[pkt_len] | ~FrameCrc))
667 stats->rx_crc_errors++;
668 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
669 stats->rx_length_errors++;
670 else
671 stats->rx_errors++;
672 dev_kfree_skb_irq(skb);
673 }
674 refill:
675 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
676 if (try_get_rx_skb(dpriv, dev) < 0)
677 break;
678 dpriv->rx_dirty++;
679 }
680 dscc4_rx_update(dpriv, dev);
681 rx_fd->state2 = 0x00000000;
682 rx_fd->end = 0xbabeface;
683 }
684
685 static void dscc4_free1(struct pci_dev *pdev)
686 {
687 struct dscc4_pci_priv *ppriv;
688 struct dscc4_dev_priv *root;
689 int i;
690
691 ppriv = pci_get_drvdata(pdev);
692 root = ppriv->root;
693
694 for (i = 0; i < dev_per_card; i++)
695 unregister_hdlc_device(dscc4_to_dev(root + i));
696
697 pci_set_drvdata(pdev, NULL);
698
699 for (i = 0; i < dev_per_card; i++)
700 free_netdev(root[i].dev);
701 kfree(root);
702 kfree(ppriv);
703 }
704
705 static int __devinit dscc4_init_one(struct pci_dev *pdev,
706 const struct pci_device_id *ent)
707 {
708 struct dscc4_pci_priv *priv;
709 struct dscc4_dev_priv *dpriv;
710 void __iomem *ioaddr;
711 int i, rc;
712
713 printk(KERN_DEBUG "%s", version);
714
715 rc = pci_enable_device(pdev);
716 if (rc < 0)
717 goto out;
718
719 rc = pci_request_region(pdev, 0, "registers");
720 if (rc < 0) {
721 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
722 DRV_NAME);
723 goto err_disable_0;
724 }
725 rc = pci_request_region(pdev, 1, "LBI interface");
726 if (rc < 0) {
727 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
728 DRV_NAME);
729 goto err_free_mmio_region_1;
730 }
731
732 ioaddr = ioremap(pci_resource_start(pdev, 0),
733 pci_resource_len(pdev, 0));
734 if (!ioaddr) {
735 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
736 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
737 (unsigned long long)pci_resource_start(pdev, 0));
738 rc = -EIO;
739 goto err_free_mmio_regions_2;
740 }
741 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
742 (unsigned long long)pci_resource_start(pdev, 0),
743 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
744
745 /* Cf errata DS5 p.2 */
746 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
747 pci_set_master(pdev);
748
749 rc = dscc4_found1(pdev, ioaddr);
750 if (rc < 0)
751 goto err_iounmap_3;
752
753 priv = pci_get_drvdata(pdev);
754
755 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
756 if (rc < 0) {
757 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
758 goto err_release_4;
759 }
760
761 /* power up/little endian/dma core controlled via lrda/ltda */
762 writel(0x00000001, ioaddr + GMODE);
763 /* Shared interrupt queue */
764 {
765 u32 bits;
766
767 bits = (IRQ_RING_SIZE >> 5) - 1;
768 bits |= bits << 4;
769 bits |= bits << 8;
770 bits |= bits << 16;
771 writel(bits, ioaddr + IQLENR0);
772 }
773 /* Global interrupt queue */
774 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
775 priv->iqcfg = (u32 *) pci_alloc_consistent(pdev,
776 IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma);
777 if (!priv->iqcfg)
778 goto err_free_irq_5;
779 writel(priv->iqcfg_dma, ioaddr + IQCFG);
780
781 rc = -ENOMEM;
782
783 /*
784 * SCC 0-3 private rx/tx irq structures
785 * IQRX/TXi needs to be set soon. Learned it the hard way...
786 */
787 for (i = 0; i < dev_per_card; i++) {
788 dpriv = priv->root + i;
789 dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev,
790 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
791 if (!dpriv->iqtx)
792 goto err_free_iqtx_6;
793 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
794 }
795 for (i = 0; i < dev_per_card; i++) {
796 dpriv = priv->root + i;
797 dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev,
798 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
799 if (!dpriv->iqrx)
800 goto err_free_iqrx_7;
801 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
802 }
803
804 /* Cf application hint. Beware of hard-lock condition on threshold. */
805 writel(0x42104000, ioaddr + FIFOCR1);
806 //writel(0x9ce69800, ioaddr + FIFOCR2);
807 writel(0xdef6d800, ioaddr + FIFOCR2);
808 //writel(0x11111111, ioaddr + FIFOCR4);
809 writel(0x18181818, ioaddr + FIFOCR4);
810 // FIXME: should depend on the chipset revision
811 writel(0x0000000e, ioaddr + FIFOCR3);
812
813 writel(0xff200001, ioaddr + GCMDR);
814
815 rc = 0;
816 out:
817 return rc;
818
819 err_free_iqrx_7:
820 while (--i >= 0) {
821 dpriv = priv->root + i;
822 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
823 dpriv->iqrx, dpriv->iqrx_dma);
824 }
825 i = dev_per_card;
826 err_free_iqtx_6:
827 while (--i >= 0) {
828 dpriv = priv->root + i;
829 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
830 dpriv->iqtx, dpriv->iqtx_dma);
831 }
832 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
833 priv->iqcfg_dma);
834 err_free_irq_5:
835 free_irq(pdev->irq, priv->root);
836 err_release_4:
837 dscc4_free1(pdev);
838 err_iounmap_3:
839 iounmap (ioaddr);
840 err_free_mmio_regions_2:
841 pci_release_region(pdev, 1);
842 err_free_mmio_region_1:
843 pci_release_region(pdev, 0);
844 err_disable_0:
845 pci_disable_device(pdev);
846 goto out;
847 };
848
849 /*
850 * Let's hope the default values are decent enough to protect my
851 * feet from the user's gun - Ueimor
852 */
853 static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
854 struct net_device *dev)
855 {
856 /* No interrupts, SCC core disabled. Let's relax */
857 scc_writel(0x00000000, dpriv, dev, CCR0);
858
859 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
860
861 /*
862 * No address recognition/crc-CCITT/cts enabled
863 * Shared flags transmission disabled - cf errata DS5 p.11
864 * Carrier detect disabled - cf errata p.14
865 * FIXME: carrier detection/polarity may be handled more gracefully.
866 */
867 scc_writel(0x02408000, dpriv, dev, CCR1);
868
869 /* crc not forwarded - Cf errata DS5 p.11 */
870 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
871 // crc forwarded
872 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
873 }
874
875 static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
876 {
877 int ret = 0;
878
879 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
880 ret = -EOPNOTSUPP;
881 else
882 dpriv->pci_priv->xtal_hz = hz;
883
884 return ret;
885 }
886
887 static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
888 {
889 struct dscc4_pci_priv *ppriv;
890 struct dscc4_dev_priv *root;
891 int i, ret = -ENOMEM;
892
893 root = kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL);
894 if (!root) {
895 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
896 goto err_out;
897 }
898 memset(root, 0, dev_per_card*sizeof(*root));
899
900 for (i = 0; i < dev_per_card; i++) {
901 root[i].dev = alloc_hdlcdev(root + i);
902 if (!root[i].dev)
903 goto err_free_dev;
904 }
905
906 ppriv = kmalloc(sizeof(*ppriv), GFP_KERNEL);
907 if (!ppriv) {
908 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
909 goto err_free_dev;
910 }
911 memset(ppriv, 0, sizeof(struct dscc4_pci_priv));
912
913 ppriv->root = root;
914 spin_lock_init(&ppriv->lock);
915
916 for (i = 0; i < dev_per_card; i++) {
917 struct dscc4_dev_priv *dpriv = root + i;
918 struct net_device *d = dscc4_to_dev(dpriv);
919 hdlc_device *hdlc = dev_to_hdlc(d);
920
921 d->base_addr = (unsigned long)ioaddr;
922 d->init = NULL;
923 d->irq = pdev->irq;
924 d->open = dscc4_open;
925 d->stop = dscc4_close;
926 d->set_multicast_list = NULL;
927 d->do_ioctl = dscc4_ioctl;
928 d->tx_timeout = dscc4_tx_timeout;
929 d->watchdog_timeo = TX_TIMEOUT;
930 SET_MODULE_OWNER(d);
931 SET_NETDEV_DEV(d, &pdev->dev);
932
933 dpriv->dev_id = i;
934 dpriv->pci_priv = ppriv;
935 dpriv->base_addr = ioaddr;
936 spin_lock_init(&dpriv->lock);
937
938 hdlc->xmit = dscc4_start_xmit;
939 hdlc->attach = dscc4_hdlc_attach;
940
941 dscc4_init_registers(dpriv, d);
942 dpriv->parity = PARITY_CRC16_PR0_CCITT;
943 dpriv->encoding = ENCODING_NRZ;
944
945 ret = dscc4_init_ring(d);
946 if (ret < 0)
947 goto err_unregister;
948
949 ret = register_hdlc_device(d);
950 if (ret < 0) {
951 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
952 dscc4_release_ring(dpriv);
953 goto err_unregister;
954 }
955 }
956
957 ret = dscc4_set_quartz(root, quartz);
958 if (ret < 0)
959 goto err_unregister;
960
961 pci_set_drvdata(pdev, ppriv);
962 return ret;
963
964 err_unregister:
965 while (i-- > 0) {
966 dscc4_release_ring(root + i);
967 unregister_hdlc_device(dscc4_to_dev(root + i));
968 }
969 kfree(ppriv);
970 i = dev_per_card;
971 err_free_dev:
972 while (i-- > 0)
973 free_netdev(root[i].dev);
974 kfree(root);
975 err_out:
976 return ret;
977 };
978
979 /* FIXME: get rid of the unneeded code */
980 static void dscc4_timer(unsigned long data)
981 {
982 struct net_device *dev = (struct net_device *)data;
983 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
984 // struct dscc4_pci_priv *ppriv;
985
986 goto done;
987 done:
988 dpriv->timer.expires = jiffies + TX_TIMEOUT;
989 add_timer(&dpriv->timer);
990 }
991
992 static void dscc4_tx_timeout(struct net_device *dev)
993 {
994 /* FIXME: something is missing there */
995 }
996
997 static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
998 {
999 sync_serial_settings *settings = &dpriv->settings;
1000
1001 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1002 struct net_device *dev = dscc4_to_dev(dpriv);
1003
1004 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1005 return -1;
1006 }
1007 return 0;
1008 }
1009
1010 #ifdef CONFIG_DSCC4_PCI_RST
1011 /*
1012 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1013 * so as to provide a safe way to reset the asic while not the whole machine
1014 * rebooting.
1015 *
1016 * This code doesn't need to be efficient. Keep It Simple
1017 */
1018 static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1019 {
1020 int i;
1021
1022 mutex_lock(&dscc4_mutex);
1023 for (i = 0; i < 16; i++)
1024 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1025
1026 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1027 writel(0x001c0000, ioaddr + GMODE);
1028 /* Configure GPIO port as output */
1029 writel(0x0000ffff, ioaddr + GPDIR);
1030 /* Disable interruption */
1031 writel(0x0000ffff, ioaddr + GPIM);
1032
1033 writel(0x0000ffff, ioaddr + GPDATA);
1034 writel(0x00000000, ioaddr + GPDATA);
1035
1036 /* Flush posted writes */
1037 readl(ioaddr + GSTAR);
1038
1039 schedule_timeout_uninterruptible(10);
1040
1041 for (i = 0; i < 16; i++)
1042 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
1043 mutex_unlock(&dscc4_mutex);
1044 }
1045 #else
1046 #define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1047 #endif /* CONFIG_DSCC4_PCI_RST */
1048
1049 static int dscc4_open(struct net_device *dev)
1050 {
1051 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1052 struct dscc4_pci_priv *ppriv;
1053 int ret = -EAGAIN;
1054
1055 if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
1056 goto err;
1057
1058 if ((ret = hdlc_open(dev)))
1059 goto err;
1060
1061 ppriv = dpriv->pci_priv;
1062
1063 /*
1064 * Due to various bugs, there is no way to reliably reset a
1065 * specific port (manufacturer's dependant special PCI #RST wiring
1066 * apart: it affects all ports). Thus the device goes in the best
1067 * silent mode possible at dscc4_close() time and simply claims to
1068 * be up if it's opened again. It still isn't possible to change
1069 * the HDLC configuration without rebooting but at least the ports
1070 * can be up/down ifconfig'ed without killing the host.
1071 */
1072 if (dpriv->flags & FakeReset) {
1073 dpriv->flags &= ~FakeReset;
1074 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1075 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1076 scc_writel(EventsMask, dpriv, dev, IMR);
1077 printk(KERN_INFO "%s: up again.\n", dev->name);
1078 goto done;
1079 }
1080
1081 /* IDT+IDR during XPR */
1082 dpriv->flags = NeedIDR | NeedIDT;
1083
1084 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1085
1086 /*
1087 * The following is a bit paranoid...
1088 *
1089 * NB: the datasheet "...CEC will stay active if the SCC is in
1090 * power-down mode or..." and CCR2.RAC = 1 are two different
1091 * situations.
1092 */
1093 if (scc_readl_star(dpriv, dev) & SccBusy) {
1094 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1095 ret = -EAGAIN;
1096 goto err_out;
1097 } else
1098 printk(KERN_INFO "%s: available. Good\n", dev->name);
1099
1100 scc_writel(EventsMask, dpriv, dev, IMR);
1101
1102 /* Posted write is flushed in the wait_ack loop */
1103 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1104
1105 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1106 goto err_disable_scc_events;
1107
1108 /*
1109 * I would expect XPR near CE completion (before ? after ?).
1110 * At worst, this code won't see a late XPR and people
1111 * will have to re-issue an ifconfig (this is harmless).
1112 * WARNING, a really missing XPR usually means a hardware
1113 * reset is needed. Suggestions anyone ?
1114 */
1115 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1116 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1117 goto err_disable_scc_events;
1118 }
1119
1120 if (debug > 2)
1121 dscc4_tx_print(dev, dpriv, "Open");
1122
1123 done:
1124 netif_start_queue(dev);
1125
1126 init_timer(&dpriv->timer);
1127 dpriv->timer.expires = jiffies + 10*HZ;
1128 dpriv->timer.data = (unsigned long)dev;
1129 dpriv->timer.function = &dscc4_timer;
1130 add_timer(&dpriv->timer);
1131 netif_carrier_on(dev);
1132
1133 return 0;
1134
1135 err_disable_scc_events:
1136 scc_writel(0xffffffff, dpriv, dev, IMR);
1137 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138 err_out:
1139 hdlc_close(dev);
1140 err:
1141 return ret;
1142 }
1143
1144 #ifdef DSCC4_POLLING
1145 static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1146 {
1147 /* FIXME: it's gonna be easy (TM), for sure */
1148 }
1149 #endif /* DSCC4_POLLING */
1150
1151 static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1152 {
1153 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1154 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1155 struct TxFD *tx_fd;
1156 int next;
1157
1158 next = dpriv->tx_current%TX_RING_SIZE;
1159 dpriv->tx_skbuff[next] = skb;
1160 tx_fd = dpriv->tx_fd + next;
1161 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
1162 tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
1163 PCI_DMA_TODEVICE);
1164 tx_fd->complete = 0x00000000;
1165 tx_fd->jiffies = jiffies;
1166 mb();
1167
1168 #ifdef DSCC4_POLLING
1169 spin_lock(&dpriv->lock);
1170 while (dscc4_tx_poll(dpriv, dev));
1171 spin_unlock(&dpriv->lock);
1172 #endif
1173
1174 dev->trans_start = jiffies;
1175
1176 if (debug > 2)
1177 dscc4_tx_print(dev, dpriv, "Xmit");
1178 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1179 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1180 netif_stop_queue(dev);
1181
1182 if (dscc4_tx_quiescent(dpriv, dev))
1183 dscc4_do_tx(dpriv, dev);
1184
1185 return 0;
1186 }
1187
1188 static int dscc4_close(struct net_device *dev)
1189 {
1190 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1191
1192 del_timer_sync(&dpriv->timer);
1193 netif_stop_queue(dev);
1194
1195 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1196 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1197 scc_writel(0xffffffff, dpriv, dev, IMR);
1198
1199 dpriv->flags |= FakeReset;
1200
1201 hdlc_close(dev);
1202
1203 return 0;
1204 }
1205
1206 static inline int dscc4_check_clock_ability(int port)
1207 {
1208 int ret = 0;
1209
1210 #ifdef CONFIG_DSCC4_PCISYNC
1211 if (port >= 2)
1212 ret = -1;
1213 #endif
1214 return ret;
1215 }
1216
1217 /*
1218 * DS1 p.137: "There are a total of 13 different clocking modes..."
1219 * ^^
1220 * Design choices:
1221 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1222 * Clock mode 3b _should_ work but the testing seems to make this point
1223 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1224 * This is supposed to provide least surprise "DTE like" behavior.
1225 * - if line rate is specified, clocks are assumed to be locally generated.
1226 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1227 * between these it automagically done according on the required frequency
1228 * scaling. Of course some rounding may take place.
1229 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1230 * appropriate external clocking device for testing.
1231 * - no time-slot/clock mode 5: shameless lazyness.
1232 *
1233 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1234 *
1235 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1236 * won't pass the init sequence. For example, straight back-to-back DTE without
1237 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1238 * called.
1239 *
1240 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1241 * DS0 for example)
1242 *
1243 * Clock mode related bits of CCR0:
1244 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1245 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1246 * | | +-------- High Speed: say 0
1247 * | | | +-+-+-- Clock Mode: 0..7
1248 * | | | | | |
1249 * -+-+-+-+-+-+-+-+
1250 * x|x|5|4|3|2|1|0| lower bits
1251 *
1252 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1253 * +-+-+-+------------------ M (0..15)
1254 * | | | | +-+-+-+-+-+-- N (0..63)
1255 * 0 0 0 0 | | | | 0 0 | | | | | |
1256 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1257 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1258 *
1259 */
1260 static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1261 {
1262 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1263 int ret = -1;
1264 u32 brr;
1265
1266 *state &= ~Ccr0ClockMask;
1267 if (*bps) { /* Clock generated - required for DCE */
1268 u32 n = 0, m = 0, divider;
1269 int xtal;
1270
1271 xtal = dpriv->pci_priv->xtal_hz;
1272 if (!xtal)
1273 goto done;
1274 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1275 goto done;
1276 divider = xtal / *bps;
1277 if (divider > BRR_DIVIDER_MAX) {
1278 divider >>= 4;
1279 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1280 } else
1281 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1282 if (divider >> 22) {
1283 n = 63;
1284 m = 15;
1285 } else if (divider) {
1286 /* Extraction of the 6 highest weighted bits */
1287 m = 0;
1288 while (0xffffffc0 & divider) {
1289 m++;
1290 divider >>= 1;
1291 }
1292 n = divider;
1293 }
1294 brr = (m << 8) | n;
1295 divider = n << m;
1296 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1297 divider <<= 4;
1298 *bps = xtal / divider;
1299 } else {
1300 /*
1301 * External clock - DTE
1302 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1303 * Nothing more to be done
1304 */
1305 brr = 0;
1306 }
1307 scc_writel(brr, dpriv, dev, BRR);
1308 ret = 0;
1309 done:
1310 return ret;
1311 }
1312
1313 static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1314 {
1315 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1316 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1317 const size_t size = sizeof(dpriv->settings);
1318 int ret = 0;
1319
1320 if (dev->flags & IFF_UP)
1321 return -EBUSY;
1322
1323 if (cmd != SIOCWANDEV)
1324 return -EOPNOTSUPP;
1325
1326 switch(ifr->ifr_settings.type) {
1327 case IF_GET_IFACE:
1328 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1329 if (ifr->ifr_settings.size < size) {
1330 ifr->ifr_settings.size = size; /* data size wanted */
1331 return -ENOBUFS;
1332 }
1333 if (copy_to_user(line, &dpriv->settings, size))
1334 return -EFAULT;
1335 break;
1336
1337 case IF_IFACE_SYNC_SERIAL:
1338 if (!capable(CAP_NET_ADMIN))
1339 return -EPERM;
1340
1341 if (dpriv->flags & FakeReset) {
1342 printk(KERN_INFO "%s: please reset the device"
1343 " before this command\n", dev->name);
1344 return -EPERM;
1345 }
1346 if (copy_from_user(&dpriv->settings, line, size))
1347 return -EFAULT;
1348 ret = dscc4_set_iface(dpriv, dev);
1349 break;
1350
1351 default:
1352 ret = hdlc_ioctl(dev, ifr, cmd);
1353 break;
1354 }
1355
1356 return ret;
1357 }
1358
1359 static int dscc4_match(struct thingie *p, int value)
1360 {
1361 int i;
1362
1363 for (i = 0; p[i].define != -1; i++) {
1364 if (value == p[i].define)
1365 break;
1366 }
1367 if (p[i].define == -1)
1368 return -1;
1369 else
1370 return i;
1371 }
1372
1373 static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1374 struct net_device *dev)
1375 {
1376 sync_serial_settings *settings = &dpriv->settings;
1377 int ret = -EOPNOTSUPP;
1378 u32 bps, state;
1379
1380 bps = settings->clock_rate;
1381 state = scc_readl(dpriv, CCR0);
1382 if (dscc4_set_clock(dev, &bps, &state) < 0)
1383 goto done;
1384 if (bps) { /* DCE */
1385 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1386 if (settings->clock_rate != bps) {
1387 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1388 dev->name, settings->clock_rate, bps);
1389 settings->clock_rate = bps;
1390 }
1391 } else { /* DTE */
1392 state |= PowerUp | Vis;
1393 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1394 }
1395 scc_writel(state, dpriv, dev, CCR0);
1396 ret = 0;
1397 done:
1398 return ret;
1399 }
1400
1401 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1402 struct net_device *dev)
1403 {
1404 struct thingie encoding[] = {
1405 { ENCODING_NRZ, 0x00000000 },
1406 { ENCODING_NRZI, 0x00200000 },
1407 { ENCODING_FM_MARK, 0x00400000 },
1408 { ENCODING_FM_SPACE, 0x00500000 },
1409 { ENCODING_MANCHESTER, 0x00600000 },
1410 { -1, 0}
1411 };
1412 int i, ret = 0;
1413
1414 i = dscc4_match(encoding, dpriv->encoding);
1415 if (i >= 0)
1416 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1417 else
1418 ret = -EOPNOTSUPP;
1419 return ret;
1420 }
1421
1422 static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1423 struct net_device *dev)
1424 {
1425 sync_serial_settings *settings = &dpriv->settings;
1426 u32 state;
1427
1428 state = scc_readl(dpriv, CCR1);
1429 if (settings->loopback) {
1430 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1431 state |= 0x00000100;
1432 } else {
1433 printk(KERN_DEBUG "%s: normal\n", dev->name);
1434 state &= ~0x00000100;
1435 }
1436 scc_writel(state, dpriv, dev, CCR1);
1437 return 0;
1438 }
1439
1440 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1441 struct net_device *dev)
1442 {
1443 struct thingie crc[] = {
1444 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1445 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1446 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1447 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1448 };
1449 int i, ret = 0;
1450
1451 i = dscc4_match(crc, dpriv->parity);
1452 if (i >= 0)
1453 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1454 else
1455 ret = -EOPNOTSUPP;
1456 return ret;
1457 }
1458
1459 static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1460 {
1461 struct {
1462 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1463 } *p, do_setting[] = {
1464 { dscc4_encoding_setting },
1465 { dscc4_clock_setting },
1466 { dscc4_loopback_setting },
1467 { dscc4_crc_setting },
1468 { NULL }
1469 };
1470 int ret = 0;
1471
1472 for (p = do_setting; p->action; p++) {
1473 if ((ret = p->action(dpriv, dev)) < 0)
1474 break;
1475 }
1476 return ret;
1477 }
1478
1479 static irqreturn_t dscc4_irq(int irq, void *token)
1480 {
1481 struct dscc4_dev_priv *root = token;
1482 struct dscc4_pci_priv *priv;
1483 struct net_device *dev;
1484 void __iomem *ioaddr;
1485 u32 state;
1486 unsigned long flags;
1487 int i, handled = 1;
1488
1489 priv = root->pci_priv;
1490 dev = dscc4_to_dev(root);
1491
1492 spin_lock_irqsave(&priv->lock, flags);
1493
1494 ioaddr = root->base_addr;
1495
1496 state = readl(ioaddr + GSTAR);
1497 if (!state) {
1498 handled = 0;
1499 goto out;
1500 }
1501 if (debug > 3)
1502 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1503 writel(state, ioaddr + GSTAR);
1504
1505 if (state & Arf) {
1506 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1507 dev->name);
1508 goto out;
1509 }
1510 state &= ~ArAck;
1511 if (state & Cfg) {
1512 if (debug > 0)
1513 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
1514 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
1515 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1516 if (!(state &= ~Cfg))
1517 goto out;
1518 }
1519 if (state & RxEvt) {
1520 i = dev_per_card - 1;
1521 do {
1522 dscc4_rx_irq(priv, root + i);
1523 } while (--i >= 0);
1524 state &= ~RxEvt;
1525 }
1526 if (state & TxEvt) {
1527 i = dev_per_card - 1;
1528 do {
1529 dscc4_tx_irq(priv, root + i);
1530 } while (--i >= 0);
1531 state &= ~TxEvt;
1532 }
1533 out:
1534 spin_unlock_irqrestore(&priv->lock, flags);
1535 return IRQ_RETVAL(handled);
1536 }
1537
1538 static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1539 struct dscc4_dev_priv *dpriv)
1540 {
1541 struct net_device *dev = dscc4_to_dev(dpriv);
1542 u32 state;
1543 int cur, loop = 0;
1544
1545 try:
1546 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
1547 state = dpriv->iqtx[cur];
1548 if (!state) {
1549 if (debug > 4)
1550 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1551 state);
1552 if ((debug > 1) && (loop > 1))
1553 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1554 if (loop && netif_queue_stopped(dev))
1555 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1556 netif_wake_queue(dev);
1557
1558 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1559 !dscc4_tx_done(dpriv))
1560 dscc4_do_tx(dpriv, dev);
1561 return;
1562 }
1563 loop++;
1564 dpriv->iqtx[cur] = 0;
1565 dpriv->iqtx_current++;
1566
1567 if (state_check(state, dpriv, dev, "Tx") < 0)
1568 return;
1569
1570 if (state & SccEvt) {
1571 if (state & Alls) {
1572 struct net_device_stats *stats = hdlc_stats(dev);
1573 struct sk_buff *skb;
1574 struct TxFD *tx_fd;
1575
1576 if (debug > 2)
1577 dscc4_tx_print(dev, dpriv, "Alls");
1578 /*
1579 * DataComplete can't be trusted for Tx completion.
1580 * Cf errata DS5 p.8
1581 */
1582 cur = dpriv->tx_dirty%TX_RING_SIZE;
1583 tx_fd = dpriv->tx_fd + cur;
1584 skb = dpriv->tx_skbuff[cur];
1585 if (skb) {
1586 pci_unmap_single(ppriv->pdev, tx_fd->data,
1587 skb->len, PCI_DMA_TODEVICE);
1588 if (tx_fd->state & FrameEnd) {
1589 stats->tx_packets++;
1590 stats->tx_bytes += skb->len;
1591 }
1592 dev_kfree_skb_irq(skb);
1593 dpriv->tx_skbuff[cur] = NULL;
1594 ++dpriv->tx_dirty;
1595 } else {
1596 if (debug > 1)
1597 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1598 dev->name, cur);
1599 }
1600 /*
1601 * If the driver ends sending crap on the wire, it
1602 * will be way easier to diagnose than the (not so)
1603 * random freeze induced by null sized tx frames.
1604 */
1605 tx_fd->data = tx_fd->next;
1606 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1607 tx_fd->complete = 0x00000000;
1608 tx_fd->jiffies = 0;
1609
1610 if (!(state &= ~Alls))
1611 goto try;
1612 }
1613 /*
1614 * Transmit Data Underrun
1615 */
1616 if (state & Xdu) {
1617 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1618 dpriv->flags = NeedIDT;
1619 /* Tx reset */
1620 writel(MTFi | Rdt,
1621 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1622 writel(Action, dpriv->base_addr + GCMDR);
1623 return;
1624 }
1625 if (state & Cts) {
1626 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1627 if (!(state &= ~Cts)) /* DEBUG */
1628 goto try;
1629 }
1630 if (state & Xmr) {
1631 /* Frame needs to be sent again - FIXME */
1632 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1633 if (!(state &= ~Xmr)) /* DEBUG */
1634 goto try;
1635 }
1636 if (state & Xpr) {
1637 void __iomem *scc_addr;
1638 unsigned long ring;
1639 int i;
1640
1641 /*
1642 * - the busy condition happens (sometimes);
1643 * - it doesn't seem to make the handler unreliable.
1644 */
1645 for (i = 1; i; i <<= 1) {
1646 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1647 break;
1648 }
1649 if (!i)
1650 printk(KERN_INFO "%s busy in irq\n", dev->name);
1651
1652 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1653 /* Keep this order: IDT before IDR */
1654 if (dpriv->flags & NeedIDT) {
1655 if (debug > 2)
1656 dscc4_tx_print(dev, dpriv, "Xpr");
1657 ring = dpriv->tx_fd_dma +
1658 (dpriv->tx_dirty%TX_RING_SIZE)*
1659 sizeof(struct TxFD);
1660 writel(ring, scc_addr + CH0BTDA);
1661 dscc4_do_tx(dpriv, dev);
1662 writel(MTFi | Idt, scc_addr + CH0CFG);
1663 if (dscc4_do_action(dev, "IDT") < 0)
1664 goto err_xpr;
1665 dpriv->flags &= ~NeedIDT;
1666 }
1667 if (dpriv->flags & NeedIDR) {
1668 ring = dpriv->rx_fd_dma +
1669 (dpriv->rx_current%RX_RING_SIZE)*
1670 sizeof(struct RxFD);
1671 writel(ring, scc_addr + CH0BRDA);
1672 dscc4_rx_update(dpriv, dev);
1673 writel(MTFi | Idr, scc_addr + CH0CFG);
1674 if (dscc4_do_action(dev, "IDR") < 0)
1675 goto err_xpr;
1676 dpriv->flags &= ~NeedIDR;
1677 smp_wmb();
1678 /* Activate receiver and misc */
1679 scc_writel(0x08050008, dpriv, dev, CCR2);
1680 }
1681 err_xpr:
1682 if (!(state &= ~Xpr))
1683 goto try;
1684 }
1685 if (state & Cd) {
1686 if (debug > 0)
1687 printk(KERN_INFO "%s: CD transition\n", dev->name);
1688 if (!(state &= ~Cd)) /* DEBUG */
1689 goto try;
1690 }
1691 } else { /* ! SccEvt */
1692 if (state & Hi) {
1693 #ifdef DSCC4_POLLING
1694 while (!dscc4_tx_poll(dpriv, dev));
1695 #endif
1696 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1697 state &= ~Hi;
1698 }
1699 if (state & Err) {
1700 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
1701 hdlc_stats(dev)->tx_errors++;
1702 state &= ~Err;
1703 }
1704 }
1705 goto try;
1706 }
1707
1708 static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1709 struct dscc4_dev_priv *dpriv)
1710 {
1711 struct net_device *dev = dscc4_to_dev(dpriv);
1712 u32 state;
1713 int cur;
1714
1715 try:
1716 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
1717 state = dpriv->iqrx[cur];
1718 if (!state)
1719 return;
1720 dpriv->iqrx[cur] = 0;
1721 dpriv->iqrx_current++;
1722
1723 if (state_check(state, dpriv, dev, "Rx") < 0)
1724 return;
1725
1726 if (!(state & SccEvt)){
1727 struct RxFD *rx_fd;
1728
1729 if (debug > 4)
1730 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1731 state);
1732 state &= 0x00ffffff;
1733 if (state & Err) { /* Hold or reset */
1734 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1735 cur = dpriv->rx_current%RX_RING_SIZE;
1736 rx_fd = dpriv->rx_fd + cur;
1737 /*
1738 * Presume we're not facing a DMAC receiver reset.
1739 * As We use the rx size-filtering feature of the
1740 * DSCC4, the beginning of a new frame is waiting in
1741 * the rx fifo. I bet a Receive Data Overflow will
1742 * happen most of time but let's try and avoid it.
1743 * Btw (as for RDO) if one experiences ERR whereas
1744 * the system looks rather idle, there may be a
1745 * problem with latency. In this case, increasing
1746 * RX_RING_SIZE may help.
1747 */
1748 //while (dpriv->rx_needs_refill) {
1749 while (!(rx_fd->state1 & Hold)) {
1750 rx_fd++;
1751 cur++;
1752 if (!(cur = cur%RX_RING_SIZE))
1753 rx_fd = dpriv->rx_fd;
1754 }
1755 //dpriv->rx_needs_refill--;
1756 try_get_rx_skb(dpriv, dev);
1757 if (!rx_fd->data)
1758 goto try;
1759 rx_fd->state1 &= ~Hold;
1760 rx_fd->state2 = 0x00000000;
1761 rx_fd->end = 0xbabeface;
1762 //}
1763 goto try;
1764 }
1765 if (state & Fi) {
1766 dscc4_rx_skb(dpriv, dev);
1767 goto try;
1768 }
1769 if (state & Hi ) { /* HI bit */
1770 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1771 state &= ~Hi;
1772 goto try;
1773 }
1774 } else { /* SccEvt */
1775 if (debug > 1) {
1776 //FIXME: verifier la presence de tous les evenements
1777 static struct {
1778 u32 mask;
1779 const char *irq_name;
1780 } evts[] = {
1781 { 0x00008000, "TIN"},
1782 { 0x00000020, "RSC"},
1783 { 0x00000010, "PCE"},
1784 { 0x00000008, "PLLA"},
1785 { 0, NULL}
1786 }, *evt;
1787
1788 for (evt = evts; evt->irq_name; evt++) {
1789 if (state & evt->mask) {
1790 printk(KERN_DEBUG "%s: %s\n",
1791 dev->name, evt->irq_name);
1792 if (!(state &= ~evt->mask))
1793 goto try;
1794 }
1795 }
1796 } else {
1797 if (!(state &= ~0x0000c03c))
1798 goto try;
1799 }
1800 if (state & Cts) {
1801 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1802 if (!(state &= ~Cts)) /* DEBUG */
1803 goto try;
1804 }
1805 /*
1806 * Receive Data Overflow (FIXME: fscked)
1807 */
1808 if (state & Rdo) {
1809 struct RxFD *rx_fd;
1810 void __iomem *scc_addr;
1811 int cur;
1812
1813 //if (debug)
1814 // dscc4_rx_dump(dpriv);
1815 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1816
1817 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1818 /*
1819 * This has no effect. Why ?
1820 * ORed with TxSccRes, one sees the CFG ack (for
1821 * the TX part only).
1822 */
1823 scc_writel(RxSccRes, dpriv, dev, CMDR);
1824 dpriv->flags |= RdoSet;
1825
1826 /*
1827 * Let's try and save something in the received data.
1828 * rx_current must be incremented at least once to
1829 * avoid HOLD in the BRDA-to-be-pointed desc.
1830 */
1831 do {
1832 cur = dpriv->rx_current++%RX_RING_SIZE;
1833 rx_fd = dpriv->rx_fd + cur;
1834 if (!(rx_fd->state2 & DataComplete))
1835 break;
1836 if (rx_fd->state2 & FrameAborted) {
1837 hdlc_stats(dev)->rx_over_errors++;
1838 rx_fd->state1 |= Hold;
1839 rx_fd->state2 = 0x00000000;
1840 rx_fd->end = 0xbabeface;
1841 } else
1842 dscc4_rx_skb(dpriv, dev);
1843 } while (1);
1844
1845 if (debug > 0) {
1846 if (dpriv->flags & RdoSet)
1847 printk(KERN_DEBUG
1848 "%s: no RDO in Rx data\n", DRV_NAME);
1849 }
1850 #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1851 /*
1852 * FIXME: must the reset be this violent ?
1853 */
1854 #warning "FIXME: CH0BRDA"
1855 writel(dpriv->rx_fd_dma +
1856 (dpriv->rx_current%RX_RING_SIZE)*
1857 sizeof(struct RxFD), scc_addr + CH0BRDA);
1858 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1859 if (dscc4_do_action(dev, "RDR") < 0) {
1860 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1861 dev->name, "RDR");
1862 goto rdo_end;
1863 }
1864 writel(MTFi|Idr, scc_addr + CH0CFG);
1865 if (dscc4_do_action(dev, "IDR") < 0) {
1866 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1867 dev->name, "IDR");
1868 goto rdo_end;
1869 }
1870 rdo_end:
1871 #endif
1872 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1873 goto try;
1874 }
1875 if (state & Cd) {
1876 printk(KERN_INFO "%s: CD transition\n", dev->name);
1877 if (!(state &= ~Cd)) /* DEBUG */
1878 goto try;
1879 }
1880 if (state & Flex) {
1881 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1882 if (!(state &= ~Flex))
1883 goto try;
1884 }
1885 }
1886 }
1887
1888 /*
1889 * I had expected the following to work for the first descriptor
1890 * (tx_fd->state = 0xc0000000)
1891 * - Hold=1 (don't try and branch to the next descripto);
1892 * - No=0 (I want an empty data section, i.e. size=0);
1893 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1894 * It failed and locked solid. Thus the introduction of a dummy skb.
1895 * Problem is acknowledged in errata sheet DS5. Joy :o/
1896 */
1897 static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1898 {
1899 struct sk_buff *skb;
1900
1901 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1902 if (skb) {
1903 int last = dpriv->tx_dirty%TX_RING_SIZE;
1904 struct TxFD *tx_fd = dpriv->tx_fd + last;
1905
1906 skb->len = DUMMY_SKB_SIZE;
1907 memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE);
1908 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
1909 tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
1910 DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
1911 dpriv->tx_skbuff[last] = skb;
1912 }
1913 return skb;
1914 }
1915
1916 static int dscc4_init_ring(struct net_device *dev)
1917 {
1918 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1919 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1920 struct TxFD *tx_fd;
1921 struct RxFD *rx_fd;
1922 void *ring;
1923 int i;
1924
1925 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1926 if (!ring)
1927 goto err_out;
1928 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1929
1930 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1931 if (!ring)
1932 goto err_free_dma_rx;
1933 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1934
1935 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1936 dpriv->tx_dirty = 0xffffffff;
1937 i = dpriv->tx_current = 0;
1938 do {
1939 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1940 tx_fd->complete = 0x00000000;
1941 /* FIXME: NULL should be ok - to be tried */
1942 tx_fd->data = dpriv->tx_fd_dma;
1943 (tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
1944 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1945 } while (i < TX_RING_SIZE);
1946
1947 if (!dscc4_init_dummy_skb(dpriv))
1948 goto err_free_dma_tx;
1949
1950 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1951 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1952 do {
1953 /* size set by the host. Multiple of 4 bytes please */
1954 rx_fd->state1 = HiDesc;
1955 rx_fd->state2 = 0x00000000;
1956 rx_fd->end = 0xbabeface;
1957 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1958 // FIXME: return value verifiee mais traitement suspect
1959 if (try_get_rx_skb(dpriv, dev) >= 0)
1960 dpriv->rx_dirty++;
1961 (rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
1962 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1963 } while (i < RX_RING_SIZE);
1964
1965 return 0;
1966
1967 err_free_dma_tx:
1968 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1969 err_free_dma_rx:
1970 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1971 err_out:
1972 return -ENOMEM;
1973 }
1974
1975 static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1976 {
1977 struct dscc4_pci_priv *ppriv;
1978 struct dscc4_dev_priv *root;
1979 void __iomem *ioaddr;
1980 int i;
1981
1982 ppriv = pci_get_drvdata(pdev);
1983 root = ppriv->root;
1984
1985 ioaddr = root->base_addr;
1986
1987 dscc4_pci_reset(pdev, ioaddr);
1988
1989 free_irq(pdev->irq, root);
1990 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1991 ppriv->iqcfg_dma);
1992 for (i = 0; i < dev_per_card; i++) {
1993 struct dscc4_dev_priv *dpriv = root + i;
1994
1995 dscc4_release_ring(dpriv);
1996 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1997 dpriv->iqrx, dpriv->iqrx_dma);
1998 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1999 dpriv->iqtx, dpriv->iqtx_dma);
2000 }
2001
2002 dscc4_free1(pdev);
2003
2004 iounmap(ioaddr);
2005
2006 pci_release_region(pdev, 1);
2007 pci_release_region(pdev, 0);
2008
2009 pci_disable_device(pdev);
2010 }
2011
2012 static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2013 unsigned short parity)
2014 {
2015 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2016
2017 if (encoding != ENCODING_NRZ &&
2018 encoding != ENCODING_NRZI &&
2019 encoding != ENCODING_FM_MARK &&
2020 encoding != ENCODING_FM_SPACE &&
2021 encoding != ENCODING_MANCHESTER)
2022 return -EINVAL;
2023
2024 if (parity != PARITY_NONE &&
2025 parity != PARITY_CRC16_PR0_CCITT &&
2026 parity != PARITY_CRC16_PR1_CCITT &&
2027 parity != PARITY_CRC32_PR0_CCITT &&
2028 parity != PARITY_CRC32_PR1_CCITT)
2029 return -EINVAL;
2030
2031 dpriv->encoding = encoding;
2032 dpriv->parity = parity;
2033 return 0;
2034 }
2035
2036 #ifndef MODULE
2037 static int __init dscc4_setup(char *str)
2038 {
2039 int *args[] = { &debug, &quartz, NULL }, **p = args;
2040
2041 while (*p && (get_option(&str, *p) == 2))
2042 p++;
2043 return 1;
2044 }
2045
2046 __setup("dscc4.setup=", dscc4_setup);
2047 #endif
2048
2049 static struct pci_device_id dscc4_pci_tbl[] = {
2050 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2051 PCI_ANY_ID, PCI_ANY_ID, },
2052 { 0,}
2053 };
2054 MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2055
2056 static struct pci_driver dscc4_driver = {
2057 .name = DRV_NAME,
2058 .id_table = dscc4_pci_tbl,
2059 .probe = dscc4_init_one,
2060 .remove = __devexit_p(dscc4_remove_one),
2061 };
2062
2063 static int __init dscc4_init_module(void)
2064 {
2065 return pci_register_driver(&dscc4_driver);
2066 }
2067
2068 static void __exit dscc4_cleanup_module(void)
2069 {
2070 pci_unregister_driver(&dscc4_driver);
2071 }
2072
2073 module_init(dscc4_init_module);
2074 module_exit(dscc4_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)