drivers/net/wan/c101.c

   1 /*
   2  * Moxa C101 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
  11  *
  12  * Sources of information:
  13  *    Hitachi HD64570 SCA User's Manual
  14  *    Moxa C101 User's Manual
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/hdlc.h>
  27 #include <linux/delay.h>
  28 #include <asm/io.h>
  29
  30 #include "hd64570.h"
  31
  32
  33 static const char* version = "Moxa C101 driver version: 1.15";
  34 static const char* devname = "C101";
  35
  36 #undef DEBUG_PKT
  37 #define DEBUG_RINGS
  38
  39 #define C101_PAGE 0x1D00
  40 #define C101_DTR 0x1E00
  41 #define C101_SCA 0x1F00
  42 #define C101_WINDOW_SIZE 0x2000
  43 #define C101_MAPPED_RAM_SIZE 0x4000
  44
  45 #define RAM_SIZE (256 * 1024)
  46 #define TX_RING_BUFFERS 10
  47 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /                \
  48                          (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
  49
  50 #define CLOCK_BASE 9830400      /* 9.8304 MHz */
  51 #define PAGE0_ALWAYS_MAPPED
  52
  53 static char *hw;                /* pointer to hw=xxx command line string */
  54
  55
  56 typedef struct card_s {
  57         struct net_device *dev;
  58         spinlock_t lock;        /* TX lock */
  59         u8 __iomem *win0base;   /* ISA window base address */
  60         u32 phy_winbase;        /* ISA physical base address */
  61         sync_serial_settings settings;
  62         int rxpart;             /* partial frame received, next frame invalid*/
  63         unsigned short encoding;
  64         unsigned short parity;
  65         u16 rx_ring_buffers;    /* number of buffers in a ring */
  66         u16 tx_ring_buffers;
  67         u16 buff_offset;        /* offset of first buffer of first channel */
  68         u16 rxin;               /* rx ring buffer 'in' pointer */
  69         u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  70         u16 txlast;
  71         u8 rxs, txs, tmc;       /* SCA registers */
  72         u8 irq;                 /* IRQ (3-15) */
  73         u8 page;
  74
  75         struct card_s *next_card;
  76 }card_t;
  77
  78 typedef card_t port_t;
  79
  80 static card_t *first_card;
  81 static card_t **new_card = &first_card;
  82
  83
  84 #define sca_in(reg, card)          readb((card)->win0base + C101_SCA + (reg))
  85 #define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
  86 #define sca_inw(reg, card)         readw((card)->win0base + C101_SCA + (reg))
  87
  88 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
  89 #define sca_outw(value, reg, card) do { \
  90         writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
  91         writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
  92 } while(0)
  93
  94 #define port_to_card(port)         (port)
  95 #define log_node(port)             (0)
  96 #define phy_node(port)             (0)
  97 #define winsize(card)              (C101_WINDOW_SIZE)
  98 #define win0base(card)             ((card)->win0base)
  99 #define winbase(card)              ((card)->win0base + 0x2000)
 100 #define get_port(card, port)       (card)
 101 static void sca_msci_intr(port_t *port);
 102
 103
 104 static inline u8 sca_get_page(card_t *card)
 105 {
 106         return card->page;
 107 }
 108
 109 static inline void openwin(card_t *card, u8 page)
 110 {
 111         card->page = page;
 112         writeb(page, card->win0base + C101_PAGE);
 113 }
 114
 115
 116 #include "hd6457x.c"
 117
 118
 119 static inline void set_carrier(port_t *port)
 120 {
 121         if (!sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD)
 122                 netif_carrier_on(port_to_dev(port));
 123         else
 124                 netif_carrier_off(port_to_dev(port));
 125 }
 126
 127
 128 static void sca_msci_intr(port_t *port)
 129 {
 130         u8 stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI ST1 status */
 131
 132         /* Reset MSCI TX underrun status bit */
 133         sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, port);
 134
 135         if (stat & ST1_UDRN) {
 136                 struct net_device_stats *stats = hdlc_stats(port_to_dev(port));
 137                 stats->tx_errors++; /* TX Underrun error detected */
 138                 stats->tx_fifo_errors++;
 139         }
 140
 141         /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
 142         sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
 143
 144         if (stat & ST1_CDCD)
 145                 set_carrier(port);
 146 }
 147
 148
 149 static void c101_set_iface(port_t *port)
 150 {
 151         u8 rxs = port->rxs & CLK_BRG_MASK;
 152         u8 txs = port->txs & CLK_BRG_MASK;
 153
 154         switch(port->settings.clock_type) {
 155         case CLOCK_INT:
 156                 rxs |= CLK_BRG_RX; /* TX clock */
 157                 txs |= CLK_RXCLK_TX; /* BRG output */
 158                 break;
 159
 160         case CLOCK_TXINT:
 161                 rxs |= CLK_LINE_RX; /* RXC input */
 162                 txs |= CLK_BRG_TX; /* BRG output */
 163                 break;
 164
 165         case CLOCK_TXFROMRX:
 166                 rxs |= CLK_LINE_RX; /* RXC input */
 167                 txs |= CLK_RXCLK_TX; /* RX clock */
 168                 break;
 169
 170         default:        /* EXTernal clock */
 171                 rxs |= CLK_LINE_RX; /* RXC input */
 172                 txs |= CLK_LINE_TX; /* TXC input */
 173         }
 174
 175         port->rxs = rxs;
 176         port->txs = txs;
 177         sca_out(rxs, MSCI1_OFFSET + RXS, port);
 178         sca_out(txs, MSCI1_OFFSET + TXS, port);
 179         sca_set_port(port);
 180 }
 181
 182
 183 static int c101_open(struct net_device *dev)
 184 {
 185         port_t *port = dev_to_port(dev);
 186         int result;
 187
 188         result = hdlc_open(dev);
 189         if (result)
 190                 return result;
 191
 192         writeb(1, port->win0base + C101_DTR);
 193         sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
 194         sca_open(dev);
 195         /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
 196         sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
 197         sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
 198
 199         set_carrier(port);
 200
 201         /* enable MSCI1 CDCD interrupt */
 202         sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
 203         sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
 204         sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
 205         c101_set_iface(port);
 206         return 0;
 207 }
 208
 209
 210 static int c101_close(struct net_device *dev)
 211 {
 212         port_t *port = dev_to_port(dev);
 213
 214         sca_close(dev);
 215         writeb(0, port->win0base + C101_DTR);
 216         sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 217         hdlc_close(dev);
 218         return 0;
 219 }
 220
 221
 222 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 223 {
 224         const size_t size = sizeof(sync_serial_settings);
 225         sync_serial_settings new_line;
 226         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 227         port_t *port = dev_to_port(dev);
 228
 229 #ifdef DEBUG_RINGS
 230         if (cmd == SIOCDEVPRIVATE) {
 231                 sca_dump_rings(dev);
 232                 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
 233                        sca_in(MSCI1_OFFSET + ST0, port),
 234                        sca_in(MSCI1_OFFSET + ST1, port),
 235                        sca_in(MSCI1_OFFSET + ST2, port),
 236                        sca_in(MSCI1_OFFSET + ST3, port));
 237                 return 0;
 238         }
 239 #endif
 240         if (cmd != SIOCWANDEV)
 241                 return hdlc_ioctl(dev, ifr, cmd);
 242
 243         switch(ifr->ifr_settings.type) {
 244         case IF_GET_IFACE:
 245                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 246                 if (ifr->ifr_settings.size < size) {
 247                         ifr->ifr_settings.size = size; /* data size wanted */
 248                         return -ENOBUFS;
 249                 }
 250                 if (copy_to_user(line, &port->settings, size))
 251                         return -EFAULT;
 252                 return 0;
 253
 254         case IF_IFACE_SYNC_SERIAL:
 255                 if(!capable(CAP_NET_ADMIN))
 256                         return -EPERM;
 257
 258                 if (copy_from_user(&new_line, line, size))
 259                         return -EFAULT;
 260
 261                 if (new_line.clock_type != CLOCK_EXT &&
 262                     new_line.clock_type != CLOCK_TXFROMRX &&
 263                     new_line.clock_type != CLOCK_INT &&
 264                     new_line.clock_type != CLOCK_TXINT)
 265                 return -EINVAL; /* No such clock setting */
 266
 267                 if (new_line.loopback != 0 && new_line.loopback != 1)
 268                         return -EINVAL;
 269
 270                 memcpy(&port->settings, &new_line, size); /* Update settings */
 271                 c101_set_iface(port);
 272                 return 0;
 273
 274         default:
 275                 return hdlc_ioctl(dev, ifr, cmd);
 276         }
 277 }
 278
 279
 280
 281 static void c101_destroy_card(card_t *card)
 282 {
 283         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 284
 285         if (card->irq)
 286                 free_irq(card->irq, card);
 287
 288         if (card->win0base) {
 289                 iounmap(card->win0base);
 290                 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
 291         }
 292
 293         free_netdev(card->dev);
 294
 295         kfree(card);
 296 }
 297
 298
 299
 300 static int __init c101_run(unsigned long irq, unsigned long winbase)
 301 {
 302         struct net_device *dev;
 303         hdlc_device *hdlc;
 304         card_t *card;
 305         int result;
 306
 307         if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
 308                 printk(KERN_ERR "c101: invalid IRQ value\n");
 309                 return -ENODEV;
 310         }
 311
 312         if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
 313                 printk(KERN_ERR "c101: invalid RAM value\n");
 314                 return -ENODEV;
 315         }
 316
 317         card = kmalloc(sizeof(card_t), GFP_KERNEL);
 318         if (card == NULL) {
 319                 printk(KERN_ERR "c101: unable to allocate memory\n");
 320                 return -ENOBUFS;
 321         }
 322         memset(card, 0, sizeof(card_t));
 323
 324         card->dev = alloc_hdlcdev(card);
 325         if (!card->dev) {
 326                 printk(KERN_ERR "c101: unable to allocate memory\n");
 327                 kfree(card);
 328                 return -ENOBUFS;
 329         }
 330
 331         if (request_irq(irq, sca_intr, 0, devname, card)) {
 332                 printk(KERN_ERR "c101: could not allocate IRQ\n");
 333                 c101_destroy_card(card);
 334                 return -EBUSY;
 335         }
 336         card->irq = irq;
 337
 338         if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
 339                 printk(KERN_ERR "c101: could not request RAM window\n");
 340                 c101_destroy_card(card);
 341                 return -EBUSY;
 342         }
 343         card->phy_winbase = winbase;
 344         card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
 345         if (!card->win0base) {
 346                 printk(KERN_ERR "c101: could not map I/O address\n");
 347                 c101_destroy_card(card);
 348                 return -EFAULT;
 349         }
 350
 351         card->tx_ring_buffers = TX_RING_BUFFERS;
 352         card->rx_ring_buffers = RX_RING_BUFFERS;
 353         card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
 354
 355         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 356         udelay(100);
 357         writeb(0, card->win0base + C101_PAGE);
 358         writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
 359
 360         sca_init(card, 0);
 361
 362         dev = port_to_dev(card);
 363         hdlc = dev_to_hdlc(dev);
 364
 365         spin_lock_init(&card->lock);
 366         SET_MODULE_OWNER(dev);
 367         dev->irq = irq;
 368         dev->mem_start = winbase;
 369         dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
 370         dev->tx_queue_len = 50;
 371         dev->do_ioctl = c101_ioctl;
 372         dev->open = c101_open;
 373         dev->stop = c101_close;
 374         hdlc->attach = sca_attach;
 375         hdlc->xmit = sca_xmit;
 376         card->settings.clock_type = CLOCK_EXT;
 377
 378         result = register_hdlc_device(dev);
 379         if (result) {
 380                 printk(KERN_WARNING "c101: unable to register hdlc device\n");
 381                 c101_destroy_card(card);
 382                 return result;
 383         }
 384
 385         sca_init_sync_port(card); /* Set up C101 memory */
 386         set_carrier(card);
 387
 388         printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
 389                " using %u TX + %u RX packets rings\n",
 390                dev->name, card->irq,
 391                card->tx_ring_buffers, card->rx_ring_buffers);
 392
 393         *new_card = card;
 394         new_card = &card->next_card;
 395         return 0;
 396 }
 397
 398
 399
 400 static int __init c101_init(void)
 401 {
 402         if (hw == NULL) {
 403 #ifdef MODULE
 404                 printk(KERN_INFO "c101: no card initialized\n");
 405 #endif
 406                 return -ENOSYS; /* no parameters specified, abort */
 407         }
 408
 409         printk(KERN_INFO "%s\n", version);
 410
 411         do {
 412                 unsigned long irq, ram;
 413
 414                 irq = simple_strtoul(hw, &hw, 0);
 415
 416                 if (*hw++ != ',')
 417                         break;
 418                 ram = simple_strtoul(hw, &hw, 0);
 419
 420                 if (*hw == ':' || *hw == '\x0')
 421                         c101_run(irq, ram);
 422
 423                 if (*hw == '\x0')
 424                         return first_card ? 0 : -ENOSYS;
 425         }while(*hw++ == ':');
 426
 427         printk(KERN_ERR "c101: invalid hardware parameters\n");
 428         return first_card ? 0 : -ENOSYS;
 429 }
 430
 431
 432 static void __exit c101_cleanup(void)
 433 {
 434         card_t *card = first_card;
 435
 436         while (card) {
 437                 card_t *ptr = card;
 438                 card = card->next_card;
 439                 unregister_hdlc_device(port_to_dev(ptr));
 440                 c101_destroy_card(ptr);
 441         }
 442 }
 443
 444
 445 module_init(c101_init);
 446 module_exit(c101_cleanup);
 447
 448 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 449 MODULE_DESCRIPTION("Moxa C101 serial port driver");
 450 MODULE_LICENSE("GPL v2");
 451 module_param(hw, charp, 0444);
 452 MODULE_PARM_DESC(hw, "irq,ram:irq,...");