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Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / tulip / dmfe.c
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Implement pci_driver::suspend() and pci_driver::resume()
59 power management methods.
60
61 Check on 64 bit boxes.
62 Check and fix on big endian boxes.
63
64 Test and make sure PCI latency is now correct for all cases.
65 */
66
67 #define DRV_NAME "dmfe"
68 #define DRV_VERSION "1.36.4"
69 #define DRV_RELDATE "2002-01-17"
70
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/ptrace.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/slab.h>
79 #include <linux/interrupt.h>
80 #include <linux/pci.h>
81 #include <linux/dma-mapping.h>
82 #include <linux/init.h>
83 #include <linux/netdevice.h>
84 #include <linux/etherdevice.h>
85 #include <linux/ethtool.h>
86 #include <linux/skbuff.h>
87 #include <linux/delay.h>
88 #include <linux/spinlock.h>
89 #include <linux/crc32.h>
90 #include <linux/bitops.h>
91
92 #include <asm/processor.h>
93 #include <asm/io.h>
94 #include <asm/dma.h>
95 #include <asm/uaccess.h>
96 #include <asm/irq.h>
97
98
99 /* Board/System/Debug information/definition ---------------- */
100 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
101 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
102 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
103 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
104
105 #define DM9102_IO_SIZE 0x80
106 #define DM9102A_IO_SIZE 0x100
107 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
108 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
109 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
110 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
111 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
112 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
113 #define TX_BUF_ALLOC 0x600
114 #define RX_ALLOC_SIZE 0x620
115 #define DM910X_RESET 1
116 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
117 #define CR6_DEFAULT 0x00080000 /* HD */
118 #define CR7_DEFAULT 0x180c1
119 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
120 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
121 #define MAX_PACKET_SIZE 1514
122 #define DMFE_MAX_MULTICAST 14
123 #define RX_COPY_SIZE 100
124 #define MAX_CHECK_PACKET 0x8000
125 #define DM9801_NOISE_FLOOR 8
126 #define DM9802_NOISE_FLOOR 5
127
128 #define DMFE_10MHF 0
129 #define DMFE_100MHF 1
130 #define DMFE_10MFD 4
131 #define DMFE_100MFD 5
132 #define DMFE_AUTO 8
133 #define DMFE_1M_HPNA 0x10
134
135 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
136 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
137 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
138 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
139 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
140 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
141
142 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
143 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
144 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
145
146 #define DMFE_DBUG(dbug_now, msg, value) \
147 do { \
148 if (dmfe_debug || (dbug_now)) \
149 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
150 (msg), (long) (value)); \
151 } while (0)
152
153 #define SHOW_MEDIA_TYPE(mode) \
154 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
155 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
156
157
158 /* CR9 definition: SROM/MII */
159 #define CR9_SROM_READ 0x4800
160 #define CR9_SRCS 0x1
161 #define CR9_SRCLK 0x2
162 #define CR9_CRDOUT 0x8
163 #define SROM_DATA_0 0x0
164 #define SROM_DATA_1 0x4
165 #define PHY_DATA_1 0x20000
166 #define PHY_DATA_0 0x00000
167 #define MDCLKH 0x10000
168
169 #define PHY_POWER_DOWN 0x800
170
171 #define SROM_V41_CODE 0x14
172
173 #define SROM_CLK_WRITE(data, ioaddr) \
174 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
175 udelay(5); \
176 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
179 udelay(5);
180
181 #define __CHK_IO_SIZE(pci_id, dev_rev) \
182 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? \
183 DM9102A_IO_SIZE: DM9102_IO_SIZE)
184
185 #define CHK_IO_SIZE(pci_dev, dev_rev) \
186 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev))
187
188 /* Sten Check */
189 #define DEVICE net_device
190
191 /* Structure/enum declaration ------------------------------- */
192 struct tx_desc {
193 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
194 char *tx_buf_ptr; /* Data for us */
195 struct tx_desc *next_tx_desc;
196 } __attribute__(( aligned(32) ));
197
198 struct rx_desc {
199 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
200 struct sk_buff *rx_skb_ptr; /* Data for us */
201 struct rx_desc *next_rx_desc;
202 } __attribute__(( aligned(32) ));
203
204 struct dmfe_board_info {
205 u32 chip_id; /* Chip vendor/Device ID */
206 u32 chip_revision; /* Chip revision */
207 struct DEVICE *next_dev; /* next device */
208 struct pci_dev *pdev; /* PCI device */
209 spinlock_t lock;
210
211 long ioaddr; /* I/O base address */
212 u32 cr0_data;
213 u32 cr5_data;
214 u32 cr6_data;
215 u32 cr7_data;
216 u32 cr15_data;
217
218 /* pointer for memory physical address */
219 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
220 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
221 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
222 dma_addr_t first_tx_desc_dma;
223 dma_addr_t first_rx_desc_dma;
224
225 /* descriptor pointer */
226 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
227 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
228 unsigned char *desc_pool_ptr; /* descriptor pool memory */
229 struct tx_desc *first_tx_desc;
230 struct tx_desc *tx_insert_ptr;
231 struct tx_desc *tx_remove_ptr;
232 struct rx_desc *first_rx_desc;
233 struct rx_desc *rx_insert_ptr;
234 struct rx_desc *rx_ready_ptr; /* packet come pointer */
235 unsigned long tx_packet_cnt; /* transmitted packet count */
236 unsigned long tx_queue_cnt; /* wait to send packet count */
237 unsigned long rx_avail_cnt; /* available rx descriptor count */
238 unsigned long interval_rx_cnt; /* rx packet count a callback time */
239
240 u16 HPNA_command; /* For HPNA register 16 */
241 u16 HPNA_timer; /* For HPNA remote device check */
242 u16 dbug_cnt;
243 u16 NIC_capability; /* NIC media capability */
244 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
245
246 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
247 u8 chip_type; /* Keep DM9102A chip type */
248 u8 media_mode; /* user specify media mode */
249 u8 op_mode; /* real work media mode */
250 u8 phy_addr;
251 u8 wait_reset; /* Hardware failed, need to reset */
252 u8 dm910x_chk_mode; /* Operating mode check */
253 u8 first_in_callback; /* Flag to record state */
254 struct timer_list timer;
255
256 /* System defined statistic counter */
257 struct net_device_stats stats;
258
259 /* Driver defined statistic counter */
260 unsigned long tx_fifo_underrun;
261 unsigned long tx_loss_carrier;
262 unsigned long tx_no_carrier;
263 unsigned long tx_late_collision;
264 unsigned long tx_excessive_collision;
265 unsigned long tx_jabber_timeout;
266 unsigned long reset_count;
267 unsigned long reset_cr8;
268 unsigned long reset_fatal;
269 unsigned long reset_TXtimeout;
270
271 /* NIC SROM data */
272 unsigned char srom[128];
273 };
274
275 enum dmfe_offsets {
276 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
277 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
278 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
279 DCR15 = 0x78
280 };
281
282 enum dmfe_CR6_bits {
283 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
284 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
285 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
286 };
287
288 /* Global variable declaration ----------------------------- */
289 static int __devinitdata printed_version;
290 static char version[] __devinitdata =
291 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
292 DRV_VERSION " (" DRV_RELDATE ")\n";
293
294 static int dmfe_debug;
295 static unsigned char dmfe_media_mode = DMFE_AUTO;
296 static u32 dmfe_cr6_user_set;
297
298 /* For module input parameter */
299 static int debug;
300 static u32 cr6set;
301 static unsigned char mode = 8;
302 static u8 chkmode = 1;
303 static u8 HPNA_mode; /* Default: Low Power/High Speed */
304 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
305 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
306 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
307 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
308 4: TX pause packet */
309
310
311 /* function declaration ------------------------------------- */
312 static int dmfe_open(struct DEVICE *);
313 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
314 static int dmfe_stop(struct DEVICE *);
315 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
316 static void dmfe_set_filter_mode(struct DEVICE *);
317 static const struct ethtool_ops netdev_ethtool_ops;
318 static u16 read_srom_word(long ,int);
319 static irqreturn_t dmfe_interrupt(int , void *);
320 #ifdef CONFIG_NET_POLL_CONTROLLER
321 static void poll_dmfe (struct net_device *dev);
322 #endif
323 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
324 static void allocate_rx_buffer(struct dmfe_board_info *);
325 static void update_cr6(u32, unsigned long);
326 static void send_filter_frame(struct DEVICE * ,int);
327 static void dm9132_id_table(struct DEVICE * ,int);
328 static u16 phy_read(unsigned long, u8, u8, u32);
329 static void phy_write(unsigned long, u8, u8, u16, u32);
330 static void phy_write_1bit(unsigned long, u32);
331 static u16 phy_read_1bit(unsigned long);
332 static u8 dmfe_sense_speed(struct dmfe_board_info *);
333 static void dmfe_process_mode(struct dmfe_board_info *);
334 static void dmfe_timer(unsigned long);
335 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
336 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
337 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
338 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
339 static void dmfe_dynamic_reset(struct DEVICE *);
340 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
341 static void dmfe_init_dm910x(struct DEVICE *);
342 static void dmfe_parse_srom(struct dmfe_board_info *);
343 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
344 static void dmfe_program_DM9802(struct dmfe_board_info *);
345 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
346 static void dmfe_set_phyxcer(struct dmfe_board_info *);
347
348 /* DM910X network board routine ---------------------------- */
349
350 /*
351 * Search DM910X board ,allocate space and register it
352 */
353
354 static int __devinit dmfe_init_one (struct pci_dev *pdev,
355 const struct pci_device_id *ent)
356 {
357 struct dmfe_board_info *db; /* board information structure */
358 struct net_device *dev;
359 u32 dev_rev, pci_pmr;
360 int i, err;
361
362 DMFE_DBUG(0, "dmfe_init_one()", 0);
363
364 if (!printed_version++)
365 printk(version);
366
367 /* Init network device */
368 dev = alloc_etherdev(sizeof(*db));
369 if (dev == NULL)
370 return -ENOMEM;
371 SET_MODULE_OWNER(dev);
372 SET_NETDEV_DEV(dev, &pdev->dev);
373
374 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
375 printk(KERN_WARNING DRV_NAME
376 ": 32-bit PCI DMA not available.\n");
377 err = -ENODEV;
378 goto err_out_free;
379 }
380
381 /* Enable Master/IO access, Disable memory access */
382 err = pci_enable_device(pdev);
383 if (err)
384 goto err_out_free;
385
386 if (!pci_resource_start(pdev, 0)) {
387 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
388 err = -ENODEV;
389 goto err_out_disable;
390 }
391
392 /* Read Chip revision */
393 pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
394
395 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
396 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
397 err = -ENODEV;
398 goto err_out_disable;
399 }
400
401 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
402
403 /* Set Latency Timer 80h */
404 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
405 Need a PCI quirk.. */
406
407 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
408 #endif
409
410 if (pci_request_regions(pdev, DRV_NAME)) {
411 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
412 err = -ENODEV;
413 goto err_out_disable;
414 }
415
416 /* Init system & device */
417 db = netdev_priv(dev);
418
419 /* Allocate Tx/Rx descriptor memory */
420 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
421 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
422
423 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
424 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
425
426 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
427 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
428 db->buf_pool_start = db->buf_pool_ptr;
429 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
430
431 db->chip_id = ent->driver_data;
432 db->ioaddr = pci_resource_start(pdev, 0);
433 db->chip_revision = dev_rev;
434
435 db->pdev = pdev;
436
437 dev->base_addr = db->ioaddr;
438 dev->irq = pdev->irq;
439 pci_set_drvdata(pdev, dev);
440 dev->open = &dmfe_open;
441 dev->hard_start_xmit = &dmfe_start_xmit;
442 dev->stop = &dmfe_stop;
443 dev->get_stats = &dmfe_get_stats;
444 dev->set_multicast_list = &dmfe_set_filter_mode;
445 #ifdef CONFIG_NET_POLL_CONTROLLER
446 dev->poll_controller = &poll_dmfe;
447 #endif
448 dev->ethtool_ops = &netdev_ethtool_ops;
449 netif_carrier_off(dev);
450 spin_lock_init(&db->lock);
451
452 pci_read_config_dword(pdev, 0x50, &pci_pmr);
453 pci_pmr &= 0x70000;
454 if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
455 db->chip_type = 1; /* DM9102A E3 */
456 else
457 db->chip_type = 0;
458
459 /* read 64 word srom data */
460 for (i = 0; i < 64; i++)
461 ((u16 *) db->srom)[i] =
462 cpu_to_le16(read_srom_word(db->ioaddr, i));
463
464 /* Set Node address */
465 for (i = 0; i < 6; i++)
466 dev->dev_addr[i] = db->srom[20 + i];
467
468 err = register_netdev (dev);
469 if (err)
470 goto err_out_res;
471
472 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
473 dev->name,
474 ent->driver_data >> 16,
475 pci_name(pdev));
476 for (i = 0; i < 6; i++)
477 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
478 printk(", irq %d.\n", dev->irq);
479
480 pci_set_master(pdev);
481
482 return 0;
483
484 err_out_res:
485 pci_release_regions(pdev);
486 err_out_disable:
487 pci_disable_device(pdev);
488 err_out_free:
489 pci_set_drvdata(pdev, NULL);
490 free_netdev(dev);
491
492 return err;
493 }
494
495
496 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
497 {
498 struct net_device *dev = pci_get_drvdata(pdev);
499 struct dmfe_board_info *db = netdev_priv(dev);
500
501 DMFE_DBUG(0, "dmfe_remove_one()", 0);
502
503 if (dev) {
504
505 unregister_netdev(dev);
506
507 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
508 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
509 db->desc_pool_dma_ptr);
510 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
511 db->buf_pool_ptr, db->buf_pool_dma_ptr);
512 pci_release_regions(pdev);
513 free_netdev(dev); /* free board information */
514
515 pci_set_drvdata(pdev, NULL);
516 }
517
518 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
519 }
520
521
522 /*
523 * Open the interface.
524 * The interface is opened whenever "ifconfig" actives it.
525 */
526
527 static int dmfe_open(struct DEVICE *dev)
528 {
529 int ret;
530 struct dmfe_board_info *db = netdev_priv(dev);
531
532 DMFE_DBUG(0, "dmfe_open", 0);
533
534 ret = request_irq(dev->irq, &dmfe_interrupt,
535 IRQF_SHARED, dev->name, dev);
536 if (ret)
537 return ret;
538
539 /* system variable init */
540 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
541 db->tx_packet_cnt = 0;
542 db->tx_queue_cnt = 0;
543 db->rx_avail_cnt = 0;
544 db->wait_reset = 0;
545
546 db->first_in_callback = 0;
547 db->NIC_capability = 0xf; /* All capability*/
548 db->PHY_reg4 = 0x1e0;
549
550 /* CR6 operation mode decision */
551 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
552 (db->chip_revision >= 0x02000030) ) {
553 db->cr6_data |= DMFE_TXTH_256;
554 db->cr0_data = CR0_DEFAULT;
555 db->dm910x_chk_mode=4; /* Enter the normal mode */
556 } else {
557 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
558 db->cr0_data = 0;
559 db->dm910x_chk_mode = 1; /* Enter the check mode */
560 }
561
562 /* Initilize DM910X board */
563 dmfe_init_dm910x(dev);
564
565 /* Active System Interface */
566 netif_wake_queue(dev);
567
568 /* set and active a timer process */
569 init_timer(&db->timer);
570 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
571 db->timer.data = (unsigned long)dev;
572 db->timer.function = &dmfe_timer;
573 add_timer(&db->timer);
574
575 return 0;
576 }
577
578
579 /* Initilize DM910X board
580 * Reset DM910X board
581 * Initilize TX/Rx descriptor chain structure
582 * Send the set-up frame
583 * Enable Tx/Rx machine
584 */
585
586 static void dmfe_init_dm910x(struct DEVICE *dev)
587 {
588 struct dmfe_board_info *db = netdev_priv(dev);
589 unsigned long ioaddr = db->ioaddr;
590
591 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
592
593 /* Reset DM910x MAC controller */
594 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
595 udelay(100);
596 outl(db->cr0_data, ioaddr + DCR0);
597 udelay(5);
598
599 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
600 db->phy_addr = 1;
601
602 /* Parser SROM and media mode */
603 dmfe_parse_srom(db);
604 db->media_mode = dmfe_media_mode;
605
606 /* RESET Phyxcer Chip by GPR port bit 7 */
607 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
608 if (db->chip_id == PCI_DM9009_ID) {
609 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
610 mdelay(300); /* Delay 300 ms */
611 }
612 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
613
614 /* Process Phyxcer Media Mode */
615 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
616 dmfe_set_phyxcer(db);
617
618 /* Media Mode Process */
619 if ( !(db->media_mode & DMFE_AUTO) )
620 db->op_mode = db->media_mode; /* Force Mode */
621
622 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
623 dmfe_descriptor_init(db, ioaddr);
624
625 /* Init CR6 to program DM910x operation */
626 update_cr6(db->cr6_data, ioaddr);
627
628 /* Send setup frame */
629 if (db->chip_id == PCI_DM9132_ID)
630 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
631 else
632 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
633
634 /* Init CR7, interrupt active bit */
635 db->cr7_data = CR7_DEFAULT;
636 outl(db->cr7_data, ioaddr + DCR7);
637
638 /* Init CR15, Tx jabber and Rx watchdog timer */
639 outl(db->cr15_data, ioaddr + DCR15);
640
641 /* Enable DM910X Tx/Rx function */
642 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
643 update_cr6(db->cr6_data, ioaddr);
644 }
645
646
647 /*
648 * Hardware start transmission.
649 * Send a packet to media from the upper layer.
650 */
651
652 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
653 {
654 struct dmfe_board_info *db = netdev_priv(dev);
655 struct tx_desc *txptr;
656 unsigned long flags;
657
658 DMFE_DBUG(0, "dmfe_start_xmit", 0);
659
660 /* Resource flag check */
661 netif_stop_queue(dev);
662
663 /* Too large packet check */
664 if (skb->len > MAX_PACKET_SIZE) {
665 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
666 dev_kfree_skb(skb);
667 return 0;
668 }
669
670 spin_lock_irqsave(&db->lock, flags);
671
672 /* No Tx resource check, it never happen nromally */
673 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
674 spin_unlock_irqrestore(&db->lock, flags);
675 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
676 db->tx_queue_cnt);
677 return 1;
678 }
679
680 /* Disable NIC interrupt */
681 outl(0, dev->base_addr + DCR7);
682
683 /* transmit this packet */
684 txptr = db->tx_insert_ptr;
685 memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
686 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
687
688 /* Point to next transmit free descriptor */
689 db->tx_insert_ptr = txptr->next_tx_desc;
690
691 /* Transmit Packet Process */
692 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
693 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
694 db->tx_packet_cnt++; /* Ready to send */
695 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
696 dev->trans_start = jiffies; /* saved time stamp */
697 } else {
698 db->tx_queue_cnt++; /* queue TX packet */
699 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
700 }
701
702 /* Tx resource check */
703 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
704 netif_wake_queue(dev);
705
706 /* Restore CR7 to enable interrupt */
707 spin_unlock_irqrestore(&db->lock, flags);
708 outl(db->cr7_data, dev->base_addr + DCR7);
709
710 /* free this SKB */
711 dev_kfree_skb(skb);
712
713 return 0;
714 }
715
716
717 /*
718 * Stop the interface.
719 * The interface is stopped when it is brought.
720 */
721
722 static int dmfe_stop(struct DEVICE *dev)
723 {
724 struct dmfe_board_info *db = netdev_priv(dev);
725 unsigned long ioaddr = dev->base_addr;
726
727 DMFE_DBUG(0, "dmfe_stop", 0);
728
729 /* disable system */
730 netif_stop_queue(dev);
731
732 /* deleted timer */
733 del_timer_sync(&db->timer);
734
735 /* Reset & stop DM910X board */
736 outl(DM910X_RESET, ioaddr + DCR0);
737 udelay(5);
738 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
739
740 /* free interrupt */
741 free_irq(dev->irq, dev);
742
743 /* free allocated rx buffer */
744 dmfe_free_rxbuffer(db);
745
746 #if 0
747 /* show statistic counter */
748 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
749 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
750 db->tx_fifo_underrun, db->tx_excessive_collision,
751 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
752 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
753 db->reset_fatal, db->reset_TXtimeout);
754 #endif
755
756 return 0;
757 }
758
759
760 /*
761 * DM9102 insterrupt handler
762 * receive the packet to upper layer, free the transmitted packet
763 */
764
765 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
766 {
767 struct DEVICE *dev = dev_id;
768 struct dmfe_board_info *db = netdev_priv(dev);
769 unsigned long ioaddr = dev->base_addr;
770 unsigned long flags;
771
772 DMFE_DBUG(0, "dmfe_interrupt()", 0);
773
774 spin_lock_irqsave(&db->lock, flags);
775
776 /* Got DM910X status */
777 db->cr5_data = inl(ioaddr + DCR5);
778 outl(db->cr5_data, ioaddr + DCR5);
779 if ( !(db->cr5_data & 0xc1) ) {
780 spin_unlock_irqrestore(&db->lock, flags);
781 return IRQ_HANDLED;
782 }
783
784 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
785 outl(0, ioaddr + DCR7);
786
787 /* Check system status */
788 if (db->cr5_data & 0x2000) {
789 /* system bus error happen */
790 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
791 db->reset_fatal++;
792 db->wait_reset = 1; /* Need to RESET */
793 spin_unlock_irqrestore(&db->lock, flags);
794 return IRQ_HANDLED;
795 }
796
797 /* Received the coming packet */
798 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
799 dmfe_rx_packet(dev, db);
800
801 /* reallocate rx descriptor buffer */
802 if (db->rx_avail_cnt<RX_DESC_CNT)
803 allocate_rx_buffer(db);
804
805 /* Free the transmitted descriptor */
806 if ( db->cr5_data & 0x01)
807 dmfe_free_tx_pkt(dev, db);
808
809 /* Mode Check */
810 if (db->dm910x_chk_mode & 0x2) {
811 db->dm910x_chk_mode = 0x4;
812 db->cr6_data |= 0x100;
813 update_cr6(db->cr6_data, db->ioaddr);
814 }
815
816 /* Restore CR7 to enable interrupt mask */
817 outl(db->cr7_data, ioaddr + DCR7);
818
819 spin_unlock_irqrestore(&db->lock, flags);
820 return IRQ_HANDLED;
821 }
822
823
824 #ifdef CONFIG_NET_POLL_CONTROLLER
825 /*
826 * Polling 'interrupt' - used by things like netconsole to send skbs
827 * without having to re-enable interrupts. It's not called while
828 * the interrupt routine is executing.
829 */
830
831 static void poll_dmfe (struct net_device *dev)
832 {
833 /* disable_irq here is not very nice, but with the lockless
834 interrupt handler we have no other choice. */
835 disable_irq(dev->irq);
836 dmfe_interrupt (dev->irq, dev);
837 enable_irq(dev->irq);
838 }
839 #endif
840
841 /*
842 * Free TX resource after TX complete
843 */
844
845 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
846 {
847 struct tx_desc *txptr;
848 unsigned long ioaddr = dev->base_addr;
849 u32 tdes0;
850
851 txptr = db->tx_remove_ptr;
852 while(db->tx_packet_cnt) {
853 tdes0 = le32_to_cpu(txptr->tdes0);
854 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
855 if (tdes0 & 0x80000000)
856 break;
857
858 /* A packet sent completed */
859 db->tx_packet_cnt--;
860 db->stats.tx_packets++;
861
862 /* Transmit statistic counter */
863 if ( tdes0 != 0x7fffffff ) {
864 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
865 db->stats.collisions += (tdes0 >> 3) & 0xf;
866 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
867 if (tdes0 & TDES0_ERR_MASK) {
868 db->stats.tx_errors++;
869
870 if (tdes0 & 0x0002) { /* UnderRun */
871 db->tx_fifo_underrun++;
872 if ( !(db->cr6_data & CR6_SFT) ) {
873 db->cr6_data = db->cr6_data | CR6_SFT;
874 update_cr6(db->cr6_data, db->ioaddr);
875 }
876 }
877 if (tdes0 & 0x0100)
878 db->tx_excessive_collision++;
879 if (tdes0 & 0x0200)
880 db->tx_late_collision++;
881 if (tdes0 & 0x0400)
882 db->tx_no_carrier++;
883 if (tdes0 & 0x0800)
884 db->tx_loss_carrier++;
885 if (tdes0 & 0x4000)
886 db->tx_jabber_timeout++;
887 }
888 }
889
890 txptr = txptr->next_tx_desc;
891 }/* End of while */
892
893 /* Update TX remove pointer to next */
894 db->tx_remove_ptr = txptr;
895
896 /* Send the Tx packet in queue */
897 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
898 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
899 db->tx_packet_cnt++; /* Ready to send */
900 db->tx_queue_cnt--;
901 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
902 dev->trans_start = jiffies; /* saved time stamp */
903 }
904
905 /* Resource available check */
906 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
907 netif_wake_queue(dev); /* Active upper layer, send again */
908 }
909
910
911 /*
912 * Calculate the CRC valude of the Rx packet
913 * flag = 1 : return the reverse CRC (for the received packet CRC)
914 * 0 : return the normal CRC (for Hash Table index)
915 */
916
917 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
918 {
919 u32 crc = crc32(~0, Data, Len);
920 if (flag) crc = ~crc;
921 return crc;
922 }
923
924
925 /*
926 * Receive the come packet and pass to upper layer
927 */
928
929 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
930 {
931 struct rx_desc *rxptr;
932 struct sk_buff *skb, *newskb;
933 int rxlen;
934 u32 rdes0;
935
936 rxptr = db->rx_ready_ptr;
937
938 while(db->rx_avail_cnt) {
939 rdes0 = le32_to_cpu(rxptr->rdes0);
940 if (rdes0 & 0x80000000) /* packet owner check */
941 break;
942
943 db->rx_avail_cnt--;
944 db->interval_rx_cnt++;
945
946 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
947 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
948
949 if ( (rdes0 & 0x300) != 0x300) {
950 /* A packet without First/Last flag */
951 /* reuse this SKB */
952 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
953 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
954 } else {
955 /* A packet with First/Last flag */
956 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
957
958 /* error summary bit check */
959 if (rdes0 & 0x8000) {
960 /* This is a error packet */
961 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
962 db->stats.rx_errors++;
963 if (rdes0 & 1)
964 db->stats.rx_fifo_errors++;
965 if (rdes0 & 2)
966 db->stats.rx_crc_errors++;
967 if (rdes0 & 0x80)
968 db->stats.rx_length_errors++;
969 }
970
971 if ( !(rdes0 & 0x8000) ||
972 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
973 skb = rxptr->rx_skb_ptr;
974
975 /* Received Packet CRC check need or not */
976 if ( (db->dm910x_chk_mode & 1) &&
977 (cal_CRC(skb->data, rxlen, 1) !=
978 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
979 /* Found a error received packet */
980 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
981 db->dm910x_chk_mode = 3;
982 } else {
983 /* Good packet, send to upper layer */
984 /* Shorst packet used new SKB */
985 if ((rxlen < RX_COPY_SIZE) &&
986 ((newskb = dev_alloc_skb(rxlen + 2))
987 != NULL)) {
988
989 skb = newskb;
990 /* size less than COPY_SIZE, allocate a rxlen SKB */
991 skb->dev = dev;
992 skb_reserve(skb, 2); /* 16byte align */
993 memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->data, rxlen);
994 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
995 } else {
996 skb->dev = dev;
997 skb_put(skb, rxlen);
998 }
999 skb->protocol = eth_type_trans(skb, dev);
1000 netif_rx(skb);
1001 dev->last_rx = jiffies;
1002 db->stats.rx_packets++;
1003 db->stats.rx_bytes += rxlen;
1004 }
1005 } else {
1006 /* Reuse SKB buffer when the packet is error */
1007 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1008 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1009 }
1010 }
1011
1012 rxptr = rxptr->next_rx_desc;
1013 }
1014
1015 db->rx_ready_ptr = rxptr;
1016 }
1017
1018
1019 /*
1020 * Get statistics from driver.
1021 */
1022
1023 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1024 {
1025 struct dmfe_board_info *db = netdev_priv(dev);
1026
1027 DMFE_DBUG(0, "dmfe_get_stats", 0);
1028 return &db->stats;
1029 }
1030
1031
1032 /*
1033 * Set DM910X multicast address
1034 */
1035
1036 static void dmfe_set_filter_mode(struct DEVICE * dev)
1037 {
1038 struct dmfe_board_info *db = netdev_priv(dev);
1039 unsigned long flags;
1040
1041 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1042 spin_lock_irqsave(&db->lock, flags);
1043
1044 if (dev->flags & IFF_PROMISC) {
1045 DMFE_DBUG(0, "Enable PROM Mode", 0);
1046 db->cr6_data |= CR6_PM | CR6_PBF;
1047 update_cr6(db->cr6_data, db->ioaddr);
1048 spin_unlock_irqrestore(&db->lock, flags);
1049 return;
1050 }
1051
1052 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1053 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1054 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1055 db->cr6_data |= CR6_PAM;
1056 spin_unlock_irqrestore(&db->lock, flags);
1057 return;
1058 }
1059
1060 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1061 if (db->chip_id == PCI_DM9132_ID)
1062 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1063 else
1064 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1065 spin_unlock_irqrestore(&db->lock, flags);
1066 }
1067
1068 static void netdev_get_drvinfo(struct net_device *dev,
1069 struct ethtool_drvinfo *info)
1070 {
1071 struct dmfe_board_info *np = netdev_priv(dev);
1072
1073 strcpy(info->driver, DRV_NAME);
1074 strcpy(info->version, DRV_VERSION);
1075 if (np->pdev)
1076 strcpy(info->bus_info, pci_name(np->pdev));
1077 else
1078 sprintf(info->bus_info, "EISA 0x%lx %d",
1079 dev->base_addr, dev->irq);
1080 }
1081
1082 static const struct ethtool_ops netdev_ethtool_ops = {
1083 .get_drvinfo = netdev_get_drvinfo,
1084 .get_link = ethtool_op_get_link,
1085 };
1086
1087 /*
1088 * A periodic timer routine
1089 * Dynamic media sense, allocate Rx buffer...
1090 */
1091
1092 static void dmfe_timer(unsigned long data)
1093 {
1094 u32 tmp_cr8;
1095 unsigned char tmp_cr12;
1096 struct DEVICE *dev = (struct DEVICE *) data;
1097 struct dmfe_board_info *db = netdev_priv(dev);
1098 unsigned long flags;
1099
1100 int link_ok, link_ok_phy;
1101
1102 DMFE_DBUG(0, "dmfe_timer()", 0);
1103 spin_lock_irqsave(&db->lock, flags);
1104
1105 /* Media mode process when Link OK before enter this route */
1106 if (db->first_in_callback == 0) {
1107 db->first_in_callback = 1;
1108 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1109 db->cr6_data &= ~0x40000;
1110 update_cr6(db->cr6_data, db->ioaddr);
1111 phy_write(db->ioaddr,
1112 db->phy_addr, 0, 0x1000, db->chip_id);
1113 db->cr6_data |= 0x40000;
1114 update_cr6(db->cr6_data, db->ioaddr);
1115 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1116 add_timer(&db->timer);
1117 spin_unlock_irqrestore(&db->lock, flags);
1118 return;
1119 }
1120 }
1121
1122
1123 /* Operating Mode Check */
1124 if ( (db->dm910x_chk_mode & 0x1) &&
1125 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1126 db->dm910x_chk_mode = 0x4;
1127
1128 /* Dynamic reset DM910X : system error or transmit time-out */
1129 tmp_cr8 = inl(db->ioaddr + DCR8);
1130 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1131 db->reset_cr8++;
1132 db->wait_reset = 1;
1133 }
1134 db->interval_rx_cnt = 0;
1135
1136 /* TX polling kick monitor */
1137 if ( db->tx_packet_cnt &&
1138 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1139 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1140
1141 /* TX Timeout */
1142 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1143 db->reset_TXtimeout++;
1144 db->wait_reset = 1;
1145 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1146 dev->name);
1147 }
1148 }
1149
1150 if (db->wait_reset) {
1151 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1152 db->reset_count++;
1153 dmfe_dynamic_reset(dev);
1154 db->first_in_callback = 0;
1155 db->timer.expires = DMFE_TIMER_WUT;
1156 add_timer(&db->timer);
1157 spin_unlock_irqrestore(&db->lock, flags);
1158 return;
1159 }
1160
1161 /* Link status check, Dynamic media type change */
1162 if (db->chip_id == PCI_DM9132_ID)
1163 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1164 else
1165 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1166
1167 if ( ((db->chip_id == PCI_DM9102_ID) &&
1168 (db->chip_revision == 0x02000030)) ||
1169 ((db->chip_id == PCI_DM9132_ID) &&
1170 (db->chip_revision == 0x02000010)) ) {
1171 /* DM9102A Chip */
1172 if (tmp_cr12 & 2)
1173 link_ok = 0;
1174 else
1175 link_ok = 1;
1176 }
1177 else
1178 /*0x43 is used instead of 0x3 because bit 6 should represent
1179 link status of external PHY */
1180 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1181
1182
1183 /* If chip reports that link is failed it could be because external
1184 PHY link status pin is not conected correctly to chip
1185 To be sure ask PHY too.
1186 */
1187
1188 /* need a dummy read because of PHY's register latch*/
1189 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1190 link_ok_phy = (phy_read (db->ioaddr,
1191 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1192
1193 if (link_ok_phy != link_ok) {
1194 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1195 link_ok = link_ok | link_ok_phy;
1196 }
1197
1198 if ( !link_ok && netif_carrier_ok(dev)) {
1199 /* Link Failed */
1200 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1201 netif_carrier_off(dev);
1202
1203 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1204 /* AUTO or force 1M Homerun/Longrun don't need */
1205 if ( !(db->media_mode & 0x38) )
1206 phy_write(db->ioaddr, db->phy_addr,
1207 0, 0x1000, db->chip_id);
1208
1209 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1210 if (db->media_mode & DMFE_AUTO) {
1211 /* 10/100M link failed, used 1M Home-Net */
1212 db->cr6_data|=0x00040000; /* bit18=1, MII */
1213 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1214 update_cr6(db->cr6_data, db->ioaddr);
1215 }
1216 } else if (!netif_carrier_ok(dev)) {
1217
1218 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1219
1220 /* Auto Sense Speed */
1221 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1222 netif_carrier_on(dev);
1223 SHOW_MEDIA_TYPE(db->op_mode);
1224 }
1225
1226 dmfe_process_mode(db);
1227 }
1228
1229 /* HPNA remote command check */
1230 if (db->HPNA_command & 0xf00) {
1231 db->HPNA_timer--;
1232 if (!db->HPNA_timer)
1233 dmfe_HPNA_remote_cmd_chk(db);
1234 }
1235
1236 /* Timer active again */
1237 db->timer.expires = DMFE_TIMER_WUT;
1238 add_timer(&db->timer);
1239 spin_unlock_irqrestore(&db->lock, flags);
1240 }
1241
1242
1243 /*
1244 * Dynamic reset the DM910X board
1245 * Stop DM910X board
1246 * Free Tx/Rx allocated memory
1247 * Reset DM910X board
1248 * Re-initilize DM910X board
1249 */
1250
1251 static void dmfe_dynamic_reset(struct DEVICE *dev)
1252 {
1253 struct dmfe_board_info *db = netdev_priv(dev);
1254
1255 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1256
1257 /* Sopt MAC controller */
1258 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1259 update_cr6(db->cr6_data, dev->base_addr);
1260 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1261 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1262
1263 /* Disable upper layer interface */
1264 netif_stop_queue(dev);
1265
1266 /* Free Rx Allocate buffer */
1267 dmfe_free_rxbuffer(db);
1268
1269 /* system variable init */
1270 db->tx_packet_cnt = 0;
1271 db->tx_queue_cnt = 0;
1272 db->rx_avail_cnt = 0;
1273 netif_carrier_off(dev);
1274 db->wait_reset = 0;
1275
1276 /* Re-initilize DM910X board */
1277 dmfe_init_dm910x(dev);
1278
1279 /* Restart upper layer interface */
1280 netif_wake_queue(dev);
1281 }
1282
1283
1284 /*
1285 * free all allocated rx buffer
1286 */
1287
1288 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1289 {
1290 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1291
1292 /* free allocated rx buffer */
1293 while (db->rx_avail_cnt) {
1294 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1295 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1296 db->rx_avail_cnt--;
1297 }
1298 }
1299
1300
1301 /*
1302 * Reuse the SK buffer
1303 */
1304
1305 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1306 {
1307 struct rx_desc *rxptr = db->rx_insert_ptr;
1308
1309 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1310 rxptr->rx_skb_ptr = skb;
1311 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1312 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1313 wmb();
1314 rxptr->rdes0 = cpu_to_le32(0x80000000);
1315 db->rx_avail_cnt++;
1316 db->rx_insert_ptr = rxptr->next_rx_desc;
1317 } else
1318 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1319 }
1320
1321
1322 /*
1323 * Initialize transmit/Receive descriptor
1324 * Using Chain structure, and allocate Tx/Rx buffer
1325 */
1326
1327 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1328 {
1329 struct tx_desc *tmp_tx;
1330 struct rx_desc *tmp_rx;
1331 unsigned char *tmp_buf;
1332 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1333 dma_addr_t tmp_buf_dma;
1334 int i;
1335
1336 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1337
1338 /* tx descriptor start pointer */
1339 db->tx_insert_ptr = db->first_tx_desc;
1340 db->tx_remove_ptr = db->first_tx_desc;
1341 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1342
1343 /* rx descriptor start pointer */
1344 db->first_rx_desc = (void *)db->first_tx_desc +
1345 sizeof(struct tx_desc) * TX_DESC_CNT;
1346
1347 db->first_rx_desc_dma = db->first_tx_desc_dma +
1348 sizeof(struct tx_desc) * TX_DESC_CNT;
1349 db->rx_insert_ptr = db->first_rx_desc;
1350 db->rx_ready_ptr = db->first_rx_desc;
1351 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1352
1353 /* Init Transmit chain */
1354 tmp_buf = db->buf_pool_start;
1355 tmp_buf_dma = db->buf_pool_dma_start;
1356 tmp_tx_dma = db->first_tx_desc_dma;
1357 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1358 tmp_tx->tx_buf_ptr = tmp_buf;
1359 tmp_tx->tdes0 = cpu_to_le32(0);
1360 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1361 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1362 tmp_tx_dma += sizeof(struct tx_desc);
1363 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1364 tmp_tx->next_tx_desc = tmp_tx + 1;
1365 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1366 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1367 }
1368 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1369 tmp_tx->next_tx_desc = db->first_tx_desc;
1370
1371 /* Init Receive descriptor chain */
1372 tmp_rx_dma=db->first_rx_desc_dma;
1373 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1374 tmp_rx->rdes0 = cpu_to_le32(0);
1375 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1376 tmp_rx_dma += sizeof(struct rx_desc);
1377 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1378 tmp_rx->next_rx_desc = tmp_rx + 1;
1379 }
1380 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1381 tmp_rx->next_rx_desc = db->first_rx_desc;
1382
1383 /* pre-allocate Rx buffer */
1384 allocate_rx_buffer(db);
1385 }
1386
1387
1388 /*
1389 * Update CR6 value
1390 * Firstly stop DM910X , then written value and start
1391 */
1392
1393 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1394 {
1395 u32 cr6_tmp;
1396
1397 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1398 outl(cr6_tmp, ioaddr + DCR6);
1399 udelay(5);
1400 outl(cr6_data, ioaddr + DCR6);
1401 udelay(5);
1402 }
1403
1404
1405 /*
1406 * Send a setup frame for DM9132
1407 * This setup frame initilize DM910X address filter mode
1408 */
1409
1410 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1411 {
1412 struct dev_mc_list *mcptr;
1413 u16 * addrptr;
1414 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1415 u32 hash_val;
1416 u16 i, hash_table[4];
1417
1418 DMFE_DBUG(0, "dm9132_id_table()", 0);
1419
1420 /* Node address */
1421 addrptr = (u16 *) dev->dev_addr;
1422 outw(addrptr[0], ioaddr);
1423 ioaddr += 4;
1424 outw(addrptr[1], ioaddr);
1425 ioaddr += 4;
1426 outw(addrptr[2], ioaddr);
1427 ioaddr += 4;
1428
1429 /* Clear Hash Table */
1430 for (i = 0; i < 4; i++)
1431 hash_table[i] = 0x0;
1432
1433 /* broadcast address */
1434 hash_table[3] = 0x8000;
1435
1436 /* the multicast address in Hash Table : 64 bits */
1437 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1438 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1439 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1440 }
1441
1442 /* Write the hash table to MAC MD table */
1443 for (i = 0; i < 4; i++, ioaddr += 4)
1444 outw(hash_table[i], ioaddr);
1445 }
1446
1447
1448 /*
1449 * Send a setup frame for DM9102/DM9102A
1450 * This setup frame initilize DM910X address filter mode
1451 */
1452
1453 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1454 {
1455 struct dmfe_board_info *db = netdev_priv(dev);
1456 struct dev_mc_list *mcptr;
1457 struct tx_desc *txptr;
1458 u16 * addrptr;
1459 u32 * suptr;
1460 int i;
1461
1462 DMFE_DBUG(0, "send_filter_frame()", 0);
1463
1464 txptr = db->tx_insert_ptr;
1465 suptr = (u32 *) txptr->tx_buf_ptr;
1466
1467 /* Node address */
1468 addrptr = (u16 *) dev->dev_addr;
1469 *suptr++ = addrptr[0];
1470 *suptr++ = addrptr[1];
1471 *suptr++ = addrptr[2];
1472
1473 /* broadcast address */
1474 *suptr++ = 0xffff;
1475 *suptr++ = 0xffff;
1476 *suptr++ = 0xffff;
1477
1478 /* fit the multicast address */
1479 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1480 addrptr = (u16 *) mcptr->dmi_addr;
1481 *suptr++ = addrptr[0];
1482 *suptr++ = addrptr[1];
1483 *suptr++ = addrptr[2];
1484 }
1485
1486 for (; i<14; i++) {
1487 *suptr++ = 0xffff;
1488 *suptr++ = 0xffff;
1489 *suptr++ = 0xffff;
1490 }
1491
1492 /* prepare the setup frame */
1493 db->tx_insert_ptr = txptr->next_tx_desc;
1494 txptr->tdes1 = cpu_to_le32(0x890000c0);
1495
1496 /* Resource Check and Send the setup packet */
1497 if (!db->tx_packet_cnt) {
1498 /* Resource Empty */
1499 db->tx_packet_cnt++;
1500 txptr->tdes0 = cpu_to_le32(0x80000000);
1501 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1502 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1503 update_cr6(db->cr6_data, dev->base_addr);
1504 dev->trans_start = jiffies;
1505 } else
1506 db->tx_queue_cnt++; /* Put in TX queue */
1507 }
1508
1509
1510 /*
1511 * Allocate rx buffer,
1512 * As possible as allocate maxiumn Rx buffer
1513 */
1514
1515 static void allocate_rx_buffer(struct dmfe_board_info *db)
1516 {
1517 struct rx_desc *rxptr;
1518 struct sk_buff *skb;
1519
1520 rxptr = db->rx_insert_ptr;
1521
1522 while(db->rx_avail_cnt < RX_DESC_CNT) {
1523 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1524 break;
1525 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1526 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1527 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1528 wmb();
1529 rxptr->rdes0 = cpu_to_le32(0x80000000);
1530 rxptr = rxptr->next_rx_desc;
1531 db->rx_avail_cnt++;
1532 }
1533
1534 db->rx_insert_ptr = rxptr;
1535 }
1536
1537
1538 /*
1539 * Read one word data from the serial ROM
1540 */
1541
1542 static u16 read_srom_word(long ioaddr, int offset)
1543 {
1544 int i;
1545 u16 srom_data = 0;
1546 long cr9_ioaddr = ioaddr + DCR9;
1547
1548 outl(CR9_SROM_READ, cr9_ioaddr);
1549 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1550
1551 /* Send the Read Command 110b */
1552 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1553 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1554 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1555
1556 /* Send the offset */
1557 for (i = 5; i >= 0; i--) {
1558 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1559 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1560 }
1561
1562 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1563
1564 for (i = 16; i > 0; i--) {
1565 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1566 udelay(5);
1567 srom_data = (srom_data << 1) |
1568 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1569 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1570 udelay(5);
1571 }
1572
1573 outl(CR9_SROM_READ, cr9_ioaddr);
1574 return srom_data;
1575 }
1576
1577
1578 /*
1579 * Auto sense the media mode
1580 */
1581
1582 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1583 {
1584 u8 ErrFlag = 0;
1585 u16 phy_mode;
1586
1587 /* CR6 bit18=0, select 10/100M */
1588 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1589
1590 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1591 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1592
1593 if ( (phy_mode & 0x24) == 0x24 ) {
1594 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1595 phy_mode = phy_read(db->ioaddr,
1596 db->phy_addr, 7, db->chip_id) & 0xf000;
1597 else /* DM9102/DM9102A */
1598 phy_mode = phy_read(db->ioaddr,
1599 db->phy_addr, 17, db->chip_id) & 0xf000;
1600 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1601 switch (phy_mode) {
1602 case 0x1000: db->op_mode = DMFE_10MHF; break;
1603 case 0x2000: db->op_mode = DMFE_10MFD; break;
1604 case 0x4000: db->op_mode = DMFE_100MHF; break;
1605 case 0x8000: db->op_mode = DMFE_100MFD; break;
1606 default: db->op_mode = DMFE_10MHF;
1607 ErrFlag = 1;
1608 break;
1609 }
1610 } else {
1611 db->op_mode = DMFE_10MHF;
1612 DMFE_DBUG(0, "Link Failed :", phy_mode);
1613 ErrFlag = 1;
1614 }
1615
1616 return ErrFlag;
1617 }
1618
1619
1620 /*
1621 * Set 10/100 phyxcer capability
1622 * AUTO mode : phyxcer register4 is NIC capability
1623 * Force mode: phyxcer register4 is the force media
1624 */
1625
1626 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1627 {
1628 u16 phy_reg;
1629
1630 /* Select 10/100M phyxcer */
1631 db->cr6_data &= ~0x40000;
1632 update_cr6(db->cr6_data, db->ioaddr);
1633
1634 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1635 if (db->chip_id == PCI_DM9009_ID) {
1636 phy_reg = phy_read(db->ioaddr,
1637 db->phy_addr, 18, db->chip_id) & ~0x1000;
1638
1639 phy_write(db->ioaddr,
1640 db->phy_addr, 18, phy_reg, db->chip_id);
1641 }
1642
1643 /* Phyxcer capability setting */
1644 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1645
1646 if (db->media_mode & DMFE_AUTO) {
1647 /* AUTO Mode */
1648 phy_reg |= db->PHY_reg4;
1649 } else {
1650 /* Force Mode */
1651 switch(db->media_mode) {
1652 case DMFE_10MHF: phy_reg |= 0x20; break;
1653 case DMFE_10MFD: phy_reg |= 0x40; break;
1654 case DMFE_100MHF: phy_reg |= 0x80; break;
1655 case DMFE_100MFD: phy_reg |= 0x100; break;
1656 }
1657 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1658 }
1659
1660 /* Write new capability to Phyxcer Reg4 */
1661 if ( !(phy_reg & 0x01e0)) {
1662 phy_reg|=db->PHY_reg4;
1663 db->media_mode|=DMFE_AUTO;
1664 }
1665 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1666
1667 /* Restart Auto-Negotiation */
1668 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1669 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1670 if ( !db->chip_type )
1671 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1672 }
1673
1674
1675 /*
1676 * Process op-mode
1677 * AUTO mode : PHY controller in Auto-negotiation Mode
1678 * Force mode: PHY controller in force mode with HUB
1679 * N-way force capability with SWITCH
1680 */
1681
1682 static void dmfe_process_mode(struct dmfe_board_info *db)
1683 {
1684 u16 phy_reg;
1685
1686 /* Full Duplex Mode Check */
1687 if (db->op_mode & 0x4)
1688 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1689 else
1690 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1691
1692 /* Transciver Selection */
1693 if (db->op_mode & 0x10) /* 1M HomePNA */
1694 db->cr6_data |= 0x40000;/* External MII select */
1695 else
1696 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1697
1698 update_cr6(db->cr6_data, db->ioaddr);
1699
1700 /* 10/100M phyxcer force mode need */
1701 if ( !(db->media_mode & 0x18)) {
1702 /* Forece Mode */
1703 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1704 if ( !(phy_reg & 0x1) ) {
1705 /* parter without N-Way capability */
1706 phy_reg = 0x0;
1707 switch(db->op_mode) {
1708 case DMFE_10MHF: phy_reg = 0x0; break;
1709 case DMFE_10MFD: phy_reg = 0x100; break;
1710 case DMFE_100MHF: phy_reg = 0x2000; break;
1711 case DMFE_100MFD: phy_reg = 0x2100; break;
1712 }
1713 phy_write(db->ioaddr,
1714 db->phy_addr, 0, phy_reg, db->chip_id);
1715 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1716 mdelay(20);
1717 phy_write(db->ioaddr,
1718 db->phy_addr, 0, phy_reg, db->chip_id);
1719 }
1720 }
1721 }
1722
1723
1724 /*
1725 * Write a word to Phy register
1726 */
1727
1728 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1729 u16 phy_data, u32 chip_id)
1730 {
1731 u16 i;
1732 unsigned long ioaddr;
1733
1734 if (chip_id == PCI_DM9132_ID) {
1735 ioaddr = iobase + 0x80 + offset * 4;
1736 outw(phy_data, ioaddr);
1737 } else {
1738 /* DM9102/DM9102A Chip */
1739 ioaddr = iobase + DCR9;
1740
1741 /* Send 33 synchronization clock to Phy controller */
1742 for (i = 0; i < 35; i++)
1743 phy_write_1bit(ioaddr, PHY_DATA_1);
1744
1745 /* Send start command(01) to Phy */
1746 phy_write_1bit(ioaddr, PHY_DATA_0);
1747 phy_write_1bit(ioaddr, PHY_DATA_1);
1748
1749 /* Send write command(01) to Phy */
1750 phy_write_1bit(ioaddr, PHY_DATA_0);
1751 phy_write_1bit(ioaddr, PHY_DATA_1);
1752
1753 /* Send Phy address */
1754 for (i = 0x10; i > 0; i = i >> 1)
1755 phy_write_1bit(ioaddr,
1756 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1757
1758 /* Send register address */
1759 for (i = 0x10; i > 0; i = i >> 1)
1760 phy_write_1bit(ioaddr,
1761 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1762
1763 /* written trasnition */
1764 phy_write_1bit(ioaddr, PHY_DATA_1);
1765 phy_write_1bit(ioaddr, PHY_DATA_0);
1766
1767 /* Write a word data to PHY controller */
1768 for ( i = 0x8000; i > 0; i >>= 1)
1769 phy_write_1bit(ioaddr,
1770 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1771 }
1772 }
1773
1774
1775 /*
1776 * Read a word data from phy register
1777 */
1778
1779 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1780 {
1781 int i;
1782 u16 phy_data;
1783 unsigned long ioaddr;
1784
1785 if (chip_id == PCI_DM9132_ID) {
1786 /* DM9132 Chip */
1787 ioaddr = iobase + 0x80 + offset * 4;
1788 phy_data = inw(ioaddr);
1789 } else {
1790 /* DM9102/DM9102A Chip */
1791 ioaddr = iobase + DCR9;
1792
1793 /* Send 33 synchronization clock to Phy controller */
1794 for (i = 0; i < 35; i++)
1795 phy_write_1bit(ioaddr, PHY_DATA_1);
1796
1797 /* Send start command(01) to Phy */
1798 phy_write_1bit(ioaddr, PHY_DATA_0);
1799 phy_write_1bit(ioaddr, PHY_DATA_1);
1800
1801 /* Send read command(10) to Phy */
1802 phy_write_1bit(ioaddr, PHY_DATA_1);
1803 phy_write_1bit(ioaddr, PHY_DATA_0);
1804
1805 /* Send Phy address */
1806 for (i = 0x10; i > 0; i = i >> 1)
1807 phy_write_1bit(ioaddr,
1808 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1809
1810 /* Send register address */
1811 for (i = 0x10; i > 0; i = i >> 1)
1812 phy_write_1bit(ioaddr,
1813 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1814
1815 /* Skip transition state */
1816 phy_read_1bit(ioaddr);
1817
1818 /* read 16bit data */
1819 for (phy_data = 0, i = 0; i < 16; i++) {
1820 phy_data <<= 1;
1821 phy_data |= phy_read_1bit(ioaddr);
1822 }
1823 }
1824
1825 return phy_data;
1826 }
1827
1828
1829 /*
1830 * Write one bit data to Phy Controller
1831 */
1832
1833 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1834 {
1835 outl(phy_data, ioaddr); /* MII Clock Low */
1836 udelay(1);
1837 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1838 udelay(1);
1839 outl(phy_data, ioaddr); /* MII Clock Low */
1840 udelay(1);
1841 }
1842
1843
1844 /*
1845 * Read one bit phy data from PHY controller
1846 */
1847
1848 static u16 phy_read_1bit(unsigned long ioaddr)
1849 {
1850 u16 phy_data;
1851
1852 outl(0x50000, ioaddr);
1853 udelay(1);
1854 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1855 outl(0x40000, ioaddr);
1856 udelay(1);
1857
1858 return phy_data;
1859 }
1860
1861
1862 /*
1863 * Parser SROM and media mode
1864 */
1865
1866 static void dmfe_parse_srom(struct dmfe_board_info * db)
1867 {
1868 char * srom = db->srom;
1869 int dmfe_mode, tmp_reg;
1870
1871 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1872
1873 /* Init CR15 */
1874 db->cr15_data = CR15_DEFAULT;
1875
1876 /* Check SROM Version */
1877 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1878 /* SROM V4.01 */
1879 /* Get NIC support media mode */
1880 db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2);
1881 db->PHY_reg4 = 0;
1882 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1883 switch( db->NIC_capability & tmp_reg ) {
1884 case 0x1: db->PHY_reg4 |= 0x0020; break;
1885 case 0x2: db->PHY_reg4 |= 0x0040; break;
1886 case 0x4: db->PHY_reg4 |= 0x0080; break;
1887 case 0x8: db->PHY_reg4 |= 0x0100; break;
1888 }
1889 }
1890
1891 /* Media Mode Force or not check */
1892 dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) &
1893 le32_to_cpup((__le32 *)srom + 36/4);
1894 switch(dmfe_mode) {
1895 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1896 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1897 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1898 case 0x100:
1899 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1900 }
1901
1902 /* Special Function setting */
1903 /* VLAN function */
1904 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1905 db->cr15_data |= 0x40;
1906
1907 /* Flow Control */
1908 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1909 db->cr15_data |= 0x400;
1910
1911 /* TX pause packet */
1912 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1913 db->cr15_data |= 0x9800;
1914 }
1915
1916 /* Parse HPNA parameter */
1917 db->HPNA_command = 1;
1918
1919 /* Accept remote command or not */
1920 if (HPNA_rx_cmd == 0)
1921 db->HPNA_command |= 0x8000;
1922
1923 /* Issue remote command & operation mode */
1924 if (HPNA_tx_cmd == 1)
1925 switch(HPNA_mode) { /* Issue Remote Command */
1926 case 0: db->HPNA_command |= 0x0904; break;
1927 case 1: db->HPNA_command |= 0x0a00; break;
1928 case 2: db->HPNA_command |= 0x0506; break;
1929 case 3: db->HPNA_command |= 0x0602; break;
1930 }
1931 else
1932 switch(HPNA_mode) { /* Don't Issue */
1933 case 0: db->HPNA_command |= 0x0004; break;
1934 case 1: db->HPNA_command |= 0x0000; break;
1935 case 2: db->HPNA_command |= 0x0006; break;
1936 case 3: db->HPNA_command |= 0x0002; break;
1937 }
1938
1939 /* Check DM9801 or DM9802 present or not */
1940 db->HPNA_present = 0;
1941 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1942 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1943 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1944 /* DM9801 or DM9802 present */
1945 db->HPNA_timer = 8;
1946 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1947 /* DM9801 HomeRun */
1948 db->HPNA_present = 1;
1949 dmfe_program_DM9801(db, tmp_reg);
1950 } else {
1951 /* DM9802 LongRun */
1952 db->HPNA_present = 2;
1953 dmfe_program_DM9802(db);
1954 }
1955 }
1956
1957 }
1958
1959
1960 /*
1961 * Init HomeRun DM9801
1962 */
1963
1964 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1965 {
1966 uint reg17, reg25;
1967
1968 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1969 switch(HPNA_rev) {
1970 case 0xb900: /* DM9801 E3 */
1971 db->HPNA_command |= 0x1000;
1972 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
1973 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
1974 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1975 break;
1976 case 0xb901: /* DM9801 E4 */
1977 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1978 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
1979 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1980 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
1981 break;
1982 case 0xb902: /* DM9801 E5 */
1983 case 0xb903: /* DM9801 E6 */
1984 default:
1985 db->HPNA_command |= 0x1000;
1986 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
1987 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
1988 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
1989 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
1990 break;
1991 }
1992 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
1993 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
1994 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
1995 }
1996
1997
1998 /*
1999 * Init HomeRun DM9802
2000 */
2001
2002 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2003 {
2004 uint phy_reg;
2005
2006 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2007 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2008 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2009 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2010 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2011 }
2012
2013
2014 /*
2015 * Check remote HPNA power and speed status. If not correct,
2016 * issue command again.
2017 */
2018
2019 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2020 {
2021 uint phy_reg;
2022
2023 /* Got remote device status */
2024 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2025 switch(phy_reg) {
2026 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2027 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2028 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2029 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2030 }
2031
2032 /* Check remote device status match our setting ot not */
2033 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2034 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2035 db->chip_id);
2036 db->HPNA_timer=8;
2037 } else
2038 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2039 }
2040
2041
2042
2043 static struct pci_device_id dmfe_pci_tbl[] = {
2044 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2045 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2046 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2047 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2048 { 0, }
2049 };
2050 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2051
2052
2053 static struct pci_driver dmfe_driver = {
2054 .name = "dmfe",
2055 .id_table = dmfe_pci_tbl,
2056 .probe = dmfe_init_one,
2057 .remove = __devexit_p(dmfe_remove_one),
2058 };
2059
2060 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2061 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2062 MODULE_LICENSE("GPL");
2063 MODULE_VERSION(DRV_VERSION);
2064
2065 module_param(debug, int, 0);
2066 module_param(mode, byte, 0);
2067 module_param(cr6set, int, 0);
2068 module_param(chkmode, byte, 0);
2069 module_param(HPNA_mode, byte, 0);
2070 module_param(HPNA_rx_cmd, byte, 0);
2071 module_param(HPNA_tx_cmd, byte, 0);
2072 module_param(HPNA_NoiseFloor, byte, 0);
2073 module_param(SF_mode, byte, 0);
2074 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2075 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2076 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2077
2078 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2079 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2080
2081 /* Description:
2082 * when user used insmod to add module, system invoked init_module()
2083 * to initilize and register.
2084 */
2085
2086 static int __init dmfe_init_module(void)
2087 {
2088 int rc;
2089
2090 printk(version);
2091 printed_version = 1;
2092
2093 DMFE_DBUG(0, "init_module() ", debug);
2094
2095 if (debug)
2096 dmfe_debug = debug; /* set debug flag */
2097 if (cr6set)
2098 dmfe_cr6_user_set = cr6set;
2099
2100 switch(mode) {
2101 case DMFE_10MHF:
2102 case DMFE_100MHF:
2103 case DMFE_10MFD:
2104 case DMFE_100MFD:
2105 case DMFE_1M_HPNA:
2106 dmfe_media_mode = mode;
2107 break;
2108 default:dmfe_media_mode = DMFE_AUTO;
2109 break;
2110 }
2111
2112 if (HPNA_mode > 4)
2113 HPNA_mode = 0; /* Default: LP/HS */
2114 if (HPNA_rx_cmd > 1)
2115 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2116 if (HPNA_tx_cmd > 1)
2117 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2118 if (HPNA_NoiseFloor > 15)
2119 HPNA_NoiseFloor = 0;
2120
2121 rc = pci_register_driver(&dmfe_driver);
2122 if (rc < 0)
2123 return rc;
2124
2125 return 0;
2126 }
2127
2128
2129 /*
2130 * Description:
2131 * when user used rmmod to delete module, system invoked clean_module()
2132 * to un-register all registered services.
2133 */
2134
2135 static void __exit dmfe_cleanup_module(void)
2136 {
2137 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2138 pci_unregister_driver(&dmfe_driver);
2139 }
2140
2141 module_init(dmfe_init_module);
2142 module_exit(dmfe_cleanup_module);