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PCI: Change all drivers to use pci_device->revision
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / tulip / de4x5.c
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
437 present.
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444 */
445
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/slab.h>
454 #include <linux/pci.h>
455 #include <linux/eisa.h>
456 #include <linux/delay.h>
457 #include <linux/init.h>
458 #include <linux/spinlock.h>
459 #include <linux/crc32.h>
460 #include <linux/netdevice.h>
461 #include <linux/etherdevice.h>
462 #include <linux/skbuff.h>
463 #include <linux/time.h>
464 #include <linux/types.h>
465 #include <linux/unistd.h>
466 #include <linux/ctype.h>
467 #include <linux/dma-mapping.h>
468 #include <linux/moduleparam.h>
469 #include <linux/bitops.h>
470
471 #include <asm/io.h>
472 #include <asm/dma.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
479
480 #include "de4x5.h"
481
482 static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
483
484 #define c_char const char
485 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
486
487 /*
488 ** MII Information
489 */
490 struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499 };
500
501 struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518 };
519
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522 struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530 };
531
532 /*
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
535 */
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542 };
543
544 /*
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548 */
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553 /*
554 ** Define special SROM detection cases
555 */
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559 };
560
561 #define SMC 1
562 #define ACCTON 2
563
564 /*
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
568 */
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574 };
575
576
577 #ifdef DE4X5_DEBUG
578 static int de4x5_debug = DE4X5_DEBUG;
579 #else
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582 #endif
583
584 /*
585 ** Allow per adapter set up. For modules this is simply a command line
586 ** parameter, e.g.:
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588 **
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591 ** here
592 */
593 #ifdef DE4X5_PARM
594 static char *args = DE4X5_PARM;
595 #else
596 static char *args;
597 #endif
598
599 struct parameters {
600 bool fdx;
601 int autosense;
602 };
603
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608 /*
609 ** Ethernet PROM defines
610 */
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
613
614 /*
615 ** Ethernet Info
616 */
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627 /*
628 ** EISA bus defines
629 */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
637
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640 /*
641 ** Ethernet PROM defines for DC21040
642 */
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
645
646 /*
647 ** PCI Bus defines
648 */
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653 /*
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
658 */
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670 #define DESC_ALIGN
671
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
673 static int dec_only;
674 #else
675 static int dec_only = 1;
676 #endif
677
678 /*
679 ** DE4X5 IRQ ENABLE/DISABLE
680 */
681 #define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684 }
685
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690 }
691
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695 }
696
697 #define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701 }
702
703 /*
704 ** DE4X5 START/STOP
705 */
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710 }
711
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716 }
717
718 /*
719 ** DE4X5 SIA RESET
720 */
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723 /*
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725 */
726 #define DE4X5_AUTOSENSE_MS 250
727
728 /*
729 ** SROM Structure
730 */
731 struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742 };
743 #define SUB_VENDOR_ID 0x500a
744
745 /*
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
752 */
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758 struct de4x5_desc {
759 volatile s32 status;
760 u32 des1;
761 u32 buf;
762 u32 next;
763 DESC_ALIGN
764 };
765
766 /*
767 ** The DE4X5 private structure
768 */
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773 struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785 };
786
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff *skb; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860 };
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
900 static int de4x5_close(struct net_device *dev);
901 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903 static void set_multicast_list(struct net_device *dev);
904 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906 /*
907 ** Private functions
908 */
909 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910 static int de4x5_init(struct net_device *dev);
911 static int de4x5_sw_reset(struct net_device *dev);
912 static int de4x5_rx(struct net_device *dev);
913 static int de4x5_tx(struct net_device *dev);
914 static int de4x5_ast(struct net_device *dev);
915 static int de4x5_txur(struct net_device *dev);
916 static int de4x5_rx_ovfc(struct net_device *dev);
917
918 static int autoconf_media(struct net_device *dev);
919 static void create_packet(struct net_device *dev, char *frame, int len);
920 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921 static int dc21040_autoconf(struct net_device *dev);
922 static int dc21041_autoconf(struct net_device *dev);
923 static int dc21140m_autoconf(struct net_device *dev);
924 static int dc2114x_autoconf(struct net_device *dev);
925 static int srom_autoconf(struct net_device *dev);
926 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929 static int test_for_100Mb(struct net_device *dev, int msec);
930 static int wait_for_link(struct net_device *dev);
931 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
932 static int is_spd_100(struct net_device *dev);
933 static int is_100_up(struct net_device *dev);
934 static int is_10_up(struct net_device *dev);
935 static int is_anc_capable(struct net_device *dev);
936 static int ping_media(struct net_device *dev, int msec);
937 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938 static void de4x5_free_rx_buffs(struct net_device *dev);
939 static void de4x5_free_tx_buffs(struct net_device *dev);
940 static void de4x5_save_skbs(struct net_device *dev);
941 static void de4x5_rst_desc_ring(struct net_device *dev);
942 static void de4x5_cache_state(struct net_device *dev, int flag);
943 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946 static void de4x5_setup_intr(struct net_device *dev);
947 static void de4x5_init_connection(struct net_device *dev);
948 static int de4x5_reset_phy(struct net_device *dev);
949 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951 static int test_tp(struct net_device *dev, s32 msec);
952 static int EISA_signature(char *name, struct device *device);
953 static int PCI_signature(char *name, struct de4x5_private *lp);
954 static void DevicePresent(struct net_device *dev, u_long iobase);
955 static void enet_addr_rst(u_long aprom_addr);
956 static int de4x5_bad_srom(struct de4x5_private *lp);
957 static short srom_rd(u_long address, u_char offset);
958 static void srom_latch(u_int command, u_long address);
959 static void srom_command(u_int command, u_long address);
960 static void srom_address(u_int command, u_long address, u_char offset);
961 static short srom_data(u_int command, u_long address);
962 /*static void srom_busy(u_int command, u_long address);*/
963 static void sendto_srom(u_int command, u_long addr);
964 static int getfrom_srom(u_long addr);
965 static int srom_map_media(struct net_device *dev);
966 static int srom_infoleaf_info(struct net_device *dev);
967 static void srom_init(struct net_device *dev);
968 static void srom_exec(struct net_device *dev, u_char *p);
969 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static int mii_rdata(u_long ioaddr);
972 static void mii_wdata(int data, int len, u_long ioaddr);
973 static void mii_ta(u_long rw, u_long ioaddr);
974 static int mii_swap(int data, int len);
975 static void mii_address(u_char addr, u_long ioaddr);
976 static void sendto_mii(u32 command, int data, u_long ioaddr);
977 static int getfrom_mii(u32 command, u_long ioaddr);
978 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979 static int mii_get_phy(struct net_device *dev);
980 static void SetMulticastFilter(struct net_device *dev);
981 static int get_hw_addr(struct net_device *dev);
982 static void srom_repair(struct net_device *dev, int card);
983 static int test_bad_enet(struct net_device *dev, int status);
984 static int an_exception(struct de4x5_private *lp);
985 static char *build_setup_frame(struct net_device *dev, int mode);
986 static void disable_ast(struct net_device *dev);
987 static void enable_ast(struct net_device *dev, u32 time_out);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
992 static void yawn(struct net_device *dev, int state);
993 static void de4x5_parse_params(struct net_device *dev);
994 static void de4x5_dbg_open(struct net_device *dev);
995 static void de4x5_dbg_mii(struct net_device *dev, int k);
996 static void de4x5_dbg_media(struct net_device *dev);
997 static void de4x5_dbg_srom(struct de4x5_srom *p);
998 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
999 static int de4x5_strncmp(char *a, char *b, int n);
1000 static int dc21041_infoleaf(struct net_device *dev);
1001 static int dc21140_infoleaf(struct net_device *dev);
1002 static int dc21142_infoleaf(struct net_device *dev);
1003 static int dc21143_infoleaf(struct net_device *dev);
1004 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1010 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1011
1012 /*
1013 ** Note now that module autoprobing is allowed under EISA and PCI. The
1014 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1015 ** to "do the right thing".
1016 */
1017
1018 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1019
1020 module_param(io, int, 0);
1021 module_param(de4x5_debug, int, 0);
1022 module_param(dec_only, int, 0);
1023 module_param(args, charp, 0);
1024
1025 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1026 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1027 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1028 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1029 MODULE_LICENSE("GPL");
1030
1031 /*
1032 ** List the SROM infoleaf functions and chipsets
1033 */
1034 struct InfoLeaf {
1035 int chipset;
1036 int (*fn)(struct net_device *);
1037 };
1038 static struct InfoLeaf infoleaf_array[] = {
1039 {DC21041, dc21041_infoleaf},
1040 {DC21140, dc21140_infoleaf},
1041 {DC21142, dc21142_infoleaf},
1042 {DC21143, dc21143_infoleaf}
1043 };
1044 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1045
1046 /*
1047 ** List the SROM info block functions
1048 */
1049 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1050 type0_infoblock,
1051 type1_infoblock,
1052 type2_infoblock,
1053 type3_infoblock,
1054 type4_infoblock,
1055 type5_infoblock,
1056 compact_infoblock
1057 };
1058
1059 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1060
1061 /*
1062 ** Miscellaneous defines...
1063 */
1064 #define RESET_DE4X5 {\
1065 int i;\
1066 i=inl(DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i | BMR_SWR, DE4X5_BMR);\
1069 mdelay(1);\
1070 outl(i, DE4X5_BMR);\
1071 mdelay(1);\
1072 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1073 mdelay(1);\
1074 }
1075
1076 #define PHY_HARD_RESET {\
1077 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1078 mdelay(1); /* Assert for 1ms */\
1079 outl(0x00, DE4X5_GEP);\
1080 mdelay(2); /* Wait for 2ms */\
1081 }
1082
1083
1084 static int __devinit
1085 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1086 {
1087 char name[DE4X5_NAME_LENGTH + 1];
1088 struct de4x5_private *lp = netdev_priv(dev);
1089 struct pci_dev *pdev = NULL;
1090 int i, status=0;
1091
1092 gendev->driver_data = dev;
1093
1094 /* Ensure we're not sleeping */
1095 if (lp->bus == EISA) {
1096 outb(WAKEUP, PCI_CFPM);
1097 } else {
1098 pdev = to_pci_dev (gendev);
1099 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1100 }
1101 mdelay(10);
1102
1103 RESET_DE4X5;
1104
1105 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1106 return -ENXIO; /* Hardware could not reset */
1107 }
1108
1109 /*
1110 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1111 */
1112 lp->useSROM = false;
1113 if (lp->bus == PCI) {
1114 PCI_signature(name, lp);
1115 } else {
1116 EISA_signature(name, gendev);
1117 }
1118
1119 if (*name == '\0') { /* Not found a board signature */
1120 return -ENXIO;
1121 }
1122
1123 dev->base_addr = iobase;
1124 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1125
1126 printk(", h/w address ");
1127 status = get_hw_addr(dev);
1128 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1129 printk("%2.2x:", dev->dev_addr[i]);
1130 }
1131 printk("%2.2x,\n", dev->dev_addr[i]);
1132
1133 if (status != 0) {
1134 printk(" which has an Ethernet PROM CRC error.\n");
1135 return -ENXIO;
1136 } else {
1137 lp->cache.gepc = GEP_INIT;
1138 lp->asBit = GEP_SLNK;
1139 lp->asPolarity = GEP_SLNK;
1140 lp->asBitValid = ~0;
1141 lp->timeout = -1;
1142 lp->gendev = gendev;
1143 spin_lock_init(&lp->lock);
1144 init_timer(&lp->timer);
1145 de4x5_parse_params(dev);
1146
1147 /*
1148 ** Choose correct autosensing in case someone messed up
1149 */
1150 lp->autosense = lp->params.autosense;
1151 if (lp->chipset != DC21140) {
1152 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1153 lp->params.autosense = TP;
1154 }
1155 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1156 lp->params.autosense = BNC;
1157 }
1158 }
1159 lp->fdx = lp->params.fdx;
1160 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1161
1162 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1163 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1164 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1165 #endif
1166 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1167 &lp->dma_rings, GFP_ATOMIC);
1168 if (lp->rx_ring == NULL) {
1169 return -ENOMEM;
1170 }
1171
1172 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1173
1174 /*
1175 ** Set up the RX descriptor ring (Intels)
1176 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1177 */
1178 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1179 for (i=0; i<NUM_RX_DESC; i++) {
1180 lp->rx_ring[i].status = 0;
1181 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1182 lp->rx_ring[i].buf = 0;
1183 lp->rx_ring[i].next = 0;
1184 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1185 }
1186
1187 #else
1188 {
1189 dma_addr_t dma_rx_bufs;
1190
1191 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1192 * sizeof(struct de4x5_desc);
1193 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1194 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1195 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1196 for (i=0; i<NUM_RX_DESC; i++) {
1197 lp->rx_ring[i].status = 0;
1198 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1199 lp->rx_ring[i].buf =
1200 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1201 lp->rx_ring[i].next = 0;
1202 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1203 }
1204
1205 }
1206 #endif
1207
1208 barrier();
1209
1210 lp->rxRingSize = NUM_RX_DESC;
1211 lp->txRingSize = NUM_TX_DESC;
1212
1213 /* Write the end of list marker to the descriptor lists */
1214 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1215 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1216
1217 /* Tell the adapter where the TX/RX rings are located. */
1218 outl(lp->dma_rings, DE4X5_RRBA);
1219 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1220 DE4X5_TRBA);
1221
1222 /* Initialise the IRQ mask and Enable/Disable */
1223 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1224 lp->irq_en = IMR_NIM | IMR_AIM;
1225
1226 /* Create a loopback packet frame for later media probing */
1227 create_packet(dev, lp->frame, sizeof(lp->frame));
1228
1229 /* Check if the RX overflow bug needs testing for */
1230 i = lp->cfrv & 0x000000fe;
1231 if ((lp->chipset == DC21140) && (i == 0x20)) {
1232 lp->rx_ovf = 1;
1233 }
1234
1235 /* Initialise the SROM pointers if possible */
1236 if (lp->useSROM) {
1237 lp->state = INITIALISED;
1238 if (srom_infoleaf_info(dev)) {
1239 dma_free_coherent (gendev, lp->dma_size,
1240 lp->rx_ring, lp->dma_rings);
1241 return -ENXIO;
1242 }
1243 srom_init(dev);
1244 }
1245
1246 lp->state = CLOSED;
1247
1248 /*
1249 ** Check for an MII interface
1250 */
1251 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1252 mii_get_phy(dev);
1253 }
1254
1255 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1256 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1257 }
1258
1259 if (de4x5_debug & DEBUG_VERSION) {
1260 printk(version);
1261 }
1262
1263 /* The DE4X5-specific entries in the device structure. */
1264 SET_MODULE_OWNER(dev);
1265 SET_NETDEV_DEV(dev, gendev);
1266 dev->open = &de4x5_open;
1267 dev->hard_start_xmit = &de4x5_queue_pkt;
1268 dev->stop = &de4x5_close;
1269 dev->get_stats = &de4x5_get_stats;
1270 dev->set_multicast_list = &set_multicast_list;
1271 dev->do_ioctl = &de4x5_ioctl;
1272
1273 dev->mem_start = 0;
1274
1275 /* Fill in the generic fields of the device structure. */
1276 if ((status = register_netdev (dev))) {
1277 dma_free_coherent (gendev, lp->dma_size,
1278 lp->rx_ring, lp->dma_rings);
1279 return status;
1280 }
1281
1282 /* Let the adapter sleep to save power */
1283 yawn(dev, SLEEP);
1284
1285 return status;
1286 }
1287
1288
1289 static int
1290 de4x5_open(struct net_device *dev)
1291 {
1292 struct de4x5_private *lp = netdev_priv(dev);
1293 u_long iobase = dev->base_addr;
1294 int i, status = 0;
1295 s32 omr;
1296
1297 /* Allocate the RX buffers */
1298 for (i=0; i<lp->rxRingSize; i++) {
1299 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1300 de4x5_free_rx_buffs(dev);
1301 return -EAGAIN;
1302 }
1303 }
1304
1305 /*
1306 ** Wake up the adapter
1307 */
1308 yawn(dev, WAKEUP);
1309
1310 /*
1311 ** Re-initialize the DE4X5...
1312 */
1313 status = de4x5_init(dev);
1314 spin_lock_init(&lp->lock);
1315 lp->state = OPEN;
1316 de4x5_dbg_open(dev);
1317
1318 if (request_irq(dev->irq, (void *)de4x5_interrupt, IRQF_SHARED,
1319 lp->adapter_name, dev)) {
1320 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1321 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1322 lp->adapter_name, dev)) {
1323 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1324 disable_ast(dev);
1325 de4x5_free_rx_buffs(dev);
1326 de4x5_free_tx_buffs(dev);
1327 yawn(dev, SLEEP);
1328 lp->state = CLOSED;
1329 return -EAGAIN;
1330 } else {
1331 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1332 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1333 }
1334 }
1335
1336 lp->interrupt = UNMASK_INTERRUPTS;
1337 dev->trans_start = jiffies;
1338
1339 START_DE4X5;
1340
1341 de4x5_setup_intr(dev);
1342
1343 if (de4x5_debug & DEBUG_OPEN) {
1344 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1345 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1346 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1347 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1348 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1349 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1350 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1351 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1352 }
1353
1354 return status;
1355 }
1356
1357 /*
1358 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1359 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1360 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1361 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1362 ** to be data corruption problems if it is larger (UDP errors seen from a
1363 ** ttcp source).
1364 */
1365 static int
1366 de4x5_init(struct net_device *dev)
1367 {
1368 /* Lock out other processes whilst setting up the hardware */
1369 netif_stop_queue(dev);
1370
1371 de4x5_sw_reset(dev);
1372
1373 /* Autoconfigure the connected port */
1374 autoconf_media(dev);
1375
1376 return 0;
1377 }
1378
1379 static int
1380 de4x5_sw_reset(struct net_device *dev)
1381 {
1382 struct de4x5_private *lp = netdev_priv(dev);
1383 u_long iobase = dev->base_addr;
1384 int i, j, status = 0;
1385 s32 bmr, omr;
1386
1387 /* Select the MII or SRL port now and RESET the MAC */
1388 if (!lp->useSROM) {
1389 if (lp->phy[lp->active].id != 0) {
1390 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1391 } else {
1392 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1393 }
1394 de4x5_switch_mac_port(dev);
1395 }
1396
1397 /*
1398 ** Set the programmable burst length to 8 longwords for all the DC21140
1399 ** Fasternet chips and 4 longwords for all others: DMA errors result
1400 ** without these values. Cache align 16 long.
1401 */
1402 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1403 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1404 outl(bmr, DE4X5_BMR);
1405
1406 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1407 if (lp->chipset == DC21140) {
1408 omr |= (OMR_SDP | OMR_SB);
1409 }
1410 lp->setup_f = PERFECT;
1411 outl(lp->dma_rings, DE4X5_RRBA);
1412 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1413 DE4X5_TRBA);
1414
1415 lp->rx_new = lp->rx_old = 0;
1416 lp->tx_new = lp->tx_old = 0;
1417
1418 for (i = 0; i < lp->rxRingSize; i++) {
1419 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1420 }
1421
1422 for (i = 0; i < lp->txRingSize; i++) {
1423 lp->tx_ring[i].status = cpu_to_le32(0);
1424 }
1425
1426 barrier();
1427
1428 /* Build the setup frame depending on filtering mode */
1429 SetMulticastFilter(dev);
1430
1431 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1432 outl(omr|OMR_ST, DE4X5_OMR);
1433
1434 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1435
1436 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1437 mdelay(1);
1438 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1439 }
1440 outl(omr, DE4X5_OMR); /* Stop everything! */
1441
1442 if (j == 0) {
1443 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1444 inl(DE4X5_STS));
1445 status = -EIO;
1446 }
1447
1448 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1449 lp->tx_old = lp->tx_new;
1450
1451 return status;
1452 }
1453
1454 /*
1455 ** Writes a socket buffer address to the next available transmit descriptor.
1456 */
1457 static int
1458 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1459 {
1460 struct de4x5_private *lp = netdev_priv(dev);
1461 u_long iobase = dev->base_addr;
1462 int status = 0;
1463 u_long flags = 0;
1464
1465 netif_stop_queue(dev);
1466 if (!lp->tx_enable) { /* Cannot send for now */
1467 return -1;
1468 }
1469
1470 /*
1471 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1472 ** interrupts are lost by delayed descriptor status updates relative to
1473 ** the irq assertion, especially with a busy PCI bus.
1474 */
1475 spin_lock_irqsave(&lp->lock, flags);
1476 de4x5_tx(dev);
1477 spin_unlock_irqrestore(&lp->lock, flags);
1478
1479 /* Test if cache is already locked - requeue skb if so */
1480 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1481 return -1;
1482
1483 /* Transmit descriptor ring full or stale skb */
1484 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1485 if (lp->interrupt) {
1486 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1487 } else {
1488 de4x5_put_cache(dev, skb);
1489 }
1490 if (de4x5_debug & DEBUG_TX) {
1491 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1492 }
1493 } else if (skb->len > 0) {
1494 /* If we already have stuff queued locally, use that first */
1495 if (lp->cache.skb && !lp->interrupt) {
1496 de4x5_put_cache(dev, skb);
1497 skb = de4x5_get_cache(dev);
1498 }
1499
1500 while (skb && !netif_queue_stopped(dev) &&
1501 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1502 spin_lock_irqsave(&lp->lock, flags);
1503 netif_stop_queue(dev);
1504 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1505 lp->stats.tx_bytes += skb->len;
1506 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1507
1508 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1509 dev->trans_start = jiffies;
1510
1511 if (TX_BUFFS_AVAIL) {
1512 netif_start_queue(dev); /* Another pkt may be queued */
1513 }
1514 skb = de4x5_get_cache(dev);
1515 spin_unlock_irqrestore(&lp->lock, flags);
1516 }
1517 if (skb) de4x5_putb_cache(dev, skb);
1518 }
1519
1520 lp->cache.lock = 0;
1521
1522 return status;
1523 }
1524
1525 /*
1526 ** The DE4X5 interrupt handler.
1527 **
1528 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1529 ** so that the asserted interrupt always has some real data to work with -
1530 ** if these I/O accesses are ever changed to memory accesses, ensure the
1531 ** STS write is read immediately to complete the transaction if the adapter
1532 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1533 ** is high and descriptor status bits cannot be set before the associated
1534 ** interrupt is asserted and this routine entered.
1535 */
1536 static irqreturn_t
1537 de4x5_interrupt(int irq, void *dev_id)
1538 {
1539 struct net_device *dev = dev_id;
1540 struct de4x5_private *lp;
1541 s32 imr, omr, sts, limit;
1542 u_long iobase;
1543 unsigned int handled = 0;
1544
1545 lp = netdev_priv(dev);
1546 spin_lock(&lp->lock);
1547 iobase = dev->base_addr;
1548
1549 DISABLE_IRQs; /* Ensure non re-entrancy */
1550
1551 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1552 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1553
1554 synchronize_irq(dev->irq);
1555
1556 for (limit=0; limit<8; limit++) {
1557 sts = inl(DE4X5_STS); /* Read IRQ status */
1558 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1559
1560 if (!(sts & lp->irq_mask)) break;/* All done */
1561 handled = 1;
1562
1563 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1564 de4x5_rx(dev);
1565
1566 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1567 de4x5_tx(dev);
1568
1569 if (sts & STS_LNF) { /* TP Link has failed */
1570 lp->irq_mask &= ~IMR_LFM;
1571 }
1572
1573 if (sts & STS_UNF) { /* Transmit underrun */
1574 de4x5_txur(dev);
1575 }
1576
1577 if (sts & STS_SE) { /* Bus Error */
1578 STOP_DE4X5;
1579 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1580 dev->name, sts);
1581 spin_unlock(&lp->lock);
1582 return IRQ_HANDLED;
1583 }
1584 }
1585
1586 /* Load the TX ring with any locally stored packets */
1587 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1588 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1589 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1590 }
1591 lp->cache.lock = 0;
1592 }
1593
1594 lp->interrupt = UNMASK_INTERRUPTS;
1595 ENABLE_IRQs;
1596 spin_unlock(&lp->lock);
1597
1598 return IRQ_RETVAL(handled);
1599 }
1600
1601 static int
1602 de4x5_rx(struct net_device *dev)
1603 {
1604 struct de4x5_private *lp = netdev_priv(dev);
1605 u_long iobase = dev->base_addr;
1606 int entry;
1607 s32 status;
1608
1609 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1610 entry=lp->rx_new) {
1611 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1612
1613 if (lp->rx_ovf) {
1614 if (inl(DE4X5_MFC) & MFC_FOCM) {
1615 de4x5_rx_ovfc(dev);
1616 break;
1617 }
1618 }
1619
1620 if (status & RD_FS) { /* Remember the start of frame */
1621 lp->rx_old = entry;
1622 }
1623
1624 if (status & RD_LS) { /* Valid frame status */
1625 if (lp->tx_enable) lp->linkOK++;
1626 if (status & RD_ES) { /* There was an error. */
1627 lp->stats.rx_errors++; /* Update the error stats. */
1628 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1629 if (status & RD_CE) lp->stats.rx_crc_errors++;
1630 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1631 if (status & RD_TL) lp->stats.rx_length_errors++;
1632 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1633 if (status & RD_CS) lp->pktStats.rx_collision++;
1634 if (status & RD_DB) lp->pktStats.rx_dribble++;
1635 if (status & RD_OF) lp->pktStats.rx_overflow++;
1636 } else { /* A valid frame received */
1637 struct sk_buff *skb;
1638 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1639 >> 16) - 4;
1640
1641 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1642 printk("%s: Insufficient memory; nuking packet.\n",
1643 dev->name);
1644 lp->stats.rx_dropped++;
1645 } else {
1646 de4x5_dbg_rx(skb, pkt_len);
1647
1648 /* Push up the protocol stack */
1649 skb->protocol=eth_type_trans(skb,dev);
1650 de4x5_local_stats(dev, skb->data, pkt_len);
1651 netif_rx(skb);
1652
1653 /* Update stats */
1654 dev->last_rx = jiffies;
1655 lp->stats.rx_packets++;
1656 lp->stats.rx_bytes += pkt_len;
1657 }
1658 }
1659
1660 /* Change buffer ownership for this frame, back to the adapter */
1661 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1662 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1663 barrier();
1664 }
1665 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1666 barrier();
1667 }
1668
1669 /*
1670 ** Update entry information
1671 */
1672 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1673 }
1674
1675 return 0;
1676 }
1677
1678 static inline void
1679 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680 {
1681 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1682 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683 DMA_TO_DEVICE);
1684 if ((u_long) lp->tx_skb[entry] > 1)
1685 dev_kfree_skb_irq(lp->tx_skb[entry]);
1686 lp->tx_skb[entry] = NULL;
1687 }
1688
1689 /*
1690 ** Buffer sent - check for TX buffer errors.
1691 */
1692 static int
1693 de4x5_tx(struct net_device *dev)
1694 {
1695 struct de4x5_private *lp = netdev_priv(dev);
1696 u_long iobase = dev->base_addr;
1697 int entry;
1698 s32 status;
1699
1700 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1701 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1702 if (status < 0) { /* Buffer not sent yet */
1703 break;
1704 } else if (status != 0x7fffffff) { /* Not setup frame */
1705 if (status & TD_ES) { /* An error happened */
1706 lp->stats.tx_errors++;
1707 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1708 if (status & TD_LC) lp->stats.tx_window_errors++;
1709 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1710 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1711 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1712
1713 if (TX_PKT_PENDING) {
1714 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1715 }
1716 } else { /* Packet sent */
1717 lp->stats.tx_packets++;
1718 if (lp->tx_enable) lp->linkOK++;
1719 }
1720 /* Update the collision counter */
1721 lp->stats.collisions += ((status & TD_EC) ? 16 :
1722 ((status & TD_CC) >> 3));
1723
1724 /* Free the buffer. */
1725 if (lp->tx_skb[entry] != NULL)
1726 de4x5_free_tx_buff(lp, entry);
1727 }
1728
1729 /* Update all the pointers */
1730 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1731 }
1732
1733 /* Any resources available? */
1734 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1735 if (lp->interrupt)
1736 netif_wake_queue(dev);
1737 else
1738 netif_start_queue(dev);
1739 }
1740
1741 return 0;
1742 }
1743
1744 static int
1745 de4x5_ast(struct net_device *dev)
1746 {
1747 struct de4x5_private *lp = netdev_priv(dev);
1748 int next_tick = DE4X5_AUTOSENSE_MS;
1749
1750 disable_ast(dev);
1751
1752 if (lp->useSROM) {
1753 next_tick = srom_autoconf(dev);
1754 } else if (lp->chipset == DC21140) {
1755 next_tick = dc21140m_autoconf(dev);
1756 } else if (lp->chipset == DC21041) {
1757 next_tick = dc21041_autoconf(dev);
1758 } else if (lp->chipset == DC21040) {
1759 next_tick = dc21040_autoconf(dev);
1760 }
1761 lp->linkOK = 0;
1762 enable_ast(dev, next_tick);
1763
1764 return 0;
1765 }
1766
1767 static int
1768 de4x5_txur(struct net_device *dev)
1769 {
1770 struct de4x5_private *lp = netdev_priv(dev);
1771 u_long iobase = dev->base_addr;
1772 int omr;
1773
1774 omr = inl(DE4X5_OMR);
1775 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1776 omr &= ~(OMR_ST|OMR_SR);
1777 outl(omr, DE4X5_OMR);
1778 while (inl(DE4X5_STS) & STS_TS);
1779 if ((omr & OMR_TR) < OMR_TR) {
1780 omr += 0x4000;
1781 } else {
1782 omr |= OMR_SF;
1783 }
1784 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1785 }
1786
1787 return 0;
1788 }
1789
1790 static int
1791 de4x5_rx_ovfc(struct net_device *dev)
1792 {
1793 struct de4x5_private *lp = netdev_priv(dev);
1794 u_long iobase = dev->base_addr;
1795 int omr;
1796
1797 omr = inl(DE4X5_OMR);
1798 outl(omr & ~OMR_SR, DE4X5_OMR);
1799 while (inl(DE4X5_STS) & STS_RS);
1800
1801 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1802 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1803 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1804 }
1805
1806 outl(omr, DE4X5_OMR);
1807
1808 return 0;
1809 }
1810
1811 static int
1812 de4x5_close(struct net_device *dev)
1813 {
1814 struct de4x5_private *lp = netdev_priv(dev);
1815 u_long iobase = dev->base_addr;
1816 s32 imr, omr;
1817
1818 disable_ast(dev);
1819
1820 netif_stop_queue(dev);
1821
1822 if (de4x5_debug & DEBUG_CLOSE) {
1823 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1824 dev->name, inl(DE4X5_STS));
1825 }
1826
1827 /*
1828 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1829 */
1830 DISABLE_IRQs;
1831 STOP_DE4X5;
1832
1833 /* Free the associated irq */
1834 free_irq(dev->irq, dev);
1835 lp->state = CLOSED;
1836
1837 /* Free any socket buffers */
1838 de4x5_free_rx_buffs(dev);
1839 de4x5_free_tx_buffs(dev);
1840
1841 /* Put the adapter to sleep to save power */
1842 yawn(dev, SLEEP);
1843
1844 return 0;
1845 }
1846
1847 static struct net_device_stats *
1848 de4x5_get_stats(struct net_device *dev)
1849 {
1850 struct de4x5_private *lp = netdev_priv(dev);
1851 u_long iobase = dev->base_addr;
1852
1853 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1854
1855 return &lp->stats;
1856 }
1857
1858 static void
1859 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1860 {
1861 struct de4x5_private *lp = netdev_priv(dev);
1862 int i;
1863
1864 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1865 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1866 lp->pktStats.bins[i]++;
1867 i = DE4X5_PKT_STAT_SZ;
1868 }
1869 }
1870 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1871 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1872 lp->pktStats.broadcast++;
1873 } else {
1874 lp->pktStats.multicast++;
1875 }
1876 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1877 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1878 lp->pktStats.unicast++;
1879 }
1880
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1884 }
1885
1886 return;
1887 }
1888
1889 /*
1890 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1891 ** If the flag is changed on a descriptor that is being read by the hardware,
1892 ** I assume PCI transaction ordering will mean you are either successful or
1893 ** just miss asserting the change to the hardware. Anyway you're messing with
1894 ** a descriptor you don't own, but this shouldn't kill the chip provided
1895 ** the descriptor register is read only to the hardware.
1896 */
1897 static void
1898 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1899 {
1900 struct de4x5_private *lp = netdev_priv(dev);
1901 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1902 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1903
1904 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1905 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1906 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1907 lp->tx_skb[lp->tx_new] = skb;
1908 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1909 barrier();
1910
1911 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1912 barrier();
1913 }
1914
1915 /*
1916 ** Set or clear the multicast filter for this adaptor.
1917 */
1918 static void
1919 set_multicast_list(struct net_device *dev)
1920 {
1921 struct de4x5_private *lp = netdev_priv(dev);
1922 u_long iobase = dev->base_addr;
1923
1924 /* First, double check that the adapter is open */
1925 if (lp->state == OPEN) {
1926 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1927 u32 omr;
1928 omr = inl(DE4X5_OMR);
1929 omr |= OMR_PR;
1930 outl(omr, DE4X5_OMR);
1931 } else {
1932 SetMulticastFilter(dev);
1933 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1934 SETUP_FRAME_LEN, (struct sk_buff *)1);
1935
1936 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1937 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1938 dev->trans_start = jiffies;
1939 }
1940 }
1941 }
1942
1943 /*
1944 ** Calculate the hash code and update the logical address filter
1945 ** from a list of ethernet multicast addresses.
1946 ** Little endian crc one liner from Matt Thomas, DEC.
1947 */
1948 static void
1949 SetMulticastFilter(struct net_device *dev)
1950 {
1951 struct de4x5_private *lp = netdev_priv(dev);
1952 struct dev_mc_list *dmi=dev->mc_list;
1953 u_long iobase = dev->base_addr;
1954 int i, j, bit, byte;
1955 u16 hashcode;
1956 u32 omr, crc;
1957 char *pa;
1958 unsigned char *addrs;
1959
1960 omr = inl(DE4X5_OMR);
1961 omr &= ~(OMR_PR | OMR_PM);
1962 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1963
1964 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1965 omr |= OMR_PM; /* Pass all multicasts */
1966 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1967 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1968 addrs=dmi->dmi_addr;
1969 dmi=dmi->next;
1970 if ((*addrs & 0x01) == 1) { /* multicast address? */
1971 crc = ether_crc_le(ETH_ALEN, addrs);
1972 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1973
1974 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1975 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1976
1977 byte <<= 1; /* calc offset into setup frame */
1978 if (byte & 0x02) {
1979 byte -= 1;
1980 }
1981 lp->setup_frame[byte] |= bit;
1982 }
1983 }
1984 } else { /* Perfect filtering */
1985 for (j=0; j<dev->mc_count; j++) {
1986 addrs=dmi->dmi_addr;
1987 dmi=dmi->next;
1988 for (i=0; i<ETH_ALEN; i++) {
1989 *(pa + (i&1)) = *addrs++;
1990 if (i & 0x01) pa += 4;
1991 }
1992 }
1993 }
1994 outl(omr, DE4X5_OMR);
1995
1996 return;
1997 }
1998
1999 #ifdef CONFIG_EISA
2000
2001 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2002
2003 static int __init de4x5_eisa_probe (struct device *gendev)
2004 {
2005 struct eisa_device *edev;
2006 u_long iobase;
2007 u_char irq, regval;
2008 u_short vendor;
2009 u32 cfid;
2010 int status, device;
2011 struct net_device *dev;
2012 struct de4x5_private *lp;
2013
2014 edev = to_eisa_device (gendev);
2015 iobase = edev->base_addr;
2016
2017 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2018 return -EBUSY;
2019
2020 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2021 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2022 status = -EBUSY;
2023 goto release_reg_1;
2024 }
2025
2026 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2027 status = -ENOMEM;
2028 goto release_reg_2;
2029 }
2030 lp = netdev_priv(dev);
2031
2032 cfid = (u32) inl(PCI_CFID);
2033 lp->cfrv = (u_short) inl(PCI_CFRV);
2034 device = (cfid >> 8) & 0x00ffff00;
2035 vendor = (u_short) cfid;
2036
2037 /* Read the EISA Configuration Registers */
2038 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2039 #ifdef CONFIG_ALPHA
2040 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2041 * care about the EISA configuration, and thus doesn't
2042 * configure the PLX bridge properly. Oh well... Simply mimic
2043 * the EISA config file to sort it out. */
2044
2045 /* EISA REG1: Assert DecChip 21040 HW Reset */
2046 outb (ER1_IAM | 1, EISA_REG1);
2047 mdelay (1);
2048
2049 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2050 outb (ER1_IAM, EISA_REG1);
2051 mdelay (1);
2052
2053 /* EISA REG3: R/W Burst Transfer Enable */
2054 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2055
2056 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2057 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2058 #endif
2059 irq = de4x5_irq[(regval >> 1) & 0x03];
2060
2061 if (is_DC2114x) {
2062 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2063 }
2064 lp->chipset = device;
2065 lp->bus = EISA;
2066
2067 /* Write the PCI Configuration Registers */
2068 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2069 outl(0x00006000, PCI_CFLT);
2070 outl(iobase, PCI_CBIO);
2071
2072 DevicePresent(dev, EISA_APROM);
2073
2074 dev->irq = irq;
2075
2076 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2077 return 0;
2078 }
2079
2080 free_netdev (dev);
2081 release_reg_2:
2082 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2083 release_reg_1:
2084 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2085
2086 return status;
2087 }
2088
2089 static int __devexit de4x5_eisa_remove (struct device *device)
2090 {
2091 struct net_device *dev;
2092 u_long iobase;
2093
2094 dev = device->driver_data;
2095 iobase = dev->base_addr;
2096
2097 unregister_netdev (dev);
2098 free_netdev (dev);
2099 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2100 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2101
2102 return 0;
2103 }
2104
2105 static struct eisa_device_id de4x5_eisa_ids[] = {
2106 { "DEC4250", 0 }, /* 0 is the board name index... */
2107 { "" }
2108 };
2109 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2110
2111 static struct eisa_driver de4x5_eisa_driver = {
2112 .id_table = de4x5_eisa_ids,
2113 .driver = {
2114 .name = "de4x5",
2115 .probe = de4x5_eisa_probe,
2116 .remove = __devexit_p (de4x5_eisa_remove),
2117 }
2118 };
2119 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2120 #endif
2121
2122 #ifdef CONFIG_PCI
2123
2124 /*
2125 ** This function searches the current bus (which is >0) for a DECchip with an
2126 ** SROM, so that in multiport cards that have one SROM shared between multiple
2127 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2128 ** For single port cards this is a time waster...
2129 */
2130 static void __devinit
2131 srom_search(struct net_device *dev, struct pci_dev *pdev)
2132 {
2133 u_char pb;
2134 u_short vendor, status;
2135 u_int irq = 0, device;
2136 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2137 int i, j;
2138 struct de4x5_private *lp = netdev_priv(dev);
2139 struct list_head *walk;
2140
2141 list_for_each(walk, &pdev->bus_list) {
2142 struct pci_dev *this_dev = pci_dev_b(walk);
2143
2144 /* Skip the pci_bus list entry */
2145 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2146
2147 vendor = this_dev->vendor;
2148 device = this_dev->device << 8;
2149 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2150
2151 /* Get the chip configuration revision register */
2152 pb = this_dev->bus->number;
2153
2154 /* Set the device number information */
2155 lp->device = PCI_SLOT(this_dev->devfn);
2156 lp->bus_num = pb;
2157
2158 /* Set the chipset information */
2159 if (is_DC2114x) {
2160 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2161 ? DC21142 : DC21143);
2162 }
2163 lp->chipset = device;
2164
2165 /* Get the board I/O address (64 bits on sparc64) */
2166 iobase = pci_resource_start(this_dev, 0);
2167
2168 /* Fetch the IRQ to be used */
2169 irq = this_dev->irq;
2170 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2171
2172 /* Check if I/O accesses are enabled */
2173 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2174 if (!(status & PCI_COMMAND_IO)) continue;
2175
2176 /* Search for a valid SROM attached to this DECchip */
2177 DevicePresent(dev, DE4X5_APROM);
2178 for (j=0, i=0; i<ETH_ALEN; i++) {
2179 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2180 }
2181 if ((j != 0) && (j != 0x5fa)) {
2182 last.chipset = device;
2183 last.bus = pb;
2184 last.irq = irq;
2185 for (i=0; i<ETH_ALEN; i++) {
2186 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2187 }
2188 return;
2189 }
2190 }
2191
2192 return;
2193 }
2194
2195 /*
2196 ** PCI bus I/O device probe
2197 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2198 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2199 ** enabled by the user first in the set up utility. Hence we just check for
2200 ** enabled features and silently ignore the card if they're not.
2201 **
2202 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2203 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2204 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2205 ** PC doesn't conform to the PCI standard)!
2206 **
2207 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2208 ** kernels use the V0.535[n] drivers.
2209 */
2210
2211 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2212 const struct pci_device_id *ent)
2213 {
2214 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2215 u_short vendor, status;
2216 u_int irq = 0, device;
2217 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2218 int error;
2219 struct net_device *dev;
2220 struct de4x5_private *lp;
2221
2222 dev_num = PCI_SLOT(pdev->devfn);
2223 pb = pdev->bus->number;
2224
2225 if (io) { /* probe a single PCI device */
2226 pbus = (u_short)(io >> 8);
2227 dnum = (u_short)(io & 0xff);
2228 if ((pbus != pb) || (dnum != dev_num))
2229 return -ENODEV;
2230 }
2231
2232 vendor = pdev->vendor;
2233 device = pdev->device << 8;
2234 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2235 return -ENODEV;
2236
2237 /* Ok, the device seems to be for us. */
2238 if ((error = pci_enable_device (pdev)))
2239 return error;
2240
2241 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2242 error = -ENOMEM;
2243 goto disable_dev;
2244 }
2245
2246 lp = netdev_priv(dev);
2247 lp->bus = PCI;
2248 lp->bus_num = 0;
2249
2250 /* Search for an SROM on this bus */
2251 if (lp->bus_num != pb) {
2252 lp->bus_num = pb;
2253 srom_search(dev, pdev);
2254 }
2255
2256 /* Get the chip configuration revision register */
2257 lp->cfrv = pdev->revision;
2258
2259 /* Set the device number information */
2260 lp->device = dev_num;
2261 lp->bus_num = pb;
2262
2263 /* Set the chipset information */
2264 if (is_DC2114x) {
2265 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2266 }
2267 lp->chipset = device;
2268
2269 /* Get the board I/O address (64 bits on sparc64) */
2270 iobase = pci_resource_start(pdev, 0);
2271
2272 /* Fetch the IRQ to be used */
2273 irq = pdev->irq;
2274 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2275 error = -ENODEV;
2276 goto free_dev;
2277 }
2278
2279 /* Check if I/O accesses and Bus Mastering are enabled */
2280 pci_read_config_word(pdev, PCI_COMMAND, &status);
2281 #ifdef __powerpc__
2282 if (!(status & PCI_COMMAND_IO)) {
2283 status |= PCI_COMMAND_IO;
2284 pci_write_config_word(pdev, PCI_COMMAND, status);
2285 pci_read_config_word(pdev, PCI_COMMAND, &status);
2286 }
2287 #endif /* __powerpc__ */
2288 if (!(status & PCI_COMMAND_IO)) {
2289 error = -ENODEV;
2290 goto free_dev;
2291 }
2292
2293 if (!(status & PCI_COMMAND_MASTER)) {
2294 status |= PCI_COMMAND_MASTER;
2295 pci_write_config_word(pdev, PCI_COMMAND, status);
2296 pci_read_config_word(pdev, PCI_COMMAND, &status);
2297 }
2298 if (!(status & PCI_COMMAND_MASTER)) {
2299 error = -ENODEV;
2300 goto free_dev;
2301 }
2302
2303 /* Check the latency timer for values >= 0x60 */
2304 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2305 if (timer < 0x60) {
2306 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2307 }
2308
2309 DevicePresent(dev, DE4X5_APROM);
2310
2311 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2312 error = -EBUSY;
2313 goto free_dev;
2314 }
2315
2316 dev->irq = irq;
2317
2318 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2319 goto release;
2320 }
2321
2322 return 0;
2323
2324 release:
2325 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2326 free_dev:
2327 free_netdev (dev);
2328 disable_dev:
2329 pci_disable_device (pdev);
2330 return error;
2331 }
2332
2333 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2334 {
2335 struct net_device *dev;
2336 u_long iobase;
2337
2338 dev = pdev->dev.driver_data;
2339 iobase = dev->base_addr;
2340
2341 unregister_netdev (dev);
2342 free_netdev (dev);
2343 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2344 pci_disable_device (pdev);
2345 }
2346
2347 static struct pci_device_id de4x5_pci_tbl[] = {
2348 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2350 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2352 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2354 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2356 { },
2357 };
2358
2359 static struct pci_driver de4x5_pci_driver = {
2360 .name = "de4x5",
2361 .id_table = de4x5_pci_tbl,
2362 .probe = de4x5_pci_probe,
2363 .remove = __devexit_p (de4x5_pci_remove),
2364 };
2365
2366 #endif
2367
2368 /*
2369 ** Auto configure the media here rather than setting the port at compile
2370 ** time. This routine is called by de4x5_init() and when a loss of media is
2371 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2372 ** [TP] or no recent receive activity) to check whether the user has been
2373 ** sneaky and changed the port on us.
2374 */
2375 static int
2376 autoconf_media(struct net_device *dev)
2377 {
2378 struct de4x5_private *lp = netdev_priv(dev);
2379 u_long iobase = dev->base_addr;
2380 int next_tick = DE4X5_AUTOSENSE_MS;
2381
2382 lp->linkOK = 0;
2383 lp->c_media = AUTO; /* Bogus last media */
2384 disable_ast(dev);
2385 inl(DE4X5_MFC); /* Zero the lost frames counter */
2386 lp->media = INIT;
2387 lp->tcount = 0;
2388
2389 if (lp->useSROM) {
2390 next_tick = srom_autoconf(dev);
2391 } else if (lp->chipset == DC21040) {
2392 next_tick = dc21040_autoconf(dev);
2393 } else if (lp->chipset == DC21041) {
2394 next_tick = dc21041_autoconf(dev);
2395 } else if (lp->chipset == DC21140) {
2396 next_tick = dc21140m_autoconf(dev);
2397 }
2398
2399 enable_ast(dev, next_tick);
2400
2401 return (lp->media);
2402 }
2403
2404 /*
2405 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2406 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2407 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2408 ** The only way to test for that is to place a loopback packet onto the
2409 ** network and watch for errors. Since we're messing with the interrupt mask
2410 ** register, disable the board interrupts and do not allow any more packets to
2411 ** be queued to the hardware. Re-enable everything only when the media is
2412 ** found.
2413 ** I may have to "age out" locally queued packets so that the higher layer
2414 ** timeouts don't effectively duplicate packets on the network.
2415 */
2416 static int
2417 dc21040_autoconf(struct net_device *dev)
2418 {
2419 struct de4x5_private *lp = netdev_priv(dev);
2420 u_long iobase = dev->base_addr;
2421 int next_tick = DE4X5_AUTOSENSE_MS;
2422 s32 imr;
2423
2424 switch (lp->media) {
2425 case INIT:
2426 DISABLE_IRQs;
2427 lp->tx_enable = false;
2428 lp->timeout = -1;
2429 de4x5_save_skbs(dev);
2430 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2431 lp->media = TP;
2432 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2433 lp->media = BNC_AUI;
2434 } else if (lp->autosense == EXT_SIA) {
2435 lp->media = EXT_SIA;
2436 } else {
2437 lp->media = NC;
2438 }
2439 lp->local_state = 0;
2440 next_tick = dc21040_autoconf(dev);
2441 break;
2442
2443 case TP:
2444 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2445 TP_SUSPECT, test_tp);
2446 break;
2447
2448 case TP_SUSPECT:
2449 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2450 break;
2451
2452 case BNC:
2453 case AUI:
2454 case BNC_AUI:
2455 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2456 BNC_AUI_SUSPECT, ping_media);
2457 break;
2458
2459 case BNC_AUI_SUSPECT:
2460 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2461 break;
2462
2463 case EXT_SIA:
2464 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2465 NC, EXT_SIA_SUSPECT, ping_media);
2466 break;
2467
2468 case EXT_SIA_SUSPECT:
2469 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2470 break;
2471
2472 case NC:
2473 /* default to TP for all */
2474 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2475 if (lp->media != lp->c_media) {
2476 de4x5_dbg_media(dev);
2477 lp->c_media = lp->media;
2478 }
2479 lp->media = INIT;
2480 lp->tx_enable = false;
2481 break;
2482 }
2483
2484 return next_tick;
2485 }
2486
2487 static int
2488 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2489 int next_state, int suspect_state,
2490 int (*fn)(struct net_device *, int))
2491 {
2492 struct de4x5_private *lp = netdev_priv(dev);
2493 int next_tick = DE4X5_AUTOSENSE_MS;
2494 int linkBad;
2495
2496 switch (lp->local_state) {
2497 case 0:
2498 reset_init_sia(dev, csr13, csr14, csr15);
2499 lp->local_state++;
2500 next_tick = 500;
2501 break;
2502
2503 case 1:
2504 if (!lp->tx_enable) {
2505 linkBad = fn(dev, timeout);
2506 if (linkBad < 0) {
2507 next_tick = linkBad & ~TIMER_CB;
2508 } else {
2509 if (linkBad && (lp->autosense == AUTO)) {
2510 lp->local_state = 0;
2511 lp->media = next_state;
2512 } else {
2513 de4x5_init_connection(dev);
2514 }
2515 }
2516 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2517 lp->media = suspect_state;
2518 next_tick = 3000;
2519 }
2520 break;
2521 }
2522
2523 return next_tick;
2524 }
2525
2526 static int
2527 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2528 int (*fn)(struct net_device *, int),
2529 int (*asfn)(struct net_device *))
2530 {
2531 struct de4x5_private *lp = netdev_priv(dev);
2532 int next_tick = DE4X5_AUTOSENSE_MS;
2533 int linkBad;
2534
2535 switch (lp->local_state) {
2536 case 1:
2537 if (lp->linkOK) {
2538 lp->media = prev_state;
2539 } else {
2540 lp->local_state++;
2541 next_tick = asfn(dev);
2542 }
2543 break;
2544
2545 case 2:
2546 linkBad = fn(dev, timeout);
2547 if (linkBad < 0) {
2548 next_tick = linkBad & ~TIMER_CB;
2549 } else if (!linkBad) {
2550 lp->local_state--;
2551 lp->media = prev_state;
2552 } else {
2553 lp->media = INIT;
2554 lp->tcount++;
2555 }
2556 }
2557
2558 return next_tick;
2559 }
2560
2561 /*
2562 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2563 ** before BNC, because the BNC port will indicate activity if it's not
2564 ** terminated correctly. The only way to test for that is to place a loopback
2565 ** packet onto the network and watch for errors. Since we're messing with
2566 ** the interrupt mask register, disable the board interrupts and do not allow
2567 ** any more packets to be queued to the hardware. Re-enable everything only
2568 ** when the media is found.
2569 */
2570 static int
2571 dc21041_autoconf(struct net_device *dev)
2572 {
2573 struct de4x5_private *lp = netdev_priv(dev);
2574 u_long iobase = dev->base_addr;
2575 s32 sts, irqs, irq_mask, imr, omr;
2576 int next_tick = DE4X5_AUTOSENSE_MS;
2577
2578 switch (lp->media) {
2579 case INIT:
2580 DISABLE_IRQs;
2581 lp->tx_enable = false;
2582 lp->timeout = -1;
2583 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2584 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2585 lp->media = TP; /* On chip auto negotiation is broken */
2586 } else if (lp->autosense == TP) {
2587 lp->media = TP;
2588 } else if (lp->autosense == BNC) {
2589 lp->media = BNC;
2590 } else if (lp->autosense == AUI) {
2591 lp->media = AUI;
2592 } else {
2593 lp->media = NC;
2594 }
2595 lp->local_state = 0;
2596 next_tick = dc21041_autoconf(dev);
2597 break;
2598
2599 case TP_NW:
2600 if (lp->timeout < 0) {
2601 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2602 outl(omr | OMR_FDX, DE4X5_OMR);
2603 }
2604 irqs = STS_LNF | STS_LNP;
2605 irq_mask = IMR_LFM | IMR_LPM;
2606 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2607 if (sts < 0) {
2608 next_tick = sts & ~TIMER_CB;
2609 } else {
2610 if (sts & STS_LNP) {
2611 lp->media = ANS;
2612 } else {
2613 lp->media = AUI;
2614 }
2615 next_tick = dc21041_autoconf(dev);
2616 }
2617 break;
2618
2619 case ANS:
2620 if (!lp->tx_enable) {
2621 irqs = STS_LNP;
2622 irq_mask = IMR_LPM;
2623 sts = test_ans(dev, irqs, irq_mask, 3000);
2624 if (sts < 0) {
2625 next_tick = sts & ~TIMER_CB;
2626 } else {
2627 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2628 lp->media = TP;
2629 next_tick = dc21041_autoconf(dev);
2630 } else {
2631 lp->local_state = 1;
2632 de4x5_init_connection(dev);
2633 }
2634 }
2635 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2636 lp->media = ANS_SUSPECT;
2637 next_tick = 3000;
2638 }
2639 break;
2640
2641 case ANS_SUSPECT:
2642 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2643 break;
2644
2645 case TP:
2646 if (!lp->tx_enable) {
2647 if (lp->timeout < 0) {
2648 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2649 outl(omr & ~OMR_FDX, DE4X5_OMR);
2650 }
2651 irqs = STS_LNF | STS_LNP;
2652 irq_mask = IMR_LFM | IMR_LPM;
2653 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2654 if (sts < 0) {
2655 next_tick = sts & ~TIMER_CB;
2656 } else {
2657 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2658 if (inl(DE4X5_SISR) & SISR_NRA) {
2659 lp->media = AUI; /* Non selected port activity */
2660 } else {
2661 lp->media = BNC;
2662 }
2663 next_tick = dc21041_autoconf(dev);
2664 } else {
2665 lp->local_state = 1;
2666 de4x5_init_connection(dev);
2667 }
2668 }
2669 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2670 lp->media = TP_SUSPECT;
2671 next_tick = 3000;
2672 }
2673 break;
2674
2675 case TP_SUSPECT:
2676 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2677 break;
2678
2679 case AUI:
2680 if (!lp->tx_enable) {
2681 if (lp->timeout < 0) {
2682 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2683 outl(omr & ~OMR_FDX, DE4X5_OMR);
2684 }
2685 irqs = 0;
2686 irq_mask = 0;
2687 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2688 if (sts < 0) {
2689 next_tick = sts & ~TIMER_CB;
2690 } else {
2691 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2692 lp->media = BNC;
2693 next_tick = dc21041_autoconf(dev);
2694 } else {
2695 lp->local_state = 1;
2696 de4x5_init_connection(dev);
2697 }
2698 }
2699 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2700 lp->media = AUI_SUSPECT;
2701 next_tick = 3000;
2702 }
2703 break;
2704
2705 case AUI_SUSPECT:
2706 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2707 break;
2708
2709 case BNC:
2710 switch (lp->local_state) {
2711 case 0:
2712 if (lp->timeout < 0) {
2713 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2714 outl(omr & ~OMR_FDX, DE4X5_OMR);
2715 }
2716 irqs = 0;
2717 irq_mask = 0;
2718 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2719 if (sts < 0) {
2720 next_tick = sts & ~TIMER_CB;
2721 } else {
2722 lp->local_state++; /* Ensure media connected */
2723 next_tick = dc21041_autoconf(dev);
2724 }
2725 break;
2726
2727 case 1:
2728 if (!lp->tx_enable) {
2729 if ((sts = ping_media(dev, 3000)) < 0) {
2730 next_tick = sts & ~TIMER_CB;
2731 } else {
2732 if (sts) {
2733 lp->local_state = 0;
2734 lp->media = NC;
2735 } else {
2736 de4x5_init_connection(dev);
2737 }
2738 }
2739 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2740 lp->media = BNC_SUSPECT;
2741 next_tick = 3000;
2742 }
2743 break;
2744 }
2745 break;
2746
2747 case BNC_SUSPECT:
2748 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2749 break;
2750
2751 case NC:
2752 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2753 outl(omr | OMR_FDX, DE4X5_OMR);
2754 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2755 if (lp->media != lp->c_media) {
2756 de4x5_dbg_media(dev);
2757 lp->c_media = lp->media;
2758 }
2759 lp->media = INIT;
2760 lp->tx_enable = false;
2761 break;
2762 }
2763
2764 return next_tick;
2765 }
2766
2767 /*
2768 ** Some autonegotiation chips are broken in that they do not return the
2769 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2770 ** register, except at the first power up negotiation.
2771 */
2772 static int
2773 dc21140m_autoconf(struct net_device *dev)
2774 {
2775 struct de4x5_private *lp = netdev_priv(dev);
2776 int ana, anlpa, cap, cr, slnk, sr;
2777 int next_tick = DE4X5_AUTOSENSE_MS;
2778 u_long imr, omr, iobase = dev->base_addr;
2779
2780 switch(lp->media) {
2781 case INIT:
2782 if (lp->timeout < 0) {
2783 DISABLE_IRQs;
2784 lp->tx_enable = false;
2785 lp->linkOK = 0;
2786 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2787 }
2788 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2789 next_tick &= ~TIMER_CB;
2790 } else {
2791 if (lp->useSROM) {
2792 if (srom_map_media(dev) < 0) {
2793 lp->tcount++;
2794 return next_tick;
2795 }
2796 srom_exec(dev, lp->phy[lp->active].gep);
2797 if (lp->infoblock_media == ANS) {
2798 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2799 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2800 }
2801 } else {
2802 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2803 SET_10Mb;
2804 if (lp->autosense == _100Mb) {
2805 lp->media = _100Mb;
2806 } else if (lp->autosense == _10Mb) {
2807 lp->media = _10Mb;
2808 } else if ((lp->autosense == AUTO) &&
2809 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2810 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2811 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2812 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2813 lp->media = ANS;
2814 } else if (lp->autosense == AUTO) {
2815 lp->media = SPD_DET;
2816 } else if (is_spd_100(dev) && is_100_up(dev)) {
2817 lp->media = _100Mb;
2818 } else {
2819 lp->media = NC;
2820 }
2821 }
2822 lp->local_state = 0;
2823 next_tick = dc21140m_autoconf(dev);
2824 }
2825 break;
2826
2827 case ANS:
2828 switch (lp->local_state) {
2829 case 0:
2830 if (lp->timeout < 0) {
2831 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2832 }
2833 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2834 if (cr < 0) {
2835 next_tick = cr & ~TIMER_CB;
2836 } else {
2837 if (cr) {
2838 lp->local_state = 0;
2839 lp->media = SPD_DET;
2840 } else {
2841 lp->local_state++;
2842 }
2843 next_tick = dc21140m_autoconf(dev);
2844 }
2845 break;
2846
2847 case 1:
2848 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2849 next_tick = sr & ~TIMER_CB;
2850 } else {
2851 lp->media = SPD_DET;
2852 lp->local_state = 0;
2853 if (sr) { /* Success! */
2854 lp->tmp = MII_SR_ASSC;
2855 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2856 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2857 if (!(anlpa & MII_ANLPA_RF) &&
2858 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2859 if (cap & MII_ANA_100M) {
2860 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2861 lp->media = _100Mb;
2862 } else if (cap & MII_ANA_10M) {
2863 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2864
2865 lp->media = _10Mb;
2866 }
2867 }
2868 } /* Auto Negotiation failed to finish */
2869 next_tick = dc21140m_autoconf(dev);
2870 } /* Auto Negotiation failed to start */
2871 break;
2872 }
2873 break;
2874
2875 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2876 if (lp->timeout < 0) {
2877 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2878 (~gep_rd(dev) & GEP_LNP));
2879 SET_100Mb_PDET;
2880 }
2881 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2882 next_tick = slnk & ~TIMER_CB;
2883 } else {
2884 if (is_spd_100(dev) && is_100_up(dev)) {
2885 lp->media = _100Mb;
2886 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2887 lp->media = _10Mb;
2888 } else {
2889 lp->media = NC;
2890 }
2891 next_tick = dc21140m_autoconf(dev);
2892 }
2893 break;
2894
2895 case _100Mb: /* Set 100Mb/s */
2896 next_tick = 3000;
2897 if (!lp->tx_enable) {
2898 SET_100Mb;
2899 de4x5_init_connection(dev);
2900 } else {
2901 if (!lp->linkOK && (lp->autosense == AUTO)) {
2902 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2903 lp->media = INIT;
2904 lp->tcount++;
2905 next_tick = DE4X5_AUTOSENSE_MS;
2906 }
2907 }
2908 }
2909 break;
2910
2911 case BNC:
2912 case AUI:
2913 case _10Mb: /* Set 10Mb/s */
2914 next_tick = 3000;
2915 if (!lp->tx_enable) {
2916 SET_10Mb;
2917 de4x5_init_connection(dev);
2918 } else {
2919 if (!lp->linkOK && (lp->autosense == AUTO)) {
2920 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2921 lp->media = INIT;
2922 lp->tcount++;
2923 next_tick = DE4X5_AUTOSENSE_MS;
2924 }
2925 }
2926 }
2927 break;
2928
2929 case NC:
2930 if (lp->media != lp->c_media) {
2931 de4x5_dbg_media(dev);
2932 lp->c_media = lp->media;
2933 }
2934 lp->media = INIT;
2935 lp->tx_enable = false;
2936 break;
2937 }
2938
2939 return next_tick;
2940 }
2941
2942 /*
2943 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2944 ** changing how I figure out the media - but trying to keep it backwards
2945 ** compatible with the de500-xa and de500-aa.
2946 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2947 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2948 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2949 ** active.
2950 ** When autonegotiation is working, the ANS part searches the SROM for
2951 ** the highest common speed (TP) link that both can run and if that can
2952 ** be full duplex. That infoblock is executed and then the link speed set.
2953 **
2954 ** Only _10Mb and _100Mb are tested here.
2955 */
2956 static int
2957 dc2114x_autoconf(struct net_device *dev)
2958 {
2959 struct de4x5_private *lp = netdev_priv(dev);
2960 u_long iobase = dev->base_addr;
2961 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2962 int next_tick = DE4X5_AUTOSENSE_MS;
2963
2964 switch (lp->media) {
2965 case INIT:
2966 if (lp->timeout < 0) {
2967 DISABLE_IRQs;
2968 lp->tx_enable = false;
2969 lp->linkOK = 0;
2970 lp->timeout = -1;
2971 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2972 if (lp->params.autosense & ~AUTO) {
2973 srom_map_media(dev); /* Fixed media requested */
2974 if (lp->media != lp->params.autosense) {
2975 lp->tcount++;
2976 lp->media = INIT;
2977 return next_tick;
2978 }
2979 lp->media = INIT;
2980 }
2981 }
2982 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2983 next_tick &= ~TIMER_CB;
2984 } else {
2985 if (lp->autosense == _100Mb) {
2986 lp->media = _100Mb;
2987 } else if (lp->autosense == _10Mb) {
2988 lp->media = _10Mb;
2989 } else if (lp->autosense == TP) {
2990 lp->media = TP;
2991 } else if (lp->autosense == BNC) {
2992 lp->media = BNC;
2993 } else if (lp->autosense == AUI) {
2994 lp->media = AUI;
2995 } else {
2996 lp->media = SPD_DET;
2997 if ((lp->infoblock_media == ANS) &&
2998 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2999 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3000 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3001 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3002 lp->media = ANS;
3003 }
3004 }
3005 lp->local_state = 0;
3006 next_tick = dc2114x_autoconf(dev);
3007 }
3008 break;
3009
3010 case ANS:
3011 switch (lp->local_state) {
3012 case 0:
3013 if (lp->timeout < 0) {
3014 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3015 }
3016 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
3017 if (cr < 0) {
3018 next_tick = cr & ~TIMER_CB;
3019 } else {
3020 if (cr) {
3021 lp->local_state = 0;
3022 lp->media = SPD_DET;
3023 } else {
3024 lp->local_state++;
3025 }
3026 next_tick = dc2114x_autoconf(dev);
3027 }
3028 break;
3029
3030 case 1:
3031 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3032 if (sr < 0) {
3033 next_tick = sr & ~TIMER_CB;
3034 } else {
3035 lp->media = SPD_DET;
3036 lp->local_state = 0;
3037 if (sr) { /* Success! */
3038 lp->tmp = MII_SR_ASSC;
3039 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3040 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3041 if (!(anlpa & MII_ANLPA_RF) &&
3042 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3043 if (cap & MII_ANA_100M) {
3044 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3045 lp->media = _100Mb;
3046 } else if (cap & MII_ANA_10M) {
3047 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3048 lp->media = _10Mb;
3049 }
3050 }
3051 } /* Auto Negotiation failed to finish */
3052 next_tick = dc2114x_autoconf(dev);
3053 } /* Auto Negotiation failed to start */
3054 break;
3055 }
3056 break;
3057
3058 case AUI:
3059 if (!lp->tx_enable) {
3060 if (lp->timeout < 0) {
3061 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3062 outl(omr & ~OMR_FDX, DE4X5_OMR);
3063 }
3064 irqs = 0;
3065 irq_mask = 0;
3066 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3067 if (sts < 0) {
3068 next_tick = sts & ~TIMER_CB;
3069 } else {
3070 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3071 lp->media = BNC;
3072 next_tick = dc2114x_autoconf(dev);
3073 } else {
3074 lp->local_state = 1;
3075 de4x5_init_connection(dev);
3076 }
3077 }
3078 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3079 lp->media = AUI_SUSPECT;
3080 next_tick = 3000;
3081 }
3082 break;
3083
3084 case AUI_SUSPECT:
3085 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3086 break;
3087
3088 case BNC:
3089 switch (lp->local_state) {
3090 case 0:
3091 if (lp->timeout < 0) {
3092 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3093 outl(omr & ~OMR_FDX, DE4X5_OMR);
3094 }
3095 irqs = 0;
3096 irq_mask = 0;
3097 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3098 if (sts < 0) {
3099 next_tick = sts & ~TIMER_CB;
3100 } else {
3101 lp->local_state++; /* Ensure media connected */
3102 next_tick = dc2114x_autoconf(dev);
3103 }
3104 break;
3105
3106 case 1:
3107 if (!lp->tx_enable) {
3108 if ((sts = ping_media(dev, 3000)) < 0) {
3109 next_tick = sts & ~TIMER_CB;
3110 } else {
3111 if (sts) {
3112 lp->local_state = 0;
3113 lp->tcount++;
3114 lp->media = INIT;
3115 } else {
3116 de4x5_init_connection(dev);
3117 }
3118 }
3119 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3120 lp->media = BNC_SUSPECT;
3121 next_tick = 3000;
3122 }
3123 break;
3124 }
3125 break;
3126
3127 case BNC_SUSPECT:
3128 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3129 break;
3130
3131 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3132 if (srom_map_media(dev) < 0) {
3133 lp->tcount++;
3134 lp->media = INIT;
3135 return next_tick;
3136 }
3137 if (lp->media == _100Mb) {
3138 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3139 lp->media = SPD_DET;
3140 return (slnk & ~TIMER_CB);
3141 }
3142 } else {
3143 if (wait_for_link(dev) < 0) {
3144 lp->media = SPD_DET;
3145 return PDET_LINK_WAIT;
3146 }
3147 }
3148 if (lp->media == ANS) { /* Do MII parallel detection */
3149 if (is_spd_100(dev)) {
3150 lp->media = _100Mb;
3151 } else {
3152 lp->media = _10Mb;
3153 }
3154 next_tick = dc2114x_autoconf(dev);
3155 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3156 (((lp->media == _10Mb) || (lp->media == TP) ||
3157 (lp->media == BNC) || (lp->media == AUI)) &&
3158 is_10_up(dev))) {
3159 next_tick = dc2114x_autoconf(dev);
3160 } else {
3161 lp->tcount++;
3162 lp->media = INIT;
3163 }
3164 break;
3165
3166 case _10Mb:
3167 next_tick = 3000;
3168 if (!lp->tx_enable) {
3169 SET_10Mb;
3170 de4x5_init_connection(dev);
3171 } else {
3172 if (!lp->linkOK && (lp->autosense == AUTO)) {
3173 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3174 lp->media = INIT;
3175 lp->tcount++;
3176 next_tick = DE4X5_AUTOSENSE_MS;
3177 }
3178 }
3179 }
3180 break;
3181
3182 case _100Mb:
3183 next_tick = 3000;
3184 if (!lp->tx_enable) {
3185 SET_100Mb;
3186 de4x5_init_connection(dev);
3187 } else {
3188 if (!lp->linkOK && (lp->autosense == AUTO)) {
3189 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3190 lp->media = INIT;
3191 lp->tcount++;
3192 next_tick = DE4X5_AUTOSENSE_MS;
3193 }
3194 }
3195 }
3196 break;
3197
3198 default:
3199 lp->tcount++;
3200 printk("Huh?: media:%02x\n", lp->media);
3201 lp->media = INIT;
3202 break;
3203 }
3204
3205 return next_tick;
3206 }
3207
3208 static int
3209 srom_autoconf(struct net_device *dev)
3210 {
3211 struct de4x5_private *lp = netdev_priv(dev);
3212
3213 return lp->infoleaf_fn(dev);
3214 }
3215
3216 /*
3217 ** This mapping keeps the original media codes and FDX flag unchanged.
3218 ** While it isn't strictly necessary, it helps me for the moment...
3219 ** The early return avoids a media state / SROM media space clash.
3220 */
3221 static int
3222 srom_map_media(struct net_device *dev)
3223 {
3224 struct de4x5_private *lp = netdev_priv(dev);
3225
3226 lp->fdx = false;
3227 if (lp->infoblock_media == lp->media)
3228 return 0;
3229
3230 switch(lp->infoblock_media) {
3231 case SROM_10BASETF:
3232 if (!lp->params.fdx) return -1;
3233 lp->fdx = true;
3234 case SROM_10BASET:
3235 if (lp->params.fdx && !lp->fdx) return -1;
3236 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3237 lp->media = _10Mb;
3238 } else {
3239 lp->media = TP;
3240 }
3241 break;
3242
3243 case SROM_10BASE2:
3244 lp->media = BNC;
3245 break;
3246
3247 case SROM_10BASE5:
3248 lp->media = AUI;
3249 break;
3250
3251 case SROM_100BASETF:
3252 if (!lp->params.fdx) return -1;
3253 lp->fdx = true;
3254 case SROM_100BASET:
3255 if (lp->params.fdx && !lp->fdx) return -1;
3256 lp->media = _100Mb;
3257 break;
3258
3259 case SROM_100BASET4:
3260 lp->media = _100Mb;
3261 break;
3262
3263 case SROM_100BASEFF:
3264 if (!lp->params.fdx) return -1;
3265 lp->fdx = true;
3266 case SROM_100BASEF:
3267 if (lp->params.fdx && !lp->fdx) return -1;
3268 lp->media = _100Mb;
3269 break;
3270
3271 case ANS:
3272 lp->media = ANS;
3273 lp->fdx = lp->params.fdx;
3274 break;
3275
3276 default:
3277 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3278 lp->infoblock_media);
3279 return -1;
3280 break;
3281 }
3282
3283 return 0;
3284 }
3285
3286 static void
3287 de4x5_init_connection(struct net_device *dev)
3288 {
3289 struct de4x5_private *lp = netdev_priv(dev);
3290 u_long iobase = dev->base_addr;
3291 u_long flags = 0;
3292
3293 if (lp->media != lp->c_media) {
3294 de4x5_dbg_media(dev);
3295 lp->c_media = lp->media; /* Stop scrolling media messages */
3296 }
3297
3298 spin_lock_irqsave(&lp->lock, flags);
3299 de4x5_rst_desc_ring(dev);
3300 de4x5_setup_intr(dev);
3301 lp->tx_enable = true;
3302 spin_unlock_irqrestore(&lp->lock, flags);
3303 outl(POLL_DEMAND, DE4X5_TPD);
3304
3305 netif_wake_queue(dev);
3306
3307 return;
3308 }
3309
3310 /*
3311 ** General PHY reset function. Some MII devices don't reset correctly
3312 ** since their MII address pins can float at voltages that are dependent
3313 ** on the signal pin use. Do a double reset to ensure a reset.
3314 */
3315 static int
3316 de4x5_reset_phy(struct net_device *dev)
3317 {
3318 struct de4x5_private *lp = netdev_priv(dev);
3319 u_long iobase = dev->base_addr;
3320 int next_tick = 0;
3321
3322 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3323 if (lp->timeout < 0) {
3324 if (lp->useSROM) {
3325 if (lp->phy[lp->active].rst) {
3326 srom_exec(dev, lp->phy[lp->active].rst);
3327 srom_exec(dev, lp->phy[lp->active].rst);
3328 } else if (lp->rst) { /* Type 5 infoblock reset */
3329 srom_exec(dev, lp->rst);
3330 srom_exec(dev, lp->rst);
3331 }
3332 } else {
3333 PHY_HARD_RESET;
3334 }
3335 if (lp->useMII) {
3336 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3337 }
3338 }
3339 if (lp->useMII) {
3340 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3341 }
3342 } else if (lp->chipset == DC21140) {
3343 PHY_HARD_RESET;
3344 }
3345
3346 return next_tick;
3347 }
3348
3349 static int
3350 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3351 {
3352 struct de4x5_private *lp = netdev_priv(dev);
3353 u_long iobase = dev->base_addr;
3354 s32 sts, csr12;
3355
3356 if (lp->timeout < 0) {
3357 lp->timeout = msec/100;
3358 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3359 reset_init_sia(dev, csr13, csr14, csr15);
3360 }
3361
3362 /* set up the interrupt mask */
3363 outl(irq_mask, DE4X5_IMR);
3364
3365 /* clear all pending interrupts */
3366 sts = inl(DE4X5_STS);
3367 outl(sts, DE4X5_STS);
3368
3369 /* clear csr12 NRA and SRA bits */
3370 if ((lp->chipset == DC21041) || lp->useSROM) {
3371 csr12 = inl(DE4X5_SISR);
3372 outl(csr12, DE4X5_SISR);
3373 }
3374 }
3375
3376 sts = inl(DE4X5_STS) & ~TIMER_CB;
3377
3378 if (!(sts & irqs) && --lp->timeout) {
3379 sts = 100 | TIMER_CB;
3380 } else {
3381 lp->timeout = -1;
3382 }
3383
3384 return sts;
3385 }
3386
3387 static int
3388 test_tp(struct net_device *dev, s32 msec)
3389 {
3390 struct de4x5_private *lp = netdev_priv(dev);
3391 u_long iobase = dev->base_addr;
3392 int sisr;
3393
3394 if (lp->timeout < 0) {
3395 lp->timeout = msec/100;
3396 }
3397
3398 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3399
3400 if (sisr && --lp->timeout) {
3401 sisr = 100 | TIMER_CB;
3402 } else {
3403 lp->timeout = -1;
3404 }
3405
3406 return sisr;
3407 }
3408
3409 /*
3410 ** Samples the 100Mb Link State Signal. The sample interval is important
3411 ** because too fast a rate can give erroneous results and confuse the
3412 ** speed sense algorithm.
3413 */
3414 #define SAMPLE_INTERVAL 500 /* ms */
3415 #define SAMPLE_DELAY 2000 /* ms */
3416 static int
3417 test_for_100Mb(struct net_device *dev, int msec)
3418 {
3419 struct de4x5_private *lp = netdev_priv(dev);
3420 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3421
3422 if (lp->timeout < 0) {
3423 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3424 if (msec > SAMPLE_DELAY) {
3425 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3426 gep = SAMPLE_DELAY | TIMER_CB;
3427 return gep;
3428 } else {
3429 lp->timeout = msec/SAMPLE_INTERVAL;
3430 }
3431 }
3432
3433 if (lp->phy[lp->active].id || lp->useSROM) {
3434 gep = is_100_up(dev) | is_spd_100(dev);
3435 } else {
3436 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3437 }
3438 if (!(gep & ret) && --lp->timeout) {
3439 gep = SAMPLE_INTERVAL | TIMER_CB;
3440 } else {
3441 lp->timeout = -1;
3442 }
3443
3444 return gep;
3445 }
3446
3447 static int
3448 wait_for_link(struct net_device *dev)
3449 {
3450 struct de4x5_private *lp = netdev_priv(dev);
3451
3452 if (lp->timeout < 0) {
3453 lp->timeout = 1;
3454 }
3455
3456 if (lp->timeout--) {
3457 return TIMER_CB;
3458 } else {
3459 lp->timeout = -1;
3460 }
3461
3462 return 0;
3463 }
3464
3465 /*
3466 **
3467 **
3468 */
3469 static int
3470 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3471 {
3472 struct de4x5_private *lp = netdev_priv(dev);
3473 int test;
3474 u_long iobase = dev->base_addr;
3475
3476 if (lp->timeout < 0) {
3477 lp->timeout = msec/100;
3478 }
3479
3480 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3481 test = (reg ^ (pol ? ~0 : 0)) & mask;
3482
3483 if (test && --lp->timeout) {
3484 reg = 100 | TIMER_CB;
3485 } else {
3486 lp->timeout = -1;
3487 }
3488
3489 return reg;
3490 }
3491
3492 static int
3493 is_spd_100(struct net_device *dev)
3494 {
3495 struct de4x5_private *lp = netdev_priv(dev);
3496 u_long iobase = dev->base_addr;
3497 int spd;
3498
3499 if (lp->useMII) {
3500 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3501 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3502 spd &= lp->phy[lp->active].spd.mask;
3503 } else if (!lp->useSROM) { /* de500-xa */
3504 spd = ((~gep_rd(dev)) & GEP_SLNK);
3505 } else {
3506 if ((lp->ibn == 2) || !lp->asBitValid)
3507 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3508
3509 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3510 (lp->linkOK & ~lp->asBitValid);
3511 }
3512
3513 return spd;
3514 }
3515
3516 static int
3517 is_100_up(struct net_device *dev)
3518 {
3519 struct de4x5_private *lp = netdev_priv(dev);
3520 u_long iobase = dev->base_addr;
3521
3522 if (lp->useMII) {
3523 /* Double read for sticky bits & temporary drops */
3524 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3525 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3526 } else if (!lp->useSROM) { /* de500-xa */
3527 return ((~gep_rd(dev)) & GEP_SLNK);
3528 } else {
3529 if ((lp->ibn == 2) || !lp->asBitValid)
3530 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3531
3532 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3533 (lp->linkOK & ~lp->asBitValid));
3534 }
3535 }
3536
3537 static int
3538 is_10_up(struct net_device *dev)
3539 {
3540 struct de4x5_private *lp = netdev_priv(dev);
3541 u_long iobase = dev->base_addr;
3542
3543 if (lp->useMII) {
3544 /* Double read for sticky bits & temporary drops */
3545 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3546 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3547 } else if (!lp->useSROM) { /* de500-xa */
3548 return ((~gep_rd(dev)) & GEP_LNP);
3549 } else {
3550 if ((lp->ibn == 2) || !lp->asBitValid)
3551 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3552 (~inl(DE4X5_SISR)&SISR_LS10):
3553 0);
3554
3555 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3556 (lp->linkOK & ~lp->asBitValid));
3557 }
3558 }
3559
3560 static int
3561 is_anc_capable(struct net_device *dev)
3562 {
3563 struct de4x5_private *lp = netdev_priv(dev);
3564 u_long iobase = dev->base_addr;
3565
3566 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3567 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3568 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3569 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3570 } else {
3571 return 0;
3572 }
3573 }
3574
3575 /*
3576 ** Send a packet onto the media and watch for send errors that indicate the
3577 ** media is bad or unconnected.
3578 */
3579 static int
3580 ping_media(struct net_device *dev, int msec)
3581 {
3582 struct de4x5_private *lp = netdev_priv(dev);
3583 u_long iobase = dev->base_addr;
3584 int sisr;
3585
3586 if (lp->timeout < 0) {
3587 lp->timeout = msec/100;
3588
3589 lp->tmp = lp->tx_new; /* Remember the ring position */
3590 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3591 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3592 outl(POLL_DEMAND, DE4X5_TPD);
3593 }
3594
3595 sisr = inl(DE4X5_SISR);
3596
3597 if ((!(sisr & SISR_NCR)) &&
3598 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3599 (--lp->timeout)) {
3600 sisr = 100 | TIMER_CB;
3601 } else {
3602 if ((!(sisr & SISR_NCR)) &&
3603 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3604 lp->timeout) {
3605 sisr = 0;
3606 } else {
3607 sisr = 1;
3608 }
3609 lp->timeout = -1;
3610 }
3611
3612 return sisr;
3613 }
3614
3615 /*
3616 ** This function does 2 things: on Intels it kmalloc's another buffer to
3617 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3618 ** into which the packet is copied.
3619 */
3620 static struct sk_buff *
3621 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3622 {
3623 struct de4x5_private *lp = netdev_priv(dev);
3624 struct sk_buff *p;
3625
3626 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3627 struct sk_buff *ret;
3628 u_long i=0, tmp;
3629
3630 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3631 if (!p) return NULL;
3632
3633 tmp = virt_to_bus(p->data);
3634 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3635 skb_reserve(p, i);
3636 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3637
3638 ret = lp->rx_skb[index];
3639 lp->rx_skb[index] = p;
3640
3641 if ((u_long) ret > 1) {
3642 skb_put(ret, len);
3643 }
3644
3645 return ret;
3646
3647 #else
3648 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3649
3650 p = dev_alloc_skb(len + 2);
3651 if (!p) return NULL;
3652
3653 skb_reserve(p, 2); /* Align */
3654 if (index < lp->rx_old) { /* Wrapped buffer */
3655 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3656 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3657 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3658 } else { /* Linear buffer */
3659 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3660 }
3661
3662 return p;
3663 #endif
3664 }
3665
3666 static void
3667 de4x5_free_rx_buffs(struct net_device *dev)
3668 {
3669 struct de4x5_private *lp = netdev_priv(dev);
3670 int i;
3671
3672 for (i=0; i<lp->rxRingSize; i++) {
3673 if ((u_long) lp->rx_skb[i] > 1) {
3674 dev_kfree_skb(lp->rx_skb[i]);
3675 }
3676 lp->rx_ring[i].status = 0;
3677 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3678 }
3679
3680 return;
3681 }
3682
3683 static void
3684 de4x5_free_tx_buffs(struct net_device *dev)
3685 {
3686 struct de4x5_private *lp = netdev_priv(dev);
3687 int i;
3688
3689 for (i=0; i<lp->txRingSize; i++) {
3690 if (lp->tx_skb[i])
3691 de4x5_free_tx_buff(lp, i);
3692 lp->tx_ring[i].status = 0;
3693 }
3694
3695 /* Unload the locally queued packets */
3696 while (lp->cache.skb) {
3697 dev_kfree_skb(de4x5_get_cache(dev));
3698 }
3699
3700 return;
3701 }
3702
3703 /*
3704 ** When a user pulls a connection, the DECchip can end up in a
3705 ** 'running - waiting for end of transmission' state. This means that we
3706 ** have to perform a chip soft reset to ensure that we can synchronize
3707 ** the hardware and software and make any media probes using a loopback
3708 ** packet meaningful.
3709 */
3710 static void
3711 de4x5_save_skbs(struct net_device *dev)
3712 {
3713 struct de4x5_private *lp = netdev_priv(dev);
3714 u_long iobase = dev->base_addr;
3715 s32 omr;
3716
3717 if (!lp->cache.save_cnt) {
3718 STOP_DE4X5;
3719 de4x5_tx(dev); /* Flush any sent skb's */
3720 de4x5_free_tx_buffs(dev);
3721 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3722 de4x5_sw_reset(dev);
3723 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3724 lp->cache.save_cnt++;
3725 START_DE4X5;
3726 }
3727
3728 return;
3729 }
3730
3731 static void
3732 de4x5_rst_desc_ring(struct net_device *dev)
3733 {
3734 struct de4x5_private *lp = netdev_priv(dev);
3735 u_long iobase = dev->base_addr;
3736 int i;
3737 s32 omr;
3738
3739 if (lp->cache.save_cnt) {
3740 STOP_DE4X5;
3741 outl(lp->dma_rings, DE4X5_RRBA);
3742 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3743 DE4X5_TRBA);
3744
3745 lp->rx_new = lp->rx_old = 0;
3746 lp->tx_new = lp->tx_old = 0;
3747
3748 for (i = 0; i < lp->rxRingSize; i++) {
3749 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3750 }
3751
3752 for (i = 0; i < lp->txRingSize; i++) {
3753 lp->tx_ring[i].status = cpu_to_le32(0);
3754 }
3755
3756 barrier();
3757 lp->cache.save_cnt--;
3758 START_DE4X5;
3759 }
3760
3761 return;
3762 }
3763
3764 static void
3765 de4x5_cache_state(struct net_device *dev, int flag)
3766 {
3767 struct de4x5_private *lp = netdev_priv(dev);
3768 u_long iobase = dev->base_addr;
3769
3770 switch(flag) {
3771 case DE4X5_SAVE_STATE:
3772 lp->cache.csr0 = inl(DE4X5_BMR);
3773 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3774 lp->cache.csr7 = inl(DE4X5_IMR);
3775 break;
3776
3777 case DE4X5_RESTORE_STATE:
3778 outl(lp->cache.csr0, DE4X5_BMR);
3779 outl(lp->cache.csr6, DE4X5_OMR);
3780 outl(lp->cache.csr7, DE4X5_IMR);
3781 if (lp->chipset == DC21140) {
3782 gep_wr(lp->cache.gepc, dev);
3783 gep_wr(lp->cache.gep, dev);
3784 } else {
3785 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3786 lp->cache.csr15);
3787 }
3788 break;
3789 }
3790
3791 return;
3792 }
3793
3794 static void
3795 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3796 {
3797 struct de4x5_private *lp = netdev_priv(dev);
3798 struct sk_buff *p;
3799
3800 if (lp->cache.skb) {
3801 for (p=lp->cache.skb; p->next; p=p->next);
3802 p->next = skb;
3803 } else {
3804 lp->cache.skb = skb;
3805 }
3806 skb->next = NULL;
3807
3808 return;
3809 }
3810
3811 static void
3812 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3813 {
3814 struct de4x5_private *lp = netdev_priv(dev);
3815 struct sk_buff *p = lp->cache.skb;
3816
3817 lp->cache.skb = skb;
3818 skb->next = p;
3819
3820 return;
3821 }
3822
3823 static struct sk_buff *
3824 de4x5_get_cache(struct net_device *dev)
3825 {
3826 struct de4x5_private *lp = netdev_priv(dev);
3827 struct sk_buff *p = lp->cache.skb;
3828
3829 if (p) {
3830 lp->cache.skb = p->next;
3831 p->next = NULL;
3832 }
3833
3834 return p;
3835 }
3836
3837 /*
3838 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3839 ** is received and the auto-negotiation status is NWAY OK.
3840 */
3841 static int
3842 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3843 {
3844 struct de4x5_private *lp = netdev_priv(dev);
3845 u_long iobase = dev->base_addr;
3846 s32 sts, ans;
3847
3848 if (lp->timeout < 0) {
3849 lp->timeout = msec/100;
3850 outl(irq_mask, DE4X5_IMR);
3851
3852 /* clear all pending interrupts */
3853 sts = inl(DE4X5_STS);
3854 outl(sts, DE4X5_STS);
3855 }
3856
3857 ans = inl(DE4X5_SISR) & SISR_ANS;
3858 sts = inl(DE4X5_STS) & ~TIMER_CB;
3859
3860 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3861 sts = 100 | TIMER_CB;
3862 } else {
3863 lp->timeout = -1;
3864 }
3865
3866 return sts;
3867 }
3868
3869 static void
3870 de4x5_setup_intr(struct net_device *dev)
3871 {
3872 struct de4x5_private *lp = netdev_priv(dev);
3873 u_long iobase = dev->base_addr;
3874 s32 imr, sts;
3875
3876 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3877 imr = 0;
3878 UNMASK_IRQs;
3879 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3880 outl(sts, DE4X5_STS);
3881 ENABLE_IRQs;
3882 }
3883
3884 return;
3885 }
3886
3887 /*
3888 **
3889 */
3890 static void
3891 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3892 {
3893 struct de4x5_private *lp = netdev_priv(dev);
3894 u_long iobase = dev->base_addr;
3895
3896 RESET_SIA;
3897 if (lp->useSROM) {
3898 if (lp->ibn == 3) {
3899 srom_exec(dev, lp->phy[lp->active].rst);
3900 srom_exec(dev, lp->phy[lp->active].gep);
3901 outl(1, DE4X5_SICR);
3902 return;
3903 } else {
3904 csr15 = lp->cache.csr15;
3905 csr14 = lp->cache.csr14;
3906 csr13 = lp->cache.csr13;
3907 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3908 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3909 }
3910 } else {
3911 outl(csr15, DE4X5_SIGR);
3912 }
3913 outl(csr14, DE4X5_STRR);
3914 outl(csr13, DE4X5_SICR);
3915
3916 mdelay(10);
3917
3918 return;
3919 }
3920
3921 /*
3922 ** Create a loopback ethernet packet
3923 */
3924 static void
3925 create_packet(struct net_device *dev, char *frame, int len)
3926 {
3927 int i;
3928 char *buf = frame;
3929
3930 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3931 *buf++ = dev->dev_addr[i];
3932 }
3933 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3934 *buf++ = dev->dev_addr[i];
3935 }
3936
3937 *buf++ = 0; /* Packet length (2 bytes) */
3938 *buf++ = 1;
3939
3940 return;
3941 }
3942
3943 /*
3944 ** Look for a particular board name in the EISA configuration space
3945 */
3946 static int
3947 EISA_signature(char *name, struct device *device)
3948 {
3949 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3950 struct eisa_device *edev;
3951
3952 *name = '\0';
3953 edev = to_eisa_device (device);
3954 i = edev->id.driver_data;
3955
3956 if (i >= 0 && i < siglen) {
3957 strcpy (name, de4x5_signatures[i]);
3958 status = 1;
3959 }
3960
3961 return status; /* return the device name string */
3962 }
3963
3964 /*
3965 ** Look for a particular board name in the PCI configuration space
3966 */
3967 static int
3968 PCI_signature(char *name, struct de4x5_private *lp)
3969 {
3970 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3971
3972 if (lp->chipset == DC21040) {
3973 strcpy(name, "DE434/5");
3974 return status;
3975 } else { /* Search for a DEC name in the SROM */
3976 int i = *((char *)&lp->srom + 19) * 3;
3977 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3978 }
3979 name[8] = '\0';
3980 for (i=0; i<siglen; i++) {
3981 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3982 }
3983 if (i == siglen) {
3984 if (dec_only) {
3985 *name = '\0';
3986 } else { /* Use chip name to avoid confusion */
3987 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3988 ((lp->chipset == DC21041) ? "DC21041" :
3989 ((lp->chipset == DC21140) ? "DC21140" :
3990 ((lp->chipset == DC21142) ? "DC21142" :
3991 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3992 )))))));
3993 }
3994 if (lp->chipset != DC21041) {
3995 lp->useSROM = true; /* card is not recognisably DEC */
3996 }
3997 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3998 lp->useSROM = true;
3999 }
4000
4001 return status;
4002 }
4003
4004 /*
4005 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4006 ** the DC21040, else read the SROM for the other chips.
4007 ** The SROM may not be present in a multi-MAC card, so first read the
4008 ** MAC address and check for a bad address. If there is a bad one then exit
4009 ** immediately with the prior srom contents intact (the h/w address will
4010 ** be fixed up later).
4011 */
4012 static void
4013 DevicePresent(struct net_device *dev, u_long aprom_addr)
4014 {
4015 int i, j=0;
4016 struct de4x5_private *lp = netdev_priv(dev);
4017
4018 if (lp->chipset == DC21040) {
4019 if (lp->bus == EISA) {
4020 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4021 } else {
4022 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4023 }
4024 } else { /* Read new srom */
4025 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4026 for (i=0; i<(ETH_ALEN>>1); i++) {
4027 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4028 *p = le16_to_cpu(tmp);
4029 j += *p++;
4030 }
4031 if ((j == 0) || (j == 0x2fffd)) {
4032 return;
4033 }
4034
4035 p=(short *)&lp->srom;
4036 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4037 tmp = srom_rd(aprom_addr, i);
4038 *p++ = le16_to_cpu(tmp);
4039 }
4040 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4041 }
4042
4043 return;
4044 }
4045
4046 /*
4047 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4048 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4049 ** it...from depca.c.
4050 */
4051 static void
4052 enet_addr_rst(u_long aprom_addr)
4053 {
4054 union {
4055 struct {
4056 u32 a;
4057 u32 b;
4058 } llsig;
4059 char Sig[sizeof(u32) << 1];
4060 } dev;
4061 short sigLength=0;
4062 s8 data;
4063 int i, j;
4064
4065 dev.llsig.a = ETH_PROM_SIG;
4066 dev.llsig.b = ETH_PROM_SIG;
4067 sigLength = sizeof(u32) << 1;
4068
4069 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4070 data = inb(aprom_addr);
4071 if (dev.Sig[j] == data) { /* track signature */
4072 j++;
4073 } else { /* lost signature; begin search again */
4074 if (data == dev.Sig[0]) { /* rare case.... */
4075 j=1;
4076 } else {
4077 j=0;
4078 }
4079 }
4080 }
4081
4082 return;
4083 }
4084
4085 /*
4086 ** For the bad status case and no SROM, then add one to the previous
4087 ** address. However, need to add one backwards in case we have 0xff
4088 ** as one or more of the bytes. Only the last 3 bytes should be checked
4089 ** as the first three are invariant - assigned to an organisation.
4090 */
4091 static int
4092 get_hw_addr(struct net_device *dev)
4093 {
4094 u_long iobase = dev->base_addr;
4095 int broken, i, k, tmp, status = 0;
4096 u_short j,chksum;
4097 struct de4x5_private *lp = netdev_priv(dev);
4098
4099 broken = de4x5_bad_srom(lp);
4100
4101 for (i=0,k=0,j=0;j<3;j++) {
4102 k <<= 1;
4103 if (k > 0xffff) k-=0xffff;
4104
4105 if (lp->bus == PCI) {
4106 if (lp->chipset == DC21040) {
4107 while ((tmp = inl(DE4X5_APROM)) < 0);
4108 k += (u_char) tmp;
4109 dev->dev_addr[i++] = (u_char) tmp;
4110 while ((tmp = inl(DE4X5_APROM)) < 0);
4111 k += (u_short) (tmp << 8);
4112 dev->dev_addr[i++] = (u_char) tmp;
4113 } else if (!broken) {
4114 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4115 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4116 } else if ((broken == SMC) || (broken == ACCTON)) {
4117 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4118 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4119 }
4120 } else {
4121 k += (u_char) (tmp = inb(EISA_APROM));
4122 dev->dev_addr[i++] = (u_char) tmp;
4123 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4124 dev->dev_addr[i++] = (u_char) tmp;
4125 }
4126
4127 if (k > 0xffff) k-=0xffff;
4128 }
4129 if (k == 0xffff) k=0;
4130
4131 if (lp->bus == PCI) {
4132 if (lp->chipset == DC21040) {
4133 while ((tmp = inl(DE4X5_APROM)) < 0);
4134 chksum = (u_char) tmp;
4135 while ((tmp = inl(DE4X5_APROM)) < 0);
4136 chksum |= (u_short) (tmp << 8);
4137 if ((k != chksum) && (dec_only)) status = -1;
4138 }
4139 } else {
4140 chksum = (u_char) inb(EISA_APROM);
4141 chksum |= (u_short) (inb(EISA_APROM) << 8);
4142 if ((k != chksum) && (dec_only)) status = -1;
4143 }
4144
4145 /* If possible, try to fix a broken card - SMC only so far */
4146 srom_repair(dev, broken);
4147
4148 #ifdef CONFIG_PPC_PMAC
4149 /*
4150 ** If the address starts with 00 a0, we have to bit-reverse
4151 ** each byte of the address.
4152 */
4153 if ( machine_is(powermac) &&
4154 (dev->dev_addr[0] == 0) &&
4155 (dev->dev_addr[1] == 0xa0) )
4156 {
4157 for (i = 0; i < ETH_ALEN; ++i)
4158 {
4159 int x = dev->dev_addr[i];
4160 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4161 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4162 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4163 }
4164 }
4165 #endif /* CONFIG_PPC_PMAC */
4166
4167 /* Test for a bad enet address */
4168 status = test_bad_enet(dev, status);
4169
4170 return status;
4171 }
4172
4173 /*
4174 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4175 ** didn't seem to work here...?
4176 */
4177 static int
4178 de4x5_bad_srom(struct de4x5_private *lp)
4179 {
4180 int i, status = 0;
4181
4182 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4183 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4184 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4185 if (i == 0) {
4186 status = SMC;
4187 } else if (i == 1) {
4188 status = ACCTON;
4189 }
4190 break;
4191 }
4192 }
4193
4194 return status;
4195 }
4196
4197 static int
4198 de4x5_strncmp(char *a, char *b, int n)
4199 {
4200 int ret=0;
4201
4202 for (;n && !ret;n--) {
4203 ret = *a++ - *b++;
4204 }
4205
4206 return ret;
4207 }
4208
4209 static void
4210 srom_repair(struct net_device *dev, int card)
4211 {
4212 struct de4x5_private *lp = netdev_priv(dev);
4213
4214 switch(card) {
4215 case SMC:
4216 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4217 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4218 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4219 lp->useSROM = true;
4220 break;
4221 }
4222
4223 return;
4224 }
4225
4226 /*
4227 ** Assume that the irq's do not follow the PCI spec - this is seems
4228 ** to be true so far (2 for 2).
4229 */
4230 static int
4231 test_bad_enet(struct net_device *dev, int status)
4232 {
4233 struct de4x5_private *lp = netdev_priv(dev);
4234 int i, tmp;
4235
4236 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4237 if ((tmp == 0) || (tmp == 0x5fa)) {
4238 if ((lp->chipset == last.chipset) &&
4239 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4240 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4241 for (i=ETH_ALEN-1; i>2; --i) {
4242 dev->dev_addr[i] += 1;
4243 if (dev->dev_addr[i] != 0) break;
4244 }
4245 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4246 if (!an_exception(lp)) {
4247 dev->irq = last.irq;
4248 }
4249
4250 status = 0;
4251 }
4252 } else if (!status) {
4253 last.chipset = lp->chipset;
4254 last.bus = lp->bus_num;
4255 last.irq = dev->irq;
4256 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4257 }
4258
4259 return status;
4260 }
4261
4262 /*
4263 ** List of board exceptions with correctly wired IRQs
4264 */
4265 static int
4266 an_exception(struct de4x5_private *lp)
4267 {
4268 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4269 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4270 return -1;
4271 }
4272
4273 return 0;
4274 }
4275
4276 /*
4277 ** SROM Read
4278 */
4279 static short
4280 srom_rd(u_long addr, u_char offset)
4281 {
4282 sendto_srom(SROM_RD | SROM_SR, addr);
4283
4284 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4285 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4286 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4287
4288 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4289 }
4290
4291 static void
4292 srom_latch(u_int command, u_long addr)
4293 {
4294 sendto_srom(command, addr);
4295 sendto_srom(command | DT_CLK, addr);
4296 sendto_srom(command, addr);
4297
4298 return;
4299 }
4300
4301 static void
4302 srom_command(u_int command, u_long addr)
4303 {
4304 srom_latch(command, addr);
4305 srom_latch(command, addr);
4306 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4307
4308 return;
4309 }
4310
4311 static void
4312 srom_address(u_int command, u_long addr, u_char offset)
4313 {
4314 int i, a;
4315
4316 a = offset << 2;
4317 for (i=0; i<6; i++, a <<= 1) {
4318 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4319 }
4320 udelay(1);
4321
4322 i = (getfrom_srom(addr) >> 3) & 0x01;
4323
4324 return;
4325 }
4326
4327 static short
4328 srom_data(u_int command, u_long addr)
4329 {
4330 int i;
4331 short word = 0;
4332 s32 tmp;
4333
4334 for (i=0; i<16; i++) {
4335 sendto_srom(command | DT_CLK, addr);
4336 tmp = getfrom_srom(addr);
4337 sendto_srom(command, addr);
4338
4339 word = (word << 1) | ((tmp >> 3) & 0x01);
4340 }
4341
4342 sendto_srom(command & 0x0000ff00, addr);
4343
4344 return word;
4345 }
4346
4347 /*
4348 static void
4349 srom_busy(u_int command, u_long addr)
4350 {
4351 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4352
4353 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4354 mdelay(1);
4355 }
4356
4357 sendto_srom(command & 0x0000ff00, addr);
4358
4359 return;
4360 }
4361 */
4362
4363 static void
4364 sendto_srom(u_int command, u_long addr)
4365 {
4366 outl(command, addr);
4367 udelay(1);
4368
4369 return;
4370 }
4371
4372 static int
4373 getfrom_srom(u_long addr)
4374 {
4375 s32 tmp;
4376
4377 tmp = inl(addr);
4378 udelay(1);
4379
4380 return tmp;
4381 }
4382
4383 static int
4384 srom_infoleaf_info(struct net_device *dev)
4385 {
4386 struct de4x5_private *lp = netdev_priv(dev);
4387 int i, count;
4388 u_char *p;
4389
4390 /* Find the infoleaf decoder function that matches this chipset */
4391 for (i=0; i<INFOLEAF_SIZE; i++) {
4392 if (lp->chipset == infoleaf_array[i].chipset) break;
4393 }
4394 if (i == INFOLEAF_SIZE) {
4395 lp->useSROM = false;
4396 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4397 dev->name);
4398 return -ENXIO;
4399 }
4400
4401 lp->infoleaf_fn = infoleaf_array[i].fn;
4402
4403 /* Find the information offset that this function should use */
4404 count = *((u_char *)&lp->srom + 19);
4405 p = (u_char *)&lp->srom + 26;
4406
4407 if (count > 1) {
4408 for (i=count; i; --i, p+=3) {
4409 if (lp->device == *p) break;
4410 }
4411 if (i == 0) {
4412 lp->useSROM = false;
4413 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4414 dev->name, lp->device);
4415 return -ENXIO;
4416 }
4417 }
4418
4419 lp->infoleaf_offset = TWIDDLE(p+1);
4420
4421 return 0;
4422 }
4423
4424 /*
4425 ** This routine loads any type 1 or 3 MII info into the mii device
4426 ** struct and executes any type 5 code to reset PHY devices for this
4427 ** controller.
4428 ** The info for the MII devices will be valid since the index used
4429 ** will follow the discovery process from MII address 1-31 then 0.
4430 */
4431 static void
4432 srom_init(struct net_device *dev)
4433 {
4434 struct de4x5_private *lp = netdev_priv(dev);
4435 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4436 u_char count;
4437
4438 p+=2;
4439 if (lp->chipset == DC21140) {
4440 lp->cache.gepc = (*p++ | GEP_CTRL);
4441 gep_wr(lp->cache.gepc, dev);
4442 }
4443
4444 /* Block count */
4445 count = *p++;
4446
4447 /* Jump the infoblocks to find types */
4448 for (;count; --count) {
4449 if (*p < 128) {
4450 p += COMPACT_LEN;
4451 } else if (*(p+1) == 5) {
4452 type5_infoblock(dev, 1, p);
4453 p += ((*p & BLOCK_LEN) + 1);
4454 } else if (*(p+1) == 4) {
4455 p += ((*p & BLOCK_LEN) + 1);
4456 } else if (*(p+1) == 3) {
4457 type3_infoblock(dev, 1, p);
4458 p += ((*p & BLOCK_LEN) + 1);
4459 } else if (*(p+1) == 2) {
4460 p += ((*p & BLOCK_LEN) + 1);
4461 } else if (*(p+1) == 1) {
4462 type1_infoblock(dev, 1, p);
4463 p += ((*p & BLOCK_LEN) + 1);
4464 } else {
4465 p += ((*p & BLOCK_LEN) + 1);
4466 }
4467 }
4468
4469 return;
4470 }
4471
4472 /*
4473 ** A generic routine that writes GEP control, data and reset information
4474 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4475 */
4476 static void
4477 srom_exec(struct net_device *dev, u_char *p)
4478 {
4479 struct de4x5_private *lp = netdev_priv(dev);
4480 u_long iobase = dev->base_addr;
4481 u_char count = (p ? *p++ : 0);
4482 u_short *w = (u_short *)p;
4483
4484 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4485
4486 if (lp->chipset != DC21140) RESET_SIA;
4487
4488 while (count--) {
4489 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4490 *p++ : TWIDDLE(w++)), dev);
4491 mdelay(2); /* 2ms per action */
4492 }
4493
4494 if (lp->chipset != DC21140) {
4495 outl(lp->cache.csr14, DE4X5_STRR);
4496 outl(lp->cache.csr13, DE4X5_SICR);
4497 }
4498
4499 return;
4500 }
4501
4502 /*
4503 ** Basically this function is a NOP since it will never be called,
4504 ** unless I implement the DC21041 SROM functions. There's no need
4505 ** since the existing code will be satisfactory for all boards.
4506 */
4507 static int
4508 dc21041_infoleaf(struct net_device *dev)
4509 {
4510 return DE4X5_AUTOSENSE_MS;
4511 }
4512
4513 static int
4514 dc21140_infoleaf(struct net_device *dev)
4515 {
4516 struct de4x5_private *lp = netdev_priv(dev);
4517 u_char count = 0;
4518 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4519 int next_tick = DE4X5_AUTOSENSE_MS;
4520
4521 /* Read the connection type */
4522 p+=2;
4523
4524 /* GEP control */
4525 lp->cache.gepc = (*p++ | GEP_CTRL);
4526
4527 /* Block count */
4528 count = *p++;
4529
4530 /* Recursively figure out the info blocks */
4531 if (*p < 128) {
4532 next_tick = dc_infoblock[COMPACT](dev, count, p);
4533 } else {
4534 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4535 }
4536
4537 if (lp->tcount == count) {
4538 lp->media = NC;
4539 if (lp->media != lp->c_media) {
4540 de4x5_dbg_media(dev);
4541 lp->c_media = lp->media;
4542 }
4543 lp->media = INIT;
4544 lp->tcount = 0;
4545 lp->tx_enable = false;
4546 }
4547
4548 return next_tick & ~TIMER_CB;
4549 }
4550
4551 static int
4552 dc21142_infoleaf(struct net_device *dev)
4553 {
4554 struct de4x5_private *lp = netdev_priv(dev);
4555 u_char count = 0;
4556 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4557 int next_tick = DE4X5_AUTOSENSE_MS;
4558
4559 /* Read the connection type */
4560 p+=2;
4561
4562 /* Block count */
4563 count = *p++;
4564
4565 /* Recursively figure out the info blocks */
4566 if (*p < 128) {
4567 next_tick = dc_infoblock[COMPACT](dev, count, p);
4568 } else {
4569 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4570 }
4571
4572 if (lp->tcount == count) {
4573 lp->media = NC;
4574 if (lp->media != lp->c_media) {
4575 de4x5_dbg_media(dev);
4576 lp->c_media = lp->media;
4577 }
4578 lp->media = INIT;
4579 lp->tcount = 0;
4580 lp->tx_enable = false;
4581 }
4582
4583 return next_tick & ~TIMER_CB;
4584 }
4585
4586 static int
4587 dc21143_infoleaf(struct net_device *dev)
4588 {
4589 struct de4x5_private *lp = netdev_priv(dev);
4590 u_char count = 0;
4591 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4592 int next_tick = DE4X5_AUTOSENSE_MS;
4593
4594 /* Read the connection type */
4595 p+=2;
4596
4597 /* Block count */
4598 count = *p++;
4599
4600 /* Recursively figure out the info blocks */
4601 if (*p < 128) {
4602 next_tick = dc_infoblock[COMPACT](dev, count, p);
4603 } else {
4604 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4605 }
4606 if (lp->tcount == count) {
4607 lp->media = NC;
4608 if (lp->media != lp->c_media) {
4609 de4x5_dbg_media(dev);
4610 lp->c_media = lp->media;
4611 }
4612 lp->media = INIT;
4613 lp->tcount = 0;
4614 lp->tx_enable = false;
4615 }
4616
4617 return next_tick & ~TIMER_CB;
4618 }
4619
4620 /*
4621 ** The compact infoblock is only designed for DC21140[A] chips, so
4622 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4623 */
4624 static int
4625 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4626 {
4627 struct de4x5_private *lp = netdev_priv(dev);
4628 u_char flags, csr6;
4629
4630 /* Recursively figure out the info blocks */
4631 if (--count > lp->tcount) {
4632 if (*(p+COMPACT_LEN) < 128) {
4633 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4634 } else {
4635 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4636 }
4637 }
4638
4639 if ((lp->media == INIT) && (lp->timeout < 0)) {
4640 lp->ibn = COMPACT;
4641 lp->active = 0;
4642 gep_wr(lp->cache.gepc, dev);
4643 lp->infoblock_media = (*p++) & COMPACT_MC;
4644 lp->cache.gep = *p++;
4645 csr6 = *p++;
4646 flags = *p++;
4647
4648 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4649 lp->defMedium = (flags & 0x40) ? -1 : 0;
4650 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4651 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4652 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4653 lp->useMII = false;
4654
4655 de4x5_switch_mac_port(dev);
4656 }
4657
4658 return dc21140m_autoconf(dev);
4659 }
4660
4661 /*
4662 ** This block describes non MII media for the DC21140[A] only.
4663 */
4664 static int
4665 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4666 {
4667 struct de4x5_private *lp = netdev_priv(dev);
4668 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4669
4670 /* Recursively figure out the info blocks */
4671 if (--count > lp->tcount) {
4672 if (*(p+len) < 128) {
4673 return dc_infoblock[COMPACT](dev, count, p+len);
4674 } else {
4675 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4676 }
4677 }
4678
4679 if ((lp->media == INIT) && (lp->timeout < 0)) {
4680 lp->ibn = 0;
4681 lp->active = 0;
4682 gep_wr(lp->cache.gepc, dev);
4683 p+=2;
4684 lp->infoblock_media = (*p++) & BLOCK0_MC;
4685 lp->cache.gep = *p++;
4686 csr6 = *p++;
4687 flags = *p++;
4688
4689 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4690 lp->defMedium = (flags & 0x40) ? -1 : 0;
4691 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4692 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4693 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4694 lp->useMII = false;
4695
4696 de4x5_switch_mac_port(dev);
4697 }
4698
4699 return dc21140m_autoconf(dev);
4700 }
4701
4702 /* These functions are under construction! */
4703
4704 static int
4705 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4706 {
4707 struct de4x5_private *lp = netdev_priv(dev);
4708 u_char len = (*p & BLOCK_LEN)+1;
4709
4710 /* Recursively figure out the info blocks */
4711 if (--count > lp->tcount) {
4712 if (*(p+len) < 128) {
4713 return dc_infoblock[COMPACT](dev, count, p+len);
4714 } else {
4715 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4716 }
4717 }
4718
4719 p += 2;
4720 if (lp->state == INITIALISED) {
4721 lp->ibn = 1;
4722 lp->active = *p++;
4723 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4724 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4725 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4726 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4727 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4728 lp->phy[lp->active].ttm = TWIDDLE(p);
4729 return 0;
4730 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4731 lp->ibn = 1;
4732 lp->active = *p;
4733 lp->infoblock_csr6 = OMR_MII_100;
4734 lp->useMII = true;
4735 lp->infoblock_media = ANS;
4736
4737 de4x5_switch_mac_port(dev);
4738 }
4739
4740 return dc21140m_autoconf(dev);
4741 }
4742
4743 static int
4744 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4745 {
4746 struct de4x5_private *lp = netdev_priv(dev);
4747 u_char len = (*p & BLOCK_LEN)+1;
4748
4749 /* Recursively figure out the info blocks */
4750 if (--count > lp->tcount) {
4751 if (*(p+len) < 128) {
4752 return dc_infoblock[COMPACT](dev, count, p+len);
4753 } else {
4754 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4755 }
4756 }
4757
4758 if ((lp->media == INIT) && (lp->timeout < 0)) {
4759 lp->ibn = 2;
4760 lp->active = 0;
4761 p += 2;
4762 lp->infoblock_media = (*p) & MEDIA_CODE;
4763
4764 if ((*p++) & EXT_FIELD) {
4765 lp->cache.csr13 = TWIDDLE(p); p += 2;
4766 lp->cache.csr14 = TWIDDLE(p); p += 2;
4767 lp->cache.csr15 = TWIDDLE(p); p += 2;
4768 } else {
4769 lp->cache.csr13 = CSR13;
4770 lp->cache.csr14 = CSR14;
4771 lp->cache.csr15 = CSR15;
4772 }
4773 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4774 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4775 lp->infoblock_csr6 = OMR_SIA;
4776 lp->useMII = false;
4777
4778 de4x5_switch_mac_port(dev);
4779 }
4780
4781 return dc2114x_autoconf(dev);
4782 }
4783
4784 static int
4785 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4786 {
4787 struct de4x5_private *lp = netdev_priv(dev);
4788 u_char len = (*p & BLOCK_LEN)+1;
4789
4790 /* Recursively figure out the info blocks */
4791 if (--count > lp->tcount) {
4792 if (*(p+len) < 128) {
4793 return dc_infoblock[COMPACT](dev, count, p+len);
4794 } else {
4795 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4796 }
4797 }
4798
4799 p += 2;
4800 if (lp->state == INITIALISED) {
4801 lp->ibn = 3;
4802 lp->active = *p++;
4803 if (MOTO_SROM_BUG) lp->active = 0;
4804 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4805 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4806 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4807 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4808 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4809 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4810 lp->phy[lp->active].mci = *p;
4811 return 0;
4812 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4813 lp->ibn = 3;
4814 lp->active = *p;
4815 if (MOTO_SROM_BUG) lp->active = 0;
4816 lp->infoblock_csr6 = OMR_MII_100;
4817 lp->useMII = true;
4818 lp->infoblock_media = ANS;
4819
4820 de4x5_switch_mac_port(dev);
4821 }
4822
4823 return dc2114x_autoconf(dev);
4824 }
4825
4826 static int
4827 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4828 {
4829 struct de4x5_private *lp = netdev_priv(dev);
4830 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4831
4832 /* Recursively figure out the info blocks */
4833 if (--count > lp->tcount) {
4834 if (*(p+len) < 128) {
4835 return dc_infoblock[COMPACT](dev, count, p+len);
4836 } else {
4837 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4838 }
4839 }
4840
4841 if ((lp->media == INIT) && (lp->timeout < 0)) {
4842 lp->ibn = 4;
4843 lp->active = 0;
4844 p+=2;
4845 lp->infoblock_media = (*p++) & MEDIA_CODE;
4846 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4847 lp->cache.csr14 = CSR14;
4848 lp->cache.csr15 = CSR15;
4849 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4850 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4851 csr6 = *p++;
4852 flags = *p++;
4853
4854 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4855 lp->defMedium = (flags & 0x40) ? -1 : 0;
4856 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4857 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4858 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4859 lp->useMII = false;
4860
4861 de4x5_switch_mac_port(dev);
4862 }
4863
4864 return dc2114x_autoconf(dev);
4865 }
4866
4867 /*
4868 ** This block type provides information for resetting external devices
4869 ** (chips) through the General Purpose Register.
4870 */
4871 static int
4872 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4873 {
4874 struct de4x5_private *lp = netdev_priv(dev);
4875 u_char len = (*p & BLOCK_LEN)+1;
4876
4877 /* Recursively figure out the info blocks */
4878 if (--count > lp->tcount) {
4879 if (*(p+len) < 128) {
4880 return dc_infoblock[COMPACT](dev, count, p+len);
4881 } else {
4882 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4883 }
4884 }
4885
4886 /* Must be initializing to run this code */
4887 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4888 p+=2;
4889 lp->rst = p;
4890 srom_exec(dev, lp->rst);
4891 }
4892
4893 return DE4X5_AUTOSENSE_MS;
4894 }
4895
4896 /*
4897 ** MII Read/Write
4898 */
4899
4900 static int
4901 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4902 {
4903 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4904 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4905 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4906 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4907 mii_address(phyreg, ioaddr); /* PHY Register to read */
4908 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4909
4910 return mii_rdata(ioaddr); /* Read data */
4911 }
4912
4913 static void
4914 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4915 {
4916 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4917 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4918 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4919 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4920 mii_address(phyreg, ioaddr); /* PHY Register to write */
4921 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4922 data = mii_swap(data, 16); /* Swap data bit ordering */
4923 mii_wdata(data, 16, ioaddr); /* Write data */
4924
4925 return;
4926 }
4927
4928 static int
4929 mii_rdata(u_long ioaddr)
4930 {
4931 int i;
4932 s32 tmp = 0;
4933
4934 for (i=0; i<16; i++) {
4935 tmp <<= 1;
4936 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4937 }
4938
4939 return tmp;
4940 }
4941
4942 static void
4943 mii_wdata(int data, int len, u_long ioaddr)
4944 {
4945 int i;
4946
4947 for (i=0; i<len; i++) {
4948 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4949 data >>= 1;
4950 }
4951
4952 return;
4953 }
4954
4955 static void
4956 mii_address(u_char addr, u_long ioaddr)
4957 {
4958 int i;
4959
4960 addr = mii_swap(addr, 5);
4961 for (i=0; i<5; i++) {
4962 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4963 addr >>= 1;
4964 }
4965
4966 return;
4967 }
4968
4969 static void
4970 mii_ta(u_long rw, u_long ioaddr)
4971 {
4972 if (rw == MII_STWR) {
4973 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4974 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4975 } else {
4976 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4977 }
4978
4979 return;
4980 }
4981
4982 static int
4983 mii_swap(int data, int len)
4984 {
4985 int i, tmp = 0;
4986
4987 for (i=0; i<len; i++) {
4988 tmp <<= 1;
4989 tmp |= (data & 1);
4990 data >>= 1;
4991 }
4992
4993 return tmp;
4994 }
4995
4996 static void
4997 sendto_mii(u32 command, int data, u_long ioaddr)
4998 {
4999 u32 j;
5000
5001 j = (data & 1) << 17;
5002 outl(command | j, ioaddr);
5003 udelay(1);
5004 outl(command | MII_MDC | j, ioaddr);
5005 udelay(1);
5006
5007 return;
5008 }
5009
5010 static int
5011 getfrom_mii(u32 command, u_long ioaddr)
5012 {
5013 outl(command, ioaddr);
5014 udelay(1);
5015 outl(command | MII_MDC, ioaddr);
5016 udelay(1);
5017
5018 return ((inl(ioaddr) >> 19) & 1);
5019 }
5020
5021 /*
5022 ** Here's 3 ways to calculate the OUI from the ID registers.
5023 */
5024 static int
5025 mii_get_oui(u_char phyaddr, u_long ioaddr)
5026 {
5027 /*
5028 union {
5029 u_short reg;
5030 u_char breg[2];
5031 } a;
5032 int i, r2, r3, ret=0;*/
5033 int r2, r3;
5034
5035 /* Read r2 and r3 */
5036 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5037 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5038 /* SEEQ and Cypress way * /
5039 / * Shuffle r2 and r3 * /
5040 a.reg=0;
5041 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5042 r2 = ((r2>>2)&0x3fff);
5043
5044 / * Bit reverse r3 * /
5045 for (i=0;i<8;i++) {
5046 ret<<=1;
5047 ret |= (r3&1);
5048 r3>>=1;
5049 }
5050
5051 / * Bit reverse r2 * /
5052 for (i=0;i<16;i++) {
5053 a.reg<<=1;
5054 a.reg |= (r2&1);
5055 r2>>=1;
5056 }
5057
5058 / * Swap r2 bytes * /
5059 i=a.breg[0];
5060 a.breg[0]=a.breg[1];
5061 a.breg[1]=i;
5062
5063 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5064 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5065 return r2; /* (I did it) My way */
5066 }
5067
5068 /*
5069 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5070 */
5071 static int
5072 mii_get_phy(struct net_device *dev)
5073 {
5074 struct de4x5_private *lp = netdev_priv(dev);
5075 u_long iobase = dev->base_addr;
5076 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5077 int id;
5078
5079 lp->active = 0;
5080 lp->useMII = true;
5081
5082 /* Search the MII address space for possible PHY devices */
5083 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5084 lp->phy[lp->active].addr = i;
5085 if (i==0) n++; /* Count cycles */
5086 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5087 id = mii_get_oui(i, DE4X5_MII);
5088 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5089 for (j=0; j<limit; j++) { /* Search PHY table */
5090 if (id != phy_info[j].id) continue; /* ID match? */
5091 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5092 if (k < DE4X5_MAX_PHY) {
5093 memcpy((char *)&lp->phy[k],
5094 (char *)&phy_info[j], sizeof(struct phy_table));
5095 lp->phy[k].addr = i;
5096 lp->mii_cnt++;
5097 lp->active++;
5098 } else {
5099 goto purgatory; /* Stop the search */
5100 }
5101 break;
5102 }
5103 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5104 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5105 lp->phy[k].addr = i;
5106 lp->phy[k].id = id;
5107 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5108 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5109 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5110 lp->mii_cnt++;
5111 lp->active++;
5112 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5113 j = de4x5_debug;
5114 de4x5_debug |= DEBUG_MII;
5115 de4x5_dbg_mii(dev, k);
5116 de4x5_debug = j;
5117 printk("\n");
5118 }
5119 }
5120 purgatory:
5121 lp->active = 0;
5122 if (lp->phy[0].id) { /* Reset the PHY devices */
5123 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5124 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5125 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5126
5127 de4x5_dbg_mii(dev, k);
5128 }
5129 }
5130 if (!lp->mii_cnt) lp->useMII = false;
5131
5132 return lp->mii_cnt;
5133 }
5134
5135 static char *
5136 build_setup_frame(struct net_device *dev, int mode)
5137 {
5138 struct de4x5_private *lp = netdev_priv(dev);
5139 int i;
5140 char *pa = lp->setup_frame;
5141
5142 /* Initialise the setup frame */
5143 if (mode == ALL) {
5144 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5145 }
5146
5147 if (lp->setup_f == HASH_PERF) {
5148 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5149 *(pa + i) = dev->dev_addr[i]; /* Host address */
5150 if (i & 0x01) pa += 2;
5151 }
5152 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5153 } else {
5154 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5155 *(pa + (i&1)) = dev->dev_addr[i];
5156 if (i & 0x01) pa += 4;
5157 }
5158 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5159 *(pa + (i&1)) = (char) 0xff;
5160 if (i & 0x01) pa += 4;
5161 }
5162 }
5163
5164 return pa; /* Points to the next entry */
5165 }
5166
5167 static void
5168 enable_ast(struct net_device *dev, u32 time_out)
5169 {
5170 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5171
5172 return;
5173 }
5174
5175 static void
5176 disable_ast(struct net_device *dev)
5177 {
5178 struct de4x5_private *lp = netdev_priv(dev);
5179
5180 del_timer(&lp->timer);
5181
5182 return;
5183 }
5184
5185 static long
5186 de4x5_switch_mac_port(struct net_device *dev)
5187 {
5188 struct de4x5_private *lp = netdev_priv(dev);
5189 u_long iobase = dev->base_addr;
5190 s32 omr;
5191
5192 STOP_DE4X5;
5193
5194 /* Assert the OMR_PS bit in CSR6 */
5195 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5196 OMR_FDX));
5197 omr |= lp->infoblock_csr6;
5198 if (omr & OMR_PS) omr |= OMR_HBD;
5199 outl(omr, DE4X5_OMR);
5200
5201 /* Soft Reset */
5202 RESET_DE4X5;
5203
5204 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5205 if (lp->chipset == DC21140) {
5206 gep_wr(lp->cache.gepc, dev);
5207 gep_wr(lp->cache.gep, dev);
5208 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5209 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5210 }
5211
5212 /* Restore CSR6 */
5213 outl(omr, DE4X5_OMR);
5214
5215 /* Reset CSR8 */
5216 inl(DE4X5_MFC);
5217
5218 return omr;
5219 }
5220
5221 static void
5222 gep_wr(s32 data, struct net_device *dev)
5223 {
5224 struct de4x5_private *lp = netdev_priv(dev);
5225 u_long iobase = dev->base_addr;
5226
5227 if (lp->chipset == DC21140) {
5228 outl(data, DE4X5_GEP);
5229 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5230 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5231 }
5232
5233 return;
5234 }
5235
5236 static int
5237 gep_rd(struct net_device *dev)
5238 {
5239 struct de4x5_private *lp = netdev_priv(dev);
5240 u_long iobase = dev->base_addr;
5241
5242 if (lp->chipset == DC21140) {
5243 return inl(DE4X5_GEP);
5244 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5245 return (inl(DE4X5_SIGR) & 0x000fffff);
5246 }
5247
5248 return 0;
5249 }
5250
5251 static void
5252 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5253 {
5254 struct de4x5_private *lp = netdev_priv(dev);
5255 int dt;
5256
5257 /* First, cancel any pending timer events */
5258 del_timer(&lp->timer);
5259
5260 /* Convert msec to ticks */
5261 dt = (msec * HZ) / 1000;
5262 if (dt==0) dt=1;
5263
5264 /* Set up timer */
5265 init_timer(&lp->timer);
5266 lp->timer.expires = jiffies + dt;
5267 lp->timer.function = fn;
5268 lp->timer.data = data;
5269 add_timer(&lp->timer);
5270
5271 return;
5272 }
5273
5274 static void
5275 yawn(struct net_device *dev, int state)
5276 {
5277 struct de4x5_private *lp = netdev_priv(dev);
5278 u_long iobase = dev->base_addr;
5279
5280 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5281
5282 if(lp->bus == EISA) {
5283 switch(state) {
5284 case WAKEUP:
5285 outb(WAKEUP, PCI_CFPM);
5286 mdelay(10);
5287 break;
5288
5289 case SNOOZE:
5290 outb(SNOOZE, PCI_CFPM);
5291 break;
5292
5293 case SLEEP:
5294 outl(0, DE4X5_SICR);
5295 outb(SLEEP, PCI_CFPM);
5296 break;
5297 }
5298 } else {
5299 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5300 switch(state) {
5301 case WAKEUP:
5302 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5303 mdelay(10);
5304 break;
5305
5306 case SNOOZE:
5307 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5308 break;
5309
5310 case SLEEP:
5311 outl(0, DE4X5_SICR);
5312 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5313 break;
5314 }
5315 }
5316
5317 return;
5318 }
5319
5320 static void
5321 de4x5_parse_params(struct net_device *dev)
5322 {
5323 struct de4x5_private *lp = netdev_priv(dev);
5324 char *p, *q, t;
5325
5326 lp->params.fdx = 0;
5327 lp->params.autosense = AUTO;
5328
5329 if (args == NULL) return;
5330
5331 if ((p = strstr(args, dev->name))) {
5332 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5333 t = *q;
5334 *q = '\0';
5335
5336 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5337
5338 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5339 if (strstr(p, "TP")) {
5340 lp->params.autosense = TP;
5341 } else if (strstr(p, "TP_NW")) {
5342 lp->params.autosense = TP_NW;
5343 } else if (strstr(p, "BNC")) {
5344 lp->params.autosense = BNC;
5345 } else if (strstr(p, "AUI")) {
5346 lp->params.autosense = AUI;
5347 } else if (strstr(p, "BNC_AUI")) {
5348 lp->params.autosense = BNC;
5349 } else if (strstr(p, "10Mb")) {
5350 lp->params.autosense = _10Mb;
5351 } else if (strstr(p, "100Mb")) {
5352 lp->params.autosense = _100Mb;
5353 } else if (strstr(p, "AUTO")) {
5354 lp->params.autosense = AUTO;
5355 }
5356 }
5357 *q = t;
5358 }
5359
5360 return;
5361 }
5362
5363 static void
5364 de4x5_dbg_open(struct net_device *dev)
5365 {
5366 struct de4x5_private *lp = netdev_priv(dev);
5367 int i;
5368
5369 if (de4x5_debug & DEBUG_OPEN) {
5370 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5371 printk("\tphysical address: ");
5372 for (i=0;i<6;i++) {
5373 printk("%2.2x:",(short)dev->dev_addr[i]);
5374 }
5375 printk("\n");
5376 printk("Descriptor head addresses:\n");
5377 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5378 printk("Descriptor addresses:\nRX: ");
5379 for (i=0;i<lp->rxRingSize-1;i++){
5380 if (i < 3) {
5381 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5382 }
5383 }
5384 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5385 printk("TX: ");
5386 for (i=0;i<lp->txRingSize-1;i++){
5387 if (i < 3) {
5388 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5389 }
5390 }
5391 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5392 printk("Descriptor buffers:\nRX: ");
5393 for (i=0;i<lp->rxRingSize-1;i++){
5394 if (i < 3) {
5395 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5396 }
5397 }
5398 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5399 printk("TX: ");
5400 for (i=0;i<lp->txRingSize-1;i++){
5401 if (i < 3) {
5402 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5403 }
5404 }
5405 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5406 printk("Ring size: \nRX: %d\nTX: %d\n",
5407 (short)lp->rxRingSize,
5408 (short)lp->txRingSize);
5409 }
5410
5411 return;
5412 }
5413
5414 static void
5415 de4x5_dbg_mii(struct net_device *dev, int k)
5416 {
5417 struct de4x5_private *lp = netdev_priv(dev);
5418 u_long iobase = dev->base_addr;
5419
5420 if (de4x5_debug & DEBUG_MII) {
5421 printk("\nMII device address: %d\n", lp->phy[k].addr);
5422 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5423 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5424 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5425 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5426 if (lp->phy[k].id != BROADCOM_T4) {
5427 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5428 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5429 }
5430 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5431 if (lp->phy[k].id != BROADCOM_T4) {
5432 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5434 } else {
5435 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5436 }
5437 }
5438
5439 return;
5440 }
5441
5442 static void
5443 de4x5_dbg_media(struct net_device *dev)
5444 {
5445 struct de4x5_private *lp = netdev_priv(dev);
5446
5447 if (lp->media != lp->c_media) {
5448 if (de4x5_debug & DEBUG_MEDIA) {
5449 printk("%s: media is %s%s\n", dev->name,
5450 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5451 (lp->media == TP ? "TP" :
5452 (lp->media == ANS ? "TP/Nway" :
5453 (lp->media == BNC ? "BNC" :
5454 (lp->media == AUI ? "AUI" :
5455 (lp->media == BNC_AUI ? "BNC/AUI" :
5456 (lp->media == EXT_SIA ? "EXT SIA" :
5457 (lp->media == _100Mb ? "100Mb/s" :
5458 (lp->media == _10Mb ? "10Mb/s" :
5459 "???"
5460 ))))))))), (lp->fdx?" full duplex.":"."));
5461 }
5462 lp->c_media = lp->media;
5463 }
5464
5465 return;
5466 }
5467
5468 static void
5469 de4x5_dbg_srom(struct de4x5_srom *p)
5470 {
5471 int i;
5472
5473 if (de4x5_debug & DEBUG_SROM) {
5474 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5475 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5476 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5477 printk("SROM version: %02x\n", (u_char)(p->version));
5478 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5479
5480 printk("Hardware Address: ");
5481 for (i=0;i<ETH_ALEN-1;i++) {
5482 printk("%02x:", (u_char)*(p->ieee_addr+i));
5483 }
5484 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5485 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5486 for (i=0; i<64; i++) {
5487 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5488 }
5489 }
5490
5491 return;
5492 }
5493
5494 static void
5495 de4x5_dbg_rx(struct sk_buff *skb, int len)
5496 {
5497 int i, j;
5498
5499 if (de4x5_debug & DEBUG_RX) {
5500 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5501 (u_char)skb->data[0],
5502 (u_char)skb->data[1],
5503 (u_char)skb->data[2],
5504 (u_char)skb->data[3],
5505 (u_char)skb->data[4],
5506 (u_char)skb->data[5],
5507 (u_char)skb->data[6],
5508 (u_char)skb->data[7],
5509 (u_char)skb->data[8],
5510 (u_char)skb->data[9],
5511 (u_char)skb->data[10],
5512 (u_char)skb->data[11],
5513 (u_char)skb->data[12],
5514 (u_char)skb->data[13],
5515 len);
5516 for (j=0; len>0;j+=16, len-=16) {
5517 printk(" %03x: ",j);
5518 for (i=0; i<16 && i<len; i++) {
5519 printk("%02x ",(u_char)skb->data[i+j]);
5520 }
5521 printk("\n");
5522 }
5523 }
5524
5525 return;
5526 }
5527
5528 /*
5529 ** Perform IOCTL call functions here. Some are privileged operations and the
5530 ** effective uid is checked in those cases. In the normal course of events
5531 ** this function is only used for my testing.
5532 */
5533 static int
5534 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5535 {
5536 struct de4x5_private *lp = netdev_priv(dev);
5537 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5538 u_long iobase = dev->base_addr;
5539 int i, j, status = 0;
5540 s32 omr;
5541 union {
5542 u8 addr[144];
5543 u16 sval[72];
5544 u32 lval[36];
5545 } tmp;
5546 u_long flags = 0;
5547
5548 switch(ioc->cmd) {
5549 case DE4X5_GET_HWADDR: /* Get the hardware address */
5550 ioc->len = ETH_ALEN;
5551 for (i=0; i<ETH_ALEN; i++) {
5552 tmp.addr[i] = dev->dev_addr[i];
5553 }
5554 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5555 break;
5556
5557 case DE4X5_SET_HWADDR: /* Set the hardware address */
5558 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5559 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5560 if (netif_queue_stopped(dev))
5561 return -EBUSY;
5562 netif_stop_queue(dev);
5563 for (i=0; i<ETH_ALEN; i++) {
5564 dev->dev_addr[i] = tmp.addr[i];
5565 }
5566 build_setup_frame(dev, PHYS_ADDR_ONLY);
5567 /* Set up the descriptor and give ownership to the card */
5568 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5569 SETUP_FRAME_LEN, (struct sk_buff *)1);
5570 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5571 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5572 netif_wake_queue(dev); /* Unlock the TX ring */
5573 break;
5574
5575 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5576 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5577 omr = inl(DE4X5_OMR);
5578 omr |= OMR_PR;
5579 outl(omr, DE4X5_OMR);
5580 dev->flags |= IFF_PROMISC;
5581 break;
5582
5583 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5584 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5585 omr = inl(DE4X5_OMR);
5586 omr &= ~OMR_PR;
5587 outl(omr, DE4X5_OMR);
5588 dev->flags &= ~IFF_PROMISC;
5589 break;
5590
5591 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5592 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5593 printk("%s: Boo!\n", dev->name);
5594 break;
5595
5596 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5597 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5598 omr = inl(DE4X5_OMR);
5599 omr |= OMR_PM;
5600 outl(omr, DE4X5_OMR);
5601 break;
5602
5603 case DE4X5_GET_STATS: /* Get the driver statistics */
5604 {
5605 struct pkt_stats statbuf;
5606 ioc->len = sizeof(statbuf);
5607 spin_lock_irqsave(&lp->lock, flags);
5608 memcpy(&statbuf, &lp->pktStats, ioc->len);
5609 spin_unlock_irqrestore(&lp->lock, flags);
5610 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5611 return -EFAULT;
5612 break;
5613 }
5614 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5615 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5616 spin_lock_irqsave(&lp->lock, flags);
5617 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5618 spin_unlock_irqrestore(&lp->lock, flags);
5619 break;
5620
5621 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5622 tmp.addr[0] = inl(DE4X5_OMR);
5623 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5624 break;
5625
5626 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5627 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5628 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5629 outl(tmp.addr[0], DE4X5_OMR);
5630 break;
5631
5632 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5633 j = 0;
5634 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5635 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5636 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5637 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5638 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5639 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5640 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5641 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5642 ioc->len = j;
5643 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5644 break;
5645
5646 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5647 /*
5648 case DE4X5_DUMP:
5649 j = 0;
5650 tmp.addr[j++] = dev->irq;
5651 for (i=0; i<ETH_ALEN; i++) {
5652 tmp.addr[j++] = dev->dev_addr[i];
5653 }
5654 tmp.addr[j++] = lp->rxRingSize;
5655 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5656 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5657
5658 for (i=0;i<lp->rxRingSize-1;i++){
5659 if (i < 3) {
5660 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5661 }
5662 }
5663 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5664 for (i=0;i<lp->txRingSize-1;i++){
5665 if (i < 3) {
5666 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5667 }
5668 }
5669 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5670
5671 for (i=0;i<lp->rxRingSize-1;i++){
5672 if (i < 3) {
5673 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5674 }
5675 }
5676 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5677 for (i=0;i<lp->txRingSize-1;i++){
5678 if (i < 3) {
5679 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5680 }
5681 }
5682 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5683
5684 for (i=0;i<lp->rxRingSize;i++){
5685 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5686 }
5687 for (i=0;i<lp->txRingSize;i++){
5688 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5689 }
5690
5691 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5692 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5693 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5694 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5695 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5696 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5697 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5699 tmp.lval[j>>2] = lp->chipset; j+=4;
5700 if (lp->chipset == DC21140) {
5701 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5702 } else {
5703 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5705 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5706 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5707 }
5708 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5709 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5710 tmp.lval[j>>2] = lp->active; j+=4;
5711 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5712 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5713 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5714 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5715 if (lp->phy[lp->active].id != BROADCOM_T4) {
5716 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5717 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 }
5719 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5720 if (lp->phy[lp->active].id != BROADCOM_T4) {
5721 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5722 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 } else {
5724 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5725 }
5726 }
5727
5728 tmp.addr[j++] = lp->txRingSize;
5729 tmp.addr[j++] = netif_queue_stopped(dev);
5730
5731 ioc->len = j;
5732 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5733 break;
5734
5735 */
5736 default:
5737 return -EOPNOTSUPP;
5738 }
5739
5740 return status;
5741 }
5742
5743 static int __init de4x5_module_init (void)
5744 {
5745 int err = 0;
5746
5747 #ifdef CONFIG_PCI
5748 err = pci_register_driver(&de4x5_pci_driver);
5749 #endif
5750 #ifdef CONFIG_EISA
5751 err |= eisa_driver_register (&de4x5_eisa_driver);
5752 #endif
5753
5754 return err;
5755 }
5756
5757 static void __exit de4x5_module_exit (void)
5758 {
5759 #ifdef CONFIG_PCI
5760 pci_unregister_driver (&de4x5_pci_driver);
5761 #endif
5762 #ifdef CONFIG_EISA
5763 eisa_driver_unregister (&de4x5_eisa_driver);
5764 #endif
5765 }
5766
5767 module_init (de4x5_module_init);
5768 module_exit (de4x5_module_exit);