2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.101"
72 #define DRV_MODULE_RELDATE "August 28, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define TG3_DMA_BYTE_ENAB 64
130 #define TG3_RX_STD_DMA_SZ 1536
131 #define TG3_RX_JMB_DMA_SZ 9046
133 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138 /* minimum number of free TX descriptors required to wake up TX process */
139 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
141 #define TG3_RAW_IP_ALIGN 2
143 /* number of ETHTOOL_GSTATS u64's */
144 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
146 #define TG3_NUM_TEST 6
148 #define FIRMWARE_TG3 "tigon/tg3.bin"
149 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
152 static char version
[] __devinitdata
=
153 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157 MODULE_LICENSE("GPL");
158 MODULE_VERSION(DRV_MODULE_VERSION
);
159 MODULE_FIRMWARE(FIRMWARE_TG3
);
160 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
163 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
165 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
166 module_param(tg3_debug
, int, 0);
167 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
169 static struct pci_device_id tg3_pci_tbl
[] = {
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
246 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
248 static const struct {
249 const char string
[ETH_GSTRING_LEN
];
250 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
253 { "rx_ucast_packets" },
254 { "rx_mcast_packets" },
255 { "rx_bcast_packets" },
257 { "rx_align_errors" },
258 { "rx_xon_pause_rcvd" },
259 { "rx_xoff_pause_rcvd" },
260 { "rx_mac_ctrl_rcvd" },
261 { "rx_xoff_entered" },
262 { "rx_frame_too_long_errors" },
264 { "rx_undersize_packets" },
265 { "rx_in_length_errors" },
266 { "rx_out_length_errors" },
267 { "rx_64_or_less_octet_packets" },
268 { "rx_65_to_127_octet_packets" },
269 { "rx_128_to_255_octet_packets" },
270 { "rx_256_to_511_octet_packets" },
271 { "rx_512_to_1023_octet_packets" },
272 { "rx_1024_to_1522_octet_packets" },
273 { "rx_1523_to_2047_octet_packets" },
274 { "rx_2048_to_4095_octet_packets" },
275 { "rx_4096_to_8191_octet_packets" },
276 { "rx_8192_to_9022_octet_packets" },
283 { "tx_flow_control" },
285 { "tx_single_collisions" },
286 { "tx_mult_collisions" },
288 { "tx_excessive_collisions" },
289 { "tx_late_collisions" },
290 { "tx_collide_2times" },
291 { "tx_collide_3times" },
292 { "tx_collide_4times" },
293 { "tx_collide_5times" },
294 { "tx_collide_6times" },
295 { "tx_collide_7times" },
296 { "tx_collide_8times" },
297 { "tx_collide_9times" },
298 { "tx_collide_10times" },
299 { "tx_collide_11times" },
300 { "tx_collide_12times" },
301 { "tx_collide_13times" },
302 { "tx_collide_14times" },
303 { "tx_collide_15times" },
304 { "tx_ucast_packets" },
305 { "tx_mcast_packets" },
306 { "tx_bcast_packets" },
307 { "tx_carrier_sense_errors" },
311 { "dma_writeq_full" },
312 { "dma_write_prioq_full" },
316 { "rx_threshold_hit" },
318 { "dma_readq_full" },
319 { "dma_read_prioq_full" },
320 { "tx_comp_queue_full" },
322 { "ring_set_send_prod_index" },
323 { "ring_status_update" },
325 { "nic_avoided_irqs" },
326 { "nic_tx_threshold_hit" }
329 static const struct {
330 const char string
[ETH_GSTRING_LEN
];
331 } ethtool_test_keys
[TG3_NUM_TEST
] = {
332 { "nvram test (online) " },
333 { "link test (online) " },
334 { "register test (offline)" },
335 { "memory test (offline)" },
336 { "loopback test (offline)" },
337 { "interrupt test (offline)" },
340 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
342 writel(val
, tp
->regs
+ off
);
345 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
347 return (readl(tp
->regs
+ off
));
350 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
352 writel(val
, tp
->aperegs
+ off
);
355 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
357 return (readl(tp
->aperegs
+ off
));
360 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
364 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
365 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
366 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
367 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
370 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
372 writel(val
, tp
->regs
+ off
);
373 readl(tp
->regs
+ off
);
376 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
381 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
382 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
383 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
384 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
388 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
392 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
393 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
394 TG3_64BIT_REG_LOW
, val
);
397 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
398 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
399 TG3_64BIT_REG_LOW
, val
);
403 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
405 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
406 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
408 /* In indirect mode when disabling interrupts, we also need
409 * to clear the interrupt bit in the GRC local ctrl register.
411 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
413 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
414 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
418 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
423 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
424 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
425 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
426 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
430 /* usec_wait specifies the wait time in usec when writing to certain registers
431 * where it is unsafe to read back the register without some delay.
432 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
433 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
435 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
437 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
438 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
439 /* Non-posted methods */
440 tp
->write32(tp
, off
, val
);
443 tg3_write32(tp
, off
, val
);
448 /* Wait again after the read for the posted method to guarantee that
449 * the wait time is met.
455 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
457 tp
->write32_mbox(tp
, off
, val
);
458 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
459 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
460 tp
->read32_mbox(tp
, off
);
463 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
465 void __iomem
*mbox
= tp
->regs
+ off
;
467 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
469 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
473 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
475 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
478 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
480 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
483 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
484 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
485 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
486 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
487 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
489 #define tw32(reg,val) tp->write32(tp, reg, val)
490 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
491 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
492 #define tr32(reg) tp->read32(tp, reg)
494 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
498 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
499 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
502 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
503 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
504 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
505 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
507 /* Always leave this as zero. */
508 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
510 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
511 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
513 /* Always leave this as zero. */
514 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
516 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
519 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
523 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
524 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
529 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
530 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
531 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
532 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
534 /* Always leave this as zero. */
535 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
537 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
538 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
540 /* Always leave this as zero. */
541 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
543 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
546 static void tg3_ape_lock_init(struct tg3
*tp
)
550 /* Make sure the driver hasn't any stale locks. */
551 for (i
= 0; i
< 8; i
++)
552 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
553 APE_LOCK_GRANT_DRIVER
);
556 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
562 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
566 case TG3_APE_LOCK_GRC
:
567 case TG3_APE_LOCK_MEM
:
575 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
577 /* Wait for up to 1 millisecond to acquire lock. */
578 for (i
= 0; i
< 100; i
++) {
579 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
580 if (status
== APE_LOCK_GRANT_DRIVER
)
585 if (status
!= APE_LOCK_GRANT_DRIVER
) {
586 /* Revoke the lock request. */
587 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
588 APE_LOCK_GRANT_DRIVER
);
596 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
600 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
604 case TG3_APE_LOCK_GRC
:
605 case TG3_APE_LOCK_MEM
:
612 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
615 static void tg3_disable_ints(struct tg3
*tp
)
619 tw32(TG3PCI_MISC_HOST_CTRL
,
620 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
621 for (i
= 0; i
< tp
->irq_max
; i
++)
622 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
625 static void tg3_enable_ints(struct tg3
*tp
)
633 tw32(TG3PCI_MISC_HOST_CTRL
,
634 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
636 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
637 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
638 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
639 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
640 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
642 coal_now
|= tnapi
->coal_now
;
645 /* Force an initial interrupt */
646 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
647 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
648 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
650 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
651 HOSTCC_MODE_ENABLE
| coal_now
);
654 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
656 struct tg3
*tp
= tnapi
->tp
;
657 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
658 unsigned int work_exists
= 0;
660 /* check for phy events */
661 if (!(tp
->tg3_flags
&
662 (TG3_FLAG_USE_LINKCHG_REG
|
663 TG3_FLAG_POLL_SERDES
))) {
664 if (sblk
->status
& SD_STATUS_LINK_CHG
)
667 /* check for RX/TX work to do */
668 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
669 sblk
->idx
[0].rx_producer
!= tnapi
->rx_rcb_ptr
)
676 * similar to tg3_enable_ints, but it accurately determines whether there
677 * is new work pending and can return without flushing the PIO write
678 * which reenables interrupts
680 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
682 struct tg3
*tp
= tnapi
->tp
;
684 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
687 /* When doing tagged status, this work check is unnecessary.
688 * The last_tag we write above tells the chip which piece of
689 * work we've completed.
691 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
693 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
694 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
697 static inline void tg3_netif_stop(struct tg3
*tp
)
699 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
700 napi_disable(&tp
->napi
[0].napi
);
701 netif_tx_disable(tp
->dev
);
704 static inline void tg3_netif_start(struct tg3
*tp
)
706 struct tg3_napi
*tnapi
= &tp
->napi
[0];
707 netif_wake_queue(tp
->dev
);
708 /* NOTE: unconditional netif_wake_queue is only appropriate
709 * so long as all callers are assured to have free tx slots
710 * (such as after tg3_init_hw)
712 napi_enable(&tnapi
->napi
);
713 tnapi
->hw_status
->status
|= SD_STATUS_UPDATED
;
717 static void tg3_switch_clocks(struct tg3
*tp
)
719 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
722 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
723 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
726 orig_clock_ctrl
= clock_ctrl
;
727 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
728 CLOCK_CTRL_CLKRUN_OENABLE
|
730 tp
->pci_clock_ctrl
= clock_ctrl
;
732 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
733 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
734 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
735 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
737 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
738 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
740 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
742 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
743 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
746 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
749 #define PHY_BUSY_LOOPS 5000
751 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
757 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
759 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
765 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
766 MI_COM_PHY_ADDR_MASK
);
767 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
768 MI_COM_REG_ADDR_MASK
);
769 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
771 tw32_f(MAC_MI_COM
, frame_val
);
773 loops
= PHY_BUSY_LOOPS
;
776 frame_val
= tr32(MAC_MI_COM
);
778 if ((frame_val
& MI_COM_BUSY
) == 0) {
780 frame_val
= tr32(MAC_MI_COM
);
788 *val
= frame_val
& MI_COM_DATA_MASK
;
792 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
793 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
800 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
806 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
807 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
810 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
812 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
816 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
817 MI_COM_PHY_ADDR_MASK
);
818 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
819 MI_COM_REG_ADDR_MASK
);
820 frame_val
|= (val
& MI_COM_DATA_MASK
);
821 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
823 tw32_f(MAC_MI_COM
, frame_val
);
825 loops
= PHY_BUSY_LOOPS
;
828 frame_val
= tr32(MAC_MI_COM
);
829 if ((frame_val
& MI_COM_BUSY
) == 0) {
831 frame_val
= tr32(MAC_MI_COM
);
841 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
842 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
849 static int tg3_bmcr_reset(struct tg3
*tp
)
854 /* OK, reset it, and poll the BMCR_RESET bit until it
855 * clears or we time out.
857 phy_control
= BMCR_RESET
;
858 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
864 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
868 if ((phy_control
& BMCR_RESET
) == 0) {
880 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
882 struct tg3
*tp
= bp
->priv
;
885 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
888 if (tg3_readphy(tp
, reg
, &val
))
894 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
896 struct tg3
*tp
= bp
->priv
;
898 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
901 if (tg3_writephy(tp
, reg
, val
))
907 static int tg3_mdio_reset(struct mii_bus
*bp
)
912 static void tg3_mdio_config_5785(struct tg3
*tp
)
915 struct phy_device
*phydev
;
917 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
918 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
919 case TG3_PHY_ID_BCM50610
:
920 val
= MAC_PHYCFG2_50610_LED_MODES
;
922 case TG3_PHY_ID_BCMAC131
:
923 val
= MAC_PHYCFG2_AC131_LED_MODES
;
925 case TG3_PHY_ID_RTL8211C
:
926 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
928 case TG3_PHY_ID_RTL8201E
:
929 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
935 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
936 tw32(MAC_PHYCFG2
, val
);
938 val
= tr32(MAC_PHYCFG1
);
939 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
940 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
941 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
942 tw32(MAC_PHYCFG1
, val
);
947 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
948 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
949 MAC_PHYCFG2_FMODE_MASK_MASK
|
950 MAC_PHYCFG2_GMODE_MASK_MASK
|
951 MAC_PHYCFG2_ACT_MASK_MASK
|
952 MAC_PHYCFG2_QUAL_MASK_MASK
|
953 MAC_PHYCFG2_INBAND_ENABLE
;
955 tw32(MAC_PHYCFG2
, val
);
957 val
= tr32(MAC_PHYCFG1
);
958 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
959 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
960 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
961 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
962 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
963 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
964 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
966 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
967 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
968 tw32(MAC_PHYCFG1
, val
);
970 val
= tr32(MAC_EXT_RGMII_MODE
);
971 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
972 MAC_RGMII_MODE_RX_QUALITY
|
973 MAC_RGMII_MODE_RX_ACTIVITY
|
974 MAC_RGMII_MODE_RX_ENG_DET
|
975 MAC_RGMII_MODE_TX_ENABLE
|
976 MAC_RGMII_MODE_TX_LOWPWR
|
977 MAC_RGMII_MODE_TX_RESET
);
978 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
979 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
980 val
|= MAC_RGMII_MODE_RX_INT_B
|
981 MAC_RGMII_MODE_RX_QUALITY
|
982 MAC_RGMII_MODE_RX_ACTIVITY
|
983 MAC_RGMII_MODE_RX_ENG_DET
;
984 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
985 val
|= MAC_RGMII_MODE_TX_ENABLE
|
986 MAC_RGMII_MODE_TX_LOWPWR
|
987 MAC_RGMII_MODE_TX_RESET
;
989 tw32(MAC_EXT_RGMII_MODE
, val
);
992 static void tg3_mdio_start(struct tg3
*tp
)
994 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
995 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
996 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
997 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
1000 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1001 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1004 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
1005 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1006 tg3_mdio_config_5785(tp
);
1009 static void tg3_mdio_stop(struct tg3
*tp
)
1011 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1012 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
1013 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_PAUSED
;
1014 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
1018 static int tg3_mdio_init(struct tg3
*tp
)
1022 struct phy_device
*phydev
;
1026 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1027 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1030 tp
->mdio_bus
= mdiobus_alloc();
1031 if (tp
->mdio_bus
== NULL
)
1034 tp
->mdio_bus
->name
= "tg3 mdio bus";
1035 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1036 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1037 tp
->mdio_bus
->priv
= tp
;
1038 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1039 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1040 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1041 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1042 tp
->mdio_bus
->phy_mask
= ~(1 << PHY_ADDR
);
1043 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1045 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1046 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1048 /* The bus registration will look for all the PHYs on the mdio bus.
1049 * Unfortunately, it does not ensure the PHY is powered up before
1050 * accessing the PHY ID registers. A chip reset is the
1051 * quickest way to bring the device back to an operational state..
1053 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1056 i
= mdiobus_register(tp
->mdio_bus
);
1058 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1060 mdiobus_free(tp
->mdio_bus
);
1064 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1066 if (!phydev
|| !phydev
->drv
) {
1067 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1068 mdiobus_unregister(tp
->mdio_bus
);
1069 mdiobus_free(tp
->mdio_bus
);
1073 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1074 case TG3_PHY_ID_BCM57780
:
1075 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1077 case TG3_PHY_ID_BCM50610
:
1078 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1079 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1080 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1081 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1082 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1083 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1085 case TG3_PHY_ID_RTL8211C
:
1086 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1088 case TG3_PHY_ID_RTL8201E
:
1089 case TG3_PHY_ID_BCMAC131
:
1090 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1091 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1095 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1097 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1098 tg3_mdio_config_5785(tp
);
1103 static void tg3_mdio_fini(struct tg3
*tp
)
1105 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1106 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1107 mdiobus_unregister(tp
->mdio_bus
);
1108 mdiobus_free(tp
->mdio_bus
);
1109 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
1113 /* tp->lock is held. */
1114 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1118 val
= tr32(GRC_RX_CPU_EVENT
);
1119 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1120 tw32_f(GRC_RX_CPU_EVENT
, val
);
1122 tp
->last_event_jiffies
= jiffies
;
1125 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1127 /* tp->lock is held. */
1128 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1131 unsigned int delay_cnt
;
1134 /* If enough time has passed, no wait is necessary. */
1135 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1136 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1138 if (time_remain
< 0)
1141 /* Check if we can shorten the wait time. */
1142 delay_cnt
= jiffies_to_usecs(time_remain
);
1143 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1144 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1145 delay_cnt
= (delay_cnt
>> 3) + 1;
1147 for (i
= 0; i
< delay_cnt
; i
++) {
1148 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1154 /* tp->lock is held. */
1155 static void tg3_ump_link_report(struct tg3
*tp
)
1160 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1161 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1164 tg3_wait_for_event_ack(tp
);
1166 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1168 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1171 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1173 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1174 val
|= (reg
& 0xffff);
1175 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1178 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1180 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1181 val
|= (reg
& 0xffff);
1182 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1185 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1186 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1188 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1189 val
|= (reg
& 0xffff);
1191 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1193 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1197 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1199 tg3_generate_fw_event(tp
);
1202 static void tg3_link_report(struct tg3
*tp
)
1204 if (!netif_carrier_ok(tp
->dev
)) {
1205 if (netif_msg_link(tp
))
1206 printk(KERN_INFO PFX
"%s: Link is down.\n",
1208 tg3_ump_link_report(tp
);
1209 } else if (netif_msg_link(tp
)) {
1210 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1212 (tp
->link_config
.active_speed
== SPEED_1000
?
1214 (tp
->link_config
.active_speed
== SPEED_100
?
1216 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1219 printk(KERN_INFO PFX
1220 "%s: Flow control is %s for TX and %s for RX.\n",
1222 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1224 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1226 tg3_ump_link_report(tp
);
1230 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1234 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1235 miireg
= ADVERTISE_PAUSE_CAP
;
1236 else if (flow_ctrl
& FLOW_CTRL_TX
)
1237 miireg
= ADVERTISE_PAUSE_ASYM
;
1238 else if (flow_ctrl
& FLOW_CTRL_RX
)
1239 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1246 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1250 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1251 miireg
= ADVERTISE_1000XPAUSE
;
1252 else if (flow_ctrl
& FLOW_CTRL_TX
)
1253 miireg
= ADVERTISE_1000XPSE_ASYM
;
1254 else if (flow_ctrl
& FLOW_CTRL_RX
)
1255 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1262 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1266 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1267 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1268 if (rmtadv
& LPA_1000XPAUSE
)
1269 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1270 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1273 if (rmtadv
& LPA_1000XPAUSE
)
1274 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1276 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1277 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1284 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1288 u32 old_rx_mode
= tp
->rx_mode
;
1289 u32 old_tx_mode
= tp
->tx_mode
;
1291 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1292 autoneg
= tp
->mdio_bus
->phy_map
[PHY_ADDR
]->autoneg
;
1294 autoneg
= tp
->link_config
.autoneg
;
1296 if (autoneg
== AUTONEG_ENABLE
&&
1297 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1298 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1299 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1301 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1303 flowctrl
= tp
->link_config
.flowctrl
;
1305 tp
->link_config
.active_flowctrl
= flowctrl
;
1307 if (flowctrl
& FLOW_CTRL_RX
)
1308 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1310 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1312 if (old_rx_mode
!= tp
->rx_mode
)
1313 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1315 if (flowctrl
& FLOW_CTRL_TX
)
1316 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1318 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1320 if (old_tx_mode
!= tp
->tx_mode
)
1321 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1324 static void tg3_adjust_link(struct net_device
*dev
)
1326 u8 oldflowctrl
, linkmesg
= 0;
1327 u32 mac_mode
, lcl_adv
, rmt_adv
;
1328 struct tg3
*tp
= netdev_priv(dev
);
1329 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1331 spin_lock(&tp
->lock
);
1333 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1334 MAC_MODE_HALF_DUPLEX
);
1336 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1342 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1343 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1345 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1347 if (phydev
->duplex
== DUPLEX_HALF
)
1348 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1350 lcl_adv
= tg3_advert_flowctrl_1000T(
1351 tp
->link_config
.flowctrl
);
1354 rmt_adv
= LPA_PAUSE_CAP
;
1355 if (phydev
->asym_pause
)
1356 rmt_adv
|= LPA_PAUSE_ASYM
;
1359 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1361 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1363 if (mac_mode
!= tp
->mac_mode
) {
1364 tp
->mac_mode
= mac_mode
;
1365 tw32_f(MAC_MODE
, tp
->mac_mode
);
1369 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1370 if (phydev
->speed
== SPEED_10
)
1372 MAC_MI_STAT_10MBPS_MODE
|
1373 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1375 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1378 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1379 tw32(MAC_TX_LENGTHS
,
1380 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1381 (6 << TX_LENGTHS_IPG_SHIFT
) |
1382 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1384 tw32(MAC_TX_LENGTHS
,
1385 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1386 (6 << TX_LENGTHS_IPG_SHIFT
) |
1387 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1389 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1390 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1391 phydev
->speed
!= tp
->link_config
.active_speed
||
1392 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1393 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1396 tp
->link_config
.active_speed
= phydev
->speed
;
1397 tp
->link_config
.active_duplex
= phydev
->duplex
;
1399 spin_unlock(&tp
->lock
);
1402 tg3_link_report(tp
);
1405 static int tg3_phy_init(struct tg3
*tp
)
1407 struct phy_device
*phydev
;
1409 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1412 /* Bring the PHY back to a known state. */
1415 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1417 /* Attach the MAC to the PHY. */
1418 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1419 phydev
->dev_flags
, phydev
->interface
);
1420 if (IS_ERR(phydev
)) {
1421 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1422 return PTR_ERR(phydev
);
1425 /* Mask with MAC supported features. */
1426 switch (phydev
->interface
) {
1427 case PHY_INTERFACE_MODE_GMII
:
1428 case PHY_INTERFACE_MODE_RGMII
:
1429 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1430 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1432 SUPPORTED_Asym_Pause
);
1436 case PHY_INTERFACE_MODE_MII
:
1437 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1439 SUPPORTED_Asym_Pause
);
1442 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1446 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1448 phydev
->advertising
= phydev
->supported
;
1453 static void tg3_phy_start(struct tg3
*tp
)
1455 struct phy_device
*phydev
;
1457 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1460 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1462 if (tp
->link_config
.phy_is_low_power
) {
1463 tp
->link_config
.phy_is_low_power
= 0;
1464 phydev
->speed
= tp
->link_config
.orig_speed
;
1465 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1466 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1467 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1472 phy_start_aneg(phydev
);
1475 static void tg3_phy_stop(struct tg3
*tp
)
1477 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1480 phy_stop(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1483 static void tg3_phy_fini(struct tg3
*tp
)
1485 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1486 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1487 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1491 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1493 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1494 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1497 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1501 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1504 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1505 phytest
| MII_TG3_FET_SHADOW_EN
);
1506 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1508 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1510 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1511 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1513 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1517 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1521 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
1524 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1525 tg3_phy_fet_toggle_apd(tp
, enable
);
1529 reg
= MII_TG3_MISC_SHDW_WREN
|
1530 MII_TG3_MISC_SHDW_SCR5_SEL
|
1531 MII_TG3_MISC_SHDW_SCR5_LPED
|
1532 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1533 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1534 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1535 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1536 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1538 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1541 reg
= MII_TG3_MISC_SHDW_WREN
|
1542 MII_TG3_MISC_SHDW_APD_SEL
|
1543 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1545 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1547 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1550 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1554 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1555 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1558 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1561 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1562 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1564 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1565 ephy
| MII_TG3_FET_SHADOW_EN
);
1566 if (!tg3_readphy(tp
, reg
, &phy
)) {
1568 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1570 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1571 tg3_writephy(tp
, reg
, phy
);
1573 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1576 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1577 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1578 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1579 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1581 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1583 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1584 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1585 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1590 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1594 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1597 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1598 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1599 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1600 (val
| (1 << 15) | (1 << 4)));
1603 static void tg3_phy_apply_otp(struct tg3
*tp
)
1612 /* Enable SM_DSP clock and tx 6dB coding. */
1613 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1614 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1615 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1616 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1618 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1619 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1620 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1622 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1623 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1624 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1626 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1627 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1628 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1630 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1631 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1633 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1634 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1636 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1637 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1638 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1640 /* Turn off SM_DSP clock. */
1641 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1642 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1643 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1646 static int tg3_wait_macro_done(struct tg3
*tp
)
1653 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1654 if ((tmp32
& 0x1000) == 0)
1664 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1666 static const u32 test_pat
[4][6] = {
1667 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1668 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1669 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1670 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1674 for (chan
= 0; chan
< 4; chan
++) {
1677 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1678 (chan
* 0x2000) | 0x0200);
1679 tg3_writephy(tp
, 0x16, 0x0002);
1681 for (i
= 0; i
< 6; i
++)
1682 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1685 tg3_writephy(tp
, 0x16, 0x0202);
1686 if (tg3_wait_macro_done(tp
)) {
1691 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1692 (chan
* 0x2000) | 0x0200);
1693 tg3_writephy(tp
, 0x16, 0x0082);
1694 if (tg3_wait_macro_done(tp
)) {
1699 tg3_writephy(tp
, 0x16, 0x0802);
1700 if (tg3_wait_macro_done(tp
)) {
1705 for (i
= 0; i
< 6; i
+= 2) {
1708 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1709 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1710 tg3_wait_macro_done(tp
)) {
1716 if (low
!= test_pat
[chan
][i
] ||
1717 high
!= test_pat
[chan
][i
+1]) {
1718 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1719 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1720 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1730 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1734 for (chan
= 0; chan
< 4; chan
++) {
1737 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1738 (chan
* 0x2000) | 0x0200);
1739 tg3_writephy(tp
, 0x16, 0x0002);
1740 for (i
= 0; i
< 6; i
++)
1741 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1742 tg3_writephy(tp
, 0x16, 0x0202);
1743 if (tg3_wait_macro_done(tp
))
1750 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1752 u32 reg32
, phy9_orig
;
1753 int retries
, do_phy_reset
, err
;
1759 err
= tg3_bmcr_reset(tp
);
1765 /* Disable transmitter and interrupt. */
1766 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1770 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1772 /* Set full-duplex, 1000 mbps. */
1773 tg3_writephy(tp
, MII_BMCR
,
1774 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1776 /* Set to master mode. */
1777 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1780 tg3_writephy(tp
, MII_TG3_CTRL
,
1781 (MII_TG3_CTRL_AS_MASTER
|
1782 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1784 /* Enable SM_DSP_CLOCK and 6dB. */
1785 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1787 /* Block the PHY control access. */
1788 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1789 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1791 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1794 } while (--retries
);
1796 err
= tg3_phy_reset_chanpat(tp
);
1800 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1801 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1803 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1804 tg3_writephy(tp
, 0x16, 0x0000);
1806 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1807 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1808 /* Set Extended packet length bit for jumbo frames */
1809 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1812 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1815 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1817 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1819 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1826 /* This will reset the tigon3 PHY if there is no valid
1827 * link unless the FORCE argument is non-zero.
1829 static int tg3_phy_reset(struct tg3
*tp
)
1835 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1838 val
= tr32(GRC_MISC_CFG
);
1839 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1842 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1843 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1847 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1848 netif_carrier_off(tp
->dev
);
1849 tg3_link_report(tp
);
1852 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1853 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1854 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1855 err
= tg3_phy_reset_5703_4_5(tp
);
1862 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1863 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1864 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1865 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1867 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1870 err
= tg3_bmcr_reset(tp
);
1874 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1877 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1878 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1880 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1883 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1884 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1887 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1888 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1889 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1890 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1892 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1896 tg3_phy_apply_otp(tp
);
1898 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1899 tg3_phy_toggle_apd(tp
, true);
1901 tg3_phy_toggle_apd(tp
, false);
1904 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1905 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1906 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1907 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1908 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1909 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1910 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1912 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1913 tg3_writephy(tp
, 0x1c, 0x8d68);
1914 tg3_writephy(tp
, 0x1c, 0x8d68);
1916 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1917 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1918 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1919 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1920 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1921 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1922 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1923 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1924 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1926 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1927 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1928 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1929 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1930 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1931 tg3_writephy(tp
, MII_TG3_TEST1
,
1932 MII_TG3_TEST1_TRIM_EN
| 0x4);
1934 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1935 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1937 /* Set Extended packet length bit (bit 14) on all chips that */
1938 /* support jumbo frames */
1939 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1940 /* Cannot do read-modify-write on 5401 */
1941 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1942 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1945 /* Set bit 14 with read-modify-write to preserve other bits */
1946 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1947 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1948 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1951 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1952 * jumbo frames transmission.
1954 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1957 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1958 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1959 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1962 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1963 /* adjust output voltage */
1964 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
1967 tg3_phy_toggle_automdix(tp
, 1);
1968 tg3_phy_set_wirespeed(tp
);
1972 static void tg3_frob_aux_power(struct tg3
*tp
)
1974 struct tg3
*tp_peer
= tp
;
1976 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
1979 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
1980 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
1981 struct net_device
*dev_peer
;
1983 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
1984 /* remove_one() may have been run on the peer. */
1988 tp_peer
= netdev_priv(dev_peer
);
1991 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1992 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
1993 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1994 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
1995 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1996 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1997 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1998 (GRC_LCLCTRL_GPIO_OE0
|
1999 GRC_LCLCTRL_GPIO_OE1
|
2000 GRC_LCLCTRL_GPIO_OE2
|
2001 GRC_LCLCTRL_GPIO_OUTPUT0
|
2002 GRC_LCLCTRL_GPIO_OUTPUT1
),
2004 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2005 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2006 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2007 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2008 GRC_LCLCTRL_GPIO_OE1
|
2009 GRC_LCLCTRL_GPIO_OE2
|
2010 GRC_LCLCTRL_GPIO_OUTPUT0
|
2011 GRC_LCLCTRL_GPIO_OUTPUT1
|
2013 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2015 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2016 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2018 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2019 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2022 u32 grc_local_ctrl
= 0;
2024 if (tp_peer
!= tp
&&
2025 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2028 /* Workaround to prevent overdrawing Amps. */
2029 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2031 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2032 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2033 grc_local_ctrl
, 100);
2036 /* On 5753 and variants, GPIO2 cannot be used. */
2037 no_gpio2
= tp
->nic_sram_data_cfg
&
2038 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2040 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2041 GRC_LCLCTRL_GPIO_OE1
|
2042 GRC_LCLCTRL_GPIO_OE2
|
2043 GRC_LCLCTRL_GPIO_OUTPUT1
|
2044 GRC_LCLCTRL_GPIO_OUTPUT2
;
2046 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2047 GRC_LCLCTRL_GPIO_OUTPUT2
);
2049 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2050 grc_local_ctrl
, 100);
2052 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2054 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2055 grc_local_ctrl
, 100);
2058 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2059 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2060 grc_local_ctrl
, 100);
2064 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2065 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2066 if (tp_peer
!= tp
&&
2067 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2070 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2071 (GRC_LCLCTRL_GPIO_OE1
|
2072 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2074 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2075 GRC_LCLCTRL_GPIO_OE1
, 100);
2077 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2078 (GRC_LCLCTRL_GPIO_OE1
|
2079 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2084 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2086 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2088 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2089 if (speed
!= SPEED_10
)
2091 } else if (speed
== SPEED_10
)
2097 static int tg3_setup_phy(struct tg3
*, int);
2099 #define RESET_KIND_SHUTDOWN 0
2100 #define RESET_KIND_INIT 1
2101 #define RESET_KIND_SUSPEND 2
2103 static void tg3_write_sig_post_reset(struct tg3
*, int);
2104 static int tg3_halt_cpu(struct tg3
*, u32
);
2106 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2110 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2111 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2112 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2113 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2116 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2117 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2118 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2123 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2125 val
= tr32(GRC_MISC_CFG
);
2126 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2129 } else if (do_low_power
) {
2130 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2131 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2133 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2134 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2135 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2136 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2137 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2140 /* The PHY should not be powered down on some chips because
2143 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2144 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2145 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2146 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2149 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2150 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2151 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2152 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2153 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2154 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2157 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2160 /* tp->lock is held. */
2161 static int tg3_nvram_lock(struct tg3
*tp
)
2163 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2166 if (tp
->nvram_lock_cnt
== 0) {
2167 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2168 for (i
= 0; i
< 8000; i
++) {
2169 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2174 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2178 tp
->nvram_lock_cnt
++;
2183 /* tp->lock is held. */
2184 static void tg3_nvram_unlock(struct tg3
*tp
)
2186 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2187 if (tp
->nvram_lock_cnt
> 0)
2188 tp
->nvram_lock_cnt
--;
2189 if (tp
->nvram_lock_cnt
== 0)
2190 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2194 /* tp->lock is held. */
2195 static void tg3_enable_nvram_access(struct tg3
*tp
)
2197 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2198 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2199 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2201 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2205 /* tp->lock is held. */
2206 static void tg3_disable_nvram_access(struct tg3
*tp
)
2208 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2209 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2210 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2212 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2216 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2217 u32 offset
, u32
*val
)
2222 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2225 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2226 EEPROM_ADDR_DEVID_MASK
|
2228 tw32(GRC_EEPROM_ADDR
,
2230 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2231 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2232 EEPROM_ADDR_ADDR_MASK
) |
2233 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2235 for (i
= 0; i
< 1000; i
++) {
2236 tmp
= tr32(GRC_EEPROM_ADDR
);
2238 if (tmp
& EEPROM_ADDR_COMPLETE
)
2242 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2245 tmp
= tr32(GRC_EEPROM_DATA
);
2248 * The data will always be opposite the native endian
2249 * format. Perform a blind byteswap to compensate.
2256 #define NVRAM_CMD_TIMEOUT 10000
2258 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2262 tw32(NVRAM_CMD
, nvram_cmd
);
2263 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2265 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2271 if (i
== NVRAM_CMD_TIMEOUT
)
2277 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2279 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2280 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2281 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2282 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2283 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2285 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2286 ATMEL_AT45DB0X1B_PAGE_POS
) +
2287 (addr
% tp
->nvram_pagesize
);
2292 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2294 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2295 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2296 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2297 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2298 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2300 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2301 tp
->nvram_pagesize
) +
2302 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2307 /* NOTE: Data read in from NVRAM is byteswapped according to
2308 * the byteswapping settings for all other register accesses.
2309 * tg3 devices are BE devices, so on a BE machine, the data
2310 * returned will be exactly as it is seen in NVRAM. On a LE
2311 * machine, the 32-bit value will be byteswapped.
2313 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2317 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2318 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2320 offset
= tg3_nvram_phys_addr(tp
, offset
);
2322 if (offset
> NVRAM_ADDR_MSK
)
2325 ret
= tg3_nvram_lock(tp
);
2329 tg3_enable_nvram_access(tp
);
2331 tw32(NVRAM_ADDR
, offset
);
2332 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2333 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2336 *val
= tr32(NVRAM_RDDATA
);
2338 tg3_disable_nvram_access(tp
);
2340 tg3_nvram_unlock(tp
);
2345 /* Ensures NVRAM data is in bytestream format. */
2346 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2349 int res
= tg3_nvram_read(tp
, offset
, &v
);
2351 *val
= cpu_to_be32(v
);
2355 /* tp->lock is held. */
2356 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2358 u32 addr_high
, addr_low
;
2361 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2362 tp
->dev
->dev_addr
[1]);
2363 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2364 (tp
->dev
->dev_addr
[3] << 16) |
2365 (tp
->dev
->dev_addr
[4] << 8) |
2366 (tp
->dev
->dev_addr
[5] << 0));
2367 for (i
= 0; i
< 4; i
++) {
2368 if (i
== 1 && skip_mac_1
)
2370 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2371 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2374 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2375 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2376 for (i
= 0; i
< 12; i
++) {
2377 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2378 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2382 addr_high
= (tp
->dev
->dev_addr
[0] +
2383 tp
->dev
->dev_addr
[1] +
2384 tp
->dev
->dev_addr
[2] +
2385 tp
->dev
->dev_addr
[3] +
2386 tp
->dev
->dev_addr
[4] +
2387 tp
->dev
->dev_addr
[5]) &
2388 TX_BACKOFF_SEED_MASK
;
2389 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2392 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2395 bool device_should_wake
, do_low_power
;
2397 /* Make sure register accesses (indirect or otherwise)
2398 * will function correctly.
2400 pci_write_config_dword(tp
->pdev
,
2401 TG3PCI_MISC_HOST_CTRL
,
2402 tp
->misc_host_ctrl
);
2406 pci_enable_wake(tp
->pdev
, state
, false);
2407 pci_set_power_state(tp
->pdev
, PCI_D0
);
2409 /* Switch out of Vaux if it is a NIC */
2410 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2411 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2421 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2422 tp
->dev
->name
, state
);
2426 /* Restore the CLKREQ setting. */
2427 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2430 pci_read_config_word(tp
->pdev
,
2431 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2433 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2434 pci_write_config_word(tp
->pdev
,
2435 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2439 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2440 tw32(TG3PCI_MISC_HOST_CTRL
,
2441 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2443 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2444 device_may_wakeup(&tp
->pdev
->dev
) &&
2445 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2447 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2448 do_low_power
= false;
2449 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2450 !tp
->link_config
.phy_is_low_power
) {
2451 struct phy_device
*phydev
;
2452 u32 phyid
, advertising
;
2454 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
2456 tp
->link_config
.phy_is_low_power
= 1;
2458 tp
->link_config
.orig_speed
= phydev
->speed
;
2459 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2460 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2461 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2463 advertising
= ADVERTISED_TP
|
2465 ADVERTISED_Autoneg
|
2466 ADVERTISED_10baseT_Half
;
2468 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2469 device_should_wake
) {
2470 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2472 ADVERTISED_100baseT_Half
|
2473 ADVERTISED_100baseT_Full
|
2474 ADVERTISED_10baseT_Full
;
2476 advertising
|= ADVERTISED_10baseT_Full
;
2479 phydev
->advertising
= advertising
;
2481 phy_start_aneg(phydev
);
2483 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2484 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2485 phyid
&= TG3_PHY_OUI_MASK
;
2486 if (phyid
== TG3_PHY_OUI_1
||
2487 phyid
== TG3_PHY_OUI_2
||
2488 phyid
== TG3_PHY_OUI_3
)
2489 do_low_power
= true;
2493 do_low_power
= true;
2495 if (tp
->link_config
.phy_is_low_power
== 0) {
2496 tp
->link_config
.phy_is_low_power
= 1;
2497 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2498 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2499 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2502 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2503 tp
->link_config
.speed
= SPEED_10
;
2504 tp
->link_config
.duplex
= DUPLEX_HALF
;
2505 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2506 tg3_setup_phy(tp
, 0);
2510 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2513 val
= tr32(GRC_VCPU_EXT_CTRL
);
2514 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2515 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2519 for (i
= 0; i
< 200; i
++) {
2520 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2521 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2526 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2527 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2528 WOL_DRV_STATE_SHUTDOWN
|
2532 if (device_should_wake
) {
2535 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2537 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2541 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2542 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2544 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2546 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2547 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2549 u32 speed
= (tp
->tg3_flags
&
2550 TG3_FLAG_WOL_SPEED_100MB
) ?
2551 SPEED_100
: SPEED_10
;
2552 if (tg3_5700_link_polarity(tp
, speed
))
2553 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2555 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2558 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2561 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2562 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2564 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2565 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2566 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2567 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2568 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2569 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2571 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2572 mac_mode
|= tp
->mac_mode
&
2573 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2574 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2575 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2578 tw32_f(MAC_MODE
, mac_mode
);
2581 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2585 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2586 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2587 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2590 base_val
= tp
->pci_clock_ctrl
;
2591 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2592 CLOCK_CTRL_TXCLK_DISABLE
);
2594 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2595 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2596 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2597 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2598 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2600 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2601 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2602 u32 newbits1
, newbits2
;
2604 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2605 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2606 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2607 CLOCK_CTRL_TXCLK_DISABLE
|
2609 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2610 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2611 newbits1
= CLOCK_CTRL_625_CORE
;
2612 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2614 newbits1
= CLOCK_CTRL_ALTCLK
;
2615 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2618 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2621 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2624 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2627 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2628 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2629 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2630 CLOCK_CTRL_TXCLK_DISABLE
|
2631 CLOCK_CTRL_44MHZ_CORE
);
2633 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2636 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2637 tp
->pci_clock_ctrl
| newbits3
, 40);
2641 if (!(device_should_wake
) &&
2642 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2643 tg3_power_down_phy(tp
, do_low_power
);
2645 tg3_frob_aux_power(tp
);
2647 /* Workaround for unstable PLL clock */
2648 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2649 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2650 u32 val
= tr32(0x7d00);
2652 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2654 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2657 err
= tg3_nvram_lock(tp
);
2658 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2660 tg3_nvram_unlock(tp
);
2664 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2666 if (device_should_wake
)
2667 pci_enable_wake(tp
->pdev
, state
, true);
2669 /* Finally, set the new power state. */
2670 pci_set_power_state(tp
->pdev
, state
);
2675 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2677 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2678 case MII_TG3_AUX_STAT_10HALF
:
2680 *duplex
= DUPLEX_HALF
;
2683 case MII_TG3_AUX_STAT_10FULL
:
2685 *duplex
= DUPLEX_FULL
;
2688 case MII_TG3_AUX_STAT_100HALF
:
2690 *duplex
= DUPLEX_HALF
;
2693 case MII_TG3_AUX_STAT_100FULL
:
2695 *duplex
= DUPLEX_FULL
;
2698 case MII_TG3_AUX_STAT_1000HALF
:
2699 *speed
= SPEED_1000
;
2700 *duplex
= DUPLEX_HALF
;
2703 case MII_TG3_AUX_STAT_1000FULL
:
2704 *speed
= SPEED_1000
;
2705 *duplex
= DUPLEX_FULL
;
2709 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2710 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2712 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2716 *speed
= SPEED_INVALID
;
2717 *duplex
= DUPLEX_INVALID
;
2722 static void tg3_phy_copper_begin(struct tg3
*tp
)
2727 if (tp
->link_config
.phy_is_low_power
) {
2728 /* Entering low power mode. Disable gigabit and
2729 * 100baseT advertisements.
2731 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2733 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2734 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2735 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2736 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2738 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2739 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2740 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2741 tp
->link_config
.advertising
&=
2742 ~(ADVERTISED_1000baseT_Half
|
2743 ADVERTISED_1000baseT_Full
);
2745 new_adv
= ADVERTISE_CSMA
;
2746 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2747 new_adv
|= ADVERTISE_10HALF
;
2748 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2749 new_adv
|= ADVERTISE_10FULL
;
2750 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2751 new_adv
|= ADVERTISE_100HALF
;
2752 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2753 new_adv
|= ADVERTISE_100FULL
;
2755 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2757 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2759 if (tp
->link_config
.advertising
&
2760 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2762 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2763 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2764 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2765 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2766 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2767 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2768 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2769 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2770 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2771 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2773 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2776 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2777 new_adv
|= ADVERTISE_CSMA
;
2779 /* Asking for a specific link mode. */
2780 if (tp
->link_config
.speed
== SPEED_1000
) {
2781 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2783 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2784 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2786 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2787 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2788 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2789 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2790 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2792 if (tp
->link_config
.speed
== SPEED_100
) {
2793 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2794 new_adv
|= ADVERTISE_100FULL
;
2796 new_adv
|= ADVERTISE_100HALF
;
2798 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2799 new_adv
|= ADVERTISE_10FULL
;
2801 new_adv
|= ADVERTISE_10HALF
;
2803 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2808 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2811 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2812 tp
->link_config
.speed
!= SPEED_INVALID
) {
2813 u32 bmcr
, orig_bmcr
;
2815 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2816 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2819 switch (tp
->link_config
.speed
) {
2825 bmcr
|= BMCR_SPEED100
;
2829 bmcr
|= TG3_BMCR_SPEED1000
;
2833 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2834 bmcr
|= BMCR_FULLDPLX
;
2836 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2837 (bmcr
!= orig_bmcr
)) {
2838 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2839 for (i
= 0; i
< 1500; i
++) {
2843 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2844 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2846 if (!(tmp
& BMSR_LSTATUS
)) {
2851 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2855 tg3_writephy(tp
, MII_BMCR
,
2856 BMCR_ANENABLE
| BMCR_ANRESTART
);
2860 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2864 /* Turn off tap power management. */
2865 /* Set Extended packet length bit */
2866 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2868 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2869 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2871 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2872 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2874 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2875 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2877 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2878 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2880 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2881 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2888 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2890 u32 adv_reg
, all_mask
= 0;
2892 if (mask
& ADVERTISED_10baseT_Half
)
2893 all_mask
|= ADVERTISE_10HALF
;
2894 if (mask
& ADVERTISED_10baseT_Full
)
2895 all_mask
|= ADVERTISE_10FULL
;
2896 if (mask
& ADVERTISED_100baseT_Half
)
2897 all_mask
|= ADVERTISE_100HALF
;
2898 if (mask
& ADVERTISED_100baseT_Full
)
2899 all_mask
|= ADVERTISE_100FULL
;
2901 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2904 if ((adv_reg
& all_mask
) != all_mask
)
2906 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2910 if (mask
& ADVERTISED_1000baseT_Half
)
2911 all_mask
|= ADVERTISE_1000HALF
;
2912 if (mask
& ADVERTISED_1000baseT_Full
)
2913 all_mask
|= ADVERTISE_1000FULL
;
2915 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2918 if ((tg3_ctrl
& all_mask
) != all_mask
)
2924 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2928 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2931 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2932 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2934 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2935 if (curadv
!= reqadv
)
2938 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2939 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2941 /* Reprogram the advertisement register, even if it
2942 * does not affect the current link. If the link
2943 * gets renegotiated in the future, we can save an
2944 * additional renegotiation cycle by advertising
2945 * it correctly in the first place.
2947 if (curadv
!= reqadv
) {
2948 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
2949 ADVERTISE_PAUSE_ASYM
);
2950 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
2957 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
2959 int current_link_up
;
2961 u32 lcl_adv
, rmt_adv
;
2969 (MAC_STATUS_SYNC_CHANGED
|
2970 MAC_STATUS_CFG_CHANGED
|
2971 MAC_STATUS_MI_COMPLETION
|
2972 MAC_STATUS_LNKSTATE_CHANGED
));
2975 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
2977 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
2981 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
2983 /* Some third-party PHYs need to be reset on link going
2986 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2987 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2988 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
2989 netif_carrier_ok(tp
->dev
)) {
2990 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2991 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2992 !(bmsr
& BMSR_LSTATUS
))
2998 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
2999 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3000 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
3001 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
3004 if (!(bmsr
& BMSR_LSTATUS
)) {
3005 err
= tg3_init_5401phy_dsp(tp
);
3009 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3010 for (i
= 0; i
< 1000; i
++) {
3012 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3013 (bmsr
& BMSR_LSTATUS
)) {
3019 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
3020 !(bmsr
& BMSR_LSTATUS
) &&
3021 tp
->link_config
.active_speed
== SPEED_1000
) {
3022 err
= tg3_phy_reset(tp
);
3024 err
= tg3_init_5401phy_dsp(tp
);
3029 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3030 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3031 /* 5701 {A0,B0} CRC bug workaround */
3032 tg3_writephy(tp
, 0x15, 0x0a75);
3033 tg3_writephy(tp
, 0x1c, 0x8c68);
3034 tg3_writephy(tp
, 0x1c, 0x8d68);
3035 tg3_writephy(tp
, 0x1c, 0x8c68);
3038 /* Clear pending interrupts... */
3039 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3040 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3042 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3043 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3044 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3045 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3047 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3048 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3049 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3050 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3051 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3053 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3056 current_link_up
= 0;
3057 current_speed
= SPEED_INVALID
;
3058 current_duplex
= DUPLEX_INVALID
;
3060 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3063 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3064 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3065 if (!(val
& (1 << 10))) {
3067 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3073 for (i
= 0; i
< 100; i
++) {
3074 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3075 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3076 (bmsr
& BMSR_LSTATUS
))
3081 if (bmsr
& BMSR_LSTATUS
) {
3084 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3085 for (i
= 0; i
< 2000; i
++) {
3087 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3092 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3097 for (i
= 0; i
< 200; i
++) {
3098 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3099 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3101 if (bmcr
&& bmcr
!= 0x7fff)
3109 tp
->link_config
.active_speed
= current_speed
;
3110 tp
->link_config
.active_duplex
= current_duplex
;
3112 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3113 if ((bmcr
& BMCR_ANENABLE
) &&
3114 tg3_copper_is_advertising_all(tp
,
3115 tp
->link_config
.advertising
)) {
3116 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3118 current_link_up
= 1;
3121 if (!(bmcr
& BMCR_ANENABLE
) &&
3122 tp
->link_config
.speed
== current_speed
&&
3123 tp
->link_config
.duplex
== current_duplex
&&
3124 tp
->link_config
.flowctrl
==
3125 tp
->link_config
.active_flowctrl
) {
3126 current_link_up
= 1;
3130 if (current_link_up
== 1 &&
3131 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3132 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3136 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3139 tg3_phy_copper_begin(tp
);
3141 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3142 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3143 (tmp
& BMSR_LSTATUS
))
3144 current_link_up
= 1;
3147 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3148 if (current_link_up
== 1) {
3149 if (tp
->link_config
.active_speed
== SPEED_100
||
3150 tp
->link_config
.active_speed
== SPEED_10
)
3151 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3153 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3154 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3155 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3157 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3159 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3160 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3161 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3163 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3164 if (current_link_up
== 1 &&
3165 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3166 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3168 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3171 /* ??? Without this setting Netgear GA302T PHY does not
3172 * ??? send/receive packets...
3174 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
3175 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3176 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3177 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3181 tw32_f(MAC_MODE
, tp
->mac_mode
);
3184 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3185 /* Polled via timer. */
3186 tw32_f(MAC_EVENT
, 0);
3188 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3192 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3193 current_link_up
== 1 &&
3194 tp
->link_config
.active_speed
== SPEED_1000
&&
3195 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3196 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3199 (MAC_STATUS_SYNC_CHANGED
|
3200 MAC_STATUS_CFG_CHANGED
));
3203 NIC_SRAM_FIRMWARE_MBOX
,
3204 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3207 /* Prevent send BD corruption. */
3208 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3209 u16 oldlnkctl
, newlnkctl
;
3211 pci_read_config_word(tp
->pdev
,
3212 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3214 if (tp
->link_config
.active_speed
== SPEED_100
||
3215 tp
->link_config
.active_speed
== SPEED_10
)
3216 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3218 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3219 if (newlnkctl
!= oldlnkctl
)
3220 pci_write_config_word(tp
->pdev
,
3221 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3223 } else if (tp
->tg3_flags3
& TG3_FLG3_TOGGLE_10_100_L1PLLPD
) {
3224 u32 newreg
, oldreg
= tr32(TG3_PCIE_LNKCTL
);
3225 if (tp
->link_config
.active_speed
== SPEED_100
||
3226 tp
->link_config
.active_speed
== SPEED_10
)
3227 newreg
= oldreg
& ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
3229 newreg
= oldreg
| TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
3230 if (newreg
!= oldreg
)
3231 tw32(TG3_PCIE_LNKCTL
, newreg
);
3234 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3235 if (current_link_up
)
3236 netif_carrier_on(tp
->dev
);
3238 netif_carrier_off(tp
->dev
);
3239 tg3_link_report(tp
);
3245 struct tg3_fiber_aneginfo
{
3247 #define ANEG_STATE_UNKNOWN 0
3248 #define ANEG_STATE_AN_ENABLE 1
3249 #define ANEG_STATE_RESTART_INIT 2
3250 #define ANEG_STATE_RESTART 3
3251 #define ANEG_STATE_DISABLE_LINK_OK 4
3252 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3253 #define ANEG_STATE_ABILITY_DETECT 6
3254 #define ANEG_STATE_ACK_DETECT_INIT 7
3255 #define ANEG_STATE_ACK_DETECT 8
3256 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3257 #define ANEG_STATE_COMPLETE_ACK 10
3258 #define ANEG_STATE_IDLE_DETECT_INIT 11
3259 #define ANEG_STATE_IDLE_DETECT 12
3260 #define ANEG_STATE_LINK_OK 13
3261 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3262 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3265 #define MR_AN_ENABLE 0x00000001
3266 #define MR_RESTART_AN 0x00000002
3267 #define MR_AN_COMPLETE 0x00000004
3268 #define MR_PAGE_RX 0x00000008
3269 #define MR_NP_LOADED 0x00000010
3270 #define MR_TOGGLE_TX 0x00000020
3271 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3272 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3273 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3274 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3275 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3276 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3277 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3278 #define MR_TOGGLE_RX 0x00002000
3279 #define MR_NP_RX 0x00004000
3281 #define MR_LINK_OK 0x80000000
3283 unsigned long link_time
, cur_time
;
3285 u32 ability_match_cfg
;
3286 int ability_match_count
;
3288 char ability_match
, idle_match
, ack_match
;
3290 u32 txconfig
, rxconfig
;
3291 #define ANEG_CFG_NP 0x00000080
3292 #define ANEG_CFG_ACK 0x00000040
3293 #define ANEG_CFG_RF2 0x00000020
3294 #define ANEG_CFG_RF1 0x00000010
3295 #define ANEG_CFG_PS2 0x00000001
3296 #define ANEG_CFG_PS1 0x00008000
3297 #define ANEG_CFG_HD 0x00004000
3298 #define ANEG_CFG_FD 0x00002000
3299 #define ANEG_CFG_INVAL 0x00001f06
3304 #define ANEG_TIMER_ENAB 2
3305 #define ANEG_FAILED -1
3307 #define ANEG_STATE_SETTLE_TIME 10000
3309 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3310 struct tg3_fiber_aneginfo
*ap
)
3313 unsigned long delta
;
3317 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3321 ap
->ability_match_cfg
= 0;
3322 ap
->ability_match_count
= 0;
3323 ap
->ability_match
= 0;
3329 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3330 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3332 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3333 ap
->ability_match_cfg
= rx_cfg_reg
;
3334 ap
->ability_match
= 0;
3335 ap
->ability_match_count
= 0;
3337 if (++ap
->ability_match_count
> 1) {
3338 ap
->ability_match
= 1;
3339 ap
->ability_match_cfg
= rx_cfg_reg
;
3342 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3350 ap
->ability_match_cfg
= 0;
3351 ap
->ability_match_count
= 0;
3352 ap
->ability_match
= 0;
3358 ap
->rxconfig
= rx_cfg_reg
;
3362 case ANEG_STATE_UNKNOWN
:
3363 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3364 ap
->state
= ANEG_STATE_AN_ENABLE
;
3367 case ANEG_STATE_AN_ENABLE
:
3368 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3369 if (ap
->flags
& MR_AN_ENABLE
) {
3372 ap
->ability_match_cfg
= 0;
3373 ap
->ability_match_count
= 0;
3374 ap
->ability_match
= 0;
3378 ap
->state
= ANEG_STATE_RESTART_INIT
;
3380 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3384 case ANEG_STATE_RESTART_INIT
:
3385 ap
->link_time
= ap
->cur_time
;
3386 ap
->flags
&= ~(MR_NP_LOADED
);
3388 tw32(MAC_TX_AUTO_NEG
, 0);
3389 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3390 tw32_f(MAC_MODE
, tp
->mac_mode
);
3393 ret
= ANEG_TIMER_ENAB
;
3394 ap
->state
= ANEG_STATE_RESTART
;
3397 case ANEG_STATE_RESTART
:
3398 delta
= ap
->cur_time
- ap
->link_time
;
3399 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3400 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3402 ret
= ANEG_TIMER_ENAB
;
3406 case ANEG_STATE_DISABLE_LINK_OK
:
3410 case ANEG_STATE_ABILITY_DETECT_INIT
:
3411 ap
->flags
&= ~(MR_TOGGLE_TX
);
3412 ap
->txconfig
= ANEG_CFG_FD
;
3413 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3414 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3415 ap
->txconfig
|= ANEG_CFG_PS1
;
3416 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3417 ap
->txconfig
|= ANEG_CFG_PS2
;
3418 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3419 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3420 tw32_f(MAC_MODE
, tp
->mac_mode
);
3423 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3426 case ANEG_STATE_ABILITY_DETECT
:
3427 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3428 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3432 case ANEG_STATE_ACK_DETECT_INIT
:
3433 ap
->txconfig
|= ANEG_CFG_ACK
;
3434 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3435 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3436 tw32_f(MAC_MODE
, tp
->mac_mode
);
3439 ap
->state
= ANEG_STATE_ACK_DETECT
;
3442 case ANEG_STATE_ACK_DETECT
:
3443 if (ap
->ack_match
!= 0) {
3444 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3445 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3446 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3448 ap
->state
= ANEG_STATE_AN_ENABLE
;
3450 } else if (ap
->ability_match
!= 0 &&
3451 ap
->rxconfig
== 0) {
3452 ap
->state
= ANEG_STATE_AN_ENABLE
;
3456 case ANEG_STATE_COMPLETE_ACK_INIT
:
3457 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3461 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3462 MR_LP_ADV_HALF_DUPLEX
|
3463 MR_LP_ADV_SYM_PAUSE
|
3464 MR_LP_ADV_ASYM_PAUSE
|
3465 MR_LP_ADV_REMOTE_FAULT1
|
3466 MR_LP_ADV_REMOTE_FAULT2
|
3467 MR_LP_ADV_NEXT_PAGE
|
3470 if (ap
->rxconfig
& ANEG_CFG_FD
)
3471 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3472 if (ap
->rxconfig
& ANEG_CFG_HD
)
3473 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3474 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3475 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3476 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3477 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3478 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3479 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3480 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3481 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3482 if (ap
->rxconfig
& ANEG_CFG_NP
)
3483 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3485 ap
->link_time
= ap
->cur_time
;
3487 ap
->flags
^= (MR_TOGGLE_TX
);
3488 if (ap
->rxconfig
& 0x0008)
3489 ap
->flags
|= MR_TOGGLE_RX
;
3490 if (ap
->rxconfig
& ANEG_CFG_NP
)
3491 ap
->flags
|= MR_NP_RX
;
3492 ap
->flags
|= MR_PAGE_RX
;
3494 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3495 ret
= ANEG_TIMER_ENAB
;
3498 case ANEG_STATE_COMPLETE_ACK
:
3499 if (ap
->ability_match
!= 0 &&
3500 ap
->rxconfig
== 0) {
3501 ap
->state
= ANEG_STATE_AN_ENABLE
;
3504 delta
= ap
->cur_time
- ap
->link_time
;
3505 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3506 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3507 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3509 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3510 !(ap
->flags
& MR_NP_RX
)) {
3511 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3519 case ANEG_STATE_IDLE_DETECT_INIT
:
3520 ap
->link_time
= ap
->cur_time
;
3521 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3522 tw32_f(MAC_MODE
, tp
->mac_mode
);
3525 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3526 ret
= ANEG_TIMER_ENAB
;
3529 case ANEG_STATE_IDLE_DETECT
:
3530 if (ap
->ability_match
!= 0 &&
3531 ap
->rxconfig
== 0) {
3532 ap
->state
= ANEG_STATE_AN_ENABLE
;
3535 delta
= ap
->cur_time
- ap
->link_time
;
3536 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3537 /* XXX another gem from the Broadcom driver :( */
3538 ap
->state
= ANEG_STATE_LINK_OK
;
3542 case ANEG_STATE_LINK_OK
:
3543 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3547 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3548 /* ??? unimplemented */
3551 case ANEG_STATE_NEXT_PAGE_WAIT
:
3552 /* ??? unimplemented */
3563 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3566 struct tg3_fiber_aneginfo aninfo
;
3567 int status
= ANEG_FAILED
;
3571 tw32_f(MAC_TX_AUTO_NEG
, 0);
3573 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3574 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3577 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3580 memset(&aninfo
, 0, sizeof(aninfo
));
3581 aninfo
.flags
|= MR_AN_ENABLE
;
3582 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3583 aninfo
.cur_time
= 0;
3585 while (++tick
< 195000) {
3586 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3587 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3593 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3594 tw32_f(MAC_MODE
, tp
->mac_mode
);
3597 *txflags
= aninfo
.txconfig
;
3598 *rxflags
= aninfo
.flags
;
3600 if (status
== ANEG_DONE
&&
3601 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3602 MR_LP_ADV_FULL_DUPLEX
)))
3608 static void tg3_init_bcm8002(struct tg3
*tp
)
3610 u32 mac_status
= tr32(MAC_STATUS
);
3613 /* Reset when initting first time or we have a link. */
3614 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3615 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3618 /* Set PLL lock range. */
3619 tg3_writephy(tp
, 0x16, 0x8007);
3622 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3624 /* Wait for reset to complete. */
3625 /* XXX schedule_timeout() ... */
3626 for (i
= 0; i
< 500; i
++)
3629 /* Config mode; select PMA/Ch 1 regs. */
3630 tg3_writephy(tp
, 0x10, 0x8411);
3632 /* Enable auto-lock and comdet, select txclk for tx. */
3633 tg3_writephy(tp
, 0x11, 0x0a10);
3635 tg3_writephy(tp
, 0x18, 0x00a0);
3636 tg3_writephy(tp
, 0x16, 0x41ff);
3638 /* Assert and deassert POR. */
3639 tg3_writephy(tp
, 0x13, 0x0400);
3641 tg3_writephy(tp
, 0x13, 0x0000);
3643 tg3_writephy(tp
, 0x11, 0x0a50);
3645 tg3_writephy(tp
, 0x11, 0x0a10);
3647 /* Wait for signal to stabilize */
3648 /* XXX schedule_timeout() ... */
3649 for (i
= 0; i
< 15000; i
++)
3652 /* Deselect the channel register so we can read the PHYID
3655 tg3_writephy(tp
, 0x10, 0x8011);
3658 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3661 u32 sg_dig_ctrl
, sg_dig_status
;
3662 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3663 int workaround
, port_a
;
3664 int current_link_up
;
3667 expected_sg_dig_ctrl
= 0;
3670 current_link_up
= 0;
3672 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3673 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3675 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3678 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3679 /* preserve bits 20-23 for voltage regulator */
3680 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3683 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3685 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3686 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3688 u32 val
= serdes_cfg
;
3694 tw32_f(MAC_SERDES_CFG
, val
);
3697 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3699 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3700 tg3_setup_flow_control(tp
, 0, 0);
3701 current_link_up
= 1;
3706 /* Want auto-negotiation. */
3707 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3709 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3710 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3711 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3712 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3713 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3715 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3716 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3717 tp
->serdes_counter
&&
3718 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3719 MAC_STATUS_RCVD_CFG
)) ==
3720 MAC_STATUS_PCS_SYNCED
)) {
3721 tp
->serdes_counter
--;
3722 current_link_up
= 1;
3727 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3728 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3730 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3732 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3733 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3734 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3735 MAC_STATUS_SIGNAL_DET
)) {
3736 sg_dig_status
= tr32(SG_DIG_STATUS
);
3737 mac_status
= tr32(MAC_STATUS
);
3739 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3740 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3741 u32 local_adv
= 0, remote_adv
= 0;
3743 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3744 local_adv
|= ADVERTISE_1000XPAUSE
;
3745 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3746 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3748 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3749 remote_adv
|= LPA_1000XPAUSE
;
3750 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3751 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3753 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3754 current_link_up
= 1;
3755 tp
->serdes_counter
= 0;
3756 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3757 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3758 if (tp
->serdes_counter
)
3759 tp
->serdes_counter
--;
3762 u32 val
= serdes_cfg
;
3769 tw32_f(MAC_SERDES_CFG
, val
);
3772 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3775 /* Link parallel detection - link is up */
3776 /* only if we have PCS_SYNC and not */
3777 /* receiving config code words */
3778 mac_status
= tr32(MAC_STATUS
);
3779 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3780 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3781 tg3_setup_flow_control(tp
, 0, 0);
3782 current_link_up
= 1;
3784 TG3_FLG2_PARALLEL_DETECT
;
3785 tp
->serdes_counter
=
3786 SERDES_PARALLEL_DET_TIMEOUT
;
3788 goto restart_autoneg
;
3792 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3793 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3797 return current_link_up
;
3800 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3802 int current_link_up
= 0;
3804 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3807 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3808 u32 txflags
, rxflags
;
3811 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3812 u32 local_adv
= 0, remote_adv
= 0;
3814 if (txflags
& ANEG_CFG_PS1
)
3815 local_adv
|= ADVERTISE_1000XPAUSE
;
3816 if (txflags
& ANEG_CFG_PS2
)
3817 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3819 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3820 remote_adv
|= LPA_1000XPAUSE
;
3821 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3822 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3824 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3826 current_link_up
= 1;
3828 for (i
= 0; i
< 30; i
++) {
3831 (MAC_STATUS_SYNC_CHANGED
|
3832 MAC_STATUS_CFG_CHANGED
));
3834 if ((tr32(MAC_STATUS
) &
3835 (MAC_STATUS_SYNC_CHANGED
|
3836 MAC_STATUS_CFG_CHANGED
)) == 0)
3840 mac_status
= tr32(MAC_STATUS
);
3841 if (current_link_up
== 0 &&
3842 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3843 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3844 current_link_up
= 1;
3846 tg3_setup_flow_control(tp
, 0, 0);
3848 /* Forcing 1000FD link up. */
3849 current_link_up
= 1;
3851 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3854 tw32_f(MAC_MODE
, tp
->mac_mode
);
3859 return current_link_up
;
3862 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3865 u16 orig_active_speed
;
3866 u8 orig_active_duplex
;
3868 int current_link_up
;
3871 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3872 orig_active_speed
= tp
->link_config
.active_speed
;
3873 orig_active_duplex
= tp
->link_config
.active_duplex
;
3875 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3876 netif_carrier_ok(tp
->dev
) &&
3877 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3878 mac_status
= tr32(MAC_STATUS
);
3879 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3880 MAC_STATUS_SIGNAL_DET
|
3881 MAC_STATUS_CFG_CHANGED
|
3882 MAC_STATUS_RCVD_CFG
);
3883 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3884 MAC_STATUS_SIGNAL_DET
)) {
3885 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3886 MAC_STATUS_CFG_CHANGED
));
3891 tw32_f(MAC_TX_AUTO_NEG
, 0);
3893 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3894 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3895 tw32_f(MAC_MODE
, tp
->mac_mode
);
3898 if (tp
->phy_id
== PHY_ID_BCM8002
)
3899 tg3_init_bcm8002(tp
);
3901 /* Enable link change event even when serdes polling. */
3902 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3905 current_link_up
= 0;
3906 mac_status
= tr32(MAC_STATUS
);
3908 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3909 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3911 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3913 tp
->napi
[0].hw_status
->status
=
3914 (SD_STATUS_UPDATED
|
3915 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3917 for (i
= 0; i
< 100; i
++) {
3918 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3919 MAC_STATUS_CFG_CHANGED
));
3921 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3922 MAC_STATUS_CFG_CHANGED
|
3923 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3927 mac_status
= tr32(MAC_STATUS
);
3928 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3929 current_link_up
= 0;
3930 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3931 tp
->serdes_counter
== 0) {
3932 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3933 MAC_MODE_SEND_CONFIGS
));
3935 tw32_f(MAC_MODE
, tp
->mac_mode
);
3939 if (current_link_up
== 1) {
3940 tp
->link_config
.active_speed
= SPEED_1000
;
3941 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3942 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3943 LED_CTRL_LNKLED_OVERRIDE
|
3944 LED_CTRL_1000MBPS_ON
));
3946 tp
->link_config
.active_speed
= SPEED_INVALID
;
3947 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3948 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3949 LED_CTRL_LNKLED_OVERRIDE
|
3950 LED_CTRL_TRAFFIC_OVERRIDE
));
3953 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3954 if (current_link_up
)
3955 netif_carrier_on(tp
->dev
);
3957 netif_carrier_off(tp
->dev
);
3958 tg3_link_report(tp
);
3960 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
3961 if (orig_pause_cfg
!= now_pause_cfg
||
3962 orig_active_speed
!= tp
->link_config
.active_speed
||
3963 orig_active_duplex
!= tp
->link_config
.active_duplex
)
3964 tg3_link_report(tp
);
3970 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
3972 int current_link_up
, err
= 0;
3976 u32 local_adv
, remote_adv
;
3978 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3979 tw32_f(MAC_MODE
, tp
->mac_mode
);
3985 (MAC_STATUS_SYNC_CHANGED
|
3986 MAC_STATUS_CFG_CHANGED
|
3987 MAC_STATUS_MI_COMPLETION
|
3988 MAC_STATUS_LNKSTATE_CHANGED
));
3994 current_link_up
= 0;
3995 current_speed
= SPEED_INVALID
;
3996 current_duplex
= DUPLEX_INVALID
;
3998 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3999 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4000 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
4001 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4002 bmsr
|= BMSR_LSTATUS
;
4004 bmsr
&= ~BMSR_LSTATUS
;
4007 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4009 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4010 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4011 /* do nothing, just check for link up at the end */
4012 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4015 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4016 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4017 ADVERTISE_1000XPAUSE
|
4018 ADVERTISE_1000XPSE_ASYM
|
4021 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4023 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4024 new_adv
|= ADVERTISE_1000XHALF
;
4025 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4026 new_adv
|= ADVERTISE_1000XFULL
;
4028 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4029 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4030 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4031 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4033 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4034 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4035 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4042 bmcr
&= ~BMCR_SPEED1000
;
4043 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4045 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4046 new_bmcr
|= BMCR_FULLDPLX
;
4048 if (new_bmcr
!= bmcr
) {
4049 /* BMCR_SPEED1000 is a reserved bit that needs
4050 * to be set on write.
4052 new_bmcr
|= BMCR_SPEED1000
;
4054 /* Force a linkdown */
4055 if (netif_carrier_ok(tp
->dev
)) {
4058 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4059 adv
&= ~(ADVERTISE_1000XFULL
|
4060 ADVERTISE_1000XHALF
|
4062 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4063 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4067 netif_carrier_off(tp
->dev
);
4069 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4071 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4072 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4073 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4075 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4076 bmsr
|= BMSR_LSTATUS
;
4078 bmsr
&= ~BMSR_LSTATUS
;
4080 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4084 if (bmsr
& BMSR_LSTATUS
) {
4085 current_speed
= SPEED_1000
;
4086 current_link_up
= 1;
4087 if (bmcr
& BMCR_FULLDPLX
)
4088 current_duplex
= DUPLEX_FULL
;
4090 current_duplex
= DUPLEX_HALF
;
4095 if (bmcr
& BMCR_ANENABLE
) {
4098 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4099 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4100 common
= local_adv
& remote_adv
;
4101 if (common
& (ADVERTISE_1000XHALF
|
4102 ADVERTISE_1000XFULL
)) {
4103 if (common
& ADVERTISE_1000XFULL
)
4104 current_duplex
= DUPLEX_FULL
;
4106 current_duplex
= DUPLEX_HALF
;
4109 current_link_up
= 0;
4113 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4114 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4116 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4117 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4118 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4120 tw32_f(MAC_MODE
, tp
->mac_mode
);
4123 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4125 tp
->link_config
.active_speed
= current_speed
;
4126 tp
->link_config
.active_duplex
= current_duplex
;
4128 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4129 if (current_link_up
)
4130 netif_carrier_on(tp
->dev
);
4132 netif_carrier_off(tp
->dev
);
4133 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4135 tg3_link_report(tp
);
4140 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4142 if (tp
->serdes_counter
) {
4143 /* Give autoneg time to complete. */
4144 tp
->serdes_counter
--;
4147 if (!netif_carrier_ok(tp
->dev
) &&
4148 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4151 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4152 if (bmcr
& BMCR_ANENABLE
) {
4155 /* Select shadow register 0x1f */
4156 tg3_writephy(tp
, 0x1c, 0x7c00);
4157 tg3_readphy(tp
, 0x1c, &phy1
);
4159 /* Select expansion interrupt status register */
4160 tg3_writephy(tp
, 0x17, 0x0f01);
4161 tg3_readphy(tp
, 0x15, &phy2
);
4162 tg3_readphy(tp
, 0x15, &phy2
);
4164 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4165 /* We have signal detect and not receiving
4166 * config code words, link is up by parallel
4170 bmcr
&= ~BMCR_ANENABLE
;
4171 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4172 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4173 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4177 else if (netif_carrier_ok(tp
->dev
) &&
4178 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4179 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4182 /* Select expansion interrupt status register */
4183 tg3_writephy(tp
, 0x17, 0x0f01);
4184 tg3_readphy(tp
, 0x15, &phy2
);
4188 /* Config code words received, turn on autoneg. */
4189 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4190 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4192 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4198 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4202 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4203 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4204 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
4205 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4207 err
= tg3_setup_copper_phy(tp
, force_reset
);
4210 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4213 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4214 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4216 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4221 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4222 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4223 tw32(GRC_MISC_CFG
, val
);
4226 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4227 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4228 tw32(MAC_TX_LENGTHS
,
4229 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4230 (6 << TX_LENGTHS_IPG_SHIFT
) |
4231 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4233 tw32(MAC_TX_LENGTHS
,
4234 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4235 (6 << TX_LENGTHS_IPG_SHIFT
) |
4236 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4238 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4239 if (netif_carrier_ok(tp
->dev
)) {
4240 tw32(HOSTCC_STAT_COAL_TICKS
,
4241 tp
->coal
.stats_block_coalesce_usecs
);
4243 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4247 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4248 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4249 if (!netif_carrier_ok(tp
->dev
))
4250 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4253 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4254 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4260 /* This is called whenever we suspect that the system chipset is re-
4261 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4262 * is bogus tx completions. We try to recover by setting the
4263 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4266 static void tg3_tx_recover(struct tg3
*tp
)
4268 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4269 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4271 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4272 "mapped I/O cycles to the network device, attempting to "
4273 "recover. Please report the problem to the driver maintainer "
4274 "and include system chipset information.\n", tp
->dev
->name
);
4276 spin_lock(&tp
->lock
);
4277 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4278 spin_unlock(&tp
->lock
);
4281 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4284 return tnapi
->tx_pending
-
4285 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4288 /* Tigon3 never reports partial packet sends. So we do not
4289 * need special logic to handle SKBs that have not had all
4290 * of their frags sent yet, like SunGEM does.
4292 static void tg3_tx(struct tg3_napi
*tnapi
)
4294 struct tg3
*tp
= tnapi
->tp
;
4295 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4296 u32 sw_idx
= tnapi
->tx_cons
;
4298 while (sw_idx
!= hw_idx
) {
4299 struct tx_ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4300 struct sk_buff
*skb
= ri
->skb
;
4303 if (unlikely(skb
== NULL
)) {
4308 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4312 sw_idx
= NEXT_TX(sw_idx
);
4314 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4315 ri
= &tnapi
->tx_buffers
[sw_idx
];
4316 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4318 sw_idx
= NEXT_TX(sw_idx
);
4323 if (unlikely(tx_bug
)) {
4329 tnapi
->tx_cons
= sw_idx
;
4331 /* Need to make the tx_cons update visible to tg3_start_xmit()
4332 * before checking for netif_queue_stopped(). Without the
4333 * memory barrier, there is a small possibility that tg3_start_xmit()
4334 * will miss it and cause the queue to be stopped forever.
4338 if (unlikely(netif_queue_stopped(tp
->dev
) &&
4339 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4340 netif_tx_lock(tp
->dev
);
4341 if (netif_queue_stopped(tp
->dev
) &&
4342 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4343 netif_wake_queue(tp
->dev
);
4344 netif_tx_unlock(tp
->dev
);
4348 /* Returns size of skb allocated or < 0 on error.
4350 * We only need to fill in the address because the other members
4351 * of the RX descriptor are invariant, see tg3_init_rings.
4353 * Note the purposeful assymetry of cpu vs. chip accesses. For
4354 * posting buffers we only dirty the first cache line of the RX
4355 * descriptor (containing the address). Whereas for the RX status
4356 * buffers the cpu only reads the last cacheline of the RX descriptor
4357 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4359 static int tg3_alloc_rx_skb(struct tg3_napi
*tnapi
, u32 opaque_key
,
4360 int src_idx
, u32 dest_idx_unmasked
)
4362 struct tg3
*tp
= tnapi
->tp
;
4363 struct tg3_rx_buffer_desc
*desc
;
4364 struct ring_info
*map
, *src_map
;
4365 struct sk_buff
*skb
;
4367 int skb_size
, dest_idx
;
4368 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4371 switch (opaque_key
) {
4372 case RXD_OPAQUE_RING_STD
:
4373 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4374 desc
= &tpr
->rx_std
[dest_idx
];
4375 map
= &tpr
->rx_std_buffers
[dest_idx
];
4377 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4378 skb_size
= tp
->rx_pkt_map_sz
;
4381 case RXD_OPAQUE_RING_JUMBO
:
4382 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4383 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4384 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4386 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4387 skb_size
= TG3_RX_JMB_MAP_SZ
;
4394 /* Do not overwrite any of the map or rp information
4395 * until we are sure we can commit to a new buffer.
4397 * Callers depend upon this behavior and assume that
4398 * we leave everything unchanged if we fail.
4400 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4404 skb_reserve(skb
, tp
->rx_offset
);
4406 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4407 PCI_DMA_FROMDEVICE
);
4410 pci_unmap_addr_set(map
, mapping
, mapping
);
4412 if (src_map
!= NULL
)
4413 src_map
->skb
= NULL
;
4415 desc
->addr_hi
= ((u64
)mapping
>> 32);
4416 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4421 /* We only need to move over in the address because the other
4422 * members of the RX descriptor are invariant. See notes above
4423 * tg3_alloc_rx_skb for full details.
4425 static void tg3_recycle_rx(struct tg3_napi
*tnapi
, u32 opaque_key
,
4426 int src_idx
, u32 dest_idx_unmasked
)
4428 struct tg3
*tp
= tnapi
->tp
;
4429 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4430 struct ring_info
*src_map
, *dest_map
;
4432 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4434 switch (opaque_key
) {
4435 case RXD_OPAQUE_RING_STD
:
4436 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4437 dest_desc
= &tpr
->rx_std
[dest_idx
];
4438 dest_map
= &tpr
->rx_std_buffers
[dest_idx
];
4439 src_desc
= &tpr
->rx_std
[src_idx
];
4440 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4443 case RXD_OPAQUE_RING_JUMBO
:
4444 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4445 dest_desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4446 dest_map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4447 src_desc
= &tpr
->rx_jmb
[src_idx
].std
;
4448 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4455 dest_map
->skb
= src_map
->skb
;
4456 pci_unmap_addr_set(dest_map
, mapping
,
4457 pci_unmap_addr(src_map
, mapping
));
4458 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4459 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4461 src_map
->skb
= NULL
;
4464 /* The RX ring scheme is composed of multiple rings which post fresh
4465 * buffers to the chip, and one special ring the chip uses to report
4466 * status back to the host.
4468 * The special ring reports the status of received packets to the
4469 * host. The chip does not write into the original descriptor the
4470 * RX buffer was obtained from. The chip simply takes the original
4471 * descriptor as provided by the host, updates the status and length
4472 * field, then writes this into the next status ring entry.
4474 * Each ring the host uses to post buffers to the chip is described
4475 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4476 * it is first placed into the on-chip ram. When the packet's length
4477 * is known, it walks down the TG3_BDINFO entries to select the ring.
4478 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4479 * which is within the range of the new packet's length is chosen.
4481 * The "separate ring for rx status" scheme may sound queer, but it makes
4482 * sense from a cache coherency perspective. If only the host writes
4483 * to the buffer post rings, and only the chip writes to the rx status
4484 * rings, then cache lines never move beyond shared-modified state.
4485 * If both the host and chip were to write into the same ring, cache line
4486 * eviction could occur since both entities want it in an exclusive state.
4488 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4490 struct tg3
*tp
= tnapi
->tp
;
4491 u32 work_mask
, rx_std_posted
= 0;
4492 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4495 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4497 hw_idx
= tnapi
->hw_status
->idx
[0].rx_producer
;
4499 * We need to order the read of hw_idx and the read of
4500 * the opaque cookie.
4505 while (sw_idx
!= hw_idx
&& budget
> 0) {
4506 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4508 struct sk_buff
*skb
;
4509 dma_addr_t dma_addr
;
4510 u32 opaque_key
, desc_idx
, *post_ptr
;
4512 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4513 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4514 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4515 struct ring_info
*ri
= &tpr
->rx_std_buffers
[desc_idx
];
4516 dma_addr
= pci_unmap_addr(ri
, mapping
);
4518 post_ptr
= &tpr
->rx_std_ptr
;
4520 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4521 struct ring_info
*ri
= &tpr
->rx_jmb_buffers
[desc_idx
];
4522 dma_addr
= pci_unmap_addr(ri
, mapping
);
4524 post_ptr
= &tpr
->rx_jmb_ptr
;
4526 goto next_pkt_nopost
;
4528 work_mask
|= opaque_key
;
4530 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4531 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4533 tg3_recycle_rx(tnapi
, opaque_key
,
4534 desc_idx
, *post_ptr
);
4536 /* Other statistics kept track of by card. */
4537 tp
->net_stats
.rx_dropped
++;
4541 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4544 if (len
> RX_COPY_THRESHOLD
4545 && tp
->rx_offset
== NET_IP_ALIGN
4546 /* rx_offset will likely not equal NET_IP_ALIGN
4547 * if this is a 5701 card running in PCI-X mode
4548 * [see tg3_get_invariants()]
4553 skb_size
= tg3_alloc_rx_skb(tnapi
, opaque_key
,
4554 desc_idx
, *post_ptr
);
4558 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4559 PCI_DMA_FROMDEVICE
);
4563 struct sk_buff
*copy_skb
;
4565 tg3_recycle_rx(tnapi
, opaque_key
,
4566 desc_idx
, *post_ptr
);
4568 copy_skb
= netdev_alloc_skb(tp
->dev
,
4569 len
+ TG3_RAW_IP_ALIGN
);
4570 if (copy_skb
== NULL
)
4571 goto drop_it_no_recycle
;
4573 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4574 skb_put(copy_skb
, len
);
4575 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4576 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4577 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4579 /* We'll reuse the original ring buffer. */
4583 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4584 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4585 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4586 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4587 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4589 skb
->ip_summed
= CHECKSUM_NONE
;
4591 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4593 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4594 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4599 #if TG3_VLAN_TAG_USED
4600 if (tp
->vlgrp
!= NULL
&&
4601 desc
->type_flags
& RXD_FLAG_VLAN
) {
4602 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
,
4603 desc
->err_vlan
& RXD_VLAN_MASK
, skb
);
4606 napi_gro_receive(&tnapi
->napi
, skb
);
4614 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4615 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4617 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4618 TG3_64BIT_REG_LOW
, idx
);
4619 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4624 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4626 /* Refresh hw_idx to see if there is new work */
4627 if (sw_idx
== hw_idx
) {
4628 hw_idx
= tnapi
->hw_status
->idx
[0].rx_producer
;
4633 /* ACK the status ring. */
4634 tnapi
->rx_rcb_ptr
= sw_idx
;
4635 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4637 /* Refill RX ring(s). */
4638 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4639 sw_idx
= tpr
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4640 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4643 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4644 sw_idx
= tpr
->rx_jmb_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4645 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4653 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4655 struct tg3
*tp
= tnapi
->tp
;
4656 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4658 /* handle link change and other phy events */
4659 if (!(tp
->tg3_flags
&
4660 (TG3_FLAG_USE_LINKCHG_REG
|
4661 TG3_FLAG_POLL_SERDES
))) {
4662 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4663 sblk
->status
= SD_STATUS_UPDATED
|
4664 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4665 spin_lock(&tp
->lock
);
4666 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4668 (MAC_STATUS_SYNC_CHANGED
|
4669 MAC_STATUS_CFG_CHANGED
|
4670 MAC_STATUS_MI_COMPLETION
|
4671 MAC_STATUS_LNKSTATE_CHANGED
));
4674 tg3_setup_phy(tp
, 0);
4675 spin_unlock(&tp
->lock
);
4679 /* run TX completion thread */
4680 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4682 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4686 /* run RX thread, within the bounds set by NAPI.
4687 * All RX "locking" is done by ensuring outside
4688 * code synchronizes with tg3->napi.poll()
4690 if (sblk
->idx
[0].rx_producer
!= tnapi
->rx_rcb_ptr
)
4691 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4696 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4698 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
4699 struct tg3
*tp
= tnapi
->tp
;
4701 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4704 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
4706 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4709 if (unlikely(work_done
>= budget
))
4712 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4713 /* tp->last_tag is used in tg3_int_reenable() below
4714 * to tell the hw how much work has been processed,
4715 * so we must read it before checking for more work.
4717 tnapi
->last_tag
= sblk
->status_tag
;
4718 tnapi
->last_irq_tag
= tnapi
->last_tag
;
4721 sblk
->status
&= ~SD_STATUS_UPDATED
;
4723 if (likely(!tg3_has_work(tnapi
))) {
4724 napi_complete(napi
);
4725 tg3_int_reenable(tnapi
);
4733 /* work_done is guaranteed to be less than budget. */
4734 napi_complete(napi
);
4735 schedule_work(&tp
->reset_task
);
4739 static void tg3_irq_quiesce(struct tg3
*tp
)
4743 BUG_ON(tp
->irq_sync
);
4748 for (i
= 0; i
< tp
->irq_cnt
; i
++)
4749 synchronize_irq(tp
->napi
[i
].irq_vec
);
4752 static inline int tg3_irq_sync(struct tg3
*tp
)
4754 return tp
->irq_sync
;
4757 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4758 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4759 * with as well. Most of the time, this is not necessary except when
4760 * shutting down the device.
4762 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4764 spin_lock_bh(&tp
->lock
);
4766 tg3_irq_quiesce(tp
);
4769 static inline void tg3_full_unlock(struct tg3
*tp
)
4771 spin_unlock_bh(&tp
->lock
);
4774 /* One-shot MSI handler - Chip automatically disables interrupt
4775 * after sending MSI so driver doesn't have to do it.
4777 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4779 struct tg3_napi
*tnapi
= dev_id
;
4780 struct tg3
*tp
= tnapi
->tp
;
4782 prefetch(tnapi
->hw_status
);
4783 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4785 if (likely(!tg3_irq_sync(tp
)))
4786 napi_schedule(&tnapi
->napi
);
4791 /* MSI ISR - No need to check for interrupt sharing and no need to
4792 * flush status block and interrupt mailbox. PCI ordering rules
4793 * guarantee that MSI will arrive after the status block.
4795 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4797 struct tg3_napi
*tnapi
= dev_id
;
4798 struct tg3
*tp
= tnapi
->tp
;
4800 prefetch(tnapi
->hw_status
);
4801 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4803 * Writing any value to intr-mbox-0 clears PCI INTA# and
4804 * chip-internal interrupt pending events.
4805 * Writing non-zero to intr-mbox-0 additional tells the
4806 * NIC to stop sending us irqs, engaging "in-intr-handler"
4809 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4810 if (likely(!tg3_irq_sync(tp
)))
4811 napi_schedule(&tnapi
->napi
);
4813 return IRQ_RETVAL(1);
4816 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4818 struct tg3_napi
*tnapi
= dev_id
;
4819 struct tg3
*tp
= tnapi
->tp
;
4820 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4821 unsigned int handled
= 1;
4823 /* In INTx mode, it is possible for the interrupt to arrive at
4824 * the CPU before the status block posted prior to the interrupt.
4825 * Reading the PCI State register will confirm whether the
4826 * interrupt is ours and will flush the status block.
4828 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4829 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4830 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4837 * Writing any value to intr-mbox-0 clears PCI INTA# and
4838 * chip-internal interrupt pending events.
4839 * Writing non-zero to intr-mbox-0 additional tells the
4840 * NIC to stop sending us irqs, engaging "in-intr-handler"
4843 * Flush the mailbox to de-assert the IRQ immediately to prevent
4844 * spurious interrupts. The flush impacts performance but
4845 * excessive spurious interrupts can be worse in some cases.
4847 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4848 if (tg3_irq_sync(tp
))
4850 sblk
->status
&= ~SD_STATUS_UPDATED
;
4851 if (likely(tg3_has_work(tnapi
))) {
4852 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4853 napi_schedule(&tnapi
->napi
);
4855 /* No work, shared interrupt perhaps? re-enable
4856 * interrupts, and flush that PCI write
4858 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4862 return IRQ_RETVAL(handled
);
4865 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4867 struct tg3_napi
*tnapi
= dev_id
;
4868 struct tg3
*tp
= tnapi
->tp
;
4869 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4870 unsigned int handled
= 1;
4872 /* In INTx mode, it is possible for the interrupt to arrive at
4873 * the CPU before the status block posted prior to the interrupt.
4874 * Reading the PCI State register will confirm whether the
4875 * interrupt is ours and will flush the status block.
4877 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
4878 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4879 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4886 * writing any value to intr-mbox-0 clears PCI INTA# and
4887 * chip-internal interrupt pending events.
4888 * writing non-zero to intr-mbox-0 additional tells the
4889 * NIC to stop sending us irqs, engaging "in-intr-handler"
4892 * Flush the mailbox to de-assert the IRQ immediately to prevent
4893 * spurious interrupts. The flush impacts performance but
4894 * excessive spurious interrupts can be worse in some cases.
4896 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4899 * In a shared interrupt configuration, sometimes other devices'
4900 * interrupts will scream. We record the current status tag here
4901 * so that the above check can report that the screaming interrupts
4902 * are unhandled. Eventually they will be silenced.
4904 tnapi
->last_irq_tag
= sblk
->status_tag
;
4906 if (tg3_irq_sync(tp
))
4909 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4911 napi_schedule(&tnapi
->napi
);
4914 return IRQ_RETVAL(handled
);
4917 /* ISR for interrupt test */
4918 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4920 struct tg3_napi
*tnapi
= dev_id
;
4921 struct tg3
*tp
= tnapi
->tp
;
4922 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4924 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4925 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4926 tg3_disable_ints(tp
);
4927 return IRQ_RETVAL(1);
4929 return IRQ_RETVAL(0);
4932 static int tg3_init_hw(struct tg3
*, int);
4933 static int tg3_halt(struct tg3
*, int, int);
4935 /* Restart hardware after configuration changes, self-test, etc.
4936 * Invoked with tp->lock held.
4938 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4939 __releases(tp
->lock
)
4940 __acquires(tp
->lock
)
4944 err
= tg3_init_hw(tp
, reset_phy
);
4946 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
4947 "aborting.\n", tp
->dev
->name
);
4948 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
4949 tg3_full_unlock(tp
);
4950 del_timer_sync(&tp
->timer
);
4952 napi_enable(&tp
->napi
[0].napi
);
4954 tg3_full_lock(tp
, 0);
4959 #ifdef CONFIG_NET_POLL_CONTROLLER
4960 static void tg3_poll_controller(struct net_device
*dev
)
4963 struct tg3
*tp
= netdev_priv(dev
);
4965 for (i
= 0; i
< tp
->irq_cnt
; i
++)
4966 tg3_interrupt(tp
->napi
[i
].irq_vec
, dev
);
4970 static void tg3_reset_task(struct work_struct
*work
)
4972 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
4974 unsigned int restart_timer
;
4976 tg3_full_lock(tp
, 0);
4978 if (!netif_running(tp
->dev
)) {
4979 tg3_full_unlock(tp
);
4983 tg3_full_unlock(tp
);
4989 tg3_full_lock(tp
, 1);
4991 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
4992 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
4994 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
4995 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
4996 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
4997 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
4998 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
5001 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
5002 err
= tg3_init_hw(tp
, 1);
5006 tg3_netif_start(tp
);
5009 mod_timer(&tp
->timer
, jiffies
+ 1);
5012 tg3_full_unlock(tp
);
5018 static void tg3_dump_short_state(struct tg3
*tp
)
5020 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5021 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5022 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5023 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5026 static void tg3_tx_timeout(struct net_device
*dev
)
5028 struct tg3
*tp
= netdev_priv(dev
);
5030 if (netif_msg_tx_err(tp
)) {
5031 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
5033 tg3_dump_short_state(tp
);
5036 schedule_work(&tp
->reset_task
);
5039 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5040 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5042 u32 base
= (u32
) mapping
& 0xffffffff;
5044 return ((base
> 0xffffdcc0) &&
5045 (base
+ len
+ 8 < base
));
5048 /* Test for DMA addresses > 40-bit */
5049 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5052 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5053 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5054 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5061 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5063 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5064 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
5065 u32 last_plus_one
, u32
*start
,
5066 u32 base_flags
, u32 mss
)
5068 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5069 struct sk_buff
*new_skb
;
5070 dma_addr_t new_addr
= 0;
5074 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5075 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5077 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5079 new_skb
= skb_copy_expand(skb
,
5080 skb_headroom(skb
) + more_headroom
,
5081 skb_tailroom(skb
), GFP_ATOMIC
);
5087 /* New SKB is guaranteed to be linear. */
5089 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
5090 new_addr
= skb_shinfo(new_skb
)->dma_head
;
5092 /* Make sure new skb does not cross any 4G boundaries.
5093 * Drop the packet if it does.
5095 if (ret
|| tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5097 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
5100 dev_kfree_skb(new_skb
);
5103 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5104 base_flags
, 1 | (mss
<< 1));
5105 *start
= NEXT_TX(entry
);
5109 /* Now clean up the sw ring entries. */
5111 while (entry
!= last_plus_one
) {
5113 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5115 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5116 entry
= NEXT_TX(entry
);
5120 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5126 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5127 dma_addr_t mapping
, int len
, u32 flags
,
5130 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5131 int is_end
= (mss_and_is_end
& 0x1);
5132 u32 mss
= (mss_and_is_end
>> 1);
5136 flags
|= TXD_FLAG_END
;
5137 if (flags
& TXD_FLAG_VLAN
) {
5138 vlan_tag
= flags
>> 16;
5141 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5143 txd
->addr_hi
= ((u64
) mapping
>> 32);
5144 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5145 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5146 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5149 /* hard_start_xmit for devices that don't have any bugs and
5150 * support TG3_FLG2_HW_TSO_2 only.
5152 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5153 struct net_device
*dev
)
5155 struct tg3
*tp
= netdev_priv(dev
);
5156 u32 len
, entry
, base_flags
, mss
;
5157 struct skb_shared_info
*sp
;
5159 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5161 len
= skb_headlen(skb
);
5163 /* We are running in BH disabled context with netif_tx_lock
5164 * and TX reclaim runs via tp->napi.poll inside of a software
5165 * interrupt. Furthermore, IRQ processing runs lockless so we have
5166 * no IRQ context deadlocks to worry about either. Rejoice!
5168 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5169 if (!netif_queue_stopped(dev
)) {
5170 netif_stop_queue(dev
);
5172 /* This is a hard error, log it. */
5173 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5174 "queue awake!\n", dev
->name
);
5176 return NETDEV_TX_BUSY
;
5179 entry
= tnapi
->tx_prod
;
5182 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5183 int tcp_opt_len
, ip_tcp_len
;
5185 if (skb_header_cloned(skb
) &&
5186 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5191 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5192 mss
|= (skb_headlen(skb
) - ETH_HLEN
) << 9;
5194 struct iphdr
*iph
= ip_hdr(skb
);
5196 tcp_opt_len
= tcp_optlen(skb
);
5197 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5200 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5201 mss
|= (ip_tcp_len
+ tcp_opt_len
) << 9;
5204 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5205 TXD_FLAG_CPU_POST_DMA
);
5207 tcp_hdr(skb
)->check
= 0;
5210 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5211 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5212 #if TG3_VLAN_TAG_USED
5213 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5214 base_flags
|= (TXD_FLAG_VLAN
|
5215 (vlan_tx_tag_get(skb
) << 16));
5218 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5223 sp
= skb_shinfo(skb
);
5225 mapping
= sp
->dma_head
;
5227 tnapi
->tx_buffers
[entry
].skb
= skb
;
5229 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5230 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5232 entry
= NEXT_TX(entry
);
5234 /* Now loop through additional data fragments, and queue them. */
5235 if (skb_shinfo(skb
)->nr_frags
> 0) {
5236 unsigned int i
, last
;
5238 last
= skb_shinfo(skb
)->nr_frags
- 1;
5239 for (i
= 0; i
<= last
; i
++) {
5240 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5243 mapping
= sp
->dma_maps
[i
];
5244 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5246 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5247 base_flags
, (i
== last
) | (mss
<< 1));
5249 entry
= NEXT_TX(entry
);
5253 /* Packets are ready, update Tx producer idx local and on card. */
5254 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5256 tnapi
->tx_prod
= entry
;
5257 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5258 netif_stop_queue(dev
);
5259 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5260 netif_wake_queue(tp
->dev
);
5266 return NETDEV_TX_OK
;
5269 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5270 struct net_device
*);
5272 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5273 * TSO header is greater than 80 bytes.
5275 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5277 struct sk_buff
*segs
, *nskb
;
5278 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5280 /* Estimate the number of fragments in the worst case */
5281 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5282 netif_stop_queue(tp
->dev
);
5283 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5284 return NETDEV_TX_BUSY
;
5286 netif_wake_queue(tp
->dev
);
5289 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5291 goto tg3_tso_bug_end
;
5297 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5303 return NETDEV_TX_OK
;
5306 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5307 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5309 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5310 struct net_device
*dev
)
5312 struct tg3
*tp
= netdev_priv(dev
);
5313 u32 len
, entry
, base_flags
, mss
;
5314 struct skb_shared_info
*sp
;
5315 int would_hit_hwbug
;
5317 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5319 len
= skb_headlen(skb
);
5321 /* We are running in BH disabled context with netif_tx_lock
5322 * and TX reclaim runs via tp->napi.poll inside of a software
5323 * interrupt. Furthermore, IRQ processing runs lockless so we have
5324 * no IRQ context deadlocks to worry about either. Rejoice!
5326 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5327 if (!netif_queue_stopped(dev
)) {
5328 netif_stop_queue(dev
);
5330 /* This is a hard error, log it. */
5331 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5332 "queue awake!\n", dev
->name
);
5334 return NETDEV_TX_BUSY
;
5337 entry
= tnapi
->tx_prod
;
5339 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5340 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5342 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5344 int tcp_opt_len
, ip_tcp_len
, hdr_len
;
5346 if (skb_header_cloned(skb
) &&
5347 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5352 tcp_opt_len
= tcp_optlen(skb
);
5353 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5355 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5356 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5357 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5358 return (tg3_tso_bug(tp
, skb
));
5360 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5361 TXD_FLAG_CPU_POST_DMA
);
5365 iph
->tot_len
= htons(mss
+ hdr_len
);
5366 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5367 tcp_hdr(skb
)->check
= 0;
5368 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5370 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5375 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
5376 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
5377 if (tcp_opt_len
|| iph
->ihl
> 5) {
5380 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5381 mss
|= (tsflags
<< 11);
5384 if (tcp_opt_len
|| iph
->ihl
> 5) {
5387 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5388 base_flags
|= tsflags
<< 12;
5392 #if TG3_VLAN_TAG_USED
5393 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5394 base_flags
|= (TXD_FLAG_VLAN
|
5395 (vlan_tx_tag_get(skb
) << 16));
5398 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5403 sp
= skb_shinfo(skb
);
5405 mapping
= sp
->dma_head
;
5407 tnapi
->tx_buffers
[entry
].skb
= skb
;
5409 would_hit_hwbug
= 0;
5411 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5412 would_hit_hwbug
= 1;
5413 else if (tg3_4g_overflow_test(mapping
, len
))
5414 would_hit_hwbug
= 1;
5416 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5417 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5419 entry
= NEXT_TX(entry
);
5421 /* Now loop through additional data fragments, and queue them. */
5422 if (skb_shinfo(skb
)->nr_frags
> 0) {
5423 unsigned int i
, last
;
5425 last
= skb_shinfo(skb
)->nr_frags
- 1;
5426 for (i
= 0; i
<= last
; i
++) {
5427 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5430 mapping
= sp
->dma_maps
[i
];
5432 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5434 if (tg3_4g_overflow_test(mapping
, len
))
5435 would_hit_hwbug
= 1;
5437 if (tg3_40bit_overflow_test(tp
, mapping
, len
))
5438 would_hit_hwbug
= 1;
5440 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5441 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5442 base_flags
, (i
== last
)|(mss
<< 1));
5444 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5445 base_flags
, (i
== last
));
5447 entry
= NEXT_TX(entry
);
5451 if (would_hit_hwbug
) {
5452 u32 last_plus_one
= entry
;
5455 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5456 start
&= (TG3_TX_RING_SIZE
- 1);
5458 /* If the workaround fails due to memory/mapping
5459 * failure, silently drop this packet.
5461 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5462 &start
, base_flags
, mss
))
5468 /* Packets are ready, update Tx producer idx local and on card. */
5469 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, entry
);
5471 tnapi
->tx_prod
= entry
;
5472 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5473 netif_stop_queue(dev
);
5474 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5475 netif_wake_queue(tp
->dev
);
5481 return NETDEV_TX_OK
;
5484 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5489 if (new_mtu
> ETH_DATA_LEN
) {
5490 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5491 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5492 ethtool_op_set_tso(dev
, 0);
5495 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5497 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5498 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5499 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5503 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5505 struct tg3
*tp
= netdev_priv(dev
);
5508 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5511 if (!netif_running(dev
)) {
5512 /* We'll just catch it later when the
5515 tg3_set_mtu(dev
, tp
, new_mtu
);
5523 tg3_full_lock(tp
, 1);
5525 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5527 tg3_set_mtu(dev
, tp
, new_mtu
);
5529 err
= tg3_restart_hw(tp
, 0);
5532 tg3_netif_start(tp
);
5534 tg3_full_unlock(tp
);
5542 static void tg3_rx_prodring_free(struct tg3
*tp
,
5543 struct tg3_rx_prodring_set
*tpr
)
5546 struct ring_info
*rxp
;
5548 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5549 rxp
= &tpr
->rx_std_buffers
[i
];
5551 if (rxp
->skb
== NULL
)
5554 pci_unmap_single(tp
->pdev
,
5555 pci_unmap_addr(rxp
, mapping
),
5557 PCI_DMA_FROMDEVICE
);
5558 dev_kfree_skb_any(rxp
->skb
);
5562 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5563 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5564 rxp
= &tpr
->rx_jmb_buffers
[i
];
5566 if (rxp
->skb
== NULL
)
5569 pci_unmap_single(tp
->pdev
,
5570 pci_unmap_addr(rxp
, mapping
),
5572 PCI_DMA_FROMDEVICE
);
5573 dev_kfree_skb_any(rxp
->skb
);
5579 /* Initialize tx/rx rings for packet processing.
5581 * The chip has been shut down and the driver detached from
5582 * the networking, so no interrupts or new tx packets will
5583 * end up in the driver. tp->{tx,}lock are held and thus
5586 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
5587 struct tg3_rx_prodring_set
*tpr
)
5589 u32 i
, rx_pkt_dma_sz
;
5590 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5592 /* Zero out all descriptors. */
5593 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
5595 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
5596 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5597 tp
->dev
->mtu
> ETH_DATA_LEN
)
5598 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
5599 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
5601 /* Initialize invariants of the rings, we only set this
5602 * stuff once. This works because the card does not
5603 * write into the rx buffer posting rings.
5605 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5606 struct tg3_rx_buffer_desc
*rxd
;
5608 rxd
= &tpr
->rx_std
[i
];
5609 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
5610 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5611 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5612 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5615 /* Now allocate fresh SKBs for each rx ring. */
5616 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5617 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5618 printk(KERN_WARNING PFX
5619 "%s: Using a smaller RX standard ring, "
5620 "only %d out of %d buffers were allocated "
5622 tp
->dev
->name
, i
, tp
->rx_pending
);
5630 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
5633 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
5635 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5636 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5637 struct tg3_rx_buffer_desc
*rxd
;
5639 rxd
= &tpr
->rx_jmb
[i
].std
;
5640 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
5641 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5643 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5644 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5647 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5648 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_JUMBO
,
5650 printk(KERN_WARNING PFX
5651 "%s: Using a smaller RX jumbo ring, "
5652 "only %d out of %d buffers were "
5653 "allocated successfully.\n",
5654 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5657 tp
->rx_jumbo_pending
= i
;
5667 tg3_rx_prodring_free(tp
, tpr
);
5671 static void tg3_rx_prodring_fini(struct tg3
*tp
,
5672 struct tg3_rx_prodring_set
*tpr
)
5674 kfree(tpr
->rx_std_buffers
);
5675 tpr
->rx_std_buffers
= NULL
;
5676 kfree(tpr
->rx_jmb_buffers
);
5677 tpr
->rx_jmb_buffers
= NULL
;
5679 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5680 tpr
->rx_std
, tpr
->rx_std_mapping
);
5684 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5685 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
5690 static int tg3_rx_prodring_init(struct tg3
*tp
,
5691 struct tg3_rx_prodring_set
*tpr
)
5693 tpr
->rx_std_buffers
= kzalloc(sizeof(struct ring_info
) *
5694 TG3_RX_RING_SIZE
, GFP_KERNEL
);
5695 if (!tpr
->rx_std_buffers
)
5698 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5699 &tpr
->rx_std_mapping
);
5703 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5704 tpr
->rx_jmb_buffers
= kzalloc(sizeof(struct ring_info
) *
5705 TG3_RX_JUMBO_RING_SIZE
,
5707 if (!tpr
->rx_jmb_buffers
)
5710 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
5711 TG3_RX_JUMBO_RING_BYTES
,
5712 &tpr
->rx_jmb_mapping
);
5720 tg3_rx_prodring_fini(tp
, tpr
);
5724 /* Free up pending packets in all rx/tx rings.
5726 * The chip has been shut down and the driver detached from
5727 * the networking, so no interrupts or new tx packets will
5728 * end up in the driver. tp->{tx,}lock is not held and we are not
5729 * in an interrupt context and thus may sleep.
5731 static void tg3_free_rings(struct tg3
*tp
)
5735 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
5736 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
5738 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5739 struct tx_ring_info
*txp
;
5740 struct sk_buff
*skb
;
5742 txp
= &tnapi
->tx_buffers
[i
];
5750 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5754 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5756 dev_kfree_skb_any(skb
);
5760 tg3_rx_prodring_free(tp
, &tp
->prodring
[0]);
5763 /* Initialize tx/rx rings for packet processing.
5765 * The chip has been shut down and the driver detached from
5766 * the networking, so no interrupts or new tx packets will
5767 * end up in the driver. tp->{tx,}lock are held and thus
5770 static int tg3_init_rings(struct tg3
*tp
)
5774 /* Free up all the SKBs. */
5777 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5778 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5780 tnapi
->last_tag
= 0;
5781 tnapi
->last_irq_tag
= 0;
5782 tnapi
->hw_status
->status
= 0;
5783 tnapi
->hw_status
->status_tag
= 0;
5784 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5788 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5790 tnapi
->rx_rcb_ptr
= 0;
5791 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5794 return tg3_rx_prodring_alloc(tp
, &tp
->prodring
[0]);
5798 * Must not be invoked with interrupt sources disabled and
5799 * the hardware shutdown down.
5801 static void tg3_free_consistent(struct tg3
*tp
)
5805 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5806 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5808 if (tnapi
->tx_ring
) {
5809 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5810 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
5811 tnapi
->tx_ring
= NULL
;
5814 kfree(tnapi
->tx_buffers
);
5815 tnapi
->tx_buffers
= NULL
;
5817 if (tnapi
->rx_rcb
) {
5818 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5820 tnapi
->rx_rcb_mapping
);
5821 tnapi
->rx_rcb
= NULL
;
5824 if (tnapi
->hw_status
) {
5825 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5827 tnapi
->status_mapping
);
5828 tnapi
->hw_status
= NULL
;
5833 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5834 tp
->hw_stats
, tp
->stats_mapping
);
5835 tp
->hw_stats
= NULL
;
5838 tg3_rx_prodring_fini(tp
, &tp
->prodring
[0]);
5842 * Must not be invoked with interrupt sources disabled and
5843 * the hardware shutdown down. Can sleep.
5845 static int tg3_alloc_consistent(struct tg3
*tp
)
5849 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[0]))
5852 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5853 sizeof(struct tg3_hw_stats
),
5854 &tp
->stats_mapping
);
5858 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5860 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
5861 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
5863 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5865 &tnapi
->status_mapping
);
5866 if (!tnapi
->hw_status
)
5869 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5871 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
5872 TG3_RX_RCB_RING_BYTES(tp
),
5873 &tnapi
->rx_rcb_mapping
);
5877 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5879 tnapi
->tx_buffers
= kzalloc(sizeof(struct tx_ring_info
) *
5880 TG3_TX_RING_SIZE
, GFP_KERNEL
);
5881 if (!tnapi
->tx_buffers
)
5884 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
,
5886 &tnapi
->tx_desc_mapping
);
5887 if (!tnapi
->tx_ring
)
5894 tg3_free_consistent(tp
);
5898 #define MAX_WAIT_CNT 1000
5900 /* To stop a block, clear the enable bit and poll till it
5901 * clears. tp->lock is held.
5903 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
5908 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5915 /* We can't enable/disable these bits of the
5916 * 5705/5750, just say success.
5929 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5932 if ((val
& enable_bit
) == 0)
5936 if (i
== MAX_WAIT_CNT
&& !silent
) {
5937 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
5938 "ofs=%lx enable_bit=%x\n",
5946 /* tp->lock is held. */
5947 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
5951 tg3_disable_ints(tp
);
5953 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
5954 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5957 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
5958 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
5959 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
5960 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
5961 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
5962 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
5964 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
5965 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
5966 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
5967 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
5968 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
5969 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
5970 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
5972 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
5973 tw32_f(MAC_MODE
, tp
->mac_mode
);
5976 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
5977 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5979 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5981 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
5984 if (i
>= MAX_WAIT_CNT
) {
5985 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
5986 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5987 tp
->dev
->name
, tr32(MAC_TX_MODE
));
5991 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
5992 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
5993 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
5995 tw32(FTQ_RESET
, 0xffffffff);
5996 tw32(FTQ_RESET
, 0x00000000);
5998 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
5999 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
6001 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6002 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6003 if (tnapi
->hw_status
)
6004 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6007 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
6012 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
6017 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
6018 if (apedata
!= APE_SEG_SIG_MAGIC
)
6021 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
6022 if (!(apedata
& APE_FW_STATUS_READY
))
6025 /* Wait for up to 1 millisecond for APE to service previous event. */
6026 for (i
= 0; i
< 10; i
++) {
6027 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
6030 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
6032 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6033 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
6034 event
| APE_EVENT_STATUS_EVENT_PENDING
);
6036 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
6038 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6044 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6045 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6048 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6053 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6057 case RESET_KIND_INIT
:
6058 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6059 APE_HOST_SEG_SIG_MAGIC
);
6060 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6061 APE_HOST_SEG_LEN_MAGIC
);
6062 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6063 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6064 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6065 APE_HOST_DRIVER_ID_MAGIC
);
6066 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6067 APE_HOST_BEHAV_NO_PHYLOCK
);
6069 event
= APE_EVENT_STATUS_STATE_START
;
6071 case RESET_KIND_SHUTDOWN
:
6072 /* With the interface we are currently using,
6073 * APE does not track driver state. Wiping
6074 * out the HOST SEGMENT SIGNATURE forces
6075 * the APE to assume OS absent status.
6077 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6079 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6081 case RESET_KIND_SUSPEND
:
6082 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6088 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6090 tg3_ape_send_event(tp
, event
);
6093 /* tp->lock is held. */
6094 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6096 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6097 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6099 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6101 case RESET_KIND_INIT
:
6102 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6106 case RESET_KIND_SHUTDOWN
:
6107 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6111 case RESET_KIND_SUSPEND
:
6112 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6121 if (kind
== RESET_KIND_INIT
||
6122 kind
== RESET_KIND_SUSPEND
)
6123 tg3_ape_driver_state_change(tp
, kind
);
6126 /* tp->lock is held. */
6127 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6129 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6131 case RESET_KIND_INIT
:
6132 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6133 DRV_STATE_START_DONE
);
6136 case RESET_KIND_SHUTDOWN
:
6137 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6138 DRV_STATE_UNLOAD_DONE
);
6146 if (kind
== RESET_KIND_SHUTDOWN
)
6147 tg3_ape_driver_state_change(tp
, kind
);
6150 /* tp->lock is held. */
6151 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6153 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6155 case RESET_KIND_INIT
:
6156 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6160 case RESET_KIND_SHUTDOWN
:
6161 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6165 case RESET_KIND_SUSPEND
:
6166 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6176 static int tg3_poll_fw(struct tg3
*tp
)
6181 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6182 /* Wait up to 20ms for init done. */
6183 for (i
= 0; i
< 200; i
++) {
6184 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6191 /* Wait for firmware initialization to complete. */
6192 for (i
= 0; i
< 100000; i
++) {
6193 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6194 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6199 /* Chip might not be fitted with firmware. Some Sun onboard
6200 * parts are configured like that. So don't signal the timeout
6201 * of the above loop as an error, but do report the lack of
6202 * running firmware once.
6205 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6206 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6208 printk(KERN_INFO PFX
"%s: No firmware running.\n",
6215 /* Save PCI command register before chip reset */
6216 static void tg3_save_pci_state(struct tg3
*tp
)
6218 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6221 /* Restore PCI state after chip reset */
6222 static void tg3_restore_pci_state(struct tg3
*tp
)
6226 /* Re-enable indirect register accesses. */
6227 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6228 tp
->misc_host_ctrl
);
6230 /* Set MAX PCI retry to zero. */
6231 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6232 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6233 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6234 val
|= PCISTATE_RETRY_SAME_DMA
;
6235 /* Allow reads and writes to the APE register and memory space. */
6236 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6237 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6238 PCISTATE_ALLOW_APE_SHMEM_WR
;
6239 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6241 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6243 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6244 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6245 pcie_set_readrq(tp
->pdev
, 4096);
6247 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6248 tp
->pci_cacheline_sz
);
6249 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6254 /* Make sure PCI-X relaxed ordering bit is clear. */
6255 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6258 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6260 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6261 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6265 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6267 /* Chip reset on 5780 will reset MSI enable bit,
6268 * so need to restore it.
6270 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6273 pci_read_config_word(tp
->pdev
,
6274 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6276 pci_write_config_word(tp
->pdev
,
6277 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6278 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6279 val
= tr32(MSGINT_MODE
);
6280 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6285 static void tg3_stop_fw(struct tg3
*);
6287 /* tp->lock is held. */
6288 static int tg3_chip_reset(struct tg3
*tp
)
6291 void (*write_op
)(struct tg3
*, u32
, u32
);
6298 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6300 /* No matching tg3_nvram_unlock() after this because
6301 * chip reset below will undo the nvram lock.
6303 tp
->nvram_lock_cnt
= 0;
6305 /* GRC_MISC_CFG core clock reset will clear the memory
6306 * enable bit in PCI register 4 and the MSI enable bit
6307 * on some chips, so we save relevant registers here.
6309 tg3_save_pci_state(tp
);
6311 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6312 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6313 tw32(GRC_FASTBOOT_PC
, 0);
6316 * We must avoid the readl() that normally takes place.
6317 * It locks machines, causes machine checks, and other
6318 * fun things. So, temporarily disable the 5701
6319 * hardware workaround, while we do the reset.
6321 write_op
= tp
->write32
;
6322 if (write_op
== tg3_write_flush_reg32
)
6323 tp
->write32
= tg3_write32
;
6325 /* Prevent the irq handler from reading or writing PCI registers
6326 * during chip reset when the memory enable bit in the PCI command
6327 * register may be cleared. The chip does not generate interrupt
6328 * at this time, but the irq handler may still be called due to irq
6329 * sharing or irqpoll.
6331 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6332 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6333 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6334 if (tnapi
->hw_status
) {
6335 tnapi
->hw_status
->status
= 0;
6336 tnapi
->hw_status
->status_tag
= 0;
6338 tnapi
->last_tag
= 0;
6339 tnapi
->last_irq_tag
= 0;
6343 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6344 synchronize_irq(tp
->napi
[i
].irq_vec
);
6346 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6347 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6348 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6352 val
= GRC_MISC_CFG_CORECLK_RESET
;
6354 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6355 if (tr32(0x7e2c) == 0x60) {
6358 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6359 tw32(GRC_MISC_CFG
, (1 << 29));
6364 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6365 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6366 tw32(GRC_VCPU_EXT_CTRL
,
6367 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6370 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6371 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6372 tw32(GRC_MISC_CFG
, val
);
6374 /* restore 5701 hardware bug workaround write method */
6375 tp
->write32
= write_op
;
6377 /* Unfortunately, we have to delay before the PCI read back.
6378 * Some 575X chips even will not respond to a PCI cfg access
6379 * when the reset command is given to the chip.
6381 * How do these hardware designers expect things to work
6382 * properly if the PCI write is posted for a long period
6383 * of time? It is always necessary to have some method by
6384 * which a register read back can occur to push the write
6385 * out which does the reset.
6387 * For most tg3 variants the trick below was working.
6392 /* Flush PCI posted writes. The normal MMIO registers
6393 * are inaccessible at this time so this is the only
6394 * way to make this reliably (actually, this is no longer
6395 * the case, see above). I tried to use indirect
6396 * register read/write but this upset some 5701 variants.
6398 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6402 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6405 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6409 /* Wait for link training to complete. */
6410 for (i
= 0; i
< 5000; i
++)
6413 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6414 pci_write_config_dword(tp
->pdev
, 0xc4,
6415 cfg_val
| (1 << 15));
6418 /* Clear the "no snoop" and "relaxed ordering" bits. */
6419 pci_read_config_word(tp
->pdev
,
6420 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6422 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
6423 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6425 * Older PCIe devices only support the 128 byte
6426 * MPS setting. Enforce the restriction.
6428 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
6429 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
6430 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
6431 pci_write_config_word(tp
->pdev
,
6432 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6435 pcie_set_readrq(tp
->pdev
, 4096);
6437 /* Clear error status */
6438 pci_write_config_word(tp
->pdev
,
6439 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6440 PCI_EXP_DEVSTA_CED
|
6441 PCI_EXP_DEVSTA_NFED
|
6442 PCI_EXP_DEVSTA_FED
|
6443 PCI_EXP_DEVSTA_URD
);
6446 tg3_restore_pci_state(tp
);
6448 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6451 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6452 val
= tr32(MEMARB_MODE
);
6453 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6455 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6457 tw32(0x5000, 0x400);
6460 tw32(GRC_MODE
, tp
->grc_mode
);
6462 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6465 tw32(0xc4, val
| (1 << 15));
6468 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6469 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6470 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6471 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6472 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6473 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6476 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6477 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6478 tw32_f(MAC_MODE
, tp
->mac_mode
);
6479 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6480 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6481 tw32_f(MAC_MODE
, tp
->mac_mode
);
6482 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6483 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6484 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6485 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6486 tw32_f(MAC_MODE
, tp
->mac_mode
);
6488 tw32_f(MAC_MODE
, 0);
6491 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6493 err
= tg3_poll_fw(tp
);
6499 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6500 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6503 tw32(0x7c00, val
| (1 << 25));
6506 /* Reprobe ASF enable state. */
6507 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6508 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6509 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6510 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6513 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6514 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6515 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6516 tp
->last_event_jiffies
= jiffies
;
6517 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6518 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6525 /* tp->lock is held. */
6526 static void tg3_stop_fw(struct tg3
*tp
)
6528 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6529 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6530 /* Wait for RX cpu to ACK the previous event. */
6531 tg3_wait_for_event_ack(tp
);
6533 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6535 tg3_generate_fw_event(tp
);
6537 /* Wait for RX cpu to ACK this event. */
6538 tg3_wait_for_event_ack(tp
);
6542 /* tp->lock is held. */
6543 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6549 tg3_write_sig_pre_reset(tp
, kind
);
6551 tg3_abort_hw(tp
, silent
);
6552 err
= tg3_chip_reset(tp
);
6554 __tg3_set_mac_addr(tp
, 0);
6556 tg3_write_sig_legacy(tp
, kind
);
6557 tg3_write_sig_post_reset(tp
, kind
);
6565 #define RX_CPU_SCRATCH_BASE 0x30000
6566 #define RX_CPU_SCRATCH_SIZE 0x04000
6567 #define TX_CPU_SCRATCH_BASE 0x34000
6568 #define TX_CPU_SCRATCH_SIZE 0x04000
6570 /* tp->lock is held. */
6571 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6575 BUG_ON(offset
== TX_CPU_BASE
&&
6576 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6578 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6579 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6581 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6584 if (offset
== RX_CPU_BASE
) {
6585 for (i
= 0; i
< 10000; i
++) {
6586 tw32(offset
+ CPU_STATE
, 0xffffffff);
6587 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6588 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6592 tw32(offset
+ CPU_STATE
, 0xffffffff);
6593 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6596 for (i
= 0; i
< 10000; i
++) {
6597 tw32(offset
+ CPU_STATE
, 0xffffffff);
6598 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6599 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6605 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6608 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6612 /* Clear firmware's nvram arbitration. */
6613 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6614 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6619 unsigned int fw_base
;
6620 unsigned int fw_len
;
6621 const __be32
*fw_data
;
6624 /* tp->lock is held. */
6625 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6626 int cpu_scratch_size
, struct fw_info
*info
)
6628 int err
, lock_err
, i
;
6629 void (*write_op
)(struct tg3
*, u32
, u32
);
6631 if (cpu_base
== TX_CPU_BASE
&&
6632 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6633 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6634 "TX cpu firmware on %s which is 5705.\n",
6639 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6640 write_op
= tg3_write_mem
;
6642 write_op
= tg3_write_indirect_reg32
;
6644 /* It is possible that bootcode is still loading at this point.
6645 * Get the nvram lock first before halting the cpu.
6647 lock_err
= tg3_nvram_lock(tp
);
6648 err
= tg3_halt_cpu(tp
, cpu_base
);
6650 tg3_nvram_unlock(tp
);
6654 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6655 write_op(tp
, cpu_scratch_base
+ i
, 0);
6656 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6657 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6658 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6659 write_op(tp
, (cpu_scratch_base
+
6660 (info
->fw_base
& 0xffff) +
6662 be32_to_cpu(info
->fw_data
[i
]));
6670 /* tp->lock is held. */
6671 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6673 struct fw_info info
;
6674 const __be32
*fw_data
;
6677 fw_data
= (void *)tp
->fw
->data
;
6679 /* Firmware blob starts with version numbers, followed by
6680 start address and length. We are setting complete length.
6681 length = end_address_of_bss - start_address_of_text.
6682 Remainder is the blob to be loaded contiguously
6683 from start address. */
6685 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6686 info
.fw_len
= tp
->fw
->size
- 12;
6687 info
.fw_data
= &fw_data
[3];
6689 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6690 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6695 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6696 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6701 /* Now startup only the RX cpu. */
6702 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6703 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6705 for (i
= 0; i
< 5; i
++) {
6706 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6708 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6709 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6710 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6714 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6715 "to set RX CPU PC, is %08x should be %08x\n",
6716 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6720 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6721 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6726 /* 5705 needs a special version of the TSO firmware. */
6728 /* tp->lock is held. */
6729 static int tg3_load_tso_firmware(struct tg3
*tp
)
6731 struct fw_info info
;
6732 const __be32
*fw_data
;
6733 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6736 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6739 fw_data
= (void *)tp
->fw
->data
;
6741 /* Firmware blob starts with version numbers, followed by
6742 start address and length. We are setting complete length.
6743 length = end_address_of_bss - start_address_of_text.
6744 Remainder is the blob to be loaded contiguously
6745 from start address. */
6747 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6748 cpu_scratch_size
= tp
->fw_len
;
6749 info
.fw_len
= tp
->fw
->size
- 12;
6750 info
.fw_data
= &fw_data
[3];
6752 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6753 cpu_base
= RX_CPU_BASE
;
6754 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6756 cpu_base
= TX_CPU_BASE
;
6757 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6758 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6761 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6762 cpu_scratch_base
, cpu_scratch_size
,
6767 /* Now startup the cpu. */
6768 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6769 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6771 for (i
= 0; i
< 5; i
++) {
6772 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6774 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6775 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6776 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6780 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6781 "to set CPU PC, is %08x should be %08x\n",
6782 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6786 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6787 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6792 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6794 struct tg3
*tp
= netdev_priv(dev
);
6795 struct sockaddr
*addr
= p
;
6796 int err
= 0, skip_mac_1
= 0;
6798 if (!is_valid_ether_addr(addr
->sa_data
))
6801 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6803 if (!netif_running(dev
))
6806 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6807 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6809 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6810 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6811 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6812 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6814 /* Skip MAC addr 1 if ASF is using it. */
6815 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6816 !(addr1_high
== 0 && addr1_low
== 0))
6819 spin_lock_bh(&tp
->lock
);
6820 __tg3_set_mac_addr(tp
, skip_mac_1
);
6821 spin_unlock_bh(&tp
->lock
);
6826 /* tp->lock is held. */
6827 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6828 dma_addr_t mapping
, u32 maxlen_flags
,
6832 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6833 ((u64
) mapping
>> 32));
6835 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6836 ((u64
) mapping
& 0xffffffff));
6838 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6841 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6843 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
6847 static void __tg3_set_rx_mode(struct net_device
*);
6848 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
6850 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
6851 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
6852 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
6853 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
6854 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6855 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
6856 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
6858 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
6859 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
6860 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6861 u32 val
= ec
->stats_block_coalesce_usecs
;
6863 if (!netif_carrier_ok(tp
->dev
))
6866 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
6870 /* tp->lock is held. */
6871 static void tg3_rings_reset(struct tg3
*tp
)
6874 u32 stblk
, txrcb
, rxrcb
, limit
;
6875 struct tg3_napi
*tnapi
= &tp
->napi
[0];
6877 /* Disable all transmit rings but the first. */
6878 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6879 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
6881 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
6883 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
6884 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
6885 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
6886 BDINFO_FLAGS_DISABLED
);
6889 /* Disable all receive return rings but the first. */
6890 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6891 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
6892 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
6893 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
6895 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
6897 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
6898 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
6899 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
6900 BDINFO_FLAGS_DISABLED
);
6902 /* Disable interrupts */
6903 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
6905 /* Zero mailbox registers. */
6906 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) {
6907 for (i
= 1; i
< TG3_IRQ_MAX_VECS
; i
++) {
6908 tp
->napi
[i
].tx_prod
= 0;
6909 tp
->napi
[i
].tx_cons
= 0;
6910 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
6911 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
6912 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
6915 tp
->napi
[0].tx_prod
= 0;
6916 tp
->napi
[0].tx_cons
= 0;
6917 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
6918 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
6921 /* Make sure the NIC-based send BD rings are disabled. */
6922 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6923 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
6924 for (i
= 0; i
< 16; i
++)
6925 tw32_tx_mbox(mbox
+ i
* 8, 0);
6928 txrcb
= NIC_SRAM_SEND_RCB
;
6929 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
6931 /* Clear status block in ram. */
6932 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6934 /* Set status block DMA address */
6935 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6936 ((u64
) tnapi
->status_mapping
>> 32));
6937 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6938 ((u64
) tnapi
->status_mapping
& 0xffffffff));
6940 if (tnapi
->tx_ring
) {
6941 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
6942 (TG3_TX_RING_SIZE
<<
6943 BDINFO_FLAGS_MAXLEN_SHIFT
),
6944 NIC_SRAM_TX_BUFFER_DESC
);
6945 txrcb
+= TG3_BDINFO_SIZE
;
6948 if (tnapi
->rx_rcb
) {
6949 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
6950 (TG3_RX_RCB_RING_SIZE(tp
) <<
6951 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
6952 rxrcb
+= TG3_BDINFO_SIZE
;
6955 stblk
= HOSTCC_STATBLCK_RING1
;
6957 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
6958 u64 mapping
= (u64
)tnapi
->status_mapping
;
6959 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
6960 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
6962 /* Clear status block in ram. */
6963 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6965 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
6966 (TG3_TX_RING_SIZE
<<
6967 BDINFO_FLAGS_MAXLEN_SHIFT
),
6968 NIC_SRAM_TX_BUFFER_DESC
);
6970 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
6971 (TG3_RX_RCB_RING_SIZE(tp
) <<
6972 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
6975 txrcb
+= TG3_BDINFO_SIZE
;
6976 rxrcb
+= TG3_BDINFO_SIZE
;
6980 /* tp->lock is held. */
6981 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
6983 u32 val
, rdmac_mode
;
6985 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
6987 tg3_disable_ints(tp
);
6991 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
6993 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
6994 tg3_abort_hw(tp
, 1);
6998 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
7001 err
= tg3_chip_reset(tp
);
7005 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
7007 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
7008 val
= tr32(TG3_CPMU_CTRL
);
7009 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
7010 tw32(TG3_CPMU_CTRL
, val
);
7012 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
7013 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
7014 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
7015 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
7017 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
7018 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
7019 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
7020 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
7022 val
= tr32(TG3_CPMU_HST_ACC
);
7023 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
7024 val
|= CPMU_HST_ACC_MACCLK_6_25
;
7025 tw32(TG3_CPMU_HST_ACC
, val
);
7028 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
7029 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
7030 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
7031 PCIE_PWR_MGMT_L1_THRESH_4MS
;
7032 tw32(PCIE_PWR_MGMT_THRESH
, val
);
7034 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
7035 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
7037 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
7040 if (tp
->tg3_flags3
& TG3_FLG3_TOGGLE_10_100_L1PLLPD
) {
7041 val
= tr32(TG3_PCIE_LNKCTL
);
7042 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
)
7043 val
|= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
;
7045 val
&= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
;
7046 tw32(TG3_PCIE_LNKCTL
, val
);
7049 /* This works around an issue with Athlon chipsets on
7050 * B3 tigon3 silicon. This bit has no effect on any
7051 * other revision. But do not set this on PCI Express
7052 * chips and don't even touch the clocks if the CPMU is present.
7054 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
7055 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
7056 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
7057 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
7060 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
7061 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
7062 val
= tr32(TG3PCI_PCISTATE
);
7063 val
|= PCISTATE_RETRY_SAME_DMA
;
7064 tw32(TG3PCI_PCISTATE
, val
);
7067 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
7068 /* Allow reads and writes to the
7069 * APE register and memory space.
7071 val
= tr32(TG3PCI_PCISTATE
);
7072 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
7073 PCISTATE_ALLOW_APE_SHMEM_WR
;
7074 tw32(TG3PCI_PCISTATE
, val
);
7077 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
7078 /* Enable some hw fixes. */
7079 val
= tr32(TG3PCI_MSI_DATA
);
7080 val
|= (1 << 26) | (1 << 28) | (1 << 29);
7081 tw32(TG3PCI_MSI_DATA
, val
);
7084 /* Descriptor ring init may make accesses to the
7085 * NIC SRAM area to setup the TX descriptors, so we
7086 * can only do this after the hardware has been
7087 * successfully reset.
7089 err
= tg3_init_rings(tp
);
7093 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7094 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7095 /* This value is determined during the probe time DMA
7096 * engine test, tg3_test_dma.
7098 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7101 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7102 GRC_MODE_4X_NIC_SEND_RINGS
|
7103 GRC_MODE_NO_TX_PHDR_CSUM
|
7104 GRC_MODE_NO_RX_PHDR_CSUM
);
7105 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7107 /* Pseudo-header checksum is done by hardware logic and not
7108 * the offload processers, so make the chip do the pseudo-
7109 * header checksums on receive. For transmit it is more
7110 * convenient to do the pseudo-header checksum in software
7111 * as Linux does that on transmit for us in all cases.
7113 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7117 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7119 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7120 val
= tr32(GRC_MISC_CFG
);
7122 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7123 tw32(GRC_MISC_CFG
, val
);
7125 /* Initialize MBUF/DESC pool. */
7126 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7128 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7129 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7130 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7131 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7133 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7134 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7135 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7137 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7140 fw_len
= tp
->fw_len
;
7141 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7142 tw32(BUFMGR_MB_POOL_ADDR
,
7143 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7144 tw32(BUFMGR_MB_POOL_SIZE
,
7145 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7148 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7149 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7150 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7151 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7152 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7153 tw32(BUFMGR_MB_HIGH_WATER
,
7154 tp
->bufmgr_config
.mbuf_high_water
);
7156 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7157 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7158 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7159 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7160 tw32(BUFMGR_MB_HIGH_WATER
,
7161 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7163 tw32(BUFMGR_DMA_LOW_WATER
,
7164 tp
->bufmgr_config
.dma_low_water
);
7165 tw32(BUFMGR_DMA_HIGH_WATER
,
7166 tp
->bufmgr_config
.dma_high_water
);
7168 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7169 for (i
= 0; i
< 2000; i
++) {
7170 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7175 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
7180 /* Setup replenish threshold. */
7181 val
= tp
->rx_pending
/ 8;
7184 else if (val
> tp
->rx_std_max_post
)
7185 val
= tp
->rx_std_max_post
;
7186 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7187 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7188 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7190 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7191 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7194 tw32(RCVBDI_STD_THRESH
, val
);
7196 /* Initialize TG3_BDINFO's at:
7197 * RCVDBDI_STD_BD: standard eth size rx ring
7198 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7199 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7202 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7203 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7204 * ring attribute flags
7205 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7207 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7208 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7210 * The size of each ring is fixed in the firmware, but the location is
7213 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7214 ((u64
) tpr
->rx_std_mapping
>> 32));
7215 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7216 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7217 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7218 NIC_SRAM_RX_BUFFER_DESC
);
7220 /* Disable the mini ring */
7221 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7222 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7223 BDINFO_FLAGS_DISABLED
);
7225 /* Program the jumbo buffer descriptor ring control
7226 * blocks on those devices that have them.
7228 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7229 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7230 /* Setup replenish threshold. */
7231 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7233 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7234 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7235 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7236 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7237 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7238 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7239 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7240 BDINFO_FLAGS_USE_EXT_RECV
);
7241 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7242 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7244 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7245 BDINFO_FLAGS_DISABLED
);
7248 val
= RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7250 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7252 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7254 tpr
->rx_std_ptr
= tp
->rx_pending
;
7255 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7258 tpr
->rx_jmb_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7259 tp
->rx_jumbo_pending
: 0;
7260 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7263 tg3_rings_reset(tp
);
7265 /* Initialize MAC address and backoff seed. */
7266 __tg3_set_mac_addr(tp
, 0);
7268 /* MTU + ethernet header + FCS + optional VLAN tag */
7269 tw32(MAC_RX_MTU_SIZE
,
7270 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7272 /* The slot time is changed by tg3_setup_phy if we
7273 * run at gigabit with half duplex.
7275 tw32(MAC_TX_LENGTHS
,
7276 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7277 (6 << TX_LENGTHS_IPG_SHIFT
) |
7278 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7280 /* Receive rules. */
7281 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7282 tw32(RCVLPC_CONFIG
, 0x0181);
7284 /* Calculate RDMAC_MODE setting early, we need it to determine
7285 * the RCVLPC_STATE_ENABLE mask.
7287 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7288 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7289 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7290 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7291 RDMAC_MODE_LNGREAD_ENAB
);
7293 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7294 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7295 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7296 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7297 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7298 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7300 /* If statement applies to 5705 and 5750 PCI devices only */
7301 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7302 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7303 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7304 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7305 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7306 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7307 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7308 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7309 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7313 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7314 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7316 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7317 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7319 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7320 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7321 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7323 /* Receive/send statistics. */
7324 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7325 val
= tr32(RCVLPC_STATS_ENABLE
);
7326 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7327 tw32(RCVLPC_STATS_ENABLE
, val
);
7328 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7329 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7330 val
= tr32(RCVLPC_STATS_ENABLE
);
7331 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
7332 tw32(RCVLPC_STATS_ENABLE
, val
);
7334 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
7336 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
7337 tw32(SNDDATAI_STATSENAB
, 0xffffff);
7338 tw32(SNDDATAI_STATSCTRL
,
7339 (SNDDATAI_SCTRL_ENABLE
|
7340 SNDDATAI_SCTRL_FASTUPD
));
7342 /* Setup host coalescing engine. */
7343 tw32(HOSTCC_MODE
, 0);
7344 for (i
= 0; i
< 2000; i
++) {
7345 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
7350 __tg3_set_coalesce(tp
, &tp
->coal
);
7352 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7353 /* Status/statistics block address. See tg3_timer,
7354 * the tg3_periodic_fetch_stats call there, and
7355 * tg3_get_stats to see how this works for 5705/5750 chips.
7357 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7358 ((u64
) tp
->stats_mapping
>> 32));
7359 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7360 ((u64
) tp
->stats_mapping
& 0xffffffff));
7361 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
7363 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
7365 /* Clear statistics and status block memory areas */
7366 for (i
= NIC_SRAM_STATS_BLK
;
7367 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
7369 tg3_write_mem(tp
, i
, 0);
7374 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
7376 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
7377 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
7378 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7379 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
7381 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7382 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
7383 /* reset to prevent losing 1st rx packet intermittently */
7384 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7388 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7389 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
7392 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
7393 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
7394 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7395 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7396 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
7397 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7398 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
7401 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7402 * If TG3_FLG2_IS_NIC is zero, we should read the
7403 * register to preserve the GPIO settings for LOMs. The GPIOs,
7404 * whether used as inputs or outputs, are set by boot code after
7407 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
7410 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
7411 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
7412 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
7414 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7415 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
7416 GRC_LCLCTRL_GPIO_OUTPUT3
;
7418 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7419 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
7421 tp
->grc_local_ctrl
&= ~gpio_mask
;
7422 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
7424 /* GPIO1 must be driven high for eeprom write protect */
7425 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
7426 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
7427 GRC_LCLCTRL_GPIO_OUTPUT1
);
7429 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7432 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7433 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7437 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7438 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7439 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7440 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7441 WDMAC_MODE_LNGREAD_ENAB
);
7443 /* If statement applies to 5705 and 5750 PCI devices only */
7444 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7445 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7446 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7447 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
7448 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7449 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7451 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7452 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7453 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7454 val
|= WDMAC_MODE_RX_ACCEL
;
7458 /* Enable host coalescing bug fix */
7459 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7460 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7462 tw32_f(WDMAC_MODE
, val
);
7465 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7468 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7470 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7471 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7472 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7473 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7474 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7475 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7477 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7481 tw32_f(RDMAC_MODE
, rdmac_mode
);
7484 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7485 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7486 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7488 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7490 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7492 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7494 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7495 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7496 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7497 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7498 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7499 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7500 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
7501 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7503 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7504 err
= tg3_load_5701_a0_firmware_fix(tp
);
7509 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7510 err
= tg3_load_tso_firmware(tp
);
7515 tp
->tx_mode
= TX_MODE_ENABLE
;
7516 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7519 tp
->rx_mode
= RX_MODE_ENABLE
;
7520 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7521 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7523 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7526 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7528 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7529 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7530 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7533 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7536 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7537 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7538 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7539 /* Set drive transmission level to 1.2V */
7540 /* only if the signal pre-emphasis bit is not set */
7541 val
= tr32(MAC_SERDES_CFG
);
7544 tw32(MAC_SERDES_CFG
, val
);
7546 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7547 tw32(MAC_SERDES_CFG
, 0x616000);
7550 /* Prevent chip from dropping frames when flow control
7553 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7555 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7556 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7557 /* Use hardware link auto-negotiation */
7558 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7561 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7562 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7565 tmp
= tr32(SERDES_RX_CTRL
);
7566 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7567 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7568 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7569 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7572 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7573 if (tp
->link_config
.phy_is_low_power
) {
7574 tp
->link_config
.phy_is_low_power
= 0;
7575 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7576 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7577 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7580 err
= tg3_setup_phy(tp
, 0);
7584 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7585 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
7588 /* Clear CRC stats. */
7589 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7590 tg3_writephy(tp
, MII_TG3_TEST1
,
7591 tmp
| MII_TG3_TEST1_CRC_EN
);
7592 tg3_readphy(tp
, 0x14, &tmp
);
7597 __tg3_set_rx_mode(tp
->dev
);
7599 /* Initialize receive rules. */
7600 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7601 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7602 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7603 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7605 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7606 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7610 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7614 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7616 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7618 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7620 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7622 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7624 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7626 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7628 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7630 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7632 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7634 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7636 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7638 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7640 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7648 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7649 /* Write our heartbeat update interval to APE. */
7650 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7651 APE_HOST_HEARTBEAT_INT_DISABLE
);
7653 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7658 /* Called at device open time to get the chip ready for
7659 * packet processing. Invoked with tp->lock held.
7661 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7663 tg3_switch_clocks(tp
);
7665 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7667 return tg3_reset_hw(tp
, reset_phy
);
7670 #define TG3_STAT_ADD32(PSTAT, REG) \
7671 do { u32 __val = tr32(REG); \
7672 (PSTAT)->low += __val; \
7673 if ((PSTAT)->low < __val) \
7674 (PSTAT)->high += 1; \
7677 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7679 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7681 if (!netif_carrier_ok(tp
->dev
))
7684 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7685 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7686 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7687 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7688 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7689 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7690 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7691 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7692 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7693 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7694 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7695 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7696 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7698 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7699 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7700 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7701 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7702 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7703 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7704 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7705 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7706 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7707 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7708 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7709 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7710 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7711 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7713 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7714 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7715 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7718 static void tg3_timer(unsigned long __opaque
)
7720 struct tg3
*tp
= (struct tg3
*) __opaque
;
7725 spin_lock(&tp
->lock
);
7727 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7728 /* All of this garbage is because when using non-tagged
7729 * IRQ status the mailbox/status_block protocol the chip
7730 * uses with the cpu is race prone.
7732 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
7733 tw32(GRC_LOCAL_CTRL
,
7734 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7736 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7737 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
7740 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7741 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7742 spin_unlock(&tp
->lock
);
7743 schedule_work(&tp
->reset_task
);
7748 /* This part only runs once per second. */
7749 if (!--tp
->timer_counter
) {
7750 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7751 tg3_periodic_fetch_stats(tp
);
7753 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
7757 mac_stat
= tr32(MAC_STATUS
);
7760 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
7761 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
7763 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
7767 tg3_setup_phy(tp
, 0);
7768 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
7769 u32 mac_stat
= tr32(MAC_STATUS
);
7772 if (netif_carrier_ok(tp
->dev
) &&
7773 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
7776 if (! netif_carrier_ok(tp
->dev
) &&
7777 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
7778 MAC_STATUS_SIGNAL_DET
))) {
7782 if (!tp
->serdes_counter
) {
7785 ~MAC_MODE_PORT_MODE_MASK
));
7787 tw32_f(MAC_MODE
, tp
->mac_mode
);
7790 tg3_setup_phy(tp
, 0);
7792 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
7793 tg3_serdes_parallel_detect(tp
);
7795 tp
->timer_counter
= tp
->timer_multiplier
;
7798 /* Heartbeat is only sent once every 2 seconds.
7800 * The heartbeat is to tell the ASF firmware that the host
7801 * driver is still alive. In the event that the OS crashes,
7802 * ASF needs to reset the hardware to free up the FIFO space
7803 * that may be filled with rx packets destined for the host.
7804 * If the FIFO is full, ASF will no longer function properly.
7806 * Unintended resets have been reported on real time kernels
7807 * where the timer doesn't run on time. Netpoll will also have
7810 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7811 * to check the ring condition when the heartbeat is expiring
7812 * before doing the reset. This will prevent most unintended
7815 if (!--tp
->asf_counter
) {
7816 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7817 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7818 tg3_wait_for_event_ack(tp
);
7820 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
7821 FWCMD_NICDRV_ALIVE3
);
7822 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
7823 /* 5 seconds timeout */
7824 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
7826 tg3_generate_fw_event(tp
);
7828 tp
->asf_counter
= tp
->asf_multiplier
;
7831 spin_unlock(&tp
->lock
);
7834 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7835 add_timer(&tp
->timer
);
7838 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
7841 unsigned long flags
;
7843 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
7845 if (tp
->irq_cnt
== 1)
7846 name
= tp
->dev
->name
;
7848 name
= &tnapi
->irq_lbl
[0];
7849 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
7850 name
[IFNAMSIZ
-1] = 0;
7853 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
7855 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
7857 flags
= IRQF_SAMPLE_RANDOM
;
7860 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7861 fn
= tg3_interrupt_tagged
;
7862 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
7865 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
7868 static int tg3_test_interrupt(struct tg3
*tp
)
7870 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7871 struct net_device
*dev
= tp
->dev
;
7872 int err
, i
, intr_ok
= 0;
7874 if (!netif_running(dev
))
7877 tg3_disable_ints(tp
);
7879 free_irq(tnapi
->irq_vec
, tnapi
);
7881 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
7882 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
7886 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
7887 tg3_enable_ints(tp
);
7889 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7892 for (i
= 0; i
< 5; i
++) {
7893 u32 int_mbox
, misc_host_ctrl
;
7895 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
7896 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
7898 if ((int_mbox
!= 0) ||
7899 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
7907 tg3_disable_ints(tp
);
7909 free_irq(tnapi
->irq_vec
, tnapi
);
7911 err
= tg3_request_irq(tp
, 0);
7922 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7923 * successfully restored
7925 static int tg3_test_msi(struct tg3
*tp
)
7930 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
7933 /* Turn off SERR reporting in case MSI terminates with Master
7936 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7937 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
7938 pci_cmd
& ~PCI_COMMAND_SERR
);
7940 err
= tg3_test_interrupt(tp
);
7942 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
7947 /* other failures */
7951 /* MSI test failed, go back to INTx mode */
7952 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
7953 "switching to INTx mode. Please report this failure to "
7954 "the PCI maintainer and include system chipset information.\n",
7957 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
7959 pci_disable_msi(tp
->pdev
);
7961 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7963 err
= tg3_request_irq(tp
, 0);
7967 /* Need to reset the chip because the MSI cycle may have terminated
7968 * with Master Abort.
7970 tg3_full_lock(tp
, 1);
7972 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7973 err
= tg3_init_hw(tp
, 1);
7975 tg3_full_unlock(tp
);
7978 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
7983 static int tg3_request_firmware(struct tg3
*tp
)
7985 const __be32
*fw_data
;
7987 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
7988 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
7989 tp
->dev
->name
, tp
->fw_needed
);
7993 fw_data
= (void *)tp
->fw
->data
;
7995 /* Firmware blob starts with version numbers, followed by
7996 * start address and _full_ length including BSS sections
7997 * (which must be longer than the actual data, of course
8000 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
8001 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
8002 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
8003 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
8004 release_firmware(tp
->fw
);
8009 /* We no longer need firmware; we have it. */
8010 tp
->fw_needed
= NULL
;
8014 static bool tg3_enable_msix(struct tg3
*tp
)
8016 int i
, rc
, cpus
= num_online_cpus();
8017 struct msix_entry msix_ent
[tp
->irq_max
];
8020 /* Just fallback to the simpler MSI mode. */
8024 * We want as many rx rings enabled as there are cpus.
8025 * The first MSIX vector only deals with link interrupts, etc,
8026 * so we add one to the number of vectors we are requesting.
8028 tp
->irq_cnt
= min_t(unsigned, cpus
+ 1, tp
->irq_max
);
8030 for (i
= 0; i
< tp
->irq_max
; i
++) {
8031 msix_ent
[i
].entry
= i
;
8032 msix_ent
[i
].vector
= 0;
8035 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
8037 if (rc
< TG3_RSS_MIN_NUM_MSIX_VECS
)
8039 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
8042 "%s: Requested %d MSI-X vectors, received %d\n",
8043 tp
->dev
->name
, tp
->irq_cnt
, rc
);
8047 for (i
= 0; i
< tp
->irq_max
; i
++)
8048 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
8053 static void tg3_ints_init(struct tg3
*tp
)
8055 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI_OR_MSIX
) &&
8056 !(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
8057 /* All MSI supporting chips should support tagged
8058 * status. Assert that this is the case.
8060 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
8061 "Not using MSI.\n", tp
->dev
->name
);
8065 if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
) && tg3_enable_msix(tp
))
8066 tp
->tg3_flags2
|= TG3_FLG2_USING_MSIX
;
8067 else if ((tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) &&
8068 pci_enable_msi(tp
->pdev
) == 0)
8069 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
8071 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI_OR_MSIX
) {
8072 u32 msi_mode
= tr32(MSGINT_MODE
);
8073 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
8076 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)) {
8078 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
8082 static void tg3_ints_fini(struct tg3
*tp
)
8084 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSIX
)
8085 pci_disable_msix(tp
->pdev
);
8086 else if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
)
8087 pci_disable_msi(tp
->pdev
);
8088 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI_OR_MSIX
;
8091 static int tg3_open(struct net_device
*dev
)
8093 struct tg3
*tp
= netdev_priv(dev
);
8096 if (tp
->fw_needed
) {
8097 err
= tg3_request_firmware(tp
);
8098 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
8102 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
8104 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
8105 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
8106 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
8108 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
8112 netif_carrier_off(tp
->dev
);
8114 err
= tg3_set_power_state(tp
, PCI_D0
);
8118 tg3_full_lock(tp
, 0);
8120 tg3_disable_ints(tp
);
8121 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8123 tg3_full_unlock(tp
);
8126 * Setup interrupts first so we know how
8127 * many NAPI resources to allocate
8131 /* The placement of this call is tied
8132 * to the setup and use of Host TX descriptors.
8134 err
= tg3_alloc_consistent(tp
);
8138 napi_enable(&tp
->napi
[0].napi
);
8140 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8141 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8142 err
= tg3_request_irq(tp
, i
);
8144 for (i
--; i
>= 0; i
--)
8145 free_irq(tnapi
->irq_vec
, tnapi
);
8153 tg3_full_lock(tp
, 0);
8155 err
= tg3_init_hw(tp
, 1);
8157 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8160 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8161 tp
->timer_offset
= HZ
;
8163 tp
->timer_offset
= HZ
/ 10;
8165 BUG_ON(tp
->timer_offset
> HZ
);
8166 tp
->timer_counter
= tp
->timer_multiplier
=
8167 (HZ
/ tp
->timer_offset
);
8168 tp
->asf_counter
= tp
->asf_multiplier
=
8169 ((HZ
/ tp
->timer_offset
) * 2);
8171 init_timer(&tp
->timer
);
8172 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8173 tp
->timer
.data
= (unsigned long) tp
;
8174 tp
->timer
.function
= tg3_timer
;
8177 tg3_full_unlock(tp
);
8182 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8183 err
= tg3_test_msi(tp
);
8186 tg3_full_lock(tp
, 0);
8187 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8189 tg3_full_unlock(tp
);
8194 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8195 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
) {
8196 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8198 tw32(PCIE_TRANSACTION_CFG
,
8199 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8206 tg3_full_lock(tp
, 0);
8208 add_timer(&tp
->timer
);
8209 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8210 tg3_enable_ints(tp
);
8212 tg3_full_unlock(tp
);
8214 netif_start_queue(dev
);
8219 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8220 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8221 free_irq(tnapi
->irq_vec
, tnapi
);
8225 napi_disable(&tp
->napi
[0].napi
);
8226 tg3_free_consistent(tp
);
8234 /*static*/ void tg3_dump_state(struct tg3
*tp
)
8236 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
8239 struct tg3_hw_status
*sblk
= tp
->napi
[0]->hw_status
;
8241 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
8242 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
8243 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8247 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8248 tr32(MAC_MODE
), tr32(MAC_STATUS
));
8249 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8250 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
8251 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8252 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
8253 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8254 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
8256 /* Send data initiator control block */
8257 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8258 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
8259 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8260 tr32(SNDDATAI_STATSCTRL
));
8262 /* Send data completion control block */
8263 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
8265 /* Send BD ring selector block */
8266 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8267 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
8269 /* Send BD initiator control block */
8270 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8271 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
8273 /* Send BD completion control block */
8274 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
8276 /* Receive list placement control block */
8277 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8278 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
8279 printk(" RCVLPC_STATSCTRL[%08x]\n",
8280 tr32(RCVLPC_STATSCTRL
));
8282 /* Receive data and receive BD initiator control block */
8283 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8284 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
8286 /* Receive data completion control block */
8287 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8290 /* Receive BD initiator control block */
8291 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8292 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
8294 /* Receive BD completion control block */
8295 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8296 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
8298 /* Receive list selector control block */
8299 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8300 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
8302 /* Mbuf cluster free block */
8303 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8304 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
8306 /* Host coalescing control block */
8307 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8308 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
8309 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8310 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8311 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8312 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8313 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8314 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8315 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8316 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
8317 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8318 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
8320 /* Memory arbiter control block */
8321 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8322 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
8324 /* Buffer manager control block */
8325 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8326 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
8327 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8328 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
8329 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8330 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8331 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
8332 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
8334 /* Read DMA control block */
8335 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8336 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
8338 /* Write DMA control block */
8339 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8340 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
8342 /* DMA completion block */
8343 printk("DEBUG: DMAC_MODE[%08x]\n",
8347 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8348 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
8349 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8350 tr32(GRC_LOCAL_CTRL
));
8353 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8354 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
8355 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
8356 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
8357 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
8358 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8359 tr32(RCVDBDI_STD_BD
+ 0x0),
8360 tr32(RCVDBDI_STD_BD
+ 0x4),
8361 tr32(RCVDBDI_STD_BD
+ 0x8),
8362 tr32(RCVDBDI_STD_BD
+ 0xc));
8363 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8364 tr32(RCVDBDI_MINI_BD
+ 0x0),
8365 tr32(RCVDBDI_MINI_BD
+ 0x4),
8366 tr32(RCVDBDI_MINI_BD
+ 0x8),
8367 tr32(RCVDBDI_MINI_BD
+ 0xc));
8369 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
8370 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
8371 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
8372 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
8373 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8374 val32
, val32_2
, val32_3
, val32_4
);
8376 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
8377 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
8378 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
8379 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
8380 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8381 val32
, val32_2
, val32_3
, val32_4
);
8383 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
8384 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
8385 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
8386 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
8387 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
8388 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8389 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
8391 /* SW status block */
8393 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8396 sblk
->rx_jumbo_consumer
,
8398 sblk
->rx_mini_consumer
,
8399 sblk
->idx
[0].rx_producer
,
8400 sblk
->idx
[0].tx_consumer
);
8402 /* SW statistics block */
8403 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8404 ((u32
*)tp
->hw_stats
)[0],
8405 ((u32
*)tp
->hw_stats
)[1],
8406 ((u32
*)tp
->hw_stats
)[2],
8407 ((u32
*)tp
->hw_stats
)[3]);
8410 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8411 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
8412 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
8413 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
8414 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
8416 /* NIC side send descriptors. */
8417 for (i
= 0; i
< 6; i
++) {
8420 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
8421 + (i
* sizeof(struct tg3_tx_buffer_desc
));
8422 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8424 readl(txd
+ 0x0), readl(txd
+ 0x4),
8425 readl(txd
+ 0x8), readl(txd
+ 0xc));
8428 /* NIC side RX descriptors. */
8429 for (i
= 0; i
< 6; i
++) {
8432 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
8433 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8434 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8436 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8437 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8438 rxd
+= (4 * sizeof(u32
));
8439 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8441 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8442 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8445 for (i
= 0; i
< 6; i
++) {
8448 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
8449 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8450 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8452 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8453 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8454 rxd
+= (4 * sizeof(u32
));
8455 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8457 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8458 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8463 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8464 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8466 static int tg3_close(struct net_device
*dev
)
8469 struct tg3
*tp
= netdev_priv(dev
);
8471 napi_disable(&tp
->napi
[0].napi
);
8472 cancel_work_sync(&tp
->reset_task
);
8474 netif_stop_queue(dev
);
8476 del_timer_sync(&tp
->timer
);
8478 tg3_full_lock(tp
, 1);
8483 tg3_disable_ints(tp
);
8485 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8487 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8489 tg3_full_unlock(tp
);
8491 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8492 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8493 free_irq(tnapi
->irq_vec
, tnapi
);
8498 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
8499 sizeof(tp
->net_stats_prev
));
8500 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
8501 sizeof(tp
->estats_prev
));
8503 tg3_free_consistent(tp
);
8505 tg3_set_power_state(tp
, PCI_D3hot
);
8507 netif_carrier_off(tp
->dev
);
8512 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8516 #if (BITS_PER_LONG == 32)
8519 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8524 static inline u64
get_estat64(tg3_stat64_t
*val
)
8526 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8529 static unsigned long calc_crc_errors(struct tg3
*tp
)
8531 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8533 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8534 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8535 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8538 spin_lock_bh(&tp
->lock
);
8539 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8540 tg3_writephy(tp
, MII_TG3_TEST1
,
8541 val
| MII_TG3_TEST1_CRC_EN
);
8542 tg3_readphy(tp
, 0x14, &val
);
8545 spin_unlock_bh(&tp
->lock
);
8547 tp
->phy_crc_errors
+= val
;
8549 return tp
->phy_crc_errors
;
8552 return get_stat64(&hw_stats
->rx_fcs_errors
);
8555 #define ESTAT_ADD(member) \
8556 estats->member = old_estats->member + \
8557 get_estat64(&hw_stats->member)
8559 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8561 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8562 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8563 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8568 ESTAT_ADD(rx_octets
);
8569 ESTAT_ADD(rx_fragments
);
8570 ESTAT_ADD(rx_ucast_packets
);
8571 ESTAT_ADD(rx_mcast_packets
);
8572 ESTAT_ADD(rx_bcast_packets
);
8573 ESTAT_ADD(rx_fcs_errors
);
8574 ESTAT_ADD(rx_align_errors
);
8575 ESTAT_ADD(rx_xon_pause_rcvd
);
8576 ESTAT_ADD(rx_xoff_pause_rcvd
);
8577 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8578 ESTAT_ADD(rx_xoff_entered
);
8579 ESTAT_ADD(rx_frame_too_long_errors
);
8580 ESTAT_ADD(rx_jabbers
);
8581 ESTAT_ADD(rx_undersize_packets
);
8582 ESTAT_ADD(rx_in_length_errors
);
8583 ESTAT_ADD(rx_out_length_errors
);
8584 ESTAT_ADD(rx_64_or_less_octet_packets
);
8585 ESTAT_ADD(rx_65_to_127_octet_packets
);
8586 ESTAT_ADD(rx_128_to_255_octet_packets
);
8587 ESTAT_ADD(rx_256_to_511_octet_packets
);
8588 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8589 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8590 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8591 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8592 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8593 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8595 ESTAT_ADD(tx_octets
);
8596 ESTAT_ADD(tx_collisions
);
8597 ESTAT_ADD(tx_xon_sent
);
8598 ESTAT_ADD(tx_xoff_sent
);
8599 ESTAT_ADD(tx_flow_control
);
8600 ESTAT_ADD(tx_mac_errors
);
8601 ESTAT_ADD(tx_single_collisions
);
8602 ESTAT_ADD(tx_mult_collisions
);
8603 ESTAT_ADD(tx_deferred
);
8604 ESTAT_ADD(tx_excessive_collisions
);
8605 ESTAT_ADD(tx_late_collisions
);
8606 ESTAT_ADD(tx_collide_2times
);
8607 ESTAT_ADD(tx_collide_3times
);
8608 ESTAT_ADD(tx_collide_4times
);
8609 ESTAT_ADD(tx_collide_5times
);
8610 ESTAT_ADD(tx_collide_6times
);
8611 ESTAT_ADD(tx_collide_7times
);
8612 ESTAT_ADD(tx_collide_8times
);
8613 ESTAT_ADD(tx_collide_9times
);
8614 ESTAT_ADD(tx_collide_10times
);
8615 ESTAT_ADD(tx_collide_11times
);
8616 ESTAT_ADD(tx_collide_12times
);
8617 ESTAT_ADD(tx_collide_13times
);
8618 ESTAT_ADD(tx_collide_14times
);
8619 ESTAT_ADD(tx_collide_15times
);
8620 ESTAT_ADD(tx_ucast_packets
);
8621 ESTAT_ADD(tx_mcast_packets
);
8622 ESTAT_ADD(tx_bcast_packets
);
8623 ESTAT_ADD(tx_carrier_sense_errors
);
8624 ESTAT_ADD(tx_discards
);
8625 ESTAT_ADD(tx_errors
);
8627 ESTAT_ADD(dma_writeq_full
);
8628 ESTAT_ADD(dma_write_prioq_full
);
8629 ESTAT_ADD(rxbds_empty
);
8630 ESTAT_ADD(rx_discards
);
8631 ESTAT_ADD(rx_errors
);
8632 ESTAT_ADD(rx_threshold_hit
);
8634 ESTAT_ADD(dma_readq_full
);
8635 ESTAT_ADD(dma_read_prioq_full
);
8636 ESTAT_ADD(tx_comp_queue_full
);
8638 ESTAT_ADD(ring_set_send_prod_index
);
8639 ESTAT_ADD(ring_status_update
);
8640 ESTAT_ADD(nic_irqs
);
8641 ESTAT_ADD(nic_avoided_irqs
);
8642 ESTAT_ADD(nic_tx_threshold_hit
);
8647 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8649 struct tg3
*tp
= netdev_priv(dev
);
8650 struct net_device_stats
*stats
= &tp
->net_stats
;
8651 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8652 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8657 stats
->rx_packets
= old_stats
->rx_packets
+
8658 get_stat64(&hw_stats
->rx_ucast_packets
) +
8659 get_stat64(&hw_stats
->rx_mcast_packets
) +
8660 get_stat64(&hw_stats
->rx_bcast_packets
);
8662 stats
->tx_packets
= old_stats
->tx_packets
+
8663 get_stat64(&hw_stats
->tx_ucast_packets
) +
8664 get_stat64(&hw_stats
->tx_mcast_packets
) +
8665 get_stat64(&hw_stats
->tx_bcast_packets
);
8667 stats
->rx_bytes
= old_stats
->rx_bytes
+
8668 get_stat64(&hw_stats
->rx_octets
);
8669 stats
->tx_bytes
= old_stats
->tx_bytes
+
8670 get_stat64(&hw_stats
->tx_octets
);
8672 stats
->rx_errors
= old_stats
->rx_errors
+
8673 get_stat64(&hw_stats
->rx_errors
);
8674 stats
->tx_errors
= old_stats
->tx_errors
+
8675 get_stat64(&hw_stats
->tx_errors
) +
8676 get_stat64(&hw_stats
->tx_mac_errors
) +
8677 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8678 get_stat64(&hw_stats
->tx_discards
);
8680 stats
->multicast
= old_stats
->multicast
+
8681 get_stat64(&hw_stats
->rx_mcast_packets
);
8682 stats
->collisions
= old_stats
->collisions
+
8683 get_stat64(&hw_stats
->tx_collisions
);
8685 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8686 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8687 get_stat64(&hw_stats
->rx_undersize_packets
);
8689 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8690 get_stat64(&hw_stats
->rxbds_empty
);
8691 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8692 get_stat64(&hw_stats
->rx_align_errors
);
8693 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8694 get_stat64(&hw_stats
->tx_discards
);
8695 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8696 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8698 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8699 calc_crc_errors(tp
);
8701 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8702 get_stat64(&hw_stats
->rx_discards
);
8707 static inline u32
calc_crc(unsigned char *buf
, int len
)
8715 for (j
= 0; j
< len
; j
++) {
8718 for (k
= 0; k
< 8; k
++) {
8732 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
8734 /* accept or reject all multicast frames */
8735 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
8736 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
8737 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
8738 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
8741 static void __tg3_set_rx_mode(struct net_device
*dev
)
8743 struct tg3
*tp
= netdev_priv(dev
);
8746 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
8747 RX_MODE_KEEP_VLAN_TAG
);
8749 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8752 #if TG3_VLAN_TAG_USED
8754 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8755 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8757 /* By definition, VLAN is disabled always in this
8760 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8761 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8764 if (dev
->flags
& IFF_PROMISC
) {
8765 /* Promiscuous mode. */
8766 rx_mode
|= RX_MODE_PROMISC
;
8767 } else if (dev
->flags
& IFF_ALLMULTI
) {
8768 /* Accept all multicast. */
8769 tg3_set_multi (tp
, 1);
8770 } else if (dev
->mc_count
< 1) {
8771 /* Reject all multicast. */
8772 tg3_set_multi (tp
, 0);
8774 /* Accept one or more multicast(s). */
8775 struct dev_mc_list
*mclist
;
8777 u32 mc_filter
[4] = { 0, };
8782 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
8783 i
++, mclist
= mclist
->next
) {
8785 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
8787 regidx
= (bit
& 0x60) >> 5;
8789 mc_filter
[regidx
] |= (1 << bit
);
8792 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
8793 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
8794 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
8795 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
8798 if (rx_mode
!= tp
->rx_mode
) {
8799 tp
->rx_mode
= rx_mode
;
8800 tw32_f(MAC_RX_MODE
, rx_mode
);
8805 static void tg3_set_rx_mode(struct net_device
*dev
)
8807 struct tg3
*tp
= netdev_priv(dev
);
8809 if (!netif_running(dev
))
8812 tg3_full_lock(tp
, 0);
8813 __tg3_set_rx_mode(dev
);
8814 tg3_full_unlock(tp
);
8817 #define TG3_REGDUMP_LEN (32 * 1024)
8819 static int tg3_get_regs_len(struct net_device
*dev
)
8821 return TG3_REGDUMP_LEN
;
8824 static void tg3_get_regs(struct net_device
*dev
,
8825 struct ethtool_regs
*regs
, void *_p
)
8828 struct tg3
*tp
= netdev_priv(dev
);
8834 memset(p
, 0, TG3_REGDUMP_LEN
);
8836 if (tp
->link_config
.phy_is_low_power
)
8839 tg3_full_lock(tp
, 0);
8841 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8842 #define GET_REG32_LOOP(base,len) \
8843 do { p = (u32 *)(orig_p + (base)); \
8844 for (i = 0; i < len; i += 4) \
8845 __GET_REG32((base) + i); \
8847 #define GET_REG32_1(reg) \
8848 do { p = (u32 *)(orig_p + (reg)); \
8849 __GET_REG32((reg)); \
8852 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
8853 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
8854 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
8855 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
8856 GET_REG32_1(SNDDATAC_MODE
);
8857 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
8858 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
8859 GET_REG32_1(SNDBDC_MODE
);
8860 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
8861 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
8862 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
8863 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
8864 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
8865 GET_REG32_1(RCVDCC_MODE
);
8866 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
8867 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
8868 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
8869 GET_REG32_1(MBFREE_MODE
);
8870 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
8871 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
8872 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
8873 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
8874 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
8875 GET_REG32_1(RX_CPU_MODE
);
8876 GET_REG32_1(RX_CPU_STATE
);
8877 GET_REG32_1(RX_CPU_PGMCTR
);
8878 GET_REG32_1(RX_CPU_HWBKPT
);
8879 GET_REG32_1(TX_CPU_MODE
);
8880 GET_REG32_1(TX_CPU_STATE
);
8881 GET_REG32_1(TX_CPU_PGMCTR
);
8882 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
8883 GET_REG32_LOOP(FTQ_RESET
, 0x120);
8884 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
8885 GET_REG32_1(DMAC_MODE
);
8886 GET_REG32_LOOP(GRC_MODE
, 0x4c);
8887 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
8888 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
8891 #undef GET_REG32_LOOP
8894 tg3_full_unlock(tp
);
8897 static int tg3_get_eeprom_len(struct net_device
*dev
)
8899 struct tg3
*tp
= netdev_priv(dev
);
8901 return tp
->nvram_size
;
8904 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8906 struct tg3
*tp
= netdev_priv(dev
);
8909 u32 i
, offset
, len
, b_offset
, b_count
;
8912 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
8915 if (tp
->link_config
.phy_is_low_power
)
8918 offset
= eeprom
->offset
;
8922 eeprom
->magic
= TG3_EEPROM_MAGIC
;
8925 /* adjustments to start on required 4 byte boundary */
8926 b_offset
= offset
& 3;
8927 b_count
= 4 - b_offset
;
8928 if (b_count
> len
) {
8929 /* i.e. offset=1 len=2 */
8932 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
8935 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
8938 eeprom
->len
+= b_count
;
8941 /* read bytes upto the last 4 byte boundary */
8942 pd
= &data
[eeprom
->len
];
8943 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
8944 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
8949 memcpy(pd
+ i
, &val
, 4);
8954 /* read last bytes not ending on 4 byte boundary */
8955 pd
= &data
[eeprom
->len
];
8957 b_offset
= offset
+ len
- b_count
;
8958 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
8961 memcpy(pd
, &val
, b_count
);
8962 eeprom
->len
+= b_count
;
8967 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
8969 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8971 struct tg3
*tp
= netdev_priv(dev
);
8973 u32 offset
, len
, b_offset
, odd_len
;
8977 if (tp
->link_config
.phy_is_low_power
)
8980 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
8981 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
8984 offset
= eeprom
->offset
;
8987 if ((b_offset
= (offset
& 3))) {
8988 /* adjustments to start on required 4 byte boundary */
8989 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
9000 /* adjustments to end on required 4 byte boundary */
9002 len
= (len
+ 3) & ~3;
9003 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
9009 if (b_offset
|| odd_len
) {
9010 buf
= kmalloc(len
, GFP_KERNEL
);
9014 memcpy(buf
, &start
, 4);
9016 memcpy(buf
+len
-4, &end
, 4);
9017 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
9020 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
9028 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9030 struct tg3
*tp
= netdev_priv(dev
);
9032 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9033 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9035 return phy_ethtool_gset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
9038 cmd
->supported
= (SUPPORTED_Autoneg
);
9040 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
9041 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
9042 SUPPORTED_1000baseT_Full
);
9044 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
9045 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
9046 SUPPORTED_100baseT_Full
|
9047 SUPPORTED_10baseT_Half
|
9048 SUPPORTED_10baseT_Full
|
9050 cmd
->port
= PORT_TP
;
9052 cmd
->supported
|= SUPPORTED_FIBRE
;
9053 cmd
->port
= PORT_FIBRE
;
9056 cmd
->advertising
= tp
->link_config
.advertising
;
9057 if (netif_running(dev
)) {
9058 cmd
->speed
= tp
->link_config
.active_speed
;
9059 cmd
->duplex
= tp
->link_config
.active_duplex
;
9061 cmd
->phy_address
= PHY_ADDR
;
9062 cmd
->transceiver
= XCVR_INTERNAL
;
9063 cmd
->autoneg
= tp
->link_config
.autoneg
;
9069 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
9071 struct tg3
*tp
= netdev_priv(dev
);
9073 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9074 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9076 return phy_ethtool_sset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
9079 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
9080 cmd
->autoneg
!= AUTONEG_DISABLE
)
9083 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
9084 cmd
->duplex
!= DUPLEX_FULL
&&
9085 cmd
->duplex
!= DUPLEX_HALF
)
9088 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9089 u32 mask
= ADVERTISED_Autoneg
|
9091 ADVERTISED_Asym_Pause
;
9093 if (!(tp
->tg3_flags2
& TG3_FLAG_10_100_ONLY
))
9094 mask
|= ADVERTISED_1000baseT_Half
|
9095 ADVERTISED_1000baseT_Full
;
9097 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
9098 mask
|= ADVERTISED_100baseT_Half
|
9099 ADVERTISED_100baseT_Full
|
9100 ADVERTISED_10baseT_Half
|
9101 ADVERTISED_10baseT_Full
|
9104 mask
|= ADVERTISED_FIBRE
;
9106 if (cmd
->advertising
& ~mask
)
9109 mask
&= (ADVERTISED_1000baseT_Half
|
9110 ADVERTISED_1000baseT_Full
|
9111 ADVERTISED_100baseT_Half
|
9112 ADVERTISED_100baseT_Full
|
9113 ADVERTISED_10baseT_Half
|
9114 ADVERTISED_10baseT_Full
);
9116 cmd
->advertising
&= mask
;
9118 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
9119 if (cmd
->speed
!= SPEED_1000
)
9122 if (cmd
->duplex
!= DUPLEX_FULL
)
9125 if (cmd
->speed
!= SPEED_100
&&
9126 cmd
->speed
!= SPEED_10
)
9131 tg3_full_lock(tp
, 0);
9133 tp
->link_config
.autoneg
= cmd
->autoneg
;
9134 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
9135 tp
->link_config
.advertising
= (cmd
->advertising
|
9136 ADVERTISED_Autoneg
);
9137 tp
->link_config
.speed
= SPEED_INVALID
;
9138 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9140 tp
->link_config
.advertising
= 0;
9141 tp
->link_config
.speed
= cmd
->speed
;
9142 tp
->link_config
.duplex
= cmd
->duplex
;
9145 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9146 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9147 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9149 if (netif_running(dev
))
9150 tg3_setup_phy(tp
, 1);
9152 tg3_full_unlock(tp
);
9157 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9159 struct tg3
*tp
= netdev_priv(dev
);
9161 strcpy(info
->driver
, DRV_MODULE_NAME
);
9162 strcpy(info
->version
, DRV_MODULE_VERSION
);
9163 strcpy(info
->fw_version
, tp
->fw_ver
);
9164 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9167 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9169 struct tg3
*tp
= netdev_priv(dev
);
9171 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9172 device_can_wakeup(&tp
->pdev
->dev
))
9173 wol
->supported
= WAKE_MAGIC
;
9177 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9178 device_can_wakeup(&tp
->pdev
->dev
))
9179 wol
->wolopts
= WAKE_MAGIC
;
9180 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9183 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9185 struct tg3
*tp
= netdev_priv(dev
);
9186 struct device
*dp
= &tp
->pdev
->dev
;
9188 if (wol
->wolopts
& ~WAKE_MAGIC
)
9190 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9191 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9194 spin_lock_bh(&tp
->lock
);
9195 if (wol
->wolopts
& WAKE_MAGIC
) {
9196 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9197 device_set_wakeup_enable(dp
, true);
9199 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9200 device_set_wakeup_enable(dp
, false);
9202 spin_unlock_bh(&tp
->lock
);
9207 static u32
tg3_get_msglevel(struct net_device
*dev
)
9209 struct tg3
*tp
= netdev_priv(dev
);
9210 return tp
->msg_enable
;
9213 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9215 struct tg3
*tp
= netdev_priv(dev
);
9216 tp
->msg_enable
= value
;
9219 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9221 struct tg3
*tp
= netdev_priv(dev
);
9223 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9228 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9229 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
9231 dev
->features
|= NETIF_F_TSO6
;
9232 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9233 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9234 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9235 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9236 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9237 dev
->features
|= NETIF_F_TSO_ECN
;
9239 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9241 return ethtool_op_set_tso(dev
, value
);
9244 static int tg3_nway_reset(struct net_device
*dev
)
9246 struct tg3
*tp
= netdev_priv(dev
);
9249 if (!netif_running(dev
))
9252 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9255 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9256 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9258 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
9262 spin_lock_bh(&tp
->lock
);
9264 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9265 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9266 ((bmcr
& BMCR_ANENABLE
) ||
9267 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9268 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9272 spin_unlock_bh(&tp
->lock
);
9278 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9280 struct tg3
*tp
= netdev_priv(dev
);
9282 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9283 ering
->rx_mini_max_pending
= 0;
9284 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9285 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9287 ering
->rx_jumbo_max_pending
= 0;
9289 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9291 ering
->rx_pending
= tp
->rx_pending
;
9292 ering
->rx_mini_pending
= 0;
9293 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9294 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9296 ering
->rx_jumbo_pending
= 0;
9298 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9301 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9303 struct tg3
*tp
= netdev_priv(dev
);
9304 int i
, irq_sync
= 0, err
= 0;
9306 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9307 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9308 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9309 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9310 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9311 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9314 if (netif_running(dev
)) {
9320 tg3_full_lock(tp
, irq_sync
);
9322 tp
->rx_pending
= ering
->rx_pending
;
9324 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9325 tp
->rx_pending
> 63)
9326 tp
->rx_pending
= 63;
9327 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9329 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++)
9330 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
9332 if (netif_running(dev
)) {
9333 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9334 err
= tg3_restart_hw(tp
, 1);
9336 tg3_netif_start(tp
);
9339 tg3_full_unlock(tp
);
9341 if (irq_sync
&& !err
)
9347 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9349 struct tg3
*tp
= netdev_priv(dev
);
9351 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9353 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9354 epause
->rx_pause
= 1;
9356 epause
->rx_pause
= 0;
9358 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9359 epause
->tx_pause
= 1;
9361 epause
->tx_pause
= 0;
9364 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9366 struct tg3
*tp
= netdev_priv(dev
);
9369 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9370 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9373 if (epause
->autoneg
) {
9375 struct phy_device
*phydev
;
9377 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
9379 if (epause
->rx_pause
) {
9380 if (epause
->tx_pause
)
9381 newadv
= ADVERTISED_Pause
;
9383 newadv
= ADVERTISED_Pause
|
9384 ADVERTISED_Asym_Pause
;
9385 } else if (epause
->tx_pause
) {
9386 newadv
= ADVERTISED_Asym_Pause
;
9390 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9391 u32 oldadv
= phydev
->advertising
&
9393 ADVERTISED_Asym_Pause
);
9394 if (oldadv
!= newadv
) {
9395 phydev
->advertising
&=
9396 ~(ADVERTISED_Pause
|
9397 ADVERTISED_Asym_Pause
);
9398 phydev
->advertising
|= newadv
;
9399 err
= phy_start_aneg(phydev
);
9402 tp
->link_config
.advertising
&=
9403 ~(ADVERTISED_Pause
|
9404 ADVERTISED_Asym_Pause
);
9405 tp
->link_config
.advertising
|= newadv
;
9408 if (epause
->rx_pause
)
9409 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9411 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9413 if (epause
->tx_pause
)
9414 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9416 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9418 if (netif_running(dev
))
9419 tg3_setup_flow_control(tp
, 0, 0);
9424 if (netif_running(dev
)) {
9429 tg3_full_lock(tp
, irq_sync
);
9431 if (epause
->autoneg
)
9432 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9434 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9435 if (epause
->rx_pause
)
9436 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9438 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9439 if (epause
->tx_pause
)
9440 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9442 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9444 if (netif_running(dev
)) {
9445 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9446 err
= tg3_restart_hw(tp
, 1);
9448 tg3_netif_start(tp
);
9451 tg3_full_unlock(tp
);
9457 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9459 struct tg3
*tp
= netdev_priv(dev
);
9460 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9463 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9465 struct tg3
*tp
= netdev_priv(dev
);
9467 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9473 spin_lock_bh(&tp
->lock
);
9475 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9477 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9478 spin_unlock_bh(&tp
->lock
);
9483 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
9485 struct tg3
*tp
= netdev_priv(dev
);
9487 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9493 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9494 ethtool_op_set_tx_ipv6_csum(dev
, data
);
9496 ethtool_op_set_tx_csum(dev
, data
);
9501 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
9505 return TG3_NUM_TEST
;
9507 return TG3_NUM_STATS
;
9513 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
9515 switch (stringset
) {
9517 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
9520 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
9523 WARN_ON(1); /* we need a WARN() */
9528 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
9530 struct tg3
*tp
= netdev_priv(dev
);
9533 if (!netif_running(tp
->dev
))
9537 data
= UINT_MAX
/ 2;
9539 for (i
= 0; i
< (data
* 2); i
++) {
9541 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9542 LED_CTRL_1000MBPS_ON
|
9543 LED_CTRL_100MBPS_ON
|
9544 LED_CTRL_10MBPS_ON
|
9545 LED_CTRL_TRAFFIC_OVERRIDE
|
9546 LED_CTRL_TRAFFIC_BLINK
|
9547 LED_CTRL_TRAFFIC_LED
);
9550 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9551 LED_CTRL_TRAFFIC_OVERRIDE
);
9553 if (msleep_interruptible(500))
9556 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9560 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9561 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9563 struct tg3
*tp
= netdev_priv(dev
);
9564 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9567 #define NVRAM_TEST_SIZE 0x100
9568 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9569 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9570 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9571 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9572 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9574 static int tg3_test_nvram(struct tg3
*tp
)
9578 int i
, j
, k
, err
= 0, size
;
9580 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9583 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
9586 if (magic
== TG3_EEPROM_MAGIC
)
9587 size
= NVRAM_TEST_SIZE
;
9588 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9589 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9590 TG3_EEPROM_SB_FORMAT_1
) {
9591 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9592 case TG3_EEPROM_SB_REVISION_0
:
9593 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9595 case TG3_EEPROM_SB_REVISION_2
:
9596 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9598 case TG3_EEPROM_SB_REVISION_3
:
9599 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9606 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9607 size
= NVRAM_SELFBOOT_HW_SIZE
;
9611 buf
= kmalloc(size
, GFP_KERNEL
);
9616 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9617 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
9624 /* Selfboot format */
9625 magic
= be32_to_cpu(buf
[0]);
9626 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9627 TG3_EEPROM_MAGIC_FW
) {
9628 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9630 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9631 TG3_EEPROM_SB_REVISION_2
) {
9632 /* For rev 2, the csum doesn't include the MBA. */
9633 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9635 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9638 for (i
= 0; i
< size
; i
++)
9651 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9652 TG3_EEPROM_MAGIC_HW
) {
9653 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9654 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9655 u8
*buf8
= (u8
*) buf
;
9657 /* Separate the parity bits and the data bytes. */
9658 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9659 if ((i
== 0) || (i
== 8)) {
9663 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9664 parity
[k
++] = buf8
[i
] & msk
;
9671 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9672 parity
[k
++] = buf8
[i
] & msk
;
9675 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9676 parity
[k
++] = buf8
[i
] & msk
;
9679 data
[j
++] = buf8
[i
];
9683 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9684 u8 hw8
= hweight8(data
[i
]);
9686 if ((hw8
& 0x1) && parity
[i
])
9688 else if (!(hw8
& 0x1) && !parity
[i
])
9695 /* Bootstrap checksum at offset 0x10 */
9696 csum
= calc_crc((unsigned char *) buf
, 0x10);
9697 if (csum
!= be32_to_cpu(buf
[0x10/4]))
9700 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9701 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9702 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
9712 #define TG3_SERDES_TIMEOUT_SEC 2
9713 #define TG3_COPPER_TIMEOUT_SEC 6
9715 static int tg3_test_link(struct tg3
*tp
)
9719 if (!netif_running(tp
->dev
))
9722 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
9723 max
= TG3_SERDES_TIMEOUT_SEC
;
9725 max
= TG3_COPPER_TIMEOUT_SEC
;
9727 for (i
= 0; i
< max
; i
++) {
9728 if (netif_carrier_ok(tp
->dev
))
9731 if (msleep_interruptible(1000))
9738 /* Only test the commonly used registers */
9739 static int tg3_test_registers(struct tg3
*tp
)
9741 int i
, is_5705
, is_5750
;
9742 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
9746 #define TG3_FL_5705 0x1
9747 #define TG3_FL_NOT_5705 0x2
9748 #define TG3_FL_NOT_5788 0x4
9749 #define TG3_FL_NOT_5750 0x8
9753 /* MAC Control Registers */
9754 { MAC_MODE
, TG3_FL_NOT_5705
,
9755 0x00000000, 0x00ef6f8c },
9756 { MAC_MODE
, TG3_FL_5705
,
9757 0x00000000, 0x01ef6b8c },
9758 { MAC_STATUS
, TG3_FL_NOT_5705
,
9759 0x03800107, 0x00000000 },
9760 { MAC_STATUS
, TG3_FL_5705
,
9761 0x03800100, 0x00000000 },
9762 { MAC_ADDR_0_HIGH
, 0x0000,
9763 0x00000000, 0x0000ffff },
9764 { MAC_ADDR_0_LOW
, 0x0000,
9765 0x00000000, 0xffffffff },
9766 { MAC_RX_MTU_SIZE
, 0x0000,
9767 0x00000000, 0x0000ffff },
9768 { MAC_TX_MODE
, 0x0000,
9769 0x00000000, 0x00000070 },
9770 { MAC_TX_LENGTHS
, 0x0000,
9771 0x00000000, 0x00003fff },
9772 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
9773 0x00000000, 0x000007fc },
9774 { MAC_RX_MODE
, TG3_FL_5705
,
9775 0x00000000, 0x000007dc },
9776 { MAC_HASH_REG_0
, 0x0000,
9777 0x00000000, 0xffffffff },
9778 { MAC_HASH_REG_1
, 0x0000,
9779 0x00000000, 0xffffffff },
9780 { MAC_HASH_REG_2
, 0x0000,
9781 0x00000000, 0xffffffff },
9782 { MAC_HASH_REG_3
, 0x0000,
9783 0x00000000, 0xffffffff },
9785 /* Receive Data and Receive BD Initiator Control Registers. */
9786 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
9787 0x00000000, 0xffffffff },
9788 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
9789 0x00000000, 0xffffffff },
9790 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
9791 0x00000000, 0x00000003 },
9792 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
9793 0x00000000, 0xffffffff },
9794 { RCVDBDI_STD_BD
+0, 0x0000,
9795 0x00000000, 0xffffffff },
9796 { RCVDBDI_STD_BD
+4, 0x0000,
9797 0x00000000, 0xffffffff },
9798 { RCVDBDI_STD_BD
+8, 0x0000,
9799 0x00000000, 0xffff0002 },
9800 { RCVDBDI_STD_BD
+0xc, 0x0000,
9801 0x00000000, 0xffffffff },
9803 /* Receive BD Initiator Control Registers. */
9804 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
9805 0x00000000, 0xffffffff },
9806 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
9807 0x00000000, 0x000003ff },
9808 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
9809 0x00000000, 0xffffffff },
9811 /* Host Coalescing Control Registers. */
9812 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
9813 0x00000000, 0x00000004 },
9814 { HOSTCC_MODE
, TG3_FL_5705
,
9815 0x00000000, 0x000000f6 },
9816 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
9817 0x00000000, 0xffffffff },
9818 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
9819 0x00000000, 0x000003ff },
9820 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
9821 0x00000000, 0xffffffff },
9822 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
9823 0x00000000, 0x000003ff },
9824 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
9825 0x00000000, 0xffffffff },
9826 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9827 0x00000000, 0x000000ff },
9828 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
9829 0x00000000, 0xffffffff },
9830 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9831 0x00000000, 0x000000ff },
9832 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9833 0x00000000, 0xffffffff },
9834 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9835 0x00000000, 0xffffffff },
9836 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9837 0x00000000, 0xffffffff },
9838 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9839 0x00000000, 0x000000ff },
9840 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9841 0x00000000, 0xffffffff },
9842 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9843 0x00000000, 0x000000ff },
9844 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
9845 0x00000000, 0xffffffff },
9846 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
9847 0x00000000, 0xffffffff },
9848 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
9849 0x00000000, 0xffffffff },
9850 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
9851 0x00000000, 0xffffffff },
9852 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
9853 0x00000000, 0xffffffff },
9854 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
9855 0xffffffff, 0x00000000 },
9856 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
9857 0xffffffff, 0x00000000 },
9859 /* Buffer Manager Control Registers. */
9860 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
9861 0x00000000, 0x007fff80 },
9862 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
9863 0x00000000, 0x007fffff },
9864 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
9865 0x00000000, 0x0000003f },
9866 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
9867 0x00000000, 0x000001ff },
9868 { BUFMGR_MB_HIGH_WATER
, 0x0000,
9869 0x00000000, 0x000001ff },
9870 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
9871 0xffffffff, 0x00000000 },
9872 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
9873 0xffffffff, 0x00000000 },
9875 /* Mailbox Registers */
9876 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
9877 0x00000000, 0x000001ff },
9878 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
9879 0x00000000, 0x000001ff },
9880 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
9881 0x00000000, 0x000007ff },
9882 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
9883 0x00000000, 0x000001ff },
9885 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9888 is_5705
= is_5750
= 0;
9889 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9891 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
9895 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
9896 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
9899 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
9902 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9903 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
9906 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
9909 offset
= (u32
) reg_tbl
[i
].offset
;
9910 read_mask
= reg_tbl
[i
].read_mask
;
9911 write_mask
= reg_tbl
[i
].write_mask
;
9913 /* Save the original register content */
9914 save_val
= tr32(offset
);
9916 /* Determine the read-only value. */
9917 read_val
= save_val
& read_mask
;
9919 /* Write zero to the register, then make sure the read-only bits
9920 * are not changed and the read/write bits are all zeros.
9926 /* Test the read-only and read/write bits. */
9927 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
9930 /* Write ones to all the bits defined by RdMask and WrMask, then
9931 * make sure the read-only bits are not changed and the
9932 * read/write bits are all ones.
9934 tw32(offset
, read_mask
| write_mask
);
9938 /* Test the read-only bits. */
9939 if ((val
& read_mask
) != read_val
)
9942 /* Test the read/write bits. */
9943 if ((val
& write_mask
) != write_mask
)
9946 tw32(offset
, save_val
);
9952 if (netif_msg_hw(tp
))
9953 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
9955 tw32(offset
, save_val
);
9959 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
9961 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9965 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
9966 for (j
= 0; j
< len
; j
+= 4) {
9969 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
9970 tg3_read_mem(tp
, offset
+ j
, &val
);
9971 if (val
!= test_pattern
[i
])
9978 static int tg3_test_memory(struct tg3
*tp
)
9980 static struct mem_entry
{
9983 } mem_tbl_570x
[] = {
9984 { 0x00000000, 0x00b50},
9985 { 0x00002000, 0x1c000},
9986 { 0xffffffff, 0x00000}
9987 }, mem_tbl_5705
[] = {
9988 { 0x00000100, 0x0000c},
9989 { 0x00000200, 0x00008},
9990 { 0x00004000, 0x00800},
9991 { 0x00006000, 0x01000},
9992 { 0x00008000, 0x02000},
9993 { 0x00010000, 0x0e000},
9994 { 0xffffffff, 0x00000}
9995 }, mem_tbl_5755
[] = {
9996 { 0x00000200, 0x00008},
9997 { 0x00004000, 0x00800},
9998 { 0x00006000, 0x00800},
9999 { 0x00008000, 0x02000},
10000 { 0x00010000, 0x0c000},
10001 { 0xffffffff, 0x00000}
10002 }, mem_tbl_5906
[] = {
10003 { 0x00000200, 0x00008},
10004 { 0x00004000, 0x00400},
10005 { 0x00006000, 0x00400},
10006 { 0x00008000, 0x01000},
10007 { 0x00010000, 0x01000},
10008 { 0xffffffff, 0x00000}
10010 struct mem_entry
*mem_tbl
;
10014 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
10015 mem_tbl
= mem_tbl_5755
;
10016 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10017 mem_tbl
= mem_tbl_5906
;
10018 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
10019 mem_tbl
= mem_tbl_5705
;
10021 mem_tbl
= mem_tbl_570x
;
10023 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
10024 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
10025 mem_tbl
[i
].len
)) != 0)
10032 #define TG3_MAC_LOOPBACK 0
10033 #define TG3_PHY_LOOPBACK 1
10035 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
10037 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
10038 u32 desc_idx
, coal_now
;
10039 struct sk_buff
*skb
, *rx_skb
;
10042 int num_pkts
, tx_len
, rx_len
, i
, err
;
10043 struct tg3_rx_buffer_desc
*desc
;
10044 struct tg3_napi
*tnapi
, *rnapi
;
10045 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
10047 tnapi
= &tp
->napi
[0];
10048 rnapi
= &tp
->napi
[0];
10049 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
10051 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
10052 /* HW errata - mac loopback fails in some cases on 5780.
10053 * Normal traffic and PHY loopback are not affected by
10056 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
10059 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
10060 MAC_MODE_PORT_INT_LPBACK
;
10061 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10062 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10063 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
10064 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10066 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10067 tw32(MAC_MODE
, mac_mode
);
10068 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
10071 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10072 tg3_phy_fet_toggle_apd(tp
, false);
10073 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
10075 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
10077 tg3_phy_toggle_automdix(tp
, 0);
10079 tg3_writephy(tp
, MII_BMCR
, val
);
10082 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
10083 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
10084 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10085 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x1800);
10086 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
10088 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
10090 /* reset to prevent losing 1st rx packet intermittently */
10091 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
10092 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10094 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10096 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
10097 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
10098 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
10099 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
10100 mac_mode
|= MAC_MODE_LINK_POLARITY
;
10101 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
10102 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
10104 tw32(MAC_MODE
, mac_mode
);
10112 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
10116 tx_data
= skb_put(skb
, tx_len
);
10117 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
10118 memset(tx_data
+ 6, 0x0, 8);
10120 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
10122 for (i
= 14; i
< tx_len
; i
++)
10123 tx_data
[i
] = (u8
) (i
& 0xff);
10125 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
10127 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10132 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10136 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10141 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10142 tr32_mailbox(tnapi
->prodmbox
);
10146 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10147 for (i
= 0; i
< 25; i
++) {
10148 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10153 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10154 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10155 if ((tx_idx
== tnapi
->tx_prod
) &&
10156 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10160 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10161 dev_kfree_skb(skb
);
10163 if (tx_idx
!= tnapi
->tx_prod
)
10166 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10169 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10170 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10171 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10172 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10175 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10176 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10179 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10180 if (rx_len
!= tx_len
)
10183 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10185 map
= pci_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10186 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10188 for (i
= 14; i
< tx_len
; i
++) {
10189 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10194 /* tg3_free_rings will unmap and free the rx_skb */
10199 #define TG3_MAC_LOOPBACK_FAILED 1
10200 #define TG3_PHY_LOOPBACK_FAILED 2
10201 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10202 TG3_PHY_LOOPBACK_FAILED)
10204 static int tg3_test_loopback(struct tg3
*tp
)
10209 if (!netif_running(tp
->dev
))
10210 return TG3_LOOPBACK_FAILED
;
10212 err
= tg3_reset_hw(tp
, 1);
10214 return TG3_LOOPBACK_FAILED
;
10216 /* Turn off gphy autopowerdown. */
10217 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10218 tg3_phy_toggle_apd(tp
, false);
10220 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10224 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10226 /* Wait for up to 40 microseconds to acquire lock. */
10227 for (i
= 0; i
< 4; i
++) {
10228 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10229 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10234 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10235 return TG3_LOOPBACK_FAILED
;
10237 /* Turn off link-based power management. */
10238 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10239 tw32(TG3_CPMU_CTRL
,
10240 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10241 CPMU_CTRL_LINK_AWARE_MODE
));
10244 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10245 err
|= TG3_MAC_LOOPBACK_FAILED
;
10247 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10248 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10250 /* Release the mutex */
10251 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10254 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10255 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10256 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10257 err
|= TG3_PHY_LOOPBACK_FAILED
;
10260 /* Re-enable gphy autopowerdown. */
10261 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10262 tg3_phy_toggle_apd(tp
, true);
10267 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10270 struct tg3
*tp
= netdev_priv(dev
);
10272 if (tp
->link_config
.phy_is_low_power
)
10273 tg3_set_power_state(tp
, PCI_D0
);
10275 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10277 if (tg3_test_nvram(tp
) != 0) {
10278 etest
->flags
|= ETH_TEST_FL_FAILED
;
10281 if (tg3_test_link(tp
) != 0) {
10282 etest
->flags
|= ETH_TEST_FL_FAILED
;
10285 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10286 int err
, err2
= 0, irq_sync
= 0;
10288 if (netif_running(dev
)) {
10290 tg3_netif_stop(tp
);
10294 tg3_full_lock(tp
, irq_sync
);
10296 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10297 err
= tg3_nvram_lock(tp
);
10298 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10299 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10300 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10302 tg3_nvram_unlock(tp
);
10304 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10307 if (tg3_test_registers(tp
) != 0) {
10308 etest
->flags
|= ETH_TEST_FL_FAILED
;
10311 if (tg3_test_memory(tp
) != 0) {
10312 etest
->flags
|= ETH_TEST_FL_FAILED
;
10315 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10316 etest
->flags
|= ETH_TEST_FL_FAILED
;
10318 tg3_full_unlock(tp
);
10320 if (tg3_test_interrupt(tp
) != 0) {
10321 etest
->flags
|= ETH_TEST_FL_FAILED
;
10325 tg3_full_lock(tp
, 0);
10327 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10328 if (netif_running(dev
)) {
10329 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10330 err2
= tg3_restart_hw(tp
, 1);
10332 tg3_netif_start(tp
);
10335 tg3_full_unlock(tp
);
10337 if (irq_sync
&& !err2
)
10340 if (tp
->link_config
.phy_is_low_power
)
10341 tg3_set_power_state(tp
, PCI_D3hot
);
10345 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10347 struct mii_ioctl_data
*data
= if_mii(ifr
);
10348 struct tg3
*tp
= netdev_priv(dev
);
10351 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10352 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10354 return phy_mii_ioctl(tp
->mdio_bus
->phy_map
[PHY_ADDR
], data
, cmd
);
10359 data
->phy_id
= PHY_ADDR
;
10362 case SIOCGMIIREG
: {
10365 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10366 break; /* We have no PHY */
10368 if (tp
->link_config
.phy_is_low_power
)
10371 spin_lock_bh(&tp
->lock
);
10372 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10373 spin_unlock_bh(&tp
->lock
);
10375 data
->val_out
= mii_regval
;
10381 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10382 break; /* We have no PHY */
10384 if (!capable(CAP_NET_ADMIN
))
10387 if (tp
->link_config
.phy_is_low_power
)
10390 spin_lock_bh(&tp
->lock
);
10391 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10392 spin_unlock_bh(&tp
->lock
);
10400 return -EOPNOTSUPP
;
10403 #if TG3_VLAN_TAG_USED
10404 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10406 struct tg3
*tp
= netdev_priv(dev
);
10408 if (!netif_running(dev
)) {
10413 tg3_netif_stop(tp
);
10415 tg3_full_lock(tp
, 0);
10419 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10420 __tg3_set_rx_mode(dev
);
10422 tg3_netif_start(tp
);
10424 tg3_full_unlock(tp
);
10428 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10430 struct tg3
*tp
= netdev_priv(dev
);
10432 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10436 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10438 struct tg3
*tp
= netdev_priv(dev
);
10439 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10440 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
10442 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
10443 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
10444 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
10445 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
10446 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
10449 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
10450 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
10451 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
10452 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
10453 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
10454 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
10455 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
10456 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
10457 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
10458 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
10461 /* No rx interrupts will be generated if both are zero */
10462 if ((ec
->rx_coalesce_usecs
== 0) &&
10463 (ec
->rx_max_coalesced_frames
== 0))
10466 /* No tx interrupts will be generated if both are zero */
10467 if ((ec
->tx_coalesce_usecs
== 0) &&
10468 (ec
->tx_max_coalesced_frames
== 0))
10471 /* Only copy relevant parameters, ignore all others. */
10472 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
10473 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
10474 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
10475 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
10476 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
10477 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
10478 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
10479 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
10480 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
10482 if (netif_running(dev
)) {
10483 tg3_full_lock(tp
, 0);
10484 __tg3_set_coalesce(tp
, &tp
->coal
);
10485 tg3_full_unlock(tp
);
10490 static const struct ethtool_ops tg3_ethtool_ops
= {
10491 .get_settings
= tg3_get_settings
,
10492 .set_settings
= tg3_set_settings
,
10493 .get_drvinfo
= tg3_get_drvinfo
,
10494 .get_regs_len
= tg3_get_regs_len
,
10495 .get_regs
= tg3_get_regs
,
10496 .get_wol
= tg3_get_wol
,
10497 .set_wol
= tg3_set_wol
,
10498 .get_msglevel
= tg3_get_msglevel
,
10499 .set_msglevel
= tg3_set_msglevel
,
10500 .nway_reset
= tg3_nway_reset
,
10501 .get_link
= ethtool_op_get_link
,
10502 .get_eeprom_len
= tg3_get_eeprom_len
,
10503 .get_eeprom
= tg3_get_eeprom
,
10504 .set_eeprom
= tg3_set_eeprom
,
10505 .get_ringparam
= tg3_get_ringparam
,
10506 .set_ringparam
= tg3_set_ringparam
,
10507 .get_pauseparam
= tg3_get_pauseparam
,
10508 .set_pauseparam
= tg3_set_pauseparam
,
10509 .get_rx_csum
= tg3_get_rx_csum
,
10510 .set_rx_csum
= tg3_set_rx_csum
,
10511 .set_tx_csum
= tg3_set_tx_csum
,
10512 .set_sg
= ethtool_op_set_sg
,
10513 .set_tso
= tg3_set_tso
,
10514 .self_test
= tg3_self_test
,
10515 .get_strings
= tg3_get_strings
,
10516 .phys_id
= tg3_phys_id
,
10517 .get_ethtool_stats
= tg3_get_ethtool_stats
,
10518 .get_coalesce
= tg3_get_coalesce
,
10519 .set_coalesce
= tg3_set_coalesce
,
10520 .get_sset_count
= tg3_get_sset_count
,
10523 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
10525 u32 cursize
, val
, magic
;
10527 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
10529 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10532 if ((magic
!= TG3_EEPROM_MAGIC
) &&
10533 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
10534 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
10538 * Size the chip by reading offsets at increasing powers of two.
10539 * When we encounter our validation signature, we know the addressing
10540 * has wrapped around, and thus have our chip size.
10544 while (cursize
< tp
->nvram_size
) {
10545 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
10554 tp
->nvram_size
= cursize
;
10557 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10561 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10562 tg3_nvram_read(tp
, 0, &val
) != 0)
10565 /* Selfboot format */
10566 if (val
!= TG3_EEPROM_MAGIC
) {
10567 tg3_get_eeprom_size(tp
);
10571 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10573 /* This is confusing. We want to operate on the
10574 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10575 * call will read from NVRAM and byteswap the data
10576 * according to the byteswapping settings for all
10577 * other register accesses. This ensures the data we
10578 * want will always reside in the lower 16-bits.
10579 * However, the data in NVRAM is in LE format, which
10580 * means the data from the NVRAM read will always be
10581 * opposite the endianness of the CPU. The 16-bit
10582 * byteswap then brings the data to CPU endianness.
10584 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
10588 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10591 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10595 nvcfg1
= tr32(NVRAM_CFG1
);
10596 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10597 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10599 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10600 tw32(NVRAM_CFG1
, nvcfg1
);
10603 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10604 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10605 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10606 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10607 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10608 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10609 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10611 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10612 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10613 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10615 case FLASH_VENDOR_ATMEL_EEPROM
:
10616 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10617 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10618 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10620 case FLASH_VENDOR_ST
:
10621 tp
->nvram_jedecnum
= JEDEC_ST
;
10622 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10623 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10625 case FLASH_VENDOR_SAIFUN
:
10626 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10627 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10629 case FLASH_VENDOR_SST_SMALL
:
10630 case FLASH_VENDOR_SST_LARGE
:
10631 tp
->nvram_jedecnum
= JEDEC_SST
;
10632 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10636 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10637 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10638 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10642 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10646 nvcfg1
= tr32(NVRAM_CFG1
);
10648 /* NVRAM protection for TPM */
10649 if (nvcfg1
& (1 << 27))
10650 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10652 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10653 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10654 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10655 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10656 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10658 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10659 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10660 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10661 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10663 case FLASH_5752VENDOR_ST_M45PE10
:
10664 case FLASH_5752VENDOR_ST_M45PE20
:
10665 case FLASH_5752VENDOR_ST_M45PE40
:
10666 tp
->nvram_jedecnum
= JEDEC_ST
;
10667 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10668 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10672 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10673 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10674 case FLASH_5752PAGE_SIZE_256
:
10675 tp
->nvram_pagesize
= 256;
10677 case FLASH_5752PAGE_SIZE_512
:
10678 tp
->nvram_pagesize
= 512;
10680 case FLASH_5752PAGE_SIZE_1K
:
10681 tp
->nvram_pagesize
= 1024;
10683 case FLASH_5752PAGE_SIZE_2K
:
10684 tp
->nvram_pagesize
= 2048;
10686 case FLASH_5752PAGE_SIZE_4K
:
10687 tp
->nvram_pagesize
= 4096;
10689 case FLASH_5752PAGE_SIZE_264
:
10690 tp
->nvram_pagesize
= 264;
10694 /* For eeprom, set pagesize to maximum eeprom size */
10695 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10697 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10698 tw32(NVRAM_CFG1
, nvcfg1
);
10702 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
10704 u32 nvcfg1
, protect
= 0;
10706 nvcfg1
= tr32(NVRAM_CFG1
);
10708 /* NVRAM protection for TPM */
10709 if (nvcfg1
& (1 << 27)) {
10710 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10714 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10716 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10717 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10718 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10719 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
10720 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10721 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10722 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10723 tp
->nvram_pagesize
= 264;
10724 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
10725 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
10726 tp
->nvram_size
= (protect
? 0x3e200 :
10727 TG3_NVRAM_SIZE_512KB
);
10728 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
10729 tp
->nvram_size
= (protect
? 0x1f200 :
10730 TG3_NVRAM_SIZE_256KB
);
10732 tp
->nvram_size
= (protect
? 0x1f200 :
10733 TG3_NVRAM_SIZE_128KB
);
10735 case FLASH_5752VENDOR_ST_M45PE10
:
10736 case FLASH_5752VENDOR_ST_M45PE20
:
10737 case FLASH_5752VENDOR_ST_M45PE40
:
10738 tp
->nvram_jedecnum
= JEDEC_ST
;
10739 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10740 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10741 tp
->nvram_pagesize
= 256;
10742 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
10743 tp
->nvram_size
= (protect
?
10744 TG3_NVRAM_SIZE_64KB
:
10745 TG3_NVRAM_SIZE_128KB
);
10746 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
10747 tp
->nvram_size
= (protect
?
10748 TG3_NVRAM_SIZE_64KB
:
10749 TG3_NVRAM_SIZE_256KB
);
10751 tp
->nvram_size
= (protect
?
10752 TG3_NVRAM_SIZE_128KB
:
10753 TG3_NVRAM_SIZE_512KB
);
10758 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
10762 nvcfg1
= tr32(NVRAM_CFG1
);
10764 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10765 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
10766 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10767 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
10768 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10769 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10770 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10771 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10773 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10774 tw32(NVRAM_CFG1
, nvcfg1
);
10776 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10777 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10778 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10779 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10780 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10781 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10782 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10783 tp
->nvram_pagesize
= 264;
10785 case FLASH_5752VENDOR_ST_M45PE10
:
10786 case FLASH_5752VENDOR_ST_M45PE20
:
10787 case FLASH_5752VENDOR_ST_M45PE40
:
10788 tp
->nvram_jedecnum
= JEDEC_ST
;
10789 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10790 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10791 tp
->nvram_pagesize
= 256;
10796 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
10798 u32 nvcfg1
, protect
= 0;
10800 nvcfg1
= tr32(NVRAM_CFG1
);
10802 /* NVRAM protection for TPM */
10803 if (nvcfg1
& (1 << 27)) {
10804 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10808 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10810 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10811 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10812 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10813 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10814 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10815 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10816 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10817 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10818 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10819 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10820 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10821 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10822 tp
->nvram_pagesize
= 256;
10824 case FLASH_5761VENDOR_ST_A_M45PE20
:
10825 case FLASH_5761VENDOR_ST_A_M45PE40
:
10826 case FLASH_5761VENDOR_ST_A_M45PE80
:
10827 case FLASH_5761VENDOR_ST_A_M45PE16
:
10828 case FLASH_5761VENDOR_ST_M_M45PE20
:
10829 case FLASH_5761VENDOR_ST_M_M45PE40
:
10830 case FLASH_5761VENDOR_ST_M_M45PE80
:
10831 case FLASH_5761VENDOR_ST_M_M45PE16
:
10832 tp
->nvram_jedecnum
= JEDEC_ST
;
10833 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10834 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10835 tp
->nvram_pagesize
= 256;
10840 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
10843 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10844 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10845 case FLASH_5761VENDOR_ST_A_M45PE16
:
10846 case FLASH_5761VENDOR_ST_M_M45PE16
:
10847 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
10849 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10850 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10851 case FLASH_5761VENDOR_ST_A_M45PE80
:
10852 case FLASH_5761VENDOR_ST_M_M45PE80
:
10853 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
10855 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10856 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10857 case FLASH_5761VENDOR_ST_A_M45PE40
:
10858 case FLASH_5761VENDOR_ST_M_M45PE40
:
10859 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10861 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10862 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10863 case FLASH_5761VENDOR_ST_A_M45PE20
:
10864 case FLASH_5761VENDOR_ST_M_M45PE20
:
10865 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10871 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
10873 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10874 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10875 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10878 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
10882 nvcfg1
= tr32(NVRAM_CFG1
);
10884 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10885 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10886 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10887 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10888 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10889 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10891 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10892 tw32(NVRAM_CFG1
, nvcfg1
);
10894 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10895 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10896 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10897 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10898 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10899 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10900 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10901 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10902 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10903 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10905 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10906 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10907 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10908 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10909 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10911 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10912 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10913 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10915 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10916 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10917 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10921 case FLASH_5752VENDOR_ST_M45PE10
:
10922 case FLASH_5752VENDOR_ST_M45PE20
:
10923 case FLASH_5752VENDOR_ST_M45PE40
:
10924 tp
->nvram_jedecnum
= JEDEC_ST
;
10925 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10926 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10928 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10929 case FLASH_5752VENDOR_ST_M45PE10
:
10930 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10932 case FLASH_5752VENDOR_ST_M45PE20
:
10933 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10935 case FLASH_5752VENDOR_ST_M45PE40
:
10936 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10941 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
10945 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10946 case FLASH_5752PAGE_SIZE_256
:
10947 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10948 tp
->nvram_pagesize
= 256;
10950 case FLASH_5752PAGE_SIZE_512
:
10951 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10952 tp
->nvram_pagesize
= 512;
10954 case FLASH_5752PAGE_SIZE_1K
:
10955 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10956 tp
->nvram_pagesize
= 1024;
10958 case FLASH_5752PAGE_SIZE_2K
:
10959 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10960 tp
->nvram_pagesize
= 2048;
10962 case FLASH_5752PAGE_SIZE_4K
:
10963 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10964 tp
->nvram_pagesize
= 4096;
10966 case FLASH_5752PAGE_SIZE_264
:
10967 tp
->nvram_pagesize
= 264;
10969 case FLASH_5752PAGE_SIZE_528
:
10970 tp
->nvram_pagesize
= 528;
10975 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10976 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
10978 tw32_f(GRC_EEPROM_ADDR
,
10979 (EEPROM_ADDR_FSM_RESET
|
10980 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
10981 EEPROM_ADDR_CLKPERD_SHIFT
)));
10985 /* Enable seeprom accesses. */
10986 tw32_f(GRC_LOCAL_CTRL
,
10987 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
10990 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
10991 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
10992 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
10994 if (tg3_nvram_lock(tp
)) {
10995 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
10996 "tg3_nvram_init failed.\n", tp
->dev
->name
);
10999 tg3_enable_nvram_access(tp
);
11001 tp
->nvram_size
= 0;
11003 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
11004 tg3_get_5752_nvram_info(tp
);
11005 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
11006 tg3_get_5755_nvram_info(tp
);
11007 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
11008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
11009 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11010 tg3_get_5787_nvram_info(tp
);
11011 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
11012 tg3_get_5761_nvram_info(tp
);
11013 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11014 tg3_get_5906_nvram_info(tp
);
11015 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
11016 tg3_get_57780_nvram_info(tp
);
11018 tg3_get_nvram_info(tp
);
11020 if (tp
->nvram_size
== 0)
11021 tg3_get_nvram_size(tp
);
11023 tg3_disable_nvram_access(tp
);
11024 tg3_nvram_unlock(tp
);
11027 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
11029 tg3_get_eeprom_size(tp
);
11033 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
11034 u32 offset
, u32 len
, u8
*buf
)
11039 for (i
= 0; i
< len
; i
+= 4) {
11045 memcpy(&data
, buf
+ i
, 4);
11048 * The SEEPROM interface expects the data to always be opposite
11049 * the native endian format. We accomplish this by reversing
11050 * all the operations that would have been performed on the
11051 * data from a call to tg3_nvram_read_be32().
11053 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
11055 val
= tr32(GRC_EEPROM_ADDR
);
11056 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
11058 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
11060 tw32(GRC_EEPROM_ADDR
, val
|
11061 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
11062 (addr
& EEPROM_ADDR_ADDR_MASK
) |
11063 EEPROM_ADDR_START
|
11064 EEPROM_ADDR_WRITE
);
11066 for (j
= 0; j
< 1000; j
++) {
11067 val
= tr32(GRC_EEPROM_ADDR
);
11069 if (val
& EEPROM_ADDR_COMPLETE
)
11073 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
11082 /* offset and length are dword aligned */
11083 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
11087 u32 pagesize
= tp
->nvram_pagesize
;
11088 u32 pagemask
= pagesize
- 1;
11092 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
11098 u32 phy_addr
, page_off
, size
;
11100 phy_addr
= offset
& ~pagemask
;
11102 for (j
= 0; j
< pagesize
; j
+= 4) {
11103 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
11104 (__be32
*) (tmp
+ j
));
11111 page_off
= offset
& pagemask
;
11118 memcpy(tmp
+ page_off
, buf
, size
);
11120 offset
= offset
+ (pagesize
- page_off
);
11122 tg3_enable_nvram_access(tp
);
11125 * Before we can erase the flash page, we need
11126 * to issue a special "write enable" command.
11128 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11130 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11133 /* Erase the target page */
11134 tw32(NVRAM_ADDR
, phy_addr
);
11136 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
11137 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11139 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11142 /* Issue another write enable to start the write. */
11143 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11145 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11148 for (j
= 0; j
< pagesize
; j
+= 4) {
11151 data
= *((__be32
*) (tmp
+ j
));
11153 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11155 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11157 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11161 nvram_cmd
|= NVRAM_CMD_FIRST
;
11162 else if (j
== (pagesize
- 4))
11163 nvram_cmd
|= NVRAM_CMD_LAST
;
11165 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11172 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11173 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11180 /* offset and length are dword aligned */
11181 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11186 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11187 u32 page_off
, phy_addr
, nvram_cmd
;
11190 memcpy(&data
, buf
+ i
, 4);
11191 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11193 page_off
= offset
% tp
->nvram_pagesize
;
11195 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11197 tw32(NVRAM_ADDR
, phy_addr
);
11199 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11201 if ((page_off
== 0) || (i
== 0))
11202 nvram_cmd
|= NVRAM_CMD_FIRST
;
11203 if (page_off
== (tp
->nvram_pagesize
- 4))
11204 nvram_cmd
|= NVRAM_CMD_LAST
;
11206 if (i
== (len
- 4))
11207 nvram_cmd
|= NVRAM_CMD_LAST
;
11209 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11210 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11211 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11212 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11214 if ((ret
= tg3_nvram_exec_cmd(tp
,
11215 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11220 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11221 /* We always do complete word writes to eeprom. */
11222 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11225 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11231 /* offset and length are dword aligned */
11232 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11236 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11237 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11238 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11242 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11243 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11248 ret
= tg3_nvram_lock(tp
);
11252 tg3_enable_nvram_access(tp
);
11253 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11254 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
11255 tw32(NVRAM_WRITE1
, 0x406);
11257 grc_mode
= tr32(GRC_MODE
);
11258 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11260 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11261 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11263 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11267 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11271 grc_mode
= tr32(GRC_MODE
);
11272 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11274 tg3_disable_nvram_access(tp
);
11275 tg3_nvram_unlock(tp
);
11278 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11279 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11286 struct subsys_tbl_ent
{
11287 u16 subsys_vendor
, subsys_devid
;
11291 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
11292 /* Broadcom boards. */
11293 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
11294 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
11295 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
11296 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
11297 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
11298 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
11299 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
11300 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
11301 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
11302 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
11303 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
11306 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
11307 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
11308 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
11309 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
11310 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
11313 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
11314 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
11315 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
11316 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
11318 /* Compaq boards. */
11319 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
11320 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
11321 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
11322 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
11323 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
11326 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
11329 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
11333 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
11334 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
11335 tp
->pdev
->subsystem_vendor
) &&
11336 (subsys_id_to_phy_id
[i
].subsys_devid
==
11337 tp
->pdev
->subsystem_device
))
11338 return &subsys_id_to_phy_id
[i
];
11343 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
11348 /* On some early chips the SRAM cannot be accessed in D3hot state,
11349 * so need make sure we're in D0.
11351 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
11352 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11353 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
11356 /* Make sure register accesses (indirect or otherwise)
11357 * will function correctly.
11359 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11360 tp
->misc_host_ctrl
);
11362 /* The memory arbiter has to be enabled in order for SRAM accesses
11363 * to succeed. Normally on powerup the tg3 chip firmware will make
11364 * sure it is enabled, but other entities such as system netboot
11365 * code might disable it.
11367 val
= tr32(MEMARB_MODE
);
11368 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
11370 tp
->phy_id
= PHY_ID_INVALID
;
11371 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11373 /* Assume an onboard device and WOL capable by default. */
11374 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
11376 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11377 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
11378 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11379 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11381 val
= tr32(VCPU_CFGSHDW
);
11382 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
11383 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11384 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
11385 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
11386 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11390 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
11391 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
11392 u32 nic_cfg
, led_cfg
;
11393 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
11394 int eeprom_phy_serdes
= 0;
11396 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
11397 tp
->nic_sram_data_cfg
= nic_cfg
;
11399 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
11400 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
11401 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
11402 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
11403 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
11404 (ver
> 0) && (ver
< 0x100))
11405 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
11407 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11408 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
11410 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
11411 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
11412 eeprom_phy_serdes
= 1;
11414 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
11415 if (nic_phy_id
!= 0) {
11416 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
11417 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
11419 eeprom_phy_id
= (id1
>> 16) << 10;
11420 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
11421 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
11425 tp
->phy_id
= eeprom_phy_id
;
11426 if (eeprom_phy_serdes
) {
11427 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
11428 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
11430 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11433 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11434 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11435 SHASTA_EXT_LED_MODE_MASK
);
11437 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11441 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11442 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11445 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11446 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11449 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11450 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11452 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11453 * read on some older 5700/5701 bootcode.
11455 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11457 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11459 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11463 case SHASTA_EXT_LED_SHARED
:
11464 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11465 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11466 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11467 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11468 LED_CTRL_MODE_PHY_2
);
11471 case SHASTA_EXT_LED_MAC
:
11472 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11475 case SHASTA_EXT_LED_COMBO
:
11476 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11477 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11478 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11479 LED_CTRL_MODE_PHY_2
);
11484 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11485 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11486 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11487 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11489 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11490 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11492 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11493 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11494 if ((tp
->pdev
->subsystem_vendor
==
11495 PCI_VENDOR_ID_ARIMA
) &&
11496 (tp
->pdev
->subsystem_device
== 0x205a ||
11497 tp
->pdev
->subsystem_device
== 0x2063))
11498 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11500 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11501 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11504 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11505 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11506 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11507 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11510 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11511 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11512 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11514 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11515 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11516 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11518 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11519 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11520 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11522 if (cfg2
& (1 << 17))
11523 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11525 /* serdes signal pre-emphasis in register 0x590 set by */
11526 /* bootcode if bit 18 is set */
11527 if (cfg2
& (1 << 18))
11528 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11530 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11531 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11532 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11533 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11535 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11538 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11539 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11540 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11543 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11544 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11545 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11546 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11547 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11548 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11551 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11552 device_set_wakeup_enable(&tp
->pdev
->dev
,
11553 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11556 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11561 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11562 tw32(OTP_CTRL
, cmd
);
11564 /* Wait for up to 1 ms for command to execute. */
11565 for (i
= 0; i
< 100; i
++) {
11566 val
= tr32(OTP_STATUS
);
11567 if (val
& OTP_STATUS_CMD_DONE
)
11572 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11575 /* Read the gphy configuration from the OTP region of the chip. The gphy
11576 * configuration is a 32-bit value that straddles the alignment boundary.
11577 * We do two 32-bit reads and then shift and merge the results.
11579 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11581 u32 bhalf_otp
, thalf_otp
;
11583 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11585 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11588 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11590 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11593 thalf_otp
= tr32(OTP_READ_DATA
);
11595 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11597 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11600 bhalf_otp
= tr32(OTP_READ_DATA
);
11602 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11605 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11607 u32 hw_phy_id_1
, hw_phy_id_2
;
11608 u32 hw_phy_id
, hw_phy_id_masked
;
11611 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11612 return tg3_phy_init(tp
);
11614 /* Reading the PHY ID register can conflict with ASF
11615 * firmware access to the PHY hardware.
11618 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11619 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11620 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11622 /* Now read the physical PHY_ID from the chip and verify
11623 * that it is sane. If it doesn't look good, we fall back
11624 * to either the hard-coded table based PHY_ID and failing
11625 * that the value found in the eeprom area.
11627 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11628 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11630 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11631 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11632 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11634 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11637 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11638 tp
->phy_id
= hw_phy_id
;
11639 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11640 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11642 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11644 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11645 /* Do nothing, phy ID already set up in
11646 * tg3_get_eeprom_hw_cfg().
11649 struct subsys_tbl_ent
*p
;
11651 /* No eeprom signature? Try the hardcoded
11652 * subsys device table.
11654 p
= lookup_by_subsys(tp
);
11658 tp
->phy_id
= p
->phy_id
;
11660 tp
->phy_id
== PHY_ID_BCM8002
)
11661 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11665 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
11666 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
11667 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
11668 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
11670 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
11671 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
11672 (bmsr
& BMSR_LSTATUS
))
11673 goto skip_phy_reset
;
11675 err
= tg3_phy_reset(tp
);
11679 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
11680 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
11681 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
11683 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
11684 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
11685 MII_TG3_CTRL_ADV_1000_FULL
);
11686 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
11687 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
11688 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
11689 MII_TG3_CTRL_ENABLE_AS_MASTER
);
11692 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
11693 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
11694 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
11695 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
11696 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11698 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11699 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11701 tg3_writephy(tp
, MII_BMCR
,
11702 BMCR_ANENABLE
| BMCR_ANRESTART
);
11704 tg3_phy_set_wirespeed(tp
);
11706 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11707 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11708 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11712 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
11713 err
= tg3_init_5401phy_dsp(tp
);
11718 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
11719 err
= tg3_init_5401phy_dsp(tp
);
11722 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
11723 tp
->link_config
.advertising
=
11724 (ADVERTISED_1000baseT_Half
|
11725 ADVERTISED_1000baseT_Full
|
11726 ADVERTISED_Autoneg
|
11728 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
11729 tp
->link_config
.advertising
&=
11730 ~(ADVERTISED_1000baseT_Half
|
11731 ADVERTISED_1000baseT_Full
);
11736 static void __devinit
tg3_read_partno(struct tg3
*tp
)
11738 unsigned char vpd_data
[256]; /* in little-endian format */
11742 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11743 tg3_nvram_read(tp
, 0x0, &magic
))
11744 goto out_not_found
;
11746 if (magic
== TG3_EEPROM_MAGIC
) {
11747 for (i
= 0; i
< 256; i
+= 4) {
11750 /* The data is in little-endian format in NVRAM.
11751 * Use the big-endian read routines to preserve
11752 * the byte order as it exists in NVRAM.
11754 if (tg3_nvram_read_be32(tp
, 0x100 + i
, &tmp
))
11755 goto out_not_found
;
11757 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
11762 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
11763 for (i
= 0; i
< 256; i
+= 4) {
11768 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
11770 while (j
++ < 100) {
11771 pci_read_config_word(tp
->pdev
, vpd_cap
+
11772 PCI_VPD_ADDR
, &tmp16
);
11773 if (tmp16
& 0x8000)
11777 if (!(tmp16
& 0x8000))
11778 goto out_not_found
;
11780 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
11782 v
= cpu_to_le32(tmp
);
11783 memcpy(&vpd_data
[i
], &v
, sizeof(v
));
11787 /* Now parse and find the part number. */
11788 for (i
= 0; i
< 254; ) {
11789 unsigned char val
= vpd_data
[i
];
11790 unsigned int block_end
;
11792 if (val
== 0x82 || val
== 0x91) {
11795 (vpd_data
[i
+ 2] << 8)));
11800 goto out_not_found
;
11802 block_end
= (i
+ 3 +
11804 (vpd_data
[i
+ 2] << 8)));
11807 if (block_end
> 256)
11808 goto out_not_found
;
11810 while (i
< (block_end
- 2)) {
11811 if (vpd_data
[i
+ 0] == 'P' &&
11812 vpd_data
[i
+ 1] == 'N') {
11813 int partno_len
= vpd_data
[i
+ 2];
11816 if (partno_len
> 24 || (partno_len
+ i
) > 256)
11817 goto out_not_found
;
11819 memcpy(tp
->board_part_number
,
11820 &vpd_data
[i
], partno_len
);
11825 i
+= 3 + vpd_data
[i
+ 2];
11828 /* Part number not found. */
11829 goto out_not_found
;
11833 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11834 strcpy(tp
->board_part_number
, "BCM95906");
11835 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11836 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
11837 strcpy(tp
->board_part_number
, "BCM57780");
11838 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11839 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
11840 strcpy(tp
->board_part_number
, "BCM57760");
11841 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11842 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
11843 strcpy(tp
->board_part_number
, "BCM57790");
11844 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11845 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
11846 strcpy(tp
->board_part_number
, "BCM57788");
11848 strcpy(tp
->board_part_number
, "none");
11851 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
11855 if (tg3_nvram_read(tp
, offset
, &val
) ||
11856 (val
& 0xfc000000) != 0x0c000000 ||
11857 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
11864 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
11866 u32 val
, offset
, start
, ver_offset
;
11868 bool newver
= false;
11870 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
11871 tg3_nvram_read(tp
, 0x4, &start
))
11874 offset
= tg3_nvram_logical_addr(tp
, offset
);
11876 if (tg3_nvram_read(tp
, offset
, &val
))
11879 if ((val
& 0xfc000000) == 0x0c000000) {
11880 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
11888 if (tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
11891 offset
= offset
+ ver_offset
- start
;
11892 for (i
= 0; i
< 16; i
+= 4) {
11894 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
11897 memcpy(tp
->fw_ver
+ i
, &v
, sizeof(v
));
11902 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
11905 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
11906 TG3_NVM_BCVER_MAJSFT
;
11907 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
11908 snprintf(&tp
->fw_ver
[0], 32, "v%d.%02d", major
, minor
);
11912 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
11914 u32 val
, major
, minor
;
11916 /* Use native endian representation */
11917 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
11920 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
11921 TG3_NVM_HWSB_CFG1_MAJSFT
;
11922 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
11923 TG3_NVM_HWSB_CFG1_MINSFT
;
11925 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
11928 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
11930 u32 offset
, major
, minor
, build
;
11932 tp
->fw_ver
[0] = 's';
11933 tp
->fw_ver
[1] = 'b';
11934 tp
->fw_ver
[2] = '\0';
11936 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
11939 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
11940 case TG3_EEPROM_SB_REVISION_0
:
11941 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
11943 case TG3_EEPROM_SB_REVISION_2
:
11944 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
11946 case TG3_EEPROM_SB_REVISION_3
:
11947 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
11953 if (tg3_nvram_read(tp
, offset
, &val
))
11956 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
11957 TG3_EEPROM_SB_EDH_BLD_SHFT
;
11958 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
11959 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
11960 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
11962 if (minor
> 99 || build
> 26)
11965 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
11968 tp
->fw_ver
[8] = 'a' + build
- 1;
11969 tp
->fw_ver
[9] = '\0';
11973 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
11975 u32 val
, offset
, start
;
11978 for (offset
= TG3_NVM_DIR_START
;
11979 offset
< TG3_NVM_DIR_END
;
11980 offset
+= TG3_NVM_DIRENT_SIZE
) {
11981 if (tg3_nvram_read(tp
, offset
, &val
))
11984 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
11988 if (offset
== TG3_NVM_DIR_END
)
11991 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11992 start
= 0x08000000;
11993 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
11996 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
11997 !tg3_fw_img_is_valid(tp
, offset
) ||
11998 tg3_nvram_read(tp
, offset
+ 8, &val
))
12001 offset
+= val
- start
;
12003 vlen
= strlen(tp
->fw_ver
);
12005 tp
->fw_ver
[vlen
++] = ',';
12006 tp
->fw_ver
[vlen
++] = ' ';
12008 for (i
= 0; i
< 4; i
++) {
12010 if (tg3_nvram_read_be32(tp
, offset
, &v
))
12013 offset
+= sizeof(v
);
12015 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
12016 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
12020 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
12025 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
12030 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
12031 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
12034 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
12035 if (apedata
!= APE_SEG_SIG_MAGIC
)
12038 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
12039 if (!(apedata
& APE_FW_STATUS_READY
))
12042 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
12044 vlen
= strlen(tp
->fw_ver
);
12046 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
12047 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
12048 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
12049 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
12050 (apedata
& APE_FW_VERSION_BLDMSK
));
12053 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
12057 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
12058 tp
->fw_ver
[0] = 's';
12059 tp
->fw_ver
[1] = 'b';
12060 tp
->fw_ver
[2] = '\0';
12065 if (tg3_nvram_read(tp
, 0, &val
))
12068 if (val
== TG3_EEPROM_MAGIC
)
12069 tg3_read_bc_ver(tp
);
12070 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
12071 tg3_read_sb_ver(tp
, val
);
12072 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12073 tg3_read_hwsb_ver(tp
);
12077 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
12078 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
12081 tg3_read_mgmtfw_ver(tp
);
12083 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
12086 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
12088 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
12090 static struct pci_device_id write_reorder_chipsets
[] = {
12091 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12092 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
12093 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
12094 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
12095 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
12096 PCI_DEVICE_ID_VIA_8385_0
) },
12100 u32 pci_state_reg
, grc_misc_cfg
;
12105 /* Force memory write invalidate off. If we leave it on,
12106 * then on 5700_BX chips we have to enable a workaround.
12107 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12108 * to match the cacheline size. The Broadcom driver have this
12109 * workaround but turns MWI off all the times so never uses
12110 * it. This seems to suggest that the workaround is insufficient.
12112 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12113 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
12114 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12116 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12117 * has the register indirect write enable bit set before
12118 * we try to access any of the MMIO registers. It is also
12119 * critical that the PCI-X hw workaround situation is decided
12120 * before that as well.
12122 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12125 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
12126 MISC_HOST_CTRL_CHIPREV_SHIFT
);
12127 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
12128 u32 prod_id_asic_rev
;
12130 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
12131 &prod_id_asic_rev
);
12132 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
12135 /* Wrong chip ID in 5752 A0. This code can be removed later
12136 * as A0 is not in production.
12138 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12139 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12141 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12142 * we need to disable memory and use config. cycles
12143 * only to access all registers. The 5702/03 chips
12144 * can mistakenly decode the special cycles from the
12145 * ICH chipsets as memory write cycles, causing corruption
12146 * of register and memory space. Only certain ICH bridges
12147 * will drive special cycles with non-zero data during the
12148 * address phase which can fall within the 5703's address
12149 * range. This is not an ICH bug as the PCI spec allows
12150 * non-zero address during special cycles. However, only
12151 * these ICH bridges are known to drive non-zero addresses
12152 * during special cycles.
12154 * Since special cycles do not cross PCI bridges, we only
12155 * enable this workaround if the 5703 is on the secondary
12156 * bus of these ICH bridges.
12158 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12159 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12160 static struct tg3_dev_id
{
12164 } ich_chipsets
[] = {
12165 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12167 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12169 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12171 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12175 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12176 struct pci_dev
*bridge
= NULL
;
12178 while (pci_id
->vendor
!= 0) {
12179 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12185 if (pci_id
->rev
!= PCI_ANY_ID
) {
12186 if (bridge
->revision
> pci_id
->rev
)
12189 if (bridge
->subordinate
&&
12190 (bridge
->subordinate
->number
==
12191 tp
->pdev
->bus
->number
)) {
12193 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12194 pci_dev_put(bridge
);
12200 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12201 static struct tg3_dev_id
{
12204 } bridge_chipsets
[] = {
12205 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12206 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12209 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12210 struct pci_dev
*bridge
= NULL
;
12212 while (pci_id
->vendor
!= 0) {
12213 bridge
= pci_get_device(pci_id
->vendor
,
12220 if (bridge
->subordinate
&&
12221 (bridge
->subordinate
->number
<=
12222 tp
->pdev
->bus
->number
) &&
12223 (bridge
->subordinate
->subordinate
>=
12224 tp
->pdev
->bus
->number
)) {
12225 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12226 pci_dev_put(bridge
);
12232 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12233 * DMA addresses > 40-bit. This bridge may have other additional
12234 * 57xx devices behind it in some 4-port NIC designs for example.
12235 * Any tg3 device found behind the bridge will also need the 40-bit
12238 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12239 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12240 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12241 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12242 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12245 struct pci_dev
*bridge
= NULL
;
12248 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12249 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12251 if (bridge
&& bridge
->subordinate
&&
12252 (bridge
->subordinate
->number
<=
12253 tp
->pdev
->bus
->number
) &&
12254 (bridge
->subordinate
->subordinate
>=
12255 tp
->pdev
->bus
->number
)) {
12256 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12257 pci_dev_put(bridge
);
12263 /* Initialize misc host control in PCI block. */
12264 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12265 MISC_HOST_CTRL_CHIPREV
);
12266 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12267 tp
->misc_host_ctrl
);
12269 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12270 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
))
12271 tp
->pdev_peer
= tg3_find_peer(tp
);
12273 /* Intentionally exclude ASIC_REV_5906 */
12274 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12275 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12276 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12277 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12278 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12279 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12280 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
12282 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12283 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12284 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
12285 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12286 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12287 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
12289 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
12290 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12291 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
12293 /* 5700 B0 chips do not support checksumming correctly due
12294 * to hardware bugs.
12296 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
12297 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
12299 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
12300 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
12301 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
12302 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
12305 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
12306 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
12307 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
12308 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
12309 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
12310 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
12311 tp
->pdev_peer
== tp
->pdev
))
12312 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
12314 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12315 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12316 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
12317 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
12319 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
12320 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12322 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
12323 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
12329 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12330 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12331 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
12333 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12336 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
12337 if (tp
->pcie_cap
!= 0) {
12340 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12342 pcie_set_readrq(tp
->pdev
, 4096);
12344 pci_read_config_word(tp
->pdev
,
12345 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
12347 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
12348 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12349 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
12350 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12351 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12352 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
12353 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
12354 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
12356 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
12357 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12358 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12359 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12360 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
12361 if (!tp
->pcix_cap
) {
12362 printk(KERN_ERR PFX
"Cannot find PCI-X "
12363 "capability, aborting.\n");
12367 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
12368 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
12371 /* If we have an AMD 762 or VIA K8T800 chipset, write
12372 * reordering to the mailbox registers done by the host
12373 * controller can cause major troubles. We read back from
12374 * every mailbox register write to force the writes to be
12375 * posted to the chip in order.
12377 if (pci_dev_present(write_reorder_chipsets
) &&
12378 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12379 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
12381 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
12382 &tp
->pci_cacheline_sz
);
12383 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12384 &tp
->pci_lat_timer
);
12385 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12386 tp
->pci_lat_timer
< 64) {
12387 tp
->pci_lat_timer
= 64;
12388 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12389 tp
->pci_lat_timer
);
12392 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
12393 /* 5700 BX chips need to have their TX producer index
12394 * mailboxes written twice to workaround a bug.
12396 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
12398 /* If we are in PCI-X mode, enable register write workaround.
12400 * The workaround is to use indirect register accesses
12401 * for all chip writes not to mailbox registers.
12403 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12406 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12408 /* The chip can have it's power management PCI config
12409 * space registers clobbered due to this bug.
12410 * So explicitly force the chip into D0 here.
12412 pci_read_config_dword(tp
->pdev
,
12413 tp
->pm_cap
+ PCI_PM_CTRL
,
12415 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
12416 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
12417 pci_write_config_dword(tp
->pdev
,
12418 tp
->pm_cap
+ PCI_PM_CTRL
,
12421 /* Also, force SERR#/PERR# in PCI command. */
12422 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12423 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
12424 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12428 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
12429 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
12430 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
12431 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
12433 /* Chip-specific fixup from Broadcom driver */
12434 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
12435 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
12436 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
12437 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
12440 /* Default fast path register access methods */
12441 tp
->read32
= tg3_read32
;
12442 tp
->write32
= tg3_write32
;
12443 tp
->read32_mbox
= tg3_read32
;
12444 tp
->write32_mbox
= tg3_write32
;
12445 tp
->write32_tx_mbox
= tg3_write32
;
12446 tp
->write32_rx_mbox
= tg3_write32
;
12448 /* Various workaround register access methods */
12449 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
12450 tp
->write32
= tg3_write_indirect_reg32
;
12451 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
12452 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12453 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
12455 * Back to back register writes can cause problems on these
12456 * chips, the workaround is to read back all reg writes
12457 * except those to mailbox regs.
12459 * See tg3_write_indirect_reg32().
12461 tp
->write32
= tg3_write_flush_reg32
;
12465 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
12466 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
12467 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
12468 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
12469 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
12472 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
12473 tp
->read32
= tg3_read_indirect_reg32
;
12474 tp
->write32
= tg3_write_indirect_reg32
;
12475 tp
->read32_mbox
= tg3_read_indirect_mbox
;
12476 tp
->write32_mbox
= tg3_write_indirect_mbox
;
12477 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
12478 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
12483 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12484 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
12485 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12487 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12488 tp
->read32_mbox
= tg3_read32_mbox_5906
;
12489 tp
->write32_mbox
= tg3_write32_mbox_5906
;
12490 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
12491 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
12494 if (tp
->write32
== tg3_write_indirect_reg32
||
12495 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12496 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12497 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
12498 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
12500 /* Get eeprom hw config before calling tg3_set_power_state().
12501 * In particular, the TG3_FLG2_IS_NIC flag must be
12502 * determined before calling tg3_set_power_state() so that
12503 * we know whether or not to switch out of Vaux power.
12504 * When the flag is set, it means that GPIO1 is used for eeprom
12505 * write protect and also implies that it is a LOM where GPIOs
12506 * are not used to switch power.
12508 tg3_get_eeprom_hw_cfg(tp
);
12510 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
12511 /* Allow reads and writes to the
12512 * APE register and memory space.
12514 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
12515 PCISTATE_ALLOW_APE_SHMEM_WR
;
12516 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12520 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12521 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12522 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12523 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12524 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
12526 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12527 * GPIO1 driven high will bring 5700's external PHY out of reset.
12528 * It is also used as eeprom write protect on LOMs.
12530 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
12531 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12532 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
12533 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
12534 GRC_LCLCTRL_GPIO_OUTPUT1
);
12535 /* Unused GPIO3 must be driven as output on 5752 because there
12536 * are no pull-up resistors on unused GPIO pins.
12538 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12539 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12541 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12542 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12543 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12545 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
12546 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
12547 /* Turn off the debug UART. */
12548 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12549 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12550 /* Keep VMain power. */
12551 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12552 GRC_LCLCTRL_GPIO_OUTPUT0
;
12555 /* Force the chip into D0. */
12556 err
= tg3_set_power_state(tp
, PCI_D0
);
12558 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12559 pci_name(tp
->pdev
));
12563 /* Derive initial jumbo mode from MTU assigned in
12564 * ether_setup() via the alloc_etherdev() call
12566 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12567 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12568 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12570 /* Determine WakeOnLan speed to use. */
12571 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12572 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12573 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12574 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12575 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12577 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12580 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12581 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
12583 /* A few boards don't want Ethernet@WireSpeed phy feature */
12584 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12585 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12586 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12587 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12588 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
12589 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12590 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12592 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12593 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12594 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12595 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12596 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12598 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12599 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
12600 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12601 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
) {
12602 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12603 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12604 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12605 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12606 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12607 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12608 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12609 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12610 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12612 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12615 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12616 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12617 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12618 if (tp
->phy_otp
== 0)
12619 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12622 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
12623 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
12625 tp
->mi_mode
= MAC_MI_MODE_BASE
;
12627 tp
->coalesce_mode
= 0;
12628 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
12629 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
12630 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
12632 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12633 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12634 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
12636 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
&&
12637 tr32(RCVLPC_STATS_ENABLE
) & RCVLPC_STATSENAB_ASF_FIX
) ||
12638 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
)
12639 tp
->tg3_flags3
|= TG3_FLG3_TOGGLE_10_100_L1PLLPD
;
12641 err
= tg3_mdio_init(tp
);
12645 /* Initialize data/descriptor byte/word swapping. */
12646 val
= tr32(GRC_MODE
);
12647 val
&= GRC_MODE_HOST_STACKUP
;
12648 tw32(GRC_MODE
, val
| tp
->grc_mode
);
12650 tg3_switch_clocks(tp
);
12652 /* Clear this out for sanity. */
12653 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12655 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12657 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
12658 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
12659 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
12661 if (chiprevid
== CHIPREV_ID_5701_A0
||
12662 chiprevid
== CHIPREV_ID_5701_B0
||
12663 chiprevid
== CHIPREV_ID_5701_B2
||
12664 chiprevid
== CHIPREV_ID_5701_B5
) {
12665 void __iomem
*sram_base
;
12667 /* Write some dummy words into the SRAM status block
12668 * area, see if it reads back correctly. If the return
12669 * value is bad, force enable the PCIX workaround.
12671 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
12673 writel(0x00000000, sram_base
);
12674 writel(0x00000000, sram_base
+ 4);
12675 writel(0xffffffff, sram_base
+ 4);
12676 if (readl(sram_base
) != 0x00000000)
12677 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12682 tg3_nvram_init(tp
);
12684 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
12685 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
12687 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12688 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
12689 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
12690 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
12692 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
12693 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
12694 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
12695 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
12696 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
12697 HOSTCC_MODE_CLRTICK_TXBD
);
12699 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
12700 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12701 tp
->misc_host_ctrl
);
12704 /* Preserve the APE MAC_MODE bits */
12705 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
12706 tp
->mac_mode
= tr32(MAC_MODE
) |
12707 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
12709 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
12711 /* these are limited to 10/100 only */
12712 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12713 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
12714 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12715 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12716 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
12717 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
12718 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
12719 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12720 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
12721 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
12722 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
12723 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
12724 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
12725 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
12727 err
= tg3_phy_probe(tp
);
12729 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
12730 pci_name(tp
->pdev
), err
);
12731 /* ... but do not return immediately ... */
12735 tg3_read_partno(tp
);
12736 tg3_read_fw_ver(tp
);
12738 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
12739 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12741 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12742 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
12744 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12747 /* 5700 {AX,BX} chips have a broken status block link
12748 * change bit implementation, so we must use the
12749 * status register in those cases.
12751 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12752 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
12754 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
12756 /* The led_ctrl is set during tg3_phy_probe, here we might
12757 * have to force the link status polling mechanism based
12758 * upon subsystem IDs.
12760 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
12761 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12762 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
12763 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
12764 TG3_FLAG_USE_LINKCHG_REG
);
12767 /* For all SERDES we poll the MAC status register. */
12768 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
12769 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
12771 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
12773 tp
->rx_offset
= NET_IP_ALIGN
;
12774 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12775 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
12778 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
12780 /* Increment the rx prod index on the rx std ring by at most
12781 * 8 for these chips to workaround hw errata.
12783 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12784 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12785 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12786 tp
->rx_std_max_post
= 8;
12788 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
12789 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
12790 PCIE_PWR_MGMT_L1_THRESH_MSK
;
12795 #ifdef CONFIG_SPARC
12796 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
12798 struct net_device
*dev
= tp
->dev
;
12799 struct pci_dev
*pdev
= tp
->pdev
;
12800 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
12801 const unsigned char *addr
;
12804 addr
= of_get_property(dp
, "local-mac-address", &len
);
12805 if (addr
&& len
== 6) {
12806 memcpy(dev
->dev_addr
, addr
, 6);
12807 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
12813 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
12815 struct net_device
*dev
= tp
->dev
;
12817 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
12818 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
12823 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
12825 struct net_device
*dev
= tp
->dev
;
12826 u32 hi
, lo
, mac_offset
;
12829 #ifdef CONFIG_SPARC
12830 if (!tg3_get_macaddr_sparc(tp
))
12835 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12836 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12837 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
12839 if (tg3_nvram_lock(tp
))
12840 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
12842 tg3_nvram_unlock(tp
);
12844 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12847 /* First try to get it from MAC address mailbox. */
12848 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
12849 if ((hi
>> 16) == 0x484b) {
12850 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12851 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
12853 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
12854 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12855 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12856 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12857 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
12859 /* Some old bootcode may report a 0 MAC address in SRAM */
12860 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
12863 /* Next, try NVRAM. */
12864 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
12865 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
12866 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
12867 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
12868 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
12870 /* Finally just fetch it out of the MAC control regs. */
12872 hi
= tr32(MAC_ADDR_0_HIGH
);
12873 lo
= tr32(MAC_ADDR_0_LOW
);
12875 dev
->dev_addr
[5] = lo
& 0xff;
12876 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12877 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12878 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12879 dev
->dev_addr
[1] = hi
& 0xff;
12880 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12884 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
12885 #ifdef CONFIG_SPARC
12886 if (!tg3_get_default_macaddr_sparc(tp
))
12891 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
12895 #define BOUNDARY_SINGLE_CACHELINE 1
12896 #define BOUNDARY_MULTI_CACHELINE 2
12898 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
12900 int cacheline_size
;
12904 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
12906 cacheline_size
= 1024;
12908 cacheline_size
= (int) byte
* 4;
12910 /* On 5703 and later chips, the boundary bits have no
12913 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12914 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
12915 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12918 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12919 goal
= BOUNDARY_MULTI_CACHELINE
;
12921 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12922 goal
= BOUNDARY_SINGLE_CACHELINE
;
12931 /* PCI controllers on most RISC systems tend to disconnect
12932 * when a device tries to burst across a cache-line boundary.
12933 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12935 * Unfortunately, for PCI-E there are only limited
12936 * write-side controls for this, and thus for reads
12937 * we will still get the disconnects. We'll also waste
12938 * these PCI cycles for both read and write for chips
12939 * other than 5700 and 5701 which do not implement the
12942 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12943 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
12944 switch (cacheline_size
) {
12949 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12950 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
12951 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
12953 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12954 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12959 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
12960 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
12964 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12965 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12968 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12969 switch (cacheline_size
) {
12973 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12974 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12975 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
12981 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12982 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
12986 switch (cacheline_size
) {
12988 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12989 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
12990 DMA_RWCTRL_WRITE_BNDRY_16
);
12995 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12996 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
12997 DMA_RWCTRL_WRITE_BNDRY_32
);
13002 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13003 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
13004 DMA_RWCTRL_WRITE_BNDRY_64
);
13009 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
13010 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
13011 DMA_RWCTRL_WRITE_BNDRY_128
);
13016 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
13017 DMA_RWCTRL_WRITE_BNDRY_256
);
13020 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
13021 DMA_RWCTRL_WRITE_BNDRY_512
);
13025 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
13026 DMA_RWCTRL_WRITE_BNDRY_1024
);
13035 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
13037 struct tg3_internal_buffer_desc test_desc
;
13038 u32 sram_dma_descs
;
13041 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
13043 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
13044 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
13045 tw32(RDMAC_STATUS
, 0);
13046 tw32(WDMAC_STATUS
, 0);
13048 tw32(BUFMGR_MODE
, 0);
13049 tw32(FTQ_RESET
, 0);
13051 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
13052 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
13053 test_desc
.nic_mbuf
= 0x00002100;
13054 test_desc
.len
= size
;
13057 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13058 * the *second* time the tg3 driver was getting loaded after an
13061 * Broadcom tells me:
13062 * ...the DMA engine is connected to the GRC block and a DMA
13063 * reset may affect the GRC block in some unpredictable way...
13064 * The behavior of resets to individual blocks has not been tested.
13066 * Broadcom noted the GRC reset will also reset all sub-components.
13069 test_desc
.cqid_sqid
= (13 << 8) | 2;
13071 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
13074 test_desc
.cqid_sqid
= (16 << 8) | 7;
13076 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
13079 test_desc
.flags
= 0x00000005;
13081 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
13084 val
= *(((u32
*)&test_desc
) + i
);
13085 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
13086 sram_dma_descs
+ (i
* sizeof(u32
)));
13087 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
13089 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
13092 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
13094 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
13098 for (i
= 0; i
< 40; i
++) {
13102 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
13104 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
13105 if ((val
& 0xffff) == sram_dma_descs
) {
13116 #define TEST_BUFFER_SIZE 0x2000
13118 static int __devinit
tg3_test_dma(struct tg3
*tp
)
13120 dma_addr_t buf_dma
;
13121 u32
*buf
, saved_dma_rwctrl
;
13124 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
13130 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
13131 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
13133 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
13135 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13136 /* DMA read watermark not used on PCIE */
13137 tp
->dma_rwctrl
|= 0x00180000;
13138 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13139 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13140 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13141 tp
->dma_rwctrl
|= 0x003f0000;
13143 tp
->dma_rwctrl
|= 0x003f000f;
13145 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13146 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13147 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13148 u32 read_water
= 0x7;
13150 /* If the 5704 is behind the EPB bridge, we can
13151 * do the less restrictive ONE_DMA workaround for
13152 * better performance.
13154 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13155 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13156 tp
->dma_rwctrl
|= 0x8000;
13157 else if (ccval
== 0x6 || ccval
== 0x7)
13158 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13160 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13162 /* Set bit 23 to enable PCIX hw bug fix */
13164 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13165 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13167 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13168 /* 5780 always in PCIX mode */
13169 tp
->dma_rwctrl
|= 0x00144000;
13170 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13171 /* 5714 always in PCIX mode */
13172 tp
->dma_rwctrl
|= 0x00148000;
13174 tp
->dma_rwctrl
|= 0x001b000f;
13178 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13179 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13180 tp
->dma_rwctrl
&= 0xfffffff0;
13182 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13183 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13184 /* Remove this if it causes problems for some boards. */
13185 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13187 /* On 5700/5701 chips, we need to set this bit.
13188 * Otherwise the chip will issue cacheline transactions
13189 * to streamable DMA memory with not all the byte
13190 * enables turned on. This is an error on several
13191 * RISC PCI controllers, in particular sparc64.
13193 * On 5703/5704 chips, this bit has been reassigned
13194 * a different meaning. In particular, it is used
13195 * on those chips to enable a PCI-X workaround.
13197 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13200 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13203 /* Unneeded, already done by tg3_get_invariants. */
13204 tg3_switch_clocks(tp
);
13208 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13209 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
13212 /* It is best to perform DMA test with maximum write burst size
13213 * to expose the 5700/5701 write DMA bug.
13215 saved_dma_rwctrl
= tp
->dma_rwctrl
;
13216 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13217 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13222 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
13225 /* Send the buffer to the chip. */
13226 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
13228 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
13233 /* validate data reached card RAM correctly. */
13234 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13236 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
13237 if (le32_to_cpu(val
) != p
[i
]) {
13238 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
13239 /* ret = -ENODEV here? */
13244 /* Now read it back. */
13245 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
13247 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
13253 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13257 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13258 DMA_RWCTRL_WRITE_BNDRY_16
) {
13259 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13260 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13261 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13264 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
13270 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
13276 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13277 DMA_RWCTRL_WRITE_BNDRY_16
) {
13278 static struct pci_device_id dma_wait_state_chipsets
[] = {
13279 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
13280 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
13284 /* DMA test passed without adjusting DMA boundary,
13285 * now look for chipsets that are known to expose the
13286 * DMA bug without failing the test.
13288 if (pci_dev_present(dma_wait_state_chipsets
)) {
13289 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13290 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13293 /* Safe to use the calculated DMA boundary. */
13294 tp
->dma_rwctrl
= saved_dma_rwctrl
;
13296 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13300 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
13305 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
13307 tp
->link_config
.advertising
=
13308 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
13309 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
13310 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
13311 ADVERTISED_Autoneg
| ADVERTISED_MII
);
13312 tp
->link_config
.speed
= SPEED_INVALID
;
13313 tp
->link_config
.duplex
= DUPLEX_INVALID
;
13314 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
13315 tp
->link_config
.active_speed
= SPEED_INVALID
;
13316 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
13317 tp
->link_config
.phy_is_low_power
= 0;
13318 tp
->link_config
.orig_speed
= SPEED_INVALID
;
13319 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
13320 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
13323 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
13325 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13326 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13327 DEFAULT_MB_RDMA_LOW_WATER_5705
;
13328 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13329 DEFAULT_MB_MACRX_LOW_WATER_5705
;
13330 tp
->bufmgr_config
.mbuf_high_water
=
13331 DEFAULT_MB_HIGH_WATER_5705
;
13332 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13333 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13334 DEFAULT_MB_MACRX_LOW_WATER_5906
;
13335 tp
->bufmgr_config
.mbuf_high_water
=
13336 DEFAULT_MB_HIGH_WATER_5906
;
13339 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13340 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
13341 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13342 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
13343 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13344 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
13346 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13347 DEFAULT_MB_RDMA_LOW_WATER
;
13348 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13349 DEFAULT_MB_MACRX_LOW_WATER
;
13350 tp
->bufmgr_config
.mbuf_high_water
=
13351 DEFAULT_MB_HIGH_WATER
;
13353 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13354 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
13355 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13356 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
13357 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13358 DEFAULT_MB_HIGH_WATER_JUMBO
;
13361 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
13362 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
13365 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
13367 switch (tp
->phy_id
& PHY_ID_MASK
) {
13368 case PHY_ID_BCM5400
: return "5400";
13369 case PHY_ID_BCM5401
: return "5401";
13370 case PHY_ID_BCM5411
: return "5411";
13371 case PHY_ID_BCM5701
: return "5701";
13372 case PHY_ID_BCM5703
: return "5703";
13373 case PHY_ID_BCM5704
: return "5704";
13374 case PHY_ID_BCM5705
: return "5705";
13375 case PHY_ID_BCM5750
: return "5750";
13376 case PHY_ID_BCM5752
: return "5752";
13377 case PHY_ID_BCM5714
: return "5714";
13378 case PHY_ID_BCM5780
: return "5780";
13379 case PHY_ID_BCM5755
: return "5755";
13380 case PHY_ID_BCM5787
: return "5787";
13381 case PHY_ID_BCM5784
: return "5784";
13382 case PHY_ID_BCM5756
: return "5722/5756";
13383 case PHY_ID_BCM5906
: return "5906";
13384 case PHY_ID_BCM5761
: return "5761";
13385 case PHY_ID_BCM8002
: return "8002/serdes";
13386 case 0: return "serdes";
13387 default: return "unknown";
13391 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
13393 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13394 strcpy(str
, "PCI Express");
13396 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13397 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
13399 strcpy(str
, "PCIX:");
13401 if ((clock_ctrl
== 7) ||
13402 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
13403 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
13404 strcat(str
, "133MHz");
13405 else if (clock_ctrl
== 0)
13406 strcat(str
, "33MHz");
13407 else if (clock_ctrl
== 2)
13408 strcat(str
, "50MHz");
13409 else if (clock_ctrl
== 4)
13410 strcat(str
, "66MHz");
13411 else if (clock_ctrl
== 6)
13412 strcat(str
, "100MHz");
13414 strcpy(str
, "PCI:");
13415 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
13416 strcat(str
, "66MHz");
13418 strcat(str
, "33MHz");
13420 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
13421 strcat(str
, ":32-bit");
13423 strcat(str
, ":64-bit");
13427 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
13429 struct pci_dev
*peer
;
13430 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
13432 for (func
= 0; func
< 8; func
++) {
13433 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
13434 if (peer
&& peer
!= tp
->pdev
)
13438 /* 5704 can be configured in single-port mode, set peer to
13439 * tp->pdev in that case.
13447 * We don't need to keep the refcount elevated; there's no way
13448 * to remove one half of this device without removing the other
13455 static void __devinit
tg3_init_coal(struct tg3
*tp
)
13457 struct ethtool_coalesce
*ec
= &tp
->coal
;
13459 memset(ec
, 0, sizeof(*ec
));
13460 ec
->cmd
= ETHTOOL_GCOALESCE
;
13461 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
13462 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
13463 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
13464 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
13465 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
13466 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
13467 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
13468 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
13469 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
13471 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
13472 HOSTCC_MODE_CLRTICK_TXBD
)) {
13473 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
13474 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
13475 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
13476 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
13479 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13480 ec
->rx_coalesce_usecs_irq
= 0;
13481 ec
->tx_coalesce_usecs_irq
= 0;
13482 ec
->stats_block_coalesce_usecs
= 0;
13486 static const struct net_device_ops tg3_netdev_ops
= {
13487 .ndo_open
= tg3_open
,
13488 .ndo_stop
= tg3_close
,
13489 .ndo_start_xmit
= tg3_start_xmit
,
13490 .ndo_get_stats
= tg3_get_stats
,
13491 .ndo_validate_addr
= eth_validate_addr
,
13492 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13493 .ndo_set_mac_address
= tg3_set_mac_addr
,
13494 .ndo_do_ioctl
= tg3_ioctl
,
13495 .ndo_tx_timeout
= tg3_tx_timeout
,
13496 .ndo_change_mtu
= tg3_change_mtu
,
13497 #if TG3_VLAN_TAG_USED
13498 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13500 #ifdef CONFIG_NET_POLL_CONTROLLER
13501 .ndo_poll_controller
= tg3_poll_controller
,
13505 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
13506 .ndo_open
= tg3_open
,
13507 .ndo_stop
= tg3_close
,
13508 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
13509 .ndo_get_stats
= tg3_get_stats
,
13510 .ndo_validate_addr
= eth_validate_addr
,
13511 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13512 .ndo_set_mac_address
= tg3_set_mac_addr
,
13513 .ndo_do_ioctl
= tg3_ioctl
,
13514 .ndo_tx_timeout
= tg3_tx_timeout
,
13515 .ndo_change_mtu
= tg3_change_mtu
,
13516 #if TG3_VLAN_TAG_USED
13517 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13519 #ifdef CONFIG_NET_POLL_CONTROLLER
13520 .ndo_poll_controller
= tg3_poll_controller
,
13524 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
13525 const struct pci_device_id
*ent
)
13527 static int tg3_version_printed
= 0;
13528 struct net_device
*dev
;
13530 int i
, err
, pm_cap
;
13531 u32 sndmbx
, rcvmbx
, intmbx
;
13533 u64 dma_mask
, persist_dma_mask
;
13535 if (tg3_version_printed
++ == 0)
13536 printk(KERN_INFO
"%s", version
);
13538 err
= pci_enable_device(pdev
);
13540 printk(KERN_ERR PFX
"Cannot enable PCI device, "
13545 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13547 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13549 goto err_out_disable_pdev
;
13552 pci_set_master(pdev
);
13554 /* Find power-management capability. */
13555 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13557 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13560 goto err_out_free_res
;
13563 dev
= alloc_etherdev(sizeof(*tp
));
13565 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13567 goto err_out_free_res
;
13570 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13572 #if TG3_VLAN_TAG_USED
13573 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13576 tp
= netdev_priv(dev
);
13579 tp
->pm_cap
= pm_cap
;
13580 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13581 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13584 tp
->msg_enable
= tg3_debug
;
13586 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13588 /* The word/byte swap controls here control register access byte
13589 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13592 tp
->misc_host_ctrl
=
13593 MISC_HOST_CTRL_MASK_PCI_INT
|
13594 MISC_HOST_CTRL_WORD_SWAP
|
13595 MISC_HOST_CTRL_INDIR_ACCESS
|
13596 MISC_HOST_CTRL_PCISTATE_RW
;
13598 /* The NONFRM (non-frame) byte/word swap controls take effect
13599 * on descriptor entries, anything which isn't packet data.
13601 * The StrongARM chips on the board (one for tx, one for rx)
13602 * are running in big-endian mode.
13604 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13605 GRC_MODE_WSWAP_NONFRM_DATA
);
13606 #ifdef __BIG_ENDIAN
13607 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13609 spin_lock_init(&tp
->lock
);
13610 spin_lock_init(&tp
->indirect_lock
);
13611 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13613 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13615 printk(KERN_ERR PFX
"Cannot map device registers, "
13618 goto err_out_free_dev
;
13621 tg3_init_link_config(tp
);
13623 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
13624 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
13626 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
13627 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
13628 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
13629 for (i
= 0; i
< TG3_IRQ_MAX_VECS
; i
++) {
13630 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
13633 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
13635 tnapi
->int_mbox
= intmbx
;
13641 tnapi
->consmbox
= rcvmbx
;
13642 tnapi
->prodmbox
= sndmbx
;
13645 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
13647 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
13649 if (!(tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSIX
))
13653 * If we support MSIX, we'll be using RSS. If we're using
13654 * RSS, the first vector only handles link interrupts and the
13655 * remaining vectors handle rx and tx interrupts. Reuse the
13656 * mailbox values for the next iteration. The values we setup
13657 * above are still useful for the single vectored mode.
13670 netif_napi_add(dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
13671 dev
->ethtool_ops
= &tg3_ethtool_ops
;
13672 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
13673 dev
->irq
= pdev
->irq
;
13675 err
= tg3_get_invariants(tp
);
13677 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
13679 goto err_out_iounmap
;
13682 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13683 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13684 dev
->netdev_ops
= &tg3_netdev_ops
;
13686 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
13689 /* The EPB bridge inside 5714, 5715, and 5780 and any
13690 * device behind the EPB cannot support DMA addresses > 40-bit.
13691 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13692 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13693 * do DMA address check in tg3_start_xmit().
13695 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
13696 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
13697 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
13698 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
13699 #ifdef CONFIG_HIGHMEM
13700 dma_mask
= DMA_BIT_MASK(64);
13703 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
13705 /* Configure DMA attributes. */
13706 if (dma_mask
> DMA_BIT_MASK(32)) {
13707 err
= pci_set_dma_mask(pdev
, dma_mask
);
13709 dev
->features
|= NETIF_F_HIGHDMA
;
13710 err
= pci_set_consistent_dma_mask(pdev
,
13713 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
13714 "DMA for consistent allocations\n");
13715 goto err_out_iounmap
;
13719 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
13720 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
13722 printk(KERN_ERR PFX
"No usable DMA configuration, "
13724 goto err_out_iounmap
;
13728 tg3_init_bufmgr_config(tp
);
13730 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
13731 tp
->fw_needed
= FIRMWARE_TG3
;
13733 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13734 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
13736 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13737 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13738 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
13739 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13740 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
13741 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
13743 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
13744 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13745 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13747 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13750 /* TSO is on by default on chips that support hardware TSO.
13751 * Firmware TSO on older chips gives lower performance, so it
13752 * is off by default, but can be enabled using ethtool.
13754 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13755 if (dev
->features
& NETIF_F_IP_CSUM
)
13756 dev
->features
|= NETIF_F_TSO
;
13757 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
13758 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
13759 dev
->features
|= NETIF_F_TSO6
;
13760 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13761 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13762 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
13763 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13764 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13765 dev
->features
|= NETIF_F_TSO_ECN
;
13769 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
13770 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
13771 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
13772 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
13773 tp
->rx_pending
= 63;
13776 err
= tg3_get_device_address(tp
);
13778 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
13783 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13784 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
13785 if (!tp
->aperegs
) {
13786 printk(KERN_ERR PFX
"Cannot map APE registers, "
13792 tg3_ape_lock_init(tp
);
13794 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
13795 tg3_read_dash_ver(tp
);
13799 * Reset chip in case UNDI or EFI driver did not shutdown
13800 * DMA self test will enable WDMAC and we'll see (spurious)
13801 * pending DMA on the PCI bus at that point.
13803 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
13804 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
13805 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
13806 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13809 err
= tg3_test_dma(tp
);
13811 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
13812 goto err_out_apeunmap
;
13815 /* flow control autonegotiation is default behavior */
13816 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
13817 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
13821 pci_set_drvdata(pdev
, dev
);
13823 err
= register_netdev(dev
);
13825 printk(KERN_ERR PFX
"Cannot register net device, "
13827 goto err_out_apeunmap
;
13830 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13832 tp
->board_part_number
,
13833 tp
->pci_chip_rev_id
,
13834 tg3_bus_string(tp
, str
),
13837 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
13839 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13841 tp
->mdio_bus
->phy_map
[PHY_ADDR
]->drv
->name
,
13842 dev_name(&tp
->mdio_bus
->phy_map
[PHY_ADDR
]->dev
));
13845 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13846 tp
->dev
->name
, tg3_phy_string(tp
),
13847 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
13848 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
13849 "10/100/1000Base-T")),
13850 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
13852 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13854 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
13855 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
13856 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
13857 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
13858 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
13859 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13860 dev
->name
, tp
->dma_rwctrl
,
13861 (pdev
->dma_mask
== DMA_BIT_MASK(32)) ? 32 :
13862 (((u64
) pdev
->dma_mask
== DMA_BIT_MASK(40)) ? 40 : 64));
13868 iounmap(tp
->aperegs
);
13869 tp
->aperegs
= NULL
;
13874 release_firmware(tp
->fw
);
13886 pci_release_regions(pdev
);
13888 err_out_disable_pdev
:
13889 pci_disable_device(pdev
);
13890 pci_set_drvdata(pdev
, NULL
);
13894 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
13896 struct net_device
*dev
= pci_get_drvdata(pdev
);
13899 struct tg3
*tp
= netdev_priv(dev
);
13902 release_firmware(tp
->fw
);
13904 flush_scheduled_work();
13906 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
13911 unregister_netdev(dev
);
13913 iounmap(tp
->aperegs
);
13914 tp
->aperegs
= NULL
;
13921 pci_release_regions(pdev
);
13922 pci_disable_device(pdev
);
13923 pci_set_drvdata(pdev
, NULL
);
13927 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
13929 struct net_device
*dev
= pci_get_drvdata(pdev
);
13930 struct tg3
*tp
= netdev_priv(dev
);
13931 pci_power_t target_state
;
13934 /* PCI register 4 needs to be saved whether netif_running() or not.
13935 * MSI address and data need to be saved if using MSI and
13938 pci_save_state(pdev
);
13940 if (!netif_running(dev
))
13943 flush_scheduled_work();
13945 tg3_netif_stop(tp
);
13947 del_timer_sync(&tp
->timer
);
13949 tg3_full_lock(tp
, 1);
13950 tg3_disable_ints(tp
);
13951 tg3_full_unlock(tp
);
13953 netif_device_detach(dev
);
13955 tg3_full_lock(tp
, 0);
13956 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13957 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
13958 tg3_full_unlock(tp
);
13960 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
13962 err
= tg3_set_power_state(tp
, target_state
);
13966 tg3_full_lock(tp
, 0);
13968 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13969 err2
= tg3_restart_hw(tp
, 1);
13973 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13974 add_timer(&tp
->timer
);
13976 netif_device_attach(dev
);
13977 tg3_netif_start(tp
);
13980 tg3_full_unlock(tp
);
13989 static int tg3_resume(struct pci_dev
*pdev
)
13991 struct net_device
*dev
= pci_get_drvdata(pdev
);
13992 struct tg3
*tp
= netdev_priv(dev
);
13995 pci_restore_state(tp
->pdev
);
13997 if (!netif_running(dev
))
14000 err
= tg3_set_power_state(tp
, PCI_D0
);
14004 netif_device_attach(dev
);
14006 tg3_full_lock(tp
, 0);
14008 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
14009 err
= tg3_restart_hw(tp
, 1);
14013 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
14014 add_timer(&tp
->timer
);
14016 tg3_netif_start(tp
);
14019 tg3_full_unlock(tp
);
14027 static struct pci_driver tg3_driver
= {
14028 .name
= DRV_MODULE_NAME
,
14029 .id_table
= tg3_pci_tbl
,
14030 .probe
= tg3_init_one
,
14031 .remove
= __devexit_p(tg3_remove_one
),
14032 .suspend
= tg3_suspend
,
14033 .resume
= tg3_resume
14036 static int __init
tg3_init(void)
14038 return pci_register_driver(&tg3_driver
);
14041 static void __exit
tg3_cleanup(void)
14043 pci_unregister_driver(&tg3_driver
);
14046 module_init(tg3_init
);
14047 module_exit(tg3_cleanup
);