2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.101"
72 #define DRV_MODULE_RELDATE "August 28, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
106 /* Do not place this n-ring entries value into the tp struct itself,
107 * we really want to expose these constants to GCC so that modulo et
108 * al. operations are done with shifts and masks instead of with
109 * hw multiply/modulo instructions. Another solution would be to
110 * replace things like '% foo' with '& (foo - 1)'.
112 #define TG3_RX_RCB_RING_SIZE(tp) \
113 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
115 #define TG3_TX_RING_SIZE 512
116 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
118 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
121 TG3_RX_JUMBO_RING_SIZE)
122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
123 TG3_RX_RCB_RING_SIZE(tp))
124 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
126 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
128 #define TG3_DMA_BYTE_ENAB 64
130 #define TG3_RX_STD_DMA_SZ 1536
131 #define TG3_RX_JMB_DMA_SZ 9046
133 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
135 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
136 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
138 /* minimum number of free TX descriptors required to wake up TX process */
139 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
141 #define TG3_RAW_IP_ALIGN 2
143 /* number of ETHTOOL_GSTATS u64's */
144 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
146 #define TG3_NUM_TEST 6
148 #define FIRMWARE_TG3 "tigon/tg3.bin"
149 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
150 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
152 static char version
[] __devinitdata
=
153 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
155 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
156 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
157 MODULE_LICENSE("GPL");
158 MODULE_VERSION(DRV_MODULE_VERSION
);
159 MODULE_FIRMWARE(FIRMWARE_TG3
);
160 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
161 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
164 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
165 module_param(tg3_debug
, int, 0);
166 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
168 static struct pci_device_id tg3_pci_tbl
[] = {
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5720
)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750M
)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
235 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
236 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
237 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
238 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
245 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
247 static const struct {
248 const char string
[ETH_GSTRING_LEN
];
249 } ethtool_stats_keys
[TG3_NUM_STATS
] = {
252 { "rx_ucast_packets" },
253 { "rx_mcast_packets" },
254 { "rx_bcast_packets" },
256 { "rx_align_errors" },
257 { "rx_xon_pause_rcvd" },
258 { "rx_xoff_pause_rcvd" },
259 { "rx_mac_ctrl_rcvd" },
260 { "rx_xoff_entered" },
261 { "rx_frame_too_long_errors" },
263 { "rx_undersize_packets" },
264 { "rx_in_length_errors" },
265 { "rx_out_length_errors" },
266 { "rx_64_or_less_octet_packets" },
267 { "rx_65_to_127_octet_packets" },
268 { "rx_128_to_255_octet_packets" },
269 { "rx_256_to_511_octet_packets" },
270 { "rx_512_to_1023_octet_packets" },
271 { "rx_1024_to_1522_octet_packets" },
272 { "rx_1523_to_2047_octet_packets" },
273 { "rx_2048_to_4095_octet_packets" },
274 { "rx_4096_to_8191_octet_packets" },
275 { "rx_8192_to_9022_octet_packets" },
282 { "tx_flow_control" },
284 { "tx_single_collisions" },
285 { "tx_mult_collisions" },
287 { "tx_excessive_collisions" },
288 { "tx_late_collisions" },
289 { "tx_collide_2times" },
290 { "tx_collide_3times" },
291 { "tx_collide_4times" },
292 { "tx_collide_5times" },
293 { "tx_collide_6times" },
294 { "tx_collide_7times" },
295 { "tx_collide_8times" },
296 { "tx_collide_9times" },
297 { "tx_collide_10times" },
298 { "tx_collide_11times" },
299 { "tx_collide_12times" },
300 { "tx_collide_13times" },
301 { "tx_collide_14times" },
302 { "tx_collide_15times" },
303 { "tx_ucast_packets" },
304 { "tx_mcast_packets" },
305 { "tx_bcast_packets" },
306 { "tx_carrier_sense_errors" },
310 { "dma_writeq_full" },
311 { "dma_write_prioq_full" },
315 { "rx_threshold_hit" },
317 { "dma_readq_full" },
318 { "dma_read_prioq_full" },
319 { "tx_comp_queue_full" },
321 { "ring_set_send_prod_index" },
322 { "ring_status_update" },
324 { "nic_avoided_irqs" },
325 { "nic_tx_threshold_hit" }
328 static const struct {
329 const char string
[ETH_GSTRING_LEN
];
330 } ethtool_test_keys
[TG3_NUM_TEST
] = {
331 { "nvram test (online) " },
332 { "link test (online) " },
333 { "register test (offline)" },
334 { "memory test (offline)" },
335 { "loopback test (offline)" },
336 { "interrupt test (offline)" },
339 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
341 writel(val
, tp
->regs
+ off
);
344 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
346 return (readl(tp
->regs
+ off
));
349 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
351 writel(val
, tp
->aperegs
+ off
);
354 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
356 return (readl(tp
->aperegs
+ off
));
359 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
363 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
364 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
365 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
366 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
369 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
371 writel(val
, tp
->regs
+ off
);
372 readl(tp
->regs
+ off
);
375 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
380 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
381 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
382 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
383 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
387 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
391 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
392 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
393 TG3_64BIT_REG_LOW
, val
);
396 if (off
== (MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
)) {
397 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
398 TG3_64BIT_REG_LOW
, val
);
402 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
403 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
404 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
405 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
407 /* In indirect mode when disabling interrupts, we also need
408 * to clear the interrupt bit in the GRC local ctrl register.
410 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
412 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
413 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
417 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
422 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
423 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
424 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
425 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
429 /* usec_wait specifies the wait time in usec when writing to certain registers
430 * where it is unsafe to read back the register without some delay.
431 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
432 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
434 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
436 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) ||
437 (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
438 /* Non-posted methods */
439 tp
->write32(tp
, off
, val
);
442 tg3_write32(tp
, off
, val
);
447 /* Wait again after the read for the posted method to guarantee that
448 * the wait time is met.
454 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
456 tp
->write32_mbox(tp
, off
, val
);
457 if (!(tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) &&
458 !(tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
))
459 tp
->read32_mbox(tp
, off
);
462 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
464 void __iomem
*mbox
= tp
->regs
+ off
;
466 if (tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
)
468 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
472 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
474 return (readl(tp
->regs
+ off
+ GRCMBOX_BASE
));
477 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
479 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
482 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
483 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
484 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
485 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
486 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
488 #define tw32(reg,val) tp->write32(tp, reg, val)
489 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
490 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
491 #define tr32(reg) tp->read32(tp, reg)
493 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
497 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
498 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
501 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
502 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
503 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
504 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
506 /* Always leave this as zero. */
507 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
509 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
510 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
512 /* Always leave this as zero. */
513 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
515 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
518 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
522 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) &&
523 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
528 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
529 if (tp
->tg3_flags
& TG3_FLAG_SRAM_USE_CONFIG
) {
530 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
531 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
533 /* Always leave this as zero. */
534 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
536 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
537 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
539 /* Always leave this as zero. */
540 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
542 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
545 static void tg3_ape_lock_init(struct tg3
*tp
)
549 /* Make sure the driver hasn't any stale locks. */
550 for (i
= 0; i
< 8; i
++)
551 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ 4 * i
,
552 APE_LOCK_GRANT_DRIVER
);
555 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
561 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
565 case TG3_APE_LOCK_GRC
:
566 case TG3_APE_LOCK_MEM
:
574 tg3_ape_write32(tp
, TG3_APE_LOCK_REQ
+ off
, APE_LOCK_REQ_DRIVER
);
576 /* Wait for up to 1 millisecond to acquire lock. */
577 for (i
= 0; i
< 100; i
++) {
578 status
= tg3_ape_read32(tp
, TG3_APE_LOCK_GRANT
+ off
);
579 if (status
== APE_LOCK_GRANT_DRIVER
)
584 if (status
!= APE_LOCK_GRANT_DRIVER
) {
585 /* Revoke the lock request. */
586 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
,
587 APE_LOCK_GRANT_DRIVER
);
595 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
599 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
603 case TG3_APE_LOCK_GRC
:
604 case TG3_APE_LOCK_MEM
:
611 tg3_ape_write32(tp
, TG3_APE_LOCK_GRANT
+ off
, APE_LOCK_GRANT_DRIVER
);
614 static void tg3_disable_ints(struct tg3
*tp
)
616 tw32(TG3PCI_MISC_HOST_CTRL
,
617 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
618 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 0x00000001);
621 static void tg3_enable_ints(struct tg3
*tp
)
624 struct tg3_napi
*tnapi
= &tp
->napi
[0];
628 tw32(TG3PCI_MISC_HOST_CTRL
,
629 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
630 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
631 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
632 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
634 coal_now
= tnapi
->coal_now
;
636 /* Force an initial interrupt */
637 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
638 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
639 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
641 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
642 HOSTCC_MODE_ENABLE
| coal_now
);
645 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
647 struct tg3
*tp
= tnapi
->tp
;
648 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
649 unsigned int work_exists
= 0;
651 /* check for phy events */
652 if (!(tp
->tg3_flags
&
653 (TG3_FLAG_USE_LINKCHG_REG
|
654 TG3_FLAG_POLL_SERDES
))) {
655 if (sblk
->status
& SD_STATUS_LINK_CHG
)
658 /* check for RX/TX work to do */
659 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
||
660 sblk
->idx
[0].rx_producer
!= tnapi
->rx_rcb_ptr
)
667 * similar to tg3_enable_ints, but it accurately determines whether there
668 * is new work pending and can return without flushing the PIO write
669 * which reenables interrupts
671 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
673 struct tg3
*tp
= tnapi
->tp
;
675 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
678 /* When doing tagged status, this work check is unnecessary.
679 * The last_tag we write above tells the chip which piece of
680 * work we've completed.
682 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) &&
684 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
685 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
688 static inline void tg3_netif_stop(struct tg3
*tp
)
690 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
691 napi_disable(&tp
->napi
[0].napi
);
692 netif_tx_disable(tp
->dev
);
695 static inline void tg3_netif_start(struct tg3
*tp
)
697 struct tg3_napi
*tnapi
= &tp
->napi
[0];
698 netif_wake_queue(tp
->dev
);
699 /* NOTE: unconditional netif_wake_queue is only appropriate
700 * so long as all callers are assured to have free tx slots
701 * (such as after tg3_init_hw)
703 napi_enable(&tnapi
->napi
);
704 tnapi
->hw_status
->status
|= SD_STATUS_UPDATED
;
708 static void tg3_switch_clocks(struct tg3
*tp
)
710 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
713 if ((tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
714 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
717 orig_clock_ctrl
= clock_ctrl
;
718 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
719 CLOCK_CTRL_CLKRUN_OENABLE
|
721 tp
->pci_clock_ctrl
= clock_ctrl
;
723 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
724 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
725 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
726 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
728 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
729 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
731 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
733 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
734 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
737 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
740 #define PHY_BUSY_LOOPS 5000
742 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
748 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
750 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
756 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
757 MI_COM_PHY_ADDR_MASK
);
758 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
759 MI_COM_REG_ADDR_MASK
);
760 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
762 tw32_f(MAC_MI_COM
, frame_val
);
764 loops
= PHY_BUSY_LOOPS
;
767 frame_val
= tr32(MAC_MI_COM
);
769 if ((frame_val
& MI_COM_BUSY
) == 0) {
771 frame_val
= tr32(MAC_MI_COM
);
779 *val
= frame_val
& MI_COM_DATA_MASK
;
783 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
784 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
791 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
797 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
798 (reg
== MII_TG3_CTRL
|| reg
== MII_TG3_AUX_CTRL
))
801 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
803 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
807 frame_val
= ((PHY_ADDR
<< MI_COM_PHY_ADDR_SHIFT
) &
808 MI_COM_PHY_ADDR_MASK
);
809 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
810 MI_COM_REG_ADDR_MASK
);
811 frame_val
|= (val
& MI_COM_DATA_MASK
);
812 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
814 tw32_f(MAC_MI_COM
, frame_val
);
816 loops
= PHY_BUSY_LOOPS
;
819 frame_val
= tr32(MAC_MI_COM
);
820 if ((frame_val
& MI_COM_BUSY
) == 0) {
822 frame_val
= tr32(MAC_MI_COM
);
832 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
833 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
840 static int tg3_bmcr_reset(struct tg3
*tp
)
845 /* OK, reset it, and poll the BMCR_RESET bit until it
846 * clears or we time out.
848 phy_control
= BMCR_RESET
;
849 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
855 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
859 if ((phy_control
& BMCR_RESET
) == 0) {
871 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
873 struct tg3
*tp
= bp
->priv
;
876 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
879 if (tg3_readphy(tp
, reg
, &val
))
885 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
887 struct tg3
*tp
= bp
->priv
;
889 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_PAUSED
)
892 if (tg3_writephy(tp
, reg
, val
))
898 static int tg3_mdio_reset(struct mii_bus
*bp
)
903 static void tg3_mdio_config_5785(struct tg3
*tp
)
906 struct phy_device
*phydev
;
908 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
909 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
910 case TG3_PHY_ID_BCM50610
:
911 val
= MAC_PHYCFG2_50610_LED_MODES
;
913 case TG3_PHY_ID_BCMAC131
:
914 val
= MAC_PHYCFG2_AC131_LED_MODES
;
916 case TG3_PHY_ID_RTL8211C
:
917 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
919 case TG3_PHY_ID_RTL8201E
:
920 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
926 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
927 tw32(MAC_PHYCFG2
, val
);
929 val
= tr32(MAC_PHYCFG1
);
930 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
931 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
932 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
933 tw32(MAC_PHYCFG1
, val
);
938 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
))
939 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
940 MAC_PHYCFG2_FMODE_MASK_MASK
|
941 MAC_PHYCFG2_GMODE_MASK_MASK
|
942 MAC_PHYCFG2_ACT_MASK_MASK
|
943 MAC_PHYCFG2_QUAL_MASK_MASK
|
944 MAC_PHYCFG2_INBAND_ENABLE
;
946 tw32(MAC_PHYCFG2
, val
);
948 val
= tr32(MAC_PHYCFG1
);
949 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
950 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
951 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
952 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
953 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
954 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
955 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
957 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
958 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
959 tw32(MAC_PHYCFG1
, val
);
961 val
= tr32(MAC_EXT_RGMII_MODE
);
962 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
963 MAC_RGMII_MODE_RX_QUALITY
|
964 MAC_RGMII_MODE_RX_ACTIVITY
|
965 MAC_RGMII_MODE_RX_ENG_DET
|
966 MAC_RGMII_MODE_TX_ENABLE
|
967 MAC_RGMII_MODE_TX_LOWPWR
|
968 MAC_RGMII_MODE_TX_RESET
);
969 if (!(tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)) {
970 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
971 val
|= MAC_RGMII_MODE_RX_INT_B
|
972 MAC_RGMII_MODE_RX_QUALITY
|
973 MAC_RGMII_MODE_RX_ACTIVITY
|
974 MAC_RGMII_MODE_RX_ENG_DET
;
975 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
976 val
|= MAC_RGMII_MODE_TX_ENABLE
|
977 MAC_RGMII_MODE_TX_LOWPWR
|
978 MAC_RGMII_MODE_TX_RESET
;
980 tw32(MAC_EXT_RGMII_MODE
, val
);
983 static void tg3_mdio_start(struct tg3
*tp
)
985 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
986 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
987 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
988 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
991 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
992 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
995 if ((tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) &&
996 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
997 tg3_mdio_config_5785(tp
);
1000 static void tg3_mdio_stop(struct tg3
*tp
)
1002 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1003 mutex_lock(&tp
->mdio_bus
->mdio_lock
);
1004 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_PAUSED
;
1005 mutex_unlock(&tp
->mdio_bus
->mdio_lock
);
1009 static int tg3_mdio_init(struct tg3
*tp
)
1013 struct phy_device
*phydev
;
1017 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) ||
1018 (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
))
1021 tp
->mdio_bus
= mdiobus_alloc();
1022 if (tp
->mdio_bus
== NULL
)
1025 tp
->mdio_bus
->name
= "tg3 mdio bus";
1026 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1027 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1028 tp
->mdio_bus
->priv
= tp
;
1029 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1030 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1031 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1032 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1033 tp
->mdio_bus
->phy_mask
= ~(1 << PHY_ADDR
);
1034 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1036 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1037 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1039 /* The bus registration will look for all the PHYs on the mdio bus.
1040 * Unfortunately, it does not ensure the PHY is powered up before
1041 * accessing the PHY ID registers. A chip reset is the
1042 * quickest way to bring the device back to an operational state..
1044 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1047 i
= mdiobus_register(tp
->mdio_bus
);
1049 printk(KERN_WARNING
"%s: mdiobus_reg failed (0x%x)\n",
1051 mdiobus_free(tp
->mdio_bus
);
1055 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1057 if (!phydev
|| !phydev
->drv
) {
1058 printk(KERN_WARNING
"%s: No PHY devices\n", tp
->dev
->name
);
1059 mdiobus_unregister(tp
->mdio_bus
);
1060 mdiobus_free(tp
->mdio_bus
);
1064 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1065 case TG3_PHY_ID_BCM57780
:
1066 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1068 case TG3_PHY_ID_BCM50610
:
1069 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_STD_IBND_DISABLE
)
1070 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1071 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_RX_EN
)
1072 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1073 if (tp
->tg3_flags3
& TG3_FLG3_RGMII_EXT_IBND_TX_EN
)
1074 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1076 case TG3_PHY_ID_RTL8211C
:
1077 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1079 case TG3_PHY_ID_RTL8201E
:
1080 case TG3_PHY_ID_BCMAC131
:
1081 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1082 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
1086 tp
->tg3_flags3
|= TG3_FLG3_MDIOBUS_INITED
;
1088 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
1089 tg3_mdio_config_5785(tp
);
1094 static void tg3_mdio_fini(struct tg3
*tp
)
1096 if (tp
->tg3_flags3
& TG3_FLG3_MDIOBUS_INITED
) {
1097 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_INITED
;
1098 mdiobus_unregister(tp
->mdio_bus
);
1099 mdiobus_free(tp
->mdio_bus
);
1100 tp
->tg3_flags3
&= ~TG3_FLG3_MDIOBUS_PAUSED
;
1104 /* tp->lock is held. */
1105 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1109 val
= tr32(GRC_RX_CPU_EVENT
);
1110 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1111 tw32_f(GRC_RX_CPU_EVENT
, val
);
1113 tp
->last_event_jiffies
= jiffies
;
1116 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1118 /* tp->lock is held. */
1119 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1122 unsigned int delay_cnt
;
1125 /* If enough time has passed, no wait is necessary. */
1126 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1127 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1129 if (time_remain
< 0)
1132 /* Check if we can shorten the wait time. */
1133 delay_cnt
= jiffies_to_usecs(time_remain
);
1134 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1135 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1136 delay_cnt
= (delay_cnt
>> 3) + 1;
1138 for (i
= 0; i
< delay_cnt
; i
++) {
1139 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1145 /* tp->lock is held. */
1146 static void tg3_ump_link_report(struct tg3
*tp
)
1151 if (!(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
1152 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
1155 tg3_wait_for_event_ack(tp
);
1157 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1159 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1162 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1164 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1165 val
|= (reg
& 0xffff);
1166 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, val
);
1169 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1171 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1172 val
|= (reg
& 0xffff);
1173 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 4, val
);
1176 if (!(tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)) {
1177 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1179 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1180 val
|= (reg
& 0xffff);
1182 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 8, val
);
1184 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1188 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 12, val
);
1190 tg3_generate_fw_event(tp
);
1193 static void tg3_link_report(struct tg3
*tp
)
1195 if (!netif_carrier_ok(tp
->dev
)) {
1196 if (netif_msg_link(tp
))
1197 printk(KERN_INFO PFX
"%s: Link is down.\n",
1199 tg3_ump_link_report(tp
);
1200 } else if (netif_msg_link(tp
)) {
1201 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
1203 (tp
->link_config
.active_speed
== SPEED_1000
?
1205 (tp
->link_config
.active_speed
== SPEED_100
?
1207 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1210 printk(KERN_INFO PFX
1211 "%s: Flow control is %s for TX and %s for RX.\n",
1213 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1215 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1217 tg3_ump_link_report(tp
);
1221 static u16
tg3_advert_flowctrl_1000T(u8 flow_ctrl
)
1225 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1226 miireg
= ADVERTISE_PAUSE_CAP
;
1227 else if (flow_ctrl
& FLOW_CTRL_TX
)
1228 miireg
= ADVERTISE_PAUSE_ASYM
;
1229 else if (flow_ctrl
& FLOW_CTRL_RX
)
1230 miireg
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1237 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1241 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1242 miireg
= ADVERTISE_1000XPAUSE
;
1243 else if (flow_ctrl
& FLOW_CTRL_TX
)
1244 miireg
= ADVERTISE_1000XPSE_ASYM
;
1245 else if (flow_ctrl
& FLOW_CTRL_RX
)
1246 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1253 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1257 if (lcladv
& ADVERTISE_1000XPAUSE
) {
1258 if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1259 if (rmtadv
& LPA_1000XPAUSE
)
1260 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1261 else if (rmtadv
& LPA_1000XPAUSE_ASYM
)
1264 if (rmtadv
& LPA_1000XPAUSE
)
1265 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1267 } else if (lcladv
& ADVERTISE_1000XPSE_ASYM
) {
1268 if ((rmtadv
& LPA_1000XPAUSE
) && (rmtadv
& LPA_1000XPAUSE_ASYM
))
1275 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1279 u32 old_rx_mode
= tp
->rx_mode
;
1280 u32 old_tx_mode
= tp
->tx_mode
;
1282 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
1283 autoneg
= tp
->mdio_bus
->phy_map
[PHY_ADDR
]->autoneg
;
1285 autoneg
= tp
->link_config
.autoneg
;
1287 if (autoneg
== AUTONEG_ENABLE
&&
1288 (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)) {
1289 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
1290 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1292 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1294 flowctrl
= tp
->link_config
.flowctrl
;
1296 tp
->link_config
.active_flowctrl
= flowctrl
;
1298 if (flowctrl
& FLOW_CTRL_RX
)
1299 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1301 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1303 if (old_rx_mode
!= tp
->rx_mode
)
1304 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1306 if (flowctrl
& FLOW_CTRL_TX
)
1307 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1309 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1311 if (old_tx_mode
!= tp
->tx_mode
)
1312 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1315 static void tg3_adjust_link(struct net_device
*dev
)
1317 u8 oldflowctrl
, linkmesg
= 0;
1318 u32 mac_mode
, lcl_adv
, rmt_adv
;
1319 struct tg3
*tp
= netdev_priv(dev
);
1320 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1322 spin_lock(&tp
->lock
);
1324 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1325 MAC_MODE_HALF_DUPLEX
);
1327 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1333 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1334 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1336 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1338 if (phydev
->duplex
== DUPLEX_HALF
)
1339 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
1341 lcl_adv
= tg3_advert_flowctrl_1000T(
1342 tp
->link_config
.flowctrl
);
1345 rmt_adv
= LPA_PAUSE_CAP
;
1346 if (phydev
->asym_pause
)
1347 rmt_adv
|= LPA_PAUSE_ASYM
;
1350 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
1352 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
1354 if (mac_mode
!= tp
->mac_mode
) {
1355 tp
->mac_mode
= mac_mode
;
1356 tw32_f(MAC_MODE
, tp
->mac_mode
);
1360 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
1361 if (phydev
->speed
== SPEED_10
)
1363 MAC_MI_STAT_10MBPS_MODE
|
1364 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1366 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
1369 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
1370 tw32(MAC_TX_LENGTHS
,
1371 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1372 (6 << TX_LENGTHS_IPG_SHIFT
) |
1373 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1375 tw32(MAC_TX_LENGTHS
,
1376 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
1377 (6 << TX_LENGTHS_IPG_SHIFT
) |
1378 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
1380 if ((phydev
->link
&& tp
->link_config
.active_speed
== SPEED_INVALID
) ||
1381 (!phydev
->link
&& tp
->link_config
.active_speed
!= SPEED_INVALID
) ||
1382 phydev
->speed
!= tp
->link_config
.active_speed
||
1383 phydev
->duplex
!= tp
->link_config
.active_duplex
||
1384 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
1387 tp
->link_config
.active_speed
= phydev
->speed
;
1388 tp
->link_config
.active_duplex
= phydev
->duplex
;
1390 spin_unlock(&tp
->lock
);
1393 tg3_link_report(tp
);
1396 static int tg3_phy_init(struct tg3
*tp
)
1398 struct phy_device
*phydev
;
1400 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
1403 /* Bring the PHY back to a known state. */
1406 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1408 /* Attach the MAC to the PHY. */
1409 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
), tg3_adjust_link
,
1410 phydev
->dev_flags
, phydev
->interface
);
1411 if (IS_ERR(phydev
)) {
1412 printk(KERN_ERR
"%s: Could not attach to PHY\n", tp
->dev
->name
);
1413 return PTR_ERR(phydev
);
1416 /* Mask with MAC supported features. */
1417 switch (phydev
->interface
) {
1418 case PHY_INTERFACE_MODE_GMII
:
1419 case PHY_INTERFACE_MODE_RGMII
:
1420 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
1421 phydev
->supported
&= (PHY_GBIT_FEATURES
|
1423 SUPPORTED_Asym_Pause
);
1427 case PHY_INTERFACE_MODE_MII
:
1428 phydev
->supported
&= (PHY_BASIC_FEATURES
|
1430 SUPPORTED_Asym_Pause
);
1433 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1437 tp
->tg3_flags3
|= TG3_FLG3_PHY_CONNECTED
;
1439 phydev
->advertising
= phydev
->supported
;
1444 static void tg3_phy_start(struct tg3
*tp
)
1446 struct phy_device
*phydev
;
1448 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1451 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
1453 if (tp
->link_config
.phy_is_low_power
) {
1454 tp
->link_config
.phy_is_low_power
= 0;
1455 phydev
->speed
= tp
->link_config
.orig_speed
;
1456 phydev
->duplex
= tp
->link_config
.orig_duplex
;
1457 phydev
->autoneg
= tp
->link_config
.orig_autoneg
;
1458 phydev
->advertising
= tp
->link_config
.orig_advertising
;
1463 phy_start_aneg(phydev
);
1466 static void tg3_phy_stop(struct tg3
*tp
)
1468 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
1471 phy_stop(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1474 static void tg3_phy_fini(struct tg3
*tp
)
1476 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
1477 phy_disconnect(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
1478 tp
->tg3_flags3
&= ~TG3_FLG3_PHY_CONNECTED
;
1482 static void tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1484 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1485 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1488 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
1492 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
1495 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1496 phytest
| MII_TG3_FET_SHADOW_EN
);
1497 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
1499 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1501 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
1502 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
1504 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
1508 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
1512 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
1515 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1516 tg3_phy_fet_toggle_apd(tp
, enable
);
1520 reg
= MII_TG3_MISC_SHDW_WREN
|
1521 MII_TG3_MISC_SHDW_SCR5_SEL
|
1522 MII_TG3_MISC_SHDW_SCR5_LPED
|
1523 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
1524 MII_TG3_MISC_SHDW_SCR5_SDTL
|
1525 MII_TG3_MISC_SHDW_SCR5_C125OE
;
1526 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
|| !enable
)
1527 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
1529 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1532 reg
= MII_TG3_MISC_SHDW_WREN
|
1533 MII_TG3_MISC_SHDW_APD_SEL
|
1534 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
1536 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
1538 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
1541 static void tg3_phy_toggle_automdix(struct tg3
*tp
, int enable
)
1545 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
1546 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
1549 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
1552 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
1553 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
1555 tg3_writephy(tp
, MII_TG3_FET_TEST
,
1556 ephy
| MII_TG3_FET_SHADOW_EN
);
1557 if (!tg3_readphy(tp
, reg
, &phy
)) {
1559 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1561 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
1562 tg3_writephy(tp
, reg
, phy
);
1564 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
1567 phy
= MII_TG3_AUXCTL_MISC_RDSEL_MISC
|
1568 MII_TG3_AUXCTL_SHDWSEL_MISC
;
1569 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
) &&
1570 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy
)) {
1572 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1574 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
1575 phy
|= MII_TG3_AUXCTL_MISC_WREN
;
1576 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1581 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
1585 if (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
)
1588 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x7007) &&
1589 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
))
1590 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1591 (val
| (1 << 15) | (1 << 4)));
1594 static void tg3_phy_apply_otp(struct tg3
*tp
)
1603 /* Enable SM_DSP clock and tx 6dB coding. */
1604 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1605 MII_TG3_AUXCTL_ACTL_SMDSP_ENA
|
1606 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1607 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1609 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
1610 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
1611 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
1613 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
1614 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
1615 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
1617 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
1618 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
1619 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
1621 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
1622 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
1624 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
1625 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
1627 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
1628 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
1629 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
1631 /* Turn off SM_DSP clock. */
1632 phy
= MII_TG3_AUXCTL_SHDWSEL_AUXCTL
|
1633 MII_TG3_AUXCTL_ACTL_TX_6DB
;
1634 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy
);
1637 static int tg3_wait_macro_done(struct tg3
*tp
)
1644 if (!tg3_readphy(tp
, 0x16, &tmp32
)) {
1645 if ((tmp32
& 0x1000) == 0)
1655 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
1657 static const u32 test_pat
[4][6] = {
1658 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1659 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1660 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1661 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1665 for (chan
= 0; chan
< 4; chan
++) {
1668 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1669 (chan
* 0x2000) | 0x0200);
1670 tg3_writephy(tp
, 0x16, 0x0002);
1672 for (i
= 0; i
< 6; i
++)
1673 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
1676 tg3_writephy(tp
, 0x16, 0x0202);
1677 if (tg3_wait_macro_done(tp
)) {
1682 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1683 (chan
* 0x2000) | 0x0200);
1684 tg3_writephy(tp
, 0x16, 0x0082);
1685 if (tg3_wait_macro_done(tp
)) {
1690 tg3_writephy(tp
, 0x16, 0x0802);
1691 if (tg3_wait_macro_done(tp
)) {
1696 for (i
= 0; i
< 6; i
+= 2) {
1699 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
1700 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
1701 tg3_wait_macro_done(tp
)) {
1707 if (low
!= test_pat
[chan
][i
] ||
1708 high
!= test_pat
[chan
][i
+1]) {
1709 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
1710 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
1711 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
1721 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
1725 for (chan
= 0; chan
< 4; chan
++) {
1728 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
1729 (chan
* 0x2000) | 0x0200);
1730 tg3_writephy(tp
, 0x16, 0x0002);
1731 for (i
= 0; i
< 6; i
++)
1732 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
1733 tg3_writephy(tp
, 0x16, 0x0202);
1734 if (tg3_wait_macro_done(tp
))
1741 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
1743 u32 reg32
, phy9_orig
;
1744 int retries
, do_phy_reset
, err
;
1750 err
= tg3_bmcr_reset(tp
);
1756 /* Disable transmitter and interrupt. */
1757 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
1761 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1763 /* Set full-duplex, 1000 mbps. */
1764 tg3_writephy(tp
, MII_BMCR
,
1765 BMCR_FULLDPLX
| TG3_BMCR_SPEED1000
);
1767 /* Set to master mode. */
1768 if (tg3_readphy(tp
, MII_TG3_CTRL
, &phy9_orig
))
1771 tg3_writephy(tp
, MII_TG3_CTRL
,
1772 (MII_TG3_CTRL_AS_MASTER
|
1773 MII_TG3_CTRL_ENABLE_AS_MASTER
));
1775 /* Enable SM_DSP_CLOCK and 6dB. */
1776 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1778 /* Block the PHY control access. */
1779 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1780 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0800);
1782 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
1785 } while (--retries
);
1787 err
= tg3_phy_reset_chanpat(tp
);
1791 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8005);
1792 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0000);
1794 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
1795 tg3_writephy(tp
, 0x16, 0x0000);
1797 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1798 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
1799 /* Set Extended packet length bit for jumbo frames */
1800 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4400);
1803 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1806 tg3_writephy(tp
, MII_TG3_CTRL
, phy9_orig
);
1808 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
1810 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
1817 /* This will reset the tigon3 PHY if there is no valid
1818 * link unless the FORCE argument is non-zero.
1820 static int tg3_phy_reset(struct tg3
*tp
)
1826 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1829 val
= tr32(GRC_MISC_CFG
);
1830 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
1833 err
= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1834 err
|= tg3_readphy(tp
, MII_BMSR
, &phy_status
);
1838 if (netif_running(tp
->dev
) && netif_carrier_ok(tp
->dev
)) {
1839 netif_carrier_off(tp
->dev
);
1840 tg3_link_report(tp
);
1843 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
1844 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
1845 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
1846 err
= tg3_phy_reset_5703_4_5(tp
);
1853 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
1854 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
1855 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
1856 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
1858 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
1861 err
= tg3_bmcr_reset(tp
);
1865 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
1868 phy
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
1869 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, phy
);
1871 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
1874 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
1875 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
1878 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
1879 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
1880 CPMU_LSPD_1000MB_MACCLK_12_5
) {
1881 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
1883 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
1887 tg3_phy_apply_otp(tp
);
1889 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
1890 tg3_phy_toggle_apd(tp
, true);
1892 tg3_phy_toggle_apd(tp
, false);
1895 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADC_BUG
) {
1896 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1897 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1898 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x2aaa);
1899 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1900 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0323);
1901 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1903 if (tp
->tg3_flags2
& TG3_FLG2_PHY_5704_A0_BUG
) {
1904 tg3_writephy(tp
, 0x1c, 0x8d68);
1905 tg3_writephy(tp
, 0x1c, 0x8d68);
1907 if (tp
->tg3_flags2
& TG3_FLG2_PHY_BER_BUG
) {
1908 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1909 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1910 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x310b);
1911 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
1912 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x9506);
1913 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x401f);
1914 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x14e2);
1915 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1917 else if (tp
->tg3_flags2
& TG3_FLG2_PHY_JITTER_BUG
) {
1918 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0c00);
1919 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
1920 if (tp
->tg3_flags2
& TG3_FLG2_PHY_ADJUST_TRIM
) {
1921 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
1922 tg3_writephy(tp
, MII_TG3_TEST1
,
1923 MII_TG3_TEST1_TRIM_EN
| 0x4);
1925 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
1926 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0400);
1928 /* Set Extended packet length bit (bit 14) on all chips that */
1929 /* support jumbo frames */
1930 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
1931 /* Cannot do read-modify-write on 5401 */
1932 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
1933 } else if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1936 /* Set bit 14 with read-modify-write to preserve other bits */
1937 if (!tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x0007) &&
1938 !tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &phy_reg
))
1939 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, phy_reg
| 0x4000);
1942 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1943 * jumbo frames transmission.
1945 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
1948 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &phy_reg
))
1949 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
1950 phy_reg
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
1953 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
1954 /* adjust output voltage */
1955 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
1958 tg3_phy_toggle_automdix(tp
, 1);
1959 tg3_phy_set_wirespeed(tp
);
1963 static void tg3_frob_aux_power(struct tg3
*tp
)
1965 struct tg3
*tp_peer
= tp
;
1967 if ((tp
->tg3_flags2
& TG3_FLG2_IS_NIC
) == 0)
1970 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
1971 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
1972 struct net_device
*dev_peer
;
1974 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
1975 /* remove_one() may have been run on the peer. */
1979 tp_peer
= netdev_priv(dev_peer
);
1982 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1983 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0 ||
1984 (tp_peer
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) != 0 ||
1985 (tp_peer
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
1986 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
1987 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
1988 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
1989 (GRC_LCLCTRL_GPIO_OE0
|
1990 GRC_LCLCTRL_GPIO_OE1
|
1991 GRC_LCLCTRL_GPIO_OE2
|
1992 GRC_LCLCTRL_GPIO_OUTPUT0
|
1993 GRC_LCLCTRL_GPIO_OUTPUT1
),
1995 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
1996 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
1997 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1998 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
1999 GRC_LCLCTRL_GPIO_OE1
|
2000 GRC_LCLCTRL_GPIO_OE2
|
2001 GRC_LCLCTRL_GPIO_OUTPUT0
|
2002 GRC_LCLCTRL_GPIO_OUTPUT1
|
2004 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2006 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2007 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2009 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2010 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
, 100);
2013 u32 grc_local_ctrl
= 0;
2015 if (tp_peer
!= tp
&&
2016 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2019 /* Workaround to prevent overdrawing Amps. */
2020 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2022 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2023 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2024 grc_local_ctrl
, 100);
2027 /* On 5753 and variants, GPIO2 cannot be used. */
2028 no_gpio2
= tp
->nic_sram_data_cfg
&
2029 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2031 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2032 GRC_LCLCTRL_GPIO_OE1
|
2033 GRC_LCLCTRL_GPIO_OE2
|
2034 GRC_LCLCTRL_GPIO_OUTPUT1
|
2035 GRC_LCLCTRL_GPIO_OUTPUT2
;
2037 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2038 GRC_LCLCTRL_GPIO_OUTPUT2
);
2040 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2041 grc_local_ctrl
, 100);
2043 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2045 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2046 grc_local_ctrl
, 100);
2049 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2050 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2051 grc_local_ctrl
, 100);
2055 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
2056 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
2057 if (tp_peer
!= tp
&&
2058 (tp_peer
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) != 0)
2061 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2062 (GRC_LCLCTRL_GPIO_OE1
|
2063 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2065 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2066 GRC_LCLCTRL_GPIO_OE1
, 100);
2068 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2069 (GRC_LCLCTRL_GPIO_OE1
|
2070 GRC_LCLCTRL_GPIO_OUTPUT1
), 100);
2075 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2077 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2079 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
) {
2080 if (speed
!= SPEED_10
)
2082 } else if (speed
== SPEED_10
)
2088 static int tg3_setup_phy(struct tg3
*, int);
2090 #define RESET_KIND_SHUTDOWN 0
2091 #define RESET_KIND_INIT 1
2092 #define RESET_KIND_SUSPEND 2
2094 static void tg3_write_sig_post_reset(struct tg3
*, int);
2095 static int tg3_halt_cpu(struct tg3
*, u32
);
2097 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
2101 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
2102 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2103 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
2104 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
2107 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
2108 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
2109 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
2114 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2116 val
= tr32(GRC_MISC_CFG
);
2117 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
2120 } else if (do_low_power
) {
2121 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2122 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
2124 tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
2125 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
|
2126 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
2127 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
2128 MII_TG3_AUXCTL_PCTL_VREG_11V
);
2131 /* The PHY should not be powered down on some chips because
2134 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2135 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2136 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
&&
2137 (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)))
2140 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
||
2141 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5761_AX
) {
2142 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2143 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2144 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
2145 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2148 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
2151 /* tp->lock is held. */
2152 static int tg3_nvram_lock(struct tg3
*tp
)
2154 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2157 if (tp
->nvram_lock_cnt
== 0) {
2158 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
2159 for (i
= 0; i
< 8000; i
++) {
2160 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
2165 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2169 tp
->nvram_lock_cnt
++;
2174 /* tp->lock is held. */
2175 static void tg3_nvram_unlock(struct tg3
*tp
)
2177 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
) {
2178 if (tp
->nvram_lock_cnt
> 0)
2179 tp
->nvram_lock_cnt
--;
2180 if (tp
->nvram_lock_cnt
== 0)
2181 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
2185 /* tp->lock is held. */
2186 static void tg3_enable_nvram_access(struct tg3
*tp
)
2188 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2189 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2190 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2192 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
2196 /* tp->lock is held. */
2197 static void tg3_disable_nvram_access(struct tg3
*tp
)
2199 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2200 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
)) {
2201 u32 nvaccess
= tr32(NVRAM_ACCESS
);
2203 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
2207 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
2208 u32 offset
, u32
*val
)
2213 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
2216 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
2217 EEPROM_ADDR_DEVID_MASK
|
2219 tw32(GRC_EEPROM_ADDR
,
2221 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
2222 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
2223 EEPROM_ADDR_ADDR_MASK
) |
2224 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
2226 for (i
= 0; i
< 1000; i
++) {
2227 tmp
= tr32(GRC_EEPROM_ADDR
);
2229 if (tmp
& EEPROM_ADDR_COMPLETE
)
2233 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
2236 tmp
= tr32(GRC_EEPROM_DATA
);
2239 * The data will always be opposite the native endian
2240 * format. Perform a blind byteswap to compensate.
2247 #define NVRAM_CMD_TIMEOUT 10000
2249 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
2253 tw32(NVRAM_CMD
, nvram_cmd
);
2254 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
2256 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
2262 if (i
== NVRAM_CMD_TIMEOUT
)
2268 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
2270 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2271 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2272 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2273 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2274 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2276 addr
= ((addr
/ tp
->nvram_pagesize
) <<
2277 ATMEL_AT45DB0X1B_PAGE_POS
) +
2278 (addr
% tp
->nvram_pagesize
);
2283 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
2285 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM
) &&
2286 (tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) &&
2287 (tp
->tg3_flags2
& TG3_FLG2_FLASH
) &&
2288 !(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM_ADDR_TRANS
) &&
2289 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
2291 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
2292 tp
->nvram_pagesize
) +
2293 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
2298 /* NOTE: Data read in from NVRAM is byteswapped according to
2299 * the byteswapping settings for all other register accesses.
2300 * tg3 devices are BE devices, so on a BE machine, the data
2301 * returned will be exactly as it is seen in NVRAM. On a LE
2302 * machine, the 32-bit value will be byteswapped.
2304 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
2308 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
))
2309 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
2311 offset
= tg3_nvram_phys_addr(tp
, offset
);
2313 if (offset
> NVRAM_ADDR_MSK
)
2316 ret
= tg3_nvram_lock(tp
);
2320 tg3_enable_nvram_access(tp
);
2322 tw32(NVRAM_ADDR
, offset
);
2323 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
2324 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
2327 *val
= tr32(NVRAM_RDDATA
);
2329 tg3_disable_nvram_access(tp
);
2331 tg3_nvram_unlock(tp
);
2336 /* Ensures NVRAM data is in bytestream format. */
2337 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
2340 int res
= tg3_nvram_read(tp
, offset
, &v
);
2342 *val
= cpu_to_be32(v
);
2346 /* tp->lock is held. */
2347 static void __tg3_set_mac_addr(struct tg3
*tp
, int skip_mac_1
)
2349 u32 addr_high
, addr_low
;
2352 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
2353 tp
->dev
->dev_addr
[1]);
2354 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
2355 (tp
->dev
->dev_addr
[3] << 16) |
2356 (tp
->dev
->dev_addr
[4] << 8) |
2357 (tp
->dev
->dev_addr
[5] << 0));
2358 for (i
= 0; i
< 4; i
++) {
2359 if (i
== 1 && skip_mac_1
)
2361 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
2362 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
2365 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2366 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
2367 for (i
= 0; i
< 12; i
++) {
2368 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
2369 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
2373 addr_high
= (tp
->dev
->dev_addr
[0] +
2374 tp
->dev
->dev_addr
[1] +
2375 tp
->dev
->dev_addr
[2] +
2376 tp
->dev
->dev_addr
[3] +
2377 tp
->dev
->dev_addr
[4] +
2378 tp
->dev
->dev_addr
[5]) &
2379 TX_BACKOFF_SEED_MASK
;
2380 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
2383 static int tg3_set_power_state(struct tg3
*tp
, pci_power_t state
)
2386 bool device_should_wake
, do_low_power
;
2388 /* Make sure register accesses (indirect or otherwise)
2389 * will function correctly.
2391 pci_write_config_dword(tp
->pdev
,
2392 TG3PCI_MISC_HOST_CTRL
,
2393 tp
->misc_host_ctrl
);
2397 pci_enable_wake(tp
->pdev
, state
, false);
2398 pci_set_power_state(tp
->pdev
, PCI_D0
);
2400 /* Switch out of Vaux if it is a NIC */
2401 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
2402 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
, 100);
2412 printk(KERN_ERR PFX
"%s: Invalid power state (D%d) requested\n",
2413 tp
->dev
->name
, state
);
2417 /* Restore the CLKREQ setting. */
2418 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
2421 pci_read_config_word(tp
->pdev
,
2422 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2424 lnkctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
2425 pci_write_config_word(tp
->pdev
,
2426 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
2430 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
2431 tw32(TG3PCI_MISC_HOST_CTRL
,
2432 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
2434 device_should_wake
= pci_pme_capable(tp
->pdev
, state
) &&
2435 device_may_wakeup(&tp
->pdev
->dev
) &&
2436 (tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
2438 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
2439 do_low_power
= false;
2440 if ((tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) &&
2441 !tp
->link_config
.phy_is_low_power
) {
2442 struct phy_device
*phydev
;
2443 u32 phyid
, advertising
;
2445 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
2447 tp
->link_config
.phy_is_low_power
= 1;
2449 tp
->link_config
.orig_speed
= phydev
->speed
;
2450 tp
->link_config
.orig_duplex
= phydev
->duplex
;
2451 tp
->link_config
.orig_autoneg
= phydev
->autoneg
;
2452 tp
->link_config
.orig_advertising
= phydev
->advertising
;
2454 advertising
= ADVERTISED_TP
|
2456 ADVERTISED_Autoneg
|
2457 ADVERTISED_10baseT_Half
;
2459 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2460 device_should_wake
) {
2461 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2463 ADVERTISED_100baseT_Half
|
2464 ADVERTISED_100baseT_Full
|
2465 ADVERTISED_10baseT_Full
;
2467 advertising
|= ADVERTISED_10baseT_Full
;
2470 phydev
->advertising
= advertising
;
2472 phy_start_aneg(phydev
);
2474 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
2475 if (phyid
!= TG3_PHY_ID_BCMAC131
) {
2476 phyid
&= TG3_PHY_OUI_MASK
;
2477 if (phyid
== TG3_PHY_OUI_1
||
2478 phyid
== TG3_PHY_OUI_2
||
2479 phyid
== TG3_PHY_OUI_3
)
2480 do_low_power
= true;
2484 do_low_power
= true;
2486 if (tp
->link_config
.phy_is_low_power
== 0) {
2487 tp
->link_config
.phy_is_low_power
= 1;
2488 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
2489 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
2490 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
2493 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
2494 tp
->link_config
.speed
= SPEED_10
;
2495 tp
->link_config
.duplex
= DUPLEX_HALF
;
2496 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
2497 tg3_setup_phy(tp
, 0);
2501 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
2504 val
= tr32(GRC_VCPU_EXT_CTRL
);
2505 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
2506 } else if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2510 for (i
= 0; i
< 200; i
++) {
2511 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
2512 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
2517 if (tp
->tg3_flags
& TG3_FLAG_WOL_CAP
)
2518 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
2519 WOL_DRV_STATE_SHUTDOWN
|
2523 if (device_should_wake
) {
2526 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
2528 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x5a);
2532 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
2533 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
2535 mac_mode
= MAC_MODE_PORT_MODE_MII
;
2537 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
2538 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
2540 u32 speed
= (tp
->tg3_flags
&
2541 TG3_FLAG_WOL_SPEED_100MB
) ?
2542 SPEED_100
: SPEED_10
;
2543 if (tg3_5700_link_polarity(tp
, speed
))
2544 mac_mode
|= MAC_MODE_LINK_POLARITY
;
2546 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
2549 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
2552 if (!(tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
2553 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
2555 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
2556 if (((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
2557 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) &&
2558 ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
2559 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)))
2560 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
2562 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
2563 mac_mode
|= tp
->mac_mode
&
2564 (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
2565 if (mac_mode
& MAC_MODE_APE_TX_EN
)
2566 mac_mode
|= MAC_MODE_TDE_ENABLE
;
2569 tw32_f(MAC_MODE
, mac_mode
);
2572 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
2576 if (!(tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
) &&
2577 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2578 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
2581 base_val
= tp
->pci_clock_ctrl
;
2582 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
2583 CLOCK_CTRL_TXCLK_DISABLE
);
2585 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
2586 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
2587 } else if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) ||
2588 (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
2589 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)) {
2591 } else if (!((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
2592 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))) {
2593 u32 newbits1
, newbits2
;
2595 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2596 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2597 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
2598 CLOCK_CTRL_TXCLK_DISABLE
|
2600 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2601 } else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
2602 newbits1
= CLOCK_CTRL_625_CORE
;
2603 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
2605 newbits1
= CLOCK_CTRL_ALTCLK
;
2606 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
2609 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
2612 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
2615 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
2618 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
2619 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
2620 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
2621 CLOCK_CTRL_TXCLK_DISABLE
|
2622 CLOCK_CTRL_44MHZ_CORE
);
2624 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
2627 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
2628 tp
->pci_clock_ctrl
| newbits3
, 40);
2632 if (!(device_should_wake
) &&
2633 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
2634 tg3_power_down_phy(tp
, do_low_power
);
2636 tg3_frob_aux_power(tp
);
2638 /* Workaround for unstable PLL clock */
2639 if ((GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
) ||
2640 (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
)) {
2641 u32 val
= tr32(0x7d00);
2643 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2645 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
2648 err
= tg3_nvram_lock(tp
);
2649 tg3_halt_cpu(tp
, RX_CPU_BASE
);
2651 tg3_nvram_unlock(tp
);
2655 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
2657 if (device_should_wake
)
2658 pci_enable_wake(tp
->pdev
, state
, true);
2660 /* Finally, set the new power state. */
2661 pci_set_power_state(tp
->pdev
, state
);
2666 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
2668 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
2669 case MII_TG3_AUX_STAT_10HALF
:
2671 *duplex
= DUPLEX_HALF
;
2674 case MII_TG3_AUX_STAT_10FULL
:
2676 *duplex
= DUPLEX_FULL
;
2679 case MII_TG3_AUX_STAT_100HALF
:
2681 *duplex
= DUPLEX_HALF
;
2684 case MII_TG3_AUX_STAT_100FULL
:
2686 *duplex
= DUPLEX_FULL
;
2689 case MII_TG3_AUX_STAT_1000HALF
:
2690 *speed
= SPEED_1000
;
2691 *duplex
= DUPLEX_HALF
;
2694 case MII_TG3_AUX_STAT_1000FULL
:
2695 *speed
= SPEED_1000
;
2696 *duplex
= DUPLEX_FULL
;
2700 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
2701 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
2703 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
2707 *speed
= SPEED_INVALID
;
2708 *duplex
= DUPLEX_INVALID
;
2713 static void tg3_phy_copper_begin(struct tg3
*tp
)
2718 if (tp
->link_config
.phy_is_low_power
) {
2719 /* Entering low power mode. Disable gigabit and
2720 * 100baseT advertisements.
2722 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2724 new_adv
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
2725 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
2726 if (tp
->tg3_flags
& TG3_FLAG_WOL_SPEED_100MB
)
2727 new_adv
|= (ADVERTISE_100HALF
| ADVERTISE_100FULL
);
2729 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2730 } else if (tp
->link_config
.speed
== SPEED_INVALID
) {
2731 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
2732 tp
->link_config
.advertising
&=
2733 ~(ADVERTISED_1000baseT_Half
|
2734 ADVERTISED_1000baseT_Full
);
2736 new_adv
= ADVERTISE_CSMA
;
2737 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Half
)
2738 new_adv
|= ADVERTISE_10HALF
;
2739 if (tp
->link_config
.advertising
& ADVERTISED_10baseT_Full
)
2740 new_adv
|= ADVERTISE_10FULL
;
2741 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Half
)
2742 new_adv
|= ADVERTISE_100HALF
;
2743 if (tp
->link_config
.advertising
& ADVERTISED_100baseT_Full
)
2744 new_adv
|= ADVERTISE_100FULL
;
2746 new_adv
|= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2748 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2750 if (tp
->link_config
.advertising
&
2751 (ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
)) {
2753 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
2754 new_adv
|= MII_TG3_CTRL_ADV_1000_HALF
;
2755 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
2756 new_adv
|= MII_TG3_CTRL_ADV_1000_FULL
;
2757 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) &&
2758 (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2759 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
))
2760 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2761 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2762 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2764 tg3_writephy(tp
, MII_TG3_CTRL
, 0);
2767 new_adv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2768 new_adv
|= ADVERTISE_CSMA
;
2770 /* Asking for a specific link mode. */
2771 if (tp
->link_config
.speed
== SPEED_1000
) {
2772 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2774 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2775 new_adv
= MII_TG3_CTRL_ADV_1000_FULL
;
2777 new_adv
= MII_TG3_CTRL_ADV_1000_HALF
;
2778 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
2779 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
2780 new_adv
|= (MII_TG3_CTRL_AS_MASTER
|
2781 MII_TG3_CTRL_ENABLE_AS_MASTER
);
2783 if (tp
->link_config
.speed
== SPEED_100
) {
2784 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2785 new_adv
|= ADVERTISE_100FULL
;
2787 new_adv
|= ADVERTISE_100HALF
;
2789 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2790 new_adv
|= ADVERTISE_10FULL
;
2792 new_adv
|= ADVERTISE_10HALF
;
2794 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
2799 tg3_writephy(tp
, MII_TG3_CTRL
, new_adv
);
2802 if (tp
->link_config
.autoneg
== AUTONEG_DISABLE
&&
2803 tp
->link_config
.speed
!= SPEED_INVALID
) {
2804 u32 bmcr
, orig_bmcr
;
2806 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
2807 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
2810 switch (tp
->link_config
.speed
) {
2816 bmcr
|= BMCR_SPEED100
;
2820 bmcr
|= TG3_BMCR_SPEED1000
;
2824 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
2825 bmcr
|= BMCR_FULLDPLX
;
2827 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
2828 (bmcr
!= orig_bmcr
)) {
2829 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
2830 for (i
= 0; i
< 1500; i
++) {
2834 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
2835 tg3_readphy(tp
, MII_BMSR
, &tmp
))
2837 if (!(tmp
& BMSR_LSTATUS
)) {
2842 tg3_writephy(tp
, MII_BMCR
, bmcr
);
2846 tg3_writephy(tp
, MII_BMCR
,
2847 BMCR_ANENABLE
| BMCR_ANRESTART
);
2851 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
2855 /* Turn off tap power management. */
2856 /* Set Extended packet length bit */
2857 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4c20);
2859 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0012);
2860 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1804);
2862 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x0013);
2863 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x1204);
2865 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2866 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0132);
2868 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8006);
2869 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0232);
2871 err
|= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x201f);
2872 err
|= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x0a20);
2879 static int tg3_copper_is_advertising_all(struct tg3
*tp
, u32 mask
)
2881 u32 adv_reg
, all_mask
= 0;
2883 if (mask
& ADVERTISED_10baseT_Half
)
2884 all_mask
|= ADVERTISE_10HALF
;
2885 if (mask
& ADVERTISED_10baseT_Full
)
2886 all_mask
|= ADVERTISE_10FULL
;
2887 if (mask
& ADVERTISED_100baseT_Half
)
2888 all_mask
|= ADVERTISE_100HALF
;
2889 if (mask
& ADVERTISED_100baseT_Full
)
2890 all_mask
|= ADVERTISE_100FULL
;
2892 if (tg3_readphy(tp
, MII_ADVERTISE
, &adv_reg
))
2895 if ((adv_reg
& all_mask
) != all_mask
)
2897 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
2901 if (mask
& ADVERTISED_1000baseT_Half
)
2902 all_mask
|= ADVERTISE_1000HALF
;
2903 if (mask
& ADVERTISED_1000baseT_Full
)
2904 all_mask
|= ADVERTISE_1000FULL
;
2906 if (tg3_readphy(tp
, MII_TG3_CTRL
, &tg3_ctrl
))
2909 if ((tg3_ctrl
& all_mask
) != all_mask
)
2915 static int tg3_adv_1000T_flowctrl_ok(struct tg3
*tp
, u32
*lcladv
, u32
*rmtadv
)
2919 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
2922 curadv
= *lcladv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2923 reqadv
= tg3_advert_flowctrl_1000T(tp
->link_config
.flowctrl
);
2925 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
2926 if (curadv
!= reqadv
)
2929 if (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
)
2930 tg3_readphy(tp
, MII_LPA
, rmtadv
);
2932 /* Reprogram the advertisement register, even if it
2933 * does not affect the current link. If the link
2934 * gets renegotiated in the future, we can save an
2935 * additional renegotiation cycle by advertising
2936 * it correctly in the first place.
2938 if (curadv
!= reqadv
) {
2939 *lcladv
&= ~(ADVERTISE_PAUSE_CAP
|
2940 ADVERTISE_PAUSE_ASYM
);
2941 tg3_writephy(tp
, MII_ADVERTISE
, *lcladv
| reqadv
);
2948 static int tg3_setup_copper_phy(struct tg3
*tp
, int force_reset
)
2950 int current_link_up
;
2952 u32 lcl_adv
, rmt_adv
;
2960 (MAC_STATUS_SYNC_CHANGED
|
2961 MAC_STATUS_CFG_CHANGED
|
2962 MAC_STATUS_MI_COMPLETION
|
2963 MAC_STATUS_LNKSTATE_CHANGED
));
2966 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
2968 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
2972 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x02);
2974 /* Some third-party PHYs need to be reset on link going
2977 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
2978 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
||
2979 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
2980 netif_carrier_ok(tp
->dev
)) {
2981 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2982 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
2983 !(bmsr
& BMSR_LSTATUS
))
2989 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
2990 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
2991 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
2992 !(tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
))
2995 if (!(bmsr
& BMSR_LSTATUS
)) {
2996 err
= tg3_init_5401phy_dsp(tp
);
3000 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3001 for (i
= 0; i
< 1000; i
++) {
3003 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3004 (bmsr
& BMSR_LSTATUS
)) {
3010 if ((tp
->phy_id
& PHY_ID_REV_MASK
) == PHY_REV_BCM5401_B0
&&
3011 !(bmsr
& BMSR_LSTATUS
) &&
3012 tp
->link_config
.active_speed
== SPEED_1000
) {
3013 err
= tg3_phy_reset(tp
);
3015 err
= tg3_init_5401phy_dsp(tp
);
3020 } else if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
3021 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
) {
3022 /* 5701 {A0,B0} CRC bug workaround */
3023 tg3_writephy(tp
, 0x15, 0x0a75);
3024 tg3_writephy(tp
, 0x1c, 0x8c68);
3025 tg3_writephy(tp
, 0x1c, 0x8d68);
3026 tg3_writephy(tp
, 0x1c, 0x8c68);
3029 /* Clear pending interrupts... */
3030 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3031 tg3_readphy(tp
, MII_TG3_ISTAT
, &dummy
);
3033 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
)
3034 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
3035 else if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
3036 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
3038 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
3039 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
3040 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
3041 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3042 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
3044 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
3047 current_link_up
= 0;
3048 current_speed
= SPEED_INVALID
;
3049 current_duplex
= DUPLEX_INVALID
;
3051 if (tp
->tg3_flags2
& TG3_FLG2_CAPACITIVE_COUPLING
) {
3054 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, 0x4007);
3055 tg3_readphy(tp
, MII_TG3_AUX_CTRL
, &val
);
3056 if (!(val
& (1 << 10))) {
3058 tg3_writephy(tp
, MII_TG3_AUX_CTRL
, val
);
3064 for (i
= 0; i
< 100; i
++) {
3065 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3066 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
3067 (bmsr
& BMSR_LSTATUS
))
3072 if (bmsr
& BMSR_LSTATUS
) {
3075 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
3076 for (i
= 0; i
< 2000; i
++) {
3078 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
3083 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
3088 for (i
= 0; i
< 200; i
++) {
3089 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
3090 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
3092 if (bmcr
&& bmcr
!= 0x7fff)
3100 tp
->link_config
.active_speed
= current_speed
;
3101 tp
->link_config
.active_duplex
= current_duplex
;
3103 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3104 if ((bmcr
& BMCR_ANENABLE
) &&
3105 tg3_copper_is_advertising_all(tp
,
3106 tp
->link_config
.advertising
)) {
3107 if (tg3_adv_1000T_flowctrl_ok(tp
, &lcl_adv
,
3109 current_link_up
= 1;
3112 if (!(bmcr
& BMCR_ANENABLE
) &&
3113 tp
->link_config
.speed
== current_speed
&&
3114 tp
->link_config
.duplex
== current_duplex
&&
3115 tp
->link_config
.flowctrl
==
3116 tp
->link_config
.active_flowctrl
) {
3117 current_link_up
= 1;
3121 if (current_link_up
== 1 &&
3122 tp
->link_config
.active_duplex
== DUPLEX_FULL
)
3123 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
3127 if (current_link_up
== 0 || tp
->link_config
.phy_is_low_power
) {
3130 tg3_phy_copper_begin(tp
);
3132 tg3_readphy(tp
, MII_BMSR
, &tmp
);
3133 if (!tg3_readphy(tp
, MII_BMSR
, &tmp
) &&
3134 (tmp
& BMSR_LSTATUS
))
3135 current_link_up
= 1;
3138 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
3139 if (current_link_up
== 1) {
3140 if (tp
->link_config
.active_speed
== SPEED_100
||
3141 tp
->link_config
.active_speed
== SPEED_10
)
3142 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3144 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3145 } else if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)
3146 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
3148 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3150 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
3151 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
3152 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
3154 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
3155 if (current_link_up
== 1 &&
3156 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
3157 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
3159 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
3162 /* ??? Without this setting Netgear GA302T PHY does not
3163 * ??? send/receive packets...
3165 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
&&
3166 tp
->pci_chip_rev_id
== CHIPREV_ID_5700_ALTIMA
) {
3167 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
3168 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
3172 tw32_f(MAC_MODE
, tp
->mac_mode
);
3175 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
3176 /* Polled via timer. */
3177 tw32_f(MAC_EVENT
, 0);
3179 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3183 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
&&
3184 current_link_up
== 1 &&
3185 tp
->link_config
.active_speed
== SPEED_1000
&&
3186 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) ||
3187 (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
))) {
3190 (MAC_STATUS_SYNC_CHANGED
|
3191 MAC_STATUS_CFG_CHANGED
));
3194 NIC_SRAM_FIRMWARE_MBOX
,
3195 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
3198 /* Prevent send BD corruption. */
3199 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
) {
3200 u16 oldlnkctl
, newlnkctl
;
3202 pci_read_config_word(tp
->pdev
,
3203 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3205 if (tp
->link_config
.active_speed
== SPEED_100
||
3206 tp
->link_config
.active_speed
== SPEED_10
)
3207 newlnkctl
= oldlnkctl
& ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3209 newlnkctl
= oldlnkctl
| PCI_EXP_LNKCTL_CLKREQ_EN
;
3210 if (newlnkctl
!= oldlnkctl
)
3211 pci_write_config_word(tp
->pdev
,
3212 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
3214 } else if (tp
->tg3_flags3
& TG3_FLG3_TOGGLE_10_100_L1PLLPD
) {
3215 u32 newreg
, oldreg
= tr32(TG3_PCIE_LNKCTL
);
3216 if (tp
->link_config
.active_speed
== SPEED_100
||
3217 tp
->link_config
.active_speed
== SPEED_10
)
3218 newreg
= oldreg
& ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
3220 newreg
= oldreg
| TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
3221 if (newreg
!= oldreg
)
3222 tw32(TG3_PCIE_LNKCTL
, newreg
);
3225 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3226 if (current_link_up
)
3227 netif_carrier_on(tp
->dev
);
3229 netif_carrier_off(tp
->dev
);
3230 tg3_link_report(tp
);
3236 struct tg3_fiber_aneginfo
{
3238 #define ANEG_STATE_UNKNOWN 0
3239 #define ANEG_STATE_AN_ENABLE 1
3240 #define ANEG_STATE_RESTART_INIT 2
3241 #define ANEG_STATE_RESTART 3
3242 #define ANEG_STATE_DISABLE_LINK_OK 4
3243 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3244 #define ANEG_STATE_ABILITY_DETECT 6
3245 #define ANEG_STATE_ACK_DETECT_INIT 7
3246 #define ANEG_STATE_ACK_DETECT 8
3247 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3248 #define ANEG_STATE_COMPLETE_ACK 10
3249 #define ANEG_STATE_IDLE_DETECT_INIT 11
3250 #define ANEG_STATE_IDLE_DETECT 12
3251 #define ANEG_STATE_LINK_OK 13
3252 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3253 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3256 #define MR_AN_ENABLE 0x00000001
3257 #define MR_RESTART_AN 0x00000002
3258 #define MR_AN_COMPLETE 0x00000004
3259 #define MR_PAGE_RX 0x00000008
3260 #define MR_NP_LOADED 0x00000010
3261 #define MR_TOGGLE_TX 0x00000020
3262 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3263 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3264 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3265 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3266 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3267 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3268 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3269 #define MR_TOGGLE_RX 0x00002000
3270 #define MR_NP_RX 0x00004000
3272 #define MR_LINK_OK 0x80000000
3274 unsigned long link_time
, cur_time
;
3276 u32 ability_match_cfg
;
3277 int ability_match_count
;
3279 char ability_match
, idle_match
, ack_match
;
3281 u32 txconfig
, rxconfig
;
3282 #define ANEG_CFG_NP 0x00000080
3283 #define ANEG_CFG_ACK 0x00000040
3284 #define ANEG_CFG_RF2 0x00000020
3285 #define ANEG_CFG_RF1 0x00000010
3286 #define ANEG_CFG_PS2 0x00000001
3287 #define ANEG_CFG_PS1 0x00008000
3288 #define ANEG_CFG_HD 0x00004000
3289 #define ANEG_CFG_FD 0x00002000
3290 #define ANEG_CFG_INVAL 0x00001f06
3295 #define ANEG_TIMER_ENAB 2
3296 #define ANEG_FAILED -1
3298 #define ANEG_STATE_SETTLE_TIME 10000
3300 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
3301 struct tg3_fiber_aneginfo
*ap
)
3304 unsigned long delta
;
3308 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
3312 ap
->ability_match_cfg
= 0;
3313 ap
->ability_match_count
= 0;
3314 ap
->ability_match
= 0;
3320 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
3321 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
3323 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
3324 ap
->ability_match_cfg
= rx_cfg_reg
;
3325 ap
->ability_match
= 0;
3326 ap
->ability_match_count
= 0;
3328 if (++ap
->ability_match_count
> 1) {
3329 ap
->ability_match
= 1;
3330 ap
->ability_match_cfg
= rx_cfg_reg
;
3333 if (rx_cfg_reg
& ANEG_CFG_ACK
)
3341 ap
->ability_match_cfg
= 0;
3342 ap
->ability_match_count
= 0;
3343 ap
->ability_match
= 0;
3349 ap
->rxconfig
= rx_cfg_reg
;
3353 case ANEG_STATE_UNKNOWN
:
3354 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
3355 ap
->state
= ANEG_STATE_AN_ENABLE
;
3358 case ANEG_STATE_AN_ENABLE
:
3359 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
3360 if (ap
->flags
& MR_AN_ENABLE
) {
3363 ap
->ability_match_cfg
= 0;
3364 ap
->ability_match_count
= 0;
3365 ap
->ability_match
= 0;
3369 ap
->state
= ANEG_STATE_RESTART_INIT
;
3371 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
3375 case ANEG_STATE_RESTART_INIT
:
3376 ap
->link_time
= ap
->cur_time
;
3377 ap
->flags
&= ~(MR_NP_LOADED
);
3379 tw32(MAC_TX_AUTO_NEG
, 0);
3380 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3381 tw32_f(MAC_MODE
, tp
->mac_mode
);
3384 ret
= ANEG_TIMER_ENAB
;
3385 ap
->state
= ANEG_STATE_RESTART
;
3388 case ANEG_STATE_RESTART
:
3389 delta
= ap
->cur_time
- ap
->link_time
;
3390 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3391 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
3393 ret
= ANEG_TIMER_ENAB
;
3397 case ANEG_STATE_DISABLE_LINK_OK
:
3401 case ANEG_STATE_ABILITY_DETECT_INIT
:
3402 ap
->flags
&= ~(MR_TOGGLE_TX
);
3403 ap
->txconfig
= ANEG_CFG_FD
;
3404 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3405 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3406 ap
->txconfig
|= ANEG_CFG_PS1
;
3407 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3408 ap
->txconfig
|= ANEG_CFG_PS2
;
3409 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3410 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3411 tw32_f(MAC_MODE
, tp
->mac_mode
);
3414 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
3417 case ANEG_STATE_ABILITY_DETECT
:
3418 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0) {
3419 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
3423 case ANEG_STATE_ACK_DETECT_INIT
:
3424 ap
->txconfig
|= ANEG_CFG_ACK
;
3425 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
3426 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
3427 tw32_f(MAC_MODE
, tp
->mac_mode
);
3430 ap
->state
= ANEG_STATE_ACK_DETECT
;
3433 case ANEG_STATE_ACK_DETECT
:
3434 if (ap
->ack_match
!= 0) {
3435 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
3436 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
3437 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
3439 ap
->state
= ANEG_STATE_AN_ENABLE
;
3441 } else if (ap
->ability_match
!= 0 &&
3442 ap
->rxconfig
== 0) {
3443 ap
->state
= ANEG_STATE_AN_ENABLE
;
3447 case ANEG_STATE_COMPLETE_ACK_INIT
:
3448 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
3452 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
3453 MR_LP_ADV_HALF_DUPLEX
|
3454 MR_LP_ADV_SYM_PAUSE
|
3455 MR_LP_ADV_ASYM_PAUSE
|
3456 MR_LP_ADV_REMOTE_FAULT1
|
3457 MR_LP_ADV_REMOTE_FAULT2
|
3458 MR_LP_ADV_NEXT_PAGE
|
3461 if (ap
->rxconfig
& ANEG_CFG_FD
)
3462 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
3463 if (ap
->rxconfig
& ANEG_CFG_HD
)
3464 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
3465 if (ap
->rxconfig
& ANEG_CFG_PS1
)
3466 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
3467 if (ap
->rxconfig
& ANEG_CFG_PS2
)
3468 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
3469 if (ap
->rxconfig
& ANEG_CFG_RF1
)
3470 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
3471 if (ap
->rxconfig
& ANEG_CFG_RF2
)
3472 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
3473 if (ap
->rxconfig
& ANEG_CFG_NP
)
3474 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
3476 ap
->link_time
= ap
->cur_time
;
3478 ap
->flags
^= (MR_TOGGLE_TX
);
3479 if (ap
->rxconfig
& 0x0008)
3480 ap
->flags
|= MR_TOGGLE_RX
;
3481 if (ap
->rxconfig
& ANEG_CFG_NP
)
3482 ap
->flags
|= MR_NP_RX
;
3483 ap
->flags
|= MR_PAGE_RX
;
3485 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
3486 ret
= ANEG_TIMER_ENAB
;
3489 case ANEG_STATE_COMPLETE_ACK
:
3490 if (ap
->ability_match
!= 0 &&
3491 ap
->rxconfig
== 0) {
3492 ap
->state
= ANEG_STATE_AN_ENABLE
;
3495 delta
= ap
->cur_time
- ap
->link_time
;
3496 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3497 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
3498 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3500 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
3501 !(ap
->flags
& MR_NP_RX
)) {
3502 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
3510 case ANEG_STATE_IDLE_DETECT_INIT
:
3511 ap
->link_time
= ap
->cur_time
;
3512 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3513 tw32_f(MAC_MODE
, tp
->mac_mode
);
3516 ap
->state
= ANEG_STATE_IDLE_DETECT
;
3517 ret
= ANEG_TIMER_ENAB
;
3520 case ANEG_STATE_IDLE_DETECT
:
3521 if (ap
->ability_match
!= 0 &&
3522 ap
->rxconfig
== 0) {
3523 ap
->state
= ANEG_STATE_AN_ENABLE
;
3526 delta
= ap
->cur_time
- ap
->link_time
;
3527 if (delta
> ANEG_STATE_SETTLE_TIME
) {
3528 /* XXX another gem from the Broadcom driver :( */
3529 ap
->state
= ANEG_STATE_LINK_OK
;
3533 case ANEG_STATE_LINK_OK
:
3534 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
3538 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
3539 /* ??? unimplemented */
3542 case ANEG_STATE_NEXT_PAGE_WAIT
:
3543 /* ??? unimplemented */
3554 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
3557 struct tg3_fiber_aneginfo aninfo
;
3558 int status
= ANEG_FAILED
;
3562 tw32_f(MAC_TX_AUTO_NEG
, 0);
3564 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
3565 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
3568 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
3571 memset(&aninfo
, 0, sizeof(aninfo
));
3572 aninfo
.flags
|= MR_AN_ENABLE
;
3573 aninfo
.state
= ANEG_STATE_UNKNOWN
;
3574 aninfo
.cur_time
= 0;
3576 while (++tick
< 195000) {
3577 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
3578 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
3584 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
3585 tw32_f(MAC_MODE
, tp
->mac_mode
);
3588 *txflags
= aninfo
.txconfig
;
3589 *rxflags
= aninfo
.flags
;
3591 if (status
== ANEG_DONE
&&
3592 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
3593 MR_LP_ADV_FULL_DUPLEX
)))
3599 static void tg3_init_bcm8002(struct tg3
*tp
)
3601 u32 mac_status
= tr32(MAC_STATUS
);
3604 /* Reset when initting first time or we have a link. */
3605 if ((tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) &&
3606 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
3609 /* Set PLL lock range. */
3610 tg3_writephy(tp
, 0x16, 0x8007);
3613 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
3615 /* Wait for reset to complete. */
3616 /* XXX schedule_timeout() ... */
3617 for (i
= 0; i
< 500; i
++)
3620 /* Config mode; select PMA/Ch 1 regs. */
3621 tg3_writephy(tp
, 0x10, 0x8411);
3623 /* Enable auto-lock and comdet, select txclk for tx. */
3624 tg3_writephy(tp
, 0x11, 0x0a10);
3626 tg3_writephy(tp
, 0x18, 0x00a0);
3627 tg3_writephy(tp
, 0x16, 0x41ff);
3629 /* Assert and deassert POR. */
3630 tg3_writephy(tp
, 0x13, 0x0400);
3632 tg3_writephy(tp
, 0x13, 0x0000);
3634 tg3_writephy(tp
, 0x11, 0x0a50);
3636 tg3_writephy(tp
, 0x11, 0x0a10);
3638 /* Wait for signal to stabilize */
3639 /* XXX schedule_timeout() ... */
3640 for (i
= 0; i
< 15000; i
++)
3643 /* Deselect the channel register so we can read the PHYID
3646 tg3_writephy(tp
, 0x10, 0x8011);
3649 static int tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
3652 u32 sg_dig_ctrl
, sg_dig_status
;
3653 u32 serdes_cfg
, expected_sg_dig_ctrl
;
3654 int workaround
, port_a
;
3655 int current_link_up
;
3658 expected_sg_dig_ctrl
= 0;
3661 current_link_up
= 0;
3663 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A0
&&
3664 tp
->pci_chip_rev_id
!= CHIPREV_ID_5704_A1
) {
3666 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
3669 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3670 /* preserve bits 20-23 for voltage regulator */
3671 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
3674 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3676 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
3677 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
3679 u32 val
= serdes_cfg
;
3685 tw32_f(MAC_SERDES_CFG
, val
);
3688 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3690 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
3691 tg3_setup_flow_control(tp
, 0, 0);
3692 current_link_up
= 1;
3697 /* Want auto-negotiation. */
3698 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
3700 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
3701 if (flowctrl
& ADVERTISE_1000XPAUSE
)
3702 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
3703 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
3704 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
3706 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
3707 if ((tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
) &&
3708 tp
->serdes_counter
&&
3709 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
3710 MAC_STATUS_RCVD_CFG
)) ==
3711 MAC_STATUS_PCS_SYNCED
)) {
3712 tp
->serdes_counter
--;
3713 current_link_up
= 1;
3718 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
3719 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
3721 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
3723 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3724 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3725 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
3726 MAC_STATUS_SIGNAL_DET
)) {
3727 sg_dig_status
= tr32(SG_DIG_STATUS
);
3728 mac_status
= tr32(MAC_STATUS
);
3730 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
3731 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
3732 u32 local_adv
= 0, remote_adv
= 0;
3734 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
3735 local_adv
|= ADVERTISE_1000XPAUSE
;
3736 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
3737 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3739 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
3740 remote_adv
|= LPA_1000XPAUSE
;
3741 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
3742 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3744 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3745 current_link_up
= 1;
3746 tp
->serdes_counter
= 0;
3747 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3748 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
3749 if (tp
->serdes_counter
)
3750 tp
->serdes_counter
--;
3753 u32 val
= serdes_cfg
;
3760 tw32_f(MAC_SERDES_CFG
, val
);
3763 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
3766 /* Link parallel detection - link is up */
3767 /* only if we have PCS_SYNC and not */
3768 /* receiving config code words */
3769 mac_status
= tr32(MAC_STATUS
);
3770 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3771 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
3772 tg3_setup_flow_control(tp
, 0, 0);
3773 current_link_up
= 1;
3775 TG3_FLG2_PARALLEL_DETECT
;
3776 tp
->serdes_counter
=
3777 SERDES_PARALLEL_DET_TIMEOUT
;
3779 goto restart_autoneg
;
3783 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
3784 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
3788 return current_link_up
;
3791 static int tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
3793 int current_link_up
= 0;
3795 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
3798 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
3799 u32 txflags
, rxflags
;
3802 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
3803 u32 local_adv
= 0, remote_adv
= 0;
3805 if (txflags
& ANEG_CFG_PS1
)
3806 local_adv
|= ADVERTISE_1000XPAUSE
;
3807 if (txflags
& ANEG_CFG_PS2
)
3808 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
3810 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
3811 remote_adv
|= LPA_1000XPAUSE
;
3812 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
3813 remote_adv
|= LPA_1000XPAUSE_ASYM
;
3815 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
3817 current_link_up
= 1;
3819 for (i
= 0; i
< 30; i
++) {
3822 (MAC_STATUS_SYNC_CHANGED
|
3823 MAC_STATUS_CFG_CHANGED
));
3825 if ((tr32(MAC_STATUS
) &
3826 (MAC_STATUS_SYNC_CHANGED
|
3827 MAC_STATUS_CFG_CHANGED
)) == 0)
3831 mac_status
= tr32(MAC_STATUS
);
3832 if (current_link_up
== 0 &&
3833 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
3834 !(mac_status
& MAC_STATUS_RCVD_CFG
))
3835 current_link_up
= 1;
3837 tg3_setup_flow_control(tp
, 0, 0);
3839 /* Forcing 1000FD link up. */
3840 current_link_up
= 1;
3842 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
3845 tw32_f(MAC_MODE
, tp
->mac_mode
);
3850 return current_link_up
;
3853 static int tg3_setup_fiber_phy(struct tg3
*tp
, int force_reset
)
3856 u16 orig_active_speed
;
3857 u8 orig_active_duplex
;
3859 int current_link_up
;
3862 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
3863 orig_active_speed
= tp
->link_config
.active_speed
;
3864 orig_active_duplex
= tp
->link_config
.active_duplex
;
3866 if (!(tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
) &&
3867 netif_carrier_ok(tp
->dev
) &&
3868 (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
)) {
3869 mac_status
= tr32(MAC_STATUS
);
3870 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
3871 MAC_STATUS_SIGNAL_DET
|
3872 MAC_STATUS_CFG_CHANGED
|
3873 MAC_STATUS_RCVD_CFG
);
3874 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
3875 MAC_STATUS_SIGNAL_DET
)) {
3876 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3877 MAC_STATUS_CFG_CHANGED
));
3882 tw32_f(MAC_TX_AUTO_NEG
, 0);
3884 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
3885 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
3886 tw32_f(MAC_MODE
, tp
->mac_mode
);
3889 if (tp
->phy_id
== PHY_ID_BCM8002
)
3890 tg3_init_bcm8002(tp
);
3892 /* Enable link change event even when serdes polling. */
3893 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
3896 current_link_up
= 0;
3897 mac_status
= tr32(MAC_STATUS
);
3899 if (tp
->tg3_flags2
& TG3_FLG2_HW_AUTONEG
)
3900 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
3902 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
3904 tp
->napi
[0].hw_status
->status
=
3905 (SD_STATUS_UPDATED
|
3906 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
3908 for (i
= 0; i
< 100; i
++) {
3909 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
3910 MAC_STATUS_CFG_CHANGED
));
3912 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
3913 MAC_STATUS_CFG_CHANGED
|
3914 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
3918 mac_status
= tr32(MAC_STATUS
);
3919 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
3920 current_link_up
= 0;
3921 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
3922 tp
->serdes_counter
== 0) {
3923 tw32_f(MAC_MODE
, (tp
->mac_mode
|
3924 MAC_MODE_SEND_CONFIGS
));
3926 tw32_f(MAC_MODE
, tp
->mac_mode
);
3930 if (current_link_up
== 1) {
3931 tp
->link_config
.active_speed
= SPEED_1000
;
3932 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
3933 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3934 LED_CTRL_LNKLED_OVERRIDE
|
3935 LED_CTRL_1000MBPS_ON
));
3937 tp
->link_config
.active_speed
= SPEED_INVALID
;
3938 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
3939 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
3940 LED_CTRL_LNKLED_OVERRIDE
|
3941 LED_CTRL_TRAFFIC_OVERRIDE
));
3944 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
3945 if (current_link_up
)
3946 netif_carrier_on(tp
->dev
);
3948 netif_carrier_off(tp
->dev
);
3949 tg3_link_report(tp
);
3951 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
3952 if (orig_pause_cfg
!= now_pause_cfg
||
3953 orig_active_speed
!= tp
->link_config
.active_speed
||
3954 orig_active_duplex
!= tp
->link_config
.active_duplex
)
3955 tg3_link_report(tp
);
3961 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, int force_reset
)
3963 int current_link_up
, err
= 0;
3967 u32 local_adv
, remote_adv
;
3969 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
3970 tw32_f(MAC_MODE
, tp
->mac_mode
);
3976 (MAC_STATUS_SYNC_CHANGED
|
3977 MAC_STATUS_CFG_CHANGED
|
3978 MAC_STATUS_MI_COMPLETION
|
3979 MAC_STATUS_LNKSTATE_CHANGED
));
3985 current_link_up
= 0;
3986 current_speed
= SPEED_INVALID
;
3987 current_duplex
= DUPLEX_INVALID
;
3989 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3990 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
3991 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
3992 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
3993 bmsr
|= BMSR_LSTATUS
;
3995 bmsr
&= ~BMSR_LSTATUS
;
3998 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4000 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
4001 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4002 /* do nothing, just check for link up at the end */
4003 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4006 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4007 new_adv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
4008 ADVERTISE_1000XPAUSE
|
4009 ADVERTISE_1000XPSE_ASYM
|
4012 new_adv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
4014 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Half
)
4015 new_adv
|= ADVERTISE_1000XHALF
;
4016 if (tp
->link_config
.advertising
& ADVERTISED_1000baseT_Full
)
4017 new_adv
|= ADVERTISE_1000XFULL
;
4019 if ((new_adv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
4020 tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4021 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
4022 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4024 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4025 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
4026 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4033 bmcr
&= ~BMCR_SPEED1000
;
4034 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
4036 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4037 new_bmcr
|= BMCR_FULLDPLX
;
4039 if (new_bmcr
!= bmcr
) {
4040 /* BMCR_SPEED1000 is a reserved bit that needs
4041 * to be set on write.
4043 new_bmcr
|= BMCR_SPEED1000
;
4045 /* Force a linkdown */
4046 if (netif_carrier_ok(tp
->dev
)) {
4049 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
4050 adv
&= ~(ADVERTISE_1000XFULL
|
4051 ADVERTISE_1000XHALF
|
4053 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
4054 tg3_writephy(tp
, MII_BMCR
, bmcr
|
4058 netif_carrier_off(tp
->dev
);
4060 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
4062 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4063 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4064 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
4066 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
4067 bmsr
|= BMSR_LSTATUS
;
4069 bmsr
&= ~BMSR_LSTATUS
;
4071 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4075 if (bmsr
& BMSR_LSTATUS
) {
4076 current_speed
= SPEED_1000
;
4077 current_link_up
= 1;
4078 if (bmcr
& BMCR_FULLDPLX
)
4079 current_duplex
= DUPLEX_FULL
;
4081 current_duplex
= DUPLEX_HALF
;
4086 if (bmcr
& BMCR_ANENABLE
) {
4089 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
4090 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
4091 common
= local_adv
& remote_adv
;
4092 if (common
& (ADVERTISE_1000XHALF
|
4093 ADVERTISE_1000XFULL
)) {
4094 if (common
& ADVERTISE_1000XFULL
)
4095 current_duplex
= DUPLEX_FULL
;
4097 current_duplex
= DUPLEX_HALF
;
4100 current_link_up
= 0;
4104 if (current_link_up
== 1 && current_duplex
== DUPLEX_FULL
)
4105 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
4107 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4108 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4109 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4111 tw32_f(MAC_MODE
, tp
->mac_mode
);
4114 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4116 tp
->link_config
.active_speed
= current_speed
;
4117 tp
->link_config
.active_duplex
= current_duplex
;
4119 if (current_link_up
!= netif_carrier_ok(tp
->dev
)) {
4120 if (current_link_up
)
4121 netif_carrier_on(tp
->dev
);
4123 netif_carrier_off(tp
->dev
);
4124 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4126 tg3_link_report(tp
);
4131 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
4133 if (tp
->serdes_counter
) {
4134 /* Give autoneg time to complete. */
4135 tp
->serdes_counter
--;
4138 if (!netif_carrier_ok(tp
->dev
) &&
4139 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
4142 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4143 if (bmcr
& BMCR_ANENABLE
) {
4146 /* Select shadow register 0x1f */
4147 tg3_writephy(tp
, 0x1c, 0x7c00);
4148 tg3_readphy(tp
, 0x1c, &phy1
);
4150 /* Select expansion interrupt status register */
4151 tg3_writephy(tp
, 0x17, 0x0f01);
4152 tg3_readphy(tp
, 0x15, &phy2
);
4153 tg3_readphy(tp
, 0x15, &phy2
);
4155 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
4156 /* We have signal detect and not receiving
4157 * config code words, link is up by parallel
4161 bmcr
&= ~BMCR_ANENABLE
;
4162 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
4163 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4164 tp
->tg3_flags2
|= TG3_FLG2_PARALLEL_DETECT
;
4168 else if (netif_carrier_ok(tp
->dev
) &&
4169 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
4170 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
)) {
4173 /* Select expansion interrupt status register */
4174 tg3_writephy(tp
, 0x17, 0x0f01);
4175 tg3_readphy(tp
, 0x15, &phy2
);
4179 /* Config code words received, turn on autoneg. */
4180 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4181 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
4183 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
4189 static int tg3_setup_phy(struct tg3
*tp
, int force_reset
)
4193 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
4194 err
= tg3_setup_fiber_phy(tp
, force_reset
);
4195 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
4196 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
4198 err
= tg3_setup_copper_phy(tp
, force_reset
);
4201 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
4204 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
4205 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
4207 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
4212 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
4213 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
4214 tw32(GRC_MISC_CFG
, val
);
4217 if (tp
->link_config
.active_speed
== SPEED_1000
&&
4218 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4219 tw32(MAC_TX_LENGTHS
,
4220 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4221 (6 << TX_LENGTHS_IPG_SHIFT
) |
4222 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4224 tw32(MAC_TX_LENGTHS
,
4225 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
4226 (6 << TX_LENGTHS_IPG_SHIFT
) |
4227 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
4229 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
4230 if (netif_carrier_ok(tp
->dev
)) {
4231 tw32(HOSTCC_STAT_COAL_TICKS
,
4232 tp
->coal
.stats_block_coalesce_usecs
);
4234 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
4238 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
) {
4239 u32 val
= tr32(PCIE_PWR_MGMT_THRESH
);
4240 if (!netif_carrier_ok(tp
->dev
))
4241 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
4244 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
4245 tw32(PCIE_PWR_MGMT_THRESH
, val
);
4251 /* This is called whenever we suspect that the system chipset is re-
4252 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4253 * is bogus tx completions. We try to recover by setting the
4254 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4257 static void tg3_tx_recover(struct tg3
*tp
)
4259 BUG_ON((tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
) ||
4260 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
4262 printk(KERN_WARNING PFX
"%s: The system may be re-ordering memory-"
4263 "mapped I/O cycles to the network device, attempting to "
4264 "recover. Please report the problem to the driver maintainer "
4265 "and include system chipset information.\n", tp
->dev
->name
);
4267 spin_lock(&tp
->lock
);
4268 tp
->tg3_flags
|= TG3_FLAG_TX_RECOVERY_PENDING
;
4269 spin_unlock(&tp
->lock
);
4272 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
4275 return tnapi
->tx_pending
-
4276 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
4279 /* Tigon3 never reports partial packet sends. So we do not
4280 * need special logic to handle SKBs that have not had all
4281 * of their frags sent yet, like SunGEM does.
4283 static void tg3_tx(struct tg3_napi
*tnapi
)
4285 struct tg3
*tp
= tnapi
->tp
;
4286 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
4287 u32 sw_idx
= tnapi
->tx_cons
;
4289 while (sw_idx
!= hw_idx
) {
4290 struct tx_ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
4291 struct sk_buff
*skb
= ri
->skb
;
4294 if (unlikely(skb
== NULL
)) {
4299 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
4303 sw_idx
= NEXT_TX(sw_idx
);
4305 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
4306 ri
= &tnapi
->tx_buffers
[sw_idx
];
4307 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
4309 sw_idx
= NEXT_TX(sw_idx
);
4314 if (unlikely(tx_bug
)) {
4320 tnapi
->tx_cons
= sw_idx
;
4322 /* Need to make the tx_cons update visible to tg3_start_xmit()
4323 * before checking for netif_queue_stopped(). Without the
4324 * memory barrier, there is a small possibility that tg3_start_xmit()
4325 * will miss it and cause the queue to be stopped forever.
4329 if (unlikely(netif_queue_stopped(tp
->dev
) &&
4330 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
4331 netif_tx_lock(tp
->dev
);
4332 if (netif_queue_stopped(tp
->dev
) &&
4333 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
4334 netif_wake_queue(tp
->dev
);
4335 netif_tx_unlock(tp
->dev
);
4339 /* Returns size of skb allocated or < 0 on error.
4341 * We only need to fill in the address because the other members
4342 * of the RX descriptor are invariant, see tg3_init_rings.
4344 * Note the purposeful assymetry of cpu vs. chip accesses. For
4345 * posting buffers we only dirty the first cache line of the RX
4346 * descriptor (containing the address). Whereas for the RX status
4347 * buffers the cpu only reads the last cacheline of the RX descriptor
4348 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4350 static int tg3_alloc_rx_skb(struct tg3_napi
*tnapi
, u32 opaque_key
,
4351 int src_idx
, u32 dest_idx_unmasked
)
4353 struct tg3
*tp
= tnapi
->tp
;
4354 struct tg3_rx_buffer_desc
*desc
;
4355 struct ring_info
*map
, *src_map
;
4356 struct sk_buff
*skb
;
4358 int skb_size
, dest_idx
;
4359 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4362 switch (opaque_key
) {
4363 case RXD_OPAQUE_RING_STD
:
4364 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4365 desc
= &tpr
->rx_std
[dest_idx
];
4366 map
= &tpr
->rx_std_buffers
[dest_idx
];
4368 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4369 skb_size
= tp
->rx_pkt_map_sz
;
4372 case RXD_OPAQUE_RING_JUMBO
:
4373 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4374 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4375 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4377 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4378 skb_size
= TG3_RX_JMB_MAP_SZ
;
4385 /* Do not overwrite any of the map or rp information
4386 * until we are sure we can commit to a new buffer.
4388 * Callers depend upon this behavior and assume that
4389 * we leave everything unchanged if we fail.
4391 skb
= netdev_alloc_skb(tp
->dev
, skb_size
+ tp
->rx_offset
);
4395 skb_reserve(skb
, tp
->rx_offset
);
4397 mapping
= pci_map_single(tp
->pdev
, skb
->data
, skb_size
,
4398 PCI_DMA_FROMDEVICE
);
4401 pci_unmap_addr_set(map
, mapping
, mapping
);
4403 if (src_map
!= NULL
)
4404 src_map
->skb
= NULL
;
4406 desc
->addr_hi
= ((u64
)mapping
>> 32);
4407 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
4412 /* We only need to move over in the address because the other
4413 * members of the RX descriptor are invariant. See notes above
4414 * tg3_alloc_rx_skb for full details.
4416 static void tg3_recycle_rx(struct tg3_napi
*tnapi
, u32 opaque_key
,
4417 int src_idx
, u32 dest_idx_unmasked
)
4419 struct tg3
*tp
= tnapi
->tp
;
4420 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
4421 struct ring_info
*src_map
, *dest_map
;
4423 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4425 switch (opaque_key
) {
4426 case RXD_OPAQUE_RING_STD
:
4427 dest_idx
= dest_idx_unmasked
% TG3_RX_RING_SIZE
;
4428 dest_desc
= &tpr
->rx_std
[dest_idx
];
4429 dest_map
= &tpr
->rx_std_buffers
[dest_idx
];
4430 src_desc
= &tpr
->rx_std
[src_idx
];
4431 src_map
= &tpr
->rx_std_buffers
[src_idx
];
4434 case RXD_OPAQUE_RING_JUMBO
:
4435 dest_idx
= dest_idx_unmasked
% TG3_RX_JUMBO_RING_SIZE
;
4436 dest_desc
= &tpr
->rx_jmb
[dest_idx
].std
;
4437 dest_map
= &tpr
->rx_jmb_buffers
[dest_idx
];
4438 src_desc
= &tpr
->rx_jmb
[src_idx
].std
;
4439 src_map
= &tpr
->rx_jmb_buffers
[src_idx
];
4446 dest_map
->skb
= src_map
->skb
;
4447 pci_unmap_addr_set(dest_map
, mapping
,
4448 pci_unmap_addr(src_map
, mapping
));
4449 dest_desc
->addr_hi
= src_desc
->addr_hi
;
4450 dest_desc
->addr_lo
= src_desc
->addr_lo
;
4452 src_map
->skb
= NULL
;
4455 /* The RX ring scheme is composed of multiple rings which post fresh
4456 * buffers to the chip, and one special ring the chip uses to report
4457 * status back to the host.
4459 * The special ring reports the status of received packets to the
4460 * host. The chip does not write into the original descriptor the
4461 * RX buffer was obtained from. The chip simply takes the original
4462 * descriptor as provided by the host, updates the status and length
4463 * field, then writes this into the next status ring entry.
4465 * Each ring the host uses to post buffers to the chip is described
4466 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4467 * it is first placed into the on-chip ram. When the packet's length
4468 * is known, it walks down the TG3_BDINFO entries to select the ring.
4469 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4470 * which is within the range of the new packet's length is chosen.
4472 * The "separate ring for rx status" scheme may sound queer, but it makes
4473 * sense from a cache coherency perspective. If only the host writes
4474 * to the buffer post rings, and only the chip writes to the rx status
4475 * rings, then cache lines never move beyond shared-modified state.
4476 * If both the host and chip were to write into the same ring, cache line
4477 * eviction could occur since both entities want it in an exclusive state.
4479 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
4481 struct tg3
*tp
= tnapi
->tp
;
4482 u32 work_mask
, rx_std_posted
= 0;
4483 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
4486 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
4488 hw_idx
= tnapi
->hw_status
->idx
[0].rx_producer
;
4490 * We need to order the read of hw_idx and the read of
4491 * the opaque cookie.
4496 while (sw_idx
!= hw_idx
&& budget
> 0) {
4497 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
4499 struct sk_buff
*skb
;
4500 dma_addr_t dma_addr
;
4501 u32 opaque_key
, desc_idx
, *post_ptr
;
4503 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
4504 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
4505 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
4506 struct ring_info
*ri
= &tpr
->rx_std_buffers
[desc_idx
];
4507 dma_addr
= pci_unmap_addr(ri
, mapping
);
4509 post_ptr
= &tpr
->rx_std_ptr
;
4511 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
4512 struct ring_info
*ri
= &tpr
->rx_jmb_buffers
[desc_idx
];
4513 dma_addr
= pci_unmap_addr(ri
, mapping
);
4515 post_ptr
= &tpr
->rx_jmb_ptr
;
4517 goto next_pkt_nopost
;
4519 work_mask
|= opaque_key
;
4521 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
4522 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
4524 tg3_recycle_rx(tnapi
, opaque_key
,
4525 desc_idx
, *post_ptr
);
4527 /* Other statistics kept track of by card. */
4528 tp
->net_stats
.rx_dropped
++;
4532 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
4535 if (len
> RX_COPY_THRESHOLD
4536 && tp
->rx_offset
== NET_IP_ALIGN
4537 /* rx_offset will likely not equal NET_IP_ALIGN
4538 * if this is a 5701 card running in PCI-X mode
4539 * [see tg3_get_invariants()]
4544 skb_size
= tg3_alloc_rx_skb(tnapi
, opaque_key
,
4545 desc_idx
, *post_ptr
);
4549 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
4550 PCI_DMA_FROMDEVICE
);
4554 struct sk_buff
*copy_skb
;
4556 tg3_recycle_rx(tnapi
, opaque_key
,
4557 desc_idx
, *post_ptr
);
4559 copy_skb
= netdev_alloc_skb(tp
->dev
,
4560 len
+ TG3_RAW_IP_ALIGN
);
4561 if (copy_skb
== NULL
)
4562 goto drop_it_no_recycle
;
4564 skb_reserve(copy_skb
, TG3_RAW_IP_ALIGN
);
4565 skb_put(copy_skb
, len
);
4566 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4567 skb_copy_from_linear_data(skb
, copy_skb
->data
, len
);
4568 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
4570 /* We'll reuse the original ring buffer. */
4574 if ((tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) &&
4575 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
4576 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
4577 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
4578 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4580 skb
->ip_summed
= CHECKSUM_NONE
;
4582 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
4584 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
4585 skb
->protocol
!= htons(ETH_P_8021Q
)) {
4590 #if TG3_VLAN_TAG_USED
4591 if (tp
->vlgrp
!= NULL
&&
4592 desc
->type_flags
& RXD_FLAG_VLAN
) {
4593 vlan_gro_receive(&tnapi
->napi
, tp
->vlgrp
,
4594 desc
->err_vlan
& RXD_VLAN_MASK
, skb
);
4597 napi_gro_receive(&tnapi
->napi
, skb
);
4605 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
4606 u32 idx
= *post_ptr
% TG3_RX_RING_SIZE
;
4608 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+
4609 TG3_64BIT_REG_LOW
, idx
);
4610 work_mask
&= ~RXD_OPAQUE_RING_STD
;
4615 sw_idx
&= (TG3_RX_RCB_RING_SIZE(tp
) - 1);
4617 /* Refresh hw_idx to see if there is new work */
4618 if (sw_idx
== hw_idx
) {
4619 hw_idx
= tnapi
->hw_status
->idx
[0].rx_producer
;
4624 /* ACK the status ring. */
4625 tnapi
->rx_rcb_ptr
= sw_idx
;
4626 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
4628 /* Refill RX ring(s). */
4629 if (work_mask
& RXD_OPAQUE_RING_STD
) {
4630 sw_idx
= tpr
->rx_std_ptr
% TG3_RX_RING_SIZE
;
4631 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4634 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
4635 sw_idx
= tpr
->rx_jmb_ptr
% TG3_RX_JUMBO_RING_SIZE
;
4636 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
4644 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
4646 struct tg3
*tp
= tnapi
->tp
;
4647 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4649 /* handle link change and other phy events */
4650 if (!(tp
->tg3_flags
&
4651 (TG3_FLAG_USE_LINKCHG_REG
|
4652 TG3_FLAG_POLL_SERDES
))) {
4653 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
4654 sblk
->status
= SD_STATUS_UPDATED
|
4655 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
4656 spin_lock(&tp
->lock
);
4657 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
4659 (MAC_STATUS_SYNC_CHANGED
|
4660 MAC_STATUS_CFG_CHANGED
|
4661 MAC_STATUS_MI_COMPLETION
|
4662 MAC_STATUS_LNKSTATE_CHANGED
));
4665 tg3_setup_phy(tp
, 0);
4666 spin_unlock(&tp
->lock
);
4670 /* run TX completion thread */
4671 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
4673 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4677 /* run RX thread, within the bounds set by NAPI.
4678 * All RX "locking" is done by ensuring outside
4679 * code synchronizes with tg3->napi.poll()
4681 if (sblk
->idx
[0].rx_producer
!= tnapi
->rx_rcb_ptr
)
4682 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
4687 static int tg3_poll(struct napi_struct
*napi
, int budget
)
4689 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
4690 struct tg3
*tp
= tnapi
->tp
;
4692 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4695 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
4697 if (unlikely(tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
))
4700 if (unlikely(work_done
>= budget
))
4703 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
4704 /* tp->last_tag is used in tg3_int_reenable() below
4705 * to tell the hw how much work has been processed,
4706 * so we must read it before checking for more work.
4708 tnapi
->last_tag
= sblk
->status_tag
;
4709 tnapi
->last_irq_tag
= tnapi
->last_tag
;
4712 sblk
->status
&= ~SD_STATUS_UPDATED
;
4714 if (likely(!tg3_has_work(tnapi
))) {
4715 napi_complete(napi
);
4716 tg3_int_reenable(tnapi
);
4724 /* work_done is guaranteed to be less than budget. */
4725 napi_complete(napi
);
4726 schedule_work(&tp
->reset_task
);
4730 static void tg3_irq_quiesce(struct tg3
*tp
)
4734 BUG_ON(tp
->irq_sync
);
4739 for (i
= 0; i
< tp
->irq_cnt
; i
++)
4740 synchronize_irq(tp
->napi
[i
].irq_vec
);
4743 static inline int tg3_irq_sync(struct tg3
*tp
)
4745 return tp
->irq_sync
;
4748 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4749 * If irq_sync is non-zero, then the IRQ handler must be synchronized
4750 * with as well. Most of the time, this is not necessary except when
4751 * shutting down the device.
4753 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
4755 spin_lock_bh(&tp
->lock
);
4757 tg3_irq_quiesce(tp
);
4760 static inline void tg3_full_unlock(struct tg3
*tp
)
4762 spin_unlock_bh(&tp
->lock
);
4765 /* One-shot MSI handler - Chip automatically disables interrupt
4766 * after sending MSI so driver doesn't have to do it.
4768 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
4770 struct tg3_napi
*tnapi
= dev_id
;
4771 struct tg3
*tp
= tnapi
->tp
;
4773 prefetch(tnapi
->hw_status
);
4774 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4776 if (likely(!tg3_irq_sync(tp
)))
4777 napi_schedule(&tnapi
->napi
);
4782 /* MSI ISR - No need to check for interrupt sharing and no need to
4783 * flush status block and interrupt mailbox. PCI ordering rules
4784 * guarantee that MSI will arrive after the status block.
4786 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
4788 struct tg3_napi
*tnapi
= dev_id
;
4789 struct tg3
*tp
= tnapi
->tp
;
4791 prefetch(tnapi
->hw_status
);
4792 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4794 * Writing any value to intr-mbox-0 clears PCI INTA# and
4795 * chip-internal interrupt pending events.
4796 * Writing non-zero to intr-mbox-0 additional tells the
4797 * NIC to stop sending us irqs, engaging "in-intr-handler"
4800 tw32_mailbox(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4801 if (likely(!tg3_irq_sync(tp
)))
4802 napi_schedule(&tnapi
->napi
);
4804 return IRQ_RETVAL(1);
4807 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
4809 struct tg3_napi
*tnapi
= dev_id
;
4810 struct tg3
*tp
= tnapi
->tp
;
4811 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4812 unsigned int handled
= 1;
4814 /* In INTx mode, it is possible for the interrupt to arrive at
4815 * the CPU before the status block posted prior to the interrupt.
4816 * Reading the PCI State register will confirm whether the
4817 * interrupt is ours and will flush the status block.
4819 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
4820 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4821 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4828 * Writing any value to intr-mbox-0 clears PCI INTA# and
4829 * chip-internal interrupt pending events.
4830 * Writing non-zero to intr-mbox-0 additional tells the
4831 * NIC to stop sending us irqs, engaging "in-intr-handler"
4834 * Flush the mailbox to de-assert the IRQ immediately to prevent
4835 * spurious interrupts. The flush impacts performance but
4836 * excessive spurious interrupts can be worse in some cases.
4838 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4839 if (tg3_irq_sync(tp
))
4841 sblk
->status
&= ~SD_STATUS_UPDATED
;
4842 if (likely(tg3_has_work(tnapi
))) {
4843 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4844 napi_schedule(&tnapi
->napi
);
4846 /* No work, shared interrupt perhaps? re-enable
4847 * interrupts, and flush that PCI write
4849 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
4853 return IRQ_RETVAL(handled
);
4856 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
4858 struct tg3_napi
*tnapi
= dev_id
;
4859 struct tg3
*tp
= tnapi
->tp
;
4860 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4861 unsigned int handled
= 1;
4863 /* In INTx mode, it is possible for the interrupt to arrive at
4864 * the CPU before the status block posted prior to the interrupt.
4865 * Reading the PCI State register will confirm whether the
4866 * interrupt is ours and will flush the status block.
4868 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
4869 if ((tp
->tg3_flags
& TG3_FLAG_CHIP_RESETTING
) ||
4870 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4877 * writing any value to intr-mbox-0 clears PCI INTA# and
4878 * chip-internal interrupt pending events.
4879 * writing non-zero to intr-mbox-0 additional tells the
4880 * NIC to stop sending us irqs, engaging "in-intr-handler"
4883 * Flush the mailbox to de-assert the IRQ immediately to prevent
4884 * spurious interrupts. The flush impacts performance but
4885 * excessive spurious interrupts can be worse in some cases.
4887 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
4890 * In a shared interrupt configuration, sometimes other devices'
4891 * interrupts will scream. We record the current status tag here
4892 * so that the above check can report that the screaming interrupts
4893 * are unhandled. Eventually they will be silenced.
4895 tnapi
->last_irq_tag
= sblk
->status_tag
;
4897 if (tg3_irq_sync(tp
))
4900 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
4902 napi_schedule(&tnapi
->napi
);
4905 return IRQ_RETVAL(handled
);
4908 /* ISR for interrupt test */
4909 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
4911 struct tg3_napi
*tnapi
= dev_id
;
4912 struct tg3
*tp
= tnapi
->tp
;
4913 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
4915 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
4916 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
4917 tg3_disable_ints(tp
);
4918 return IRQ_RETVAL(1);
4920 return IRQ_RETVAL(0);
4923 static int tg3_init_hw(struct tg3
*, int);
4924 static int tg3_halt(struct tg3
*, int, int);
4926 /* Restart hardware after configuration changes, self-test, etc.
4927 * Invoked with tp->lock held.
4929 static int tg3_restart_hw(struct tg3
*tp
, int reset_phy
)
4930 __releases(tp
->lock
)
4931 __acquires(tp
->lock
)
4935 err
= tg3_init_hw(tp
, reset_phy
);
4937 printk(KERN_ERR PFX
"%s: Failed to re-initialize device, "
4938 "aborting.\n", tp
->dev
->name
);
4939 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
4940 tg3_full_unlock(tp
);
4941 del_timer_sync(&tp
->timer
);
4943 napi_enable(&tp
->napi
[0].napi
);
4945 tg3_full_lock(tp
, 0);
4950 #ifdef CONFIG_NET_POLL_CONTROLLER
4951 static void tg3_poll_controller(struct net_device
*dev
)
4954 struct tg3
*tp
= netdev_priv(dev
);
4956 for (i
= 0; i
< tp
->irq_cnt
; i
++)
4957 tg3_interrupt(tp
->napi
[i
].irq_vec
, dev
);
4961 static void tg3_reset_task(struct work_struct
*work
)
4963 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
4965 unsigned int restart_timer
;
4967 tg3_full_lock(tp
, 0);
4969 if (!netif_running(tp
->dev
)) {
4970 tg3_full_unlock(tp
);
4974 tg3_full_unlock(tp
);
4980 tg3_full_lock(tp
, 1);
4982 restart_timer
= tp
->tg3_flags2
& TG3_FLG2_RESTART_TIMER
;
4983 tp
->tg3_flags2
&= ~TG3_FLG2_RESTART_TIMER
;
4985 if (tp
->tg3_flags
& TG3_FLAG_TX_RECOVERY_PENDING
) {
4986 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
4987 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
4988 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
4989 tp
->tg3_flags
&= ~TG3_FLAG_TX_RECOVERY_PENDING
;
4992 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
4993 err
= tg3_init_hw(tp
, 1);
4997 tg3_netif_start(tp
);
5000 mod_timer(&tp
->timer
, jiffies
+ 1);
5003 tg3_full_unlock(tp
);
5009 static void tg3_dump_short_state(struct tg3
*tp
)
5011 printk(KERN_ERR PFX
"DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5012 tr32(MAC_TX_STATUS
), tr32(MAC_RX_STATUS
));
5013 printk(KERN_ERR PFX
"DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5014 tr32(RDMAC_STATUS
), tr32(WDMAC_STATUS
));
5017 static void tg3_tx_timeout(struct net_device
*dev
)
5019 struct tg3
*tp
= netdev_priv(dev
);
5021 if (netif_msg_tx_err(tp
)) {
5022 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
5024 tg3_dump_short_state(tp
);
5027 schedule_work(&tp
->reset_task
);
5030 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5031 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
5033 u32 base
= (u32
) mapping
& 0xffffffff;
5035 return ((base
> 0xffffdcc0) &&
5036 (base
+ len
+ 8 < base
));
5039 /* Test for DMA addresses > 40-bit */
5040 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
5043 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5044 if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
)
5045 return (((u64
) mapping
+ len
) > DMA_BIT_MASK(40));
5052 static void tg3_set_txd(struct tg3_napi
*, int, dma_addr_t
, int, u32
, u32
);
5054 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5055 static int tigon3_dma_hwbug_workaround(struct tg3
*tp
, struct sk_buff
*skb
,
5056 u32 last_plus_one
, u32
*start
,
5057 u32 base_flags
, u32 mss
)
5059 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5060 struct sk_buff
*new_skb
;
5061 dma_addr_t new_addr
= 0;
5065 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
5066 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
5068 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
5070 new_skb
= skb_copy_expand(skb
,
5071 skb_headroom(skb
) + more_headroom
,
5072 skb_tailroom(skb
), GFP_ATOMIC
);
5078 /* New SKB is guaranteed to be linear. */
5080 ret
= skb_dma_map(&tp
->pdev
->dev
, new_skb
, DMA_TO_DEVICE
);
5081 new_addr
= skb_shinfo(new_skb
)->dma_head
;
5083 /* Make sure new skb does not cross any 4G boundaries.
5084 * Drop the packet if it does.
5086 if (ret
|| tg3_4g_overflow_test(new_addr
, new_skb
->len
)) {
5088 skb_dma_unmap(&tp
->pdev
->dev
, new_skb
,
5091 dev_kfree_skb(new_skb
);
5094 tg3_set_txd(tnapi
, entry
, new_addr
, new_skb
->len
,
5095 base_flags
, 1 | (mss
<< 1));
5096 *start
= NEXT_TX(entry
);
5100 /* Now clean up the sw ring entries. */
5102 while (entry
!= last_plus_one
) {
5104 tnapi
->tx_buffers
[entry
].skb
= new_skb
;
5106 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5107 entry
= NEXT_TX(entry
);
5111 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5117 static void tg3_set_txd(struct tg3_napi
*tnapi
, int entry
,
5118 dma_addr_t mapping
, int len
, u32 flags
,
5121 struct tg3_tx_buffer_desc
*txd
= &tnapi
->tx_ring
[entry
];
5122 int is_end
= (mss_and_is_end
& 0x1);
5123 u32 mss
= (mss_and_is_end
>> 1);
5127 flags
|= TXD_FLAG_END
;
5128 if (flags
& TXD_FLAG_VLAN
) {
5129 vlan_tag
= flags
>> 16;
5132 vlan_tag
|= (mss
<< TXD_MSS_SHIFT
);
5134 txd
->addr_hi
= ((u64
) mapping
>> 32);
5135 txd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
5136 txd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | flags
;
5137 txd
->vlan_tag
= vlan_tag
<< TXD_VLAN_TAG_SHIFT
;
5140 /* hard_start_xmit for devices that don't have any bugs and
5141 * support TG3_FLG2_HW_TSO_2 only.
5143 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
,
5144 struct net_device
*dev
)
5146 struct tg3
*tp
= netdev_priv(dev
);
5147 u32 len
, entry
, base_flags
, mss
;
5148 struct skb_shared_info
*sp
;
5150 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5152 len
= skb_headlen(skb
);
5154 /* We are running in BH disabled context with netif_tx_lock
5155 * and TX reclaim runs via tp->napi.poll inside of a software
5156 * interrupt. Furthermore, IRQ processing runs lockless so we have
5157 * no IRQ context deadlocks to worry about either. Rejoice!
5159 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5160 if (!netif_queue_stopped(dev
)) {
5161 netif_stop_queue(dev
);
5163 /* This is a hard error, log it. */
5164 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5165 "queue awake!\n", dev
->name
);
5167 return NETDEV_TX_BUSY
;
5170 entry
= tnapi
->tx_prod
;
5173 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5174 int tcp_opt_len
, ip_tcp_len
;
5176 if (skb_header_cloned(skb
) &&
5177 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5182 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
)
5183 mss
|= (skb_headlen(skb
) - ETH_HLEN
) << 9;
5185 struct iphdr
*iph
= ip_hdr(skb
);
5187 tcp_opt_len
= tcp_optlen(skb
);
5188 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5191 iph
->tot_len
= htons(mss
+ ip_tcp_len
+ tcp_opt_len
);
5192 mss
|= (ip_tcp_len
+ tcp_opt_len
) << 9;
5195 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5196 TXD_FLAG_CPU_POST_DMA
);
5198 tcp_hdr(skb
)->check
= 0;
5201 else if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5202 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5203 #if TG3_VLAN_TAG_USED
5204 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5205 base_flags
|= (TXD_FLAG_VLAN
|
5206 (vlan_tx_tag_get(skb
) << 16));
5209 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5214 sp
= skb_shinfo(skb
);
5216 mapping
= sp
->dma_head
;
5218 tnapi
->tx_buffers
[entry
].skb
= skb
;
5220 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5221 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5223 entry
= NEXT_TX(entry
);
5225 /* Now loop through additional data fragments, and queue them. */
5226 if (skb_shinfo(skb
)->nr_frags
> 0) {
5227 unsigned int i
, last
;
5229 last
= skb_shinfo(skb
)->nr_frags
- 1;
5230 for (i
= 0; i
<= last
; i
++) {
5231 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5234 mapping
= sp
->dma_maps
[i
];
5235 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5237 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5238 base_flags
, (i
== last
) | (mss
<< 1));
5240 entry
= NEXT_TX(entry
);
5244 /* Packets are ready, update Tx producer idx local and on card. */
5245 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
5247 tnapi
->tx_prod
= entry
;
5248 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5249 netif_stop_queue(dev
);
5250 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5251 netif_wake_queue(tp
->dev
);
5257 return NETDEV_TX_OK
;
5260 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*,
5261 struct net_device
*);
5263 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5264 * TSO header is greater than 80 bytes.
5266 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
5268 struct sk_buff
*segs
, *nskb
;
5269 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
5271 /* Estimate the number of fragments in the worst case */
5272 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
5273 netif_stop_queue(tp
->dev
);
5274 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
5275 return NETDEV_TX_BUSY
;
5277 netif_wake_queue(tp
->dev
);
5280 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
5282 goto tg3_tso_bug_end
;
5288 tg3_start_xmit_dma_bug(nskb
, tp
->dev
);
5294 return NETDEV_TX_OK
;
5297 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5298 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5300 static netdev_tx_t
tg3_start_xmit_dma_bug(struct sk_buff
*skb
,
5301 struct net_device
*dev
)
5303 struct tg3
*tp
= netdev_priv(dev
);
5304 u32 len
, entry
, base_flags
, mss
;
5305 struct skb_shared_info
*sp
;
5306 int would_hit_hwbug
;
5308 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5310 len
= skb_headlen(skb
);
5312 /* We are running in BH disabled context with netif_tx_lock
5313 * and TX reclaim runs via tp->napi.poll inside of a software
5314 * interrupt. Furthermore, IRQ processing runs lockless so we have
5315 * no IRQ context deadlocks to worry about either. Rejoice!
5317 if (unlikely(tg3_tx_avail(tnapi
) <= (skb_shinfo(skb
)->nr_frags
+ 1))) {
5318 if (!netif_queue_stopped(dev
)) {
5319 netif_stop_queue(dev
);
5321 /* This is a hard error, log it. */
5322 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when "
5323 "queue awake!\n", dev
->name
);
5325 return NETDEV_TX_BUSY
;
5328 entry
= tnapi
->tx_prod
;
5330 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5331 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
5333 if ((mss
= skb_shinfo(skb
)->gso_size
) != 0) {
5335 int tcp_opt_len
, ip_tcp_len
, hdr_len
;
5337 if (skb_header_cloned(skb
) &&
5338 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
)) {
5343 tcp_opt_len
= tcp_optlen(skb
);
5344 ip_tcp_len
= ip_hdrlen(skb
) + sizeof(struct tcphdr
);
5346 hdr_len
= ip_tcp_len
+ tcp_opt_len
;
5347 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
5348 (tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
))
5349 return (tg3_tso_bug(tp
, skb
));
5351 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
5352 TXD_FLAG_CPU_POST_DMA
);
5356 iph
->tot_len
= htons(mss
+ hdr_len
);
5357 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
5358 tcp_hdr(skb
)->check
= 0;
5359 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
5361 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5366 if ((tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) ||
5367 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)) {
5368 if (tcp_opt_len
|| iph
->ihl
> 5) {
5371 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5372 mss
|= (tsflags
<< 11);
5375 if (tcp_opt_len
|| iph
->ihl
> 5) {
5378 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
5379 base_flags
|= tsflags
<< 12;
5383 #if TG3_VLAN_TAG_USED
5384 if (tp
->vlgrp
!= NULL
&& vlan_tx_tag_present(skb
))
5385 base_flags
|= (TXD_FLAG_VLAN
|
5386 (vlan_tx_tag_get(skb
) << 16));
5389 if (skb_dma_map(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5394 sp
= skb_shinfo(skb
);
5396 mapping
= sp
->dma_head
;
5398 tnapi
->tx_buffers
[entry
].skb
= skb
;
5400 would_hit_hwbug
= 0;
5402 if (tp
->tg3_flags3
& TG3_FLG3_5701_DMA_BUG
)
5403 would_hit_hwbug
= 1;
5404 else if (tg3_4g_overflow_test(mapping
, len
))
5405 would_hit_hwbug
= 1;
5407 tg3_set_txd(tnapi
, entry
, mapping
, len
, base_flags
,
5408 (skb_shinfo(skb
)->nr_frags
== 0) | (mss
<< 1));
5410 entry
= NEXT_TX(entry
);
5412 /* Now loop through additional data fragments, and queue them. */
5413 if (skb_shinfo(skb
)->nr_frags
> 0) {
5414 unsigned int i
, last
;
5416 last
= skb_shinfo(skb
)->nr_frags
- 1;
5417 for (i
= 0; i
<= last
; i
++) {
5418 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
5421 mapping
= sp
->dma_maps
[i
];
5423 tnapi
->tx_buffers
[entry
].skb
= NULL
;
5425 if (tg3_4g_overflow_test(mapping
, len
))
5426 would_hit_hwbug
= 1;
5428 if (tg3_40bit_overflow_test(tp
, mapping
, len
))
5429 would_hit_hwbug
= 1;
5431 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
5432 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5433 base_flags
, (i
== last
)|(mss
<< 1));
5435 tg3_set_txd(tnapi
, entry
, mapping
, len
,
5436 base_flags
, (i
== last
));
5438 entry
= NEXT_TX(entry
);
5442 if (would_hit_hwbug
) {
5443 u32 last_plus_one
= entry
;
5446 start
= entry
- 1 - skb_shinfo(skb
)->nr_frags
;
5447 start
&= (TG3_TX_RING_SIZE
- 1);
5449 /* If the workaround fails due to memory/mapping
5450 * failure, silently drop this packet.
5452 if (tigon3_dma_hwbug_workaround(tp
, skb
, last_plus_one
,
5453 &start
, base_flags
, mss
))
5459 /* Packets are ready, update Tx producer idx local and on card. */
5460 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
, entry
);
5462 tnapi
->tx_prod
= entry
;
5463 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
5464 netif_stop_queue(dev
);
5465 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
5466 netif_wake_queue(tp
->dev
);
5472 return NETDEV_TX_OK
;
5475 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
5480 if (new_mtu
> ETH_DATA_LEN
) {
5481 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
5482 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
5483 ethtool_op_set_tso(dev
, 0);
5486 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
5488 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
5489 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
5490 tp
->tg3_flags
&= ~TG3_FLAG_JUMBO_RING_ENABLE
;
5494 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
5496 struct tg3
*tp
= netdev_priv(dev
);
5499 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
5502 if (!netif_running(dev
)) {
5503 /* We'll just catch it later when the
5506 tg3_set_mtu(dev
, tp
, new_mtu
);
5514 tg3_full_lock(tp
, 1);
5516 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
5518 tg3_set_mtu(dev
, tp
, new_mtu
);
5520 err
= tg3_restart_hw(tp
, 0);
5523 tg3_netif_start(tp
);
5525 tg3_full_unlock(tp
);
5533 static void tg3_rx_prodring_free(struct tg3
*tp
,
5534 struct tg3_rx_prodring_set
*tpr
)
5537 struct ring_info
*rxp
;
5539 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5540 rxp
= &tpr
->rx_std_buffers
[i
];
5542 if (rxp
->skb
== NULL
)
5545 pci_unmap_single(tp
->pdev
,
5546 pci_unmap_addr(rxp
, mapping
),
5548 PCI_DMA_FROMDEVICE
);
5549 dev_kfree_skb_any(rxp
->skb
);
5553 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5554 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5555 rxp
= &tpr
->rx_jmb_buffers
[i
];
5557 if (rxp
->skb
== NULL
)
5560 pci_unmap_single(tp
->pdev
,
5561 pci_unmap_addr(rxp
, mapping
),
5563 PCI_DMA_FROMDEVICE
);
5564 dev_kfree_skb_any(rxp
->skb
);
5570 /* Initialize tx/rx rings for packet processing.
5572 * The chip has been shut down and the driver detached from
5573 * the networking, so no interrupts or new tx packets will
5574 * end up in the driver. tp->{tx,}lock are held and thus
5577 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
5578 struct tg3_rx_prodring_set
*tpr
)
5580 u32 i
, rx_pkt_dma_sz
;
5581 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5583 /* Zero out all descriptors. */
5584 memset(tpr
->rx_std
, 0, TG3_RX_RING_BYTES
);
5586 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
5587 if ((tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) &&
5588 tp
->dev
->mtu
> ETH_DATA_LEN
)
5589 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
5590 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
5592 /* Initialize invariants of the rings, we only set this
5593 * stuff once. This works because the card does not
5594 * write into the rx buffer posting rings.
5596 for (i
= 0; i
< TG3_RX_RING_SIZE
; i
++) {
5597 struct tg3_rx_buffer_desc
*rxd
;
5599 rxd
= &tpr
->rx_std
[i
];
5600 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
5601 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
5602 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
5603 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5606 /* Now allocate fresh SKBs for each rx ring. */
5607 for (i
= 0; i
< tp
->rx_pending
; i
++) {
5608 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_STD
, -1, i
) < 0) {
5609 printk(KERN_WARNING PFX
5610 "%s: Using a smaller RX standard ring, "
5611 "only %d out of %d buffers were allocated "
5613 tp
->dev
->name
, i
, tp
->rx_pending
);
5621 if (!(tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
))
5624 memset(tpr
->rx_jmb
, 0, TG3_RX_JUMBO_RING_BYTES
);
5626 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
5627 for (i
= 0; i
< TG3_RX_JUMBO_RING_SIZE
; i
++) {
5628 struct tg3_rx_buffer_desc
*rxd
;
5630 rxd
= &tpr
->rx_jmb
[i
].std
;
5631 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
5632 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
5634 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
5635 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
5638 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
5639 if (tg3_alloc_rx_skb(tnapi
, RXD_OPAQUE_RING_JUMBO
,
5641 printk(KERN_WARNING PFX
5642 "%s: Using a smaller RX jumbo ring, "
5643 "only %d out of %d buffers were "
5644 "allocated successfully.\n",
5645 tp
->dev
->name
, i
, tp
->rx_jumbo_pending
);
5648 tp
->rx_jumbo_pending
= i
;
5658 tg3_rx_prodring_free(tp
, tpr
);
5662 static void tg3_rx_prodring_fini(struct tg3
*tp
,
5663 struct tg3_rx_prodring_set
*tpr
)
5665 kfree(tpr
->rx_std_buffers
);
5666 tpr
->rx_std_buffers
= NULL
;
5667 kfree(tpr
->rx_jmb_buffers
);
5668 tpr
->rx_jmb_buffers
= NULL
;
5670 pci_free_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5671 tpr
->rx_std
, tpr
->rx_std_mapping
);
5675 pci_free_consistent(tp
->pdev
, TG3_RX_JUMBO_RING_BYTES
,
5676 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
5681 static int tg3_rx_prodring_init(struct tg3
*tp
,
5682 struct tg3_rx_prodring_set
*tpr
)
5684 tpr
->rx_std_buffers
= kzalloc(sizeof(struct ring_info
) *
5685 TG3_RX_RING_SIZE
, GFP_KERNEL
);
5686 if (!tpr
->rx_std_buffers
)
5689 tpr
->rx_std
= pci_alloc_consistent(tp
->pdev
, TG3_RX_RING_BYTES
,
5690 &tpr
->rx_std_mapping
);
5694 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) {
5695 tpr
->rx_jmb_buffers
= kzalloc(sizeof(struct ring_info
) *
5696 TG3_RX_JUMBO_RING_SIZE
,
5698 if (!tpr
->rx_jmb_buffers
)
5701 tpr
->rx_jmb
= pci_alloc_consistent(tp
->pdev
,
5702 TG3_RX_JUMBO_RING_BYTES
,
5703 &tpr
->rx_jmb_mapping
);
5711 tg3_rx_prodring_fini(tp
, tpr
);
5715 /* Free up pending packets in all rx/tx rings.
5717 * The chip has been shut down and the driver detached from
5718 * the networking, so no interrupts or new tx packets will
5719 * end up in the driver. tp->{tx,}lock is not held and we are not
5720 * in an interrupt context and thus may sleep.
5722 static void tg3_free_rings(struct tg3
*tp
)
5724 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5727 for (i
= 0; i
< TG3_TX_RING_SIZE
; ) {
5728 struct tx_ring_info
*txp
;
5729 struct sk_buff
*skb
;
5731 txp
= &tnapi
->tx_buffers
[i
];
5739 skb_dma_unmap(&tp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5743 i
+= skb_shinfo(skb
)->nr_frags
+ 1;
5745 dev_kfree_skb_any(skb
);
5748 tg3_rx_prodring_free(tp
, &tp
->prodring
[0]);
5751 /* Initialize tx/rx rings for packet processing.
5753 * The chip has been shut down and the driver detached from
5754 * the networking, so no interrupts or new tx packets will
5755 * end up in the driver. tp->{tx,}lock are held and thus
5758 static int tg3_init_rings(struct tg3
*tp
)
5760 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5762 /* Free up all the SKBs. */
5765 /* Zero out all descriptors. */
5766 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
5768 tnapi
->rx_rcb_ptr
= 0;
5769 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5771 return tg3_rx_prodring_alloc(tp
, &tp
->prodring
[0]);
5775 * Must not be invoked with interrupt sources disabled and
5776 * the hardware shutdown down.
5778 static void tg3_free_consistent(struct tg3
*tp
)
5780 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5782 kfree(tnapi
->tx_buffers
);
5783 tnapi
->tx_buffers
= NULL
;
5784 if (tnapi
->tx_ring
) {
5785 pci_free_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5786 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
5787 tnapi
->tx_ring
= NULL
;
5789 if (tnapi
->rx_rcb
) {
5790 pci_free_consistent(tp
->pdev
, TG3_RX_RCB_RING_BYTES(tp
),
5791 tnapi
->rx_rcb
, tnapi
->rx_rcb_mapping
);
5792 tnapi
->rx_rcb
= NULL
;
5794 if (tnapi
->hw_status
) {
5795 pci_free_consistent(tp
->pdev
, TG3_HW_STATUS_SIZE
,
5797 tnapi
->status_mapping
);
5798 tnapi
->hw_status
= NULL
;
5801 pci_free_consistent(tp
->pdev
, sizeof(struct tg3_hw_stats
),
5802 tp
->hw_stats
, tp
->stats_mapping
);
5803 tp
->hw_stats
= NULL
;
5805 tg3_rx_prodring_fini(tp
, &tp
->prodring
[0]);
5809 * Must not be invoked with interrupt sources disabled and
5810 * the hardware shutdown down. Can sleep.
5812 static int tg3_alloc_consistent(struct tg3
*tp
)
5814 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5816 if (tg3_rx_prodring_init(tp
, &tp
->prodring
[0]))
5819 tnapi
->tx_buffers
= kzalloc(sizeof(struct tx_ring_info
) *
5820 TG3_TX_RING_SIZE
, GFP_KERNEL
);
5821 if (!tnapi
->tx_buffers
)
5824 tnapi
->tx_ring
= pci_alloc_consistent(tp
->pdev
, TG3_TX_RING_BYTES
,
5825 &tnapi
->tx_desc_mapping
);
5826 if (!tnapi
->tx_ring
)
5829 tnapi
->hw_status
= pci_alloc_consistent(tp
->pdev
,
5831 &tnapi
->status_mapping
);
5832 if (!tnapi
->hw_status
)
5835 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5837 tnapi
->rx_rcb
= pci_alloc_consistent(tp
->pdev
,
5838 TG3_RX_RCB_RING_BYTES(tp
),
5839 &tnapi
->rx_rcb_mapping
);
5843 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
5845 tp
->hw_stats
= pci_alloc_consistent(tp
->pdev
,
5846 sizeof(struct tg3_hw_stats
),
5847 &tp
->stats_mapping
);
5851 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5856 tg3_free_consistent(tp
);
5860 #define MAX_WAIT_CNT 1000
5862 /* To stop a block, clear the enable bit and poll till it
5863 * clears. tp->lock is held.
5865 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, int silent
)
5870 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
5877 /* We can't enable/disable these bits of the
5878 * 5705/5750, just say success.
5891 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5894 if ((val
& enable_bit
) == 0)
5898 if (i
== MAX_WAIT_CNT
&& !silent
) {
5899 printk(KERN_ERR PFX
"tg3_stop_block timed out, "
5900 "ofs=%lx enable_bit=%x\n",
5908 /* tp->lock is held. */
5909 static int tg3_abort_hw(struct tg3
*tp
, int silent
)
5912 struct tg3_napi
*tnapi
= &tp
->napi
[0];
5914 tg3_disable_ints(tp
);
5916 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
5917 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
5920 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
5921 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
5922 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
5923 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
5924 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
5925 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
5927 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
5928 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
5929 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
5930 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
5931 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
5932 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
5933 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
5935 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
5936 tw32_f(MAC_MODE
, tp
->mac_mode
);
5939 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
5940 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
5942 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
5944 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
5947 if (i
>= MAX_WAIT_CNT
) {
5948 printk(KERN_ERR PFX
"tg3_abort_hw timed out for %s, "
5949 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5950 tp
->dev
->name
, tr32(MAC_TX_MODE
));
5954 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
5955 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
5956 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
5958 tw32(FTQ_RESET
, 0xffffffff);
5959 tw32(FTQ_RESET
, 0x00000000);
5961 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
5962 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
5964 if (tnapi
->hw_status
)
5965 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
5967 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
5972 static void tg3_ape_send_event(struct tg3
*tp
, u32 event
)
5977 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
5978 if (apedata
!= APE_SEG_SIG_MAGIC
)
5981 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
5982 if (!(apedata
& APE_FW_STATUS_READY
))
5985 /* Wait for up to 1 millisecond for APE to service previous event. */
5986 for (i
= 0; i
< 10; i
++) {
5987 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
5990 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
5992 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
5993 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
5994 event
| APE_EVENT_STATUS_EVENT_PENDING
);
5996 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
5998 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6004 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
6005 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
6008 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
6013 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
6017 case RESET_KIND_INIT
:
6018 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
6019 APE_HOST_SEG_SIG_MAGIC
);
6020 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
6021 APE_HOST_SEG_LEN_MAGIC
);
6022 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
6023 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
6024 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
6025 APE_HOST_DRIVER_ID_MAGIC
);
6026 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
6027 APE_HOST_BEHAV_NO_PHYLOCK
);
6029 event
= APE_EVENT_STATUS_STATE_START
;
6031 case RESET_KIND_SHUTDOWN
:
6032 /* With the interface we are currently using,
6033 * APE does not track driver state. Wiping
6034 * out the HOST SEGMENT SIGNATURE forces
6035 * the APE to assume OS absent status.
6037 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
6039 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
6041 case RESET_KIND_SUSPEND
:
6042 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
6048 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
6050 tg3_ape_send_event(tp
, event
);
6053 /* tp->lock is held. */
6054 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
6056 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
6057 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
6059 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6061 case RESET_KIND_INIT
:
6062 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6066 case RESET_KIND_SHUTDOWN
:
6067 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6071 case RESET_KIND_SUSPEND
:
6072 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6081 if (kind
== RESET_KIND_INIT
||
6082 kind
== RESET_KIND_SUSPEND
)
6083 tg3_ape_driver_state_change(tp
, kind
);
6086 /* tp->lock is held. */
6087 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
6089 if (tp
->tg3_flags2
& TG3_FLG2_ASF_NEW_HANDSHAKE
) {
6091 case RESET_KIND_INIT
:
6092 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6093 DRV_STATE_START_DONE
);
6096 case RESET_KIND_SHUTDOWN
:
6097 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6098 DRV_STATE_UNLOAD_DONE
);
6106 if (kind
== RESET_KIND_SHUTDOWN
)
6107 tg3_ape_driver_state_change(tp
, kind
);
6110 /* tp->lock is held. */
6111 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
6113 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6115 case RESET_KIND_INIT
:
6116 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6120 case RESET_KIND_SHUTDOWN
:
6121 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6125 case RESET_KIND_SUSPEND
:
6126 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
6136 static int tg3_poll_fw(struct tg3
*tp
)
6141 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6142 /* Wait up to 20ms for init done. */
6143 for (i
= 0; i
< 200; i
++) {
6144 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
6151 /* Wait for firmware initialization to complete. */
6152 for (i
= 0; i
< 100000; i
++) {
6153 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
6154 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
6159 /* Chip might not be fitted with firmware. Some Sun onboard
6160 * parts are configured like that. So don't signal the timeout
6161 * of the above loop as an error, but do report the lack of
6162 * running firmware once.
6165 !(tp
->tg3_flags2
& TG3_FLG2_NO_FWARE_REPORTED
)) {
6166 tp
->tg3_flags2
|= TG3_FLG2_NO_FWARE_REPORTED
;
6168 printk(KERN_INFO PFX
"%s: No firmware running.\n",
6175 /* Save PCI command register before chip reset */
6176 static void tg3_save_pci_state(struct tg3
*tp
)
6178 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
6181 /* Restore PCI state after chip reset */
6182 static void tg3_restore_pci_state(struct tg3
*tp
)
6186 /* Re-enable indirect register accesses. */
6187 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
6188 tp
->misc_host_ctrl
);
6190 /* Set MAX PCI retry to zero. */
6191 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
6192 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6193 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
))
6194 val
|= PCISTATE_RETRY_SAME_DMA
;
6195 /* Allow reads and writes to the APE register and memory space. */
6196 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
6197 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6198 PCISTATE_ALLOW_APE_SHMEM_WR
;
6199 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
6201 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
6203 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
) {
6204 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
6205 pcie_set_readrq(tp
->pdev
, 4096);
6207 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
6208 tp
->pci_cacheline_sz
);
6209 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
6214 /* Make sure PCI-X relaxed ordering bit is clear. */
6215 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
6218 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6220 pcix_cmd
&= ~PCI_X_CMD_ERO
;
6221 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
6225 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
) {
6227 /* Chip reset on 5780 will reset MSI enable bit,
6228 * so need to restore it.
6230 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
6233 pci_read_config_word(tp
->pdev
,
6234 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6236 pci_write_config_word(tp
->pdev
,
6237 tp
->msi_cap
+ PCI_MSI_FLAGS
,
6238 ctrl
| PCI_MSI_FLAGS_ENABLE
);
6239 val
= tr32(MSGINT_MODE
);
6240 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
6245 static void tg3_stop_fw(struct tg3
*);
6247 /* tp->lock is held. */
6248 static int tg3_chip_reset(struct tg3
*tp
)
6251 void (*write_op
)(struct tg3
*, u32
, u32
);
6258 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
6260 /* No matching tg3_nvram_unlock() after this because
6261 * chip reset below will undo the nvram lock.
6263 tp
->nvram_lock_cnt
= 0;
6265 /* GRC_MISC_CFG core clock reset will clear the memory
6266 * enable bit in PCI register 4 and the MSI enable bit
6267 * on some chips, so we save relevant registers here.
6269 tg3_save_pci_state(tp
);
6271 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
6272 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
))
6273 tw32(GRC_FASTBOOT_PC
, 0);
6276 * We must avoid the readl() that normally takes place.
6277 * It locks machines, causes machine checks, and other
6278 * fun things. So, temporarily disable the 5701
6279 * hardware workaround, while we do the reset.
6281 write_op
= tp
->write32
;
6282 if (write_op
== tg3_write_flush_reg32
)
6283 tp
->write32
= tg3_write32
;
6285 /* Prevent the irq handler from reading or writing PCI registers
6286 * during chip reset when the memory enable bit in the PCI command
6287 * register may be cleared. The chip does not generate interrupt
6288 * at this time, but the irq handler may still be called due to irq
6289 * sharing or irqpoll.
6291 tp
->tg3_flags
|= TG3_FLAG_CHIP_RESETTING
;
6292 if (tp
->napi
[0].hw_status
) {
6293 tp
->napi
[0].hw_status
->status
= 0;
6294 tp
->napi
[0].hw_status
->status_tag
= 0;
6296 tp
->napi
[0].last_tag
= 0;
6297 tp
->napi
[0].last_irq_tag
= 0;
6300 for (i
= 0; i
< tp
->irq_cnt
; i
++)
6301 synchronize_irq(tp
->napi
[i
].irq_vec
);
6303 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6304 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
6305 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
6309 val
= GRC_MISC_CFG_CORECLK_RESET
;
6311 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
6312 if (tr32(0x7e2c) == 0x60) {
6315 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6316 tw32(GRC_MISC_CFG
, (1 << 29));
6321 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6322 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
6323 tw32(GRC_VCPU_EXT_CTRL
,
6324 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
6327 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6328 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
6329 tw32(GRC_MISC_CFG
, val
);
6331 /* restore 5701 hardware bug workaround write method */
6332 tp
->write32
= write_op
;
6334 /* Unfortunately, we have to delay before the PCI read back.
6335 * Some 575X chips even will not respond to a PCI cfg access
6336 * when the reset command is given to the chip.
6338 * How do these hardware designers expect things to work
6339 * properly if the PCI write is posted for a long period
6340 * of time? It is always necessary to have some method by
6341 * which a register read back can occur to push the write
6342 * out which does the reset.
6344 * For most tg3 variants the trick below was working.
6349 /* Flush PCI posted writes. The normal MMIO registers
6350 * are inaccessible at this time so this is the only
6351 * way to make this reliably (actually, this is no longer
6352 * the case, see above). I tried to use indirect
6353 * register read/write but this upset some 5701 variants.
6355 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
6359 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) && tp
->pcie_cap
) {
6362 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
) {
6366 /* Wait for link training to complete. */
6367 for (i
= 0; i
< 5000; i
++)
6370 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
6371 pci_write_config_dword(tp
->pdev
, 0xc4,
6372 cfg_val
| (1 << 15));
6375 /* Clear the "no snoop" and "relaxed ordering" bits. */
6376 pci_read_config_word(tp
->pdev
,
6377 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6379 val16
&= ~(PCI_EXP_DEVCTL_RELAX_EN
|
6380 PCI_EXP_DEVCTL_NOSNOOP_EN
);
6382 * Older PCIe devices only support the 128 byte
6383 * MPS setting. Enforce the restriction.
6385 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) ||
6386 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
))
6387 val16
&= ~PCI_EXP_DEVCTL_PAYLOAD
;
6388 pci_write_config_word(tp
->pdev
,
6389 tp
->pcie_cap
+ PCI_EXP_DEVCTL
,
6392 pcie_set_readrq(tp
->pdev
, 4096);
6394 /* Clear error status */
6395 pci_write_config_word(tp
->pdev
,
6396 tp
->pcie_cap
+ PCI_EXP_DEVSTA
,
6397 PCI_EXP_DEVSTA_CED
|
6398 PCI_EXP_DEVSTA_NFED
|
6399 PCI_EXP_DEVSTA_FED
|
6400 PCI_EXP_DEVSTA_URD
);
6403 tg3_restore_pci_state(tp
);
6405 tp
->tg3_flags
&= ~TG3_FLAG_CHIP_RESETTING
;
6408 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
6409 val
= tr32(MEMARB_MODE
);
6410 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
6412 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A3
) {
6414 tw32(0x5000, 0x400);
6417 tw32(GRC_MODE
, tp
->grc_mode
);
6419 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
) {
6422 tw32(0xc4, val
| (1 << 15));
6425 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
6426 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6427 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
6428 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
)
6429 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
6430 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6433 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
6434 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
6435 tw32_f(MAC_MODE
, tp
->mac_mode
);
6436 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
6437 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
6438 tw32_f(MAC_MODE
, tp
->mac_mode
);
6439 } else if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6440 tp
->mac_mode
&= (MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
);
6441 if (tp
->mac_mode
& MAC_MODE_APE_TX_EN
)
6442 tp
->mac_mode
|= MAC_MODE_TDE_ENABLE
;
6443 tw32_f(MAC_MODE
, tp
->mac_mode
);
6445 tw32_f(MAC_MODE
, 0);
6448 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
6450 err
= tg3_poll_fw(tp
);
6456 if ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
6457 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
) {
6460 tw32(0x7c00, val
| (1 << 25));
6463 /* Reprobe ASF enable state. */
6464 tp
->tg3_flags
&= ~TG3_FLAG_ENABLE_ASF
;
6465 tp
->tg3_flags2
&= ~TG3_FLG2_ASF_NEW_HANDSHAKE
;
6466 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
6467 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
6470 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
6471 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
6472 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
6473 tp
->last_event_jiffies
= jiffies
;
6474 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
6475 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
6482 /* tp->lock is held. */
6483 static void tg3_stop_fw(struct tg3
*tp
)
6485 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
6486 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
6487 /* Wait for RX cpu to ACK the previous event. */
6488 tg3_wait_for_event_ack(tp
);
6490 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
6492 tg3_generate_fw_event(tp
);
6494 /* Wait for RX cpu to ACK this event. */
6495 tg3_wait_for_event_ack(tp
);
6499 /* tp->lock is held. */
6500 static int tg3_halt(struct tg3
*tp
, int kind
, int silent
)
6506 tg3_write_sig_pre_reset(tp
, kind
);
6508 tg3_abort_hw(tp
, silent
);
6509 err
= tg3_chip_reset(tp
);
6511 __tg3_set_mac_addr(tp
, 0);
6513 tg3_write_sig_legacy(tp
, kind
);
6514 tg3_write_sig_post_reset(tp
, kind
);
6522 #define RX_CPU_SCRATCH_BASE 0x30000
6523 #define RX_CPU_SCRATCH_SIZE 0x04000
6524 #define TX_CPU_SCRATCH_BASE 0x34000
6525 #define TX_CPU_SCRATCH_SIZE 0x04000
6527 /* tp->lock is held. */
6528 static int tg3_halt_cpu(struct tg3
*tp
, u32 offset
)
6532 BUG_ON(offset
== TX_CPU_BASE
&&
6533 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
));
6535 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
6536 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
6538 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
6541 if (offset
== RX_CPU_BASE
) {
6542 for (i
= 0; i
< 10000; i
++) {
6543 tw32(offset
+ CPU_STATE
, 0xffffffff);
6544 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6545 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6549 tw32(offset
+ CPU_STATE
, 0xffffffff);
6550 tw32_f(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6553 for (i
= 0; i
< 10000; i
++) {
6554 tw32(offset
+ CPU_STATE
, 0xffffffff);
6555 tw32(offset
+ CPU_MODE
, CPU_MODE_HALT
);
6556 if (tr32(offset
+ CPU_MODE
) & CPU_MODE_HALT
)
6562 printk(KERN_ERR PFX
"tg3_reset_cpu timed out for %s, "
6565 (offset
== RX_CPU_BASE
? "RX" : "TX"));
6569 /* Clear firmware's nvram arbitration. */
6570 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
6571 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
6576 unsigned int fw_base
;
6577 unsigned int fw_len
;
6578 const __be32
*fw_data
;
6581 /* tp->lock is held. */
6582 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
, u32 cpu_scratch_base
,
6583 int cpu_scratch_size
, struct fw_info
*info
)
6585 int err
, lock_err
, i
;
6586 void (*write_op
)(struct tg3
*, u32
, u32
);
6588 if (cpu_base
== TX_CPU_BASE
&&
6589 (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6590 printk(KERN_ERR PFX
"tg3_load_firmware_cpu: Trying to load "
6591 "TX cpu firmware on %s which is 5705.\n",
6596 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
6597 write_op
= tg3_write_mem
;
6599 write_op
= tg3_write_indirect_reg32
;
6601 /* It is possible that bootcode is still loading at this point.
6602 * Get the nvram lock first before halting the cpu.
6604 lock_err
= tg3_nvram_lock(tp
);
6605 err
= tg3_halt_cpu(tp
, cpu_base
);
6607 tg3_nvram_unlock(tp
);
6611 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
6612 write_op(tp
, cpu_scratch_base
+ i
, 0);
6613 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6614 tw32(cpu_base
+ CPU_MODE
, tr32(cpu_base
+CPU_MODE
)|CPU_MODE_HALT
);
6615 for (i
= 0; i
< (info
->fw_len
/ sizeof(u32
)); i
++)
6616 write_op(tp
, (cpu_scratch_base
+
6617 (info
->fw_base
& 0xffff) +
6619 be32_to_cpu(info
->fw_data
[i
]));
6627 /* tp->lock is held. */
6628 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
6630 struct fw_info info
;
6631 const __be32
*fw_data
;
6634 fw_data
= (void *)tp
->fw
->data
;
6636 /* Firmware blob starts with version numbers, followed by
6637 start address and length. We are setting complete length.
6638 length = end_address_of_bss - start_address_of_text.
6639 Remainder is the blob to be loaded contiguously
6640 from start address. */
6642 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6643 info
.fw_len
= tp
->fw
->size
- 12;
6644 info
.fw_data
= &fw_data
[3];
6646 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
6647 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
6652 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
6653 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
6658 /* Now startup only the RX cpu. */
6659 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6660 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6662 for (i
= 0; i
< 5; i
++) {
6663 if (tr32(RX_CPU_BASE
+ CPU_PC
) == info
.fw_base
)
6665 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6666 tw32(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
6667 tw32_f(RX_CPU_BASE
+ CPU_PC
, info
.fw_base
);
6671 printk(KERN_ERR PFX
"tg3_load_firmware fails for %s "
6672 "to set RX CPU PC, is %08x should be %08x\n",
6673 tp
->dev
->name
, tr32(RX_CPU_BASE
+ CPU_PC
),
6677 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
6678 tw32_f(RX_CPU_BASE
+ CPU_MODE
, 0x00000000);
6683 /* 5705 needs a special version of the TSO firmware. */
6685 /* tp->lock is held. */
6686 static int tg3_load_tso_firmware(struct tg3
*tp
)
6688 struct fw_info info
;
6689 const __be32
*fw_data
;
6690 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
6693 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
6696 fw_data
= (void *)tp
->fw
->data
;
6698 /* Firmware blob starts with version numbers, followed by
6699 start address and length. We are setting complete length.
6700 length = end_address_of_bss - start_address_of_text.
6701 Remainder is the blob to be loaded contiguously
6702 from start address. */
6704 info
.fw_base
= be32_to_cpu(fw_data
[1]);
6705 cpu_scratch_size
= tp
->fw_len
;
6706 info
.fw_len
= tp
->fw
->size
- 12;
6707 info
.fw_data
= &fw_data
[3];
6709 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
6710 cpu_base
= RX_CPU_BASE
;
6711 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
6713 cpu_base
= TX_CPU_BASE
;
6714 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
6715 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
6718 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
6719 cpu_scratch_base
, cpu_scratch_size
,
6724 /* Now startup the cpu. */
6725 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6726 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6728 for (i
= 0; i
< 5; i
++) {
6729 if (tr32(cpu_base
+ CPU_PC
) == info
.fw_base
)
6731 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6732 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
6733 tw32_f(cpu_base
+ CPU_PC
, info
.fw_base
);
6737 printk(KERN_ERR PFX
"tg3_load_tso_firmware fails for %s "
6738 "to set CPU PC, is %08x should be %08x\n",
6739 tp
->dev
->name
, tr32(cpu_base
+ CPU_PC
),
6743 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
6744 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
6749 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
6751 struct tg3
*tp
= netdev_priv(dev
);
6752 struct sockaddr
*addr
= p
;
6753 int err
= 0, skip_mac_1
= 0;
6755 if (!is_valid_ether_addr(addr
->sa_data
))
6758 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
6760 if (!netif_running(dev
))
6763 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) {
6764 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
6766 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
6767 addr0_low
= tr32(MAC_ADDR_0_LOW
);
6768 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
6769 addr1_low
= tr32(MAC_ADDR_1_LOW
);
6771 /* Skip MAC addr 1 if ASF is using it. */
6772 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
6773 !(addr1_high
== 0 && addr1_low
== 0))
6776 spin_lock_bh(&tp
->lock
);
6777 __tg3_set_mac_addr(tp
, skip_mac_1
);
6778 spin_unlock_bh(&tp
->lock
);
6783 /* tp->lock is held. */
6784 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
6785 dma_addr_t mapping
, u32 maxlen_flags
,
6789 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
6790 ((u64
) mapping
>> 32));
6792 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
6793 ((u64
) mapping
& 0xffffffff));
6795 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
6798 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6800 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
6804 static void __tg3_set_rx_mode(struct net_device
*);
6805 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
6807 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
6808 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
6809 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
6810 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
6811 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6812 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
6813 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
6815 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
6816 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
6817 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6818 u32 val
= ec
->stats_block_coalesce_usecs
;
6820 if (!netif_carrier_ok(tp
->dev
))
6823 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
6827 /* tp->lock is held. */
6828 static void tg3_rings_reset(struct tg3
*tp
)
6831 u32 txrcb
, rxrcb
, limit
;
6832 struct tg3_napi
*tnapi
= &tp
->napi
[0];
6834 /* Disable all transmit rings but the first. */
6835 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6836 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
6838 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
6840 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
6841 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
6842 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
6843 BDINFO_FLAGS_DISABLED
);
6846 /* Disable all receive return rings but the first. */
6847 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
6848 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
6849 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
6850 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
6852 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
6854 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
6855 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
6856 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
6857 BDINFO_FLAGS_DISABLED
);
6859 /* Disable interrupts */
6860 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
6862 /* Zero mailbox registers. */
6863 tp
->napi
[0].tx_prod
= 0;
6864 tp
->napi
[0].tx_cons
= 0;
6865 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
6866 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
6868 /* Make sure the NIC-based send BD rings are disabled. */
6869 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
6870 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
6871 for (i
= 0; i
< 16; i
++)
6872 tw32_tx_mbox(mbox
+ i
* 8, 0);
6875 txrcb
= NIC_SRAM_SEND_RCB
;
6876 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
6878 /* Clear status block in ram. */
6879 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
6881 /* Set status block DMA address */
6882 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
6883 ((u64
) tnapi
->status_mapping
>> 32));
6884 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
6885 ((u64
) tnapi
->status_mapping
& 0xffffffff));
6887 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
6888 (TG3_TX_RING_SIZE
<<
6889 BDINFO_FLAGS_MAXLEN_SHIFT
),
6890 NIC_SRAM_TX_BUFFER_DESC
);
6892 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
6893 (TG3_RX_RCB_RING_SIZE(tp
) <<
6894 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
6897 /* tp->lock is held. */
6898 static int tg3_reset_hw(struct tg3
*tp
, int reset_phy
)
6900 u32 val
, rdmac_mode
;
6902 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
6904 tg3_disable_ints(tp
);
6908 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
6910 if (tp
->tg3_flags
& TG3_FLAG_INIT_COMPLETE
) {
6911 tg3_abort_hw(tp
, 1);
6915 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
))
6918 err
= tg3_chip_reset(tp
);
6922 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
6924 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
) {
6925 val
= tr32(TG3_CPMU_CTRL
);
6926 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
6927 tw32(TG3_CPMU_CTRL
, val
);
6929 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
6930 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
6931 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
6932 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
6934 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
6935 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
6936 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
6937 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
6939 val
= tr32(TG3_CPMU_HST_ACC
);
6940 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
6941 val
|= CPMU_HST_ACC_MACCLK_6_25
;
6942 tw32(TG3_CPMU_HST_ACC
, val
);
6945 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
) {
6946 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
6947 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
6948 PCIE_PWR_MGMT_L1_THRESH_4MS
;
6949 tw32(PCIE_PWR_MGMT_THRESH
, val
);
6951 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
6952 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
6954 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
6957 if (tp
->tg3_flags3
& TG3_FLG3_TOGGLE_10_100_L1PLLPD
) {
6958 val
= tr32(TG3_PCIE_LNKCTL
);
6959 if (tp
->tg3_flags3
& TG3_FLG3_CLKREQ_BUG
)
6960 val
|= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
;
6962 val
&= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
;
6963 tw32(TG3_PCIE_LNKCTL
, val
);
6966 /* This works around an issue with Athlon chipsets on
6967 * B3 tigon3 silicon. This bit has no effect on any
6968 * other revision. But do not set this on PCI Express
6969 * chips and don't even touch the clocks if the CPMU is present.
6971 if (!(tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)) {
6972 if (!(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
6973 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
6974 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
6977 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
&&
6978 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
6979 val
= tr32(TG3PCI_PCISTATE
);
6980 val
|= PCISTATE_RETRY_SAME_DMA
;
6981 tw32(TG3PCI_PCISTATE
, val
);
6984 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
6985 /* Allow reads and writes to the
6986 * APE register and memory space.
6988 val
= tr32(TG3PCI_PCISTATE
);
6989 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
6990 PCISTATE_ALLOW_APE_SHMEM_WR
;
6991 tw32(TG3PCI_PCISTATE
, val
);
6994 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_BX
) {
6995 /* Enable some hw fixes. */
6996 val
= tr32(TG3PCI_MSI_DATA
);
6997 val
|= (1 << 26) | (1 << 28) | (1 << 29);
6998 tw32(TG3PCI_MSI_DATA
, val
);
7001 /* Descriptor ring init may make accesses to the
7002 * NIC SRAM area to setup the TX descriptors, so we
7003 * can only do this after the hardware has been
7004 * successfully reset.
7006 err
= tg3_init_rings(tp
);
7010 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5784
&&
7011 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5761
) {
7012 /* This value is determined during the probe time DMA
7013 * engine test, tg3_test_dma.
7015 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
7018 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
7019 GRC_MODE_4X_NIC_SEND_RINGS
|
7020 GRC_MODE_NO_TX_PHDR_CSUM
|
7021 GRC_MODE_NO_RX_PHDR_CSUM
);
7022 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
7024 /* Pseudo-header checksum is done by hardware logic and not
7025 * the offload processers, so make the chip do the pseudo-
7026 * header checksums on receive. For transmit it is more
7027 * convenient to do the pseudo-header checksum in software
7028 * as Linux does that on transmit for us in all cases.
7030 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
7034 (GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
));
7036 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7037 val
= tr32(GRC_MISC_CFG
);
7039 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
7040 tw32(GRC_MISC_CFG
, val
);
7042 /* Initialize MBUF/DESC pool. */
7043 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7045 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5705
) {
7046 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
7047 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
7048 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
7050 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
7051 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
7052 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
7054 else if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7057 fw_len
= tp
->fw_len
;
7058 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
7059 tw32(BUFMGR_MB_POOL_ADDR
,
7060 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
7061 tw32(BUFMGR_MB_POOL_SIZE
,
7062 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
7065 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
7066 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7067 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
7068 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7069 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
7070 tw32(BUFMGR_MB_HIGH_WATER
,
7071 tp
->bufmgr_config
.mbuf_high_water
);
7073 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
7074 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
7075 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
7076 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
7077 tw32(BUFMGR_MB_HIGH_WATER
,
7078 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
7080 tw32(BUFMGR_DMA_LOW_WATER
,
7081 tp
->bufmgr_config
.dma_low_water
);
7082 tw32(BUFMGR_DMA_HIGH_WATER
,
7083 tp
->bufmgr_config
.dma_high_water
);
7085 tw32(BUFMGR_MODE
, BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
);
7086 for (i
= 0; i
< 2000; i
++) {
7087 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
7092 printk(KERN_ERR PFX
"tg3_reset_hw cannot enable BUFMGR for %s.\n",
7097 /* Setup replenish threshold. */
7098 val
= tp
->rx_pending
/ 8;
7101 else if (val
> tp
->rx_std_max_post
)
7102 val
= tp
->rx_std_max_post
;
7103 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
7104 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5906_A1
)
7105 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
7107 if (val
> (TG3_RX_INTERNAL_RING_SZ_5906
/ 2))
7108 val
= TG3_RX_INTERNAL_RING_SZ_5906
/ 2;
7111 tw32(RCVBDI_STD_THRESH
, val
);
7113 /* Initialize TG3_BDINFO's at:
7114 * RCVDBDI_STD_BD: standard eth size rx ring
7115 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7116 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7119 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7120 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7121 * ring attribute flags
7122 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7124 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7125 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7127 * The size of each ring is fixed in the firmware, but the location is
7130 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7131 ((u64
) tpr
->rx_std_mapping
>> 32));
7132 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7133 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
7134 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
7135 NIC_SRAM_RX_BUFFER_DESC
);
7137 /* Disable the mini ring */
7138 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7139 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7140 BDINFO_FLAGS_DISABLED
);
7142 /* Program the jumbo buffer descriptor ring control
7143 * blocks on those devices that have them.
7145 if ((tp
->tg3_flags
& TG3_FLAG_JUMBO_CAPABLE
) &&
7146 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
7147 /* Setup replenish threshold. */
7148 tw32(RCVBDI_JUMBO_THRESH
, tp
->rx_jumbo_pending
/ 8);
7150 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) {
7151 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7152 ((u64
) tpr
->rx_jmb_mapping
>> 32));
7153 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7154 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
7155 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7156 (RX_JUMBO_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
) |
7157 BDINFO_FLAGS_USE_EXT_RECV
);
7158 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
7159 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
7161 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
7162 BDINFO_FLAGS_DISABLED
);
7165 val
= RX_STD_MAX_SIZE
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7167 val
= RX_STD_MAX_SIZE_5705
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
7169 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
7171 tpr
->rx_std_ptr
= tp
->rx_pending
;
7172 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7175 tpr
->rx_jmb_ptr
= (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
) ?
7176 tp
->rx_jumbo_pending
: 0;
7177 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX
+ TG3_64BIT_REG_LOW
,
7180 tg3_rings_reset(tp
);
7182 /* Initialize MAC address and backoff seed. */
7183 __tg3_set_mac_addr(tp
, 0);
7185 /* MTU + ethernet header + FCS + optional VLAN tag */
7186 tw32(MAC_RX_MTU_SIZE
,
7187 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
7189 /* The slot time is changed by tg3_setup_phy if we
7190 * run at gigabit with half duplex.
7192 tw32(MAC_TX_LENGTHS
,
7193 (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
7194 (6 << TX_LENGTHS_IPG_SHIFT
) |
7195 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
7197 /* Receive rules. */
7198 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
7199 tw32(RCVLPC_CONFIG
, 0x0181);
7201 /* Calculate RDMAC_MODE setting early, we need it to determine
7202 * the RCVLPC_STATE_ENABLE mask.
7204 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
7205 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
7206 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
7207 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
7208 RDMAC_MODE_LNGREAD_ENAB
);
7210 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
7211 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7212 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7213 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
7214 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
7215 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
7217 /* If statement applies to 5705 and 5750 PCI devices only */
7218 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7219 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7220 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)) {
7221 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
&&
7222 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) {
7223 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
7224 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7225 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
)) {
7226 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7230 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)
7231 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
7233 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7234 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
7236 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
7237 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
7238 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
7240 /* Receive/send statistics. */
7241 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
7242 val
= tr32(RCVLPC_STATS_ENABLE
);
7243 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
7244 tw32(RCVLPC_STATS_ENABLE
, val
);
7245 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
7246 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7247 val
= tr32(RCVLPC_STATS_ENABLE
);
7248 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
7249 tw32(RCVLPC_STATS_ENABLE
, val
);
7251 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
7253 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
7254 tw32(SNDDATAI_STATSENAB
, 0xffffff);
7255 tw32(SNDDATAI_STATSCTRL
,
7256 (SNDDATAI_SCTRL_ENABLE
|
7257 SNDDATAI_SCTRL_FASTUPD
));
7259 /* Setup host coalescing engine. */
7260 tw32(HOSTCC_MODE
, 0);
7261 for (i
= 0; i
< 2000; i
++) {
7262 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
7267 __tg3_set_coalesce(tp
, &tp
->coal
);
7269 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7270 /* Status/statistics block address. See tg3_timer,
7271 * the tg3_periodic_fetch_stats call there, and
7272 * tg3_get_stats to see how this works for 5705/5750 chips.
7274 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
7275 ((u64
) tp
->stats_mapping
>> 32));
7276 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
7277 ((u64
) tp
->stats_mapping
& 0xffffffff));
7278 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
7280 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
7282 /* Clear statistics and status block memory areas */
7283 for (i
= NIC_SRAM_STATS_BLK
;
7284 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
7286 tg3_write_mem(tp
, i
, 0);
7291 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
7293 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
7294 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
7295 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7296 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
7298 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
7299 tp
->tg3_flags2
&= ~TG3_FLG2_PARALLEL_DETECT
;
7300 /* reset to prevent losing 1st rx packet intermittently */
7301 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7305 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7306 tp
->mac_mode
&= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
7309 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
7310 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
| MAC_MODE_FHDE_ENABLE
;
7311 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7312 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7313 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
)
7314 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7315 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
7318 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7319 * If TG3_FLG2_IS_NIC is zero, we should read the
7320 * register to preserve the GPIO settings for LOMs. The GPIOs,
7321 * whether used as inputs or outputs, are set by boot code after
7324 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)) {
7327 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
7328 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
7329 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
7331 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
7332 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
7333 GRC_LCLCTRL_GPIO_OUTPUT3
;
7335 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
7336 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
7338 tp
->grc_local_ctrl
&= ~gpio_mask
;
7339 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
7341 /* GPIO1 must be driven high for eeprom write protect */
7342 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
)
7343 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
7344 GRC_LCLCTRL_GPIO_OUTPUT1
);
7346 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7349 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
7350 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
7354 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
7355 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
7356 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
7357 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
7358 WDMAC_MODE_LNGREAD_ENAB
);
7360 /* If statement applies to 5705 and 5750 PCI devices only */
7361 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
7362 tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) ||
7363 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) {
7364 if ((tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
7365 (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
||
7366 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A2
)) {
7368 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
7369 !(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
7370 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
7371 val
|= WDMAC_MODE_RX_ACCEL
;
7375 /* Enable host coalescing bug fix */
7376 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7377 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
7379 tw32_f(WDMAC_MODE
, val
);
7382 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
7385 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7387 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
) {
7388 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
7389 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7390 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
7391 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
7392 pcix_cmd
|= PCI_X_CMD_READ_2K
;
7394 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
7398 tw32_f(RDMAC_MODE
, rdmac_mode
);
7401 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
7402 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
7403 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
7405 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
7407 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
7409 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
7411 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
7412 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
7413 tw32(RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
);
7414 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
7415 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
)
7416 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
7417 tw32(SNDBDI_MODE
, SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
);
7418 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
7420 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7421 err
= tg3_load_5701_a0_firmware_fix(tp
);
7426 if (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) {
7427 err
= tg3_load_tso_firmware(tp
);
7432 tp
->tx_mode
= TX_MODE_ENABLE
;
7433 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
7436 tp
->rx_mode
= RX_MODE_ENABLE
;
7437 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
7438 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
7440 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7443 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
7445 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
7446 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7447 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
7450 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
7453 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
7454 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) &&
7455 !(tp
->tg3_flags2
& TG3_FLG2_SERDES_PREEMPHASIS
)) {
7456 /* Set drive transmission level to 1.2V */
7457 /* only if the signal pre-emphasis bit is not set */
7458 val
= tr32(MAC_SERDES_CFG
);
7461 tw32(MAC_SERDES_CFG
, val
);
7463 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
)
7464 tw32(MAC_SERDES_CFG
, 0x616000);
7467 /* Prevent chip from dropping frames when flow control
7470 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, 2);
7472 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
&&
7473 (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
7474 /* Use hardware link auto-negotiation */
7475 tp
->tg3_flags2
|= TG3_FLG2_HW_AUTONEG
;
7478 if ((tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) &&
7479 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
)) {
7482 tmp
= tr32(SERDES_RX_CTRL
);
7483 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
7484 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
7485 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
7486 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
7489 if (!(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
7490 if (tp
->link_config
.phy_is_low_power
) {
7491 tp
->link_config
.phy_is_low_power
= 0;
7492 tp
->link_config
.speed
= tp
->link_config
.orig_speed
;
7493 tp
->link_config
.duplex
= tp
->link_config
.orig_duplex
;
7494 tp
->link_config
.autoneg
= tp
->link_config
.orig_autoneg
;
7497 err
= tg3_setup_phy(tp
, 0);
7501 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
7502 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
)) {
7505 /* Clear CRC stats. */
7506 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
7507 tg3_writephy(tp
, MII_TG3_TEST1
,
7508 tmp
| MII_TG3_TEST1_CRC_EN
);
7509 tg3_readphy(tp
, 0x14, &tmp
);
7514 __tg3_set_rx_mode(tp
->dev
);
7516 /* Initialize receive rules. */
7517 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
7518 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7519 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
7520 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
7522 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
7523 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
7527 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
7531 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
7533 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
7535 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
7537 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
7539 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
7541 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
7543 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
7545 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
7547 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
7549 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
7551 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
7553 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
7555 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
7557 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
7565 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
7566 /* Write our heartbeat update interval to APE. */
7567 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
7568 APE_HOST_HEARTBEAT_INT_DISABLE
);
7570 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
7575 /* Called at device open time to get the chip ready for
7576 * packet processing. Invoked with tp->lock held.
7578 static int tg3_init_hw(struct tg3
*tp
, int reset_phy
)
7580 tg3_switch_clocks(tp
);
7582 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
7584 return tg3_reset_hw(tp
, reset_phy
);
7587 #define TG3_STAT_ADD32(PSTAT, REG) \
7588 do { u32 __val = tr32(REG); \
7589 (PSTAT)->low += __val; \
7590 if ((PSTAT)->low < __val) \
7591 (PSTAT)->high += 1; \
7594 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
7596 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
7598 if (!netif_carrier_ok(tp
->dev
))
7601 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
7602 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
7603 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
7604 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
7605 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
7606 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
7607 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
7608 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
7609 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
7610 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
7611 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
7612 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
7613 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
7615 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
7616 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
7617 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
7618 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
7619 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
7620 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
7621 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
7622 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
7623 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
7624 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
7625 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
7626 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
7627 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
7628 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
7630 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
7631 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
7632 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
7635 static void tg3_timer(unsigned long __opaque
)
7637 struct tg3
*tp
= (struct tg3
*) __opaque
;
7642 spin_lock(&tp
->lock
);
7644 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7645 /* All of this garbage is because when using non-tagged
7646 * IRQ status the mailbox/status_block protocol the chip
7647 * uses with the cpu is race prone.
7649 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
7650 tw32(GRC_LOCAL_CTRL
,
7651 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
7653 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7654 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
7657 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
7658 tp
->tg3_flags2
|= TG3_FLG2_RESTART_TIMER
;
7659 spin_unlock(&tp
->lock
);
7660 schedule_work(&tp
->reset_task
);
7665 /* This part only runs once per second. */
7666 if (!--tp
->timer_counter
) {
7667 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
7668 tg3_periodic_fetch_stats(tp
);
7670 if (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) {
7674 mac_stat
= tr32(MAC_STATUS
);
7677 if (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) {
7678 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
7680 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
7684 tg3_setup_phy(tp
, 0);
7685 } else if (tp
->tg3_flags
& TG3_FLAG_POLL_SERDES
) {
7686 u32 mac_stat
= tr32(MAC_STATUS
);
7689 if (netif_carrier_ok(tp
->dev
) &&
7690 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
7693 if (! netif_carrier_ok(tp
->dev
) &&
7694 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
7695 MAC_STATUS_SIGNAL_DET
))) {
7699 if (!tp
->serdes_counter
) {
7702 ~MAC_MODE_PORT_MODE_MASK
));
7704 tw32_f(MAC_MODE
, tp
->mac_mode
);
7707 tg3_setup_phy(tp
, 0);
7709 } else if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
7710 tg3_serdes_parallel_detect(tp
);
7712 tp
->timer_counter
= tp
->timer_multiplier
;
7715 /* Heartbeat is only sent once every 2 seconds.
7717 * The heartbeat is to tell the ASF firmware that the host
7718 * driver is still alive. In the event that the OS crashes,
7719 * ASF needs to reset the hardware to free up the FIFO space
7720 * that may be filled with rx packets destined for the host.
7721 * If the FIFO is full, ASF will no longer function properly.
7723 * Unintended resets have been reported on real time kernels
7724 * where the timer doesn't run on time. Netpoll will also have
7727 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7728 * to check the ring condition when the heartbeat is expiring
7729 * before doing the reset. This will prevent most unintended
7732 if (!--tp
->asf_counter
) {
7733 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) &&
7734 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
7735 tg3_wait_for_event_ack(tp
);
7737 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
7738 FWCMD_NICDRV_ALIVE3
);
7739 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
7740 /* 5 seconds timeout */
7741 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
, 5);
7743 tg3_generate_fw_event(tp
);
7745 tp
->asf_counter
= tp
->asf_multiplier
;
7748 spin_unlock(&tp
->lock
);
7751 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
7752 add_timer(&tp
->timer
);
7755 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
7758 unsigned long flags
;
7760 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
7762 if (tp
->irq_cnt
== 1)
7763 name
= tp
->dev
->name
;
7765 name
= &tnapi
->irq_lbl
[0];
7766 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
7767 name
[IFNAMSIZ
-1] = 0;
7770 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7772 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
)
7774 flags
= IRQF_SAMPLE_RANDOM
;
7777 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
7778 fn
= tg3_interrupt_tagged
;
7779 flags
= IRQF_SHARED
| IRQF_SAMPLE_RANDOM
;
7782 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
7785 static int tg3_test_interrupt(struct tg3
*tp
)
7787 struct tg3_napi
*tnapi
= &tp
->napi
[0];
7788 struct net_device
*dev
= tp
->dev
;
7789 int err
, i
, intr_ok
= 0;
7791 if (!netif_running(dev
))
7794 tg3_disable_ints(tp
);
7796 free_irq(tnapi
->irq_vec
, tnapi
);
7798 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
7799 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, tnapi
);
7803 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
7804 tg3_enable_ints(tp
);
7806 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
7809 for (i
= 0; i
< 5; i
++) {
7810 u32 int_mbox
, misc_host_ctrl
;
7812 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
7813 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
7815 if ((int_mbox
!= 0) ||
7816 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
7824 tg3_disable_ints(tp
);
7826 free_irq(tnapi
->irq_vec
, tnapi
);
7828 err
= tg3_request_irq(tp
, 0);
7839 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7840 * successfully restored
7842 static int tg3_test_msi(struct tg3
*tp
)
7847 if (!(tp
->tg3_flags2
& TG3_FLG2_USING_MSI
))
7850 /* Turn off SERR reporting in case MSI terminates with Master
7853 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
7854 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
7855 pci_cmd
& ~PCI_COMMAND_SERR
);
7857 err
= tg3_test_interrupt(tp
);
7859 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
7864 /* other failures */
7868 /* MSI test failed, go back to INTx mode */
7869 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
7870 "switching to INTx mode. Please report this failure to "
7871 "the PCI maintainer and include system chipset information.\n",
7874 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
7876 pci_disable_msi(tp
->pdev
);
7878 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7880 err
= tg3_request_irq(tp
, 0);
7884 /* Need to reset the chip because the MSI cycle may have terminated
7885 * with Master Abort.
7887 tg3_full_lock(tp
, 1);
7889 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
7890 err
= tg3_init_hw(tp
, 1);
7892 tg3_full_unlock(tp
);
7895 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
7900 static int tg3_request_firmware(struct tg3
*tp
)
7902 const __be32
*fw_data
;
7904 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
7905 printk(KERN_ERR
"%s: Failed to load firmware \"%s\"\n",
7906 tp
->dev
->name
, tp
->fw_needed
);
7910 fw_data
= (void *)tp
->fw
->data
;
7912 /* Firmware blob starts with version numbers, followed by
7913 * start address and _full_ length including BSS sections
7914 * (which must be longer than the actual data, of course
7917 tp
->fw_len
= be32_to_cpu(fw_data
[2]); /* includes bss */
7918 if (tp
->fw_len
< (tp
->fw
->size
- 12)) {
7919 printk(KERN_ERR
"%s: bogus length %d in \"%s\"\n",
7920 tp
->dev
->name
, tp
->fw_len
, tp
->fw_needed
);
7921 release_firmware(tp
->fw
);
7926 /* We no longer need firmware; we have it. */
7927 tp
->fw_needed
= NULL
;
7931 static void tg3_ints_init(struct tg3
*tp
)
7933 if (tp
->tg3_flags
& TG3_FLAG_SUPPORT_MSI
) {
7934 /* All MSI supporting chips should support tagged
7935 * status. Assert that this is the case.
7937 if (!(tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)) {
7938 printk(KERN_WARNING PFX
"%s: MSI without TAGGED? "
7939 "Not using MSI.\n", tp
->dev
->name
);
7940 } else if (pci_enable_msi(tp
->pdev
) == 0) {
7943 msi_mode
= tr32(MSGINT_MODE
);
7944 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
7945 tp
->tg3_flags2
|= TG3_FLG2_USING_MSI
;
7950 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
7953 static void tg3_ints_fini(struct tg3
*tp
)
7955 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
7956 pci_disable_msi(tp
->pdev
);
7957 tp
->tg3_flags2
&= ~TG3_FLG2_USING_MSI
;
7961 static int tg3_open(struct net_device
*dev
)
7963 struct tg3
*tp
= netdev_priv(dev
);
7966 if (tp
->fw_needed
) {
7967 err
= tg3_request_firmware(tp
);
7968 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
) {
7972 printk(KERN_WARNING
"%s: TSO capability disabled.\n",
7974 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
7975 } else if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
7976 printk(KERN_NOTICE
"%s: TSO capability restored.\n",
7978 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
7982 netif_carrier_off(tp
->dev
);
7984 err
= tg3_set_power_state(tp
, PCI_D0
);
7988 tg3_full_lock(tp
, 0);
7990 tg3_disable_ints(tp
);
7991 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
7993 tg3_full_unlock(tp
);
7995 /* The placement of this call is tied
7996 * to the setup and use of Host TX descriptors.
7998 err
= tg3_alloc_consistent(tp
);
8004 napi_enable(&tp
->napi
[0].napi
);
8006 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8007 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8008 err
= tg3_request_irq(tp
, i
);
8010 for (i
--; i
>= 0; i
--)
8011 free_irq(tnapi
->irq_vec
, tnapi
);
8019 tg3_full_lock(tp
, 0);
8021 err
= tg3_init_hw(tp
, 1);
8023 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8026 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
)
8027 tp
->timer_offset
= HZ
;
8029 tp
->timer_offset
= HZ
/ 10;
8031 BUG_ON(tp
->timer_offset
> HZ
);
8032 tp
->timer_counter
= tp
->timer_multiplier
=
8033 (HZ
/ tp
->timer_offset
);
8034 tp
->asf_counter
= tp
->asf_multiplier
=
8035 ((HZ
/ tp
->timer_offset
) * 2);
8037 init_timer(&tp
->timer
);
8038 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
8039 tp
->timer
.data
= (unsigned long) tp
;
8040 tp
->timer
.function
= tg3_timer
;
8043 tg3_full_unlock(tp
);
8048 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8049 err
= tg3_test_msi(tp
);
8052 tg3_full_lock(tp
, 0);
8053 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8055 tg3_full_unlock(tp
);
8060 if (tp
->tg3_flags2
& TG3_FLG2_USING_MSI
) {
8061 if (tp
->tg3_flags2
& TG3_FLG2_1SHOT_MSI
) {
8062 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
8064 tw32(PCIE_TRANSACTION_CFG
,
8065 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
8072 tg3_full_lock(tp
, 0);
8074 add_timer(&tp
->timer
);
8075 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
8076 tg3_enable_ints(tp
);
8078 tg3_full_unlock(tp
);
8080 netif_start_queue(dev
);
8085 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8086 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8087 free_irq(tnapi
->irq_vec
, tnapi
);
8091 napi_disable(&tp
->napi
[0].napi
);
8093 tg3_free_consistent(tp
);
8098 /*static*/ void tg3_dump_state(struct tg3
*tp
)
8100 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
8103 struct tg3_hw_status
*sblk
= tp
->napi
[0]->hw_status
;
8105 pci_read_config_word(tp
->pdev
, PCI_STATUS
, &val16
);
8106 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, &val32
);
8107 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8111 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8112 tr32(MAC_MODE
), tr32(MAC_STATUS
));
8113 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8114 tr32(MAC_EVENT
), tr32(MAC_LED_CTRL
));
8115 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8116 tr32(MAC_TX_MODE
), tr32(MAC_TX_STATUS
));
8117 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8118 tr32(MAC_RX_MODE
), tr32(MAC_RX_STATUS
));
8120 /* Send data initiator control block */
8121 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8122 tr32(SNDDATAI_MODE
), tr32(SNDDATAI_STATUS
));
8123 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8124 tr32(SNDDATAI_STATSCTRL
));
8126 /* Send data completion control block */
8127 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE
));
8129 /* Send BD ring selector block */
8130 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8131 tr32(SNDBDS_MODE
), tr32(SNDBDS_STATUS
));
8133 /* Send BD initiator control block */
8134 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8135 tr32(SNDBDI_MODE
), tr32(SNDBDI_STATUS
));
8137 /* Send BD completion control block */
8138 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE
));
8140 /* Receive list placement control block */
8141 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8142 tr32(RCVLPC_MODE
), tr32(RCVLPC_STATUS
));
8143 printk(" RCVLPC_STATSCTRL[%08x]\n",
8144 tr32(RCVLPC_STATSCTRL
));
8146 /* Receive data and receive BD initiator control block */
8147 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8148 tr32(RCVDBDI_MODE
), tr32(RCVDBDI_STATUS
));
8150 /* Receive data completion control block */
8151 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8154 /* Receive BD initiator control block */
8155 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8156 tr32(RCVBDI_MODE
), tr32(RCVBDI_STATUS
));
8158 /* Receive BD completion control block */
8159 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8160 tr32(RCVCC_MODE
), tr32(RCVCC_STATUS
));
8162 /* Receive list selector control block */
8163 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8164 tr32(RCVLSC_MODE
), tr32(RCVLSC_STATUS
));
8166 /* Mbuf cluster free block */
8167 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8168 tr32(MBFREE_MODE
), tr32(MBFREE_STATUS
));
8170 /* Host coalescing control block */
8171 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8172 tr32(HOSTCC_MODE
), tr32(HOSTCC_STATUS
));
8173 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8174 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8175 tr32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8176 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8177 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
8178 tr32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
));
8179 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8180 tr32(HOSTCC_STATS_BLK_NIC_ADDR
));
8181 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8182 tr32(HOSTCC_STATUS_BLK_NIC_ADDR
));
8184 /* Memory arbiter control block */
8185 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8186 tr32(MEMARB_MODE
), tr32(MEMARB_STATUS
));
8188 /* Buffer manager control block */
8189 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8190 tr32(BUFMGR_MODE
), tr32(BUFMGR_STATUS
));
8191 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8192 tr32(BUFMGR_MB_POOL_ADDR
), tr32(BUFMGR_MB_POOL_SIZE
));
8193 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8194 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8195 tr32(BUFMGR_DMA_DESC_POOL_ADDR
),
8196 tr32(BUFMGR_DMA_DESC_POOL_SIZE
));
8198 /* Read DMA control block */
8199 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8200 tr32(RDMAC_MODE
), tr32(RDMAC_STATUS
));
8202 /* Write DMA control block */
8203 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8204 tr32(WDMAC_MODE
), tr32(WDMAC_STATUS
));
8206 /* DMA completion block */
8207 printk("DEBUG: DMAC_MODE[%08x]\n",
8211 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8212 tr32(GRC_MODE
), tr32(GRC_MISC_CFG
));
8213 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8214 tr32(GRC_LOCAL_CTRL
));
8217 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8218 tr32(RCVDBDI_JUMBO_BD
+ 0x0),
8219 tr32(RCVDBDI_JUMBO_BD
+ 0x4),
8220 tr32(RCVDBDI_JUMBO_BD
+ 0x8),
8221 tr32(RCVDBDI_JUMBO_BD
+ 0xc));
8222 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8223 tr32(RCVDBDI_STD_BD
+ 0x0),
8224 tr32(RCVDBDI_STD_BD
+ 0x4),
8225 tr32(RCVDBDI_STD_BD
+ 0x8),
8226 tr32(RCVDBDI_STD_BD
+ 0xc));
8227 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8228 tr32(RCVDBDI_MINI_BD
+ 0x0),
8229 tr32(RCVDBDI_MINI_BD
+ 0x4),
8230 tr32(RCVDBDI_MINI_BD
+ 0x8),
8231 tr32(RCVDBDI_MINI_BD
+ 0xc));
8233 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x0, &val32
);
8234 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x4, &val32_2
);
8235 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0x8, &val32_3
);
8236 tg3_read_mem(tp
, NIC_SRAM_SEND_RCB
+ 0xc, &val32_4
);
8237 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8238 val32
, val32_2
, val32_3
, val32_4
);
8240 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x0, &val32
);
8241 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x4, &val32_2
);
8242 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0x8, &val32_3
);
8243 tg3_read_mem(tp
, NIC_SRAM_RCV_RET_RCB
+ 0xc, &val32_4
);
8244 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8245 val32
, val32_2
, val32_3
, val32_4
);
8247 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x0, &val32
);
8248 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x4, &val32_2
);
8249 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x8, &val32_3
);
8250 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0xc, &val32_4
);
8251 tg3_read_mem(tp
, NIC_SRAM_STATUS_BLK
+ 0x10, &val32_5
);
8252 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8253 val32
, val32_2
, val32_3
, val32_4
, val32_5
);
8255 /* SW status block */
8257 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8260 sblk
->rx_jumbo_consumer
,
8262 sblk
->rx_mini_consumer
,
8263 sblk
->idx
[0].rx_producer
,
8264 sblk
->idx
[0].tx_consumer
);
8266 /* SW statistics block */
8267 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8268 ((u32
*)tp
->hw_stats
)[0],
8269 ((u32
*)tp
->hw_stats
)[1],
8270 ((u32
*)tp
->hw_stats
)[2],
8271 ((u32
*)tp
->hw_stats
)[3]);
8274 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8275 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x0),
8276 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0
+ 0x4),
8277 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x0),
8278 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0
+ 0x4));
8280 /* NIC side send descriptors. */
8281 for (i
= 0; i
< 6; i
++) {
8284 txd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_TX_BUFFER_DESC
8285 + (i
* sizeof(struct tg3_tx_buffer_desc
));
8286 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8288 readl(txd
+ 0x0), readl(txd
+ 0x4),
8289 readl(txd
+ 0x8), readl(txd
+ 0xc));
8292 /* NIC side RX descriptors. */
8293 for (i
= 0; i
< 6; i
++) {
8296 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_BUFFER_DESC
8297 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8298 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8300 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8301 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8302 rxd
+= (4 * sizeof(u32
));
8303 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8305 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8306 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8309 for (i
= 0; i
< 6; i
++) {
8312 rxd
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_RX_JUMBO_BUFFER_DESC
8313 + (i
* sizeof(struct tg3_rx_buffer_desc
));
8314 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8316 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8317 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8318 rxd
+= (4 * sizeof(u32
));
8319 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8321 readl(rxd
+ 0x0), readl(rxd
+ 0x4),
8322 readl(rxd
+ 0x8), readl(rxd
+ 0xc));
8327 static struct net_device_stats
*tg3_get_stats(struct net_device
*);
8328 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*);
8330 static int tg3_close(struct net_device
*dev
)
8333 struct tg3
*tp
= netdev_priv(dev
);
8335 napi_disable(&tp
->napi
[0].napi
);
8336 cancel_work_sync(&tp
->reset_task
);
8338 netif_stop_queue(dev
);
8340 del_timer_sync(&tp
->timer
);
8342 tg3_full_lock(tp
, 1);
8347 tg3_disable_ints(tp
);
8349 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
8351 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
8353 tg3_full_unlock(tp
);
8355 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
8356 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8357 free_irq(tnapi
->irq_vec
, tnapi
);
8362 memcpy(&tp
->net_stats_prev
, tg3_get_stats(tp
->dev
),
8363 sizeof(tp
->net_stats_prev
));
8364 memcpy(&tp
->estats_prev
, tg3_get_estats(tp
),
8365 sizeof(tp
->estats_prev
));
8367 tg3_free_consistent(tp
);
8369 tg3_set_power_state(tp
, PCI_D3hot
);
8371 netif_carrier_off(tp
->dev
);
8376 static inline unsigned long get_stat64(tg3_stat64_t
*val
)
8380 #if (BITS_PER_LONG == 32)
8383 ret
= ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8388 static inline u64
get_estat64(tg3_stat64_t
*val
)
8390 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
8393 static unsigned long calc_crc_errors(struct tg3
*tp
)
8395 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8397 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
8398 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
8399 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
8402 spin_lock_bh(&tp
->lock
);
8403 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
8404 tg3_writephy(tp
, MII_TG3_TEST1
,
8405 val
| MII_TG3_TEST1_CRC_EN
);
8406 tg3_readphy(tp
, 0x14, &val
);
8409 spin_unlock_bh(&tp
->lock
);
8411 tp
->phy_crc_errors
+= val
;
8413 return tp
->phy_crc_errors
;
8416 return get_stat64(&hw_stats
->rx_fcs_errors
);
8419 #define ESTAT_ADD(member) \
8420 estats->member = old_estats->member + \
8421 get_estat64(&hw_stats->member)
8423 static struct tg3_ethtool_stats
*tg3_get_estats(struct tg3
*tp
)
8425 struct tg3_ethtool_stats
*estats
= &tp
->estats
;
8426 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
8427 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8432 ESTAT_ADD(rx_octets
);
8433 ESTAT_ADD(rx_fragments
);
8434 ESTAT_ADD(rx_ucast_packets
);
8435 ESTAT_ADD(rx_mcast_packets
);
8436 ESTAT_ADD(rx_bcast_packets
);
8437 ESTAT_ADD(rx_fcs_errors
);
8438 ESTAT_ADD(rx_align_errors
);
8439 ESTAT_ADD(rx_xon_pause_rcvd
);
8440 ESTAT_ADD(rx_xoff_pause_rcvd
);
8441 ESTAT_ADD(rx_mac_ctrl_rcvd
);
8442 ESTAT_ADD(rx_xoff_entered
);
8443 ESTAT_ADD(rx_frame_too_long_errors
);
8444 ESTAT_ADD(rx_jabbers
);
8445 ESTAT_ADD(rx_undersize_packets
);
8446 ESTAT_ADD(rx_in_length_errors
);
8447 ESTAT_ADD(rx_out_length_errors
);
8448 ESTAT_ADD(rx_64_or_less_octet_packets
);
8449 ESTAT_ADD(rx_65_to_127_octet_packets
);
8450 ESTAT_ADD(rx_128_to_255_octet_packets
);
8451 ESTAT_ADD(rx_256_to_511_octet_packets
);
8452 ESTAT_ADD(rx_512_to_1023_octet_packets
);
8453 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
8454 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
8455 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
8456 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
8457 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
8459 ESTAT_ADD(tx_octets
);
8460 ESTAT_ADD(tx_collisions
);
8461 ESTAT_ADD(tx_xon_sent
);
8462 ESTAT_ADD(tx_xoff_sent
);
8463 ESTAT_ADD(tx_flow_control
);
8464 ESTAT_ADD(tx_mac_errors
);
8465 ESTAT_ADD(tx_single_collisions
);
8466 ESTAT_ADD(tx_mult_collisions
);
8467 ESTAT_ADD(tx_deferred
);
8468 ESTAT_ADD(tx_excessive_collisions
);
8469 ESTAT_ADD(tx_late_collisions
);
8470 ESTAT_ADD(tx_collide_2times
);
8471 ESTAT_ADD(tx_collide_3times
);
8472 ESTAT_ADD(tx_collide_4times
);
8473 ESTAT_ADD(tx_collide_5times
);
8474 ESTAT_ADD(tx_collide_6times
);
8475 ESTAT_ADD(tx_collide_7times
);
8476 ESTAT_ADD(tx_collide_8times
);
8477 ESTAT_ADD(tx_collide_9times
);
8478 ESTAT_ADD(tx_collide_10times
);
8479 ESTAT_ADD(tx_collide_11times
);
8480 ESTAT_ADD(tx_collide_12times
);
8481 ESTAT_ADD(tx_collide_13times
);
8482 ESTAT_ADD(tx_collide_14times
);
8483 ESTAT_ADD(tx_collide_15times
);
8484 ESTAT_ADD(tx_ucast_packets
);
8485 ESTAT_ADD(tx_mcast_packets
);
8486 ESTAT_ADD(tx_bcast_packets
);
8487 ESTAT_ADD(tx_carrier_sense_errors
);
8488 ESTAT_ADD(tx_discards
);
8489 ESTAT_ADD(tx_errors
);
8491 ESTAT_ADD(dma_writeq_full
);
8492 ESTAT_ADD(dma_write_prioq_full
);
8493 ESTAT_ADD(rxbds_empty
);
8494 ESTAT_ADD(rx_discards
);
8495 ESTAT_ADD(rx_errors
);
8496 ESTAT_ADD(rx_threshold_hit
);
8498 ESTAT_ADD(dma_readq_full
);
8499 ESTAT_ADD(dma_read_prioq_full
);
8500 ESTAT_ADD(tx_comp_queue_full
);
8502 ESTAT_ADD(ring_set_send_prod_index
);
8503 ESTAT_ADD(ring_status_update
);
8504 ESTAT_ADD(nic_irqs
);
8505 ESTAT_ADD(nic_avoided_irqs
);
8506 ESTAT_ADD(nic_tx_threshold_hit
);
8511 static struct net_device_stats
*tg3_get_stats(struct net_device
*dev
)
8513 struct tg3
*tp
= netdev_priv(dev
);
8514 struct net_device_stats
*stats
= &tp
->net_stats
;
8515 struct net_device_stats
*old_stats
= &tp
->net_stats_prev
;
8516 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
8521 stats
->rx_packets
= old_stats
->rx_packets
+
8522 get_stat64(&hw_stats
->rx_ucast_packets
) +
8523 get_stat64(&hw_stats
->rx_mcast_packets
) +
8524 get_stat64(&hw_stats
->rx_bcast_packets
);
8526 stats
->tx_packets
= old_stats
->tx_packets
+
8527 get_stat64(&hw_stats
->tx_ucast_packets
) +
8528 get_stat64(&hw_stats
->tx_mcast_packets
) +
8529 get_stat64(&hw_stats
->tx_bcast_packets
);
8531 stats
->rx_bytes
= old_stats
->rx_bytes
+
8532 get_stat64(&hw_stats
->rx_octets
);
8533 stats
->tx_bytes
= old_stats
->tx_bytes
+
8534 get_stat64(&hw_stats
->tx_octets
);
8536 stats
->rx_errors
= old_stats
->rx_errors
+
8537 get_stat64(&hw_stats
->rx_errors
);
8538 stats
->tx_errors
= old_stats
->tx_errors
+
8539 get_stat64(&hw_stats
->tx_errors
) +
8540 get_stat64(&hw_stats
->tx_mac_errors
) +
8541 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
8542 get_stat64(&hw_stats
->tx_discards
);
8544 stats
->multicast
= old_stats
->multicast
+
8545 get_stat64(&hw_stats
->rx_mcast_packets
);
8546 stats
->collisions
= old_stats
->collisions
+
8547 get_stat64(&hw_stats
->tx_collisions
);
8549 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
8550 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
8551 get_stat64(&hw_stats
->rx_undersize_packets
);
8553 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
8554 get_stat64(&hw_stats
->rxbds_empty
);
8555 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
8556 get_stat64(&hw_stats
->rx_align_errors
);
8557 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
8558 get_stat64(&hw_stats
->tx_discards
);
8559 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
8560 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
8562 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
8563 calc_crc_errors(tp
);
8565 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
8566 get_stat64(&hw_stats
->rx_discards
);
8571 static inline u32
calc_crc(unsigned char *buf
, int len
)
8579 for (j
= 0; j
< len
; j
++) {
8582 for (k
= 0; k
< 8; k
++) {
8596 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
8598 /* accept or reject all multicast frames */
8599 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
8600 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
8601 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
8602 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
8605 static void __tg3_set_rx_mode(struct net_device
*dev
)
8607 struct tg3
*tp
= netdev_priv(dev
);
8610 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
8611 RX_MODE_KEEP_VLAN_TAG
);
8613 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8616 #if TG3_VLAN_TAG_USED
8618 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8619 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8621 /* By definition, VLAN is disabled always in this
8624 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
8625 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
8628 if (dev
->flags
& IFF_PROMISC
) {
8629 /* Promiscuous mode. */
8630 rx_mode
|= RX_MODE_PROMISC
;
8631 } else if (dev
->flags
& IFF_ALLMULTI
) {
8632 /* Accept all multicast. */
8633 tg3_set_multi (tp
, 1);
8634 } else if (dev
->mc_count
< 1) {
8635 /* Reject all multicast. */
8636 tg3_set_multi (tp
, 0);
8638 /* Accept one or more multicast(s). */
8639 struct dev_mc_list
*mclist
;
8641 u32 mc_filter
[4] = { 0, };
8646 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
8647 i
++, mclist
= mclist
->next
) {
8649 crc
= calc_crc (mclist
->dmi_addr
, ETH_ALEN
);
8651 regidx
= (bit
& 0x60) >> 5;
8653 mc_filter
[regidx
] |= (1 << bit
);
8656 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
8657 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
8658 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
8659 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
8662 if (rx_mode
!= tp
->rx_mode
) {
8663 tp
->rx_mode
= rx_mode
;
8664 tw32_f(MAC_RX_MODE
, rx_mode
);
8669 static void tg3_set_rx_mode(struct net_device
*dev
)
8671 struct tg3
*tp
= netdev_priv(dev
);
8673 if (!netif_running(dev
))
8676 tg3_full_lock(tp
, 0);
8677 __tg3_set_rx_mode(dev
);
8678 tg3_full_unlock(tp
);
8681 #define TG3_REGDUMP_LEN (32 * 1024)
8683 static int tg3_get_regs_len(struct net_device
*dev
)
8685 return TG3_REGDUMP_LEN
;
8688 static void tg3_get_regs(struct net_device
*dev
,
8689 struct ethtool_regs
*regs
, void *_p
)
8692 struct tg3
*tp
= netdev_priv(dev
);
8698 memset(p
, 0, TG3_REGDUMP_LEN
);
8700 if (tp
->link_config
.phy_is_low_power
)
8703 tg3_full_lock(tp
, 0);
8705 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
8706 #define GET_REG32_LOOP(base,len) \
8707 do { p = (u32 *)(orig_p + (base)); \
8708 for (i = 0; i < len; i += 4) \
8709 __GET_REG32((base) + i); \
8711 #define GET_REG32_1(reg) \
8712 do { p = (u32 *)(orig_p + (reg)); \
8713 __GET_REG32((reg)); \
8716 GET_REG32_LOOP(TG3PCI_VENDOR
, 0xb0);
8717 GET_REG32_LOOP(MAILBOX_INTERRUPT_0
, 0x200);
8718 GET_REG32_LOOP(MAC_MODE
, 0x4f0);
8719 GET_REG32_LOOP(SNDDATAI_MODE
, 0xe0);
8720 GET_REG32_1(SNDDATAC_MODE
);
8721 GET_REG32_LOOP(SNDBDS_MODE
, 0x80);
8722 GET_REG32_LOOP(SNDBDI_MODE
, 0x48);
8723 GET_REG32_1(SNDBDC_MODE
);
8724 GET_REG32_LOOP(RCVLPC_MODE
, 0x20);
8725 GET_REG32_LOOP(RCVLPC_SELLST_BASE
, 0x15c);
8726 GET_REG32_LOOP(RCVDBDI_MODE
, 0x0c);
8727 GET_REG32_LOOP(RCVDBDI_JUMBO_BD
, 0x3c);
8728 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0
, 0x44);
8729 GET_REG32_1(RCVDCC_MODE
);
8730 GET_REG32_LOOP(RCVBDI_MODE
, 0x20);
8731 GET_REG32_LOOP(RCVCC_MODE
, 0x14);
8732 GET_REG32_LOOP(RCVLSC_MODE
, 0x08);
8733 GET_REG32_1(MBFREE_MODE
);
8734 GET_REG32_LOOP(HOSTCC_MODE
, 0x100);
8735 GET_REG32_LOOP(MEMARB_MODE
, 0x10);
8736 GET_REG32_LOOP(BUFMGR_MODE
, 0x58);
8737 GET_REG32_LOOP(RDMAC_MODE
, 0x08);
8738 GET_REG32_LOOP(WDMAC_MODE
, 0x08);
8739 GET_REG32_1(RX_CPU_MODE
);
8740 GET_REG32_1(RX_CPU_STATE
);
8741 GET_REG32_1(RX_CPU_PGMCTR
);
8742 GET_REG32_1(RX_CPU_HWBKPT
);
8743 GET_REG32_1(TX_CPU_MODE
);
8744 GET_REG32_1(TX_CPU_STATE
);
8745 GET_REG32_1(TX_CPU_PGMCTR
);
8746 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0
, 0x110);
8747 GET_REG32_LOOP(FTQ_RESET
, 0x120);
8748 GET_REG32_LOOP(MSGINT_MODE
, 0x0c);
8749 GET_REG32_1(DMAC_MODE
);
8750 GET_REG32_LOOP(GRC_MODE
, 0x4c);
8751 if (tp
->tg3_flags
& TG3_FLAG_NVRAM
)
8752 GET_REG32_LOOP(NVRAM_CMD
, 0x24);
8755 #undef GET_REG32_LOOP
8758 tg3_full_unlock(tp
);
8761 static int tg3_get_eeprom_len(struct net_device
*dev
)
8763 struct tg3
*tp
= netdev_priv(dev
);
8765 return tp
->nvram_size
;
8768 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8770 struct tg3
*tp
= netdev_priv(dev
);
8773 u32 i
, offset
, len
, b_offset
, b_count
;
8776 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
8779 if (tp
->link_config
.phy_is_low_power
)
8782 offset
= eeprom
->offset
;
8786 eeprom
->magic
= TG3_EEPROM_MAGIC
;
8789 /* adjustments to start on required 4 byte boundary */
8790 b_offset
= offset
& 3;
8791 b_count
= 4 - b_offset
;
8792 if (b_count
> len
) {
8793 /* i.e. offset=1 len=2 */
8796 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
8799 memcpy(data
, ((char*)&val
) + b_offset
, b_count
);
8802 eeprom
->len
+= b_count
;
8805 /* read bytes upto the last 4 byte boundary */
8806 pd
= &data
[eeprom
->len
];
8807 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
8808 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
8813 memcpy(pd
+ i
, &val
, 4);
8818 /* read last bytes not ending on 4 byte boundary */
8819 pd
= &data
[eeprom
->len
];
8821 b_offset
= offset
+ len
- b_count
;
8822 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
8825 memcpy(pd
, &val
, b_count
);
8826 eeprom
->len
+= b_count
;
8831 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
);
8833 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
8835 struct tg3
*tp
= netdev_priv(dev
);
8837 u32 offset
, len
, b_offset
, odd_len
;
8841 if (tp
->link_config
.phy_is_low_power
)
8844 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
8845 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
8848 offset
= eeprom
->offset
;
8851 if ((b_offset
= (offset
& 3))) {
8852 /* adjustments to start on required 4 byte boundary */
8853 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
8864 /* adjustments to end on required 4 byte boundary */
8866 len
= (len
+ 3) & ~3;
8867 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
8873 if (b_offset
|| odd_len
) {
8874 buf
= kmalloc(len
, GFP_KERNEL
);
8878 memcpy(buf
, &start
, 4);
8880 memcpy(buf
+len
-4, &end
, 4);
8881 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
8884 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
8892 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8894 struct tg3
*tp
= netdev_priv(dev
);
8896 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8897 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8899 return phy_ethtool_gset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8902 cmd
->supported
= (SUPPORTED_Autoneg
);
8904 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
8905 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
8906 SUPPORTED_1000baseT_Full
);
8908 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)) {
8909 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
8910 SUPPORTED_100baseT_Full
|
8911 SUPPORTED_10baseT_Half
|
8912 SUPPORTED_10baseT_Full
|
8914 cmd
->port
= PORT_TP
;
8916 cmd
->supported
|= SUPPORTED_FIBRE
;
8917 cmd
->port
= PORT_FIBRE
;
8920 cmd
->advertising
= tp
->link_config
.advertising
;
8921 if (netif_running(dev
)) {
8922 cmd
->speed
= tp
->link_config
.active_speed
;
8923 cmd
->duplex
= tp
->link_config
.active_duplex
;
8925 cmd
->phy_address
= PHY_ADDR
;
8926 cmd
->transceiver
= XCVR_INTERNAL
;
8927 cmd
->autoneg
= tp
->link_config
.autoneg
;
8933 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
8935 struct tg3
*tp
= netdev_priv(dev
);
8937 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
8938 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
8940 return phy_ethtool_sset(tp
->mdio_bus
->phy_map
[PHY_ADDR
], cmd
);
8943 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
8944 cmd
->autoneg
!= AUTONEG_DISABLE
)
8947 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
8948 cmd
->duplex
!= DUPLEX_FULL
&&
8949 cmd
->duplex
!= DUPLEX_HALF
)
8952 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8953 u32 mask
= ADVERTISED_Autoneg
|
8955 ADVERTISED_Asym_Pause
;
8957 if (!(tp
->tg3_flags2
& TG3_FLAG_10_100_ONLY
))
8958 mask
|= ADVERTISED_1000baseT_Half
|
8959 ADVERTISED_1000baseT_Full
;
8961 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
8962 mask
|= ADVERTISED_100baseT_Half
|
8963 ADVERTISED_100baseT_Full
|
8964 ADVERTISED_10baseT_Half
|
8965 ADVERTISED_10baseT_Full
|
8968 mask
|= ADVERTISED_FIBRE
;
8970 if (cmd
->advertising
& ~mask
)
8973 mask
&= (ADVERTISED_1000baseT_Half
|
8974 ADVERTISED_1000baseT_Full
|
8975 ADVERTISED_100baseT_Half
|
8976 ADVERTISED_100baseT_Full
|
8977 ADVERTISED_10baseT_Half
|
8978 ADVERTISED_10baseT_Full
);
8980 cmd
->advertising
&= mask
;
8982 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) {
8983 if (cmd
->speed
!= SPEED_1000
)
8986 if (cmd
->duplex
!= DUPLEX_FULL
)
8989 if (cmd
->speed
!= SPEED_100
&&
8990 cmd
->speed
!= SPEED_10
)
8995 tg3_full_lock(tp
, 0);
8997 tp
->link_config
.autoneg
= cmd
->autoneg
;
8998 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
8999 tp
->link_config
.advertising
= (cmd
->advertising
|
9000 ADVERTISED_Autoneg
);
9001 tp
->link_config
.speed
= SPEED_INVALID
;
9002 tp
->link_config
.duplex
= DUPLEX_INVALID
;
9004 tp
->link_config
.advertising
= 0;
9005 tp
->link_config
.speed
= cmd
->speed
;
9006 tp
->link_config
.duplex
= cmd
->duplex
;
9009 tp
->link_config
.orig_speed
= tp
->link_config
.speed
;
9010 tp
->link_config
.orig_duplex
= tp
->link_config
.duplex
;
9011 tp
->link_config
.orig_autoneg
= tp
->link_config
.autoneg
;
9013 if (netif_running(dev
))
9014 tg3_setup_phy(tp
, 1);
9016 tg3_full_unlock(tp
);
9021 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
9023 struct tg3
*tp
= netdev_priv(dev
);
9025 strcpy(info
->driver
, DRV_MODULE_NAME
);
9026 strcpy(info
->version
, DRV_MODULE_VERSION
);
9027 strcpy(info
->fw_version
, tp
->fw_ver
);
9028 strcpy(info
->bus_info
, pci_name(tp
->pdev
));
9031 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9033 struct tg3
*tp
= netdev_priv(dev
);
9035 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
9036 device_can_wakeup(&tp
->pdev
->dev
))
9037 wol
->supported
= WAKE_MAGIC
;
9041 if ((tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
) &&
9042 device_can_wakeup(&tp
->pdev
->dev
))
9043 wol
->wolopts
= WAKE_MAGIC
;
9044 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
9047 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
9049 struct tg3
*tp
= netdev_priv(dev
);
9050 struct device
*dp
= &tp
->pdev
->dev
;
9052 if (wol
->wolopts
& ~WAKE_MAGIC
)
9054 if ((wol
->wolopts
& WAKE_MAGIC
) &&
9055 !((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) && device_can_wakeup(dp
)))
9058 spin_lock_bh(&tp
->lock
);
9059 if (wol
->wolopts
& WAKE_MAGIC
) {
9060 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
9061 device_set_wakeup_enable(dp
, true);
9063 tp
->tg3_flags
&= ~TG3_FLAG_WOL_ENABLE
;
9064 device_set_wakeup_enable(dp
, false);
9066 spin_unlock_bh(&tp
->lock
);
9071 static u32
tg3_get_msglevel(struct net_device
*dev
)
9073 struct tg3
*tp
= netdev_priv(dev
);
9074 return tp
->msg_enable
;
9077 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
9079 struct tg3
*tp
= netdev_priv(dev
);
9080 tp
->msg_enable
= value
;
9083 static int tg3_set_tso(struct net_device
*dev
, u32 value
)
9085 struct tg3
*tp
= netdev_priv(dev
);
9087 if (!(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
)) {
9092 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
9093 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
)) {
9095 dev
->features
|= NETIF_F_TSO6
;
9096 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
9097 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
9098 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
9099 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
9100 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
9101 dev
->features
|= NETIF_F_TSO_ECN
;
9103 dev
->features
&= ~(NETIF_F_TSO6
| NETIF_F_TSO_ECN
);
9105 return ethtool_op_set_tso(dev
, value
);
9108 static int tg3_nway_reset(struct net_device
*dev
)
9110 struct tg3
*tp
= netdev_priv(dev
);
9113 if (!netif_running(dev
))
9116 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
9119 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9120 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9122 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[PHY_ADDR
]);
9126 spin_lock_bh(&tp
->lock
);
9128 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
9129 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
9130 ((bmcr
& BMCR_ANENABLE
) ||
9131 (tp
->tg3_flags2
& TG3_FLG2_PARALLEL_DETECT
))) {
9132 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
9136 spin_unlock_bh(&tp
->lock
);
9142 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9144 struct tg3
*tp
= netdev_priv(dev
);
9146 ering
->rx_max_pending
= TG3_RX_RING_SIZE
- 1;
9147 ering
->rx_mini_max_pending
= 0;
9148 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9149 ering
->rx_jumbo_max_pending
= TG3_RX_JUMBO_RING_SIZE
- 1;
9151 ering
->rx_jumbo_max_pending
= 0;
9153 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
9155 ering
->rx_pending
= tp
->rx_pending
;
9156 ering
->rx_mini_pending
= 0;
9157 if (tp
->tg3_flags
& TG3_FLAG_JUMBO_RING_ENABLE
)
9158 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
9160 ering
->rx_jumbo_pending
= 0;
9162 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
9165 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
9167 struct tg3
*tp
= netdev_priv(dev
);
9168 int irq_sync
= 0, err
= 0;
9170 if ((ering
->rx_pending
> TG3_RX_RING_SIZE
- 1) ||
9171 (ering
->rx_jumbo_pending
> TG3_RX_JUMBO_RING_SIZE
- 1) ||
9172 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
9173 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
9174 ((tp
->tg3_flags2
& TG3_FLG2_TSO_BUG
) &&
9175 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
9178 if (netif_running(dev
)) {
9184 tg3_full_lock(tp
, irq_sync
);
9186 tp
->rx_pending
= ering
->rx_pending
;
9188 if ((tp
->tg3_flags2
& TG3_FLG2_MAX_RXPEND_64
) &&
9189 tp
->rx_pending
> 63)
9190 tp
->rx_pending
= 63;
9191 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
9192 tp
->napi
[0].tx_pending
= ering
->tx_pending
;
9194 if (netif_running(dev
)) {
9195 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9196 err
= tg3_restart_hw(tp
, 1);
9198 tg3_netif_start(tp
);
9201 tg3_full_unlock(tp
);
9203 if (irq_sync
&& !err
)
9209 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9211 struct tg3
*tp
= netdev_priv(dev
);
9213 epause
->autoneg
= (tp
->tg3_flags
& TG3_FLAG_PAUSE_AUTONEG
) != 0;
9215 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
)
9216 epause
->rx_pause
= 1;
9218 epause
->rx_pause
= 0;
9220 if (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
)
9221 epause
->tx_pause
= 1;
9223 epause
->tx_pause
= 0;
9226 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
9228 struct tg3
*tp
= netdev_priv(dev
);
9231 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
9232 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
9235 if (epause
->autoneg
) {
9237 struct phy_device
*phydev
;
9239 phydev
= tp
->mdio_bus
->phy_map
[PHY_ADDR
];
9241 if (epause
->rx_pause
) {
9242 if (epause
->tx_pause
)
9243 newadv
= ADVERTISED_Pause
;
9245 newadv
= ADVERTISED_Pause
|
9246 ADVERTISED_Asym_Pause
;
9247 } else if (epause
->tx_pause
) {
9248 newadv
= ADVERTISED_Asym_Pause
;
9252 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
) {
9253 u32 oldadv
= phydev
->advertising
&
9255 ADVERTISED_Asym_Pause
);
9256 if (oldadv
!= newadv
) {
9257 phydev
->advertising
&=
9258 ~(ADVERTISED_Pause
|
9259 ADVERTISED_Asym_Pause
);
9260 phydev
->advertising
|= newadv
;
9261 err
= phy_start_aneg(phydev
);
9264 tp
->link_config
.advertising
&=
9265 ~(ADVERTISED_Pause
|
9266 ADVERTISED_Asym_Pause
);
9267 tp
->link_config
.advertising
|= newadv
;
9270 if (epause
->rx_pause
)
9271 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9273 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9275 if (epause
->tx_pause
)
9276 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9278 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9280 if (netif_running(dev
))
9281 tg3_setup_flow_control(tp
, 0, 0);
9286 if (netif_running(dev
)) {
9291 tg3_full_lock(tp
, irq_sync
);
9293 if (epause
->autoneg
)
9294 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
9296 tp
->tg3_flags
&= ~TG3_FLAG_PAUSE_AUTONEG
;
9297 if (epause
->rx_pause
)
9298 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
9300 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
9301 if (epause
->tx_pause
)
9302 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
9304 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
9306 if (netif_running(dev
)) {
9307 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
9308 err
= tg3_restart_hw(tp
, 1);
9310 tg3_netif_start(tp
);
9313 tg3_full_unlock(tp
);
9319 static u32
tg3_get_rx_csum(struct net_device
*dev
)
9321 struct tg3
*tp
= netdev_priv(dev
);
9322 return (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0;
9325 static int tg3_set_rx_csum(struct net_device
*dev
, u32 data
)
9327 struct tg3
*tp
= netdev_priv(dev
);
9329 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9335 spin_lock_bh(&tp
->lock
);
9337 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
9339 tp
->tg3_flags
&= ~TG3_FLAG_RX_CHECKSUMS
;
9340 spin_unlock_bh(&tp
->lock
);
9345 static int tg3_set_tx_csum(struct net_device
*dev
, u32 data
)
9347 struct tg3
*tp
= netdev_priv(dev
);
9349 if (tp
->tg3_flags
& TG3_FLAG_BROKEN_CHECKSUMS
) {
9355 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9356 ethtool_op_set_tx_ipv6_csum(dev
, data
);
9358 ethtool_op_set_tx_csum(dev
, data
);
9363 static int tg3_get_sset_count (struct net_device
*dev
, int sset
)
9367 return TG3_NUM_TEST
;
9369 return TG3_NUM_STATS
;
9375 static void tg3_get_strings (struct net_device
*dev
, u32 stringset
, u8
*buf
)
9377 switch (stringset
) {
9379 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
9382 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
9385 WARN_ON(1); /* we need a WARN() */
9390 static int tg3_phys_id(struct net_device
*dev
, u32 data
)
9392 struct tg3
*tp
= netdev_priv(dev
);
9395 if (!netif_running(tp
->dev
))
9399 data
= UINT_MAX
/ 2;
9401 for (i
= 0; i
< (data
* 2); i
++) {
9403 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9404 LED_CTRL_1000MBPS_ON
|
9405 LED_CTRL_100MBPS_ON
|
9406 LED_CTRL_10MBPS_ON
|
9407 LED_CTRL_TRAFFIC_OVERRIDE
|
9408 LED_CTRL_TRAFFIC_BLINK
|
9409 LED_CTRL_TRAFFIC_LED
);
9412 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
9413 LED_CTRL_TRAFFIC_OVERRIDE
);
9415 if (msleep_interruptible(500))
9418 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
9422 static void tg3_get_ethtool_stats (struct net_device
*dev
,
9423 struct ethtool_stats
*estats
, u64
*tmp_stats
)
9425 struct tg3
*tp
= netdev_priv(dev
);
9426 memcpy(tmp_stats
, tg3_get_estats(tp
), sizeof(tp
->estats
));
9429 #define NVRAM_TEST_SIZE 0x100
9430 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
9431 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
9432 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
9433 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9434 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9436 static int tg3_test_nvram(struct tg3
*tp
)
9440 int i
, j
, k
, err
= 0, size
;
9442 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
)
9445 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
9448 if (magic
== TG3_EEPROM_MAGIC
)
9449 size
= NVRAM_TEST_SIZE
;
9450 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
9451 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
9452 TG3_EEPROM_SB_FORMAT_1
) {
9453 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
9454 case TG3_EEPROM_SB_REVISION_0
:
9455 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
9457 case TG3_EEPROM_SB_REVISION_2
:
9458 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
9460 case TG3_EEPROM_SB_REVISION_3
:
9461 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
9468 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
9469 size
= NVRAM_SELFBOOT_HW_SIZE
;
9473 buf
= kmalloc(size
, GFP_KERNEL
);
9478 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
9479 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
9486 /* Selfboot format */
9487 magic
= be32_to_cpu(buf
[0]);
9488 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
9489 TG3_EEPROM_MAGIC_FW
) {
9490 u8
*buf8
= (u8
*) buf
, csum8
= 0;
9492 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
9493 TG3_EEPROM_SB_REVISION_2
) {
9494 /* For rev 2, the csum doesn't include the MBA. */
9495 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
9497 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
9500 for (i
= 0; i
< size
; i
++)
9513 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
9514 TG3_EEPROM_MAGIC_HW
) {
9515 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
9516 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
9517 u8
*buf8
= (u8
*) buf
;
9519 /* Separate the parity bits and the data bytes. */
9520 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
9521 if ((i
== 0) || (i
== 8)) {
9525 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
9526 parity
[k
++] = buf8
[i
] & msk
;
9533 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
9534 parity
[k
++] = buf8
[i
] & msk
;
9537 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
9538 parity
[k
++] = buf8
[i
] & msk
;
9541 data
[j
++] = buf8
[i
];
9545 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
9546 u8 hw8
= hweight8(data
[i
]);
9548 if ((hw8
& 0x1) && parity
[i
])
9550 else if (!(hw8
& 0x1) && !parity
[i
])
9557 /* Bootstrap checksum at offset 0x10 */
9558 csum
= calc_crc((unsigned char *) buf
, 0x10);
9559 if (csum
!= be32_to_cpu(buf
[0x10/4]))
9562 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9563 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
9564 if (csum
!= be32_to_cpu(buf
[0xfc/4]))
9574 #define TG3_SERDES_TIMEOUT_SEC 2
9575 #define TG3_COPPER_TIMEOUT_SEC 6
9577 static int tg3_test_link(struct tg3
*tp
)
9581 if (!netif_running(tp
->dev
))
9584 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
9585 max
= TG3_SERDES_TIMEOUT_SEC
;
9587 max
= TG3_COPPER_TIMEOUT_SEC
;
9589 for (i
= 0; i
< max
; i
++) {
9590 if (netif_carrier_ok(tp
->dev
))
9593 if (msleep_interruptible(1000))
9600 /* Only test the commonly used registers */
9601 static int tg3_test_registers(struct tg3
*tp
)
9603 int i
, is_5705
, is_5750
;
9604 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
9608 #define TG3_FL_5705 0x1
9609 #define TG3_FL_NOT_5705 0x2
9610 #define TG3_FL_NOT_5788 0x4
9611 #define TG3_FL_NOT_5750 0x8
9615 /* MAC Control Registers */
9616 { MAC_MODE
, TG3_FL_NOT_5705
,
9617 0x00000000, 0x00ef6f8c },
9618 { MAC_MODE
, TG3_FL_5705
,
9619 0x00000000, 0x01ef6b8c },
9620 { MAC_STATUS
, TG3_FL_NOT_5705
,
9621 0x03800107, 0x00000000 },
9622 { MAC_STATUS
, TG3_FL_5705
,
9623 0x03800100, 0x00000000 },
9624 { MAC_ADDR_0_HIGH
, 0x0000,
9625 0x00000000, 0x0000ffff },
9626 { MAC_ADDR_0_LOW
, 0x0000,
9627 0x00000000, 0xffffffff },
9628 { MAC_RX_MTU_SIZE
, 0x0000,
9629 0x00000000, 0x0000ffff },
9630 { MAC_TX_MODE
, 0x0000,
9631 0x00000000, 0x00000070 },
9632 { MAC_TX_LENGTHS
, 0x0000,
9633 0x00000000, 0x00003fff },
9634 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
9635 0x00000000, 0x000007fc },
9636 { MAC_RX_MODE
, TG3_FL_5705
,
9637 0x00000000, 0x000007dc },
9638 { MAC_HASH_REG_0
, 0x0000,
9639 0x00000000, 0xffffffff },
9640 { MAC_HASH_REG_1
, 0x0000,
9641 0x00000000, 0xffffffff },
9642 { MAC_HASH_REG_2
, 0x0000,
9643 0x00000000, 0xffffffff },
9644 { MAC_HASH_REG_3
, 0x0000,
9645 0x00000000, 0xffffffff },
9647 /* Receive Data and Receive BD Initiator Control Registers. */
9648 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
9649 0x00000000, 0xffffffff },
9650 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
9651 0x00000000, 0xffffffff },
9652 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
9653 0x00000000, 0x00000003 },
9654 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
9655 0x00000000, 0xffffffff },
9656 { RCVDBDI_STD_BD
+0, 0x0000,
9657 0x00000000, 0xffffffff },
9658 { RCVDBDI_STD_BD
+4, 0x0000,
9659 0x00000000, 0xffffffff },
9660 { RCVDBDI_STD_BD
+8, 0x0000,
9661 0x00000000, 0xffff0002 },
9662 { RCVDBDI_STD_BD
+0xc, 0x0000,
9663 0x00000000, 0xffffffff },
9665 /* Receive BD Initiator Control Registers. */
9666 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
9667 0x00000000, 0xffffffff },
9668 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
9669 0x00000000, 0x000003ff },
9670 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
9671 0x00000000, 0xffffffff },
9673 /* Host Coalescing Control Registers. */
9674 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
9675 0x00000000, 0x00000004 },
9676 { HOSTCC_MODE
, TG3_FL_5705
,
9677 0x00000000, 0x000000f6 },
9678 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
9679 0x00000000, 0xffffffff },
9680 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
9681 0x00000000, 0x000003ff },
9682 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
9683 0x00000000, 0xffffffff },
9684 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
9685 0x00000000, 0x000003ff },
9686 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
9687 0x00000000, 0xffffffff },
9688 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9689 0x00000000, 0x000000ff },
9690 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
9691 0x00000000, 0xffffffff },
9692 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9693 0x00000000, 0x000000ff },
9694 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9695 0x00000000, 0xffffffff },
9696 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
9697 0x00000000, 0xffffffff },
9698 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9699 0x00000000, 0xffffffff },
9700 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9701 0x00000000, 0x000000ff },
9702 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
9703 0x00000000, 0xffffffff },
9704 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
9705 0x00000000, 0x000000ff },
9706 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
9707 0x00000000, 0xffffffff },
9708 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
9709 0x00000000, 0xffffffff },
9710 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
9711 0x00000000, 0xffffffff },
9712 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
9713 0x00000000, 0xffffffff },
9714 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
9715 0x00000000, 0xffffffff },
9716 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
9717 0xffffffff, 0x00000000 },
9718 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
9719 0xffffffff, 0x00000000 },
9721 /* Buffer Manager Control Registers. */
9722 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
9723 0x00000000, 0x007fff80 },
9724 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
9725 0x00000000, 0x007fffff },
9726 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
9727 0x00000000, 0x0000003f },
9728 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
9729 0x00000000, 0x000001ff },
9730 { BUFMGR_MB_HIGH_WATER
, 0x0000,
9731 0x00000000, 0x000001ff },
9732 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
9733 0xffffffff, 0x00000000 },
9734 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
9735 0xffffffff, 0x00000000 },
9737 /* Mailbox Registers */
9738 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
9739 0x00000000, 0x000001ff },
9740 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
9741 0x00000000, 0x000001ff },
9742 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
9743 0x00000000, 0x000007ff },
9744 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
9745 0x00000000, 0x000001ff },
9747 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9750 is_5705
= is_5750
= 0;
9751 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
9753 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
9757 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
9758 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
9761 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
9764 if ((tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
9765 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
9768 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
9771 offset
= (u32
) reg_tbl
[i
].offset
;
9772 read_mask
= reg_tbl
[i
].read_mask
;
9773 write_mask
= reg_tbl
[i
].write_mask
;
9775 /* Save the original register content */
9776 save_val
= tr32(offset
);
9778 /* Determine the read-only value. */
9779 read_val
= save_val
& read_mask
;
9781 /* Write zero to the register, then make sure the read-only bits
9782 * are not changed and the read/write bits are all zeros.
9788 /* Test the read-only and read/write bits. */
9789 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
9792 /* Write ones to all the bits defined by RdMask and WrMask, then
9793 * make sure the read-only bits are not changed and the
9794 * read/write bits are all ones.
9796 tw32(offset
, read_mask
| write_mask
);
9800 /* Test the read-only bits. */
9801 if ((val
& read_mask
) != read_val
)
9804 /* Test the read/write bits. */
9805 if ((val
& write_mask
) != write_mask
)
9808 tw32(offset
, save_val
);
9814 if (netif_msg_hw(tp
))
9815 printk(KERN_ERR PFX
"Register test failed at offset %x\n",
9817 tw32(offset
, save_val
);
9821 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
9823 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9827 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
9828 for (j
= 0; j
< len
; j
+= 4) {
9831 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
9832 tg3_read_mem(tp
, offset
+ j
, &val
);
9833 if (val
!= test_pattern
[i
])
9840 static int tg3_test_memory(struct tg3
*tp
)
9842 static struct mem_entry
{
9845 } mem_tbl_570x
[] = {
9846 { 0x00000000, 0x00b50},
9847 { 0x00002000, 0x1c000},
9848 { 0xffffffff, 0x00000}
9849 }, mem_tbl_5705
[] = {
9850 { 0x00000100, 0x0000c},
9851 { 0x00000200, 0x00008},
9852 { 0x00004000, 0x00800},
9853 { 0x00006000, 0x01000},
9854 { 0x00008000, 0x02000},
9855 { 0x00010000, 0x0e000},
9856 { 0xffffffff, 0x00000}
9857 }, mem_tbl_5755
[] = {
9858 { 0x00000200, 0x00008},
9859 { 0x00004000, 0x00800},
9860 { 0x00006000, 0x00800},
9861 { 0x00008000, 0x02000},
9862 { 0x00010000, 0x0c000},
9863 { 0xffffffff, 0x00000}
9864 }, mem_tbl_5906
[] = {
9865 { 0x00000200, 0x00008},
9866 { 0x00004000, 0x00400},
9867 { 0x00006000, 0x00400},
9868 { 0x00008000, 0x01000},
9869 { 0x00010000, 0x01000},
9870 { 0xffffffff, 0x00000}
9872 struct mem_entry
*mem_tbl
;
9876 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
9877 mem_tbl
= mem_tbl_5755
;
9878 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
9879 mem_tbl
= mem_tbl_5906
;
9880 else if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)
9881 mem_tbl
= mem_tbl_5705
;
9883 mem_tbl
= mem_tbl_570x
;
9885 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
9886 if ((err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
,
9887 mem_tbl
[i
].len
)) != 0)
9894 #define TG3_MAC_LOOPBACK 0
9895 #define TG3_PHY_LOOPBACK 1
9897 static int tg3_run_loopback(struct tg3
*tp
, int loopback_mode
)
9899 u32 mac_mode
, rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
9900 u32 desc_idx
, coal_now
;
9901 struct sk_buff
*skb
, *rx_skb
;
9904 int num_pkts
, tx_len
, rx_len
, i
, err
;
9905 struct tg3_rx_buffer_desc
*desc
;
9906 struct tg3_napi
*tnapi
, *rnapi
;
9907 struct tg3_rx_prodring_set
*tpr
= &tp
->prodring
[0];
9909 tnapi
= &tp
->napi
[0];
9910 rnapi
= &tp
->napi
[0];
9911 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
9913 if (loopback_mode
== TG3_MAC_LOOPBACK
) {
9914 /* HW errata - mac loopback fails in some cases on 5780.
9915 * Normal traffic and PHY loopback are not affected by
9918 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
)
9921 mac_mode
= (tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
) |
9922 MAC_MODE_PORT_INT_LPBACK
;
9923 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
9924 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9925 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
9926 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9928 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9929 tw32(MAC_MODE
, mac_mode
);
9930 } else if (loopback_mode
== TG3_PHY_LOOPBACK
) {
9933 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
9934 tg3_phy_fet_toggle_apd(tp
, false);
9935 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED100
;
9937 val
= BMCR_LOOPBACK
| BMCR_FULLDPLX
| BMCR_SPEED1000
;
9939 tg3_phy_toggle_automdix(tp
, 0);
9941 tg3_writephy(tp
, MII_BMCR
, val
);
9944 mac_mode
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
9945 if (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) {
9946 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
9947 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x1800);
9948 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
9950 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
9952 /* reset to prevent losing 1st rx packet intermittently */
9953 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
) {
9954 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
9956 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
9958 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) {
9959 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)
9960 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
9961 else if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5411
)
9962 mac_mode
|= MAC_MODE_LINK_POLARITY
;
9963 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
9964 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
9966 tw32(MAC_MODE
, mac_mode
);
9974 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
9978 tx_data
= skb_put(skb
, tx_len
);
9979 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
9980 memset(tx_data
+ 6, 0x0, 8);
9982 tw32(MAC_RX_MTU_SIZE
, tx_len
+ 4);
9984 for (i
= 14; i
< tx_len
; i
++)
9985 tx_data
[i
] = (u8
) (i
& 0xff);
9987 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
9989 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
9994 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
9998 tg3_set_txd(tnapi
, tnapi
->tx_prod
, map
, tx_len
, 0, 1);
10003 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
10004 tr32_mailbox(tnapi
->prodmbox
);
10008 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
10009 for (i
= 0; i
< 25; i
++) {
10010 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10015 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
10016 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
10017 if ((tx_idx
== tnapi
->tx_prod
) &&
10018 (rx_idx
== (rx_start_idx
+ num_pkts
)))
10022 pci_unmap_single(tp
->pdev
, map
, tx_len
, PCI_DMA_TODEVICE
);
10023 dev_kfree_skb(skb
);
10025 if (tx_idx
!= tnapi
->tx_prod
)
10028 if (rx_idx
!= rx_start_idx
+ num_pkts
)
10031 desc
= &rnapi
->rx_rcb
[rx_start_idx
];
10032 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
10033 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
10034 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
10037 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
10038 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
10041 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) - 4;
10042 if (rx_len
!= tx_len
)
10045 rx_skb
= tpr
->rx_std_buffers
[desc_idx
].skb
;
10047 map
= pci_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
], mapping
);
10048 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
, PCI_DMA_FROMDEVICE
);
10050 for (i
= 14; i
< tx_len
; i
++) {
10051 if (*(rx_skb
->data
+ i
) != (u8
) (i
& 0xff))
10056 /* tg3_free_rings will unmap and free the rx_skb */
10061 #define TG3_MAC_LOOPBACK_FAILED 1
10062 #define TG3_PHY_LOOPBACK_FAILED 2
10063 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10064 TG3_PHY_LOOPBACK_FAILED)
10066 static int tg3_test_loopback(struct tg3
*tp
)
10071 if (!netif_running(tp
->dev
))
10072 return TG3_LOOPBACK_FAILED
;
10074 err
= tg3_reset_hw(tp
, 1);
10076 return TG3_LOOPBACK_FAILED
;
10078 /* Turn off gphy autopowerdown. */
10079 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10080 tg3_phy_toggle_apd(tp
, false);
10082 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10086 tw32(TG3_CPMU_MUTEX_REQ
, CPMU_MUTEX_REQ_DRIVER
);
10088 /* Wait for up to 40 microseconds to acquire lock. */
10089 for (i
= 0; i
< 4; i
++) {
10090 status
= tr32(TG3_CPMU_MUTEX_GNT
);
10091 if (status
== CPMU_MUTEX_GNT_DRIVER
)
10096 if (status
!= CPMU_MUTEX_GNT_DRIVER
)
10097 return TG3_LOOPBACK_FAILED
;
10099 /* Turn off link-based power management. */
10100 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
10101 tw32(TG3_CPMU_CTRL
,
10102 cpmuctrl
& ~(CPMU_CTRL_LINK_SPEED_MODE
|
10103 CPMU_CTRL_LINK_AWARE_MODE
));
10106 if (tg3_run_loopback(tp
, TG3_MAC_LOOPBACK
))
10107 err
|= TG3_MAC_LOOPBACK_FAILED
;
10109 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
) {
10110 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
10112 /* Release the mutex */
10113 tw32(TG3_CPMU_MUTEX_GNT
, CPMU_MUTEX_GNT_DRIVER
);
10116 if (!(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) &&
10117 !(tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)) {
10118 if (tg3_run_loopback(tp
, TG3_PHY_LOOPBACK
))
10119 err
|= TG3_PHY_LOOPBACK_FAILED
;
10122 /* Re-enable gphy autopowerdown. */
10123 if (tp
->tg3_flags3
& TG3_FLG3_PHY_ENABLE_APD
)
10124 tg3_phy_toggle_apd(tp
, true);
10129 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
10132 struct tg3
*tp
= netdev_priv(dev
);
10134 if (tp
->link_config
.phy_is_low_power
)
10135 tg3_set_power_state(tp
, PCI_D0
);
10137 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
10139 if (tg3_test_nvram(tp
) != 0) {
10140 etest
->flags
|= ETH_TEST_FL_FAILED
;
10143 if (tg3_test_link(tp
) != 0) {
10144 etest
->flags
|= ETH_TEST_FL_FAILED
;
10147 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
10148 int err
, err2
= 0, irq_sync
= 0;
10150 if (netif_running(dev
)) {
10152 tg3_netif_stop(tp
);
10156 tg3_full_lock(tp
, irq_sync
);
10158 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
10159 err
= tg3_nvram_lock(tp
);
10160 tg3_halt_cpu(tp
, RX_CPU_BASE
);
10161 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
10162 tg3_halt_cpu(tp
, TX_CPU_BASE
);
10164 tg3_nvram_unlock(tp
);
10166 if (tp
->tg3_flags2
& TG3_FLG2_MII_SERDES
)
10169 if (tg3_test_registers(tp
) != 0) {
10170 etest
->flags
|= ETH_TEST_FL_FAILED
;
10173 if (tg3_test_memory(tp
) != 0) {
10174 etest
->flags
|= ETH_TEST_FL_FAILED
;
10177 if ((data
[4] = tg3_test_loopback(tp
)) != 0)
10178 etest
->flags
|= ETH_TEST_FL_FAILED
;
10180 tg3_full_unlock(tp
);
10182 if (tg3_test_interrupt(tp
) != 0) {
10183 etest
->flags
|= ETH_TEST_FL_FAILED
;
10187 tg3_full_lock(tp
, 0);
10189 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10190 if (netif_running(dev
)) {
10191 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
10192 err2
= tg3_restart_hw(tp
, 1);
10194 tg3_netif_start(tp
);
10197 tg3_full_unlock(tp
);
10199 if (irq_sync
&& !err2
)
10202 if (tp
->link_config
.phy_is_low_power
)
10203 tg3_set_power_state(tp
, PCI_D3hot
);
10207 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10209 struct mii_ioctl_data
*data
= if_mii(ifr
);
10210 struct tg3
*tp
= netdev_priv(dev
);
10213 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
10214 if (!(tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
))
10216 return phy_mii_ioctl(tp
->mdio_bus
->phy_map
[PHY_ADDR
], data
, cmd
);
10221 data
->phy_id
= PHY_ADDR
;
10224 case SIOCGMIIREG
: {
10227 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10228 break; /* We have no PHY */
10230 if (tp
->link_config
.phy_is_low_power
)
10233 spin_lock_bh(&tp
->lock
);
10234 err
= tg3_readphy(tp
, data
->reg_num
& 0x1f, &mii_regval
);
10235 spin_unlock_bh(&tp
->lock
);
10237 data
->val_out
= mii_regval
;
10243 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
10244 break; /* We have no PHY */
10246 if (!capable(CAP_NET_ADMIN
))
10249 if (tp
->link_config
.phy_is_low_power
)
10252 spin_lock_bh(&tp
->lock
);
10253 err
= tg3_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
10254 spin_unlock_bh(&tp
->lock
);
10262 return -EOPNOTSUPP
;
10265 #if TG3_VLAN_TAG_USED
10266 static void tg3_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
10268 struct tg3
*tp
= netdev_priv(dev
);
10270 if (!netif_running(dev
)) {
10275 tg3_netif_stop(tp
);
10277 tg3_full_lock(tp
, 0);
10281 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10282 __tg3_set_rx_mode(dev
);
10284 tg3_netif_start(tp
);
10286 tg3_full_unlock(tp
);
10290 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10292 struct tg3
*tp
= netdev_priv(dev
);
10294 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
10298 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
10300 struct tg3
*tp
= netdev_priv(dev
);
10301 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
10302 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
10304 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
)) {
10305 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
10306 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
10307 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
10308 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
10311 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
10312 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
10313 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
10314 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
10315 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
10316 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
10317 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
10318 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
10319 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
10320 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
10323 /* No rx interrupts will be generated if both are zero */
10324 if ((ec
->rx_coalesce_usecs
== 0) &&
10325 (ec
->rx_max_coalesced_frames
== 0))
10328 /* No tx interrupts will be generated if both are zero */
10329 if ((ec
->tx_coalesce_usecs
== 0) &&
10330 (ec
->tx_max_coalesced_frames
== 0))
10333 /* Only copy relevant parameters, ignore all others. */
10334 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
10335 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
10336 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
10337 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
10338 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
10339 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
10340 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
10341 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
10342 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
10344 if (netif_running(dev
)) {
10345 tg3_full_lock(tp
, 0);
10346 __tg3_set_coalesce(tp
, &tp
->coal
);
10347 tg3_full_unlock(tp
);
10352 static const struct ethtool_ops tg3_ethtool_ops
= {
10353 .get_settings
= tg3_get_settings
,
10354 .set_settings
= tg3_set_settings
,
10355 .get_drvinfo
= tg3_get_drvinfo
,
10356 .get_regs_len
= tg3_get_regs_len
,
10357 .get_regs
= tg3_get_regs
,
10358 .get_wol
= tg3_get_wol
,
10359 .set_wol
= tg3_set_wol
,
10360 .get_msglevel
= tg3_get_msglevel
,
10361 .set_msglevel
= tg3_set_msglevel
,
10362 .nway_reset
= tg3_nway_reset
,
10363 .get_link
= ethtool_op_get_link
,
10364 .get_eeprom_len
= tg3_get_eeprom_len
,
10365 .get_eeprom
= tg3_get_eeprom
,
10366 .set_eeprom
= tg3_set_eeprom
,
10367 .get_ringparam
= tg3_get_ringparam
,
10368 .set_ringparam
= tg3_set_ringparam
,
10369 .get_pauseparam
= tg3_get_pauseparam
,
10370 .set_pauseparam
= tg3_set_pauseparam
,
10371 .get_rx_csum
= tg3_get_rx_csum
,
10372 .set_rx_csum
= tg3_set_rx_csum
,
10373 .set_tx_csum
= tg3_set_tx_csum
,
10374 .set_sg
= ethtool_op_set_sg
,
10375 .set_tso
= tg3_set_tso
,
10376 .self_test
= tg3_self_test
,
10377 .get_strings
= tg3_get_strings
,
10378 .phys_id
= tg3_phys_id
,
10379 .get_ethtool_stats
= tg3_get_ethtool_stats
,
10380 .get_coalesce
= tg3_get_coalesce
,
10381 .set_coalesce
= tg3_set_coalesce
,
10382 .get_sset_count
= tg3_get_sset_count
,
10385 static void __devinit
tg3_get_eeprom_size(struct tg3
*tp
)
10387 u32 cursize
, val
, magic
;
10389 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
10391 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
10394 if ((magic
!= TG3_EEPROM_MAGIC
) &&
10395 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
10396 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
10400 * Size the chip by reading offsets at increasing powers of two.
10401 * When we encounter our validation signature, we know the addressing
10402 * has wrapped around, and thus have our chip size.
10406 while (cursize
< tp
->nvram_size
) {
10407 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
10416 tp
->nvram_size
= cursize
;
10419 static void __devinit
tg3_get_nvram_size(struct tg3
*tp
)
10423 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
10424 tg3_nvram_read(tp
, 0, &val
) != 0)
10427 /* Selfboot format */
10428 if (val
!= TG3_EEPROM_MAGIC
) {
10429 tg3_get_eeprom_size(tp
);
10433 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
10435 /* This is confusing. We want to operate on the
10436 * 16-bit value at offset 0xf2. The tg3_nvram_read()
10437 * call will read from NVRAM and byteswap the data
10438 * according to the byteswapping settings for all
10439 * other register accesses. This ensures the data we
10440 * want will always reside in the lower 16-bits.
10441 * However, the data in NVRAM is in LE format, which
10442 * means the data from the NVRAM read will always be
10443 * opposite the endianness of the CPU. The 16-bit
10444 * byteswap then brings the data to CPU endianness.
10446 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
10450 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10453 static void __devinit
tg3_get_nvram_info(struct tg3
*tp
)
10457 nvcfg1
= tr32(NVRAM_CFG1
);
10458 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
10459 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10461 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10462 tw32(NVRAM_CFG1
, nvcfg1
);
10465 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
) ||
10466 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
10467 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
10468 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
10469 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10470 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10471 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10473 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
10474 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10475 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
10477 case FLASH_VENDOR_ATMEL_EEPROM
:
10478 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10479 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10480 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10482 case FLASH_VENDOR_ST
:
10483 tp
->nvram_jedecnum
= JEDEC_ST
;
10484 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
10485 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10487 case FLASH_VENDOR_SAIFUN
:
10488 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
10489 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
10491 case FLASH_VENDOR_SST_SMALL
:
10492 case FLASH_VENDOR_SST_LARGE
:
10493 tp
->nvram_jedecnum
= JEDEC_SST
;
10494 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
10498 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10499 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
10500 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10504 static void __devinit
tg3_get_5752_nvram_info(struct tg3
*tp
)
10508 nvcfg1
= tr32(NVRAM_CFG1
);
10510 /* NVRAM protection for TPM */
10511 if (nvcfg1
& (1 << 27))
10512 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10514 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10515 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
10516 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
10517 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10518 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10520 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10521 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10522 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10523 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10525 case FLASH_5752VENDOR_ST_M45PE10
:
10526 case FLASH_5752VENDOR_ST_M45PE20
:
10527 case FLASH_5752VENDOR_ST_M45PE40
:
10528 tp
->nvram_jedecnum
= JEDEC_ST
;
10529 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10530 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10534 if (tp
->tg3_flags2
& TG3_FLG2_FLASH
) {
10535 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10536 case FLASH_5752PAGE_SIZE_256
:
10537 tp
->nvram_pagesize
= 256;
10539 case FLASH_5752PAGE_SIZE_512
:
10540 tp
->nvram_pagesize
= 512;
10542 case FLASH_5752PAGE_SIZE_1K
:
10543 tp
->nvram_pagesize
= 1024;
10545 case FLASH_5752PAGE_SIZE_2K
:
10546 tp
->nvram_pagesize
= 2048;
10548 case FLASH_5752PAGE_SIZE_4K
:
10549 tp
->nvram_pagesize
= 4096;
10551 case FLASH_5752PAGE_SIZE_264
:
10552 tp
->nvram_pagesize
= 264;
10556 /* For eeprom, set pagesize to maximum eeprom size */
10557 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10559 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10560 tw32(NVRAM_CFG1
, nvcfg1
);
10564 static void __devinit
tg3_get_5755_nvram_info(struct tg3
*tp
)
10566 u32 nvcfg1
, protect
= 0;
10568 nvcfg1
= tr32(NVRAM_CFG1
);
10570 /* NVRAM protection for TPM */
10571 if (nvcfg1
& (1 << 27)) {
10572 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10576 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10578 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10579 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10580 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10581 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
10582 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10583 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10584 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10585 tp
->nvram_pagesize
= 264;
10586 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
10587 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
10588 tp
->nvram_size
= (protect
? 0x3e200 :
10589 TG3_NVRAM_SIZE_512KB
);
10590 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
10591 tp
->nvram_size
= (protect
? 0x1f200 :
10592 TG3_NVRAM_SIZE_256KB
);
10594 tp
->nvram_size
= (protect
? 0x1f200 :
10595 TG3_NVRAM_SIZE_128KB
);
10597 case FLASH_5752VENDOR_ST_M45PE10
:
10598 case FLASH_5752VENDOR_ST_M45PE20
:
10599 case FLASH_5752VENDOR_ST_M45PE40
:
10600 tp
->nvram_jedecnum
= JEDEC_ST
;
10601 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10602 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10603 tp
->nvram_pagesize
= 256;
10604 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
10605 tp
->nvram_size
= (protect
?
10606 TG3_NVRAM_SIZE_64KB
:
10607 TG3_NVRAM_SIZE_128KB
);
10608 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
10609 tp
->nvram_size
= (protect
?
10610 TG3_NVRAM_SIZE_64KB
:
10611 TG3_NVRAM_SIZE_256KB
);
10613 tp
->nvram_size
= (protect
?
10614 TG3_NVRAM_SIZE_128KB
:
10615 TG3_NVRAM_SIZE_512KB
);
10620 static void __devinit
tg3_get_5787_nvram_info(struct tg3
*tp
)
10624 nvcfg1
= tr32(NVRAM_CFG1
);
10626 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10627 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
10628 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10629 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
10630 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10631 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10632 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10633 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10635 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10636 tw32(NVRAM_CFG1
, nvcfg1
);
10638 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10639 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
10640 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
10641 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
10642 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10643 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10644 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10645 tp
->nvram_pagesize
= 264;
10647 case FLASH_5752VENDOR_ST_M45PE10
:
10648 case FLASH_5752VENDOR_ST_M45PE20
:
10649 case FLASH_5752VENDOR_ST_M45PE40
:
10650 tp
->nvram_jedecnum
= JEDEC_ST
;
10651 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10652 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10653 tp
->nvram_pagesize
= 256;
10658 static void __devinit
tg3_get_5761_nvram_info(struct tg3
*tp
)
10660 u32 nvcfg1
, protect
= 0;
10662 nvcfg1
= tr32(NVRAM_CFG1
);
10664 /* NVRAM protection for TPM */
10665 if (nvcfg1
& (1 << 27)) {
10666 tp
->tg3_flags2
|= TG3_FLG2_PROTECTED_NVRAM
;
10670 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
10672 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10673 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10674 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10675 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10676 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10677 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10678 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10679 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10680 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10681 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10682 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10683 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10684 tp
->nvram_pagesize
= 256;
10686 case FLASH_5761VENDOR_ST_A_M45PE20
:
10687 case FLASH_5761VENDOR_ST_A_M45PE40
:
10688 case FLASH_5761VENDOR_ST_A_M45PE80
:
10689 case FLASH_5761VENDOR_ST_A_M45PE16
:
10690 case FLASH_5761VENDOR_ST_M_M45PE20
:
10691 case FLASH_5761VENDOR_ST_M_M45PE40
:
10692 case FLASH_5761VENDOR_ST_M_M45PE80
:
10693 case FLASH_5761VENDOR_ST_M_M45PE16
:
10694 tp
->nvram_jedecnum
= JEDEC_ST
;
10695 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10696 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10697 tp
->nvram_pagesize
= 256;
10702 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
10705 case FLASH_5761VENDOR_ATMEL_ADB161D
:
10706 case FLASH_5761VENDOR_ATMEL_MDB161D
:
10707 case FLASH_5761VENDOR_ST_A_M45PE16
:
10708 case FLASH_5761VENDOR_ST_M_M45PE16
:
10709 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
10711 case FLASH_5761VENDOR_ATMEL_ADB081D
:
10712 case FLASH_5761VENDOR_ATMEL_MDB081D
:
10713 case FLASH_5761VENDOR_ST_A_M45PE80
:
10714 case FLASH_5761VENDOR_ST_M_M45PE80
:
10715 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
10717 case FLASH_5761VENDOR_ATMEL_ADB041D
:
10718 case FLASH_5761VENDOR_ATMEL_MDB041D
:
10719 case FLASH_5761VENDOR_ST_A_M45PE40
:
10720 case FLASH_5761VENDOR_ST_M_M45PE40
:
10721 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10723 case FLASH_5761VENDOR_ATMEL_ADB021D
:
10724 case FLASH_5761VENDOR_ATMEL_MDB021D
:
10725 case FLASH_5761VENDOR_ST_A_M45PE20
:
10726 case FLASH_5761VENDOR_ST_M_M45PE20
:
10727 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10733 static void __devinit
tg3_get_5906_nvram_info(struct tg3
*tp
)
10735 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10736 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10737 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10740 static void __devinit
tg3_get_57780_nvram_info(struct tg3
*tp
)
10744 nvcfg1
= tr32(NVRAM_CFG1
);
10746 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10747 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
10748 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
10749 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10750 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10751 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
10753 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
10754 tw32(NVRAM_CFG1
, nvcfg1
);
10756 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10757 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10758 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10759 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10760 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10761 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10762 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10763 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
10764 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10765 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10767 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10768 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
10769 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
10770 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
10771 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10773 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
10774 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
10775 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10777 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
10778 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
10779 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10783 case FLASH_5752VENDOR_ST_M45PE10
:
10784 case FLASH_5752VENDOR_ST_M45PE20
:
10785 case FLASH_5752VENDOR_ST_M45PE40
:
10786 tp
->nvram_jedecnum
= JEDEC_ST
;
10787 tp
->tg3_flags
|= TG3_FLAG_NVRAM_BUFFERED
;
10788 tp
->tg3_flags2
|= TG3_FLG2_FLASH
;
10790 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
10791 case FLASH_5752VENDOR_ST_M45PE10
:
10792 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
10794 case FLASH_5752VENDOR_ST_M45PE20
:
10795 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
10797 case FLASH_5752VENDOR_ST_M45PE40
:
10798 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
10803 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM
;
10807 switch (nvcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
10808 case FLASH_5752PAGE_SIZE_256
:
10809 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10810 tp
->nvram_pagesize
= 256;
10812 case FLASH_5752PAGE_SIZE_512
:
10813 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10814 tp
->nvram_pagesize
= 512;
10816 case FLASH_5752PAGE_SIZE_1K
:
10817 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10818 tp
->nvram_pagesize
= 1024;
10820 case FLASH_5752PAGE_SIZE_2K
:
10821 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10822 tp
->nvram_pagesize
= 2048;
10824 case FLASH_5752PAGE_SIZE_4K
:
10825 tp
->tg3_flags3
|= TG3_FLG3_NO_NVRAM_ADDR_TRANS
;
10826 tp
->nvram_pagesize
= 4096;
10828 case FLASH_5752PAGE_SIZE_264
:
10829 tp
->nvram_pagesize
= 264;
10831 case FLASH_5752PAGE_SIZE_528
:
10832 tp
->nvram_pagesize
= 528;
10837 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10838 static void __devinit
tg3_nvram_init(struct tg3
*tp
)
10840 tw32_f(GRC_EEPROM_ADDR
,
10841 (EEPROM_ADDR_FSM_RESET
|
10842 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
10843 EEPROM_ADDR_CLKPERD_SHIFT
)));
10847 /* Enable seeprom accesses. */
10848 tw32_f(GRC_LOCAL_CTRL
,
10849 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
10852 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
10853 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) {
10854 tp
->tg3_flags
|= TG3_FLAG_NVRAM
;
10856 if (tg3_nvram_lock(tp
)) {
10857 printk(KERN_WARNING PFX
"%s: Cannot get nvarm lock, "
10858 "tg3_nvram_init failed.\n", tp
->dev
->name
);
10861 tg3_enable_nvram_access(tp
);
10863 tp
->nvram_size
= 0;
10865 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
10866 tg3_get_5752_nvram_info(tp
);
10867 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
10868 tg3_get_5755_nvram_info(tp
);
10869 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
10870 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
10871 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
10872 tg3_get_5787_nvram_info(tp
);
10873 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
)
10874 tg3_get_5761_nvram_info(tp
);
10875 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
10876 tg3_get_5906_nvram_info(tp
);
10877 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
10878 tg3_get_57780_nvram_info(tp
);
10880 tg3_get_nvram_info(tp
);
10882 if (tp
->nvram_size
== 0)
10883 tg3_get_nvram_size(tp
);
10885 tg3_disable_nvram_access(tp
);
10886 tg3_nvram_unlock(tp
);
10889 tp
->tg3_flags
&= ~(TG3_FLAG_NVRAM
| TG3_FLAG_NVRAM_BUFFERED
);
10891 tg3_get_eeprom_size(tp
);
10895 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
10896 u32 offset
, u32 len
, u8
*buf
)
10901 for (i
= 0; i
< len
; i
+= 4) {
10907 memcpy(&data
, buf
+ i
, 4);
10910 * The SEEPROM interface expects the data to always be opposite
10911 * the native endian format. We accomplish this by reversing
10912 * all the operations that would have been performed on the
10913 * data from a call to tg3_nvram_read_be32().
10915 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
10917 val
= tr32(GRC_EEPROM_ADDR
);
10918 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
10920 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
10922 tw32(GRC_EEPROM_ADDR
, val
|
10923 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
10924 (addr
& EEPROM_ADDR_ADDR_MASK
) |
10925 EEPROM_ADDR_START
|
10926 EEPROM_ADDR_WRITE
);
10928 for (j
= 0; j
< 1000; j
++) {
10929 val
= tr32(GRC_EEPROM_ADDR
);
10931 if (val
& EEPROM_ADDR_COMPLETE
)
10935 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
10944 /* offset and length are dword aligned */
10945 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
10949 u32 pagesize
= tp
->nvram_pagesize
;
10950 u32 pagemask
= pagesize
- 1;
10954 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
10960 u32 phy_addr
, page_off
, size
;
10962 phy_addr
= offset
& ~pagemask
;
10964 for (j
= 0; j
< pagesize
; j
+= 4) {
10965 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
10966 (__be32
*) (tmp
+ j
));
10973 page_off
= offset
& pagemask
;
10980 memcpy(tmp
+ page_off
, buf
, size
);
10982 offset
= offset
+ (pagesize
- page_off
);
10984 tg3_enable_nvram_access(tp
);
10987 * Before we can erase the flash page, we need
10988 * to issue a special "write enable" command.
10990 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
10992 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
10995 /* Erase the target page */
10996 tw32(NVRAM_ADDR
, phy_addr
);
10998 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
10999 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
11001 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11004 /* Issue another write enable to start the write. */
11005 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11007 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
11010 for (j
= 0; j
< pagesize
; j
+= 4) {
11013 data
= *((__be32
*) (tmp
+ j
));
11015 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11017 tw32(NVRAM_ADDR
, phy_addr
+ j
);
11019 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
11023 nvram_cmd
|= NVRAM_CMD_FIRST
;
11024 else if (j
== (pagesize
- 4))
11025 nvram_cmd
|= NVRAM_CMD_LAST
;
11027 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11034 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
11035 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
11042 /* offset and length are dword aligned */
11043 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
11048 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
11049 u32 page_off
, phy_addr
, nvram_cmd
;
11052 memcpy(&data
, buf
+ i
, 4);
11053 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
11055 page_off
= offset
% tp
->nvram_pagesize
;
11057 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
11059 tw32(NVRAM_ADDR
, phy_addr
);
11061 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
11063 if ((page_off
== 0) || (i
== 0))
11064 nvram_cmd
|= NVRAM_CMD_FIRST
;
11065 if (page_off
== (tp
->nvram_pagesize
- 4))
11066 nvram_cmd
|= NVRAM_CMD_LAST
;
11068 if (i
== (len
- 4))
11069 nvram_cmd
|= NVRAM_CMD_LAST
;
11071 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5752
&&
11072 !(tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) &&
11073 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
11074 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
11076 if ((ret
= tg3_nvram_exec_cmd(tp
,
11077 NVRAM_CMD_WREN
| NVRAM_CMD_GO
|
11082 if (!(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11083 /* We always do complete word writes to eeprom. */
11084 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
11087 if ((ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
)))
11093 /* offset and length are dword aligned */
11094 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
11098 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11099 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
11100 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
11104 if (!(tp
->tg3_flags
& TG3_FLAG_NVRAM
)) {
11105 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
11110 ret
= tg3_nvram_lock(tp
);
11114 tg3_enable_nvram_access(tp
);
11115 if ((tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) &&
11116 !(tp
->tg3_flags2
& TG3_FLG2_PROTECTED_NVRAM
))
11117 tw32(NVRAM_WRITE1
, 0x406);
11119 grc_mode
= tr32(GRC_MODE
);
11120 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
11122 if ((tp
->tg3_flags
& TG3_FLAG_NVRAM_BUFFERED
) ||
11123 !(tp
->tg3_flags2
& TG3_FLG2_FLASH
)) {
11125 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
11129 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
11133 grc_mode
= tr32(GRC_MODE
);
11134 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
11136 tg3_disable_nvram_access(tp
);
11137 tg3_nvram_unlock(tp
);
11140 if (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
) {
11141 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
11148 struct subsys_tbl_ent
{
11149 u16 subsys_vendor
, subsys_devid
;
11153 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
11154 /* Broadcom boards. */
11155 { PCI_VENDOR_ID_BROADCOM
, 0x1644, PHY_ID_BCM5401
}, /* BCM95700A6 */
11156 { PCI_VENDOR_ID_BROADCOM
, 0x0001, PHY_ID_BCM5701
}, /* BCM95701A5 */
11157 { PCI_VENDOR_ID_BROADCOM
, 0x0002, PHY_ID_BCM8002
}, /* BCM95700T6 */
11158 { PCI_VENDOR_ID_BROADCOM
, 0x0003, 0 }, /* BCM95700A9 */
11159 { PCI_VENDOR_ID_BROADCOM
, 0x0005, PHY_ID_BCM5701
}, /* BCM95701T1 */
11160 { PCI_VENDOR_ID_BROADCOM
, 0x0006, PHY_ID_BCM5701
}, /* BCM95701T8 */
11161 { PCI_VENDOR_ID_BROADCOM
, 0x0007, 0 }, /* BCM95701A7 */
11162 { PCI_VENDOR_ID_BROADCOM
, 0x0008, PHY_ID_BCM5701
}, /* BCM95701A10 */
11163 { PCI_VENDOR_ID_BROADCOM
, 0x8008, PHY_ID_BCM5701
}, /* BCM95701A12 */
11164 { PCI_VENDOR_ID_BROADCOM
, 0x0009, PHY_ID_BCM5703
}, /* BCM95703Ax1 */
11165 { PCI_VENDOR_ID_BROADCOM
, 0x8009, PHY_ID_BCM5703
}, /* BCM95703Ax2 */
11168 { PCI_VENDOR_ID_3COM
, 0x1000, PHY_ID_BCM5401
}, /* 3C996T */
11169 { PCI_VENDOR_ID_3COM
, 0x1006, PHY_ID_BCM5701
}, /* 3C996BT */
11170 { PCI_VENDOR_ID_3COM
, 0x1004, 0 }, /* 3C996SX */
11171 { PCI_VENDOR_ID_3COM
, 0x1007, PHY_ID_BCM5701
}, /* 3C1000T */
11172 { PCI_VENDOR_ID_3COM
, 0x1008, PHY_ID_BCM5701
}, /* 3C940BR01 */
11175 { PCI_VENDOR_ID_DELL
, 0x00d1, PHY_ID_BCM5401
}, /* VIPER */
11176 { PCI_VENDOR_ID_DELL
, 0x0106, PHY_ID_BCM5401
}, /* JAGUAR */
11177 { PCI_VENDOR_ID_DELL
, 0x0109, PHY_ID_BCM5411
}, /* MERLOT */
11178 { PCI_VENDOR_ID_DELL
, 0x010a, PHY_ID_BCM5411
}, /* SLIM_MERLOT */
11180 /* Compaq boards. */
11181 { PCI_VENDOR_ID_COMPAQ
, 0x007c, PHY_ID_BCM5701
}, /* BANSHEE */
11182 { PCI_VENDOR_ID_COMPAQ
, 0x009a, PHY_ID_BCM5701
}, /* BANSHEE_2 */
11183 { PCI_VENDOR_ID_COMPAQ
, 0x007d, 0 }, /* CHANGELING */
11184 { PCI_VENDOR_ID_COMPAQ
, 0x0085, PHY_ID_BCM5701
}, /* NC7780 */
11185 { PCI_VENDOR_ID_COMPAQ
, 0x0099, PHY_ID_BCM5701
}, /* NC7780_2 */
11188 { PCI_VENDOR_ID_IBM
, 0x0281, 0 } /* IBM??? */
11191 static inline struct subsys_tbl_ent
*lookup_by_subsys(struct tg3
*tp
)
11195 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
11196 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
11197 tp
->pdev
->subsystem_vendor
) &&
11198 (subsys_id_to_phy_id
[i
].subsys_devid
==
11199 tp
->pdev
->subsystem_device
))
11200 return &subsys_id_to_phy_id
[i
];
11205 static void __devinit
tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
11210 /* On some early chips the SRAM cannot be accessed in D3hot state,
11211 * so need make sure we're in D0.
11213 pci_read_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
11214 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
11215 pci_write_config_word(tp
->pdev
, tp
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
11218 /* Make sure register accesses (indirect or otherwise)
11219 * will function correctly.
11221 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11222 tp
->misc_host_ctrl
);
11224 /* The memory arbiter has to be enabled in order for SRAM accesses
11225 * to succeed. Normally on powerup the tg3 chip firmware will make
11226 * sure it is enabled, but other entities such as system netboot
11227 * code might disable it.
11229 val
= tr32(MEMARB_MODE
);
11230 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
11232 tp
->phy_id
= PHY_ID_INVALID
;
11233 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11235 /* Assume an onboard device and WOL capable by default. */
11236 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
| TG3_FLAG_WOL_CAP
;
11238 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
11239 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
11240 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11241 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11243 val
= tr32(VCPU_CFGSHDW
);
11244 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
11245 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11246 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
11247 (val
& VCPU_CFGSHDW_WOL_MAGPKT
))
11248 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11252 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
11253 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
11254 u32 nic_cfg
, led_cfg
;
11255 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
11256 int eeprom_phy_serdes
= 0;
11258 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
11259 tp
->nic_sram_data_cfg
= nic_cfg
;
11261 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
11262 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
11263 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
) &&
11264 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
) &&
11265 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5703
) &&
11266 (ver
> 0) && (ver
< 0x100))
11267 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
11269 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
)
11270 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
11272 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
11273 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
11274 eeprom_phy_serdes
= 1;
11276 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
11277 if (nic_phy_id
!= 0) {
11278 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
11279 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
11281 eeprom_phy_id
= (id1
>> 16) << 10;
11282 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
11283 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
11287 tp
->phy_id
= eeprom_phy_id
;
11288 if (eeprom_phy_serdes
) {
11289 if (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)
11290 tp
->tg3_flags2
|= TG3_FLG2_MII_SERDES
;
11292 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11295 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11296 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
11297 SHASTA_EXT_LED_MODE_MASK
);
11299 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
11303 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
11304 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11307 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
11308 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11311 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
11312 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
11314 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11315 * read on some older 5700/5701 bootcode.
11317 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11319 GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
11321 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11325 case SHASTA_EXT_LED_SHARED
:
11326 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
11327 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
&&
11328 tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A1
)
11329 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11330 LED_CTRL_MODE_PHY_2
);
11333 case SHASTA_EXT_LED_MAC
:
11334 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
11337 case SHASTA_EXT_LED_COMBO
:
11338 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
11339 if (tp
->pci_chip_rev_id
!= CHIPREV_ID_5750_A0
)
11340 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
11341 LED_CTRL_MODE_PHY_2
);
11346 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
11347 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) &&
11348 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
11349 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
11351 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5784_AX
)
11352 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
11354 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
11355 tp
->tg3_flags
|= TG3_FLAG_EEPROM_WRITE_PROT
;
11356 if ((tp
->pdev
->subsystem_vendor
==
11357 PCI_VENDOR_ID_ARIMA
) &&
11358 (tp
->pdev
->subsystem_device
== 0x205a ||
11359 tp
->pdev
->subsystem_device
== 0x2063))
11360 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11362 tp
->tg3_flags
&= ~TG3_FLAG_EEPROM_WRITE_PROT
;
11363 tp
->tg3_flags2
|= TG3_FLG2_IS_NIC
;
11366 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
11367 tp
->tg3_flags
|= TG3_FLAG_ENABLE_ASF
;
11368 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
)
11369 tp
->tg3_flags2
|= TG3_FLG2_ASF_NEW_HANDSHAKE
;
11372 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
11373 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
11374 tp
->tg3_flags3
|= TG3_FLG3_ENABLE_APE
;
11376 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
&&
11377 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
11378 tp
->tg3_flags
&= ~TG3_FLAG_WOL_CAP
;
11380 if ((tp
->tg3_flags
& TG3_FLAG_WOL_CAP
) &&
11381 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
))
11382 tp
->tg3_flags
|= TG3_FLAG_WOL_ENABLE
;
11384 if (cfg2
& (1 << 17))
11385 tp
->tg3_flags2
|= TG3_FLG2_CAPACITIVE_COUPLING
;
11387 /* serdes signal pre-emphasis in register 0x590 set by */
11388 /* bootcode if bit 18 is set */
11389 if (cfg2
& (1 << 18))
11390 tp
->tg3_flags2
|= TG3_FLG2_SERDES_PREEMPHASIS
;
11392 if (((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
11393 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
)) &&
11394 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
11395 tp
->tg3_flags3
|= TG3_FLG3_PHY_ENABLE_APD
;
11397 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
11400 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
11401 if (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
)
11402 tp
->tg3_flags
|= TG3_FLAG_ASPM_WORKAROUND
;
11405 if (cfg4
& NIC_SRAM_RGMII_STD_IBND_DISABLE
)
11406 tp
->tg3_flags3
|= TG3_FLG3_RGMII_STD_IBND_DISABLE
;
11407 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
11408 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_RX_EN
;
11409 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
11410 tp
->tg3_flags3
|= TG3_FLG3_RGMII_EXT_IBND_TX_EN
;
11413 device_init_wakeup(&tp
->pdev
->dev
, tp
->tg3_flags
& TG3_FLAG_WOL_CAP
);
11414 device_set_wakeup_enable(&tp
->pdev
->dev
,
11415 tp
->tg3_flags
& TG3_FLAG_WOL_ENABLE
);
11418 static int __devinit
tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
11423 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
11424 tw32(OTP_CTRL
, cmd
);
11426 /* Wait for up to 1 ms for command to execute. */
11427 for (i
= 0; i
< 100; i
++) {
11428 val
= tr32(OTP_STATUS
);
11429 if (val
& OTP_STATUS_CMD_DONE
)
11434 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
11437 /* Read the gphy configuration from the OTP region of the chip. The gphy
11438 * configuration is a 32-bit value that straddles the alignment boundary.
11439 * We do two 32-bit reads and then shift and merge the results.
11441 static u32 __devinit
tg3_read_otp_phycfg(struct tg3
*tp
)
11443 u32 bhalf_otp
, thalf_otp
;
11445 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
11447 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
11450 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
11452 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11455 thalf_otp
= tr32(OTP_READ_DATA
);
11457 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
11459 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
11462 bhalf_otp
= tr32(OTP_READ_DATA
);
11464 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
11467 static int __devinit
tg3_phy_probe(struct tg3
*tp
)
11469 u32 hw_phy_id_1
, hw_phy_id_2
;
11470 u32 hw_phy_id
, hw_phy_id_masked
;
11473 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
)
11474 return tg3_phy_init(tp
);
11476 /* Reading the PHY ID register can conflict with ASF
11477 * firmware access to the PHY hardware.
11480 if ((tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11481 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)) {
11482 hw_phy_id
= hw_phy_id_masked
= PHY_ID_INVALID
;
11484 /* Now read the physical PHY_ID from the chip and verify
11485 * that it is sane. If it doesn't look good, we fall back
11486 * to either the hard-coded table based PHY_ID and failing
11487 * that the value found in the eeprom area.
11489 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
11490 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
11492 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
11493 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
11494 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
11496 hw_phy_id_masked
= hw_phy_id
& PHY_ID_MASK
;
11499 if (!err
&& KNOWN_PHY_ID(hw_phy_id_masked
)) {
11500 tp
->phy_id
= hw_phy_id
;
11501 if (hw_phy_id_masked
== PHY_ID_BCM8002
)
11502 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11504 tp
->tg3_flags2
&= ~TG3_FLG2_PHY_SERDES
;
11506 if (tp
->phy_id
!= PHY_ID_INVALID
) {
11507 /* Do nothing, phy ID already set up in
11508 * tg3_get_eeprom_hw_cfg().
11511 struct subsys_tbl_ent
*p
;
11513 /* No eeprom signature? Try the hardcoded
11514 * subsys device table.
11516 p
= lookup_by_subsys(tp
);
11520 tp
->phy_id
= p
->phy_id
;
11522 tp
->phy_id
== PHY_ID_BCM8002
)
11523 tp
->tg3_flags2
|= TG3_FLG2_PHY_SERDES
;
11527 if (!(tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) &&
11528 !(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) &&
11529 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)) {
11530 u32 bmsr
, adv_reg
, tg3_ctrl
, mask
;
11532 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
11533 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
11534 (bmsr
& BMSR_LSTATUS
))
11535 goto skip_phy_reset
;
11537 err
= tg3_phy_reset(tp
);
11541 adv_reg
= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
11542 ADVERTISE_100HALF
| ADVERTISE_100FULL
|
11543 ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
);
11545 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)) {
11546 tg3_ctrl
= (MII_TG3_CTRL_ADV_1000_HALF
|
11547 MII_TG3_CTRL_ADV_1000_FULL
);
11548 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
11549 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
)
11550 tg3_ctrl
|= (MII_TG3_CTRL_AS_MASTER
|
11551 MII_TG3_CTRL_ENABLE_AS_MASTER
);
11554 mask
= (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
11555 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
11556 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
);
11557 if (!tg3_copper_is_advertising_all(tp
, mask
)) {
11558 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11560 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11561 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11563 tg3_writephy(tp
, MII_BMCR
,
11564 BMCR_ANENABLE
| BMCR_ANRESTART
);
11566 tg3_phy_set_wirespeed(tp
);
11568 tg3_writephy(tp
, MII_ADVERTISE
, adv_reg
);
11569 if (!(tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
))
11570 tg3_writephy(tp
, MII_TG3_CTRL
, tg3_ctrl
);
11574 if ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
) {
11575 err
= tg3_init_5401phy_dsp(tp
);
11580 if (!err
&& ((tp
->phy_id
& PHY_ID_MASK
) == PHY_ID_BCM5401
)) {
11581 err
= tg3_init_5401phy_dsp(tp
);
11584 if (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
)
11585 tp
->link_config
.advertising
=
11586 (ADVERTISED_1000baseT_Half
|
11587 ADVERTISED_1000baseT_Full
|
11588 ADVERTISED_Autoneg
|
11590 if (tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
)
11591 tp
->link_config
.advertising
&=
11592 ~(ADVERTISED_1000baseT_Half
|
11593 ADVERTISED_1000baseT_Full
);
11598 static void __devinit
tg3_read_partno(struct tg3
*tp
)
11600 unsigned char vpd_data
[256]; /* in little-endian format */
11604 if ((tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) ||
11605 tg3_nvram_read(tp
, 0x0, &magic
))
11606 goto out_not_found
;
11608 if (magic
== TG3_EEPROM_MAGIC
) {
11609 for (i
= 0; i
< 256; i
+= 4) {
11612 /* The data is in little-endian format in NVRAM.
11613 * Use the big-endian read routines to preserve
11614 * the byte order as it exists in NVRAM.
11616 if (tg3_nvram_read_be32(tp
, 0x100 + i
, &tmp
))
11617 goto out_not_found
;
11619 memcpy(&vpd_data
[i
], &tmp
, sizeof(tmp
));
11624 vpd_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_VPD
);
11625 for (i
= 0; i
< 256; i
+= 4) {
11630 pci_write_config_word(tp
->pdev
, vpd_cap
+ PCI_VPD_ADDR
,
11632 while (j
++ < 100) {
11633 pci_read_config_word(tp
->pdev
, vpd_cap
+
11634 PCI_VPD_ADDR
, &tmp16
);
11635 if (tmp16
& 0x8000)
11639 if (!(tmp16
& 0x8000))
11640 goto out_not_found
;
11642 pci_read_config_dword(tp
->pdev
, vpd_cap
+ PCI_VPD_DATA
,
11644 v
= cpu_to_le32(tmp
);
11645 memcpy(&vpd_data
[i
], &v
, sizeof(v
));
11649 /* Now parse and find the part number. */
11650 for (i
= 0; i
< 254; ) {
11651 unsigned char val
= vpd_data
[i
];
11652 unsigned int block_end
;
11654 if (val
== 0x82 || val
== 0x91) {
11657 (vpd_data
[i
+ 2] << 8)));
11662 goto out_not_found
;
11664 block_end
= (i
+ 3 +
11666 (vpd_data
[i
+ 2] << 8)));
11669 if (block_end
> 256)
11670 goto out_not_found
;
11672 while (i
< (block_end
- 2)) {
11673 if (vpd_data
[i
+ 0] == 'P' &&
11674 vpd_data
[i
+ 1] == 'N') {
11675 int partno_len
= vpd_data
[i
+ 2];
11678 if (partno_len
> 24 || (partno_len
+ i
) > 256)
11679 goto out_not_found
;
11681 memcpy(tp
->board_part_number
,
11682 &vpd_data
[i
], partno_len
);
11687 i
+= 3 + vpd_data
[i
+ 2];
11690 /* Part number not found. */
11691 goto out_not_found
;
11695 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
11696 strcpy(tp
->board_part_number
, "BCM95906");
11697 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11698 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
11699 strcpy(tp
->board_part_number
, "BCM57780");
11700 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11701 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
11702 strcpy(tp
->board_part_number
, "BCM57760");
11703 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11704 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
11705 strcpy(tp
->board_part_number
, "BCM57790");
11706 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
&&
11707 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
11708 strcpy(tp
->board_part_number
, "BCM57788");
11710 strcpy(tp
->board_part_number
, "none");
11713 static int __devinit
tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
11717 if (tg3_nvram_read(tp
, offset
, &val
) ||
11718 (val
& 0xfc000000) != 0x0c000000 ||
11719 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
11726 static void __devinit
tg3_read_bc_ver(struct tg3
*tp
)
11728 u32 val
, offset
, start
, ver_offset
;
11730 bool newver
= false;
11732 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
11733 tg3_nvram_read(tp
, 0x4, &start
))
11736 offset
= tg3_nvram_logical_addr(tp
, offset
);
11738 if (tg3_nvram_read(tp
, offset
, &val
))
11741 if ((val
& 0xfc000000) == 0x0c000000) {
11742 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
11750 if (tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
11753 offset
= offset
+ ver_offset
- start
;
11754 for (i
= 0; i
< 16; i
+= 4) {
11756 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
11759 memcpy(tp
->fw_ver
+ i
, &v
, sizeof(v
));
11764 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
11767 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
11768 TG3_NVM_BCVER_MAJSFT
;
11769 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
11770 snprintf(&tp
->fw_ver
[0], 32, "v%d.%02d", major
, minor
);
11774 static void __devinit
tg3_read_hwsb_ver(struct tg3
*tp
)
11776 u32 val
, major
, minor
;
11778 /* Use native endian representation */
11779 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
11782 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
11783 TG3_NVM_HWSB_CFG1_MAJSFT
;
11784 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
11785 TG3_NVM_HWSB_CFG1_MINSFT
;
11787 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
11790 static void __devinit
tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
11792 u32 offset
, major
, minor
, build
;
11794 tp
->fw_ver
[0] = 's';
11795 tp
->fw_ver
[1] = 'b';
11796 tp
->fw_ver
[2] = '\0';
11798 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
11801 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
11802 case TG3_EEPROM_SB_REVISION_0
:
11803 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
11805 case TG3_EEPROM_SB_REVISION_2
:
11806 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
11808 case TG3_EEPROM_SB_REVISION_3
:
11809 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
11815 if (tg3_nvram_read(tp
, offset
, &val
))
11818 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
11819 TG3_EEPROM_SB_EDH_BLD_SHFT
;
11820 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
11821 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
11822 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
11824 if (minor
> 99 || build
> 26)
11827 snprintf(&tp
->fw_ver
[2], 30, " v%d.%02d", major
, minor
);
11830 tp
->fw_ver
[8] = 'a' + build
- 1;
11831 tp
->fw_ver
[9] = '\0';
11835 static void __devinit
tg3_read_mgmtfw_ver(struct tg3
*tp
)
11837 u32 val
, offset
, start
;
11840 for (offset
= TG3_NVM_DIR_START
;
11841 offset
< TG3_NVM_DIR_END
;
11842 offset
+= TG3_NVM_DIRENT_SIZE
) {
11843 if (tg3_nvram_read(tp
, offset
, &val
))
11846 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
11850 if (offset
== TG3_NVM_DIR_END
)
11853 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
))
11854 start
= 0x08000000;
11855 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
11858 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
11859 !tg3_fw_img_is_valid(tp
, offset
) ||
11860 tg3_nvram_read(tp
, offset
+ 8, &val
))
11863 offset
+= val
- start
;
11865 vlen
= strlen(tp
->fw_ver
);
11867 tp
->fw_ver
[vlen
++] = ',';
11868 tp
->fw_ver
[vlen
++] = ' ';
11870 for (i
= 0; i
< 4; i
++) {
11872 if (tg3_nvram_read_be32(tp
, offset
, &v
))
11875 offset
+= sizeof(v
);
11877 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
11878 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
11882 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
11887 static void __devinit
tg3_read_dash_ver(struct tg3
*tp
)
11892 if (!(tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) ||
11893 !(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
))
11896 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
11897 if (apedata
!= APE_SEG_SIG_MAGIC
)
11900 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
11901 if (!(apedata
& APE_FW_STATUS_READY
))
11904 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
11906 vlen
= strlen(tp
->fw_ver
);
11908 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " DASH v%d.%d.%d.%d",
11909 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
11910 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
11911 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
11912 (apedata
& APE_FW_VERSION_BLDMSK
));
11915 static void __devinit
tg3_read_fw_ver(struct tg3
*tp
)
11919 if (tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) {
11920 tp
->fw_ver
[0] = 's';
11921 tp
->fw_ver
[1] = 'b';
11922 tp
->fw_ver
[2] = '\0';
11927 if (tg3_nvram_read(tp
, 0, &val
))
11930 if (val
== TG3_EEPROM_MAGIC
)
11931 tg3_read_bc_ver(tp
);
11932 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
11933 tg3_read_sb_ver(tp
, val
);
11934 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
11935 tg3_read_hwsb_ver(tp
);
11939 if (!(tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) ||
11940 (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
))
11943 tg3_read_mgmtfw_ver(tp
);
11945 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
11948 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*);
11950 static int __devinit
tg3_get_invariants(struct tg3
*tp
)
11952 static struct pci_device_id write_reorder_chipsets
[] = {
11953 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11954 PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
11955 { PCI_DEVICE(PCI_VENDOR_ID_AMD
,
11956 PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
11957 { PCI_DEVICE(PCI_VENDOR_ID_VIA
,
11958 PCI_DEVICE_ID_VIA_8385_0
) },
11962 u32 pci_state_reg
, grc_misc_cfg
;
11967 /* Force memory write invalidate off. If we leave it on,
11968 * then on 5700_BX chips we have to enable a workaround.
11969 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11970 * to match the cacheline size. The Broadcom driver have this
11971 * workaround but turns MWI off all the times so never uses
11972 * it. This seems to suggest that the workaround is insufficient.
11974 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
11975 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
11976 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
11978 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11979 * has the register indirect write enable bit set before
11980 * we try to access any of the MMIO registers. It is also
11981 * critical that the PCI-X hw workaround situation is decided
11982 * before that as well.
11984 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
11987 tp
->pci_chip_rev_id
= (misc_ctrl_reg
>>
11988 MISC_HOST_CTRL_CHIPREV_SHIFT
);
11989 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_USE_PROD_ID_REG
) {
11990 u32 prod_id_asic_rev
;
11992 pci_read_config_dword(tp
->pdev
, TG3PCI_PRODID_ASICREV
,
11993 &prod_id_asic_rev
);
11994 tp
->pci_chip_rev_id
= prod_id_asic_rev
;
11997 /* Wrong chip ID in 5752 A0. This code can be removed later
11998 * as A0 is not in production.
12000 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5752_A0_HW
)
12001 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
12003 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12004 * we need to disable memory and use config. cycles
12005 * only to access all registers. The 5702/03 chips
12006 * can mistakenly decode the special cycles from the
12007 * ICH chipsets as memory write cycles, causing corruption
12008 * of register and memory space. Only certain ICH bridges
12009 * will drive special cycles with non-zero data during the
12010 * address phase which can fall within the 5703's address
12011 * range. This is not an ICH bug as the PCI spec allows
12012 * non-zero address during special cycles. However, only
12013 * these ICH bridges are known to drive non-zero addresses
12014 * during special cycles.
12016 * Since special cycles do not cross PCI bridges, we only
12017 * enable this workaround if the 5703 is on the secondary
12018 * bus of these ICH bridges.
12020 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A1
) ||
12021 (tp
->pci_chip_rev_id
== CHIPREV_ID_5703_A2
)) {
12022 static struct tg3_dev_id
{
12026 } ich_chipsets
[] = {
12027 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
12029 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
12031 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
12033 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
12037 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
12038 struct pci_dev
*bridge
= NULL
;
12040 while (pci_id
->vendor
!= 0) {
12041 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
12047 if (pci_id
->rev
!= PCI_ANY_ID
) {
12048 if (bridge
->revision
> pci_id
->rev
)
12051 if (bridge
->subordinate
&&
12052 (bridge
->subordinate
->number
==
12053 tp
->pdev
->bus
->number
)) {
12055 tp
->tg3_flags2
|= TG3_FLG2_ICH_WORKAROUND
;
12056 pci_dev_put(bridge
);
12062 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)) {
12063 static struct tg3_dev_id
{
12066 } bridge_chipsets
[] = {
12067 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
12068 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
12071 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
12072 struct pci_dev
*bridge
= NULL
;
12074 while (pci_id
->vendor
!= 0) {
12075 bridge
= pci_get_device(pci_id
->vendor
,
12082 if (bridge
->subordinate
&&
12083 (bridge
->subordinate
->number
<=
12084 tp
->pdev
->bus
->number
) &&
12085 (bridge
->subordinate
->subordinate
>=
12086 tp
->pdev
->bus
->number
)) {
12087 tp
->tg3_flags3
|= TG3_FLG3_5701_DMA_BUG
;
12088 pci_dev_put(bridge
);
12094 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12095 * DMA addresses > 40-bit. This bridge may have other additional
12096 * 57xx devices behind it in some 4-port NIC designs for example.
12097 * Any tg3 device found behind the bridge will also need the 40-bit
12100 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
||
12101 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
12102 tp
->tg3_flags2
|= TG3_FLG2_5780_CLASS
;
12103 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12104 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
12107 struct pci_dev
*bridge
= NULL
;
12110 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
12111 PCI_DEVICE_ID_SERVERWORKS_EPB
,
12113 if (bridge
&& bridge
->subordinate
&&
12114 (bridge
->subordinate
->number
<=
12115 tp
->pdev
->bus
->number
) &&
12116 (bridge
->subordinate
->subordinate
>=
12117 tp
->pdev
->bus
->number
)) {
12118 tp
->tg3_flags
|= TG3_FLAG_40BIT_DMA_BUG
;
12119 pci_dev_put(bridge
);
12125 /* Initialize misc host control in PCI block. */
12126 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
12127 MISC_HOST_CTRL_CHIPREV
);
12128 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12129 tp
->misc_host_ctrl
);
12131 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12132 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
))
12133 tp
->pdev_peer
= tg3_find_peer(tp
);
12135 /* Intentionally exclude ASIC_REV_5906 */
12136 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12137 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12138 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12139 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12140 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12141 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12142 tp
->tg3_flags3
|= TG3_FLG3_5755_PLUS
;
12144 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12145 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12146 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
12147 (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12148 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12149 tp
->tg3_flags2
|= TG3_FLG2_5750_PLUS
;
12151 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) ||
12152 (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
))
12153 tp
->tg3_flags2
|= TG3_FLG2_5705_PLUS
;
12155 /* 5700 B0 chips do not support checksumming correctly due
12156 * to hardware bugs.
12158 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5700_B0
)
12159 tp
->tg3_flags
|= TG3_FLAG_BROKEN_CHECKSUMS
;
12161 tp
->tg3_flags
|= TG3_FLAG_RX_CHECKSUMS
;
12162 tp
->dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
12163 if (tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
)
12164 tp
->dev
->features
|= NETIF_F_IPV6_CSUM
;
12167 if (tp
->tg3_flags2
& TG3_FLG2_5750_PLUS
) {
12168 tp
->tg3_flags
|= TG3_FLAG_SUPPORT_MSI
;
12169 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_AX
||
12170 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5750_BX
||
12171 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
&&
12172 tp
->pci_chip_rev_id
<= CHIPREV_ID_5714_A2
&&
12173 tp
->pdev_peer
== tp
->pdev
))
12174 tp
->tg3_flags
&= ~TG3_FLAG_SUPPORT_MSI
;
12176 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
12177 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12178 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_2
;
12179 tp
->tg3_flags2
|= TG3_FLG2_1SHOT_MSI
;
12181 tp
->tg3_flags2
|= TG3_FLG2_HW_TSO_1
| TG3_FLG2_TSO_BUG
;
12182 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) ==
12184 tp
->pci_chip_rev_id
>= CHIPREV_ID_5750_C2
)
12185 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_BUG
;
12191 if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12192 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12193 tp
->tg3_flags
|= TG3_FLAG_JUMBO_CAPABLE
;
12195 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12198 tp
->pcie_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_EXP
);
12199 if (tp
->pcie_cap
!= 0) {
12202 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12204 pcie_set_readrq(tp
->pdev
, 4096);
12206 pci_read_config_word(tp
->pdev
,
12207 tp
->pcie_cap
+ PCI_EXP_LNKCTL
,
12209 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
12210 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12211 tp
->tg3_flags2
&= ~TG3_FLG2_HW_TSO_2
;
12212 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12213 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12214 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
||
12215 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
)
12216 tp
->tg3_flags3
|= TG3_FLG3_CLKREQ_BUG
;
12218 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
) {
12219 tp
->tg3_flags2
|= TG3_FLG2_PCI_EXPRESS
;
12220 } else if (!(tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) ||
12221 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12222 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
12223 if (!tp
->pcix_cap
) {
12224 printk(KERN_ERR PFX
"Cannot find PCI-X "
12225 "capability, aborting.\n");
12229 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
12230 tp
->tg3_flags
|= TG3_FLAG_PCIX_MODE
;
12233 /* If we have an AMD 762 or VIA K8T800 chipset, write
12234 * reordering to the mailbox registers done by the host
12235 * controller can cause major troubles. We read back from
12236 * every mailbox register write to force the writes to be
12237 * posted to the chip in order.
12239 if (pci_dev_present(write_reorder_chipsets
) &&
12240 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12241 tp
->tg3_flags
|= TG3_FLAG_MBOX_WRITE_REORDER
;
12243 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
12244 &tp
->pci_cacheline_sz
);
12245 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12246 &tp
->pci_lat_timer
);
12247 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12248 tp
->pci_lat_timer
< 64) {
12249 tp
->pci_lat_timer
= 64;
12250 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
12251 tp
->pci_lat_timer
);
12254 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5700_BX
) {
12255 /* 5700 BX chips need to have their TX producer index
12256 * mailboxes written twice to workaround a bug.
12258 tp
->tg3_flags
|= TG3_FLAG_TXD_MBOX_HWBUG
;
12260 /* If we are in PCI-X mode, enable register write workaround.
12262 * The workaround is to use indirect register accesses
12263 * for all chip writes not to mailbox registers.
12265 if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
12268 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12270 /* The chip can have it's power management PCI config
12271 * space registers clobbered due to this bug.
12272 * So explicitly force the chip into D0 here.
12274 pci_read_config_dword(tp
->pdev
,
12275 tp
->pm_cap
+ PCI_PM_CTRL
,
12277 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
12278 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
12279 pci_write_config_dword(tp
->pdev
,
12280 tp
->pm_cap
+ PCI_PM_CTRL
,
12283 /* Also, force SERR#/PERR# in PCI command. */
12284 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12285 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
12286 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12290 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
12291 tp
->tg3_flags
|= TG3_FLAG_PCI_HIGH_SPEED
;
12292 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
12293 tp
->tg3_flags
|= TG3_FLAG_PCI_32BIT
;
12295 /* Chip-specific fixup from Broadcom driver */
12296 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
) &&
12297 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
12298 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
12299 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
12302 /* Default fast path register access methods */
12303 tp
->read32
= tg3_read32
;
12304 tp
->write32
= tg3_write32
;
12305 tp
->read32_mbox
= tg3_read32
;
12306 tp
->write32_mbox
= tg3_write32
;
12307 tp
->write32_tx_mbox
= tg3_write32
;
12308 tp
->write32_rx_mbox
= tg3_write32
;
12310 /* Various workaround register access methods */
12311 if (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
)
12312 tp
->write32
= tg3_write_indirect_reg32
;
12313 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
12314 ((tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) &&
12315 tp
->pci_chip_rev_id
== CHIPREV_ID_5750_A0
)) {
12317 * Back to back register writes can cause problems on these
12318 * chips, the workaround is to read back all reg writes
12319 * except those to mailbox regs.
12321 * See tg3_write_indirect_reg32().
12323 tp
->write32
= tg3_write_flush_reg32
;
12327 if ((tp
->tg3_flags
& TG3_FLAG_TXD_MBOX_HWBUG
) ||
12328 (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)) {
12329 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
12330 if (tp
->tg3_flags
& TG3_FLAG_MBOX_WRITE_REORDER
)
12331 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
12334 if (tp
->tg3_flags2
& TG3_FLG2_ICH_WORKAROUND
) {
12335 tp
->read32
= tg3_read_indirect_reg32
;
12336 tp
->write32
= tg3_write_indirect_reg32
;
12337 tp
->read32_mbox
= tg3_read_indirect_mbox
;
12338 tp
->write32_mbox
= tg3_write_indirect_mbox
;
12339 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
12340 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
12345 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
12346 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
12347 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
12349 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
12350 tp
->read32_mbox
= tg3_read32_mbox_5906
;
12351 tp
->write32_mbox
= tg3_write32_mbox_5906
;
12352 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
12353 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
12356 if (tp
->write32
== tg3_write_indirect_reg32
||
12357 ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12358 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12359 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
)))
12360 tp
->tg3_flags
|= TG3_FLAG_SRAM_USE_CONFIG
;
12362 /* Get eeprom hw config before calling tg3_set_power_state().
12363 * In particular, the TG3_FLG2_IS_NIC flag must be
12364 * determined before calling tg3_set_power_state() so that
12365 * we know whether or not to switch out of Vaux power.
12366 * When the flag is set, it means that GPIO1 is used for eeprom
12367 * write protect and also implies that it is a LOM where GPIOs
12368 * are not used to switch power.
12370 tg3_get_eeprom_hw_cfg(tp
);
12372 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
12373 /* Allow reads and writes to the
12374 * APE register and memory space.
12376 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
12377 PCISTATE_ALLOW_APE_SHMEM_WR
;
12378 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12382 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12383 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
12384 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12385 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12386 tp
->tg3_flags
|= TG3_FLAG_CPMU_PRESENT
;
12388 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12389 * GPIO1 driven high will bring 5700's external PHY out of reset.
12390 * It is also used as eeprom write protect on LOMs.
12392 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
12393 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12394 (tp
->tg3_flags
& TG3_FLAG_EEPROM_WRITE_PROT
))
12395 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
12396 GRC_LCLCTRL_GPIO_OUTPUT1
);
12397 /* Unused GPIO3 must be driven as output on 5752 because there
12398 * are no pull-up resistors on unused GPIO pins.
12400 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
)
12401 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
12403 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12404 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12405 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12407 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
12408 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
12409 /* Turn off the debug UART. */
12410 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
12411 if (tp
->tg3_flags2
& TG3_FLG2_IS_NIC
)
12412 /* Keep VMain power. */
12413 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
12414 GRC_LCLCTRL_GPIO_OUTPUT0
;
12417 /* Force the chip into D0. */
12418 err
= tg3_set_power_state(tp
, PCI_D0
);
12420 printk(KERN_ERR PFX
"(%s) transition to D0 failed\n",
12421 pci_name(tp
->pdev
));
12425 /* Derive initial jumbo mode from MTU assigned in
12426 * ether_setup() via the alloc_etherdev() call
12428 if (tp
->dev
->mtu
> ETH_DATA_LEN
&&
12429 !(tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
))
12430 tp
->tg3_flags
|= TG3_FLAG_JUMBO_RING_ENABLE
;
12432 /* Determine WakeOnLan speed to use. */
12433 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
12434 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
||
12435 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B0
||
12436 tp
->pci_chip_rev_id
== CHIPREV_ID_5701_B2
) {
12437 tp
->tg3_flags
&= ~(TG3_FLAG_WOL_SPEED_100MB
);
12439 tp
->tg3_flags
|= TG3_FLAG_WOL_SPEED_100MB
;
12442 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12443 tp
->tg3_flags3
|= TG3_FLG3_PHY_IS_FET
;
12445 /* A few boards don't want Ethernet@WireSpeed phy feature */
12446 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
) ||
12447 ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
) &&
12448 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A0
) &&
12449 (tp
->pci_chip_rev_id
!= CHIPREV_ID_5705_A1
)) ||
12450 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) ||
12451 (tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
))
12452 tp
->tg3_flags2
|= TG3_FLG2_NO_ETH_WIRE_SPEED
;
12454 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5703_AX
||
12455 GET_CHIP_REV(tp
->pci_chip_rev_id
) == CHIPREV_5704_AX
)
12456 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADC_BUG
;
12457 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5704_A0
)
12458 tp
->tg3_flags2
|= TG3_FLG2_PHY_5704_A0_BUG
;
12460 if ((tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) &&
12461 !(tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
) &&
12462 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5785
&&
12463 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_57780
) {
12464 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
||
12465 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5787
||
12466 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
||
12467 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
) {
12468 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
12469 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
12470 tp
->tg3_flags2
|= TG3_FLG2_PHY_JITTER_BUG
;
12471 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
12472 tp
->tg3_flags2
|= TG3_FLG2_PHY_ADJUST_TRIM
;
12474 tp
->tg3_flags2
|= TG3_FLG2_PHY_BER_BUG
;
12477 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
12478 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) {
12479 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
12480 if (tp
->phy_otp
== 0)
12481 tp
->phy_otp
= TG3_OTP_DEFAULT
;
12484 if (tp
->tg3_flags
& TG3_FLAG_CPMU_PRESENT
)
12485 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
12487 tp
->mi_mode
= MAC_MI_MODE_BASE
;
12489 tp
->coalesce_mode
= 0;
12490 if (GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_AX
&&
12491 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5700_BX
)
12492 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
12494 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
12495 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
12496 tp
->tg3_flags3
|= TG3_FLG3_USE_PHYLIB
;
12498 if ((tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A1
&&
12499 tr32(RCVLPC_STATS_ENABLE
) & RCVLPC_STATSENAB_ASF_FIX
) ||
12500 tp
->pci_chip_rev_id
== CHIPREV_ID_57780_A0
)
12501 tp
->tg3_flags3
|= TG3_FLG3_TOGGLE_10_100_L1PLLPD
;
12503 err
= tg3_mdio_init(tp
);
12507 /* Initialize data/descriptor byte/word swapping. */
12508 val
= tr32(GRC_MODE
);
12509 val
&= GRC_MODE_HOST_STACKUP
;
12510 tw32(GRC_MODE
, val
| tp
->grc_mode
);
12512 tg3_switch_clocks(tp
);
12514 /* Clear this out for sanity. */
12515 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12517 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
12519 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
12520 (tp
->tg3_flags
& TG3_FLAG_PCIX_TARGET_HWBUG
) == 0) {
12521 u32 chiprevid
= GET_CHIP_REV_ID(tp
->misc_host_ctrl
);
12523 if (chiprevid
== CHIPREV_ID_5701_A0
||
12524 chiprevid
== CHIPREV_ID_5701_B0
||
12525 chiprevid
== CHIPREV_ID_5701_B2
||
12526 chiprevid
== CHIPREV_ID_5701_B5
) {
12527 void __iomem
*sram_base
;
12529 /* Write some dummy words into the SRAM status block
12530 * area, see if it reads back correctly. If the return
12531 * value is bad, force enable the PCIX workaround.
12533 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
12535 writel(0x00000000, sram_base
);
12536 writel(0x00000000, sram_base
+ 4);
12537 writel(0xffffffff, sram_base
+ 4);
12538 if (readl(sram_base
) != 0x00000000)
12539 tp
->tg3_flags
|= TG3_FLAG_PCIX_TARGET_HWBUG
;
12544 tg3_nvram_init(tp
);
12546 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
12547 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
12549 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12550 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
12551 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
12552 tp
->tg3_flags2
|= TG3_FLG2_IS_5788
;
12554 if (!(tp
->tg3_flags2
& TG3_FLG2_IS_5788
) &&
12555 (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
))
12556 tp
->tg3_flags
|= TG3_FLAG_TAGGED_STATUS
;
12557 if (tp
->tg3_flags
& TG3_FLAG_TAGGED_STATUS
) {
12558 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
12559 HOSTCC_MODE_CLRTICK_TXBD
);
12561 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
12562 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
12563 tp
->misc_host_ctrl
);
12566 /* Preserve the APE MAC_MODE bits */
12567 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
)
12568 tp
->mac_mode
= tr32(MAC_MODE
) |
12569 MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
12571 tp
->mac_mode
= TG3_DEF_MAC_MODE
;
12573 /* these are limited to 10/100 only */
12574 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
&&
12575 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
12576 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
&&
12577 tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12578 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901
||
12579 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5901_2
||
12580 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5705F
)) ||
12581 (tp
->pdev
->vendor
== PCI_VENDOR_ID_BROADCOM
&&
12582 (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5751F
||
12583 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5753F
||
12584 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5787F
)) ||
12585 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
||
12586 (tp
->tg3_flags3
& TG3_FLG3_PHY_IS_FET
))
12587 tp
->tg3_flags
|= TG3_FLAG_10_100_ONLY
;
12589 err
= tg3_phy_probe(tp
);
12591 printk(KERN_ERR PFX
"(%s) phy probe failed, err %d\n",
12592 pci_name(tp
->pdev
), err
);
12593 /* ... but do not return immediately ... */
12597 tg3_read_partno(tp
);
12598 tg3_read_fw_ver(tp
);
12600 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
) {
12601 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12603 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12604 tp
->tg3_flags
|= TG3_FLAG_USE_MI_INTERRUPT
;
12606 tp
->tg3_flags
&= ~TG3_FLAG_USE_MI_INTERRUPT
;
12609 /* 5700 {AX,BX} chips have a broken status block link
12610 * change bit implementation, so we must use the
12611 * status register in those cases.
12613 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
)
12614 tp
->tg3_flags
|= TG3_FLAG_USE_LINKCHG_REG
;
12616 tp
->tg3_flags
&= ~TG3_FLAG_USE_LINKCHG_REG
;
12618 /* The led_ctrl is set during tg3_phy_probe, here we might
12619 * have to force the link status polling mechanism based
12620 * upon subsystem IDs.
12622 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
12623 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12624 !(tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)) {
12625 tp
->tg3_flags
|= (TG3_FLAG_USE_MI_INTERRUPT
|
12626 TG3_FLAG_USE_LINKCHG_REG
);
12629 /* For all SERDES we poll the MAC status register. */
12630 if (tp
->tg3_flags2
& TG3_FLG2_PHY_SERDES
)
12631 tp
->tg3_flags
|= TG3_FLAG_POLL_SERDES
;
12633 tp
->tg3_flags
&= ~TG3_FLAG_POLL_SERDES
;
12635 tp
->rx_offset
= NET_IP_ALIGN
;
12636 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
&&
12637 (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) != 0)
12640 tp
->rx_std_max_post
= TG3_RX_RING_SIZE
;
12642 /* Increment the rx prod index on the rx std ring by at most
12643 * 8 for these chips to workaround hw errata.
12645 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
||
12646 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5752
||
12647 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5755
)
12648 tp
->rx_std_max_post
= 8;
12650 if (tp
->tg3_flags
& TG3_FLAG_ASPM_WORKAROUND
)
12651 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
12652 PCIE_PWR_MGMT_L1_THRESH_MSK
;
12657 #ifdef CONFIG_SPARC
12658 static int __devinit
tg3_get_macaddr_sparc(struct tg3
*tp
)
12660 struct net_device
*dev
= tp
->dev
;
12661 struct pci_dev
*pdev
= tp
->pdev
;
12662 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
12663 const unsigned char *addr
;
12666 addr
= of_get_property(dp
, "local-mac-address", &len
);
12667 if (addr
&& len
== 6) {
12668 memcpy(dev
->dev_addr
, addr
, 6);
12669 memcpy(dev
->perm_addr
, dev
->dev_addr
, 6);
12675 static int __devinit
tg3_get_default_macaddr_sparc(struct tg3
*tp
)
12677 struct net_device
*dev
= tp
->dev
;
12679 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
12680 memcpy(dev
->perm_addr
, idprom
->id_ethaddr
, 6);
12685 static int __devinit
tg3_get_device_address(struct tg3
*tp
)
12687 struct net_device
*dev
= tp
->dev
;
12688 u32 hi
, lo
, mac_offset
;
12691 #ifdef CONFIG_SPARC
12692 if (!tg3_get_macaddr_sparc(tp
))
12697 if ((GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) ||
12698 (tp
->tg3_flags2
& TG3_FLG2_5780_CLASS
)) {
12699 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
12701 if (tg3_nvram_lock(tp
))
12702 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
12704 tg3_nvram_unlock(tp
);
12706 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
12709 /* First try to get it from MAC address mailbox. */
12710 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
12711 if ((hi
>> 16) == 0x484b) {
12712 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12713 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
12715 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
12716 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12717 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12718 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12719 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
12721 /* Some old bootcode may report a 0 MAC address in SRAM */
12722 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
12725 /* Next, try NVRAM. */
12726 if (!(tp
->tg3_flags3
& TG3_FLG3_NO_NVRAM
) &&
12727 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
12728 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
12729 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
12730 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
12732 /* Finally just fetch it out of the MAC control regs. */
12734 hi
= tr32(MAC_ADDR_0_HIGH
);
12735 lo
= tr32(MAC_ADDR_0_LOW
);
12737 dev
->dev_addr
[5] = lo
& 0xff;
12738 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
12739 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
12740 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
12741 dev
->dev_addr
[1] = hi
& 0xff;
12742 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
12746 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
12747 #ifdef CONFIG_SPARC
12748 if (!tg3_get_default_macaddr_sparc(tp
))
12753 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
12757 #define BOUNDARY_SINGLE_CACHELINE 1
12758 #define BOUNDARY_MULTI_CACHELINE 2
12760 static u32 __devinit
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
12762 int cacheline_size
;
12766 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
12768 cacheline_size
= 1024;
12770 cacheline_size
= (int) byte
* 4;
12772 /* On 5703 and later chips, the boundary bits have no
12775 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
12776 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
&&
12777 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
))
12780 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12781 goal
= BOUNDARY_MULTI_CACHELINE
;
12783 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12784 goal
= BOUNDARY_SINGLE_CACHELINE
;
12793 /* PCI controllers on most RISC systems tend to disconnect
12794 * when a device tries to burst across a cache-line boundary.
12795 * Therefore, letting tg3 do so just wastes PCI bandwidth.
12797 * Unfortunately, for PCI-E there are only limited
12798 * write-side controls for this, and thus for reads
12799 * we will still get the disconnects. We'll also waste
12800 * these PCI cycles for both read and write for chips
12801 * other than 5700 and 5701 which do not implement the
12804 if ((tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) &&
12805 !(tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
)) {
12806 switch (cacheline_size
) {
12811 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12812 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
12813 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
12815 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12816 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12821 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
12822 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
12826 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
12827 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
12830 } else if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12831 switch (cacheline_size
) {
12835 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12836 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12837 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
12843 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
12844 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
12848 switch (cacheline_size
) {
12850 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12851 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
12852 DMA_RWCTRL_WRITE_BNDRY_16
);
12857 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12858 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
12859 DMA_RWCTRL_WRITE_BNDRY_32
);
12864 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12865 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
12866 DMA_RWCTRL_WRITE_BNDRY_64
);
12871 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
12872 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
12873 DMA_RWCTRL_WRITE_BNDRY_128
);
12878 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
12879 DMA_RWCTRL_WRITE_BNDRY_256
);
12882 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
12883 DMA_RWCTRL_WRITE_BNDRY_512
);
12887 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
12888 DMA_RWCTRL_WRITE_BNDRY_1024
);
12897 static int __devinit
tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
, int size
, int to_device
)
12899 struct tg3_internal_buffer_desc test_desc
;
12900 u32 sram_dma_descs
;
12903 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
12905 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
12906 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
12907 tw32(RDMAC_STATUS
, 0);
12908 tw32(WDMAC_STATUS
, 0);
12910 tw32(BUFMGR_MODE
, 0);
12911 tw32(FTQ_RESET
, 0);
12913 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
12914 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
12915 test_desc
.nic_mbuf
= 0x00002100;
12916 test_desc
.len
= size
;
12919 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12920 * the *second* time the tg3 driver was getting loaded after an
12923 * Broadcom tells me:
12924 * ...the DMA engine is connected to the GRC block and a DMA
12925 * reset may affect the GRC block in some unpredictable way...
12926 * The behavior of resets to individual blocks has not been tested.
12928 * Broadcom noted the GRC reset will also reset all sub-components.
12931 test_desc
.cqid_sqid
= (13 << 8) | 2;
12933 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
12936 test_desc
.cqid_sqid
= (16 << 8) | 7;
12938 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
12941 test_desc
.flags
= 0x00000005;
12943 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
12946 val
= *(((u32
*)&test_desc
) + i
);
12947 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
12948 sram_dma_descs
+ (i
* sizeof(u32
)));
12949 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
12951 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
12954 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
12956 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
12960 for (i
= 0; i
< 40; i
++) {
12964 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
12966 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
12967 if ((val
& 0xffff) == sram_dma_descs
) {
12978 #define TEST_BUFFER_SIZE 0x2000
12980 static int __devinit
tg3_test_dma(struct tg3
*tp
)
12982 dma_addr_t buf_dma
;
12983 u32
*buf
, saved_dma_rwctrl
;
12986 buf
= pci_alloc_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, &buf_dma
);
12992 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
12993 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
12995 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
12997 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
12998 /* DMA read watermark not used on PCIE */
12999 tp
->dma_rwctrl
|= 0x00180000;
13000 } else if (!(tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
)) {
13001 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
||
13002 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5750
)
13003 tp
->dma_rwctrl
|= 0x003f0000;
13005 tp
->dma_rwctrl
|= 0x003f000f;
13007 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13008 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
) {
13009 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
13010 u32 read_water
= 0x7;
13012 /* If the 5704 is behind the EPB bridge, we can
13013 * do the less restrictive ONE_DMA workaround for
13014 * better performance.
13016 if ((tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) &&
13017 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13018 tp
->dma_rwctrl
|= 0x8000;
13019 else if (ccval
== 0x6 || ccval
== 0x7)
13020 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
13022 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
)
13024 /* Set bit 23 to enable PCIX hw bug fix */
13026 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
13027 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
13029 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5780
) {
13030 /* 5780 always in PCIX mode */
13031 tp
->dma_rwctrl
|= 0x00144000;
13032 } else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5714
) {
13033 /* 5714 always in PCIX mode */
13034 tp
->dma_rwctrl
|= 0x00148000;
13036 tp
->dma_rwctrl
|= 0x001b000f;
13040 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5703
||
13041 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5704
)
13042 tp
->dma_rwctrl
&= 0xfffffff0;
13044 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13045 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
) {
13046 /* Remove this if it causes problems for some boards. */
13047 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
13049 /* On 5700/5701 chips, we need to set this bit.
13050 * Otherwise the chip will issue cacheline transactions
13051 * to streamable DMA memory with not all the byte
13052 * enables turned on. This is an error on several
13053 * RISC PCI controllers, in particular sparc64.
13055 * On 5703/5704 chips, this bit has been reassigned
13056 * a different meaning. In particular, it is used
13057 * on those chips to enable a PCI-X workaround.
13059 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
13062 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13065 /* Unneeded, already done by tg3_get_invariants. */
13066 tg3_switch_clocks(tp
);
13070 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5700
&&
13071 GET_ASIC_REV(tp
->pci_chip_rev_id
) != ASIC_REV_5701
)
13074 /* It is best to perform DMA test with maximum write burst size
13075 * to expose the 5700/5701 write DMA bug.
13077 saved_dma_rwctrl
= tp
->dma_rwctrl
;
13078 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13079 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13084 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
13087 /* Send the buffer to the chip. */
13088 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 1);
13090 printk(KERN_ERR
"tg3_test_dma() Write the buffer failed %d\n", ret
);
13095 /* validate data reached card RAM correctly. */
13096 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13098 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
13099 if (le32_to_cpu(val
) != p
[i
]) {
13100 printk(KERN_ERR
" tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val
, i
);
13101 /* ret = -ENODEV here? */
13106 /* Now read it back. */
13107 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, 0);
13109 printk(KERN_ERR
"tg3_test_dma() Read the buffer failed %d\n", ret
);
13115 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
13119 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13120 DMA_RWCTRL_WRITE_BNDRY_16
) {
13121 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13122 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13123 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13126 printk(KERN_ERR
"tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p
[i
], i
);
13132 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
13138 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
13139 DMA_RWCTRL_WRITE_BNDRY_16
) {
13140 static struct pci_device_id dma_wait_state_chipsets
[] = {
13141 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
,
13142 PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
13146 /* DMA test passed without adjusting DMA boundary,
13147 * now look for chipsets that are known to expose the
13148 * DMA bug without failing the test.
13150 if (pci_dev_present(dma_wait_state_chipsets
)) {
13151 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
13152 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
13155 /* Safe to use the calculated DMA boundary. */
13156 tp
->dma_rwctrl
= saved_dma_rwctrl
;
13158 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
13162 pci_free_consistent(tp
->pdev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
13167 static void __devinit
tg3_init_link_config(struct tg3
*tp
)
13169 tp
->link_config
.advertising
=
13170 (ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
13171 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
13172 ADVERTISED_1000baseT_Half
| ADVERTISED_1000baseT_Full
|
13173 ADVERTISED_Autoneg
| ADVERTISED_MII
);
13174 tp
->link_config
.speed
= SPEED_INVALID
;
13175 tp
->link_config
.duplex
= DUPLEX_INVALID
;
13176 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
13177 tp
->link_config
.active_speed
= SPEED_INVALID
;
13178 tp
->link_config
.active_duplex
= DUPLEX_INVALID
;
13179 tp
->link_config
.phy_is_low_power
= 0;
13180 tp
->link_config
.orig_speed
= SPEED_INVALID
;
13181 tp
->link_config
.orig_duplex
= DUPLEX_INVALID
;
13182 tp
->link_config
.orig_autoneg
= AUTONEG_INVALID
;
13185 static void __devinit
tg3_init_bufmgr_config(struct tg3
*tp
)
13187 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13188 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13189 DEFAULT_MB_RDMA_LOW_WATER_5705
;
13190 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13191 DEFAULT_MB_MACRX_LOW_WATER_5705
;
13192 tp
->bufmgr_config
.mbuf_high_water
=
13193 DEFAULT_MB_HIGH_WATER_5705
;
13194 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
) {
13195 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13196 DEFAULT_MB_MACRX_LOW_WATER_5906
;
13197 tp
->bufmgr_config
.mbuf_high_water
=
13198 DEFAULT_MB_HIGH_WATER_5906
;
13201 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13202 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
13203 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13204 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
13205 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13206 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
13208 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
13209 DEFAULT_MB_RDMA_LOW_WATER
;
13210 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
13211 DEFAULT_MB_MACRX_LOW_WATER
;
13212 tp
->bufmgr_config
.mbuf_high_water
=
13213 DEFAULT_MB_HIGH_WATER
;
13215 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
13216 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
13217 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
13218 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
13219 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
13220 DEFAULT_MB_HIGH_WATER_JUMBO
;
13223 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
13224 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
13227 static char * __devinit
tg3_phy_string(struct tg3
*tp
)
13229 switch (tp
->phy_id
& PHY_ID_MASK
) {
13230 case PHY_ID_BCM5400
: return "5400";
13231 case PHY_ID_BCM5401
: return "5401";
13232 case PHY_ID_BCM5411
: return "5411";
13233 case PHY_ID_BCM5701
: return "5701";
13234 case PHY_ID_BCM5703
: return "5703";
13235 case PHY_ID_BCM5704
: return "5704";
13236 case PHY_ID_BCM5705
: return "5705";
13237 case PHY_ID_BCM5750
: return "5750";
13238 case PHY_ID_BCM5752
: return "5752";
13239 case PHY_ID_BCM5714
: return "5714";
13240 case PHY_ID_BCM5780
: return "5780";
13241 case PHY_ID_BCM5755
: return "5755";
13242 case PHY_ID_BCM5787
: return "5787";
13243 case PHY_ID_BCM5784
: return "5784";
13244 case PHY_ID_BCM5756
: return "5722/5756";
13245 case PHY_ID_BCM5906
: return "5906";
13246 case PHY_ID_BCM5761
: return "5761";
13247 case PHY_ID_BCM8002
: return "8002/serdes";
13248 case 0: return "serdes";
13249 default: return "unknown";
13253 static char * __devinit
tg3_bus_string(struct tg3
*tp
, char *str
)
13255 if (tp
->tg3_flags2
& TG3_FLG2_PCI_EXPRESS
) {
13256 strcpy(str
, "PCI Express");
13258 } else if (tp
->tg3_flags
& TG3_FLAG_PCIX_MODE
) {
13259 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
13261 strcpy(str
, "PCIX:");
13263 if ((clock_ctrl
== 7) ||
13264 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
13265 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
13266 strcat(str
, "133MHz");
13267 else if (clock_ctrl
== 0)
13268 strcat(str
, "33MHz");
13269 else if (clock_ctrl
== 2)
13270 strcat(str
, "50MHz");
13271 else if (clock_ctrl
== 4)
13272 strcat(str
, "66MHz");
13273 else if (clock_ctrl
== 6)
13274 strcat(str
, "100MHz");
13276 strcpy(str
, "PCI:");
13277 if (tp
->tg3_flags
& TG3_FLAG_PCI_HIGH_SPEED
)
13278 strcat(str
, "66MHz");
13280 strcat(str
, "33MHz");
13282 if (tp
->tg3_flags
& TG3_FLAG_PCI_32BIT
)
13283 strcat(str
, ":32-bit");
13285 strcat(str
, ":64-bit");
13289 static struct pci_dev
* __devinit
tg3_find_peer(struct tg3
*tp
)
13291 struct pci_dev
*peer
;
13292 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
13294 for (func
= 0; func
< 8; func
++) {
13295 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
13296 if (peer
&& peer
!= tp
->pdev
)
13300 /* 5704 can be configured in single-port mode, set peer to
13301 * tp->pdev in that case.
13309 * We don't need to keep the refcount elevated; there's no way
13310 * to remove one half of this device without removing the other
13317 static void __devinit
tg3_init_coal(struct tg3
*tp
)
13319 struct ethtool_coalesce
*ec
= &tp
->coal
;
13321 memset(ec
, 0, sizeof(*ec
));
13322 ec
->cmd
= ETHTOOL_GCOALESCE
;
13323 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
13324 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
13325 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
13326 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
13327 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
13328 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
13329 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
13330 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
13331 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
13333 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
13334 HOSTCC_MODE_CLRTICK_TXBD
)) {
13335 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
13336 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
13337 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
13338 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
13341 if (tp
->tg3_flags2
& TG3_FLG2_5705_PLUS
) {
13342 ec
->rx_coalesce_usecs_irq
= 0;
13343 ec
->tx_coalesce_usecs_irq
= 0;
13344 ec
->stats_block_coalesce_usecs
= 0;
13348 static const struct net_device_ops tg3_netdev_ops
= {
13349 .ndo_open
= tg3_open
,
13350 .ndo_stop
= tg3_close
,
13351 .ndo_start_xmit
= tg3_start_xmit
,
13352 .ndo_get_stats
= tg3_get_stats
,
13353 .ndo_validate_addr
= eth_validate_addr
,
13354 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13355 .ndo_set_mac_address
= tg3_set_mac_addr
,
13356 .ndo_do_ioctl
= tg3_ioctl
,
13357 .ndo_tx_timeout
= tg3_tx_timeout
,
13358 .ndo_change_mtu
= tg3_change_mtu
,
13359 #if TG3_VLAN_TAG_USED
13360 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13362 #ifdef CONFIG_NET_POLL_CONTROLLER
13363 .ndo_poll_controller
= tg3_poll_controller
,
13367 static const struct net_device_ops tg3_netdev_ops_dma_bug
= {
13368 .ndo_open
= tg3_open
,
13369 .ndo_stop
= tg3_close
,
13370 .ndo_start_xmit
= tg3_start_xmit_dma_bug
,
13371 .ndo_get_stats
= tg3_get_stats
,
13372 .ndo_validate_addr
= eth_validate_addr
,
13373 .ndo_set_multicast_list
= tg3_set_rx_mode
,
13374 .ndo_set_mac_address
= tg3_set_mac_addr
,
13375 .ndo_do_ioctl
= tg3_ioctl
,
13376 .ndo_tx_timeout
= tg3_tx_timeout
,
13377 .ndo_change_mtu
= tg3_change_mtu
,
13378 #if TG3_VLAN_TAG_USED
13379 .ndo_vlan_rx_register
= tg3_vlan_rx_register
,
13381 #ifdef CONFIG_NET_POLL_CONTROLLER
13382 .ndo_poll_controller
= tg3_poll_controller
,
13386 static int __devinit
tg3_init_one(struct pci_dev
*pdev
,
13387 const struct pci_device_id
*ent
)
13389 static int tg3_version_printed
= 0;
13390 struct net_device
*dev
;
13394 u64 dma_mask
, persist_dma_mask
;
13396 if (tg3_version_printed
++ == 0)
13397 printk(KERN_INFO
"%s", version
);
13399 err
= pci_enable_device(pdev
);
13401 printk(KERN_ERR PFX
"Cannot enable PCI device, "
13406 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13408 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
13410 goto err_out_disable_pdev
;
13413 pci_set_master(pdev
);
13415 /* Find power-management capability. */
13416 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
13418 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
13421 goto err_out_free_res
;
13424 dev
= alloc_etherdev(sizeof(*tp
));
13426 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
13428 goto err_out_free_res
;
13431 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13433 #if TG3_VLAN_TAG_USED
13434 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
13437 tp
= netdev_priv(dev
);
13440 tp
->pm_cap
= pm_cap
;
13441 tp
->rx_mode
= TG3_DEF_RX_MODE
;
13442 tp
->tx_mode
= TG3_DEF_TX_MODE
;
13445 tp
->msg_enable
= tg3_debug
;
13447 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
13449 /* The word/byte swap controls here control register access byte
13450 * swapping. DMA data byte swapping is controlled in the GRC_MODE
13453 tp
->misc_host_ctrl
=
13454 MISC_HOST_CTRL_MASK_PCI_INT
|
13455 MISC_HOST_CTRL_WORD_SWAP
|
13456 MISC_HOST_CTRL_INDIR_ACCESS
|
13457 MISC_HOST_CTRL_PCISTATE_RW
;
13459 /* The NONFRM (non-frame) byte/word swap controls take effect
13460 * on descriptor entries, anything which isn't packet data.
13462 * The StrongARM chips on the board (one for tx, one for rx)
13463 * are running in big-endian mode.
13465 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
13466 GRC_MODE_WSWAP_NONFRM_DATA
);
13467 #ifdef __BIG_ENDIAN
13468 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
13470 spin_lock_init(&tp
->lock
);
13471 spin_lock_init(&tp
->indirect_lock
);
13472 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
13474 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
13476 printk(KERN_ERR PFX
"Cannot map device registers, "
13479 goto err_out_free_dev
;
13482 tg3_init_link_config(tp
);
13484 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
13485 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
13487 tp
->napi
[0].tp
= tp
;
13488 tp
->napi
[0].int_mbox
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
13489 tp
->napi
[0].consmbox
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
13490 tp
->napi
[0].prodmbox
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
13491 tp
->napi
[0].coal_now
= HOSTCC_MODE_NOW
;
13492 tp
->napi
[0].tx_pending
= TG3_DEF_TX_RING_PENDING
;
13493 netif_napi_add(dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
13494 dev
->ethtool_ops
= &tg3_ethtool_ops
;
13495 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
13496 dev
->irq
= pdev
->irq
;
13498 err
= tg3_get_invariants(tp
);
13500 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
13502 goto err_out_iounmap
;
13505 if ((tp
->tg3_flags3
& TG3_FLG3_5755_PLUS
) ||
13506 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
)
13507 dev
->netdev_ops
= &tg3_netdev_ops
;
13509 dev
->netdev_ops
= &tg3_netdev_ops_dma_bug
;
13512 /* The EPB bridge inside 5714, 5715, and 5780 and any
13513 * device behind the EPB cannot support DMA addresses > 40-bit.
13514 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13515 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13516 * do DMA address check in tg3_start_xmit().
13518 if (tp
->tg3_flags2
& TG3_FLG2_IS_5788
)
13519 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
13520 else if (tp
->tg3_flags
& TG3_FLAG_40BIT_DMA_BUG
) {
13521 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
13522 #ifdef CONFIG_HIGHMEM
13523 dma_mask
= DMA_BIT_MASK(64);
13526 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
13528 /* Configure DMA attributes. */
13529 if (dma_mask
> DMA_BIT_MASK(32)) {
13530 err
= pci_set_dma_mask(pdev
, dma_mask
);
13532 dev
->features
|= NETIF_F_HIGHDMA
;
13533 err
= pci_set_consistent_dma_mask(pdev
,
13536 printk(KERN_ERR PFX
"Unable to obtain 64 bit "
13537 "DMA for consistent allocations\n");
13538 goto err_out_iounmap
;
13542 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
13543 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
13545 printk(KERN_ERR PFX
"No usable DMA configuration, "
13547 goto err_out_iounmap
;
13551 tg3_init_bufmgr_config(tp
);
13553 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5701_A0
)
13554 tp
->fw_needed
= FIRMWARE_TG3
;
13556 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13557 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
;
13559 else if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5700
||
13560 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5701
||
13561 tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A0
||
13562 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5906
||
13563 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0) {
13564 tp
->tg3_flags2
&= ~TG3_FLG2_TSO_CAPABLE
;
13566 tp
->tg3_flags2
|= TG3_FLG2_TSO_CAPABLE
| TG3_FLG2_TSO_BUG
;
13567 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5705
)
13568 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
13570 tp
->fw_needed
= FIRMWARE_TG3TSO
;
13573 /* TSO is on by default on chips that support hardware TSO.
13574 * Firmware TSO on older chips gives lower performance, so it
13575 * is off by default, but can be enabled using ethtool.
13577 if (tp
->tg3_flags2
& TG3_FLG2_HW_TSO
) {
13578 if (dev
->features
& NETIF_F_IP_CSUM
)
13579 dev
->features
|= NETIF_F_TSO
;
13580 if ((dev
->features
& NETIF_F_IPV6_CSUM
) &&
13581 (tp
->tg3_flags2
& TG3_FLG2_HW_TSO_2
))
13582 dev
->features
|= NETIF_F_TSO6
;
13583 if (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5761
||
13584 (GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5784
&&
13585 GET_CHIP_REV(tp
->pci_chip_rev_id
) != CHIPREV_5784_AX
) ||
13586 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_5785
||
13587 GET_ASIC_REV(tp
->pci_chip_rev_id
) == ASIC_REV_57780
)
13588 dev
->features
|= NETIF_F_TSO_ECN
;
13592 if (tp
->pci_chip_rev_id
== CHIPREV_ID_5705_A1
&&
13593 !(tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) &&
13594 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
13595 tp
->tg3_flags2
|= TG3_FLG2_MAX_RXPEND_64
;
13596 tp
->rx_pending
= 63;
13599 err
= tg3_get_device_address(tp
);
13601 printk(KERN_ERR PFX
"Could not obtain valid ethernet address, "
13606 if (tp
->tg3_flags3
& TG3_FLG3_ENABLE_APE
) {
13607 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
13608 if (!tp
->aperegs
) {
13609 printk(KERN_ERR PFX
"Cannot map APE registers, "
13615 tg3_ape_lock_init(tp
);
13617 if (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
)
13618 tg3_read_dash_ver(tp
);
13622 * Reset chip in case UNDI or EFI driver did not shutdown
13623 * DMA self test will enable WDMAC and we'll see (spurious)
13624 * pending DMA on the PCI bus at that point.
13626 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
13627 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
13628 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
13629 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13632 err
= tg3_test_dma(tp
);
13634 printk(KERN_ERR PFX
"DMA engine test failed, aborting.\n");
13635 goto err_out_apeunmap
;
13638 /* flow control autonegotiation is default behavior */
13639 tp
->tg3_flags
|= TG3_FLAG_PAUSE_AUTONEG
;
13640 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
13644 pci_set_drvdata(pdev
, dev
);
13646 err
= register_netdev(dev
);
13648 printk(KERN_ERR PFX
"Cannot register net device, "
13650 goto err_out_apeunmap
;
13653 printk(KERN_INFO
"%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
13655 tp
->board_part_number
,
13656 tp
->pci_chip_rev_id
,
13657 tg3_bus_string(tp
, str
),
13660 if (tp
->tg3_flags3
& TG3_FLG3_PHY_CONNECTED
)
13662 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
13664 tp
->mdio_bus
->phy_map
[PHY_ADDR
]->drv
->name
,
13665 dev_name(&tp
->mdio_bus
->phy_map
[PHY_ADDR
]->dev
));
13668 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
13669 tp
->dev
->name
, tg3_phy_string(tp
),
13670 ((tp
->tg3_flags
& TG3_FLAG_10_100_ONLY
) ? "10/100Base-TX" :
13671 ((tp
->tg3_flags2
& TG3_FLG2_ANY_SERDES
) ? "1000Base-SX" :
13672 "10/100/1000Base-T")),
13673 (tp
->tg3_flags2
& TG3_FLG2_NO_ETH_WIRE_SPEED
) == 0);
13675 printk(KERN_INFO
"%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
13677 (tp
->tg3_flags
& TG3_FLAG_RX_CHECKSUMS
) != 0,
13678 (tp
->tg3_flags
& TG3_FLAG_USE_LINKCHG_REG
) != 0,
13679 (tp
->tg3_flags
& TG3_FLAG_USE_MI_INTERRUPT
) != 0,
13680 (tp
->tg3_flags
& TG3_FLAG_ENABLE_ASF
) != 0,
13681 (tp
->tg3_flags2
& TG3_FLG2_TSO_CAPABLE
) != 0);
13682 printk(KERN_INFO
"%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13683 dev
->name
, tp
->dma_rwctrl
,
13684 (pdev
->dma_mask
== DMA_BIT_MASK(32)) ? 32 :
13685 (((u64
) pdev
->dma_mask
== DMA_BIT_MASK(40)) ? 40 : 64));
13691 iounmap(tp
->aperegs
);
13692 tp
->aperegs
= NULL
;
13697 release_firmware(tp
->fw
);
13709 pci_release_regions(pdev
);
13711 err_out_disable_pdev
:
13712 pci_disable_device(pdev
);
13713 pci_set_drvdata(pdev
, NULL
);
13717 static void __devexit
tg3_remove_one(struct pci_dev
*pdev
)
13719 struct net_device
*dev
= pci_get_drvdata(pdev
);
13722 struct tg3
*tp
= netdev_priv(dev
);
13725 release_firmware(tp
->fw
);
13727 flush_scheduled_work();
13729 if (tp
->tg3_flags3
& TG3_FLG3_USE_PHYLIB
) {
13734 unregister_netdev(dev
);
13736 iounmap(tp
->aperegs
);
13737 tp
->aperegs
= NULL
;
13744 pci_release_regions(pdev
);
13745 pci_disable_device(pdev
);
13746 pci_set_drvdata(pdev
, NULL
);
13750 static int tg3_suspend(struct pci_dev
*pdev
, pm_message_t state
)
13752 struct net_device
*dev
= pci_get_drvdata(pdev
);
13753 struct tg3
*tp
= netdev_priv(dev
);
13754 pci_power_t target_state
;
13757 /* PCI register 4 needs to be saved whether netif_running() or not.
13758 * MSI address and data need to be saved if using MSI and
13761 pci_save_state(pdev
);
13763 if (!netif_running(dev
))
13766 flush_scheduled_work();
13768 tg3_netif_stop(tp
);
13770 del_timer_sync(&tp
->timer
);
13772 tg3_full_lock(tp
, 1);
13773 tg3_disable_ints(tp
);
13774 tg3_full_unlock(tp
);
13776 netif_device_detach(dev
);
13778 tg3_full_lock(tp
, 0);
13779 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13780 tp
->tg3_flags
&= ~TG3_FLAG_INIT_COMPLETE
;
13781 tg3_full_unlock(tp
);
13783 target_state
= pdev
->pm_cap
? pci_target_state(pdev
) : PCI_D3hot
;
13785 err
= tg3_set_power_state(tp
, target_state
);
13789 tg3_full_lock(tp
, 0);
13791 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13792 err2
= tg3_restart_hw(tp
, 1);
13796 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13797 add_timer(&tp
->timer
);
13799 netif_device_attach(dev
);
13800 tg3_netif_start(tp
);
13803 tg3_full_unlock(tp
);
13812 static int tg3_resume(struct pci_dev
*pdev
)
13814 struct net_device
*dev
= pci_get_drvdata(pdev
);
13815 struct tg3
*tp
= netdev_priv(dev
);
13818 pci_restore_state(tp
->pdev
);
13820 if (!netif_running(dev
))
13823 err
= tg3_set_power_state(tp
, PCI_D0
);
13827 netif_device_attach(dev
);
13829 tg3_full_lock(tp
, 0);
13831 tp
->tg3_flags
|= TG3_FLAG_INIT_COMPLETE
;
13832 err
= tg3_restart_hw(tp
, 1);
13836 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
13837 add_timer(&tp
->timer
);
13839 tg3_netif_start(tp
);
13842 tg3_full_unlock(tp
);
13850 static struct pci_driver tg3_driver
= {
13851 .name
= DRV_MODULE_NAME
,
13852 .id_table
= tg3_pci_tbl
,
13853 .probe
= tg3_init_one
,
13854 .remove
= __devexit_p(tg3_remove_one
),
13855 .suspend
= tg3_suspend
,
13856 .resume
= tg3_resume
13859 static int __init
tg3_init(void)
13861 return pci_register_driver(&tg3_driver
);
13864 static void __exit
tg3_cleanup(void)
13866 pci_unregister_driver(&tg3_driver
);
13869 module_init(tg3_init
);
13870 module_exit(tg3_cleanup
);