2 * Tehuti Networks(R) Network Driver
3 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/ethtool.h>
21 #include <linux/mii.h>
22 #include <linux/crc32.h>
23 #include <linux/uaccess.h>
26 #include <linux/tcp.h>
27 #include <linux/sched.h>
28 #include <linux/tty.h>
29 #include <linux/if_vlan.h>
30 #include <linux/interrupt.h>
31 #include <linux/vmalloc.h>
32 #include <linux/firmware.h>
33 #include <asm/byteorder.h>
34 #include <linux/dma-mapping.h>
36 /* Compile Time Switches */
40 #define BDX_DELAY_WPTR
44 #if !defined CONFIG_PCI_MSI
48 #define BDX_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
54 #define BDX_OP_WRITE 2
56 /* RX copy break size */
57 #define BDX_COPYBREAK 257
59 #define DRIVER_AUTHOR "Tehuti Networks(R)"
60 #define BDX_DRV_DESC "Tehuti Networks(R) Network Driver"
61 #define BDX_DRV_NAME "tehuti"
62 #define BDX_NIC_NAME "Tehuti 10 Giga TOE SmartNIC"
63 #define BDX_NIC2PORT_NAME "Tehuti 2-Port 10 Giga TOE SmartNIC"
64 #define BDX_DRV_VERSION "7.29.3"
67 # define BDX_MSI_STRING "msi "
69 # define BDX_MSI_STRING ""
72 /* netdev tx queue len for Luxor. default value is, btw, 1000
73 * ifcontig eth1 txqueuelen 3000 - to change it at runtime */
74 #define BDX_NDEV_TXQ_LEN 3000
76 #define FIFO_SIZE 4096
77 #define FIFO_EXTRA_SPACE 1024
79 #define MIN(x, y) ((x) < (y) ? (x) : (y))
81 #if BITS_PER_LONG == 64
82 # define H32_64(x) (u32) ((u64)(x) >> 32)
83 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
84 #elif BITS_PER_LONG == 32
86 # define L32_64(x) ((u32) (x))
87 #else /* BITS_PER_LONG == ?? */
88 # error BITS_PER_LONG is undefined. Must be 64 or 32
89 #endif /* BITS_PER_LONG */
92 # define CPU_CHIP_SWAP32(x) swab32(x)
93 # define CPU_CHIP_SWAP16(x) swab16(x)
95 # define CPU_CHIP_SWAP32(x) (x)
96 # define CPU_CHIP_SWAP16(x) (x)
99 #define READ_REG(pp, reg) readl(pp->pBdxRegs + reg)
100 #define WRITE_REG(pp, reg, val) writel(val, pp->pBdxRegs + reg)
102 #ifndef DMA_32BIT_MASK
103 # define DMA_32BIT_MASK 0x00000000ffffffffULL
107 # define NET_IP_ALIGN 2
111 # define NETDEV_TX_OK 0
114 #define LUXOR_MAX_PORT 2
115 #define BDX_MAX_RX_DONE 150
116 #define BDX_TXF_DESC_SZ 16
117 #define BDX_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16)
118 #define BDX_MIN_TX_LEVEL 256
119 #define BDX_NO_UPD_PACKETS 40
125 struct bdx_priv
*priv
[LUXOR_MAX_PORT
];
128 enum { IRQ_INTX
, IRQ_MSI
, IRQ_MSIX
};
130 #define PCK_TH_MULT 128
131 #define INT_COAL_MULT 2
133 #define BITS_MASK(nbits) ((1<<nbits)-1)
134 #define GET_BITS_SHIFT(x, nbits, nshift) (((x)>>nshift)&BITS_MASK(nbits))
135 #define BITS_SHIFT_MASK(nbits, nshift) (BITS_MASK(nbits)<<nshift)
136 #define BITS_SHIFT_VAL(x, nbits, nshift) (((x)&BITS_MASK(nbits))<<nshift)
137 #define BITS_SHIFT_CLEAR(x, nbits, nshift) \
138 ((x)&(~BITS_SHIFT_MASK(nbits, nshift)))
140 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
141 #define GET_INT_COAL_RC(x) GET_BITS_SHIFT(x, 1, 15)
142 #define GET_RXF_TH(x) GET_BITS_SHIFT(x, 4, 16)
143 #define GET_PCK_TH(x) GET_BITS_SHIFT(x, 4, 20)
145 #define INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) \
146 ((coal)|((coal_rc)<<15)|((rxf_th)<<16)|((pck_th)<<20))
149 dma_addr_t da
; /* physical address of fifo (used by HW) */
150 char *va
; /* virtual address of fifo (used by SW) */
151 u32 rptr
, wptr
; /* cached values of RPTR and WPTR registers,
152 they're 32 bits on both 32 and 64 archs */
153 u16 reg_CFG0
, reg_CFG1
;
154 u16 reg_RPTR
, reg_WPTR
;
155 u16 memsz
; /* memory size allocated for fifo */
157 u16 pktsz
; /* skb packet size to allocate */
158 u16 rcvno
; /* number of buffers that come from this RXF */
162 struct fifo m
; /* minimal set of variables used by all fifos */
166 struct fifo m
; /* minimal set of variables used by all fifos */
170 struct fifo m
; /* minimal set of variables used by all fifos */
174 struct fifo m
; /* minimal set of variables used by all fifos */
184 struct rx_map
*elems
;
195 * if len == 0 addr is dma
196 * if len != 0 addr is skb */
198 union bdx_dma_addr addr
;
202 /* tx database - implemented as circular fifo buffer*/
204 struct tx_map
*start
; /* points to the first element */
205 struct tx_map
*end
; /* points just AFTER the last element */
206 struct tx_map
*rptr
; /* points to the next element to read */
207 struct tx_map
*wptr
; /* points to the next element to write */
208 int size
; /* number of elements in the db */
211 /*Internal stats structure*/
213 u64 InUCast
; /* 0x7200 */
214 u64 InMCast
; /* 0x7210 */
215 u64 InBCast
; /* 0x7220 */
216 u64 InPkts
; /* 0x7230 */
217 u64 InErrors
; /* 0x7240 */
218 u64 InDropped
; /* 0x7250 */
219 u64 FrameTooLong
; /* 0x7260 */
220 u64 FrameSequenceErrors
; /* 0x7270 */
221 u64 InVLAN
; /* 0x7280 */
222 u64 InDroppedDFE
; /* 0x7290 */
223 u64 InDroppedIntFull
; /* 0x72A0 */
224 u64 InFrameAlignErrors
; /* 0x72B0 */
226 /* 0x72C0-0x72E0 RSRV */
228 u64 OutUCast
; /* 0x72F0 */
229 u64 OutMCast
; /* 0x7300 */
230 u64 OutBCast
; /* 0x7310 */
231 u64 OutPkts
; /* 0x7320 */
233 /* 0x7330-0x7360 RSRV */
235 u64 OutVLAN
; /* 0x7370 */
236 u64 InUCastOctects
; /* 0x7380 */
237 u64 OutUCastOctects
; /* 0x7390 */
239 /* 0x73A0-0x73B0 RSRV */
241 u64 InBCastOctects
; /* 0x73C0 */
242 u64 OutBCastOctects
; /* 0x73D0 */
243 u64 InOctects
; /* 0x73E0 */
244 u64 OutOctects
; /* 0x73F0 */
248 void __iomem
*pBdxRegs
;
249 struct net_device
*ndev
;
251 struct napi_struct napi
;
253 /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */
254 struct rxd_fifo rxd_fifo0
;
255 struct rxf_fifo rxf_fifo0
;
256 struct rxdb
*rxdb
; /* rx dbs to store skb pointers */
258 struct vlan_group
*vlgrp
;
260 /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */
261 struct txd_fifo txd_fifo0
;
262 struct txf_fifo txf_fifo0
;
266 #ifdef BDX_DELAY_WPTR
270 spinlock_t tx_lock
; /* NETIF_F_LLTX mode */
276 struct bdx_stats hw_stats
;
277 struct net_device_stats net_stats
;
278 struct pci_dev
*pdev
;
290 /* RX FREE descriptor - 64bit*/
292 u32 info
; /* Buffer Count + Info - described below */
293 u32 va_lo
; /* VAdr[31:0] */
294 u32 va_hi
; /* VAdr[63:32] */
295 u32 pa_lo
; /* PAdr[31:0] */
296 u32 pa_hi
; /* PAdr[63:32] */
297 u32 len
; /* Buffer Length */
300 #define GET_RXD_BC(x) GET_BITS_SHIFT((x), 5, 0)
301 #define GET_RXD_RXFQ(x) GET_BITS_SHIFT((x), 2, 8)
302 #define GET_RXD_TO(x) GET_BITS_SHIFT((x), 1, 15)
303 #define GET_RXD_TYPE(x) GET_BITS_SHIFT((x), 4, 16)
304 #define GET_RXD_ERR(x) GET_BITS_SHIFT((x), 6, 21)
305 #define GET_RXD_RXP(x) GET_BITS_SHIFT((x), 1, 27)
306 #define GET_RXD_PKT_ID(x) GET_BITS_SHIFT((x), 3, 28)
307 #define GET_RXD_VTAG(x) GET_BITS_SHIFT((x), 1, 31)
308 #define GET_RXD_VLAN_ID(x) GET_BITS_SHIFT((x), 12, 0)
309 #define GET_RXD_VLAN_TCI(x) GET_BITS_SHIFT((x), 16, 0)
310 #define GET_RXD_CFI(x) GET_BITS_SHIFT((x), 1, 12)
311 #define GET_RXD_PRIO(x) GET_BITS_SHIFT((x), 3, 13)
321 /* PBL describes each virtual buffer to be */
322 /* transmitted from the host.*/
329 /* First word for TXD descriptor. It means: type = 3 for regular Tx packet,
330 * hw_csum = 7 for ip+udp+tcp hw checksums */
331 #define TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) \
332 ((bc) | ((checksum)<<5) | ((vtag)<<8) | \
333 ((lgsnd)<<9) | (0x30000) | ((vlan_id)<<20))
341 struct pbl pbl
[0]; /* Fragments */
342 } __attribute__ ((packed
));
344 /* Register region size */
345 #define BDX_REGS_SIZE 0x1000
347 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
348 #define regTXD_CFG1_0 0x4000
349 #define regRXF_CFG1_0 0x4010
350 #define regRXD_CFG1_0 0x4020
351 #define regTXF_CFG1_0 0x4030
352 #define regTXD_CFG0_0 0x4040
353 #define regRXF_CFG0_0 0x4050
354 #define regRXD_CFG0_0 0x4060
355 #define regTXF_CFG0_0 0x4070
356 #define regTXD_WPTR_0 0x4080
357 #define regRXF_WPTR_0 0x4090
358 #define regRXD_WPTR_0 0x40A0
359 #define regTXF_WPTR_0 0x40B0
360 #define regTXD_RPTR_0 0x40C0
361 #define regRXF_RPTR_0 0x40D0
362 #define regRXD_RPTR_0 0x40E0
363 #define regTXF_RPTR_0 0x40F0
364 #define regTXF_RPTR_3 0x40FC
366 /* hardware versioning */
367 #define FW_VER 0x5010
368 #define SROM_VER 0x5020
369 #define FPGA_VER 0x5030
370 #define FPGA_SEED 0x5040
372 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */
373 #define regISR regISR0
374 #define regISR0 0x5100
376 #define regIMR regIMR0
377 #define regIMR0 0x5110
379 #define regRDINTCM0 0x5120
380 #define regRDINTCM2 0x5128
382 #define regTDINTCM0 0x5130
384 #define regISR_MSK0 0x5140
386 #define regINIT_SEMAPHORE 0x5170
387 #define regINIT_STATUS 0x5180
389 #define regMAC_LNK_STAT 0x0200
390 #define MAC_LINK_STAT 0x4 /* Link state */
392 #define regGMAC_RXF_A 0x1240
394 #define regUNC_MAC0_A 0x1250
395 #define regUNC_MAC1_A 0x1260
396 #define regUNC_MAC2_A 0x1270
398 #define regVLAN_0 0x1800
400 #define regMAX_FRAME_A 0x12C0
402 #define regRX_MAC_MCST0 0x1A80
403 #define regRX_MAC_MCST1 0x1A84
404 #define MAC_MCST_NUM 15
405 #define regRX_MCST_HASH0 0x1A00
406 #define MAC_MCST_HASH_NUM 8
408 #define regVPC 0x2300
409 #define regVIC 0x2320
410 #define regVGLB 0x2340
412 #define regCLKPLL 0x5000
415 #define regREVISION 0x6000
416 #define regSCRATCH 0x6004
417 #define regCTRLST 0x6008
418 #define regMAC_ADDR_0 0x600C
419 #define regMAC_ADDR_1 0x6010
420 #define regFRM_LENGTH 0x6014
421 #define regPAUSE_QUANT 0x6018
422 #define regRX_FIFO_SECTION 0x601C
423 #define regTX_FIFO_SECTION 0x6020
424 #define regRX_FULLNESS 0x6024
425 #define regTX_FULLNESS 0x6028
426 #define regHASHTABLE 0x602C
427 #define regMDIO_ST 0x6030
428 #define regMDIO_CTL 0x6034
429 #define regMDIO_DATA 0x6038
430 #define regMDIO_ADDR 0x603C
432 #define regRST_PORT 0x7000
433 #define regDIS_PORT 0x7010
434 #define regRST_QU 0x7020
435 #define regDIS_QU 0x7030
437 #define regCTRLST_TX_ENA 0x0001
438 #define regCTRLST_RX_ENA 0x0002
439 #define regCTRLST_PRM_ENA 0x0010
440 #define regCTRLST_PAD_ENA 0x0020
442 #define regCTRLST_BASE (regCTRLST_PAD_ENA|regCTRLST_PRM_ENA)
444 #define regRX_FLT 0x1400
446 /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c*/
447 #define TX_RX_CFG1_BASE 0xffffffff /*0-31 */
448 #define TX_RX_CFG0_BASE 0xfffff000 /*31:12 */
449 #define TX_RX_CFG0_RSVD 0x0ffc /*11:2 */
450 #define TX_RX_CFG0_SIZE 0x0003 /*1:0 */
452 /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */
453 #define TXF_WPTR_WR_PTR 0x7ff8 /*14:3 */
455 /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */
456 #define TXF_RPTR_RD_PTR 0x7ff8 /*14:3 */
458 #define TXF_WPTR_MASK 0x7ff0 /* last 4 bits are dropped
459 * size is rounded to 16 */
463 #define IMR_INPROG 0x80000000 /*31 */
464 #define IR_LNKCHG1 0x10000000 /*28 */
465 #define IR_LNKCHG0 0x08000000 /*27 */
466 #define IR_GPIO 0x04000000 /*26 */
467 #define IR_RFRSH 0x02000000 /*25 */
468 #define IR_RSVD 0x01000000 /*24 */
469 #define IR_SWI 0x00800000 /*23 */
470 #define IR_RX_FREE_3 0x00400000 /*22 */
471 #define IR_RX_FREE_2 0x00200000 /*21 */
472 #define IR_RX_FREE_1 0x00100000 /*20 */
473 #define IR_RX_FREE_0 0x00080000 /*19 */
474 #define IR_TX_FREE_3 0x00040000 /*18 */
475 #define IR_TX_FREE_2 0x00020000 /*17 */
476 #define IR_TX_FREE_1 0x00010000 /*16 */
477 #define IR_TX_FREE_0 0x00008000 /*15 */
478 #define IR_RX_DESC_3 0x00004000 /*14 */
479 #define IR_RX_DESC_2 0x00002000 /*13 */
480 #define IR_RX_DESC_1 0x00001000 /*12 */
481 #define IR_RX_DESC_0 0x00000800 /*11 */
482 #define IR_PSE 0x00000400 /*10 */
483 #define IR_TMR3 0x00000200 /*9 */
484 #define IR_TMR2 0x00000100 /*8 */
485 #define IR_TMR1 0x00000080 /*7 */
486 #define IR_TMR0 0x00000040 /*6 */
487 #define IR_VNT 0x00000020 /*5 */
488 #define IR_RxFL 0x00000010 /*4 */
489 #define IR_SDPERR 0x00000008 /*3 */
490 #define IR_TR 0x00000004 /*2 */
491 #define IR_PCIE_LINK 0x00000002 /*1 */
492 #define IR_PCIE_TOUT 0x00000001 /*0 */
494 #define IR_EXTRA (IR_RX_FREE_0 | IR_LNKCHG0 | IR_PSE | \
495 IR_TMR0 | IR_PCIE_LINK | IR_PCIE_TOUT)
496 #define IR_RUN (IR_EXTRA | IR_RX_DESC_0 | IR_TX_FREE_0)
497 #define IR_ALL 0xfdfffff7
499 #define IR_LNKCHG0_ofst 27
501 #define GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */
502 #define GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */
503 #define GMAC_RX_FILTER_RSV0 0x0200 /* reserved */
504 #define GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */
505 #define GMAC_RX_FILTER_AOF 0x0080 /* accept over run */
506 #define GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */
507 #define GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */
508 #define GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */
509 #define GMAC_RX_FILTER_AM 0x0008 /* accept multicast */
510 #define GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */
511 #define GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscous mode */
513 #define MAX_FRAME_AB_VAL 0x3fff /* 13:0 */
515 #define CLKPLL_PLLLKD 0x0200 /*9 */
516 #define CLKPLL_RSTEND 0x0100 /*8 */
517 #define CLKPLL_SFTRST 0x0001 /*0 */
519 #define CLKPLL_LKD (CLKPLL_PLLLKD|CLKPLL_RSTEND)
522 * PCI-E Device Control Register (Offset 0x88)
523 * Source: Luxor Data Sheet, 7.1.3.3.3
525 #define PCI_DEV_CTRL_REG 0x88
526 #define GET_DEV_CTRL_MAXPL(x) GET_BITS_SHIFT(x, 3, 5)
527 #define GET_DEV_CTRL_MRRS(x) GET_BITS_SHIFT(x, 3, 12)
530 * PCI-E Link Status Register (Offset 0x92)
531 * Source: Luxor Data Sheet, 7.1.3.3.7
533 #define PCI_LINK_STATUS_REG 0x92
534 #define GET_LINK_STATUS_LANES(x) GET_BITS_SHIFT(x, 6, 4)
536 /* Debugging Macros */
538 #define ERR(fmt, args...) printk(KERN_ERR fmt, ## args)
539 #define DBG2(fmt, args...) \
540 printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args)
542 #define BDX_ASSERT(x) BUG_ON(x)
547 printk(KERN_ERR "%s:%-5d: ENTER\n", __func__, __LINE__); \
550 #define RET(args...) do { \
551 printk(KERN_ERR "%s:%-5d: RETURN\n", __func__, __LINE__); \
552 return args; } while (0)
554 #define DBG(fmt, args...) \
555 printk(KERN_ERR "%s:%-5d: " fmt, __func__, __LINE__, ## args)
557 #define ENTER do { } while (0)
558 #define RET(args...) return args
559 #define DBG(fmt, args...) do { } while (0)