net: remove interrupt.h inclusion from netdevice.h
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / starfire.c
1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
2 /*
3 Written 1998-2000 by Donald Becker.
4
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
8
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
15
16 The information below comes from Donald Becker's original driver:
17
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
21 Annapolis MD 21403
22
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
26
27 */
28
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.1"
31 #define DRV_RELDATE "July 6, 2008"
32
33 #include <linux/interrupt.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/crc32.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/if_vlan.h>
45 #include <linux/mm.h>
46 #include <linux/firmware.h>
47 #include <asm/processor.h> /* Processor type for cache alignment. */
48 #include <asm/uaccess.h>
49 #include <asm/io.h>
50
51 /*
52 * The current frame processor firmware fails to checksum a fragment
53 * of length 1. If and when this is fixed, the #define below can be removed.
54 */
55 #define HAS_BROKEN_FIRMWARE
56
57 /*
58 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 */
60 #ifdef HAS_BROKEN_FIRMWARE
61 #define PADDING_MASK 3
62 #endif
63
64 /*
65 * Define this if using the driver with the zero-copy patch
66 */
67 #define ZEROCOPY
68
69 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
70 #define VLAN_SUPPORT
71 #endif
72
73 /* The user-configurable values.
74 These may be modified when a driver module is loaded.*/
75
76 /* Used for tuning interrupt latency vs. overhead. */
77 static int intr_latency;
78 static int small_frames;
79
80 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
81 static int max_interrupt_work = 20;
82 static int mtu;
83 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
84 The Starfire has a 512 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 512;
86 /* Whether to do TCP/UDP checksums in hardware */
87 static int enable_hw_cksum = 1;
88
89 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
90 /*
91 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
92 * Setting to > 1518 effectively disables this feature.
93 *
94 * NOTE:
95 * The ia64 doesn't allow for unaligned loads even of integers being
96 * misaligned on a 2 byte boundary. Thus always force copying of
97 * packets as the starfire doesn't allow for misaligned DMAs ;-(
98 * 23/10/2000 - Jes
99 *
100 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
101 * at least, having unaligned frames leads to a rather serious performance
102 * penalty. -Ion
103 */
104 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
105 static int rx_copybreak = PKT_BUF_SZ;
106 #else
107 static int rx_copybreak /* = 0 */;
108 #endif
109
110 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
111 #ifdef __sparc__
112 #define DMA_BURST_SIZE 64
113 #else
114 #define DMA_BURST_SIZE 128
115 #endif
116
117 /* Used to pass the media type, etc.
118 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
119 The media type is usually passed in 'options[]'.
120 These variables are deprecated, use ethtool instead. -Ion
121 */
122 #define MAX_UNITS 8 /* More are supported, limit only on options */
123 static int options[MAX_UNITS] = {0, };
124 static int full_duplex[MAX_UNITS] = {0, };
125
126 /* Operational parameters that are set at compile time. */
127
128 /* The "native" ring sizes are either 256 or 2048.
129 However in some modes a descriptor may be marked to wrap the ring earlier.
130 */
131 #define RX_RING_SIZE 256
132 #define TX_RING_SIZE 32
133 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
134 #define DONE_Q_SIZE 1024
135 /* All queues must be aligned on a 256-byte boundary */
136 #define QUEUE_ALIGN 256
137
138 #if RX_RING_SIZE > 256
139 #define RX_Q_ENTRIES Rx2048QEntries
140 #else
141 #define RX_Q_ENTRIES Rx256QEntries
142 #endif
143
144 /* Operational parameters that usually are not changed. */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (2 * HZ)
147
148 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
149 /* 64-bit dma_addr_t */
150 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
151 #define netdrv_addr_t __le64
152 #define cpu_to_dma(x) cpu_to_le64(x)
153 #define dma_to_cpu(x) le64_to_cpu(x)
154 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
155 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
156 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
157 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
158 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
159 #else /* 32-bit dma_addr_t */
160 #define netdrv_addr_t __le32
161 #define cpu_to_dma(x) cpu_to_le32(x)
162 #define dma_to_cpu(x) le32_to_cpu(x)
163 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
164 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
165 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
166 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
167 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
168 #endif
169
170 #define skb_first_frag_len(skb) skb_headlen(skb)
171 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
172
173 /* Firmware names */
174 #define FIRMWARE_RX "adaptec/starfire_rx.bin"
175 #define FIRMWARE_TX "adaptec/starfire_tx.bin"
176
177 /* These identify the driver base version and may not be removed. */
178 static const char version[] __devinitconst =
179 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
180 " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
181
182 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
183 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_RX);
187 MODULE_FIRMWARE(FIRMWARE_TX);
188
189 module_param(max_interrupt_work, int, 0);
190 module_param(mtu, int, 0);
191 module_param(debug, int, 0);
192 module_param(rx_copybreak, int, 0);
193 module_param(intr_latency, int, 0);
194 module_param(small_frames, int, 0);
195 module_param_array(options, int, NULL, 0);
196 module_param_array(full_duplex, int, NULL, 0);
197 module_param(enable_hw_cksum, int, 0);
198 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
199 MODULE_PARM_DESC(mtu, "MTU (all boards)");
200 MODULE_PARM_DESC(debug, "Debug level (0-6)");
201 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
202 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
203 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
204 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
205 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
206 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
207
208 /*
209 Theory of Operation
210
211 I. Board Compatibility
212
213 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
214
215 II. Board-specific settings
216
217 III. Driver operation
218
219 IIIa. Ring buffers
220
221 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
222 ring sizes are set fixed by the hardware, but may optionally be wrapped
223 earlier by the END bit in the descriptor.
224 This driver uses that hardware queue size for the Rx ring, where a large
225 number of entries has no ill effect beyond increases the potential backlog.
226 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
227 disables the queue layer priority ordering and we have no mechanism to
228 utilize the hardware two-level priority queue. When modifying the
229 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
230 levels.
231
232 IIIb/c. Transmit/Receive Structure
233
234 See the Adaptec manual for the many possible structures, and options for
235 each structure. There are far too many to document all of them here.
236
237 For transmit this driver uses type 0/1 transmit descriptors (depending
238 on the 32/64 bitness of the architecture), and relies on automatic
239 minimum-length padding. It does not use the completion queue
240 consumer index, but instead checks for non-zero status entries.
241
242 For receive this driver uses type 2/3 receive descriptors. The driver
243 allocates full frame size skbuffs for the Rx ring buffers, so all frames
244 should fit in a single descriptor. The driver does not use the completion
245 queue consumer index, but instead checks for non-zero status entries.
246
247 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
248 is allocated and the frame is copied to the new skbuff. When the incoming
249 frame is larger, the skbuff is passed directly up the protocol stack.
250 Buffers consumed this way are replaced by newly allocated skbuffs in a later
251 phase of receive.
252
253 A notable aspect of operation is that unaligned buffers are not permitted by
254 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
255 isn't longword aligned, which may cause problems on some machine
256 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
257 the frame into a new skbuff unconditionally. Copied frames are put into the
258 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
259
260 IIId. Synchronization
261
262 The driver runs as two independent, single-threaded flows of control. One
263 is the send-packet routine, which enforces single-threaded use by the
264 dev->tbusy flag. The other thread is the interrupt handler, which is single
265 threaded by the hardware and interrupt handling software.
266
267 The send packet thread has partial control over the Tx ring and the netif_queue
268 status. If the number of free Tx slots in the ring falls below a certain number
269 (currently hardcoded to 4), it signals the upper layer to stop the queue.
270
271 The interrupt handler has exclusive control over the Rx ring and records stats
272 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
273 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
274 number of free Tx slow is above the threshold, it signals the upper layer to
275 restart the queue.
276
277 IV. Notes
278
279 IVb. References
280
281 The Adaptec Starfire manuals, available only from Adaptec.
282 http://www.scyld.com/expert/100mbps.html
283 http://www.scyld.com/expert/NWay.html
284
285 IVc. Errata
286
287 - StopOnPerr is broken, don't enable
288 - Hardware ethernet padding exposes random data, perform software padding
289 instead (unverified -- works correctly for all the hardware I have)
290
291 */
292
293
294
295 enum chip_capability_flags {CanHaveMII=1, };
296
297 enum chipset {
298 CH_6915 = 0,
299 };
300
301 static DEFINE_PCI_DEVICE_TABLE(starfire_pci_tbl) = {
302 { PCI_VDEVICE(ADAPTEC, 0x6915), CH_6915 },
303 { 0, }
304 };
305 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
306
307 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
308 static const struct chip_info {
309 const char *name;
310 int drv_flags;
311 } netdrv_tbl[] __devinitdata = {
312 { "Adaptec Starfire 6915", CanHaveMII },
313 };
314
315
316 /* Offsets to the device registers.
317 Unlike software-only systems, device drivers interact with complex hardware.
318 It's not useful to define symbolic names for every register bit in the
319 device. The name can only partially document the semantics and make
320 the driver longer and more difficult to read.
321 In general, only the important configuration values or bits changed
322 multiple times should be defined symbolically.
323 */
324 enum register_offsets {
325 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
326 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
327 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
328 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
329 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
330 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
331 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
332 TxThreshold=0x500B0,
333 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
334 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
335 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
336 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
337 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
338 TxMode=0x55000, VlanType=0x55064,
339 PerfFilterTable=0x56000, HashTable=0x56100,
340 TxGfpMem=0x58000, RxGfpMem=0x5a000,
341 };
342
343 /*
344 * Bits in the interrupt status/mask registers.
345 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
346 * enables all the interrupt sources that are or'ed into those status bits.
347 */
348 enum intr_status_bits {
349 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
350 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
351 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
352 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
353 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
354 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
355 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
356 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
357 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
358 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
359 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
360 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
361 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
362 IntrTxGfp=0x02, IntrPCIPad=0x01,
363 /* not quite bits */
364 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
365 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
366 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
367 };
368
369 /* Bits in the RxFilterMode register. */
370 enum rx_mode_bits {
371 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
372 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
373 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
374 WakeupOnGFP=0x0800,
375 };
376
377 /* Bits in the TxMode register */
378 enum tx_mode_bits {
379 MiiSoftReset=0x8000, MIILoopback=0x4000,
380 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
381 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
382 };
383
384 /* Bits in the TxDescCtrl register. */
385 enum tx_ctrl_bits {
386 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
387 TxDescSpace128=0x30, TxDescSpace256=0x40,
388 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
389 TxDescType3=0x03, TxDescType4=0x04,
390 TxNoDMACompletion=0x08,
391 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
392 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
393 TxDMABurstSizeShift=8,
394 };
395
396 /* Bits in the RxDescQCtrl register. */
397 enum rx_ctrl_bits {
398 RxBufferLenShift=16, RxMinDescrThreshShift=0,
399 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
400 Rx2048QEntries=0x4000, Rx256QEntries=0,
401 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
402 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
403 RxDescSpace4=0x000, RxDescSpace8=0x100,
404 RxDescSpace16=0x200, RxDescSpace32=0x300,
405 RxDescSpace64=0x400, RxDescSpace128=0x500,
406 RxConsumerWrEn=0x80,
407 };
408
409 /* Bits in the RxDMACtrl register. */
410 enum rx_dmactrl_bits {
411 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
412 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
413 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
414 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
415 RxChecksumRejectTCPOnly=0x01000000,
416 RxCompletionQ2Enable=0x800000,
417 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
418 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
419 RxDMAQ2NonIP=0x400000,
420 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
421 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
422 RxBurstSizeShift=0,
423 };
424
425 /* Bits in the RxCompletionAddr register */
426 enum rx_compl_bits {
427 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
428 RxComplProducerWrEn=0x40,
429 RxComplType0=0x00, RxComplType1=0x10,
430 RxComplType2=0x20, RxComplType3=0x30,
431 RxComplThreshShift=0,
432 };
433
434 /* Bits in the TxCompletionAddr register */
435 enum tx_compl_bits {
436 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
437 TxComplProducerWrEn=0x40,
438 TxComplIntrStatus=0x20,
439 CommonQueueMode=0x10,
440 TxComplThreshShift=0,
441 };
442
443 /* Bits in the GenCtrl register */
444 enum gen_ctrl_bits {
445 RxEnable=0x05, TxEnable=0x0a,
446 RxGFPEnable=0x10, TxGFPEnable=0x20,
447 };
448
449 /* Bits in the IntrTimerCtrl register */
450 enum intr_ctrl_bits {
451 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
452 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
453 IntrLatencyMask=0x1f,
454 };
455
456 /* The Rx and Tx buffer descriptors. */
457 struct starfire_rx_desc {
458 netdrv_addr_t rxaddr;
459 };
460 enum rx_desc_bits {
461 RxDescValid=1, RxDescEndRing=2,
462 };
463
464 /* Completion queue entry. */
465 struct short_rx_done_desc {
466 __le32 status; /* Low 16 bits is length. */
467 };
468 struct basic_rx_done_desc {
469 __le32 status; /* Low 16 bits is length. */
470 __le16 vlanid;
471 __le16 status2;
472 };
473 struct csum_rx_done_desc {
474 __le32 status; /* Low 16 bits is length. */
475 __le16 csum; /* Partial checksum */
476 __le16 status2;
477 };
478 struct full_rx_done_desc {
479 __le32 status; /* Low 16 bits is length. */
480 __le16 status3;
481 __le16 status2;
482 __le16 vlanid;
483 __le16 csum; /* partial checksum */
484 __le32 timestamp;
485 };
486 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
487 #ifdef VLAN_SUPPORT
488 typedef struct full_rx_done_desc rx_done_desc;
489 #define RxComplType RxComplType3
490 #else /* not VLAN_SUPPORT */
491 typedef struct csum_rx_done_desc rx_done_desc;
492 #define RxComplType RxComplType2
493 #endif /* not VLAN_SUPPORT */
494
495 enum rx_done_bits {
496 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
497 };
498
499 /* Type 1 Tx descriptor. */
500 struct starfire_tx_desc_1 {
501 __le32 status; /* Upper bits are status, lower 16 length. */
502 __le32 addr;
503 };
504
505 /* Type 2 Tx descriptor. */
506 struct starfire_tx_desc_2 {
507 __le32 status; /* Upper bits are status, lower 16 length. */
508 __le32 reserved;
509 __le64 addr;
510 };
511
512 #ifdef ADDR_64BITS
513 typedef struct starfire_tx_desc_2 starfire_tx_desc;
514 #define TX_DESC_TYPE TxDescType2
515 #else /* not ADDR_64BITS */
516 typedef struct starfire_tx_desc_1 starfire_tx_desc;
517 #define TX_DESC_TYPE TxDescType1
518 #endif /* not ADDR_64BITS */
519 #define TX_DESC_SPACING TxDescSpaceUnlim
520
521 enum tx_desc_bits {
522 TxDescID=0xB0000000,
523 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
524 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
525 };
526 struct tx_done_desc {
527 __le32 status; /* timestamp, index. */
528 #if 0
529 __le32 intrstatus; /* interrupt status */
530 #endif
531 };
532
533 struct rx_ring_info {
534 struct sk_buff *skb;
535 dma_addr_t mapping;
536 };
537 struct tx_ring_info {
538 struct sk_buff *skb;
539 dma_addr_t mapping;
540 unsigned int used_slots;
541 };
542
543 #define PHY_CNT 2
544 struct netdev_private {
545 /* Descriptor rings first for alignment. */
546 struct starfire_rx_desc *rx_ring;
547 starfire_tx_desc *tx_ring;
548 dma_addr_t rx_ring_dma;
549 dma_addr_t tx_ring_dma;
550 /* The addresses of rx/tx-in-place skbuffs. */
551 struct rx_ring_info rx_info[RX_RING_SIZE];
552 struct tx_ring_info tx_info[TX_RING_SIZE];
553 /* Pointers to completion queues (full pages). */
554 rx_done_desc *rx_done_q;
555 dma_addr_t rx_done_q_dma;
556 unsigned int rx_done;
557 struct tx_done_desc *tx_done_q;
558 dma_addr_t tx_done_q_dma;
559 unsigned int tx_done;
560 struct napi_struct napi;
561 struct net_device *dev;
562 struct pci_dev *pci_dev;
563 #ifdef VLAN_SUPPORT
564 struct vlan_group *vlgrp;
565 #endif
566 void *queue_mem;
567 dma_addr_t queue_mem_dma;
568 size_t queue_mem_size;
569
570 /* Frequently used values: keep some adjacent for cache effect. */
571 spinlock_t lock;
572 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
573 unsigned int cur_tx, dirty_tx, reap_tx;
574 unsigned int rx_buf_sz; /* Based on MTU+slack. */
575 /* These values keep track of the transceiver/media in use. */
576 int speed100; /* Set if speed == 100MBit. */
577 u32 tx_mode;
578 u32 intr_timer_ctrl;
579 u8 tx_threshold;
580 /* MII transceiver section. */
581 struct mii_if_info mii_if; /* MII lib hooks/info */
582 int phy_cnt; /* MII device addresses. */
583 unsigned char phys[PHY_CNT]; /* MII device addresses. */
584 void __iomem *base;
585 };
586
587
588 static int mdio_read(struct net_device *dev, int phy_id, int location);
589 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
590 static int netdev_open(struct net_device *dev);
591 static void check_duplex(struct net_device *dev);
592 static void tx_timeout(struct net_device *dev);
593 static void init_ring(struct net_device *dev);
594 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
595 static irqreturn_t intr_handler(int irq, void *dev_instance);
596 static void netdev_error(struct net_device *dev, int intr_status);
597 static int __netdev_rx(struct net_device *dev, int *quota);
598 static int netdev_poll(struct napi_struct *napi, int budget);
599 static void refill_rx_ring(struct net_device *dev);
600 static void netdev_error(struct net_device *dev, int intr_status);
601 static void set_rx_mode(struct net_device *dev);
602 static struct net_device_stats *get_stats(struct net_device *dev);
603 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
604 static int netdev_close(struct net_device *dev);
605 static void netdev_media_change(struct net_device *dev);
606 static const struct ethtool_ops ethtool_ops;
607
608
609 #ifdef VLAN_SUPPORT
610 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
611 {
612 struct netdev_private *np = netdev_priv(dev);
613
614 spin_lock(&np->lock);
615 if (debug > 2)
616 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
617 np->vlgrp = grp;
618 set_rx_mode(dev);
619 spin_unlock(&np->lock);
620 }
621
622 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
623 {
624 struct netdev_private *np = netdev_priv(dev);
625
626 spin_lock(&np->lock);
627 if (debug > 1)
628 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
629 set_rx_mode(dev);
630 spin_unlock(&np->lock);
631 }
632
633 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
634 {
635 struct netdev_private *np = netdev_priv(dev);
636
637 spin_lock(&np->lock);
638 if (debug > 1)
639 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
640 vlan_group_set_device(np->vlgrp, vid, NULL);
641 set_rx_mode(dev);
642 spin_unlock(&np->lock);
643 }
644 #endif /* VLAN_SUPPORT */
645
646
647 static const struct net_device_ops netdev_ops = {
648 .ndo_open = netdev_open,
649 .ndo_stop = netdev_close,
650 .ndo_start_xmit = start_tx,
651 .ndo_tx_timeout = tx_timeout,
652 .ndo_get_stats = get_stats,
653 .ndo_set_multicast_list = &set_rx_mode,
654 .ndo_do_ioctl = netdev_ioctl,
655 .ndo_change_mtu = eth_change_mtu,
656 .ndo_set_mac_address = eth_mac_addr,
657 .ndo_validate_addr = eth_validate_addr,
658 #ifdef VLAN_SUPPORT
659 .ndo_vlan_rx_register = netdev_vlan_rx_register,
660 .ndo_vlan_rx_add_vid = netdev_vlan_rx_add_vid,
661 .ndo_vlan_rx_kill_vid = netdev_vlan_rx_kill_vid,
662 #endif
663 };
664
665 static int __devinit starfire_init_one(struct pci_dev *pdev,
666 const struct pci_device_id *ent)
667 {
668 struct netdev_private *np;
669 int i, irq, option, chip_idx = ent->driver_data;
670 struct net_device *dev;
671 static int card_idx = -1;
672 long ioaddr;
673 void __iomem *base;
674 int drv_flags, io_size;
675 int boguscnt;
676
677 /* when built into the kernel, we only print version if device is found */
678 #ifndef MODULE
679 static int printed_version;
680 if (!printed_version++)
681 printk(version);
682 #endif
683
684 card_idx++;
685
686 if (pci_enable_device (pdev))
687 return -EIO;
688
689 ioaddr = pci_resource_start(pdev, 0);
690 io_size = pci_resource_len(pdev, 0);
691 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
692 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
693 return -ENODEV;
694 }
695
696 dev = alloc_etherdev(sizeof(*np));
697 if (!dev) {
698 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
699 return -ENOMEM;
700 }
701 SET_NETDEV_DEV(dev, &pdev->dev);
702
703 irq = pdev->irq;
704
705 if (pci_request_regions (pdev, DRV_NAME)) {
706 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
707 goto err_out_free_netdev;
708 }
709
710 base = ioremap(ioaddr, io_size);
711 if (!base) {
712 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
713 card_idx, io_size, ioaddr);
714 goto err_out_free_res;
715 }
716
717 pci_set_master(pdev);
718
719 /* enable MWI -- it vastly improves Rx performance on sparc64 */
720 pci_try_set_mwi(pdev);
721
722 #ifdef ZEROCOPY
723 /* Starfire can do TCP/UDP checksumming */
724 if (enable_hw_cksum)
725 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
726 #endif /* ZEROCOPY */
727
728 #ifdef VLAN_SUPPORT
729 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
730 #endif /* VLAN_RX_KILL_VID */
731 #ifdef ADDR_64BITS
732 dev->features |= NETIF_F_HIGHDMA;
733 #endif /* ADDR_64BITS */
734
735 /* Serial EEPROM reads are hidden by the hardware. */
736 for (i = 0; i < 6; i++)
737 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
738
739 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
740 if (debug > 4)
741 for (i = 0; i < 0x20; i++)
742 printk("%2.2x%s",
743 (unsigned int)readb(base + EEPROMCtrl + i),
744 i % 16 != 15 ? " " : "\n");
745 #endif
746
747 /* Issue soft reset */
748 writel(MiiSoftReset, base + TxMode);
749 udelay(1000);
750 writel(0, base + TxMode);
751
752 /* Reset the chip to erase previous misconfiguration. */
753 writel(1, base + PCIDeviceConfig);
754 boguscnt = 1000;
755 while (--boguscnt > 0) {
756 udelay(10);
757 if ((readl(base + PCIDeviceConfig) & 1) == 0)
758 break;
759 }
760 if (boguscnt == 0)
761 printk("%s: chipset reset never completed!\n", dev->name);
762 /* wait a little longer */
763 udelay(1000);
764
765 dev->base_addr = (unsigned long)base;
766 dev->irq = irq;
767
768 np = netdev_priv(dev);
769 np->dev = dev;
770 np->base = base;
771 spin_lock_init(&np->lock);
772 pci_set_drvdata(pdev, dev);
773
774 np->pci_dev = pdev;
775
776 np->mii_if.dev = dev;
777 np->mii_if.mdio_read = mdio_read;
778 np->mii_if.mdio_write = mdio_write;
779 np->mii_if.phy_id_mask = 0x1f;
780 np->mii_if.reg_num_mask = 0x1f;
781
782 drv_flags = netdrv_tbl[chip_idx].drv_flags;
783
784 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
785 if (dev->mem_start)
786 option = dev->mem_start;
787
788 /* The lower four bits are the media type. */
789 if (option & 0x200)
790 np->mii_if.full_duplex = 1;
791
792 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
793 np->mii_if.full_duplex = 1;
794
795 if (np->mii_if.full_duplex)
796 np->mii_if.force_media = 1;
797 else
798 np->mii_if.force_media = 0;
799 np->speed100 = 1;
800
801 /* timer resolution is 128 * 0.8us */
802 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
803 Timer10X | EnableIntrMasking;
804
805 if (small_frames > 0) {
806 np->intr_timer_ctrl |= SmallFrameBypass;
807 switch (small_frames) {
808 case 1 ... 64:
809 np->intr_timer_ctrl |= SmallFrame64;
810 break;
811 case 65 ... 128:
812 np->intr_timer_ctrl |= SmallFrame128;
813 break;
814 case 129 ... 256:
815 np->intr_timer_ctrl |= SmallFrame256;
816 break;
817 default:
818 np->intr_timer_ctrl |= SmallFrame512;
819 if (small_frames > 512)
820 printk("Adjusting small_frames down to 512\n");
821 break;
822 }
823 }
824
825 dev->netdev_ops = &netdev_ops;
826 dev->watchdog_timeo = TX_TIMEOUT;
827 SET_ETHTOOL_OPS(dev, &ethtool_ops);
828
829 netif_napi_add(dev, &np->napi, netdev_poll, max_interrupt_work);
830
831 if (mtu)
832 dev->mtu = mtu;
833
834 if (register_netdev(dev))
835 goto err_out_cleardev;
836
837 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
838 dev->name, netdrv_tbl[chip_idx].name, base,
839 dev->dev_addr, irq);
840
841 if (drv_flags & CanHaveMII) {
842 int phy, phy_idx = 0;
843 int mii_status;
844 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
845 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
846 mdelay(100);
847 boguscnt = 1000;
848 while (--boguscnt > 0)
849 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
850 break;
851 if (boguscnt == 0) {
852 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
853 continue;
854 }
855 mii_status = mdio_read(dev, phy, MII_BMSR);
856 if (mii_status != 0) {
857 np->phys[phy_idx++] = phy;
858 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
859 printk(KERN_INFO "%s: MII PHY found at address %d, status "
860 "%#4.4x advertising %#4.4x.\n",
861 dev->name, phy, mii_status, np->mii_if.advertising);
862 /* there can be only one PHY on-board */
863 break;
864 }
865 }
866 np->phy_cnt = phy_idx;
867 if (np->phy_cnt > 0)
868 np->mii_if.phy_id = np->phys[0];
869 else
870 memset(&np->mii_if, 0, sizeof(np->mii_if));
871 }
872
873 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
874 dev->name, enable_hw_cksum ? "enabled" : "disabled");
875 return 0;
876
877 err_out_cleardev:
878 pci_set_drvdata(pdev, NULL);
879 iounmap(base);
880 err_out_free_res:
881 pci_release_regions (pdev);
882 err_out_free_netdev:
883 free_netdev(dev);
884 return -ENODEV;
885 }
886
887
888 /* Read the MII Management Data I/O (MDIO) interfaces. */
889 static int mdio_read(struct net_device *dev, int phy_id, int location)
890 {
891 struct netdev_private *np = netdev_priv(dev);
892 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
893 int result, boguscnt=1000;
894 /* ??? Should we add a busy-wait here? */
895 do {
896 result = readl(mdio_addr);
897 } while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
898 if (boguscnt == 0)
899 return 0;
900 if ((result & 0xffff) == 0xffff)
901 return 0;
902 return result & 0xffff;
903 }
904
905
906 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
907 {
908 struct netdev_private *np = netdev_priv(dev);
909 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
910 writel(value, mdio_addr);
911 /* The busy-wait will occur before a read. */
912 }
913
914
915 static int netdev_open(struct net_device *dev)
916 {
917 const struct firmware *fw_rx, *fw_tx;
918 const __be32 *fw_rx_data, *fw_tx_data;
919 struct netdev_private *np = netdev_priv(dev);
920 void __iomem *ioaddr = np->base;
921 int i, retval;
922 size_t tx_size, rx_size;
923 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
924
925 /* Do we ever need to reset the chip??? */
926
927 retval = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
928 if (retval)
929 return retval;
930
931 /* Disable the Rx and Tx, and reset the chip. */
932 writel(0, ioaddr + GenCtrl);
933 writel(1, ioaddr + PCIDeviceConfig);
934 if (debug > 1)
935 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
936 dev->name, dev->irq);
937
938 /* Allocate the various queues. */
939 if (!np->queue_mem) {
940 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
941 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
942 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
943 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
944 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
945 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
946 if (np->queue_mem == NULL) {
947 free_irq(dev->irq, dev);
948 return -ENOMEM;
949 }
950
951 np->tx_done_q = np->queue_mem;
952 np->tx_done_q_dma = np->queue_mem_dma;
953 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
954 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
955 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
956 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
957 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
958 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
959 }
960
961 /* Start with no carrier, it gets adjusted later */
962 netif_carrier_off(dev);
963 init_ring(dev);
964 /* Set the size of the Rx buffers. */
965 writel((np->rx_buf_sz << RxBufferLenShift) |
966 (0 << RxMinDescrThreshShift) |
967 RxPrefetchMode | RxVariableQ |
968 RX_Q_ENTRIES |
969 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
970 RxDescSpace4,
971 ioaddr + RxDescQCtrl);
972
973 /* Set up the Rx DMA controller. */
974 writel(RxChecksumIgnore |
975 (0 << RxEarlyIntThreshShift) |
976 (6 << RxHighPrioThreshShift) |
977 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
978 ioaddr + RxDMACtrl);
979
980 /* Set Tx descriptor */
981 writel((2 << TxHiPriFIFOThreshShift) |
982 (0 << TxPadLenShift) |
983 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
984 TX_DESC_Q_ADDR_SIZE |
985 TX_DESC_SPACING | TX_DESC_TYPE,
986 ioaddr + TxDescCtrl);
987
988 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
989 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
990 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
991 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
992 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
993
994 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
995 writel(np->rx_done_q_dma |
996 RxComplType |
997 (0 << RxComplThreshShift),
998 ioaddr + RxCompletionAddr);
999
1000 if (debug > 1)
1001 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1002
1003 /* Fill both the Tx SA register and the Rx perfect filter. */
1004 for (i = 0; i < 6; i++)
1005 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1006 /* The first entry is special because it bypasses the VLAN filter.
1007 Don't use it. */
1008 writew(0, ioaddr + PerfFilterTable);
1009 writew(0, ioaddr + PerfFilterTable + 4);
1010 writew(0, ioaddr + PerfFilterTable + 8);
1011 for (i = 1; i < 16; i++) {
1012 __be16 *eaddrs = (__be16 *)dev->dev_addr;
1013 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1014 writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
1015 writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
1016 writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
1017 }
1018
1019 /* Initialize other registers. */
1020 /* Configure the PCI bus bursts and FIFO thresholds. */
1021 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1022 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1023 udelay(1000);
1024 writel(np->tx_mode, ioaddr + TxMode);
1025 np->tx_threshold = 4;
1026 writel(np->tx_threshold, ioaddr + TxThreshold);
1027
1028 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1029
1030 napi_enable(&np->napi);
1031
1032 netif_start_queue(dev);
1033
1034 if (debug > 1)
1035 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1036 set_rx_mode(dev);
1037
1038 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1039 check_duplex(dev);
1040
1041 /* Enable GPIO interrupts on link change */
1042 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1043
1044 /* Set the interrupt mask */
1045 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1046 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1047 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1048 ioaddr + IntrEnable);
1049 /* Enable PCI interrupts. */
1050 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1051 ioaddr + PCIDeviceConfig);
1052
1053 #ifdef VLAN_SUPPORT
1054 /* Set VLAN type to 802.1q */
1055 writel(ETH_P_8021Q, ioaddr + VlanType);
1056 #endif /* VLAN_SUPPORT */
1057
1058 retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev);
1059 if (retval) {
1060 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1061 FIRMWARE_RX);
1062 goto out_init;
1063 }
1064 if (fw_rx->size % 4) {
1065 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1066 fw_rx->size, FIRMWARE_RX);
1067 retval = -EINVAL;
1068 goto out_rx;
1069 }
1070 retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev);
1071 if (retval) {
1072 printk(KERN_ERR "starfire: Failed to load firmware \"%s\"\n",
1073 FIRMWARE_TX);
1074 goto out_rx;
1075 }
1076 if (fw_tx->size % 4) {
1077 printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n",
1078 fw_tx->size, FIRMWARE_TX);
1079 retval = -EINVAL;
1080 goto out_tx;
1081 }
1082 fw_rx_data = (const __be32 *)&fw_rx->data[0];
1083 fw_tx_data = (const __be32 *)&fw_tx->data[0];
1084 rx_size = fw_rx->size / 4;
1085 tx_size = fw_tx->size / 4;
1086
1087 /* Load Rx/Tx firmware into the frame processors */
1088 for (i = 0; i < rx_size; i++)
1089 writel(be32_to_cpup(&fw_rx_data[i]), ioaddr + RxGfpMem + i * 4);
1090 for (i = 0; i < tx_size; i++)
1091 writel(be32_to_cpup(&fw_tx_data[i]), ioaddr + TxGfpMem + i * 4);
1092 if (enable_hw_cksum)
1093 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1094 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1095 else
1096 /* Enable the Rx and Tx units only. */
1097 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1098
1099 if (debug > 1)
1100 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1101 dev->name);
1102
1103 out_tx:
1104 release_firmware(fw_tx);
1105 out_rx:
1106 release_firmware(fw_rx);
1107 out_init:
1108 if (retval)
1109 netdev_close(dev);
1110 return retval;
1111 }
1112
1113
1114 static void check_duplex(struct net_device *dev)
1115 {
1116 struct netdev_private *np = netdev_priv(dev);
1117 u16 reg0;
1118 int silly_count = 1000;
1119
1120 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1121 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1122 udelay(500);
1123 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1124 /* do nothing */;
1125 if (!silly_count) {
1126 printk("%s: MII reset failed!\n", dev->name);
1127 return;
1128 }
1129
1130 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1131
1132 if (!np->mii_if.force_media) {
1133 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1134 } else {
1135 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1136 if (np->speed100)
1137 reg0 |= BMCR_SPEED100;
1138 if (np->mii_if.full_duplex)
1139 reg0 |= BMCR_FULLDPLX;
1140 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1141 dev->name,
1142 np->speed100 ? "100" : "10",
1143 np->mii_if.full_duplex ? "full" : "half");
1144 }
1145 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1146 }
1147
1148
1149 static void tx_timeout(struct net_device *dev)
1150 {
1151 struct netdev_private *np = netdev_priv(dev);
1152 void __iomem *ioaddr = np->base;
1153 int old_debug;
1154
1155 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1156 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1157
1158 /* Perhaps we should reinitialize the hardware here. */
1159
1160 /*
1161 * Stop and restart the interface.
1162 * Cheat and increase the debug level temporarily.
1163 */
1164 old_debug = debug;
1165 debug = 2;
1166 netdev_close(dev);
1167 netdev_open(dev);
1168 debug = old_debug;
1169
1170 /* Trigger an immediate transmit demand. */
1171
1172 dev->trans_start = jiffies; /* prevent tx timeout */
1173 dev->stats.tx_errors++;
1174 netif_wake_queue(dev);
1175 }
1176
1177
1178 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1179 static void init_ring(struct net_device *dev)
1180 {
1181 struct netdev_private *np = netdev_priv(dev);
1182 int i;
1183
1184 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1185 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1186
1187 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1188
1189 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1191 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1192 np->rx_info[i].skb = skb;
1193 if (skb == NULL)
1194 break;
1195 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1196 skb->dev = dev; /* Mark as being used by this device. */
1197 /* Grrr, we cannot offset to correctly align the IP header. */
1198 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1199 }
1200 writew(i - 1, np->base + RxDescQIdx);
1201 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1202
1203 /* Clear the remainder of the Rx buffer ring. */
1204 for ( ; i < RX_RING_SIZE; i++) {
1205 np->rx_ring[i].rxaddr = 0;
1206 np->rx_info[i].skb = NULL;
1207 np->rx_info[i].mapping = 0;
1208 }
1209 /* Mark the last entry as wrapping the ring. */
1210 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1211
1212 /* Clear the completion rings. */
1213 for (i = 0; i < DONE_Q_SIZE; i++) {
1214 np->rx_done_q[i].status = 0;
1215 np->tx_done_q[i].status = 0;
1216 }
1217
1218 for (i = 0; i < TX_RING_SIZE; i++)
1219 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1220 }
1221
1222
1223 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1224 {
1225 struct netdev_private *np = netdev_priv(dev);
1226 unsigned int entry;
1227 u32 status;
1228 int i;
1229
1230 /*
1231 * be cautious here, wrapping the queue has weird semantics
1232 * and we may not have enough slots even when it seems we do.
1233 */
1234 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1235 netif_stop_queue(dev);
1236 return NETDEV_TX_BUSY;
1237 }
1238
1239 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1240 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1241 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1242 return NETDEV_TX_OK;
1243 }
1244 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1245
1246 entry = np->cur_tx % TX_RING_SIZE;
1247 for (i = 0; i < skb_num_frags(skb); i++) {
1248 int wrap_ring = 0;
1249 status = TxDescID;
1250
1251 if (i == 0) {
1252 np->tx_info[entry].skb = skb;
1253 status |= TxCRCEn;
1254 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1255 status |= TxRingWrap;
1256 wrap_ring = 1;
1257 }
1258 if (np->reap_tx) {
1259 status |= TxDescIntr;
1260 np->reap_tx = 0;
1261 }
1262 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1263 status |= TxCalTCP;
1264 dev->stats.tx_compressed++;
1265 }
1266 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1267
1268 np->tx_info[entry].mapping =
1269 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1270 } else {
1271 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1272 status |= this_frag->size;
1273 np->tx_info[entry].mapping =
1274 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1275 }
1276
1277 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1278 np->tx_ring[entry].status = cpu_to_le32(status);
1279 if (debug > 3)
1280 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1281 dev->name, np->cur_tx, np->dirty_tx,
1282 entry, status);
1283 if (wrap_ring) {
1284 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1285 np->cur_tx += np->tx_info[entry].used_slots;
1286 entry = 0;
1287 } else {
1288 np->tx_info[entry].used_slots = 1;
1289 np->cur_tx += np->tx_info[entry].used_slots;
1290 entry++;
1291 }
1292 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1293 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1294 np->reap_tx = 1;
1295 }
1296
1297 /* Non-x86: explicitly flush descriptor cache lines here. */
1298 /* Ensure all descriptors are written back before the transmit is
1299 initiated. - Jes */
1300 wmb();
1301
1302 /* Update the producer index. */
1303 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1304
1305 /* 4 is arbitrary, but should be ok */
1306 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1307 netif_stop_queue(dev);
1308
1309 return NETDEV_TX_OK;
1310 }
1311
1312
1313 /* The interrupt handler does all of the Rx thread work and cleans up
1314 after the Tx thread. */
1315 static irqreturn_t intr_handler(int irq, void *dev_instance)
1316 {
1317 struct net_device *dev = dev_instance;
1318 struct netdev_private *np = netdev_priv(dev);
1319 void __iomem *ioaddr = np->base;
1320 int boguscnt = max_interrupt_work;
1321 int consumer;
1322 int tx_status;
1323 int handled = 0;
1324
1325 do {
1326 u32 intr_status = readl(ioaddr + IntrClear);
1327
1328 if (debug > 4)
1329 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1330 dev->name, intr_status);
1331
1332 if (intr_status == 0 || intr_status == (u32) -1)
1333 break;
1334
1335 handled = 1;
1336
1337 if (intr_status & (IntrRxDone | IntrRxEmpty)) {
1338 u32 enable;
1339
1340 if (likely(napi_schedule_prep(&np->napi))) {
1341 __napi_schedule(&np->napi);
1342 enable = readl(ioaddr + IntrEnable);
1343 enable &= ~(IntrRxDone | IntrRxEmpty);
1344 writel(enable, ioaddr + IntrEnable);
1345 /* flush PCI posting buffers */
1346 readl(ioaddr + IntrEnable);
1347 } else {
1348 /* Paranoia check */
1349 enable = readl(ioaddr + IntrEnable);
1350 if (enable & (IntrRxDone | IntrRxEmpty)) {
1351 printk(KERN_INFO
1352 "%s: interrupt while in poll!\n",
1353 dev->name);
1354 enable &= ~(IntrRxDone | IntrRxEmpty);
1355 writel(enable, ioaddr + IntrEnable);
1356 }
1357 }
1358 }
1359
1360 /* Scavenge the skbuff list based on the Tx-done queue.
1361 There are redundant checks here that may be cleaned up
1362 after the driver has proven to be reliable. */
1363 consumer = readl(ioaddr + TxConsumerIdx);
1364 if (debug > 3)
1365 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1366 dev->name, consumer);
1367
1368 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1369 if (debug > 3)
1370 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1371 dev->name, np->dirty_tx, np->tx_done, tx_status);
1372 if ((tx_status & 0xe0000000) == 0xa0000000) {
1373 dev->stats.tx_packets++;
1374 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1375 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1376 struct sk_buff *skb = np->tx_info[entry].skb;
1377 np->tx_info[entry].skb = NULL;
1378 pci_unmap_single(np->pci_dev,
1379 np->tx_info[entry].mapping,
1380 skb_first_frag_len(skb),
1381 PCI_DMA_TODEVICE);
1382 np->tx_info[entry].mapping = 0;
1383 np->dirty_tx += np->tx_info[entry].used_slots;
1384 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1385 {
1386 int i;
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1388 pci_unmap_single(np->pci_dev,
1389 np->tx_info[entry].mapping,
1390 skb_shinfo(skb)->frags[i].size,
1391 PCI_DMA_TODEVICE);
1392 np->dirty_tx++;
1393 entry++;
1394 }
1395 }
1396
1397 dev_kfree_skb_irq(skb);
1398 }
1399 np->tx_done_q[np->tx_done].status = 0;
1400 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1401 }
1402 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1403
1404 if (netif_queue_stopped(dev) &&
1405 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1406 /* The ring is no longer full, wake the queue. */
1407 netif_wake_queue(dev);
1408 }
1409
1410 /* Stats overflow */
1411 if (intr_status & IntrStatsMax)
1412 get_stats(dev);
1413
1414 /* Media change interrupt. */
1415 if (intr_status & IntrLinkChange)
1416 netdev_media_change(dev);
1417
1418 /* Abnormal error summary/uncommon events handlers. */
1419 if (intr_status & IntrAbnormalSummary)
1420 netdev_error(dev, intr_status);
1421
1422 if (--boguscnt < 0) {
1423 if (debug > 1)
1424 printk(KERN_WARNING "%s: Too much work at interrupt, "
1425 "status=%#8.8x.\n",
1426 dev->name, intr_status);
1427 break;
1428 }
1429 } while (1);
1430
1431 if (debug > 4)
1432 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1433 dev->name, (int) readl(ioaddr + IntrStatus));
1434 return IRQ_RETVAL(handled);
1435 }
1436
1437
1438 /*
1439 * This routine is logically part of the interrupt/poll handler, but separated
1440 * for clarity and better register allocation.
1441 */
1442 static int __netdev_rx(struct net_device *dev, int *quota)
1443 {
1444 struct netdev_private *np = netdev_priv(dev);
1445 u32 desc_status;
1446 int retcode = 0;
1447
1448 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1449 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1450 struct sk_buff *skb;
1451 u16 pkt_len;
1452 int entry;
1453 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1454
1455 if (debug > 4)
1456 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1457 if (!(desc_status & RxOK)) {
1458 /* There was an error. */
1459 if (debug > 2)
1460 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1461 dev->stats.rx_errors++;
1462 if (desc_status & RxFIFOErr)
1463 dev->stats.rx_fifo_errors++;
1464 goto next_rx;
1465 }
1466
1467 if (*quota <= 0) { /* out of rx quota */
1468 retcode = 1;
1469 goto out;
1470 }
1471 (*quota)--;
1472
1473 pkt_len = desc_status; /* Implicitly Truncate */
1474 entry = (desc_status >> 16) & 0x7ff;
1475
1476 if (debug > 4)
1477 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1478 /* Check if the packet is long enough to accept without copying
1479 to a minimally-sized skbuff. */
1480 if (pkt_len < rx_copybreak &&
1481 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1482 skb_reserve(skb, 2); /* 16 byte align the IP header */
1483 pci_dma_sync_single_for_cpu(np->pci_dev,
1484 np->rx_info[entry].mapping,
1485 pkt_len, PCI_DMA_FROMDEVICE);
1486 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1487 pci_dma_sync_single_for_device(np->pci_dev,
1488 np->rx_info[entry].mapping,
1489 pkt_len, PCI_DMA_FROMDEVICE);
1490 skb_put(skb, pkt_len);
1491 } else {
1492 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1493 skb = np->rx_info[entry].skb;
1494 skb_put(skb, pkt_len);
1495 np->rx_info[entry].skb = NULL;
1496 np->rx_info[entry].mapping = 0;
1497 }
1498 #ifndef final_version /* Remove after testing. */
1499 /* You will want this info for the initial debug. */
1500 if (debug > 5) {
1501 printk(KERN_DEBUG " Rx data %pM %pM %2.2x%2.2x.\n",
1502 skb->data, skb->data + 6,
1503 skb->data[12], skb->data[13]);
1504 }
1505 #endif
1506
1507 skb->protocol = eth_type_trans(skb, dev);
1508 #ifdef VLAN_SUPPORT
1509 if (debug > 4)
1510 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1511 #endif
1512 if (le16_to_cpu(desc->status2) & 0x0100) {
1513 skb->ip_summed = CHECKSUM_UNNECESSARY;
1514 dev->stats.rx_compressed++;
1515 }
1516 /*
1517 * This feature doesn't seem to be working, at least
1518 * with the two firmware versions I have. If the GFP sees
1519 * an IP fragment, it either ignores it completely, or reports
1520 * "bad checksum" on it.
1521 *
1522 * Maybe I missed something -- corrections are welcome.
1523 * Until then, the printk stays. :-) -Ion
1524 */
1525 else if (le16_to_cpu(desc->status2) & 0x0040) {
1526 skb->ip_summed = CHECKSUM_COMPLETE;
1527 skb->csum = le16_to_cpu(desc->csum);
1528 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1529 }
1530 #ifdef VLAN_SUPPORT
1531 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1532 u16 vlid = le16_to_cpu(desc->vlanid);
1533
1534 if (debug > 4) {
1535 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n",
1536 vlid);
1537 }
1538 /*
1539 * vlan_hwaccel_rx expects a packet with the VLAN tag
1540 * stripped out.
1541 */
1542 vlan_hwaccel_rx(skb, np->vlgrp, vlid);
1543 } else
1544 #endif /* VLAN_SUPPORT */
1545 netif_receive_skb(skb);
1546 dev->stats.rx_packets++;
1547
1548 next_rx:
1549 np->cur_rx++;
1550 desc->status = 0;
1551 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1552 }
1553
1554 if (*quota == 0) { /* out of rx quota */
1555 retcode = 1;
1556 goto out;
1557 }
1558 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1559
1560 out:
1561 refill_rx_ring(dev);
1562 if (debug > 5)
1563 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1564 retcode, np->rx_done, desc_status);
1565 return retcode;
1566 }
1567
1568 static int netdev_poll(struct napi_struct *napi, int budget)
1569 {
1570 struct netdev_private *np = container_of(napi, struct netdev_private, napi);
1571 struct net_device *dev = np->dev;
1572 u32 intr_status;
1573 void __iomem *ioaddr = np->base;
1574 int quota = budget;
1575
1576 do {
1577 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1578
1579 if (__netdev_rx(dev, &quota))
1580 goto out;
1581
1582 intr_status = readl(ioaddr + IntrStatus);
1583 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1584
1585 napi_complete(napi);
1586 intr_status = readl(ioaddr + IntrEnable);
1587 intr_status |= IntrRxDone | IntrRxEmpty;
1588 writel(intr_status, ioaddr + IntrEnable);
1589
1590 out:
1591 if (debug > 5)
1592 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n",
1593 budget - quota);
1594
1595 /* Restart Rx engine if stopped. */
1596 return budget - quota;
1597 }
1598
1599 static void refill_rx_ring(struct net_device *dev)
1600 {
1601 struct netdev_private *np = netdev_priv(dev);
1602 struct sk_buff *skb;
1603 int entry = -1;
1604
1605 /* Refill the Rx ring buffers. */
1606 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1607 entry = np->dirty_rx % RX_RING_SIZE;
1608 if (np->rx_info[entry].skb == NULL) {
1609 skb = dev_alloc_skb(np->rx_buf_sz);
1610 np->rx_info[entry].skb = skb;
1611 if (skb == NULL)
1612 break; /* Better luck next round. */
1613 np->rx_info[entry].mapping =
1614 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1615 skb->dev = dev; /* Mark as being used by this device. */
1616 np->rx_ring[entry].rxaddr =
1617 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1618 }
1619 if (entry == RX_RING_SIZE - 1)
1620 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1621 }
1622 if (entry >= 0)
1623 writew(entry, np->base + RxDescQIdx);
1624 }
1625
1626
1627 static void netdev_media_change(struct net_device *dev)
1628 {
1629 struct netdev_private *np = netdev_priv(dev);
1630 void __iomem *ioaddr = np->base;
1631 u16 reg0, reg1, reg4, reg5;
1632 u32 new_tx_mode;
1633 u32 new_intr_timer_ctrl;
1634
1635 /* reset status first */
1636 mdio_read(dev, np->phys[0], MII_BMCR);
1637 mdio_read(dev, np->phys[0], MII_BMSR);
1638
1639 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1640 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1641
1642 if (reg1 & BMSR_LSTATUS) {
1643 /* link is up */
1644 if (reg0 & BMCR_ANENABLE) {
1645 /* autonegotiation is enabled */
1646 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1647 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1648 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1649 np->speed100 = 1;
1650 np->mii_if.full_duplex = 1;
1651 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1652 np->speed100 = 1;
1653 np->mii_if.full_duplex = 0;
1654 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1655 np->speed100 = 0;
1656 np->mii_if.full_duplex = 1;
1657 } else {
1658 np->speed100 = 0;
1659 np->mii_if.full_duplex = 0;
1660 }
1661 } else {
1662 /* autonegotiation is disabled */
1663 if (reg0 & BMCR_SPEED100)
1664 np->speed100 = 1;
1665 else
1666 np->speed100 = 0;
1667 if (reg0 & BMCR_FULLDPLX)
1668 np->mii_if.full_duplex = 1;
1669 else
1670 np->mii_if.full_duplex = 0;
1671 }
1672 netif_carrier_on(dev);
1673 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1674 dev->name,
1675 np->speed100 ? "100" : "10",
1676 np->mii_if.full_duplex ? "full" : "half");
1677
1678 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1679 if (np->mii_if.full_duplex)
1680 new_tx_mode |= FullDuplex;
1681 if (np->tx_mode != new_tx_mode) {
1682 np->tx_mode = new_tx_mode;
1683 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1684 udelay(1000);
1685 writel(np->tx_mode, ioaddr + TxMode);
1686 }
1687
1688 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1689 if (np->speed100)
1690 new_intr_timer_ctrl |= Timer10X;
1691 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1692 np->intr_timer_ctrl = new_intr_timer_ctrl;
1693 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1694 }
1695 } else {
1696 netif_carrier_off(dev);
1697 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1698 }
1699 }
1700
1701
1702 static void netdev_error(struct net_device *dev, int intr_status)
1703 {
1704 struct netdev_private *np = netdev_priv(dev);
1705
1706 /* Came close to underrunning the Tx FIFO, increase threshold. */
1707 if (intr_status & IntrTxDataLow) {
1708 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1709 writel(++np->tx_threshold, np->base + TxThreshold);
1710 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1711 dev->name, np->tx_threshold * 16);
1712 } else
1713 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1714 }
1715 if (intr_status & IntrRxGFPDead) {
1716 dev->stats.rx_fifo_errors++;
1717 dev->stats.rx_errors++;
1718 }
1719 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1720 dev->stats.tx_fifo_errors++;
1721 dev->stats.tx_errors++;
1722 }
1723 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1724 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1725 dev->name, intr_status);
1726 }
1727
1728
1729 static struct net_device_stats *get_stats(struct net_device *dev)
1730 {
1731 struct netdev_private *np = netdev_priv(dev);
1732 void __iomem *ioaddr = np->base;
1733
1734 /* This adapter architecture needs no SMP locks. */
1735 dev->stats.tx_bytes = readl(ioaddr + 0x57010);
1736 dev->stats.rx_bytes = readl(ioaddr + 0x57044);
1737 dev->stats.tx_packets = readl(ioaddr + 0x57000);
1738 dev->stats.tx_aborted_errors =
1739 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1740 dev->stats.tx_window_errors = readl(ioaddr + 0x57018);
1741 dev->stats.collisions =
1742 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1743
1744 /* The chip only need report frame silently dropped. */
1745 dev->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1746 writew(0, ioaddr + RxDMAStatus);
1747 dev->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1748 dev->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1749 dev->stats.rx_length_errors = readl(ioaddr + 0x57058);
1750 dev->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1751
1752 return &dev->stats;
1753 }
1754
1755
1756 static void set_rx_mode(struct net_device *dev)
1757 {
1758 struct netdev_private *np = netdev_priv(dev);
1759 void __iomem *ioaddr = np->base;
1760 u32 rx_mode = MinVLANPrio;
1761 struct netdev_hw_addr *ha;
1762 int i;
1763 #ifdef VLAN_SUPPORT
1764
1765 rx_mode |= VlanMode;
1766 if (np->vlgrp) {
1767 int vlan_count = 0;
1768 void __iomem *filter_addr = ioaddr + HashTable + 8;
1769 for (i = 0; i < VLAN_VID_MASK; i++) {
1770 if (vlan_group_get_device(np->vlgrp, i)) {
1771 if (vlan_count >= 32)
1772 break;
1773 writew(i, filter_addr);
1774 filter_addr += 16;
1775 vlan_count++;
1776 }
1777 }
1778 if (i == VLAN_VID_MASK) {
1779 rx_mode |= PerfectFilterVlan;
1780 while (vlan_count < 32) {
1781 writew(0, filter_addr);
1782 filter_addr += 16;
1783 vlan_count++;
1784 }
1785 }
1786 }
1787 #endif /* VLAN_SUPPORT */
1788
1789 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1790 rx_mode |= AcceptAll;
1791 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
1792 (dev->flags & IFF_ALLMULTI)) {
1793 /* Too many to match, or accept all multicasts. */
1794 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1795 } else if (netdev_mc_count(dev) <= 14) {
1796 /* Use the 16 element perfect filter, skip first two entries. */
1797 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1798 __be16 *eaddrs;
1799 netdev_for_each_mc_addr(ha, dev) {
1800 eaddrs = (__be16 *) ha->addr;
1801 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
1802 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1803 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
1804 }
1805 eaddrs = (__be16 *)dev->dev_addr;
1806 i = netdev_mc_count(dev) + 2;
1807 while (i++ < 16) {
1808 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1809 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1810 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1811 }
1812 rx_mode |= AcceptBroadcast|PerfectFilter;
1813 } else {
1814 /* Must use a multicast hash table. */
1815 void __iomem *filter_addr;
1816 __be16 *eaddrs;
1817 __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1818
1819 memset(mc_filter, 0, sizeof(mc_filter));
1820 netdev_for_each_mc_addr(ha, dev) {
1821 /* The chip uses the upper 9 CRC bits
1822 as index into the hash table */
1823 int bit_nr = ether_crc_le(ETH_ALEN, ha->addr) >> 23;
1824 __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
1825
1826 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1827 }
1828 /* Clear the perfect filter list, skip first two entries. */
1829 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1830 eaddrs = (__be16 *)dev->dev_addr;
1831 for (i = 2; i < 16; i++) {
1832 writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
1833 writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
1834 writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
1835 }
1836 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1837 writew(mc_filter[i], filter_addr);
1838 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1839 }
1840 writel(rx_mode, ioaddr + RxFilterMode);
1841 }
1842
1843 static int check_if_running(struct net_device *dev)
1844 {
1845 if (!netif_running(dev))
1846 return -EINVAL;
1847 return 0;
1848 }
1849
1850 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1851 {
1852 struct netdev_private *np = netdev_priv(dev);
1853 strcpy(info->driver, DRV_NAME);
1854 strcpy(info->version, DRV_VERSION);
1855 strcpy(info->bus_info, pci_name(np->pci_dev));
1856 }
1857
1858 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1859 {
1860 struct netdev_private *np = netdev_priv(dev);
1861 spin_lock_irq(&np->lock);
1862 mii_ethtool_gset(&np->mii_if, ecmd);
1863 spin_unlock_irq(&np->lock);
1864 return 0;
1865 }
1866
1867 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1868 {
1869 struct netdev_private *np = netdev_priv(dev);
1870 int res;
1871 spin_lock_irq(&np->lock);
1872 res = mii_ethtool_sset(&np->mii_if, ecmd);
1873 spin_unlock_irq(&np->lock);
1874 check_duplex(dev);
1875 return res;
1876 }
1877
1878 static int nway_reset(struct net_device *dev)
1879 {
1880 struct netdev_private *np = netdev_priv(dev);
1881 return mii_nway_restart(&np->mii_if);
1882 }
1883
1884 static u32 get_link(struct net_device *dev)
1885 {
1886 struct netdev_private *np = netdev_priv(dev);
1887 return mii_link_ok(&np->mii_if);
1888 }
1889
1890 static u32 get_msglevel(struct net_device *dev)
1891 {
1892 return debug;
1893 }
1894
1895 static void set_msglevel(struct net_device *dev, u32 val)
1896 {
1897 debug = val;
1898 }
1899
1900 static const struct ethtool_ops ethtool_ops = {
1901 .begin = check_if_running,
1902 .get_drvinfo = get_drvinfo,
1903 .get_settings = get_settings,
1904 .set_settings = set_settings,
1905 .nway_reset = nway_reset,
1906 .get_link = get_link,
1907 .get_msglevel = get_msglevel,
1908 .set_msglevel = set_msglevel,
1909 };
1910
1911 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1912 {
1913 struct netdev_private *np = netdev_priv(dev);
1914 struct mii_ioctl_data *data = if_mii(rq);
1915 int rc;
1916
1917 if (!netif_running(dev))
1918 return -EINVAL;
1919
1920 spin_lock_irq(&np->lock);
1921 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1922 spin_unlock_irq(&np->lock);
1923
1924 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1925 check_duplex(dev);
1926
1927 return rc;
1928 }
1929
1930 static int netdev_close(struct net_device *dev)
1931 {
1932 struct netdev_private *np = netdev_priv(dev);
1933 void __iomem *ioaddr = np->base;
1934 int i;
1935
1936 netif_stop_queue(dev);
1937
1938 napi_disable(&np->napi);
1939
1940 if (debug > 1) {
1941 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1942 dev->name, (int) readl(ioaddr + IntrStatus));
1943 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1944 dev->name, np->cur_tx, np->dirty_tx,
1945 np->cur_rx, np->dirty_rx);
1946 }
1947
1948 /* Disable interrupts by clearing the interrupt mask. */
1949 writel(0, ioaddr + IntrEnable);
1950
1951 /* Stop the chip's Tx and Rx processes. */
1952 writel(0, ioaddr + GenCtrl);
1953 readl(ioaddr + GenCtrl);
1954
1955 if (debug > 5) {
1956 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1957 (long long) np->tx_ring_dma);
1958 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1959 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1960 i, le32_to_cpu(np->tx_ring[i].status),
1961 (long long) dma_to_cpu(np->tx_ring[i].addr),
1962 le32_to_cpu(np->tx_done_q[i].status));
1963 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1964 (long long) np->rx_ring_dma, np->rx_done_q);
1965 if (np->rx_done_q)
1966 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1967 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1968 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1969 }
1970 }
1971
1972 free_irq(dev->irq, dev);
1973
1974 /* Free all the skbuffs in the Rx queue. */
1975 for (i = 0; i < RX_RING_SIZE; i++) {
1976 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1977 if (np->rx_info[i].skb != NULL) {
1978 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1979 dev_kfree_skb(np->rx_info[i].skb);
1980 }
1981 np->rx_info[i].skb = NULL;
1982 np->rx_info[i].mapping = 0;
1983 }
1984 for (i = 0; i < TX_RING_SIZE; i++) {
1985 struct sk_buff *skb = np->tx_info[i].skb;
1986 if (skb == NULL)
1987 continue;
1988 pci_unmap_single(np->pci_dev,
1989 np->tx_info[i].mapping,
1990 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1991 np->tx_info[i].mapping = 0;
1992 dev_kfree_skb(skb);
1993 np->tx_info[i].skb = NULL;
1994 }
1995
1996 return 0;
1997 }
1998
1999 #ifdef CONFIG_PM
2000 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
2001 {
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003
2004 if (netif_running(dev)) {
2005 netif_device_detach(dev);
2006 netdev_close(dev);
2007 }
2008
2009 pci_save_state(pdev);
2010 pci_set_power_state(pdev, pci_choose_state(pdev,state));
2011
2012 return 0;
2013 }
2014
2015 static int starfire_resume(struct pci_dev *pdev)
2016 {
2017 struct net_device *dev = pci_get_drvdata(pdev);
2018
2019 pci_set_power_state(pdev, PCI_D0);
2020 pci_restore_state(pdev);
2021
2022 if (netif_running(dev)) {
2023 netdev_open(dev);
2024 netif_device_attach(dev);
2025 }
2026
2027 return 0;
2028 }
2029 #endif /* CONFIG_PM */
2030
2031
2032 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2033 {
2034 struct net_device *dev = pci_get_drvdata(pdev);
2035 struct netdev_private *np = netdev_priv(dev);
2036
2037 BUG_ON(!dev);
2038
2039 unregister_netdev(dev);
2040
2041 if (np->queue_mem)
2042 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2043
2044
2045 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2046 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2047 pci_disable_device(pdev);
2048
2049 iounmap(np->base);
2050 pci_release_regions(pdev);
2051
2052 pci_set_drvdata(pdev, NULL);
2053 free_netdev(dev); /* Will also free np!! */
2054 }
2055
2056
2057 static struct pci_driver starfire_driver = {
2058 .name = DRV_NAME,
2059 .probe = starfire_init_one,
2060 .remove = __devexit_p(starfire_remove_one),
2061 #ifdef CONFIG_PM
2062 .suspend = starfire_suspend,
2063 .resume = starfire_resume,
2064 #endif /* CONFIG_PM */
2065 .id_table = starfire_pci_tbl,
2066 };
2067
2068
2069 static int __init starfire_init (void)
2070 {
2071 /* when a module, this is printed whether or not devices are found in probe */
2072 #ifdef MODULE
2073 printk(version);
2074
2075 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2076 #endif
2077
2078 BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(netdrv_addr_t));
2079
2080 return pci_register_driver(&starfire_driver);
2081 }
2082
2083
2084 static void __exit starfire_cleanup (void)
2085 {
2086 pci_unregister_driver (&starfire_driver);
2087 }
2088
2089
2090 module_init(starfire_init);
2091 module_exit(starfire_cleanup);
2092
2093
2094 /*
2095 * Local variables:
2096 * c-basic-offset: 8
2097 * tab-width: 8
2098 * End:
2099 */