2 * Definitions for the new Marvell Yukon 2 driver.
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
9 /* PCI config registers */
13 PCI_DEV_STATUS
= 0x7c,
23 PCI_Y2_PIG_ENA
= 1<<31, /* Enable Plug-in-Go (YUKON-2) */
24 PCI_Y2_DLL_DIS
= 1<<30, /* Disable PCI DLL (YUKON-2) */
25 PCI_SW_PWR_ON_RST
= 1<<30, /* SW Power on Reset (Yukon-EX) */
26 PCI_Y2_PHY2_COMA
= 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
27 PCI_Y2_PHY1_COMA
= 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
28 PCI_Y2_PHY2_POWD
= 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
29 PCI_Y2_PHY1_POWD
= 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
30 PCI_Y2_PME_LEGACY
= 1<<15, /* PCI Express legacy power management mode */
32 PCI_PHY_LNK_TIM_MSK
= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
33 PCI_ENA_L1_EVENT
= 1<<7, /* Enable PEX L1 Event */
34 PCI_ENA_GPHY_LNK
= 1<<6, /* Enable PEX L1 on GPHY Link down */
35 PCI_FORCE_PEX_L1
= 1<<5, /* Force to PEX L1 */
39 PCI_VPD_WR_THR
= 0xffL
<<24, /* Bit 31..24: VPD Write Threshold */
40 PCI_DEV_SEL
= 0x7fL
<<17, /* Bit 23..17: EEPROM Device Select */
41 PCI_VPD_ROM_SZ
= 7L<<14, /* Bit 16..14: VPD ROM Size */
43 PCI_PATCH_DIR
= 0xfL
<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
44 PCI_EXT_PATCHS
= 0xfL
<<4, /* Bit 7.. 4: Extended Patches 3..0 */
45 PCI_EN_DUMMY_RD
= 1<<3, /* Enable Dummy Read */
46 PCI_REV_DESC
= 1<<2, /* Reverse Desc. Bytes */
48 PCI_USEDATA64
= 1<<0, /* Use 64Bit Data bus ext */
51 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
53 /* (Link Training & Status State Machine) */
54 P_PEX_LTSSM_STAT_MSK
= 0x7fL
<<25, /* Bit 31..25: PEX LTSSM Mask */
55 #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
56 P_PEX_LTSSM_L1_STAT
= 0x34,
57 P_PEX_LTSSM_DET_STAT
= 0x01,
58 P_TIMER_VALUE_MSK
= 0xffL
<<16, /* Bit 23..16: Timer Value Mask */
59 /* (Active State Power Management) */
60 P_FORCE_ASPM_REQUEST
= 1<<15, /* Force ASPM Request (A1 only) */
61 P_ASPM_GPHY_LINK_DOWN
= 1<<14, /* GPHY Link Down (A1 only) */
62 P_ASPM_INT_FIFO_EMPTY
= 1<<13, /* Internal FIFO Empty (A1 only) */
63 P_ASPM_CLKRUN_REQUEST
= 1<<12, /* CLKRUN Request (A1 only) */
65 P_ASPM_FORCE_CLKREQ_ENA
= 1<<4, /* Force CLKREQ Enable (A1b only) */
66 P_ASPM_CLKREQ_PAD_CTL
= 1<<3, /* CLKREQ PAD Control (A1 only) */
67 P_ASPM_A1_MODE_SELECT
= 1<<2, /* A1 Mode Select (A1 only) */
68 P_CLK_GATE_PEX_UNIT_ENA
= 1<<1, /* Enable Gate PEX Unit Clock */
69 P_CLK_GATE_ROOT_COR_ENA
= 1<<0, /* Enable Gate Root Core Clock */
70 P_ASPM_CONTROL_MSK
= P_FORCE_ASPM_REQUEST
| P_ASPM_GPHY_LINK_DOWN
71 | P_ASPM_CLKRUN_REQUEST
| P_ASPM_INT_FIFO_EMPTY
,
74 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
76 /* Bit 31..27: for A3 & later */
77 P_CTL_DIV_CORE_CLK_ENA
= 1<<31, /* Divide Core Clock Enable */
78 P_CTL_SRESET_VMAIN_AV
= 1<<30, /* Soft Reset for Vmain_av De-Glitch */
79 P_CTL_BYPASS_VMAIN_AV
= 1<<29, /* Bypass En. for Vmain_av De-Glitch */
80 P_CTL_TIM_VMAIN_AV_MSK
= 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
81 /* Bit 26..16: Release Clock on Event */
82 P_REL_PCIE_RST_DE_ASS
= 1<<26, /* PCIe Reset De-Asserted */
83 P_REL_GPHY_REC_PACKET
= 1<<25, /* GPHY Received Packet */
84 P_REL_INT_FIFO_N_EMPTY
= 1<<24, /* Internal FIFO Not Empty */
85 P_REL_MAIN_PWR_AVAIL
= 1<<23, /* Main Power Available */
86 P_REL_CLKRUN_REQ_REL
= 1<<22, /* CLKRUN Request Release */
87 P_REL_PCIE_RESET_ASS
= 1<<21, /* PCIe Reset Asserted */
88 P_REL_PME_ASSERTED
= 1<<20, /* PME Asserted */
89 P_REL_PCIE_EXIT_L1_ST
= 1<<19, /* PCIe Exit L1 State */
90 P_REL_LOADER_NOT_FIN
= 1<<18, /* EPROM Loader Not Finished */
91 P_REL_PCIE_RX_EX_IDLE
= 1<<17, /* PCIe Rx Exit Electrical Idle State */
92 P_REL_GPHY_LINK_UP
= 1<<16, /* GPHY Link Up */
94 /* Bit 10.. 0: Mask for Gate Clock */
95 P_GAT_PCIE_RST_ASSERTED
= 1<<10,/* PCIe Reset Asserted */
96 P_GAT_GPHY_N_REC_PACKET
= 1<<9, /* GPHY Not Received Packet */
97 P_GAT_INT_FIFO_EMPTY
= 1<<8, /* Internal FIFO Empty */
98 P_GAT_MAIN_PWR_N_AVAIL
= 1<<7, /* Main Power Not Available */
99 P_GAT_CLKRUN_REQ_REL
= 1<<6, /* CLKRUN Not Requested */
100 P_GAT_PCIE_RESET_ASS
= 1<<5, /* PCIe Reset Asserted */
101 P_GAT_PME_DE_ASSERTED
= 1<<4, /* PME De-Asserted */
102 P_GAT_PCIE_ENTER_L1_ST
= 1<<3, /* PCIe Enter L1 State */
103 P_GAT_LOADER_FINISHED
= 1<<2, /* EPROM Loader Finished */
104 P_GAT_PCIE_RX_EL_IDLE
= 1<<1, /* PCIe Rx Electrical Idle State */
105 P_GAT_GPHY_LINK_DOWN
= 1<<0, /* GPHY Link Down */
107 PCIE_OUR5_EVENT_CLK_D3_SET
= P_REL_GPHY_REC_PACKET
|
108 P_REL_INT_FIFO_N_EMPTY
|
109 P_REL_PCIE_EXIT_L1_ST
|
110 P_REL_PCIE_RX_EX_IDLE
|
111 P_GAT_GPHY_N_REC_PACKET
|
112 P_GAT_INT_FIFO_EMPTY
|
113 P_GAT_PCIE_ENTER_L1_ST
|
114 P_GAT_PCIE_RX_EL_IDLE
,
117 #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
119 P_CF1_DIS_REL_EVT_RST
= 1<<24, /* Dis. Rel. Event during PCIE reset */
120 /* Bit 23..21: Release Clock on Event */
121 P_CF1_REL_LDR_NOT_FIN
= 1<<23, /* EEPROM Loader Not Finished */
122 P_CF1_REL_VMAIN_AVLBL
= 1<<22, /* Vmain available */
123 P_CF1_REL_PCIE_RESET
= 1<<21, /* PCI-E reset */
124 /* Bit 20..18: Gate Clock on Event */
125 P_CF1_GAT_LDR_NOT_FIN
= 1<<20, /* EEPROM Loader Finished */
126 P_CF1_GAT_PCIE_RX_IDLE
= 1<<19, /* PCI-E Rx Electrical idle */
127 P_CF1_GAT_PCIE_RESET
= 1<<18, /* PCI-E Reset */
128 P_CF1_PRST_PHY_CLKREQ
= 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
129 P_CF1_PCIE_RST_CLKREQ
= 1<<16, /* Enable PCI-E rst generate CLKREQ */
131 P_CF1_ENA_CFG_LDR_DONE
= 1<<8, /* Enable core level Config loader done */
133 P_CF1_ENA_TXBMU_RD_IDLE
= 1<<1, /* Enable TX BMU Read IDLE for ASPM */
134 P_CF1_ENA_TXBMU_WR_IDLE
= 1<<0, /* Enable TX BMU Write IDLE for ASPM */
136 PCIE_CFG1_EVENT_CLK_D3_SET
= P_CF1_DIS_REL_EVT_RST
|
137 P_CF1_REL_LDR_NOT_FIN
|
138 P_CF1_REL_VMAIN_AVLBL
|
139 P_CF1_REL_PCIE_RESET
|
140 P_CF1_GAT_LDR_NOT_FIN
|
141 P_CF1_GAT_PCIE_RESET
|
142 P_CF1_PRST_PHY_CLKREQ
|
143 P_CF1_ENA_CFG_LDR_DONE
|
144 P_CF1_ENA_TXBMU_RD_IDLE
|
145 P_CF1_ENA_TXBMU_WR_IDLE
,
149 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
150 PCI_STATUS_SIG_SYSTEM_ERROR | \
151 PCI_STATUS_REC_MASTER_ABORT | \
152 PCI_STATUS_REC_TARGET_ABORT | \
159 B0_POWER_CTRL
= 0x0007,
162 B0_HWE_ISRC
= 0x0010,
163 B0_HWE_IMSK
= 0x0014,
165 /* Special ISR registers (Yukon-2 only) */
166 B0_Y2_SP_ISRC2
= 0x001c,
167 B0_Y2_SP_ISRC3
= 0x0020,
168 B0_Y2_SP_EISR
= 0x0024,
169 B0_Y2_SP_LISR
= 0x0028,
170 B0_Y2_SP_ICR
= 0x002c,
175 B2_CONN_TYP
= 0x0118,
181 B2_Y2_CLK_GATE
= 0x011d,
182 B2_Y2_HW_RES
= 0x011e,
184 B2_Y2_CLK_CTRL
= 0x0120,
191 B2_TST_CTRL1
= 0x0158,
192 B2_TST_CTRL2
= 0x0159,
195 B2_I2C_CTRL
= 0x0160,
196 B2_I2C_DATA
= 0x0164,
200 B3_RAM_ADDR
= 0x0180,
201 B3_RAM_DATA_LO
= 0x0184,
202 B3_RAM_DATA_HI
= 0x0188,
204 /* RAM Interface Registers */
205 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
207 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
208 * not usable in SW. Please notice these are NOT real timeouts, these are
209 * the number of qWords transferred continuously.
211 #define RAM_BUFFER(port, reg) (reg | (port <<6))
213 B3_RI_WTO_R1
= 0x0190,
214 B3_RI_WTO_XA1
= 0x0191,
215 B3_RI_WTO_XS1
= 0x0192,
216 B3_RI_RTO_R1
= 0x0193,
217 B3_RI_RTO_XA1
= 0x0194,
218 B3_RI_RTO_XS1
= 0x0195,
219 B3_RI_WTO_R2
= 0x0196,
220 B3_RI_WTO_XA2
= 0x0197,
221 B3_RI_WTO_XS2
= 0x0198,
222 B3_RI_RTO_R2
= 0x0199,
223 B3_RI_RTO_XA2
= 0x019a,
224 B3_RI_RTO_XS2
= 0x019b,
225 B3_RI_TO_VAL
= 0x019c,
228 B3_MA_TOINI_RX1
= 0x01b0,
229 B3_MA_TOINI_RX2
= 0x01b1,
230 B3_MA_TOINI_TX1
= 0x01b2,
231 B3_MA_TOINI_TX2
= 0x01b3,
232 B3_MA_TOVAL_RX1
= 0x01b4,
233 B3_MA_TOVAL_RX2
= 0x01b5,
234 B3_MA_TOVAL_TX1
= 0x01b6,
235 B3_MA_TOVAL_TX2
= 0x01b7,
236 B3_MA_TO_CTRL
= 0x01b8,
237 B3_MA_TO_TEST
= 0x01ba,
238 B3_MA_RCINI_RX1
= 0x01c0,
239 B3_MA_RCINI_RX2
= 0x01c1,
240 B3_MA_RCINI_TX1
= 0x01c2,
241 B3_MA_RCINI_TX2
= 0x01c3,
242 B3_MA_RCVAL_RX1
= 0x01c4,
243 B3_MA_RCVAL_RX2
= 0x01c5,
244 B3_MA_RCVAL_TX1
= 0x01c6,
245 B3_MA_RCVAL_TX2
= 0x01c7,
246 B3_MA_RC_CTRL
= 0x01c8,
247 B3_MA_RC_TEST
= 0x01ca,
248 B3_PA_TOINI_RX1
= 0x01d0,
249 B3_PA_TOINI_RX2
= 0x01d4,
250 B3_PA_TOINI_TX1
= 0x01d8,
251 B3_PA_TOINI_TX2
= 0x01dc,
252 B3_PA_TOVAL_RX1
= 0x01e0,
253 B3_PA_TOVAL_RX2
= 0x01e4,
254 B3_PA_TOVAL_TX1
= 0x01e8,
255 B3_PA_TOVAL_TX2
= 0x01ec,
259 Y2_CFG_SPC
= 0x1c00, /* PCI config space region */
260 Y2_CFG_AER
= 0x1d00, /* PCI Advanced Error Report region */
263 /* B0_CTST 16 bit Control/Status register */
265 Y2_VMAIN_AVAIL
= 1<<17,/* VMAIN available (YUKON-2 only) */
266 Y2_VAUX_AVAIL
= 1<<16,/* VAUX available (YUKON-2 only) */
267 Y2_HW_WOL_ON
= 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
268 Y2_HW_WOL_OFF
= 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
269 Y2_ASF_ENABLE
= 1<<13,/* ASF Unit Enable (YUKON-2 only) */
270 Y2_ASF_DISABLE
= 1<<12,/* ASF Unit Disable (YUKON-2 only) */
271 Y2_CLK_RUN_ENA
= 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
272 Y2_CLK_RUN_DIS
= 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
273 Y2_LED_STAT_ON
= 1<<9, /* Status LED On (YUKON-2 only) */
274 Y2_LED_STAT_OFF
= 1<<8, /* Status LED Off (YUKON-2 only) */
276 CS_ST_SW_IRQ
= 1<<7, /* Set IRQ SW Request */
277 CS_CL_SW_IRQ
= 1<<6, /* Clear IRQ SW Request */
278 CS_STOP_DONE
= 1<<5, /* Stop Master is finished */
279 CS_STOP_MAST
= 1<<4, /* Command Bit to stop the master */
280 CS_MRST_CLR
= 1<<3, /* Clear Master reset */
281 CS_MRST_SET
= 1<<2, /* Set Master reset */
282 CS_RST_CLR
= 1<<1, /* Clear Software reset */
283 CS_RST_SET
= 1, /* Set Software reset */
286 /* B0_LED 8 Bit LED register */
288 /* Bit 7.. 2: reserved */
289 LED_STAT_ON
= 1<<1, /* Status LED on */
290 LED_STAT_OFF
= 1, /* Status LED off */
293 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
295 PC_VAUX_ENA
= 1<<7, /* Switch VAUX Enable */
296 PC_VAUX_DIS
= 1<<6, /* Switch VAUX Disable */
297 PC_VCC_ENA
= 1<<5, /* Switch VCC Enable */
298 PC_VCC_DIS
= 1<<4, /* Switch VCC Disable */
299 PC_VAUX_ON
= 1<<3, /* Switch VAUX On */
300 PC_VAUX_OFF
= 1<<2, /* Switch VAUX Off */
301 PC_VCC_ON
= 1<<1, /* Switch VCC On */
302 PC_VCC_OFF
= 1<<0, /* Switch VCC Off */
305 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
307 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
308 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
309 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
310 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
312 Y2_IS_HW_ERR
= 1<<31, /* Interrupt HW Error */
313 Y2_IS_STAT_BMU
= 1<<30, /* Status BMU Interrupt */
314 Y2_IS_ASF
= 1<<29, /* ASF subsystem Interrupt */
316 Y2_IS_POLL_CHK
= 1<<27, /* Check IRQ from polling unit */
317 Y2_IS_TWSI_RDY
= 1<<26, /* IRQ on end of TWSI Tx */
318 Y2_IS_IRQ_SW
= 1<<25, /* SW forced IRQ */
319 Y2_IS_TIMINT
= 1<<24, /* IRQ from Timer */
321 Y2_IS_IRQ_PHY2
= 1<<12, /* Interrupt from PHY 2 */
322 Y2_IS_IRQ_MAC2
= 1<<11, /* Interrupt from MAC 2 */
323 Y2_IS_CHK_RX2
= 1<<10, /* Descriptor error Rx 2 */
324 Y2_IS_CHK_TXS2
= 1<<9, /* Descriptor error TXS 2 */
325 Y2_IS_CHK_TXA2
= 1<<8, /* Descriptor error TXA 2 */
327 Y2_IS_IRQ_PHY1
= 1<<4, /* Interrupt from PHY 1 */
328 Y2_IS_IRQ_MAC1
= 1<<3, /* Interrupt from MAC 1 */
329 Y2_IS_CHK_RX1
= 1<<2, /* Descriptor error Rx 1 */
330 Y2_IS_CHK_TXS1
= 1<<1, /* Descriptor error TXS 1 */
331 Y2_IS_CHK_TXA1
= 1<<0, /* Descriptor error TXA 1 */
333 Y2_IS_BASE
= Y2_IS_HW_ERR
| Y2_IS_STAT_BMU
,
334 Y2_IS_PORT_1
= Y2_IS_IRQ_PHY1
| Y2_IS_IRQ_MAC1
335 | Y2_IS_CHK_TXA1
| Y2_IS_CHK_RX1
,
336 Y2_IS_PORT_2
= Y2_IS_IRQ_PHY2
| Y2_IS_IRQ_MAC2
337 | Y2_IS_CHK_TXA2
| Y2_IS_CHK_RX2
,
338 Y2_IS_ERROR
= Y2_IS_HW_ERR
|
339 Y2_IS_IRQ_MAC1
| Y2_IS_CHK_TXA1
| Y2_IS_CHK_RX1
|
340 Y2_IS_IRQ_MAC2
| Y2_IS_CHK_TXA2
| Y2_IS_CHK_RX2
,
343 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
345 IS_ERR_MSK
= 0x00003fff,/* All Error bits */
347 IS_IRQ_TIST_OV
= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
348 IS_IRQ_SENSOR
= 1<<12, /* IRQ from Sensor (YUKON only) */
349 IS_IRQ_MST_ERR
= 1<<11, /* IRQ master error detected */
350 IS_IRQ_STAT
= 1<<10, /* IRQ status exception */
351 IS_NO_STAT_M1
= 1<<9, /* No Rx Status from MAC 1 */
352 IS_NO_STAT_M2
= 1<<8, /* No Rx Status from MAC 2 */
353 IS_NO_TIST_M1
= 1<<7, /* No Time Stamp from MAC 1 */
354 IS_NO_TIST_M2
= 1<<6, /* No Time Stamp from MAC 2 */
355 IS_RAM_RD_PAR
= 1<<5, /* RAM Read Parity Error */
356 IS_RAM_WR_PAR
= 1<<4, /* RAM Write Parity Error */
357 IS_M1_PAR_ERR
= 1<<3, /* MAC 1 Parity Error */
358 IS_M2_PAR_ERR
= 1<<2, /* MAC 2 Parity Error */
359 IS_R1_PAR_ERR
= 1<<1, /* Queue R1 Parity Error */
360 IS_R2_PAR_ERR
= 1<<0, /* Queue R2 Parity Error */
363 /* Hardware error interrupt mask for Yukon 2 */
365 Y2_IS_TIST_OV
= 1<<29,/* Time Stamp Timer overflow interrupt */
366 Y2_IS_SENSOR
= 1<<28, /* Sensor interrupt */
367 Y2_IS_MST_ERR
= 1<<27, /* Master error interrupt */
368 Y2_IS_IRQ_STAT
= 1<<26, /* Status exception interrupt */
369 Y2_IS_PCI_EXP
= 1<<25, /* PCI-Express interrupt */
370 Y2_IS_PCI_NEXP
= 1<<24, /* PCI-Express error similar to PCI error */
372 Y2_IS_PAR_RD2
= 1<<13, /* Read RAM parity error interrupt */
373 Y2_IS_PAR_WR2
= 1<<12, /* Write RAM parity error interrupt */
374 Y2_IS_PAR_MAC2
= 1<<11, /* MAC hardware fault interrupt */
375 Y2_IS_PAR_RX2
= 1<<10, /* Parity Error Rx Queue 2 */
376 Y2_IS_TCP_TXS2
= 1<<9, /* TCP length mismatch sync Tx queue IRQ */
377 Y2_IS_TCP_TXA2
= 1<<8, /* TCP length mismatch async Tx queue IRQ */
379 Y2_IS_PAR_RD1
= 1<<5, /* Read RAM parity error interrupt */
380 Y2_IS_PAR_WR1
= 1<<4, /* Write RAM parity error interrupt */
381 Y2_IS_PAR_MAC1
= 1<<3, /* MAC hardware fault interrupt */
382 Y2_IS_PAR_RX1
= 1<<2, /* Parity Error Rx Queue 1 */
383 Y2_IS_TCP_TXS1
= 1<<1, /* TCP length mismatch sync Tx queue IRQ */
384 Y2_IS_TCP_TXA1
= 1<<0, /* TCP length mismatch async Tx queue IRQ */
386 Y2_HWE_L1_MASK
= Y2_IS_PAR_RD1
| Y2_IS_PAR_WR1
| Y2_IS_PAR_MAC1
|
387 Y2_IS_PAR_RX1
| Y2_IS_TCP_TXS1
| Y2_IS_TCP_TXA1
,
388 Y2_HWE_L2_MASK
= Y2_IS_PAR_RD2
| Y2_IS_PAR_WR2
| Y2_IS_PAR_MAC2
|
389 Y2_IS_PAR_RX2
| Y2_IS_TCP_TXS2
| Y2_IS_TCP_TXA2
,
391 Y2_HWE_ALL_MASK
= Y2_IS_TIST_OV
| Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
|
392 Y2_HWE_L1_MASK
| Y2_HWE_L2_MASK
,
395 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
401 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
403 TST_FRC_DPERR_MR
= 1<<7, /* force DATAPERR on MST RD */
404 TST_FRC_DPERR_MW
= 1<<6, /* force DATAPERR on MST WR */
405 TST_FRC_DPERR_TR
= 1<<5, /* force DATAPERR on TRG RD */
406 TST_FRC_DPERR_TW
= 1<<4, /* force DATAPERR on TRG WR */
407 TST_FRC_APERR_M
= 1<<3, /* force ADDRPERR on MST */
408 TST_FRC_APERR_T
= 1<<2, /* force ADDRPERR on TRG */
409 TST_CFG_WRITE_ON
= 1<<1, /* Enable Config Reg WR */
410 TST_CFG_WRITE_OFF
= 1<<0, /* Disable Config Reg WR */
415 GLB_GPIO_CLK_DEB_ENA
= 1<<31, /* Clock Debug Enable */
416 GLB_GPIO_CLK_DBG_MSK
= 0xf<<26, /* Clock Debug */
418 GLB_GPIO_INT_RST_D3_DIS
= 1<<15, /* Disable Internal Reset After D3 to D0 */
419 GLB_GPIO_LED_PAD_SPEED_UP
= 1<<14, /* LED PAD Speed Up */
420 GLB_GPIO_STAT_RACE_DIS
= 1<<13, /* Status Race Disable */
421 GLB_GPIO_TEST_SEL_MSK
= 3<<11, /* Testmode Select */
422 GLB_GPIO_TEST_SEL_BASE
= 1<<11,
423 GLB_GPIO_RAND_ENA
= 1<<10, /* Random Enable */
424 GLB_GPIO_RAND_BIT_1
= 1<<9, /* Random Bit 1 */
427 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
429 CFG_CHIP_R_MSK
= 0xf<<4, /* Bit 7.. 4: Chip Revision */
430 /* Bit 3.. 2: reserved */
431 CFG_DIS_M2_CLK
= 1<<1, /* Disable Clock for 2nd MAC */
432 CFG_SNG_MAC
= 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
435 /* B2_CHIP_ID 8 bit Chip Identification Number */
437 CHIP_ID_YUKON_XL
= 0xb3, /* YUKON-2 XL */
438 CHIP_ID_YUKON_EC_U
= 0xb4, /* YUKON-2 EC Ultra */
439 CHIP_ID_YUKON_EX
= 0xb5, /* YUKON-2 Extreme */
440 CHIP_ID_YUKON_EC
= 0xb6, /* YUKON-2 EC */
441 CHIP_ID_YUKON_FE
= 0xb7, /* YUKON-2 FE */
442 CHIP_ID_YUKON_FE_P
= 0xb8, /* YUKON-2 FE+ */
443 CHIP_ID_YUKON_SUPR
= 0xb9, /* YUKON-2 Supreme */
444 CHIP_ID_YUKON_UL_2
= 0xba, /* YUKON-2 Ultra 2 */
447 CHIP_REV_YU_EC_A1
= 0, /* Chip Rev. for Yukon-EC A1/A0 */
448 CHIP_REV_YU_EC_A2
= 1, /* Chip Rev. for Yukon-EC A2 */
449 CHIP_REV_YU_EC_A3
= 2, /* Chip Rev. for Yukon-EC A3 */
451 enum yukon_ec_u_rev
{
452 CHIP_REV_YU_EC_U_A0
= 1,
453 CHIP_REV_YU_EC_U_A1
= 2,
454 CHIP_REV_YU_EC_U_B0
= 3,
457 CHIP_REV_YU_FE_A1
= 1,
458 CHIP_REV_YU_FE_A2
= 2,
460 enum yukon_fe_p_rev
{
461 CHIP_REV_YU_FE2_A0
= 0,
464 CHIP_REV_YU_EX_A0
= 1,
465 CHIP_REV_YU_EX_B0
= 2,
467 enum yukon_supr_rev
{
468 CHIP_REV_YU_SU_A0
= 0,
472 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
474 Y2_STATUS_LNK2_INAC
= 1<<7, /* Status Link 2 inactive (0 = active) */
475 Y2_CLK_GAT_LNK2_DIS
= 1<<6, /* Disable clock gating Link 2 */
476 Y2_COR_CLK_LNK2_DIS
= 1<<5, /* Disable Core clock Link 2 */
477 Y2_PCI_CLK_LNK2_DIS
= 1<<4, /* Disable PCI clock Link 2 */
478 Y2_STATUS_LNK1_INAC
= 1<<3, /* Status Link 1 inactive (0 = active) */
479 Y2_CLK_GAT_LNK1_DIS
= 1<<2, /* Disable clock gating Link 1 */
480 Y2_COR_CLK_LNK1_DIS
= 1<<1, /* Disable Core clock Link 1 */
481 Y2_PCI_CLK_LNK1_DIS
= 1<<0, /* Disable PCI clock Link 1 */
484 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
486 CFG_LED_MODE_MSK
= 7<<2, /* Bit 4.. 2: LED Mode Mask */
487 CFG_LINK_2_AVAIL
= 1<<1, /* Link 2 available */
488 CFG_LINK_1_AVAIL
= 1<<0, /* Link 1 available */
490 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
491 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
494 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
496 Y2_CLK_DIV_VAL_MSK
= 0xff<<16,/* Bit 23..16: Clock Divisor Value */
497 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
498 Y2_CLK_DIV_VAL2_MSK
= 7<<21, /* Bit 23..21: Clock Divisor Value */
499 Y2_CLK_SELECT2_MSK
= 0x1f<<16,/* Bit 20..16: Clock Select */
500 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
501 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
502 Y2_CLK_DIV_ENA
= 1<<1, /* Enable Core Clock Division */
503 Y2_CLK_DIV_DIS
= 1<<0, /* Disable Core Clock Division */
506 /* B2_TI_CTRL 8 bit Timer control */
507 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
509 TIM_START
= 1<<2, /* Start Timer */
510 TIM_STOP
= 1<<1, /* Stop Timer */
511 TIM_CLR_IRQ
= 1<<0, /* Clear Timer IRQ (!IRQM) */
514 /* B2_TI_TEST 8 Bit Timer Test */
515 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
516 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
518 TIM_T_ON
= 1<<2, /* Test mode on */
519 TIM_T_OFF
= 1<<1, /* Test mode off */
520 TIM_T_STEP
= 1<<0, /* Test step */
523 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
524 /* Bit 31..19: reserved */
525 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
526 /* RAM Interface Registers */
528 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
530 RI_CLR_RD_PERR
= 1<<9, /* Clear IRQ RAM Read Parity Err */
531 RI_CLR_WR_PERR
= 1<<8, /* Clear IRQ RAM Write Parity Err*/
533 RI_RST_CLR
= 1<<1, /* Clear RAM Interface Reset */
534 RI_RST_SET
= 1<<0, /* Set RAM Interface Reset */
537 #define SK_RI_TO_53 36 /* RAM interface timeout */
540 /* Port related registers FIFO, and Arbiter */
541 #define SK_REG(port,reg) (((port)<<7)+(reg))
543 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
544 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
545 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
546 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
547 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
549 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
551 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
553 TXA_ENA_FSYNC
= 1<<7, /* Enable force of sync Tx queue */
554 TXA_DIS_FSYNC
= 1<<6, /* Disable force of sync Tx queue */
555 TXA_ENA_ALLOC
= 1<<5, /* Enable alloc of free bandwidth */
556 TXA_DIS_ALLOC
= 1<<4, /* Disable alloc of free bandwidth */
557 TXA_START_RC
= 1<<3, /* Start sync Rate Control */
558 TXA_STOP_RC
= 1<<2, /* Stop sync Rate Control */
559 TXA_ENA_ARB
= 1<<1, /* Enable Tx Arbiter */
560 TXA_DIS_ARB
= 1<<0, /* Disable Tx Arbiter */
566 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
568 TXA_ITI_INI
= 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
569 TXA_ITI_VAL
= 0x0204,/* 32 bit Tx Arb Interval Timer Value */
570 TXA_LIM_INI
= 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
571 TXA_LIM_VAL
= 0x020c,/* 32 bit Tx Arb Limit Counter Value */
572 TXA_CTRL
= 0x0210,/* 8 bit Tx Arbiter Control Register */
573 TXA_TEST
= 0x0211,/* 8 bit Tx Arbiter Test Register */
574 TXA_STAT
= 0x0212,/* 8 bit Tx Arbiter Status Register */
579 B6_EXT_REG
= 0x0300,/* External registers (GENESIS only) */
580 B7_CFG_SPC
= 0x0380,/* copy of the Configuration register */
581 B8_RQ1_REGS
= 0x0400,/* Receive Queue 1 */
582 B8_RQ2_REGS
= 0x0480,/* Receive Queue 2 */
583 B8_TS1_REGS
= 0x0600,/* Transmit sync queue 1 */
584 B8_TA1_REGS
= 0x0680,/* Transmit async queue 1 */
585 B8_TS2_REGS
= 0x0700,/* Transmit sync queue 2 */
586 B8_TA2_REGS
= 0x0780,/* Transmit sync queue 2 */
587 B16_RAM_REGS
= 0x0800,/* RAM Buffer Registers */
590 /* Queue Register Offsets, use Q_ADDR() to access */
592 B8_Q_REGS
= 0x0400, /* base of Queue registers */
593 Q_D
= 0x00, /* 8*32 bit Current Descriptor */
594 Q_VLAN
= 0x20, /* 16 bit Current VLAN Tag */
595 Q_DONE
= 0x24, /* 16 bit Done Index */
596 Q_AC_L
= 0x28, /* 32 bit Current Address Counter Low dWord */
597 Q_AC_H
= 0x2c, /* 32 bit Current Address Counter High dWord */
598 Q_BC
= 0x30, /* 32 bit Current Byte Counter */
599 Q_CSR
= 0x34, /* 32 bit BMU Control/Status Register */
600 Q_TEST
= 0x38, /* 32 bit Test/Control Register */
603 Q_WM
= 0x40, /* 16 bit FIFO Watermark */
604 Q_AL
= 0x42, /* 8 bit FIFO Alignment */
605 Q_RSP
= 0x44, /* 16 bit FIFO Read Shadow Pointer */
606 Q_RSL
= 0x46, /* 8 bit FIFO Read Shadow Level */
607 Q_RP
= 0x48, /* 8 bit FIFO Read Pointer */
608 Q_RL
= 0x4a, /* 8 bit FIFO Read Level */
609 Q_WP
= 0x4c, /* 8 bit FIFO Write Pointer */
610 Q_WSP
= 0x4d, /* 8 bit FIFO Write Shadow Pointer */
611 Q_WL
= 0x4e, /* 8 bit FIFO Write Level */
612 Q_WSL
= 0x4f, /* 8 bit FIFO Write Shadow Level */
614 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
616 /* Q_TEST 32 bit Test Register */
619 F_TX_CHK_AUTO_OFF
= 1<<31, /* Tx checksum auto calc off (Yukon EX) */
620 F_TX_CHK_AUTO_ON
= 1<<30, /* Tx checksum auto calc off (Yukon EX) */
623 F_M_RX_RAM_DIS
= 1<<24, /* MAC Rx RAM Read Port disable */
625 /* Hardware testbits not used */
628 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
630 Y2_B8_PREF_REGS
= 0x0450,
632 PREF_UNIT_CTRL
= 0x00, /* 32 bit Control register */
633 PREF_UNIT_LAST_IDX
= 0x04, /* 16 bit Last Index */
634 PREF_UNIT_ADDR_LO
= 0x08, /* 32 bit List start addr, low part */
635 PREF_UNIT_ADDR_HI
= 0x0c, /* 32 bit List start addr, high part*/
636 PREF_UNIT_GET_IDX
= 0x10, /* 16 bit Get Index */
637 PREF_UNIT_PUT_IDX
= 0x14, /* 16 bit Put Index */
638 PREF_UNIT_FIFO_WP
= 0x20, /* 8 bit FIFO write pointer */
639 PREF_UNIT_FIFO_RP
= 0x24, /* 8 bit FIFO read pointer */
640 PREF_UNIT_FIFO_WM
= 0x28, /* 8 bit FIFO watermark */
641 PREF_UNIT_FIFO_LEV
= 0x2c, /* 8 bit FIFO level */
643 PREF_UNIT_MASK_IDX
= 0x0fff,
645 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
647 /* RAM Buffer Register Offsets */
650 RB_START
= 0x00,/* 32 bit RAM Buffer Start Address */
651 RB_END
= 0x04,/* 32 bit RAM Buffer End Address */
652 RB_WP
= 0x08,/* 32 bit RAM Buffer Write Pointer */
653 RB_RP
= 0x0c,/* 32 bit RAM Buffer Read Pointer */
654 RB_RX_UTPP
= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
655 RB_RX_LTPP
= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
656 RB_RX_UTHP
= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
657 RB_RX_LTHP
= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
658 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
659 RB_PC
= 0x20,/* 32 bit RAM Buffer Packet Counter */
660 RB_LEV
= 0x24,/* 32 bit RAM Buffer Level Register */
661 RB_CTRL
= 0x28,/* 32 bit RAM Buffer Control Register */
662 RB_TST1
= 0x29,/* 8 bit RAM Buffer Test Register 1 */
663 RB_TST2
= 0x2a,/* 8 bit RAM Buffer Test Register 2 */
666 /* Receive and Transmit Queues */
668 Q_R1
= 0x0000, /* Receive Queue 1 */
669 Q_R2
= 0x0080, /* Receive Queue 2 */
670 Q_XS1
= 0x0200, /* Synchronous Transmit Queue 1 */
671 Q_XA1
= 0x0280, /* Asynchronous Transmit Queue 1 */
672 Q_XS2
= 0x0300, /* Synchronous Transmit Queue 2 */
673 Q_XA2
= 0x0380, /* Asynchronous Transmit Queue 2 */
676 /* Different PHY Types */
681 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
685 LNK_SYNC_INI
= 0x0c30,/* 32 bit Link Sync Cnt Init Value */
686 LNK_SYNC_VAL
= 0x0c34,/* 32 bit Link Sync Cnt Current Value */
687 LNK_SYNC_CTRL
= 0x0c38,/* 8 bit Link Sync Cnt Control Register */
688 LNK_SYNC_TST
= 0x0c39,/* 8 bit Link Sync Cnt Test Register */
690 LNK_LED_REG
= 0x0c3c,/* 8 bit Link LED Register */
692 /* Receive GMAC FIFO (YUKON and Yukon-2) */
694 RX_GMF_EA
= 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
695 RX_GMF_AF_THR
= 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
696 RX_GMF_CTRL_T
= 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
697 RX_GMF_FL_MSK
= 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
698 RX_GMF_FL_THR
= 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
699 RX_GMF_TR_THR
= 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
700 RX_GMF_UP_THR
= 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
701 RX_GMF_LP_THR
= 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
702 RX_GMF_VLAN
= 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
703 RX_GMF_WP
= 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
705 RX_GMF_WLEV
= 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
707 RX_GMF_RP
= 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
709 RX_GMF_RLEV
= 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
713 /* Q_BC 32 bit Current Byte Counter */
715 /* BMU Control Status Registers */
716 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
717 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
718 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
719 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
720 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
721 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
722 /* Q_CSR 32 bit BMU Control/Status Register */
724 /* Rx BMU Control / Status Registers (Yukon-2) */
726 BMU_IDLE
= 1<<31, /* BMU Idle State */
727 BMU_RX_TCP_PKT
= 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
728 BMU_RX_IP_PKT
= 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
730 BMU_ENA_RX_RSS_HASH
= 1<<15, /* Enable Rx RSS Hash */
731 BMU_DIS_RX_RSS_HASH
= 1<<14, /* Disable Rx RSS Hash */
732 BMU_ENA_RX_CHKSUM
= 1<<13, /* Enable Rx TCP/IP Checksum Check */
733 BMU_DIS_RX_CHKSUM
= 1<<12, /* Disable Rx TCP/IP Checksum Check */
734 BMU_CLR_IRQ_PAR
= 1<<11, /* Clear IRQ on Parity errors (Rx) */
735 BMU_CLR_IRQ_TCP
= 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
736 BMU_CLR_IRQ_CHK
= 1<<10, /* Clear IRQ Check */
737 BMU_STOP
= 1<<9, /* Stop Rx/Tx Queue */
738 BMU_START
= 1<<8, /* Start Rx/Tx Queue */
739 BMU_FIFO_OP_ON
= 1<<7, /* FIFO Operational On */
740 BMU_FIFO_OP_OFF
= 1<<6, /* FIFO Operational Off */
741 BMU_FIFO_ENA
= 1<<5, /* Enable FIFO */
742 BMU_FIFO_RST
= 1<<4, /* Reset FIFO */
743 BMU_OP_ON
= 1<<3, /* BMU Operational On */
744 BMU_OP_OFF
= 1<<2, /* BMU Operational Off */
745 BMU_RST_CLR
= 1<<1, /* Clear BMU Reset (Enable) */
746 BMU_RST_SET
= 1<<0, /* Set BMU Reset */
748 BMU_CLR_RESET
= BMU_FIFO_RST
| BMU_OP_OFF
| BMU_RST_CLR
,
749 BMU_OPER_INIT
= BMU_CLR_IRQ_PAR
| BMU_CLR_IRQ_CHK
| BMU_START
|
750 BMU_FIFO_ENA
| BMU_OP_ON
,
752 BMU_WM_DEFAULT
= 0x600,
756 /* Tx BMU Control / Status Registers (Yukon-2) */
757 /* Bit 31: same as for Rx */
759 BMU_TX_IPIDINCR_ON
= 1<<13, /* Enable IP ID Increment */
760 BMU_TX_IPIDINCR_OFF
= 1<<12, /* Disable IP ID Increment */
761 BMU_TX_CLR_IRQ_TCP
= 1<<11, /* Clear IRQ on TCP segment length mismatch */
764 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
765 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
767 PREF_UNIT_OP_ON
= 1<<3, /* prefetch unit operational */
768 PREF_UNIT_OP_OFF
= 1<<2, /* prefetch unit not operational */
769 PREF_UNIT_RST_CLR
= 1<<1, /* Clear Prefetch Unit Reset */
770 PREF_UNIT_RST_SET
= 1<<0, /* Set Prefetch Unit Reset */
773 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
774 /* RB_START 32 bit RAM Buffer Start Address */
775 /* RB_END 32 bit RAM Buffer End Address */
776 /* RB_WP 32 bit RAM Buffer Write Pointer */
777 /* RB_RP 32 bit RAM Buffer Read Pointer */
778 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
779 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
780 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
781 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
782 /* RB_PC 32 bit RAM Buffer Packet Counter */
783 /* RB_LEV 32 bit RAM Buffer Level Register */
785 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
786 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
787 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
789 /* RB_CTRL 8 bit RAM Buffer Control Register */
791 RB_ENA_STFWD
= 1<<5, /* Enable Store & Forward */
792 RB_DIS_STFWD
= 1<<4, /* Disable Store & Forward */
793 RB_ENA_OP_MD
= 1<<3, /* Enable Operation Mode */
794 RB_DIS_OP_MD
= 1<<2, /* Disable Operation Mode */
795 RB_RST_CLR
= 1<<1, /* Clear RAM Buf STM Reset */
796 RB_RST_SET
= 1<<0, /* Set RAM Buf STM Reset */
800 /* Transmit GMAC FIFO (YUKON only) */
802 TX_GMF_EA
= 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
803 TX_GMF_AE_THR
= 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
804 TX_GMF_CTRL_T
= 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
806 TX_GMF_WP
= 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
807 TX_GMF_WSP
= 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
808 TX_GMF_WLEV
= 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
810 TX_GMF_RP
= 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
811 TX_GMF_RSTP
= 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
812 TX_GMF_RLEV
= 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
814 /* Threshold values for Yukon-EC Ultra and Extreme */
815 ECU_AE_THR
= 0x0070, /* Almost Empty Threshold */
816 ECU_TXFF_LEV
= 0x01a0, /* Tx BMU FIFO Level */
817 ECU_JUMBO_WM
= 0x0080, /* Jumbo Mode Watermark */
820 /* Descriptor Poll Timer Registers */
822 B28_DPT_INI
= 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
823 B28_DPT_VAL
= 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
824 B28_DPT_CTRL
= 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
826 B28_DPT_TST
= 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
829 /* Time Stamp Timer Registers (YUKON only) */
831 GMAC_TI_ST_VAL
= 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
832 GMAC_TI_ST_CTRL
= 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
833 GMAC_TI_ST_TST
= 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
836 /* Polling Unit Registers (Yukon-2 only) */
838 POLL_CTRL
= 0x0e20, /* 32 bit Polling Unit Control Reg */
839 POLL_LAST_IDX
= 0x0e24,/* 16 bit Polling Unit List Last Index */
841 POLL_LIST_ADDR_LO
= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
842 POLL_LIST_ADDR_HI
= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
846 SMB_CFG
= 0x0e40, /* 32 bit SMBus Config Register */
847 SMB_CSR
= 0x0e44, /* 32 bit SMBus Control/Status Register */
851 CPU_WDOG
= 0x0e48, /* 32 bit Watchdog Register */
852 CPU_CNTR
= 0x0e4C, /* 32 bit Counter Register */
853 CPU_TIM
= 0x0e50,/* 32 bit Timer Compare Register */
854 CPU_AHB_ADDR
= 0x0e54, /* 32 bit CPU AHB Debug Register */
855 CPU_AHB_WDATA
= 0x0e58, /* 32 bit CPU AHB Debug Register */
856 CPU_AHB_RDATA
= 0x0e5C, /* 32 bit CPU AHB Debug Register */
857 HCU_MAP_BASE
= 0x0e60, /* 32 bit Reset Mapping Base */
858 CPU_AHB_CTRL
= 0x0e64, /* 32 bit CPU AHB Debug Register */
859 HCU_CCSR
= 0x0e68, /* 32 bit CPU Control and Status Register */
860 HCU_HCSR
= 0x0e6C, /* 32 bit Host Control and Status Register */
863 /* ASF Subsystem Registers (Yukon-2 only) */
865 B28_Y2_SMB_CONFIG
= 0x0e40,/* 32 bit ASF SMBus Config Register */
866 B28_Y2_SMB_CSD_REG
= 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
867 B28_Y2_ASF_IRQ_V_BASE
=0x0e60,/* 32 bit ASF IRQ Vector Base */
869 B28_Y2_ASF_STAT_CMD
= 0x0e68,/* 32 bit ASF Status and Command Reg */
870 B28_Y2_ASF_HOST_COM
= 0x0e6c,/* 32 bit ASF Host Communication Reg */
871 B28_Y2_DATA_REG_1
= 0x0e70,/* 32 bit ASF/Host Data Register 1 */
872 B28_Y2_DATA_REG_2
= 0x0e74,/* 32 bit ASF/Host Data Register 2 */
873 B28_Y2_DATA_REG_3
= 0x0e78,/* 32 bit ASF/Host Data Register 3 */
874 B28_Y2_DATA_REG_4
= 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
877 /* Status BMU Registers (Yukon-2 only)*/
879 STAT_CTRL
= 0x0e80,/* 32 bit Status BMU Control Reg */
880 STAT_LAST_IDX
= 0x0e84,/* 16 bit Status BMU Last Index */
882 STAT_LIST_ADDR_LO
= 0x0e88,/* 32 bit Status List Start Addr (low) */
883 STAT_LIST_ADDR_HI
= 0x0e8c,/* 32 bit Status List Start Addr (high) */
884 STAT_TXA1_RIDX
= 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
885 STAT_TXS1_RIDX
= 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
886 STAT_TXA2_RIDX
= 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
887 STAT_TXS2_RIDX
= 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
888 STAT_TX_IDX_TH
= 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
889 STAT_PUT_IDX
= 0x0e9c,/* 16 bit Status Put Index Reg */
891 /* FIFO Control/Status Registers (Yukon-2 only)*/
892 STAT_FIFO_WP
= 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
893 STAT_FIFO_RP
= 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
894 STAT_FIFO_RSP
= 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
895 STAT_FIFO_LEVEL
= 0x0ea8,/* 8 bit Status FIFO Level Reg */
896 STAT_FIFO_SHLVL
= 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
897 STAT_FIFO_WM
= 0x0eac,/* 8 bit Status FIFO Watermark Reg */
898 STAT_FIFO_ISR_WM
= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
900 /* Level and ISR Timer Registers (Yukon-2 only)*/
901 STAT_LEV_TIMER_INI
= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
902 STAT_LEV_TIMER_CNT
= 0x0eb4,/* 32 bit Level Timer Counter Reg */
903 STAT_LEV_TIMER_CTRL
= 0x0eb8,/* 8 bit Level Timer Control Reg */
904 STAT_LEV_TIMER_TEST
= 0x0eb9,/* 8 bit Level Timer Test Reg */
905 STAT_TX_TIMER_INI
= 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
906 STAT_TX_TIMER_CNT
= 0x0ec4,/* 32 bit Tx Timer Counter Reg */
907 STAT_TX_TIMER_CTRL
= 0x0ec8,/* 8 bit Tx Timer Control Reg */
908 STAT_TX_TIMER_TEST
= 0x0ec9,/* 8 bit Tx Timer Test Reg */
909 STAT_ISR_TIMER_INI
= 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
910 STAT_ISR_TIMER_CNT
= 0x0ed4,/* 32 bit ISR Timer Counter Reg */
911 STAT_ISR_TIMER_CTRL
= 0x0ed8,/* 8 bit ISR Timer Control Reg */
912 STAT_ISR_TIMER_TEST
= 0x0ed9,/* 8 bit ISR Timer Test Reg */
918 LINKLED_LINKSYNC_OFF
= 0x04,
919 LINKLED_LINKSYNC_ON
= 0x08,
920 LINKLED_BLINK_OFF
= 0x10,
921 LINKLED_BLINK_ON
= 0x20,
924 /* GMAC and GPHY Control Registers (YUKON only) */
926 GMAC_CTRL
= 0x0f00,/* 32 bit GMAC Control Reg */
927 GPHY_CTRL
= 0x0f04,/* 32 bit GPHY Control Reg */
928 GMAC_IRQ_SRC
= 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
929 GMAC_IRQ_MSK
= 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
930 GMAC_LINK_CTRL
= 0x0f10,/* 16 bit Link Control Reg */
932 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
933 WOL_CTRL_STAT
= 0x0f20,/* 16 bit WOL Control/Status Reg */
934 WOL_MATCH_CTL
= 0x0f22,/* 8 bit WOL Match Control Reg */
935 WOL_MATCH_RES
= 0x0f23,/* 8 bit WOL Match Result Reg */
936 WOL_MAC_ADDR
= 0x0f24,/* 32 bit WOL MAC Address */
937 WOL_PATT_RPTR
= 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
939 /* WOL Pattern Length Registers (YUKON only) */
940 WOL_PATT_LEN_LO
= 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
941 WOL_PATT_LEN_HI
= 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
943 /* WOL Pattern Counter Registers (YUKON only) */
944 WOL_PATT_CNT_0
= 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
945 WOL_PATT_CNT_4
= 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
947 #define WOL_REGS(port, x) (x + (port)*0x80)
950 WOL_PATT_RAM_1
= 0x1000,/* WOL Pattern RAM Link 1 */
951 WOL_PATT_RAM_2
= 0x1400,/* WOL Pattern RAM Link 2 */
953 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
956 BASE_GMAC_1
= 0x2800,/* GMAC 1 registers */
957 BASE_GMAC_2
= 0x3800,/* GMAC 2 registers */
961 * Marvel-PHY Registers, indirect addressed over GMAC
964 PHY_MARV_CTRL
= 0x00,/* 16 bit r/w PHY Control Register */
965 PHY_MARV_STAT
= 0x01,/* 16 bit r/o PHY Status Register */
966 PHY_MARV_ID0
= 0x02,/* 16 bit r/o PHY ID0 Register */
967 PHY_MARV_ID1
= 0x03,/* 16 bit r/o PHY ID1 Register */
968 PHY_MARV_AUNE_ADV
= 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
969 PHY_MARV_AUNE_LP
= 0x05,/* 16 bit r/o Link Part Ability Reg */
970 PHY_MARV_AUNE_EXP
= 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
971 PHY_MARV_NEPG
= 0x07,/* 16 bit r/w Next Page Register */
972 PHY_MARV_NEPG_LP
= 0x08,/* 16 bit r/o Next Page Link Partner */
973 /* Marvel-specific registers */
974 PHY_MARV_1000T_CTRL
= 0x09,/* 16 bit r/w 1000Base-T Control Reg */
975 PHY_MARV_1000T_STAT
= 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
976 PHY_MARV_EXT_STAT
= 0x0f,/* 16 bit r/o Extended Status Reg */
977 PHY_MARV_PHY_CTRL
= 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
978 PHY_MARV_PHY_STAT
= 0x11,/* 16 bit r/o PHY Specific Stat Reg */
979 PHY_MARV_INT_MASK
= 0x12,/* 16 bit r/w Interrupt Mask Reg */
980 PHY_MARV_INT_STAT
= 0x13,/* 16 bit r/o Interrupt Status Reg */
981 PHY_MARV_EXT_CTRL
= 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
982 PHY_MARV_RXE_CNT
= 0x15,/* 16 bit r/w Receive Error Counter */
983 PHY_MARV_EXT_ADR
= 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
984 PHY_MARV_PORT_IRQ
= 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
985 PHY_MARV_LED_CTRL
= 0x18,/* 16 bit r/w LED Control Reg */
986 PHY_MARV_LED_OVER
= 0x19,/* 16 bit r/w Manual LED Override Reg */
987 PHY_MARV_EXT_CTRL_2
= 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
988 PHY_MARV_EXT_P_STAT
= 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
989 PHY_MARV_CABLE_DIAG
= 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
990 PHY_MARV_PAGE_ADDR
= 0x1d,/* 16 bit r/w Extended Page Address Reg */
991 PHY_MARV_PAGE_DATA
= 0x1e,/* 16 bit r/w Extended Page Data Reg */
993 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
994 PHY_MARV_FE_LED_PAR
= 0x16,/* 16 bit r/w LED Parallel Select Reg. */
995 PHY_MARV_FE_LED_SER
= 0x17,/* 16 bit r/w LED Stream Select S. LED */
996 PHY_MARV_FE_VCT_TX
= 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
997 PHY_MARV_FE_VCT_RX
= 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
998 PHY_MARV_FE_SPEC_2
= 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1002 PHY_CT_RESET
= 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1003 PHY_CT_LOOP
= 1<<14, /* Bit 14: enable Loopback over PHY */
1004 PHY_CT_SPS_LSB
= 1<<13, /* Bit 13: Speed select, lower bit */
1005 PHY_CT_ANE
= 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1006 PHY_CT_PDOWN
= 1<<11, /* Bit 11: Power Down Mode */
1007 PHY_CT_ISOL
= 1<<10, /* Bit 10: Isolate Mode */
1008 PHY_CT_RE_CFG
= 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1009 PHY_CT_DUP_MD
= 1<<8, /* Bit 8: Duplex Mode */
1010 PHY_CT_COL_TST
= 1<<7, /* Bit 7: Collision Test enabled */
1011 PHY_CT_SPS_MSB
= 1<<6, /* Bit 6: Speed select, upper bit */
1015 PHY_CT_SP1000
= PHY_CT_SPS_MSB
, /* enable speed of 1000 Mbps */
1016 PHY_CT_SP100
= PHY_CT_SPS_LSB
, /* enable speed of 100 Mbps */
1017 PHY_CT_SP10
= 0, /* enable speed of 10 Mbps */
1021 PHY_ST_EXT_ST
= 1<<8, /* Bit 8: Extended Status Present */
1023 PHY_ST_PRE_SUP
= 1<<6, /* Bit 6: Preamble Suppression */
1024 PHY_ST_AN_OVER
= 1<<5, /* Bit 5: Auto-Negotiation Over */
1025 PHY_ST_REM_FLT
= 1<<4, /* Bit 4: Remote Fault Condition Occured */
1026 PHY_ST_AN_CAP
= 1<<3, /* Bit 3: Auto-Negotiation Capability */
1027 PHY_ST_LSYNC
= 1<<2, /* Bit 2: Link Synchronized */
1028 PHY_ST_JAB_DET
= 1<<1, /* Bit 1: Jabber Detected */
1029 PHY_ST_EXT_REG
= 1<<0, /* Bit 0: Extended Register available */
1033 PHY_I1_OUI_MSK
= 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1034 PHY_I1_MOD_NUM
= 0x3f<<4, /* Bit 9.. 4: Model Number */
1035 PHY_I1_REV_MSK
= 0xf, /* Bit 3.. 0: Revision Number */
1038 /* different Marvell PHY Ids */
1040 PHY_MARV_ID0_VAL
= 0x0141, /* Marvell Unique Identifier */
1042 PHY_BCOM_ID1_A1
= 0x6041,
1043 PHY_BCOM_ID1_B2
= 0x6043,
1044 PHY_BCOM_ID1_C0
= 0x6044,
1045 PHY_BCOM_ID1_C5
= 0x6047,
1047 PHY_MARV_ID1_B0
= 0x0C23, /* Yukon (PHY 88E1011) */
1048 PHY_MARV_ID1_B2
= 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1049 PHY_MARV_ID1_C2
= 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1050 PHY_MARV_ID1_Y2
= 0x0C91, /* Yukon-2 (PHY 88E1112) */
1051 PHY_MARV_ID1_FE
= 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1052 PHY_MARV_ID1_ECU
= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1055 /* Advertisement register bits */
1057 PHY_AN_NXT_PG
= 1<<15, /* Bit 15: Request Next Page */
1058 PHY_AN_ACK
= 1<<14, /* Bit 14: (ro) Acknowledge Received */
1059 PHY_AN_RF
= 1<<13, /* Bit 13: Remote Fault Bits */
1061 PHY_AN_PAUSE_ASYM
= 1<<11,/* Bit 11: Try for asymmetric */
1062 PHY_AN_PAUSE_CAP
= 1<<10, /* Bit 10: Try for pause */
1063 PHY_AN_100BASE4
= 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1064 PHY_AN_100FULL
= 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1065 PHY_AN_100HALF
= 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1066 PHY_AN_10FULL
= 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1067 PHY_AN_10HALF
= 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1068 PHY_AN_CSMA
= 1<<0, /* Bit 0: Only selector supported */
1069 PHY_AN_SEL
= 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1070 PHY_AN_FULL
= PHY_AN_100FULL
| PHY_AN_10FULL
| PHY_AN_CSMA
,
1071 PHY_AN_ALL
= PHY_AN_10HALF
| PHY_AN_10FULL
|
1072 PHY_AN_100HALF
| PHY_AN_100FULL
,
1075 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1076 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1078 PHY_B_1000S_MSF
= 1<<15, /* Bit 15: Master/Slave Fault */
1079 PHY_B_1000S_MSR
= 1<<14, /* Bit 14: Master/Slave Result */
1080 PHY_B_1000S_LRS
= 1<<13, /* Bit 13: Local Receiver Status */
1081 PHY_B_1000S_RRS
= 1<<12, /* Bit 12: Remote Receiver Status */
1082 PHY_B_1000S_LP_FD
= 1<<11, /* Bit 11: Link Partner can FD */
1083 PHY_B_1000S_LP_HD
= 1<<10, /* Bit 10: Link Partner can HD */
1084 /* Bit 9..8: reserved */
1085 PHY_B_1000S_IEC
= 0xff, /* Bit 7..0: Idle Error Count */
1088 /** Marvell-Specific */
1090 PHY_M_AN_NXT_PG
= 1<<15, /* Request Next Page */
1091 PHY_M_AN_ACK
= 1<<14, /* (ro) Acknowledge Received */
1092 PHY_M_AN_RF
= 1<<13, /* Remote Fault */
1094 PHY_M_AN_ASP
= 1<<11, /* Asymmetric Pause */
1095 PHY_M_AN_PC
= 1<<10, /* MAC Pause implemented */
1096 PHY_M_AN_100_T4
= 1<<9, /* Not cap. 100Base-T4 (always 0) */
1097 PHY_M_AN_100_FD
= 1<<8, /* Advertise 100Base-TX Full Duplex */
1098 PHY_M_AN_100_HD
= 1<<7, /* Advertise 100Base-TX Half Duplex */
1099 PHY_M_AN_10_FD
= 1<<6, /* Advertise 10Base-TX Full Duplex */
1100 PHY_M_AN_10_HD
= 1<<5, /* Advertise 10Base-TX Half Duplex */
1101 PHY_M_AN_SEL_MSK
=0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1104 /* special defines for FIBER (88E1011S only) */
1106 PHY_M_AN_ASP_X
= 1<<8, /* Asymmetric Pause */
1107 PHY_M_AN_PC_X
= 1<<7, /* MAC Pause implemented */
1108 PHY_M_AN_1000X_AHD
= 1<<6, /* Advertise 10000Base-X Half Duplex */
1109 PHY_M_AN_1000X_AFD
= 1<<5, /* Advertise 10000Base-X Full Duplex */
1112 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1114 PHY_M_P_NO_PAUSE_X
= 0<<7,/* Bit 8.. 7: no Pause Mode */
1115 PHY_M_P_SYM_MD_X
= 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1116 PHY_M_P_ASYM_MD_X
= 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1117 PHY_M_P_BOTH_MD_X
= 3<<7,/* Bit 8.. 7: both Pause Mode */
1120 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1122 PHY_M_1000C_TEST
= 7<<13,/* Bit 15..13: Test Modes */
1123 PHY_M_1000C_MSE
= 1<<12, /* Manual Master/Slave Enable */
1124 PHY_M_1000C_MSC
= 1<<11, /* M/S Configuration (1=Master) */
1125 PHY_M_1000C_MPD
= 1<<10, /* Multi-Port Device */
1126 PHY_M_1000C_AFD
= 1<<9, /* Advertise Full Duplex */
1127 PHY_M_1000C_AHD
= 1<<8, /* Advertise Half Duplex */
1130 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1132 PHY_M_PC_TX_FFD_MSK
= 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1133 PHY_M_PC_RX_FFD_MSK
= 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1134 PHY_M_PC_ASS_CRS_TX
= 1<<11, /* Assert CRS on Transmit */
1135 PHY_M_PC_FL_GOOD
= 1<<10, /* Force Link Good */
1136 PHY_M_PC_EN_DET_MSK
= 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1137 PHY_M_PC_ENA_EXT_D
= 1<<7, /* Enable Ext. Distance (10BT) */
1138 PHY_M_PC_MDIX_MSK
= 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1139 PHY_M_PC_DIS_125CLK
= 1<<4, /* Disable 125 CLK */
1140 PHY_M_PC_MAC_POW_UP
= 1<<3, /* MAC Power up */
1141 PHY_M_PC_SQE_T_ENA
= 1<<2, /* SQE Test Enabled */
1142 PHY_M_PC_POL_R_DIS
= 1<<1, /* Polarity Reversal Disabled */
1143 PHY_M_PC_DIS_JABBER
= 1<<0, /* Disable Jabber */
1147 PHY_M_PC_EN_DET
= 2<<8, /* Energy Detect (Mode 1) */
1148 PHY_M_PC_EN_DET_PLUS
= 3<<8, /* Energy Detect Plus (Mode 2) */
1151 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1154 PHY_M_PC_MAN_MDI
= 0, /* 00 = Manual MDI configuration */
1155 PHY_M_PC_MAN_MDIX
= 1, /* 01 = Manual MDIX configuration */
1156 PHY_M_PC_ENA_AUTO
= 3, /* 11 = Enable Automatic Crossover */
1159 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1161 PHY_M_PC_COP_TX_DIS
= 1<<3, /* Copper Transmitter Disable */
1162 PHY_M_PC_POW_D_ENA
= 1<<2, /* Power Down Enable */
1165 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1167 PHY_M_PC_ENA_DTE_DT
= 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1168 PHY_M_PC_ENA_ENE_DT
= 1<<14, /* Enable Energy Detect (sense & pulse) */
1169 PHY_M_PC_DIS_NLP_CK
= 1<<13, /* Disable Normal Link Puls (NLP) Check */
1170 PHY_M_PC_ENA_LIP_NP
= 1<<12, /* Enable Link Partner Next Page Reg. */
1171 PHY_M_PC_DIS_NLP_GN
= 1<<11, /* Disable Normal Link Puls Generation */
1173 PHY_M_PC_DIS_SCRAMB
= 1<<9, /* Disable Scrambler */
1174 PHY_M_PC_DIS_FEFI
= 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1176 PHY_M_PC_SH_TP_SEL
= 1<<6, /* Shielded Twisted Pair Select */
1177 PHY_M_PC_RX_FD_MSK
= 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1180 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1182 PHY_M_PS_SPEED_MSK
= 3<<14, /* Bit 15..14: Speed Mask */
1183 PHY_M_PS_SPEED_1000
= 1<<15, /* 10 = 1000 Mbps */
1184 PHY_M_PS_SPEED_100
= 1<<14, /* 01 = 100 Mbps */
1185 PHY_M_PS_SPEED_10
= 0, /* 00 = 10 Mbps */
1186 PHY_M_PS_FULL_DUP
= 1<<13, /* Full Duplex */
1187 PHY_M_PS_PAGE_REC
= 1<<12, /* Page Received */
1188 PHY_M_PS_SPDUP_RES
= 1<<11, /* Speed & Duplex Resolved */
1189 PHY_M_PS_LINK_UP
= 1<<10, /* Link Up */
1190 PHY_M_PS_CABLE_MSK
= 7<<7, /* Bit 9.. 7: Cable Length Mask */
1191 PHY_M_PS_MDI_X_STAT
= 1<<6, /* MDI Crossover Stat (1=MDIX) */
1192 PHY_M_PS_DOWNS_STAT
= 1<<5, /* Downshift Status (1=downsh.) */
1193 PHY_M_PS_ENDET_STAT
= 1<<4, /* Energy Detect Status (1=act) */
1194 PHY_M_PS_TX_P_EN
= 1<<3, /* Tx Pause Enabled */
1195 PHY_M_PS_RX_P_EN
= 1<<2, /* Rx Pause Enabled */
1196 PHY_M_PS_POL_REV
= 1<<1, /* Polarity Reversed */
1197 PHY_M_PS_JABBER
= 1<<0, /* Jabber */
1200 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1202 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1204 PHY_M_PS_DTE_DETECT
= 1<<15, /* Data Terminal Equipment (DTE) Detected */
1205 PHY_M_PS_RES_SPEED
= 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1209 PHY_M_IS_AN_ERROR
= 1<<15, /* Auto-Negotiation Error */
1210 PHY_M_IS_LSP_CHANGE
= 1<<14, /* Link Speed Changed */
1211 PHY_M_IS_DUP_CHANGE
= 1<<13, /* Duplex Mode Changed */
1212 PHY_M_IS_AN_PR
= 1<<12, /* Page Received */
1213 PHY_M_IS_AN_COMPL
= 1<<11, /* Auto-Negotiation Completed */
1214 PHY_M_IS_LST_CHANGE
= 1<<10, /* Link Status Changed */
1215 PHY_M_IS_SYMB_ERROR
= 1<<9, /* Symbol Error */
1216 PHY_M_IS_FALSE_CARR
= 1<<8, /* False Carrier */
1217 PHY_M_IS_FIFO_ERROR
= 1<<7, /* FIFO Overflow/Underrun Error */
1218 PHY_M_IS_MDI_CHANGE
= 1<<6, /* MDI Crossover Changed */
1219 PHY_M_IS_DOWNSH_DET
= 1<<5, /* Downshift Detected */
1220 PHY_M_IS_END_CHANGE
= 1<<4, /* Energy Detect Changed */
1222 PHY_M_IS_DTE_CHANGE
= 1<<2, /* DTE Power Det. Status Changed */
1223 PHY_M_IS_POL_CHANGE
= 1<<1, /* Polarity Changed */
1224 PHY_M_IS_JABBER
= 1<<0, /* Jabber */
1226 PHY_M_DEF_MSK
= PHY_M_IS_LSP_CHANGE
| PHY_M_IS_LST_CHANGE
1227 | PHY_M_IS_DUP_CHANGE
,
1228 PHY_M_AN_MSK
= PHY_M_IS_AN_ERROR
| PHY_M_IS_AN_COMPL
,
1232 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1234 PHY_M_EC_ENA_BC_EXT
= 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1235 PHY_M_EC_ENA_LIN_LB
= 1<<14, /* Enable Line Loopback (88E1111 only) */
1237 PHY_M_EC_DIS_LINK_P
= 1<<12, /* Disable Link Pulses (88E1111 only) */
1238 PHY_M_EC_M_DSC_MSK
= 3<<10, /* Bit 11..10: Master Downshift Counter */
1239 /* (88E1011 only) */
1240 PHY_M_EC_S_DSC_MSK
= 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1241 /* (88E1011 only) */
1242 PHY_M_EC_M_DSC_MSK2
= 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1243 /* (88E1111 only) */
1244 PHY_M_EC_DOWN_S_ENA
= 1<<8, /* Downshift Enable (88E1111 only) */
1245 /* !!! Errata in spec. (1 = disable) */
1246 PHY_M_EC_RX_TIM_CT
= 1<<7, /* RGMII Rx Timing Control*/
1247 PHY_M_EC_MAC_S_MSK
= 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1248 PHY_M_EC_FIB_AN_ENA
= 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1249 PHY_M_EC_DTE_D_ENA
= 1<<2, /* DTE Detect Enable (88E1111 only) */
1250 PHY_M_EC_TX_TIM_CT
= 1<<1, /* RGMII Tx Timing Control */
1251 PHY_M_EC_TRANS_DIS
= 1<<0, /* Transmitter Disable (88E1111 only) */};
1253 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1254 /* 00=1x; 01=2x; 10=3x; 11=4x */
1255 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1256 /* 00=dis; 01=1x; 10=2x; 11=3x */
1257 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1258 /* 000=1x; 001=2x; 010=3x; 011=4x */
1259 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1260 /* 01X=0; 110=2.5; 111=25 (MHz) */
1262 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1264 PHY_M_PC_DIS_LINK_Pa
= 1<<15,/* Disable Link Pulses */
1265 PHY_M_PC_DSC_MSK
= 7<<12,/* Bit 14..12: Downshift Counter */
1266 PHY_M_PC_DOWN_S_ENA
= 1<<11,/* Downshift Enable */
1268 /* !!! Errata in spec. (1 = disable) */
1270 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1271 /* 100=5x; 101=6x; 110=7x; 111=8x */
1273 MAC_TX_CLK_0_MHZ
= 2,
1274 MAC_TX_CLK_2_5_MHZ
= 6,
1275 MAC_TX_CLK_25_MHZ
= 7,
1278 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1280 PHY_M_LEDC_DIS_LED
= 1<<15, /* Disable LED */
1281 PHY_M_LEDC_PULS_MSK
= 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1282 PHY_M_LEDC_F_INT
= 1<<11, /* Force Interrupt */
1283 PHY_M_LEDC_BL_R_MSK
= 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1284 PHY_M_LEDC_DP_C_LSB
= 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1285 PHY_M_LEDC_TX_C_LSB
= 1<<6, /* Tx Control (LSB, 88E1111 only) */
1286 PHY_M_LEDC_LK_C_MSK
= 7<<3,/* Bit 5.. 3: Link Control Mask */
1287 /* (88E1111 only) */
1291 PHY_M_LEDC_LINK_MSK
= 3<<3,/* Bit 4.. 3: Link Control Mask */
1292 /* (88E1011 only) */
1293 PHY_M_LEDC_DP_CTRL
= 1<<2, /* Duplex Control */
1294 PHY_M_LEDC_DP_C_MSB
= 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1295 PHY_M_LEDC_RX_CTRL
= 1<<1, /* Rx Activity / Link */
1296 PHY_M_LEDC_TX_CTRL
= 1<<0, /* Tx Activity / Link */
1297 PHY_M_LEDC_TX_C_MSB
= 1<<0, /* Tx Control (MSB, 88E1111 only) */
1300 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1302 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1304 PHY_M_POLC_LS1M_MSK
= 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1305 PHY_M_POLC_IS0M_MSK
= 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1306 PHY_M_POLC_LOS_MSK
= 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1307 PHY_M_POLC_INIT_MSK
= 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1308 PHY_M_POLC_STA1_MSK
= 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1309 PHY_M_POLC_STA0_MSK
= 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1312 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1313 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1314 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1315 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1316 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1317 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1320 PULS_NO_STR
= 0,/* no pulse stretching */
1321 PULS_21MS
= 1,/* 21 ms to 42 ms */
1322 PULS_42MS
= 2,/* 42 ms to 84 ms */
1323 PULS_84MS
= 3,/* 84 ms to 170 ms */
1324 PULS_170MS
= 4,/* 170 ms to 340 ms */
1325 PULS_340MS
= 5,/* 340 ms to 670 ms */
1326 PULS_670MS
= 6,/* 670 ms to 1.3 s */
1327 PULS_1300MS
= 7,/* 1.3 s to 2.7 s */
1330 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1333 BLINK_42MS
= 0,/* 42 ms */
1334 BLINK_84MS
= 1,/* 84 ms */
1335 BLINK_170MS
= 2,/* 170 ms */
1336 BLINK_340MS
= 3,/* 340 ms */
1337 BLINK_670MS
= 4,/* 670 ms */
1340 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1341 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1343 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1344 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1345 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1346 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1347 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1348 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1357 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1359 PHY_M_EC2_FI_IMPED
= 1<<6, /* Fiber Input Impedance */
1360 PHY_M_EC2_FO_IMPED
= 1<<5, /* Fiber Output Impedance */
1361 PHY_M_EC2_FO_M_CLK
= 1<<4, /* Fiber Mode Clock Enable */
1362 PHY_M_EC2_FO_BOOST
= 1<<3, /* Fiber Output Boost */
1363 PHY_M_EC2_FO_AM_MSK
= 7,/* Bit 2.. 0: Fiber Output Amplitude */
1366 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1368 PHY_M_FC_AUTO_SEL
= 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1369 PHY_M_FC_AN_REG_ACC
= 1<<14, /* Fiber/Copper AN Reg. Access */
1370 PHY_M_FC_RESOLUTION
= 1<<13, /* Fiber/Copper Resolution */
1371 PHY_M_SER_IF_AN_BP
= 1<<12, /* Ser. IF AN Bypass Enable */
1372 PHY_M_SER_IF_BP_ST
= 1<<11, /* Ser. IF AN Bypass Status */
1373 PHY_M_IRQ_POLARITY
= 1<<10, /* IRQ polarity */
1374 PHY_M_DIS_AUT_MED
= 1<<9, /* Disable Aut. Medium Reg. Selection */
1375 /* (88E1111 only) */
1377 PHY_M_UNDOC1
= 1<<7, /* undocumented bit !! */
1378 PHY_M_DTE_POW_STAT
= 1<<4, /* DTE Power Status (88E1111 only) */
1379 PHY_M_MODE_MASK
= 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1382 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1383 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1384 /* Bit 15..12: reserved (used internally) */
1386 PHY_M_FELP_LED2_MSK
= 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1387 PHY_M_FELP_LED1_MSK
= 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1388 PHY_M_FELP_LED0_MSK
= 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1391 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1392 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1393 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1396 LED_PAR_CTRL_COLX
= 0x00,
1397 LED_PAR_CTRL_ERROR
= 0x01,
1398 LED_PAR_CTRL_DUPLEX
= 0x02,
1399 LED_PAR_CTRL_DP_COL
= 0x03,
1400 LED_PAR_CTRL_SPEED
= 0x04,
1401 LED_PAR_CTRL_LINK
= 0x05,
1402 LED_PAR_CTRL_TX
= 0x06,
1403 LED_PAR_CTRL_RX
= 0x07,
1404 LED_PAR_CTRL_ACT
= 0x08,
1405 LED_PAR_CTRL_LNK_RX
= 0x09,
1406 LED_PAR_CTRL_LNK_AC
= 0x0a,
1407 LED_PAR_CTRL_ACT_BL
= 0x0b,
1408 LED_PAR_CTRL_TX_BL
= 0x0c,
1409 LED_PAR_CTRL_RX_BL
= 0x0d,
1410 LED_PAR_CTRL_COL_BL
= 0x0e,
1411 LED_PAR_CTRL_INACT
= 0x0f
1414 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1416 PHY_M_FESC_DIS_WAIT
= 1<<2, /* Disable TDR Waiting Period */
1417 PHY_M_FESC_ENA_MCLK
= 1<<1, /* Enable MAC Rx Clock in sleep mode */
1418 PHY_M_FESC_SEL_CL_A
= 1<<0, /* Select Class A driver (100B-TX) */
1421 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1422 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1424 PHY_M_FIB_FORCE_LNK
= 1<<10,/* Force Link Good */
1425 PHY_M_FIB_SIGD_POL
= 1<<9, /* SIGDET Polarity */
1426 PHY_M_FIB_TX_DIS
= 1<<3, /* Transmitter Disable */
1429 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1430 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1432 PHY_M_MAC_MD_MSK
= 7<<7, /* Bit 9.. 7: Mode Select Mask */
1433 PHY_M_MAC_GMIF_PUP
= 1<<3, /* GMII Power Up (88E1149 only) */
1434 PHY_M_MAC_MD_AUTO
= 3,/* Auto Copper/1000Base-X */
1435 PHY_M_MAC_MD_COPPER
= 5,/* Copper only */
1436 PHY_M_MAC_MD_1000BX
= 7,/* 1000Base-X only */
1438 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1440 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1442 PHY_M_LEDC_LOS_MSK
= 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1443 PHY_M_LEDC_INIT_MSK
= 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1444 PHY_M_LEDC_STA1_MSK
= 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1445 PHY_M_LEDC_STA0_MSK
= 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1448 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1449 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1450 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1451 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1453 /* GMAC registers */
1454 /* Port Registers */
1456 GM_GP_STAT
= 0x0000, /* 16 bit r/o General Purpose Status */
1457 GM_GP_CTRL
= 0x0004, /* 16 bit r/w General Purpose Control */
1458 GM_TX_CTRL
= 0x0008, /* 16 bit r/w Transmit Control Reg. */
1459 GM_RX_CTRL
= 0x000c, /* 16 bit r/w Receive Control Reg. */
1460 GM_TX_FLOW_CTRL
= 0x0010, /* 16 bit r/w Transmit Flow-Control */
1461 GM_TX_PARAM
= 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1462 GM_SERIAL_MODE
= 0x0018, /* 16 bit r/w Serial Mode Register */
1463 /* Source Address Registers */
1464 GM_SRC_ADDR_1L
= 0x001c, /* 16 bit r/w Source Address 1 (low) */
1465 GM_SRC_ADDR_1M
= 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1466 GM_SRC_ADDR_1H
= 0x0024, /* 16 bit r/w Source Address 1 (high) */
1467 GM_SRC_ADDR_2L
= 0x0028, /* 16 bit r/w Source Address 2 (low) */
1468 GM_SRC_ADDR_2M
= 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1469 GM_SRC_ADDR_2H
= 0x0030, /* 16 bit r/w Source Address 2 (high) */
1471 /* Multicast Address Hash Registers */
1472 GM_MC_ADDR_H1
= 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1473 GM_MC_ADDR_H2
= 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1474 GM_MC_ADDR_H3
= 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1475 GM_MC_ADDR_H4
= 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1477 /* Interrupt Source Registers */
1478 GM_TX_IRQ_SRC
= 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1479 GM_RX_IRQ_SRC
= 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1480 GM_TR_IRQ_SRC
= 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1482 /* Interrupt Mask Registers */
1483 GM_TX_IRQ_MSK
= 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1484 GM_RX_IRQ_MSK
= 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1485 GM_TR_IRQ_MSK
= 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1487 /* Serial Management Interface (SMI) Registers */
1488 GM_SMI_CTRL
= 0x0080, /* 16 bit r/w SMI Control Register */
1489 GM_SMI_DATA
= 0x0084, /* 16 bit r/w SMI Data Register */
1490 GM_PHY_ADDR
= 0x0088, /* 16 bit r/w GPHY Address Register */
1492 GM_MIB_CNT_BASE
= 0x0100, /* Base Address of MIB Counters */
1493 GM_MIB_CNT_END
= 0x025C, /* Last MIB counter */
1498 * MIB Counters base address definitions (low word) -
1499 * use offset 4 for access to high word (32 bit r/o)
1502 GM_RXF_UC_OK
= GM_MIB_CNT_BASE
+ 0, /* Unicast Frames Received OK */
1503 GM_RXF_BC_OK
= GM_MIB_CNT_BASE
+ 8, /* Broadcast Frames Received OK */
1504 GM_RXF_MPAUSE
= GM_MIB_CNT_BASE
+ 16, /* Pause MAC Ctrl Frames Received */
1505 GM_RXF_MC_OK
= GM_MIB_CNT_BASE
+ 24, /* Multicast Frames Received OK */
1506 GM_RXF_FCS_ERR
= GM_MIB_CNT_BASE
+ 32, /* Rx Frame Check Seq. Error */
1508 GM_RXO_OK_LO
= GM_MIB_CNT_BASE
+ 48, /* Octets Received OK Low */
1509 GM_RXO_OK_HI
= GM_MIB_CNT_BASE
+ 56, /* Octets Received OK High */
1510 GM_RXO_ERR_LO
= GM_MIB_CNT_BASE
+ 64, /* Octets Received Invalid Low */
1511 GM_RXO_ERR_HI
= GM_MIB_CNT_BASE
+ 72, /* Octets Received Invalid High */
1512 GM_RXF_SHT
= GM_MIB_CNT_BASE
+ 80, /* Frames <64 Byte Received OK */
1513 GM_RXE_FRAG
= GM_MIB_CNT_BASE
+ 88, /* Frames <64 Byte Received with FCS Err */
1514 GM_RXF_64B
= GM_MIB_CNT_BASE
+ 96, /* 64 Byte Rx Frame */
1515 GM_RXF_127B
= GM_MIB_CNT_BASE
+ 104,/* 65-127 Byte Rx Frame */
1516 GM_RXF_255B
= GM_MIB_CNT_BASE
+ 112,/* 128-255 Byte Rx Frame */
1517 GM_RXF_511B
= GM_MIB_CNT_BASE
+ 120,/* 256-511 Byte Rx Frame */
1518 GM_RXF_1023B
= GM_MIB_CNT_BASE
+ 128,/* 512-1023 Byte Rx Frame */
1519 GM_RXF_1518B
= GM_MIB_CNT_BASE
+ 136,/* 1024-1518 Byte Rx Frame */
1520 GM_RXF_MAX_SZ
= GM_MIB_CNT_BASE
+ 144,/* 1519-MaxSize Byte Rx Frame */
1521 GM_RXF_LNG_ERR
= GM_MIB_CNT_BASE
+ 152,/* Rx Frame too Long Error */
1522 GM_RXF_JAB_PKT
= GM_MIB_CNT_BASE
+ 160,/* Rx Jabber Packet Frame */
1524 GM_RXE_FIFO_OV
= GM_MIB_CNT_BASE
+ 176,/* Rx FIFO overflow Event */
1525 GM_TXF_UC_OK
= GM_MIB_CNT_BASE
+ 192,/* Unicast Frames Xmitted OK */
1526 GM_TXF_BC_OK
= GM_MIB_CNT_BASE
+ 200,/* Broadcast Frames Xmitted OK */
1527 GM_TXF_MPAUSE
= GM_MIB_CNT_BASE
+ 208,/* Pause MAC Ctrl Frames Xmitted */
1528 GM_TXF_MC_OK
= GM_MIB_CNT_BASE
+ 216,/* Multicast Frames Xmitted OK */
1529 GM_TXO_OK_LO
= GM_MIB_CNT_BASE
+ 224,/* Octets Transmitted OK Low */
1530 GM_TXO_OK_HI
= GM_MIB_CNT_BASE
+ 232,/* Octets Transmitted OK High */
1531 GM_TXF_64B
= GM_MIB_CNT_BASE
+ 240,/* 64 Byte Tx Frame */
1532 GM_TXF_127B
= GM_MIB_CNT_BASE
+ 248,/* 65-127 Byte Tx Frame */
1533 GM_TXF_255B
= GM_MIB_CNT_BASE
+ 256,/* 128-255 Byte Tx Frame */
1534 GM_TXF_511B
= GM_MIB_CNT_BASE
+ 264,/* 256-511 Byte Tx Frame */
1535 GM_TXF_1023B
= GM_MIB_CNT_BASE
+ 272,/* 512-1023 Byte Tx Frame */
1536 GM_TXF_1518B
= GM_MIB_CNT_BASE
+ 280,/* 1024-1518 Byte Tx Frame */
1537 GM_TXF_MAX_SZ
= GM_MIB_CNT_BASE
+ 288,/* 1519-MaxSize Byte Tx Frame */
1539 GM_TXF_COL
= GM_MIB_CNT_BASE
+ 304,/* Tx Collision */
1540 GM_TXF_LAT_COL
= GM_MIB_CNT_BASE
+ 312,/* Tx Late Collision */
1541 GM_TXF_ABO_COL
= GM_MIB_CNT_BASE
+ 320,/* Tx aborted due to Exces. Col. */
1542 GM_TXF_MUL_COL
= GM_MIB_CNT_BASE
+ 328,/* Tx Multiple Collision */
1543 GM_TXF_SNG_COL
= GM_MIB_CNT_BASE
+ 336,/* Tx Single Collision */
1544 GM_TXE_FIFO_UR
= GM_MIB_CNT_BASE
+ 344,/* Tx FIFO Underrun Event */
1547 /* GMAC Bit Definitions */
1548 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1550 GM_GPSR_SPEED
= 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1551 GM_GPSR_DUPLEX
= 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1552 GM_GPSR_FC_TX_DIS
= 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1553 GM_GPSR_LINK_UP
= 1<<12, /* Bit 12: Link Up Status */
1554 GM_GPSR_PAUSE
= 1<<11, /* Bit 11: Pause State */
1555 GM_GPSR_TX_ACTIVE
= 1<<10, /* Bit 10: Tx in Progress */
1556 GM_GPSR_EXC_COL
= 1<<9, /* Bit 9: Excessive Collisions Occured */
1557 GM_GPSR_LAT_COL
= 1<<8, /* Bit 8: Late Collisions Occured */
1559 GM_GPSR_PHY_ST_CH
= 1<<5, /* Bit 5: PHY Status Change */
1560 GM_GPSR_GIG_SPEED
= 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1561 GM_GPSR_PART_MODE
= 1<<3, /* Bit 3: Partition mode */
1562 GM_GPSR_FC_RX_DIS
= 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1563 GM_GPSR_PROM_EN
= 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1566 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1568 GM_GPCR_PROM_ENA
= 1<<14, /* Bit 14: Enable Promiscuous Mode */
1569 GM_GPCR_FC_TX_DIS
= 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1570 GM_GPCR_TX_ENA
= 1<<12, /* Bit 12: Enable Transmit */
1571 GM_GPCR_RX_ENA
= 1<<11, /* Bit 11: Enable Receive */
1572 GM_GPCR_BURST_ENA
= 1<<10, /* Bit 10: Enable Burst Mode */
1573 GM_GPCR_LOOP_ENA
= 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1574 GM_GPCR_PART_ENA
= 1<<8, /* Bit 8: Enable Partition Mode */
1575 GM_GPCR_GIGS_ENA
= 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1576 GM_GPCR_FL_PASS
= 1<<6, /* Bit 6: Force Link Pass */
1577 GM_GPCR_DUP_FULL
= 1<<5, /* Bit 5: Full Duplex Mode */
1578 GM_GPCR_FC_RX_DIS
= 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1579 GM_GPCR_SPEED_100
= 1<<3, /* Bit 3: Port Speed 100 Mbps */
1580 GM_GPCR_AU_DUP_DIS
= 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1581 GM_GPCR_AU_FCT_DIS
= 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1582 GM_GPCR_AU_SPD_DIS
= 1<<0, /* Bit 0: Disable Auto-Update Speed */
1585 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1587 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1589 GM_TXCR_FORCE_JAM
= 1<<15, /* Bit 15: Force Jam / Flow-Control */
1590 GM_TXCR_CRC_DIS
= 1<<14, /* Bit 14: Disable insertion of CRC */
1591 GM_TXCR_PAD_DIS
= 1<<13, /* Bit 13: Disable padding of packets */
1592 GM_TXCR_COL_THR_MSK
= 7<<10, /* Bit 12..10: Collision Threshold */
1595 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1596 #define TX_COL_DEF 0x04
1598 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1600 GM_RXCR_UCF_ENA
= 1<<15, /* Bit 15: Enable Unicast filtering */
1601 GM_RXCR_MCF_ENA
= 1<<14, /* Bit 14: Enable Multicast filtering */
1602 GM_RXCR_CRC_DIS
= 1<<13, /* Bit 13: Remove 4-byte CRC */
1603 GM_RXCR_PASS_FC
= 1<<12, /* Bit 12: Pass FC packets to FIFO */
1606 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1608 GM_TXPA_JAMLEN_MSK
= 0x03<<14, /* Bit 15..14: Jam Length */
1609 GM_TXPA_JAMIPG_MSK
= 0x1f<<9, /* Bit 13..9: Jam IPG */
1610 GM_TXPA_JAMDAT_MSK
= 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1611 GM_TXPA_BO_LIM_MSK
= 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1613 TX_JAM_LEN_DEF
= 0x03,
1614 TX_JAM_IPG_DEF
= 0x0b,
1615 TX_IPG_JAM_DEF
= 0x1c,
1616 TX_BOF_LIM_DEF
= 0x04,
1619 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1620 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1621 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1622 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1625 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1627 GM_SMOD_DATABL_MSK
= 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1628 GM_SMOD_LIMIT_4
= 1<<10, /* Bit 10: 4 consecutive Tx trials */
1629 GM_SMOD_VLAN_ENA
= 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1630 GM_SMOD_JUMBO_ENA
= 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1631 GM_SMOD_IPG_MSK
= 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1634 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1635 #define DATA_BLIND_DEF 0x04
1637 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1638 #define IPG_DATA_DEF 0x1e
1640 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1642 GM_SMI_CT_PHY_A_MSK
= 0x1f<<11,/* Bit 15..11: PHY Device Address */
1643 GM_SMI_CT_REG_A_MSK
= 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1644 GM_SMI_CT_OP_RD
= 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1645 GM_SMI_CT_RD_VAL
= 1<<4, /* Bit 4: Read Valid (Read completed) */
1646 GM_SMI_CT_BUSY
= 1<<3, /* Bit 3: Busy (Operation in progress) */
1649 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1650 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1652 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1654 GM_PAR_MIB_CLR
= 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1655 GM_PAR_MIB_TST
= 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1658 /* Receive Frame Status Encoding */
1660 GMR_FS_LEN
= 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1661 GMR_FS_VLAN
= 1<<13, /* VLAN Packet */
1662 GMR_FS_JABBER
= 1<<12, /* Jabber Packet */
1663 GMR_FS_UN_SIZE
= 1<<11, /* Undersize Packet */
1664 GMR_FS_MC
= 1<<10, /* Multicast Packet */
1665 GMR_FS_BC
= 1<<9, /* Broadcast Packet */
1666 GMR_FS_RX_OK
= 1<<8, /* Receive OK (Good Packet) */
1667 GMR_FS_GOOD_FC
= 1<<7, /* Good Flow-Control Packet */
1668 GMR_FS_BAD_FC
= 1<<6, /* Bad Flow-Control Packet */
1669 GMR_FS_MII_ERR
= 1<<5, /* MII Error */
1670 GMR_FS_LONG_ERR
= 1<<4, /* Too Long Packet */
1671 GMR_FS_FRAGMENT
= 1<<3, /* Fragment */
1673 GMR_FS_CRC_ERR
= 1<<1, /* CRC Error */
1674 GMR_FS_RX_FF_OV
= 1<<0, /* Rx FIFO Overflow */
1676 GMR_FS_ANY_ERR
= GMR_FS_RX_FF_OV
| GMR_FS_CRC_ERR
|
1677 GMR_FS_FRAGMENT
| GMR_FS_LONG_ERR
|
1678 GMR_FS_MII_ERR
| GMR_FS_BAD_FC
|
1679 GMR_FS_UN_SIZE
| GMR_FS_JABBER
,
1682 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1684 RX_TRUNC_ON
= 1<<27, /* enable packet truncation */
1685 RX_TRUNC_OFF
= 1<<26, /* disable packet truncation */
1686 RX_VLAN_STRIP_ON
= 1<<25, /* enable VLAN stripping */
1687 RX_VLAN_STRIP_OFF
= 1<<24, /* disable VLAN stripping */
1689 RX_MACSEC_FLUSH_ON
= 1<<23,
1690 RX_MACSEC_FLUSH_OFF
= 1<<22,
1691 RX_MACSEC_ASF_FLUSH_ON
= 1<<21,
1692 RX_MACSEC_ASF_FLUSH_OFF
= 1<<20,
1694 GMF_RX_OVER_ON
= 1<<19, /* enable flushing on receive overrun */
1695 GMF_RX_OVER_OFF
= 1<<18, /* disable flushing on receive overrun */
1696 GMF_ASF_RX_OVER_ON
= 1<<17, /* enable flushing of ASF when overrun */
1697 GMF_ASF_RX_OVER_OFF
= 1<<16, /* disable flushing of ASF when overrun */
1699 GMF_WP_TST_ON
= 1<<14, /* Write Pointer Test On */
1700 GMF_WP_TST_OFF
= 1<<13, /* Write Pointer Test Off */
1701 GMF_WP_STEP
= 1<<12, /* Write Pointer Step/Increment */
1703 GMF_RP_TST_ON
= 1<<10, /* Read Pointer Test On */
1704 GMF_RP_TST_OFF
= 1<<9, /* Read Pointer Test Off */
1705 GMF_RP_STEP
= 1<<8, /* Read Pointer Step/Increment */
1706 GMF_RX_F_FL_ON
= 1<<7, /* Rx FIFO Flush Mode On */
1707 GMF_RX_F_FL_OFF
= 1<<6, /* Rx FIFO Flush Mode Off */
1708 GMF_CLI_RX_FO
= 1<<5, /* Clear IRQ Rx FIFO Overrun */
1709 GMF_CLI_RX_C
= 1<<4, /* Clear IRQ Rx Frame Complete */
1711 GMF_OPER_ON
= 1<<3, /* Operational Mode On */
1712 GMF_OPER_OFF
= 1<<2, /* Operational Mode Off */
1713 GMF_RST_CLR
= 1<<1, /* Clear GMAC FIFO Reset */
1714 GMF_RST_SET
= 1<<0, /* Set GMAC FIFO Reset */
1716 RX_GMF_FL_THR_DEF
= 0xa, /* flush threshold (default) */
1718 GMF_RX_CTRL_DEF
= GMF_OPER_ON
| GMF_RX_F_FL_ON
,
1721 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1723 TX_DYN_WM_ENA
= 3, /* Yukon-FE+ specific */
1726 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1728 TX_STFW_DIS
= 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1729 TX_STFW_ENA
= 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1731 TX_VLAN_TAG_ON
= 1<<25,/* enable VLAN tagging */
1732 TX_VLAN_TAG_OFF
= 1<<24,/* disable VLAN tagging */
1734 TX_JUMBO_ENA
= 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1735 TX_JUMBO_DIS
= 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1737 GMF_WSP_TST_ON
= 1<<18,/* Write Shadow Pointer Test On */
1738 GMF_WSP_TST_OFF
= 1<<17,/* Write Shadow Pointer Test Off */
1739 GMF_WSP_STEP
= 1<<16,/* Write Shadow Pointer Step/Increment */
1741 GMF_CLI_TX_FU
= 1<<6, /* Clear IRQ Tx FIFO Underrun */
1742 GMF_CLI_TX_FC
= 1<<5, /* Clear IRQ Tx Frame Complete */
1743 GMF_CLI_TX_PE
= 1<<4, /* Clear IRQ Tx Parity Error */
1746 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1748 GMT_ST_START
= 1<<2, /* Start Time Stamp Timer */
1749 GMT_ST_STOP
= 1<<1, /* Stop Time Stamp Timer */
1750 GMT_ST_CLR_IRQ
= 1<<0, /* Clear Time Stamp Timer IRQ */
1753 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1755 Y2_ASF_OS_PRES
= 1<<4, /* ASF operation system present */
1756 Y2_ASF_RESET
= 1<<3, /* ASF system in reset state */
1757 Y2_ASF_RUNNING
= 1<<2, /* ASF system operational */
1758 Y2_ASF_CLR_HSTI
= 1<<1, /* Clear ASF IRQ */
1759 Y2_ASF_IRQ
= 1<<0, /* Issue an IRQ to ASF system */
1761 Y2_ASF_UC_STATE
= 3<<2, /* ASF uC State */
1762 Y2_ASF_CLK_HALT
= 0, /* ASF system clock stopped */
1765 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1767 Y2_ASF_CLR_ASFI
= 1<<1, /* Clear host IRQ */
1768 Y2_ASF_HOST_IRQ
= 1<<0, /* Issue an IRQ to HOST system */
1770 /* HCU_CCSR CPU Control and Status Register */
1772 HCU_CCSR_SMBALERT_MONITOR
= 1<<27, /* SMBALERT pin monitor */
1773 HCU_CCSR_CPU_SLEEP
= 1<<26, /* CPU sleep status */
1774 /* Clock Stretching Timeout */
1775 HCU_CCSR_CS_TO
= 1<<25,
1776 HCU_CCSR_WDOG
= 1<<24, /* Watchdog Reset */
1778 HCU_CCSR_CLR_IRQ_HOST
= 1<<17, /* Clear IRQ_HOST */
1779 HCU_CCSR_SET_IRQ_HCU
= 1<<16, /* Set IRQ_HCU */
1781 HCU_CCSR_AHB_RST
= 1<<9, /* Reset AHB bridge */
1782 HCU_CCSR_CPU_RST_MODE
= 1<<8, /* CPU Reset Mode */
1784 HCU_CCSR_SET_SYNC_CPU
= 1<<5,
1785 HCU_CCSR_CPU_CLK_DIVIDE_MSK
= 3<<3,/* CPU Clock Divide */
1786 HCU_CCSR_CPU_CLK_DIVIDE_BASE
= 1<<3,
1787 HCU_CCSR_OS_PRSNT
= 1<<2, /* ASF OS Present */
1788 /* Microcontroller State */
1789 HCU_CCSR_UC_STATE_MSK
= 3,
1790 HCU_CCSR_UC_STATE_BASE
= 1<<0,
1791 HCU_CCSR_ASF_RESET
= 0,
1792 HCU_CCSR_ASF_HALTED
= 1<<1,
1793 HCU_CCSR_ASF_RUNNING
= 1<<0,
1796 /* HCU_HCSR Host Control and Status Register */
1798 HCU_HCSR_SET_IRQ_CPU
= 1<<16, /* Set IRQ_CPU */
1800 HCU_HCSR_CLR_IRQ_HCU
= 1<<1, /* Clear IRQ_HCU */
1801 HCU_HCSR_SET_IRQ_HOST
= 1<<0, /* Set IRQ_HOST */
1804 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1806 SC_STAT_CLR_IRQ
= 1<<4, /* Status Burst IRQ clear */
1807 SC_STAT_OP_ON
= 1<<3, /* Operational Mode On */
1808 SC_STAT_OP_OFF
= 1<<2, /* Operational Mode Off */
1809 SC_STAT_RST_CLR
= 1<<1, /* Clear Status Unit Reset (Enable) */
1810 SC_STAT_RST_SET
= 1<<0, /* Set Status Unit Reset */
1813 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1815 GMC_SET_RST
= 1<<15,/* MAC SEC RST */
1816 GMC_SEC_RST_OFF
= 1<<14,/* MAC SEC RSt OFF */
1817 GMC_BYP_MACSECRX_ON
= 1<<13,/* Bypass macsec RX */
1818 GMC_BYP_MACSECRX_OFF
= 1<<12,/* Bypass macsec RX off */
1819 GMC_BYP_MACSECTX_ON
= 1<<11,/* Bypass macsec TX */
1820 GMC_BYP_MACSECTX_OFF
= 1<<10,/* Bypass macsec TX off*/
1821 GMC_BYP_RETR_ON
= 1<<9, /* Bypass retransmit FIFO On */
1822 GMC_BYP_RETR_OFF
= 1<<8, /* Bypass retransmit FIFO Off */
1824 GMC_H_BURST_ON
= 1<<7, /* Half Duplex Burst Mode On */
1825 GMC_H_BURST_OFF
= 1<<6, /* Half Duplex Burst Mode Off */
1826 GMC_F_LOOPB_ON
= 1<<5, /* FIFO Loopback On */
1827 GMC_F_LOOPB_OFF
= 1<<4, /* FIFO Loopback Off */
1828 GMC_PAUSE_ON
= 1<<3, /* Pause On */
1829 GMC_PAUSE_OFF
= 1<<2, /* Pause Off */
1830 GMC_RST_CLR
= 1<<1, /* Clear GMAC Reset */
1831 GMC_RST_SET
= 1<<0, /* Set GMAC Reset */
1834 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1836 GPC_TX_PAUSE
= 1<<30, /* Tx pause enabled (ro) */
1837 GPC_RX_PAUSE
= 1<<29, /* Rx pause enabled (ro) */
1838 GPC_SPEED
= 3<<27, /* PHY speed (ro) */
1839 GPC_LINK
= 1<<26, /* Link up (ro) */
1840 GPC_DUPLEX
= 1<<25, /* Duplex (ro) */
1841 GPC_CLOCK
= 1<<24, /* 125Mhz clock stable (ro) */
1843 GPC_PDOWN
= 1<<23, /* Internal regulator 2.5 power down */
1844 GPC_TSTMODE
= 1<<22, /* Test mode */
1845 GPC_REG18
= 1<<21, /* Reg18 Power down */
1846 GPC_REG12SEL
= 3<<19, /* Reg12 power setting */
1847 GPC_REG18SEL
= 3<<17, /* Reg18 power setting */
1848 GPC_SPILOCK
= 1<<16, /* SPI lock (ASF) */
1850 GPC_LEDMUX
= 3<<14, /* LED Mux */
1851 GPC_INTPOL
= 1<<13, /* Interrupt polarity */
1852 GPC_DETECT
= 1<<12, /* Energy detect */
1853 GPC_1000HD
= 1<<11, /* Enable 1000Mbit HD */
1854 GPC_SLAVE
= 1<<10, /* Slave mode */
1855 GPC_PAUSE
= 1<<9, /* Pause enable */
1856 GPC_LEDCTL
= 3<<6, /* GPHY Leds */
1858 GPC_RST_CLR
= 1<<1, /* Clear GPHY Reset */
1859 GPC_RST_SET
= 1<<0, /* Set GPHY Reset */
1862 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1863 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1865 GM_IS_TX_CO_OV
= 1<<5, /* Transmit Counter Overflow IRQ */
1866 GM_IS_RX_CO_OV
= 1<<4, /* Receive Counter Overflow IRQ */
1867 GM_IS_TX_FF_UR
= 1<<3, /* Transmit FIFO Underrun */
1868 GM_IS_TX_COMPL
= 1<<2, /* Frame Transmission Complete */
1869 GM_IS_RX_FF_OR
= 1<<1, /* Receive FIFO Overrun */
1870 GM_IS_RX_COMPL
= 1<<0, /* Frame Reception Complete */
1872 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1875 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1876 enum { /* Bits 15.. 2: reserved */
1877 GMLC_RST_CLR
= 1<<1, /* Clear GMAC Link Reset */
1878 GMLC_RST_SET
= 1<<0, /* Set GMAC Link Reset */
1882 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1884 WOL_CTL_LINK_CHG_OCC
= 1<<15,
1885 WOL_CTL_MAGIC_PKT_OCC
= 1<<14,
1886 WOL_CTL_PATTERN_OCC
= 1<<13,
1887 WOL_CTL_CLEAR_RESULT
= 1<<12,
1888 WOL_CTL_ENA_PME_ON_LINK_CHG
= 1<<11,
1889 WOL_CTL_DIS_PME_ON_LINK_CHG
= 1<<10,
1890 WOL_CTL_ENA_PME_ON_MAGIC_PKT
= 1<<9,
1891 WOL_CTL_DIS_PME_ON_MAGIC_PKT
= 1<<8,
1892 WOL_CTL_ENA_PME_ON_PATTERN
= 1<<7,
1893 WOL_CTL_DIS_PME_ON_PATTERN
= 1<<6,
1894 WOL_CTL_ENA_LINK_CHG_UNIT
= 1<<5,
1895 WOL_CTL_DIS_LINK_CHG_UNIT
= 1<<4,
1896 WOL_CTL_ENA_MAGIC_PKT_UNIT
= 1<<3,
1897 WOL_CTL_DIS_MAGIC_PKT_UNIT
= 1<<2,
1898 WOL_CTL_ENA_PATTERN_UNIT
= 1<<1,
1899 WOL_CTL_DIS_PATTERN_UNIT
= 1<<0,
1920 OP_TCPCHKSUM
= OP_TCPSTART
,
1921 OP_TCPIS
= OP_TCPINIT
| OP_TCPSTART
,
1922 OP_TCPLW
= OP_TCPLCK
| OP_TCPWRITE
,
1923 OP_TCPLSW
= OP_TCPLCK
| OP_TCPSTART
| OP_TCPWRITE
,
1924 OP_TCPLISW
= OP_TCPLCK
| OP_TCPINIT
| OP_TCPSTART
| OP_TCPWRITE
,
1928 OP_ADDR64VLAN
= OP_ADDR64
| OP_VLAN
,
1930 OP_LRGLENVLAN
= OP_LRGLEN
| OP_VLAN
,
1932 OP_MSSVLAN
= OP_MSS
| OP_VLAN
,
1936 OP_LARGESEND
= 0x43,
1939 /* YUKON-2 STATUS opcodes defines */
1941 OP_RXTIMESTAMP
= 0x61,
1944 OP_RXCHKSVLAN
= OP_RXCHKS
| OP_RXVLAN
,
1945 OP_RXTIMEVLAN
= OP_RXTIMESTAMP
| OP_RXVLAN
,
1947 OP_TXINDEXLE
= 0x68,
1953 CSS_TCPUDPCSOK
= 1<<7, /* TCP / UDP checksum is ok */
1954 CSS_ISUDP
= 1<<6, /* packet is a UDP packet */
1955 CSS_ISTCP
= 1<<5, /* packet is a TCP packet */
1956 CSS_ISIPFRAG
= 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
1957 CSS_ISIPV6
= 1<<3, /* packet is a IPv6 packet */
1958 CSS_IPV4CSUMOK
= 1<<2, /* IP v4: TCP header checksum is ok */
1959 CSS_ISIPV4
= 1<<1, /* packet is a IPv4 packet */
1960 CSS_LINK_BIT
= 1<<0, /* port number (legacy) */
1963 /* Yukon 2 hardware interface */
1966 __le16 length
; /* also vlan tag or checksum start */
1969 } __attribute((packed
));
1976 } __attribute((packed
));
1978 struct sky2_status_le
{
1979 __le32 status
; /* also checksum */
1980 __le16 length
; /* also vlan tag */
1983 } __attribute((packed
));
1985 struct tx_ring_info
{
1986 struct sk_buff
*skb
;
1987 DECLARE_PCI_UNMAP_ADDR(mapaddr
);
1988 DECLARE_PCI_UNMAP_LEN(maplen
);
1991 struct rx_ring_info
{
1992 struct sk_buff
*skb
;
1993 dma_addr_t data_addr
;
1994 DECLARE_PCI_UNMAP_LEN(data_size
);
1995 dma_addr_t frag_addr
[ETH_JUMBO_MTU
>> PAGE_SHIFT
];
2007 struct net_device
*netdev
;
2010 spinlock_t phy_lock
;
2012 struct tx_ring_info
*tx_ring
;
2013 struct sky2_tx_le
*tx_le
;
2015 u16 tx_cons
; /* next le to check */
2016 u16 tx_prod
; /* next le to use */
2017 u16 tx_next
; /* debug only */
2024 struct rx_ring_info
*rx_ring ____cacheline_aligned_in_smp
;
2025 struct sky2_rx_le
*rx_le
;
2027 u16 rx_next
; /* next re to check */
2028 u16 rx_put
; /* next le index to use */
2032 struct sk_buff_head rx_recycle
;
2034 #ifdef SKY2_VLAN_TAG_USED
2036 struct vlan_group
*vlgrp
;
2046 dma_addr_t rx_le_map
;
2047 dma_addr_t tx_le_map
;
2049 u16 advertising
; /* ADVERTISED_ bits */
2050 u16 speed
; /* SPEED_1000, SPEED_100, ... */
2051 u8 wol
; /* WAKE_ bits */
2052 u8 duplex
; /* DUPLEX_HALF, DUPLEX_FULL */
2054 #define SKY2_FLAG_RX_CHECKSUM 0x0001
2055 #define SKY2_FLAG_AUTO_SPEED 0x0002
2056 #define SKY2_FLAG_AUTO_PAUSE 0x0004
2058 enum flow_control flow_mode
;
2059 enum flow_control flow_status
;
2061 #ifdef CONFIG_SKY2_DEBUG
2062 struct dentry
*debugfs
;
2068 struct pci_dev
*pdev
;
2069 struct napi_struct napi
;
2070 struct net_device
*dev
[2];
2071 unsigned long flags
;
2072 #define SKY2_HW_USE_MSI 0x00000001
2073 #define SKY2_HW_FIBRE_PHY 0x00000002
2074 #define SKY2_HW_GIGABIT 0x00000004
2075 #define SKY2_HW_NEWER_PHY 0x00000008
2076 #define SKY2_HW_RAM_BUFFER 0x00000010
2077 #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
2078 #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2079 #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
2086 struct sky2_status_le
*st_le
;
2090 struct timer_list watchdog_timer
;
2091 struct work_struct restart_work
;
2092 wait_queue_head_t msi_wait
;
2095 static inline int sky2_is_copper(const struct sky2_hw
*hw
)
2097 return !(hw
->flags
& SKY2_HW_FIBRE_PHY
);
2100 /* Register accessor for memory mapped device */
2101 static inline u32
sky2_read32(const struct sky2_hw
*hw
, unsigned reg
)
2103 return readl(hw
->regs
+ reg
);
2106 static inline u16
sky2_read16(const struct sky2_hw
*hw
, unsigned reg
)
2108 return readw(hw
->regs
+ reg
);
2111 static inline u8
sky2_read8(const struct sky2_hw
*hw
, unsigned reg
)
2113 return readb(hw
->regs
+ reg
);
2116 static inline void sky2_write32(const struct sky2_hw
*hw
, unsigned reg
, u32 val
)
2118 writel(val
, hw
->regs
+ reg
);
2121 static inline void sky2_write16(const struct sky2_hw
*hw
, unsigned reg
, u16 val
)
2123 writew(val
, hw
->regs
+ reg
);
2126 static inline void sky2_write8(const struct sky2_hw
*hw
, unsigned reg
, u8 val
)
2128 writeb(val
, hw
->regs
+ reg
);
2131 /* Yukon PHY related registers */
2132 #define SK_GMAC_REG(port,reg) \
2133 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2134 #define GM_PHY_RETRIES 100
2136 static inline u16
gma_read16(const struct sky2_hw
*hw
, unsigned port
, unsigned reg
)
2138 return sky2_read16(hw
, SK_GMAC_REG(port
,reg
));
2141 static inline u32
gma_read32(struct sky2_hw
*hw
, unsigned port
, unsigned reg
)
2143 unsigned base
= SK_GMAC_REG(port
, reg
);
2144 return (u32
) sky2_read16(hw
, base
)
2145 | (u32
) sky2_read16(hw
, base
+4) << 16;
2148 static inline void gma_write16(const struct sky2_hw
*hw
, unsigned port
, int r
, u16 v
)
2150 sky2_write16(hw
, SK_GMAC_REG(port
,r
), v
);
2153 static inline void gma_set_addr(struct sky2_hw
*hw
, unsigned port
, unsigned reg
,
2156 gma_write16(hw
, port
, reg
, (u16
) addr
[0] | ((u16
) addr
[1] << 8));
2157 gma_write16(hw
, port
, reg
+4,(u16
) addr
[2] | ((u16
) addr
[3] << 8));
2158 gma_write16(hw
, port
, reg
+8,(u16
) addr
[4] | ((u16
) addr
[5] << 8));
2161 /* PCI config space access */
2162 static inline u32
sky2_pci_read32(const struct sky2_hw
*hw
, unsigned reg
)
2164 return sky2_read32(hw
, Y2_CFG_SPC
+ reg
);
2167 static inline u16
sky2_pci_read16(const struct sky2_hw
*hw
, unsigned reg
)
2169 return sky2_read16(hw
, Y2_CFG_SPC
+ reg
);
2172 static inline void sky2_pci_write32(struct sky2_hw
*hw
, unsigned reg
, u32 val
)
2174 sky2_write32(hw
, Y2_CFG_SPC
+ reg
, val
);
2177 static inline void sky2_pci_write16(struct sky2_hw
*hw
, unsigned reg
, u16 val
)
2179 sky2_write16(hw
, Y2_CFG_SPC
+ reg
, val
);