projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.h
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */
8
9 /* PCI config registers */
10 enum {
11 PCI_DEV_REG1 = 0x40,
12 PCI_DEV_REG2 = 0x44,
13 PCI_DEV_STATUS = 0x7c,
14 PCI_DEV_REG3 = 0x80,
15 PCI_DEV_REG4 = 0x84,
16 PCI_DEV_REG5 = 0x88,
17 PCI_CFG_REG_0 = 0x90,
18 PCI_CFG_REG_1 = 0x94,
19 };
20
21 enum {
22 PEX_DEV_CAP = 0xe4,
23 PEX_DEV_CTRL = 0xe8,
24 PEX_DEV_STA = 0xea,
25 PEX_LNK_STAT = 0xf2,
26 PEX_UNC_ERR_STAT= 0x104,
27 };
28
29 /* Yukon-2 */
30 enum pci_dev_reg_1 {
31 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
32 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
33 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
34 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
35 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
37 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
38 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
39 };
40
41 enum pci_dev_reg_2 {
42 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
43 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
44 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
45
46 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
47 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
48 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
49 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
50
51 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
52 };
53
54 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
55 enum pci_dev_reg_4 {
56 /* (Link Training & Status State Machine) */
57 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
58 /* (Active State Power Management) */
59 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
60 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
61 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
62 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
63
64 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
65 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
66 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
67 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
68 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
69 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
70 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
71 };
72
73 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
74 enum pci_dev_reg_5 {
75 /* Bit 31..27: for A3 & later */
76 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
77 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
78 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
79 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
80 /* Bit 26..16: Release Clock on Event */
81 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
82 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
83 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
84 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
85 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
86 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
87 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
88 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
89 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
90 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
91 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
92
93 /* Bit 10.. 0: Mask for Gate Clock */
94 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
95 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
96 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
97 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
98 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
99 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
100 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
101 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
102 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
103 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
104 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
105
106 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
107 P_REL_INT_FIFO_N_EMPTY |
108 P_REL_PCIE_EXIT_L1_ST |
109 P_REL_PCIE_RX_EX_IDLE |
110 P_GAT_GPHY_N_REC_PACKET |
111 P_GAT_INT_FIFO_EMPTY |
112 P_GAT_PCIE_ENTER_L1_ST |
113 P_GAT_PCIE_RX_EL_IDLE,
114 };
115
116 #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
117 enum pci_cfg_reg1 {
118 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
119 /* Bit 23..21: Release Clock on Event */
120 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
121 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
122 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
123 /* Bit 20..18: Gate Clock on Event */
124 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
125 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
126 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
127 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
128 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
129
130 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
131
132 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
133 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
134
135 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
136 P_CF1_REL_LDR_NOT_FIN |
137 P_CF1_REL_VMAIN_AVLBL |
138 P_CF1_REL_PCIE_RESET |
139 P_CF1_GAT_LDR_NOT_FIN |
140 P_CF1_GAT_PCIE_RESET |
141 P_CF1_PRST_PHY_CLKREQ |
142 P_CF1_ENA_CFG_LDR_DONE |
143 P_CF1_ENA_TXBMU_RD_IDLE |
144 P_CF1_ENA_TXBMU_WR_IDLE,
145 };
146
147
148 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
149 PCI_STATUS_SIG_SYSTEM_ERROR | \
150 PCI_STATUS_REC_MASTER_ABORT | \
151 PCI_STATUS_REC_TARGET_ABORT | \
152 PCI_STATUS_PARITY)
153
154 enum pex_dev_ctrl {
155 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
156 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
157 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
158 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
159 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
160 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
161 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
162 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
163 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
164 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
165 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
166 };
167 #define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
168
169 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
170 enum pex_err {
171 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
172
173 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
174
175 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
176
177 PEX_COMP_TO = 1<<14, /* Completion Timeout */
178 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
179 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
180
181 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
182 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
183 };
184
185
186 enum csr_regs {
187 B0_RAP = 0x0000,
188 B0_CTST = 0x0004,
189 B0_Y2LED = 0x0005,
190 B0_POWER_CTRL = 0x0007,
191 B0_ISRC = 0x0008,
192 B0_IMSK = 0x000c,
193 B0_HWE_ISRC = 0x0010,
194 B0_HWE_IMSK = 0x0014,
195
196 /* Special ISR registers (Yukon-2 only) */
197 B0_Y2_SP_ISRC2 = 0x001c,
198 B0_Y2_SP_ISRC3 = 0x0020,
199 B0_Y2_SP_EISR = 0x0024,
200 B0_Y2_SP_LISR = 0x0028,
201 B0_Y2_SP_ICR = 0x002c,
202
203 B2_MAC_1 = 0x0100,
204 B2_MAC_2 = 0x0108,
205 B2_MAC_3 = 0x0110,
206 B2_CONN_TYP = 0x0118,
207 B2_PMD_TYP = 0x0119,
208 B2_MAC_CFG = 0x011a,
209 B2_CHIP_ID = 0x011b,
210 B2_E_0 = 0x011c,
211
212 B2_Y2_CLK_GATE = 0x011d,
213 B2_Y2_HW_RES = 0x011e,
214 B2_E_3 = 0x011f,
215 B2_Y2_CLK_CTRL = 0x0120,
216
217 B2_TI_INI = 0x0130,
218 B2_TI_VAL = 0x0134,
219 B2_TI_CTRL = 0x0138,
220 B2_TI_TEST = 0x0139,
221
222 B2_TST_CTRL1 = 0x0158,
223 B2_TST_CTRL2 = 0x0159,
224 B2_GP_IO = 0x015c,
225
226 B2_I2C_CTRL = 0x0160,
227 B2_I2C_DATA = 0x0164,
228 B2_I2C_IRQ = 0x0168,
229 B2_I2C_SW = 0x016c,
230
231 B3_RAM_ADDR = 0x0180,
232 B3_RAM_DATA_LO = 0x0184,
233 B3_RAM_DATA_HI = 0x0188,
234
235 /* RAM Interface Registers */
236 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
237 /*
238 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
239 * not usable in SW. Please notice these are NOT real timeouts, these are
240 * the number of qWords transferred continuously.
241 */
242 #define RAM_BUFFER(port, reg) (reg | (port <<6))
243
244 B3_RI_WTO_R1 = 0x0190,
245 B3_RI_WTO_XA1 = 0x0191,
246 B3_RI_WTO_XS1 = 0x0192,
247 B3_RI_RTO_R1 = 0x0193,
248 B3_RI_RTO_XA1 = 0x0194,
249 B3_RI_RTO_XS1 = 0x0195,
250 B3_RI_WTO_R2 = 0x0196,
251 B3_RI_WTO_XA2 = 0x0197,
252 B3_RI_WTO_XS2 = 0x0198,
253 B3_RI_RTO_R2 = 0x0199,
254 B3_RI_RTO_XA2 = 0x019a,
255 B3_RI_RTO_XS2 = 0x019b,
256 B3_RI_TO_VAL = 0x019c,
257 B3_RI_CTRL = 0x01a0,
258 B3_RI_TEST = 0x01a2,
259 B3_MA_TOINI_RX1 = 0x01b0,
260 B3_MA_TOINI_RX2 = 0x01b1,
261 B3_MA_TOINI_TX1 = 0x01b2,
262 B3_MA_TOINI_TX2 = 0x01b3,
263 B3_MA_TOVAL_RX1 = 0x01b4,
264 B3_MA_TOVAL_RX2 = 0x01b5,
265 B3_MA_TOVAL_TX1 = 0x01b6,
266 B3_MA_TOVAL_TX2 = 0x01b7,
267 B3_MA_TO_CTRL = 0x01b8,
268 B3_MA_TO_TEST = 0x01ba,
269 B3_MA_RCINI_RX1 = 0x01c0,
270 B3_MA_RCINI_RX2 = 0x01c1,
271 B3_MA_RCINI_TX1 = 0x01c2,
272 B3_MA_RCINI_TX2 = 0x01c3,
273 B3_MA_RCVAL_RX1 = 0x01c4,
274 B3_MA_RCVAL_RX2 = 0x01c5,
275 B3_MA_RCVAL_TX1 = 0x01c6,
276 B3_MA_RCVAL_TX2 = 0x01c7,
277 B3_MA_RC_CTRL = 0x01c8,
278 B3_MA_RC_TEST = 0x01ca,
279 B3_PA_TOINI_RX1 = 0x01d0,
280 B3_PA_TOINI_RX2 = 0x01d4,
281 B3_PA_TOINI_TX1 = 0x01d8,
282 B3_PA_TOINI_TX2 = 0x01dc,
283 B3_PA_TOVAL_RX1 = 0x01e0,
284 B3_PA_TOVAL_RX2 = 0x01e4,
285 B3_PA_TOVAL_TX1 = 0x01e8,
286 B3_PA_TOVAL_TX2 = 0x01ec,
287 B3_PA_CTRL = 0x01f0,
288 B3_PA_TEST = 0x01f2,
289
290 Y2_CFG_SPC = 0x1c00,
291 };
292
293 /* B0_CTST 16 bit Control/Status register */
294 enum {
295 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
296 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
297 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
298 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
299 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
300 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
301 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
302 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
303 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
304 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
305
306 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
307 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
308 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
309 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
310 CS_MRST_CLR = 1<<3, /* Clear Master reset */
311 CS_MRST_SET = 1<<2, /* Set Master reset */
312 CS_RST_CLR = 1<<1, /* Clear Software reset */
313 CS_RST_SET = 1, /* Set Software reset */
314 };
315
316 /* B0_LED 8 Bit LED register */
317 enum {
318 /* Bit 7.. 2: reserved */
319 LED_STAT_ON = 1<<1, /* Status LED on */
320 LED_STAT_OFF = 1, /* Status LED off */
321 };
322
323 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
324 enum {
325 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
326 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
327 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
328 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
329 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
330 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
331 PC_VCC_ON = 1<<1, /* Switch VCC On */
332 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
333 };
334
335 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
336
337 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
338 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
339 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
340 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
341 enum {
342 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
343 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
344 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
345
346 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
347 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
348 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
349 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
350
351 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
352 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
353 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
354 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
355 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
356
357 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
358 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
359 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
360 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
361 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
362
363 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
364 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
365 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
366 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
367 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
368 Y2_IS_ERROR = Y2_IS_HW_ERR |
369 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
370 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
371 };
372
373 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
374 enum {
375 IS_ERR_MSK = 0x00003fff,/* All Error bits */
376
377 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
378 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
379 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
380 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
381 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
382 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
383 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
384 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
385 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
386 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
387 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
388 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
389 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
390 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
391 };
392
393 /* Hardware error interrupt mask for Yukon 2 */
394 enum {
395 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
396 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
397 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
398 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
399 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
400 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
401 /* Link 2 */
402 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
403 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
404 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
405 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
406 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
407 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
408 /* Link 1 */
409 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
410 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
411 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
412 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
413 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
414 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
415
416 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
417 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
418 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
419 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
420
421 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
422 Y2_IS_PCI_EXP |
423 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
424 };
425
426 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
427 enum {
428 DPT_START = 1<<1,
429 DPT_STOP = 1<<0,
430 };
431
432 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
433 enum {
434 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
435 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
436 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
437 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
438 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
439 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
440 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
441 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
442 };
443
444 /* B2_GPIO */
445 enum {
446 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
447 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
448
449 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
450 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
451 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
452 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
453 GLB_GPIO_TEST_SEL_BASE = 1<<11,
454 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
455 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
456 };
457
458 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
459 enum {
460 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
461 /* Bit 3.. 2: reserved */
462 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
463 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
464 };
465
466 /* B2_CHIP_ID 8 bit Chip Identification Number */
467 enum {
468 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
469 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
470 CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */
471 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
472 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
473 CHIP_ID_YUKON_FE_P = 0xb8, /* Chip ID for YUKON-2 FE+ */
474 };
475 enum yukon_ec_rev {
476 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
477 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
478 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
479 };
480 enum yukon_ec_u_rev {
481 CHIP_REV_YU_EC_U_A0 = 1,
482 CHIP_REV_YU_EC_U_A1 = 2,
483 CHIP_REV_YU_EC_U_B0 = 3,
484 };
485 enum yukon_fe_rev {
486 CHIP_REV_YU_FE_A1 = 1,
487 CHIP_REV_YU_FE_A2 = 2,
488 };
489 enum yukon_fe_p_rev {
490 CHIP_REV_YU_FE2_A0 = 0,
491 };
492 enum yukon_ex_rev {
493 CHIP_REV_YU_EX_A0 = 1,
494 CHIP_REV_YU_EX_B0 = 2,
495 };
496
497
498 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
499 enum {
500 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
501 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
502 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
503 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
504 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
505 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
506 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
507 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
508 };
509
510 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
511 enum {
512 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
513 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
514 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
515 };
516 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
517 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
518
519
520 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
521 enum {
522 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
523 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
524 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
525 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
526 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
527 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
528 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
529 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
530 };
531
532 /* B2_TI_CTRL 8 bit Timer control */
533 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
534 enum {
535 TIM_START = 1<<2, /* Start Timer */
536 TIM_STOP = 1<<1, /* Stop Timer */
537 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
538 };
539
540 /* B2_TI_TEST 8 Bit Timer Test */
541 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
542 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
543 enum {
544 TIM_T_ON = 1<<2, /* Test mode on */
545 TIM_T_OFF = 1<<1, /* Test mode off */
546 TIM_T_STEP = 1<<0, /* Test step */
547 };
548
549 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
550 /* Bit 31..19: reserved */
551 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
552 /* RAM Interface Registers */
553
554 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
555 enum {
556 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
557 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
558
559 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
560 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
561 };
562
563 #define SK_RI_TO_53 36 /* RAM interface timeout */
564
565
566 /* Port related registers FIFO, and Arbiter */
567 #define SK_REG(port,reg) (((port)<<7)+(reg))
568
569 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
570 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
571 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
572 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
573 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
574
575 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
576
577 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
578 enum {
579 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
580 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
581 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
582 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
583 TXA_START_RC = 1<<3, /* Start sync Rate Control */
584 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
585 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
586 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
587 };
588
589 /*
590 * Bank 4 - 5
591 */
592 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
593 enum {
594 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
595 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
596 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
597 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
598 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
599 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
600 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
601 };
602
603
604 enum {
605 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
606 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
607 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
608 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
609 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
610 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
611 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
612 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
613 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
614 };
615
616 /* Queue Register Offsets, use Q_ADDR() to access */
617 enum {
618 B8_Q_REGS = 0x0400, /* base of Queue registers */
619 Q_D = 0x00, /* 8*32 bit Current Descriptor */
620 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
621 Q_DONE = 0x24, /* 16 bit Done Index */
622 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
623 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
624 Q_BC = 0x30, /* 32 bit Current Byte Counter */
625 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
626 Q_TEST = 0x38, /* 32 bit Test/Control Register */
627
628 /* Yukon-2 */
629 Q_WM = 0x40, /* 16 bit FIFO Watermark */
630 Q_AL = 0x42, /* 8 bit FIFO Alignment */
631 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
632 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
633 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
634 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
635 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
636 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
637 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
638 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
639 };
640 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
641
642 /* Q_TEST 32 bit Test Register */
643 enum {
644 /* Transmit */
645 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
646 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
647
648 /* Receive */
649 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
650
651 /* Hardware testbits not used */
652 };
653
654 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
655 enum {
656 Y2_B8_PREF_REGS = 0x0450,
657
658 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
659 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
660 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
661 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
662 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
663 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
664 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
665 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
666 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
667 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
668
669 PREF_UNIT_MASK_IDX = 0x0fff,
670 };
671 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
672
673 /* RAM Buffer Register Offsets */
674 enum {
675
676 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
677 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
678 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
679 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
680 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
681 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
682 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
683 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
684 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
685 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
686 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
687 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
688 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
689 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
690 };
691
692 /* Receive and Transmit Queues */
693 enum {
694 Q_R1 = 0x0000, /* Receive Queue 1 */
695 Q_R2 = 0x0080, /* Receive Queue 2 */
696 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
697 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
698 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
699 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
700 };
701
702 /* Different PHY Types */
703 enum {
704 PHY_ADDR_MARV = 0,
705 };
706
707 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
708
709
710 enum {
711 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
712 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
713 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
714 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
715
716 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
717
718 /* Receive GMAC FIFO (YUKON and Yukon-2) */
719
720 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
721 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
722 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
723 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
724 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
725 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
726 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
727 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
728 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
729 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
730
731 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
732
733 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
734
735 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
736 };
737
738
739 /* Q_BC 32 bit Current Byte Counter */
740
741 /* BMU Control Status Registers */
742 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
743 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
744 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
745 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
746 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
747 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
748 /* Q_CSR 32 bit BMU Control/Status Register */
749
750 /* Rx BMU Control / Status Registers (Yukon-2) */
751 enum {
752 BMU_IDLE = 1<<31, /* BMU Idle State */
753 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
754 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
755
756 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
757 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
758 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
759 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
760 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
761 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
762 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
763 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
764 BMU_START = 1<<8, /* Start Rx/Tx Queue */
765 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
766 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
767 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
768 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
769 BMU_OP_ON = 1<<3, /* BMU Operational On */
770 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
771 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
772 BMU_RST_SET = 1<<0, /* Set BMU Reset */
773
774 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
775 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
776 BMU_FIFO_ENA | BMU_OP_ON,
777
778 BMU_WM_DEFAULT = 0x600,
779 BMU_WM_PEX = 0x80,
780 };
781
782 /* Tx BMU Control / Status Registers (Yukon-2) */
783 /* Bit 31: same as for Rx */
784 enum {
785 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
786 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
787 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
788 };
789
790 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
791 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
792 enum {
793 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
794 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
795 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
796 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
797 };
798
799 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
800 /* RB_START 32 bit RAM Buffer Start Address */
801 /* RB_END 32 bit RAM Buffer End Address */
802 /* RB_WP 32 bit RAM Buffer Write Pointer */
803 /* RB_RP 32 bit RAM Buffer Read Pointer */
804 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
805 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
806 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
807 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
808 /* RB_PC 32 bit RAM Buffer Packet Counter */
809 /* RB_LEV 32 bit RAM Buffer Level Register */
810
811 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
812 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
813 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
814
815 /* RB_CTRL 8 bit RAM Buffer Control Register */
816 enum {
817 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
818 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
819 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
820 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
821 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
822 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
823 };
824
825
826 /* Transmit GMAC FIFO (YUKON only) */
827 enum {
828 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
829 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
830 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
831
832 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
833 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
834 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
835
836 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
837 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
838 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
839
840 /* Threshold values for Yukon-EC Ultra and Extreme */
841 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
842 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
843 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
844 };
845
846 /* Descriptor Poll Timer Registers */
847 enum {
848 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
849 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
850 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
851
852 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
853 };
854
855 /* Time Stamp Timer Registers (YUKON only) */
856 enum {
857 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
858 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
859 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
860 };
861
862 /* Polling Unit Registers (Yukon-2 only) */
863 enum {
864 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
865 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
866
867 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
868 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
869 };
870
871 enum {
872 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
873 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
874 };
875
876 enum {
877 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
878 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
879 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
880 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
881 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
882 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
883 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
884 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
885 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
886 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
887 };
888
889 /* ASF Subsystem Registers (Yukon-2 only) */
890 enum {
891 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
892 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
893 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
894
895 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
896 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
897 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
898 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
899 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
900 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
901 };
902
903 /* Status BMU Registers (Yukon-2 only)*/
904 enum {
905 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
906 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
907
908 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
909 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
910 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
911 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
912 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
913 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
914 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
915 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
916
917 /* FIFO Control/Status Registers (Yukon-2 only)*/
918 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
919 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
920 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
921 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
922 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
923 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
924 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
925
926 /* Level and ISR Timer Registers (Yukon-2 only)*/
927 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
928 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
929 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
930 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
931 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
932 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
933 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
934 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
935 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
936 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
937 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
938 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
939 };
940
941 enum {
942 LINKLED_OFF = 0x01,
943 LINKLED_ON = 0x02,
944 LINKLED_LINKSYNC_OFF = 0x04,
945 LINKLED_LINKSYNC_ON = 0x08,
946 LINKLED_BLINK_OFF = 0x10,
947 LINKLED_BLINK_ON = 0x20,
948 };
949
950 /* GMAC and GPHY Control Registers (YUKON only) */
951 enum {
952 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
953 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
954 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
955 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
956 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
957
958 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
959 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
960 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
961 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
962 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
963 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
964
965 /* WOL Pattern Length Registers (YUKON only) */
966 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
967 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
968
969 /* WOL Pattern Counter Registers (YUKON only) */
970 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
971 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
972 };
973 #define WOL_REGS(port, x) (x + (port)*0x80)
974
975 enum {
976 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
977 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
978 };
979 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
980
981 enum {
982 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
983 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
984 };
985
986 /*
987 * Marvel-PHY Registers, indirect addressed over GMAC
988 */
989 enum {
990 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
991 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
992 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
993 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
994 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
995 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
996 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
997 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
998 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
999 /* Marvel-specific registers */
1000 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1001 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1002 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1003 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1004 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1005 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1006 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1007 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1008 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1009 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1010 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1011 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1012 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1013 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1014 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1015 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1016 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1017 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1018
1019 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1020 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1021 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1022 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1023 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1024 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1025 };
1026
1027 enum {
1028 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1029 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1030 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1031 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1032 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1033 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1034 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1035 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1036 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1037 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1038 };
1039
1040 enum {
1041 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1042 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1043 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1044 };
1045
1046 enum {
1047 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1048
1049 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1050 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1051 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1052 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1053 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1054 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1055 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1056 };
1057
1058 enum {
1059 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1060 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1061 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1062 };
1063
1064 /* different Marvell PHY Ids */
1065 enum {
1066 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1067
1068 PHY_BCOM_ID1_A1 = 0x6041,
1069 PHY_BCOM_ID1_B2 = 0x6043,
1070 PHY_BCOM_ID1_C0 = 0x6044,
1071 PHY_BCOM_ID1_C5 = 0x6047,
1072
1073 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1074 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1075 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1076 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1077 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1078 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1079 };
1080
1081 /* Advertisement register bits */
1082 enum {
1083 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1084 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1085 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1086
1087 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1088 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1089 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1090 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1091 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1092 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1093 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1094 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1095 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1096 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1097 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1098 PHY_AN_100HALF | PHY_AN_100FULL,
1099 };
1100
1101 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1102 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1103 enum {
1104 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1105 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1106 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1107 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1108 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1109 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1110 /* Bit 9..8: reserved */
1111 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1112 };
1113
1114 /** Marvell-Specific */
1115 enum {
1116 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1117 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1118 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1119
1120 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1121 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1122 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1123 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1124 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1125 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1126 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1127 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1128 };
1129
1130 /* special defines for FIBER (88E1011S only) */
1131 enum {
1132 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1133 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1134 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1135 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1136 };
1137
1138 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1139 enum {
1140 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1141 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1142 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1143 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1144 };
1145
1146 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1147 enum {
1148 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1149 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1150 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1151 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1152 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1153 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1154 };
1155
1156 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1157 enum {
1158 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1159 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1160 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1161 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1162 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1163 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1164 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1165 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1166 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1167 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1168 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1169 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1170 };
1171
1172 enum {
1173 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1174 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1175 };
1176
1177 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1178
1179 enum {
1180 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1181 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1182 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1183 };
1184
1185 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1186 enum {
1187 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1188 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1189 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1190 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1191 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1192
1193 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1194 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1195
1196 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1197 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1198 };
1199
1200 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1201 enum {
1202 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1203 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1204 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1205 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1206 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1207 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1208 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1209 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1210 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1211 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1212 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1213 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1214 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1215 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1216 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1217 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1218 };
1219
1220 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1221
1222 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1223 enum {
1224 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1225 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1226 };
1227
1228 enum {
1229 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1230 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1231 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1232 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1233 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1234 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1235 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1236 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1237 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1238 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1239 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1240 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1241
1242 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1243 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1244 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1245
1246 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1247 | PHY_M_IS_DUP_CHANGE,
1248 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1249 };
1250
1251
1252 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1253 enum {
1254 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1255 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1256
1257 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1258 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1259 /* (88E1011 only) */
1260 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1261 /* (88E1011 only) */
1262 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1263 /* (88E1111 only) */
1264 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1265 /* !!! Errata in spec. (1 = disable) */
1266 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1267 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1268 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1269 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1270 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1271 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1272
1273 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1274 /* 00=1x; 01=2x; 10=3x; 11=4x */
1275 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1276 /* 00=dis; 01=1x; 10=2x; 11=3x */
1277 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1278 /* 000=1x; 001=2x; 010=3x; 011=4x */
1279 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1280 /* 01X=0; 110=2.5; 111=25 (MHz) */
1281
1282 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1283 enum {
1284 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1285 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1286 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1287 };
1288 /* !!! Errata in spec. (1 = disable) */
1289
1290 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1291 /* 100=5x; 101=6x; 110=7x; 111=8x */
1292 enum {
1293 MAC_TX_CLK_0_MHZ = 2,
1294 MAC_TX_CLK_2_5_MHZ = 6,
1295 MAC_TX_CLK_25_MHZ = 7,
1296 };
1297
1298 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1299 enum {
1300 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1301 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1302 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1303 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1304 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1305 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1306 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1307 /* (88E1111 only) */
1308 };
1309
1310 enum {
1311 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1312 /* (88E1011 only) */
1313 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1314 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1315 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1316 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1317 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1318 };
1319
1320 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1321
1322 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1323 enum {
1324 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1325 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1326 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1327 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1328 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1329 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1330 };
1331
1332 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1333 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1334 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1335 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1336 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1337 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1338
1339 enum {
1340 PULS_NO_STR = 0,/* no pulse stretching */
1341 PULS_21MS = 1,/* 21 ms to 42 ms */
1342 PULS_42MS = 2,/* 42 ms to 84 ms */
1343 PULS_84MS = 3,/* 84 ms to 170 ms */
1344 PULS_170MS = 4,/* 170 ms to 340 ms */
1345 PULS_340MS = 5,/* 340 ms to 670 ms */
1346 PULS_670MS = 6,/* 670 ms to 1.3 s */
1347 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1348 };
1349
1350 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1351
1352 enum {
1353 BLINK_42MS = 0,/* 42 ms */
1354 BLINK_84MS = 1,/* 84 ms */
1355 BLINK_170MS = 2,/* 170 ms */
1356 BLINK_340MS = 3,/* 340 ms */
1357 BLINK_670MS = 4,/* 670 ms */
1358 };
1359
1360 /**** PHY_MARV_LED_OVER 16 bit r/w LED control */
1361 enum {
1362 PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */
1363 PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */
1364 PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */
1365 PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */
1366 PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */
1367 PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */
1368
1369 PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10
1370 | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000
1371 | PHY_M_LED_MO_RX,
1372 };
1373
1374 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1375 enum {
1376 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1377 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1378 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1379 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1380 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1381 };
1382
1383 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1384 enum {
1385 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1386 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1387 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1388 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1389 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1390 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1391 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1392 /* (88E1111 only) */
1393
1394 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1395 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1396 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1397 };
1398
1399 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1400 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1401 /* Bit 15..12: reserved (used internally) */
1402 enum {
1403 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1404 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1405 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1406 };
1407
1408 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1409 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1410 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1411
1412 enum {
1413 LED_PAR_CTRL_COLX = 0x00,
1414 LED_PAR_CTRL_ERROR = 0x01,
1415 LED_PAR_CTRL_DUPLEX = 0x02,
1416 LED_PAR_CTRL_DP_COL = 0x03,
1417 LED_PAR_CTRL_SPEED = 0x04,
1418 LED_PAR_CTRL_LINK = 0x05,
1419 LED_PAR_CTRL_TX = 0x06,
1420 LED_PAR_CTRL_RX = 0x07,
1421 LED_PAR_CTRL_ACT = 0x08,
1422 LED_PAR_CTRL_LNK_RX = 0x09,
1423 LED_PAR_CTRL_LNK_AC = 0x0a,
1424 LED_PAR_CTRL_ACT_BL = 0x0b,
1425 LED_PAR_CTRL_TX_BL = 0x0c,
1426 LED_PAR_CTRL_RX_BL = 0x0d,
1427 LED_PAR_CTRL_COL_BL = 0x0e,
1428 LED_PAR_CTRL_INACT = 0x0f
1429 };
1430
1431 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1432 enum {
1433 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1434 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1435 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1436 };
1437
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1439 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1440 enum {
1441 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1442 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1443 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1444 };
1445
1446 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1447 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1448 enum {
1449 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1450 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1451 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1452 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1453 };
1454 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1455
1456 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1457 enum {
1458 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1459 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1460 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1461 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1462 };
1463
1464 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1465 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1466 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1467 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1468
1469 /* GMAC registers */
1470 /* Port Registers */
1471 enum {
1472 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1473 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1474 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1475 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1476 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1477 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1478 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1479 /* Source Address Registers */
1480 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1481 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1482 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1483 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1484 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1485 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1486
1487 /* Multicast Address Hash Registers */
1488 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1489 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1490 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1491 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1492
1493 /* Interrupt Source Registers */
1494 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1495 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1496 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1497
1498 /* Interrupt Mask Registers */
1499 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1500 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1501 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1502
1503 /* Serial Management Interface (SMI) Registers */
1504 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1505 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1506 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1507 /* MIB Counters */
1508 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1509 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1510 };
1511
1512
1513 /*
1514 * MIB Counters base address definitions (low word) -
1515 * use offset 4 for access to high word (32 bit r/o)
1516 */
1517 enum {
1518 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1519 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1520 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1521 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1522 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1523
1524 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1525 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1526 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1527 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1528 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1529 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1530 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1531 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1532 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1533 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1534 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1535 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1536 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1537 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1538 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1539
1540 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1541 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1542 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1543 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1544 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1545 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1546 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1547 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1548 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1549 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1550 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1551 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1552 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1553 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1554
1555 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1556 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1557 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1558 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1559 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1560 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1561 };
1562
1563 /* GMAC Bit Definitions */
1564 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1565 enum {
1566 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1567 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1568 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1569 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1570 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1571 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1572 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1573 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1574
1575 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1576 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1577 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1578 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1579 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1580 };
1581
1582 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1583 enum {
1584 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1585 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1586 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1587 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1588 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1589 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1590 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1591 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1592 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1593 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1594 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1595 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1596 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1597 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1598 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1599 };
1600
1601 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1602 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1603
1604 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1605 enum {
1606 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1607 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1608 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1609 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1610 };
1611
1612 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1613 #define TX_COL_DEF 0x04
1614
1615 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1616 enum {
1617 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1618 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1619 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1620 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1621 };
1622
1623 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1624 enum {
1625 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1626 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1627 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1628 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1629
1630 TX_JAM_LEN_DEF = 0x03,
1631 TX_JAM_IPG_DEF = 0x0b,
1632 TX_IPG_JAM_DEF = 0x1c,
1633 TX_BOF_LIM_DEF = 0x04,
1634 };
1635
1636 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1637 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1638 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1639 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1640
1641
1642 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1643 enum {
1644 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1645 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1646 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1647 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1648 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1649 };
1650
1651 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1652 #define DATA_BLIND_DEF 0x04
1653
1654 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1655 #define IPG_DATA_DEF 0x1e
1656
1657 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1658 enum {
1659 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1660 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1661 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1662 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1663 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1664 };
1665
1666 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1667 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1668
1669 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1670 enum {
1671 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1672 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1673 };
1674
1675 /* Receive Frame Status Encoding */
1676 enum {
1677 GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1678 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1679 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1680 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1681 GMR_FS_MC = 1<<10, /* Multicast Packet */
1682 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1683 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1684 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1685 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1686 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1687 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1688 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1689
1690 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1691 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1692
1693 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1694 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1695 GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1696 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1697 };
1698
1699 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1700 enum {
1701 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1702 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1703 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1704 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1705
1706 RX_MACSEC_FLUSH_ON = 1<<23,
1707 RX_MACSEC_FLUSH_OFF = 1<<22,
1708 RX_MACSEC_ASF_FLUSH_ON = 1<<21,
1709 RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
1710
1711 GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
1712 GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
1713 GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
1714 GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
1715
1716 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1717 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1718 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1719
1720 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1721 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1722 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1723 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1724 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1725 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1726 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1727
1728 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1729 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1730 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1731 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1732
1733 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1734
1735 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1736 };
1737
1738 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1739 enum {
1740 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1741 };
1742
1743 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1744 enum {
1745 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1746 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1747
1748 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1749 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1750
1751 TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1752 TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1753
1754 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1755 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1756 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1757
1758 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1759 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1760 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1761 };
1762
1763 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1764 enum {
1765 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1766 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1767 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1768 };
1769
1770 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1771 enum {
1772 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1773 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1774 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1775 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1776 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1777
1778 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1779 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1780 };
1781
1782 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1783 enum {
1784 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1785 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1786 };
1787 /* HCU_CCSR CPU Control and Status Register */
1788 enum {
1789 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1790 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
1791 /* Clock Stretching Timeout */
1792 HCU_CCSR_CS_TO = 1<<25,
1793 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
1794
1795 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
1796 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
1797
1798 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
1799 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
1800
1801 HCU_CCSR_SET_SYNC_CPU = 1<<5,
1802 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1803 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1804 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
1805 /* Microcontroller State */
1806 HCU_CCSR_UC_STATE_MSK = 3,
1807 HCU_CCSR_UC_STATE_BASE = 1<<0,
1808 HCU_CCSR_ASF_RESET = 0,
1809 HCU_CCSR_ASF_HALTED = 1<<1,
1810 HCU_CCSR_ASF_RUNNING = 1<<0,
1811 };
1812
1813 /* HCU_HCSR Host Control and Status Register */
1814 enum {
1815 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
1816
1817 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
1818 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
1819 };
1820
1821 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1822 enum {
1823 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1824 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1825 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1826 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1827 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1828 };
1829
1830 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1831 enum {
1832 GMC_SET_RST = 1<<15,/* MAC SEC RST */
1833 GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */
1834 GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
1835 GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
1836 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
1837 GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
1838 GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
1839 GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
1840
1841 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1842 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1843 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1844 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1845 GMC_PAUSE_ON = 1<<3, /* Pause On */
1846 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1847 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1848 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1849 };
1850
1851 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1852 enum {
1853 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1854 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1855 };
1856
1857 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1858 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1859 enum {
1860 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1861 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1862 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1863 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1864 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1865 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1866
1867 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1868 };
1869
1870 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1871 enum { /* Bits 15.. 2: reserved */
1872 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1873 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1874 };
1875
1876
1877 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1878 enum {
1879 WOL_CTL_LINK_CHG_OCC = 1<<15,
1880 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1881 WOL_CTL_PATTERN_OCC = 1<<13,
1882 WOL_CTL_CLEAR_RESULT = 1<<12,
1883 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1884 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1885 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1886 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1887 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1888 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1889 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1890 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1891 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1892 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1893 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1894 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1895 };
1896
1897
1898 /* Control flags */
1899 enum {
1900 UDPTCP = 1<<0,
1901 CALSUM = 1<<1,
1902 WR_SUM = 1<<2,
1903 INIT_SUM= 1<<3,
1904 LOCK_SUM= 1<<4,
1905 INS_VLAN= 1<<5,
1906 EOP = 1<<7,
1907 };
1908
1909 enum {
1910 HW_OWNER = 1<<7,
1911 OP_TCPWRITE = 0x11,
1912 OP_TCPSTART = 0x12,
1913 OP_TCPINIT = 0x14,
1914 OP_TCPLCK = 0x18,
1915 OP_TCPCHKSUM = OP_TCPSTART,
1916 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1917 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1918 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1919 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1920
1921 OP_ADDR64 = 0x21,
1922 OP_VLAN = 0x22,
1923 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1924 OP_LRGLEN = 0x24,
1925 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1926 OP_MSS = 0x28,
1927 OP_MSSVLAN = OP_MSS | OP_VLAN,
1928
1929 OP_BUFFER = 0x40,
1930 OP_PACKET = 0x41,
1931 OP_LARGESEND = 0x43,
1932 OP_LSOV2 = 0x45,
1933
1934 /* YUKON-2 STATUS opcodes defines */
1935 OP_RXSTAT = 0x60,
1936 OP_RXTIMESTAMP = 0x61,
1937 OP_RXVLAN = 0x62,
1938 OP_RXCHKS = 0x64,
1939 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1940 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1941 OP_RSS_HASH = 0x65,
1942 OP_TXINDEXLE = 0x68,
1943 OP_MACSEC = 0x6c,
1944 OP_PUTIDX = 0x70,
1945 };
1946
1947 enum status_css {
1948 CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */
1949 CSS_ISUDP = 1<<6, /* packet is a UDP packet */
1950 CSS_ISTCP = 1<<5, /* packet is a TCP packet */
1951 CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
1952 CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */
1953 CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */
1954 CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */
1955 CSS_LINK_BIT = 1<<0, /* port number (legacy) */
1956 };
1957
1958 /* Yukon 2 hardware interface */
1959 struct sky2_tx_le {
1960 __le32 addr;
1961 __le16 length; /* also vlan tag or checksum start */
1962 u8 ctrl;
1963 u8 opcode;
1964 } __attribute((packed));
1965
1966 struct sky2_rx_le {
1967 __le32 addr;
1968 __le16 length;
1969 u8 ctrl;
1970 u8 opcode;
1971 } __attribute((packed));
1972
1973 struct sky2_status_le {
1974 __le32 status; /* also checksum */
1975 __le16 length; /* also vlan tag */
1976 u8 css;
1977 u8 opcode;
1978 } __attribute((packed));
1979
1980 struct tx_ring_info {
1981 struct sk_buff *skb;
1982 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1983 DECLARE_PCI_UNMAP_ADDR(maplen);
1984 };
1985
1986 struct rx_ring_info {
1987 struct sk_buff *skb;
1988 dma_addr_t data_addr;
1989 DECLARE_PCI_UNMAP_ADDR(data_size);
1990 dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
1991 };
1992
1993 enum flow_control {
1994 FC_NONE = 0,
1995 FC_TX = 1,
1996 FC_RX = 2,
1997 FC_BOTH = 3,
1998 };
1999
2000 struct sky2_port {
2001 struct sky2_hw *hw;
2002 struct net_device *netdev;
2003 unsigned port;
2004 u32 msg_enable;
2005 spinlock_t phy_lock;
2006
2007 struct tx_ring_info *tx_ring;
2008 struct sky2_tx_le *tx_le;
2009 u16 tx_cons; /* next le to check */
2010 u16 tx_prod; /* next le to use */
2011 u16 tx_next; /* debug only */
2012 u32 tx_addr64;
2013 u16 tx_pending;
2014 u16 tx_last_mss;
2015 u32 tx_tcpsum;
2016
2017 struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp;
2018 struct sky2_rx_le *rx_le;
2019 u32 rx_addr64;
2020 u16 rx_next; /* next re to check */
2021 u16 rx_put; /* next le index to use */
2022 u16 rx_pending;
2023 u16 rx_data_size;
2024 u16 rx_nfrags;
2025
2026 #ifdef SKY2_VLAN_TAG_USED
2027 u16 rx_tag;
2028 struct vlan_group *vlgrp;
2029 #endif
2030 struct {
2031 unsigned long last;
2032 u32 mac_rp;
2033 u8 mac_lev;
2034 u8 fifo_rp;
2035 u8 fifo_lev;
2036 } check;
2037
2038
2039 dma_addr_t rx_le_map;
2040 dma_addr_t tx_le_map;
2041 u16 advertising; /* ADVERTISED_ bits */
2042 u16 speed; /* SPEED_1000, SPEED_100, ... */
2043 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2044 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2045 u8 rx_csum;
2046 u8 wol;
2047 enum flow_control flow_mode;
2048 enum flow_control flow_status;
2049
2050 #ifdef CONFIG_SKY2_DEBUG
2051 struct dentry *debugfs;
2052 #endif
2053 struct net_device_stats net_stats;
2054
2055 };
2056
2057 struct sky2_hw {
2058 void __iomem *regs;
2059 struct pci_dev *pdev;
2060 struct net_device *dev[2];
2061 unsigned long flags;
2062 #define SKY2_HW_USE_MSI 0x00000001
2063 #define SKY2_HW_FIBRE_PHY 0x00000002
2064 #define SKY2_HW_GIGABIT 0x00000004
2065 #define SKY2_HW_NEWER_PHY 0x00000008
2066 #define SKY2_HW_RAMBUFFER 0x00000010 /* chip has RAM FIFO */
2067 #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
2068 #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2069 #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
2070
2071 u8 chip_id;
2072 u8 chip_rev;
2073 u8 pmd_type;
2074 u8 ports;
2075
2076 struct sky2_status_le *st_le;
2077 u32 st_idx;
2078 dma_addr_t st_dma;
2079
2080 struct timer_list watchdog_timer;
2081 struct work_struct restart_work;
2082 wait_queue_head_t msi_wait;
2083 };
2084
2085 static inline int sky2_is_copper(const struct sky2_hw *hw)
2086 {
2087 return !(hw->flags & SKY2_HW_FIBRE_PHY);
2088 }
2089
2090 /* Register accessor for memory mapped device */
2091 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2092 {
2093 return readl(hw->regs + reg);
2094 }
2095
2096 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2097 {
2098 return readw(hw->regs + reg);
2099 }
2100
2101 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2102 {
2103 return readb(hw->regs + reg);
2104 }
2105
2106 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2107 {
2108 writel(val, hw->regs + reg);
2109 }
2110
2111 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2112 {
2113 writew(val, hw->regs + reg);
2114 }
2115
2116 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2117 {
2118 writeb(val, hw->regs + reg);
2119 }
2120
2121 /* Yukon PHY related registers */
2122 #define SK_GMAC_REG(port,reg) \
2123 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2124 #define GM_PHY_RETRIES 100
2125
2126 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2127 {
2128 return sky2_read16(hw, SK_GMAC_REG(port,reg));
2129 }
2130
2131 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2132 {
2133 unsigned base = SK_GMAC_REG(port, reg);
2134 return (u32) sky2_read16(hw, base)
2135 | (u32) sky2_read16(hw, base+4) << 16;
2136 }
2137
2138 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
2139 {
2140 sky2_write16(hw, SK_GMAC_REG(port,r), v);
2141 }
2142
2143 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2144 const u8 *addr)
2145 {
2146 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2147 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2148 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2149 }
2150
2151 /* PCI config space access */
2152 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2153 {
2154 return sky2_read32(hw, Y2_CFG_SPC + reg);
2155 }
2156
2157 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2158 {
2159 return sky2_read16(hw, Y2_CFG_SPC + reg);
2160 }
2161
2162 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2163 {
2164 sky2_write32(hw, Y2_CFG_SPC + reg, val);
2165 }
2166
2167 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2168 {
2169 sky2_write16(hw, Y2_CFG_SPC + reg, val);
2170 }
2171 #endif
kernel source for telekom puls (alcatel/mediatek)