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[PATCH] sky2: use standard pci register capabilties for error register
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.7"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
132 { 0 }
133 };
134
135 MODULE_DEVICE_TABLE(pci, sky2_id_table);
136
137 /* Avoid conditionals by using array */
138 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
140 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
141
142 /* This driver supports yukon2 chipset only */
143 static const char *yukon2_name[] = {
144 "XL", /* 0xb3 */
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
147 "EC", /* 0xb6 */
148 "FE", /* 0xb7 */
149 };
150
151 /* Access to external PHY */
152 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
153 {
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
162 return 0;
163 udelay(1);
164 }
165
166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
167 return -ETIMEDOUT;
168 }
169
170 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
171 {
172 int i;
173
174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176
177 for (i = 0; i < PHY_RETRIES; i++) {
178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
180 return 0;
181 }
182
183 udelay(1);
184 }
185
186 return -ETIMEDOUT;
187 }
188
189 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190 {
191 u16 v;
192
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
195 return v;
196 }
197
198 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
199 {
200 u16 power_control;
201 int vaux;
202
203 pr_debug("sky2_set_power_state %d\n", state);
204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
205
206 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
207 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
208 (power_control & PCI_PM_CAP_PME_D3cold);
209
210 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
211
212 power_control |= PCI_PM_CTRL_PME_STATUS;
213 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
214
215 switch (state) {
216 case PCI_D0:
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
234 u32 reg1;
235
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
238 reg1 &= P_ASPM_CONTROL_MSK;
239 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
240 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
241 }
242
243 break;
244
245 case PCI_D3hot:
246 case PCI_D3cold:
247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
261 break;
262 default:
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
264 }
265
266 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
268 }
269
270 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
271 {
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
278
279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287 }
288
289 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
290 {
291 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
292 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
293
294 if (sky2->autoneg == AUTONEG_ENABLE &&
295 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
299 PHY_M_EC_MAC_S_MSK);
300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
311 if (sky2_is_copper(hw)) {
312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
322 if (sky2->autoneg == AUTONEG_ENABLE &&
323 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
326 }
327 }
328 } else {
329 /* workaround for deviation #4.88 (CRC errors) */
330 /* disable Automatic Crossover */
331
332 ctrl &= ~PHY_M_PC_MDIX_MSK;
333 }
334
335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
336
337 /* special setup for PHY 88E1112 Fiber */
338 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
339 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
340
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->pmd_type == 'P') {
349 /* select page 1 to access Fiber registers */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
351
352 /* for SFP-module set SIGDET polarity to low */
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl |= PHY_M_FIB_SIGD_POL;
355 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
356 }
357
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
373 reg = 0;
374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2_is_copper(hw)) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 adv |= PHY_M_AN_1000X_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 adv |= PHY_M_AN_1000X_AHD;
394 }
395
396 /* Set Flow-control capabilities */
397 if (sky2->tx_pause && sky2->rx_pause)
398 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
399 else if (sky2->rx_pause && !sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
401 else if (!sky2->rx_pause && sky2->tx_pause)
402 adv |= PHY_AN_PAUSE_ASYM; /* local */
403
404 /* Restart Auto-negotiation */
405 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
406 } else {
407 /* forced speed/duplex settings */
408 ct1000 = PHY_M_1000C_MSE;
409
410 /* Disable auto update for duplex flow control and speed */
411 reg |= GM_GPCR_AU_ALL_DIS;
412
413 switch (sky2->speed) {
414 case SPEED_1000:
415 ctrl |= PHY_CT_SP1000;
416 reg |= GM_GPCR_SPEED_1000;
417 break;
418 case SPEED_100:
419 ctrl |= PHY_CT_SP100;
420 reg |= GM_GPCR_SPEED_100;
421 break;
422 }
423
424 if (sky2->duplex == DUPLEX_FULL) {
425 reg |= GM_GPCR_DUP_FULL;
426 ctrl |= PHY_CT_DUP_MD;
427 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
428 /* Turn off flow control for 10/100mbps */
429 sky2->rx_pause = 0;
430 sky2->tx_pause = 0;
431 }
432
433 if (!sky2->rx_pause)
434 reg |= GM_GPCR_FC_RX_DIS;
435
436 if (!sky2->tx_pause)
437 reg |= GM_GPCR_FC_TX_DIS;
438
439 /* Forward pause packets to GMAC? */
440 if (sky2->tx_pause || sky2->rx_pause)
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
442 else
443 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
444
445 ctrl |= PHY_CT_RESET;
446 }
447
448 gma_write16(hw, port, GM_GP_CTRL, reg);
449
450 if (hw->chip_id != CHIP_ID_YUKON_FE)
451 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
452
453 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
454 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
455
456 /* Setup Phy LED's */
457 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
458 ledover = 0;
459
460 switch (hw->chip_id) {
461 case CHIP_ID_YUKON_FE:
462 /* on 88E3082 these bits are at 11..9 (shifted left) */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
464
465 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
466
467 /* delete ACT LED control bits */
468 ctrl &= ~PHY_M_FELP_LED1_MSK;
469 /* change ACT LED control to blink mode */
470 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
471 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
472 break;
473
474 case CHIP_ID_YUKON_XL:
475 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
476
477 /* select page 3 to access LED control register */
478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
479
480 /* set LED Function Control register */
481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
482 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
483 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
484 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
485 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
486
487 /* set Polarity Control register */
488 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
489 (PHY_M_POLC_LS1_P_MIX(4) |
490 PHY_M_POLC_IS0_P_MIX(4) |
491 PHY_M_POLC_LOS_CTRL(2) |
492 PHY_M_POLC_INIT_CTRL(2) |
493 PHY_M_POLC_STA1_CTRL(2) |
494 PHY_M_POLC_STA0_CTRL(2)));
495
496 /* restore page register */
497 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
498 break;
499 case CHIP_ID_YUKON_EC_U:
500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501
502 /* select page 3 to access LED control register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
504
505 /* set LED Function Control register */
506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
507 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
508 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
509 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
510 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
511
512 /* set Blink Rate in LED Timer Control Register */
513 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
514 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
515 /* restore page register */
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
517 break;
518
519 default:
520 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
521 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
522 /* turn off the Rx LED (LED_RX) */
523 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
524 }
525
526 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
527 /* apply fixes in PHY AFE */
528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
530
531 /* increase differential signal amplitude in 10BASE-T */
532 gm_phy_write(hw, port, 0x18, 0xaa99);
533 gm_phy_write(hw, port, 0x17, 0x2011);
534
535 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
536 gm_phy_write(hw, port, 0x18, 0xa204);
537 gm_phy_write(hw, port, 0x17, 0x2002);
538
539 /* set page register to 0 */
540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
541 } else {
542 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
543
544 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
545 /* turn on 100 Mbps LED (LED_LINK100) */
546 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
547 }
548
549 if (ledover)
550 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
551
552 }
553
554 /* Enable phy interrupt on auto-negotiation complete (or link up) */
555 if (sky2->autoneg == AUTONEG_ENABLE)
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
557 else
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
559 }
560
561 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
562 {
563 u32 reg1;
564 static const u32 phy_power[]
565 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
566
567 /* looks like this XL is back asswards .. */
568 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
569 onoff = !onoff;
570
571 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
572
573 if (onoff)
574 /* Turn off phy power saving */
575 reg1 &= ~phy_power[port];
576 else
577 reg1 |= phy_power[port];
578
579 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
580 sky2_pci_read32(hw, PCI_DEV_REG1);
581 udelay(100);
582 }
583
584 /* Force a renegotiation */
585 static void sky2_phy_reinit(struct sky2_port *sky2)
586 {
587 spin_lock_bh(&sky2->phy_lock);
588 sky2_phy_init(sky2->hw, sky2->port);
589 spin_unlock_bh(&sky2->phy_lock);
590 }
591
592 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
593 {
594 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
595 u16 reg;
596 int i;
597 const u8 *addr = hw->dev[port]->dev_addr;
598
599 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
601
602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
603
604 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
605 /* WA DEV_472 -- looks like crossed wires on port 2 */
606 /* clear GMAC 1 Control reset */
607 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
608 do {
609 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
611 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
612 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
613 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
614 }
615
616 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
617
618 /* Enable Transmit FIFO Underrun */
619 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
620
621 spin_lock_bh(&sky2->phy_lock);
622 sky2_phy_init(hw, port);
623 spin_unlock_bh(&sky2->phy_lock);
624
625 /* MIB clear */
626 reg = gma_read16(hw, port, GM_PHY_ADDR);
627 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
628
629 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
630 gma_read16(hw, port, i);
631 gma_write16(hw, port, GM_PHY_ADDR, reg);
632
633 /* transmit control */
634 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
635
636 /* receive control reg: unicast + multicast + no FCS */
637 gma_write16(hw, port, GM_RX_CTRL,
638 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
639
640 /* transmit flow control */
641 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
642
643 /* transmit parameter */
644 gma_write16(hw, port, GM_TX_PARAM,
645 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
646 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
647 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
648 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
649
650 /* serial mode register */
651 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
652 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
653
654 if (hw->dev[port]->mtu > ETH_DATA_LEN)
655 reg |= GM_SMOD_JUMBO_ENA;
656
657 gma_write16(hw, port, GM_SERIAL_MODE, reg);
658
659 /* virtual address for data */
660 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
661
662 /* physical address: used for pause frames */
663 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
664
665 /* ignore counter overflows */
666 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
667 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
669
670 /* Configure Rx MAC FIFO */
671 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
672 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
673 GMF_OPER_ON | GMF_RX_F_FL_ON);
674
675 /* Flush Rx MAC FIFO on any flow control or error */
676 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
677
678 /* Set threshold to 0xa (64 bytes)
679 * ASF disabled so no need to do WA dev #4.30
680 */
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
682
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
686
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
695 }
696 }
697
698 }
699
700 /* Assign Ram Buffer allocation.
701 * start and end are in units of 4k bytes
702 * ram registers are in units of 64bit words
703 */
704 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
705 {
706 u32 start, end;
707
708 start = startk * 4096/8;
709 end = (endk * 4096/8) - 1;
710
711 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
712 sky2_write32(hw, RB_ADDR(q, RB_START), start);
713 sky2_write32(hw, RB_ADDR(q, RB_END), end);
714 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
715 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
716
717 if (q == Q_R1 || q == Q_R2) {
718 u32 space = (endk - startk) * 4096/8;
719 u32 tp = space - space/4;
720
721 /* On receive queue's set the thresholds
722 * give receiver priority when > 3/4 full
723 * send pause when down to 2K
724 */
725 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
726 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
727
728 tp = space - 2048/8;
729 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
730 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
731 } else {
732 /* Enable store & forward on Tx queue's because
733 * Tx FIFO is only 1K on Yukon
734 */
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
736 }
737
738 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
739 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
740 }
741
742 /* Setup Bus Memory Interface */
743 static void sky2_qset(struct sky2_hw *hw, u16 q)
744 {
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
746 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
748 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
749 }
750
751 /* Setup prefetch unit registers. This is the interface between
752 * hardware and driver list elements
753 */
754 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
755 u64 addr, u32 last)
756 {
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
761 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
763
764 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
765 }
766
767 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
768 {
769 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
770
771 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
772 return le;
773 }
774
775 /* Update chip's next pointer */
776 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
777 {
778 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
779 wmb();
780 sky2_write16(hw, q, idx);
781 sky2_read16(hw, q);
782 }
783
784
785 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
786 {
787 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
788 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
789 return le;
790 }
791
792 /* Return high part of DMA address (could be 32 or 64 bit) */
793 static inline u32 high32(dma_addr_t a)
794 {
795 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
796 }
797
798 /* Build description to hardware about buffer */
799 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
800 {
801 struct sky2_rx_le *le;
802 u32 hi = high32(map);
803 u16 len = sky2->rx_bufsize;
804
805 if (sky2->rx_addr64 != hi) {
806 le = sky2_next_rx(sky2);
807 le->addr = cpu_to_le32(hi);
808 le->ctrl = 0;
809 le->opcode = OP_ADDR64 | HW_OWNER;
810 sky2->rx_addr64 = high32(map + len);
811 }
812
813 le = sky2_next_rx(sky2);
814 le->addr = cpu_to_le32((u32) map);
815 le->length = cpu_to_le16(len);
816 le->ctrl = 0;
817 le->opcode = OP_PACKET | HW_OWNER;
818 }
819
820
821 /* Tell chip where to start receive checksum.
822 * Actually has two checksums, but set both same to avoid possible byte
823 * order problems.
824 */
825 static void rx_set_checksum(struct sky2_port *sky2)
826 {
827 struct sky2_rx_le *le;
828
829 le = sky2_next_rx(sky2);
830 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
831 le->ctrl = 0;
832 le->opcode = OP_TCPSTART | HW_OWNER;
833
834 sky2_write32(sky2->hw,
835 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
836 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
837
838 }
839
840 /*
841 * The RX Stop command will not work for Yukon-2 if the BMU does not
842 * reach the end of packet and since we can't make sure that we have
843 * incoming data, we must reset the BMU while it is not doing a DMA
844 * transfer. Since it is possible that the RX path is still active,
845 * the RX RAM buffer will be stopped first, so any possible incoming
846 * data will not trigger a DMA. After the RAM buffer is stopped, the
847 * BMU is polled until any DMA in progress is ended and only then it
848 * will be reset.
849 */
850 static void sky2_rx_stop(struct sky2_port *sky2)
851 {
852 struct sky2_hw *hw = sky2->hw;
853 unsigned rxq = rxqaddr[sky2->port];
854 int i;
855
856 /* disable the RAM Buffer receive queue */
857 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
858
859 for (i = 0; i < 0xffff; i++)
860 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
861 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
862 goto stopped;
863
864 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
865 sky2->netdev->name);
866 stopped:
867 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
868
869 /* reset the Rx prefetch unit */
870 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
871 }
872
873 /* Clean out receive buffer area, assumes receiver hardware stopped */
874 static void sky2_rx_clean(struct sky2_port *sky2)
875 {
876 unsigned i;
877
878 memset(sky2->rx_le, 0, RX_LE_BYTES);
879 for (i = 0; i < sky2->rx_pending; i++) {
880 struct ring_info *re = sky2->rx_ring + i;
881
882 if (re->skb) {
883 pci_unmap_single(sky2->hw->pdev,
884 re->mapaddr, sky2->rx_bufsize,
885 PCI_DMA_FROMDEVICE);
886 kfree_skb(re->skb);
887 re->skb = NULL;
888 }
889 }
890 }
891
892 /* Basic MII support */
893 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
894 {
895 struct mii_ioctl_data *data = if_mii(ifr);
896 struct sky2_port *sky2 = netdev_priv(dev);
897 struct sky2_hw *hw = sky2->hw;
898 int err = -EOPNOTSUPP;
899
900 if (!netif_running(dev))
901 return -ENODEV; /* Phy still in reset */
902
903 switch (cmd) {
904 case SIOCGMIIPHY:
905 data->phy_id = PHY_ADDR_MARV;
906
907 /* fallthru */
908 case SIOCGMIIREG: {
909 u16 val = 0;
910
911 spin_lock_bh(&sky2->phy_lock);
912 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
913 spin_unlock_bh(&sky2->phy_lock);
914
915 data->val_out = val;
916 break;
917 }
918
919 case SIOCSMIIREG:
920 if (!capable(CAP_NET_ADMIN))
921 return -EPERM;
922
923 spin_lock_bh(&sky2->phy_lock);
924 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
925 data->val_in);
926 spin_unlock_bh(&sky2->phy_lock);
927 break;
928 }
929 return err;
930 }
931
932 #ifdef SKY2_VLAN_TAG_USED
933 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
934 {
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
938
939 spin_lock_bh(&sky2->tx_lock);
940
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
943 sky2->vlgrp = grp;
944
945 spin_unlock_bh(&sky2->tx_lock);
946 }
947
948 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
949 {
950 struct sky2_port *sky2 = netdev_priv(dev);
951 struct sky2_hw *hw = sky2->hw;
952 u16 port = sky2->port;
953
954 spin_lock_bh(&sky2->tx_lock);
955
956 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
957 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
958 if (sky2->vlgrp)
959 sky2->vlgrp->vlan_devices[vid] = NULL;
960
961 spin_unlock_bh(&sky2->tx_lock);
962 }
963 #endif
964
965 /*
966 * It appears the hardware has a bug in the FIFO logic that
967 * cause it to hang if the FIFO gets overrun and the receive buffer
968 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
969 * aligned except if slab debugging is enabled.
970 */
971 static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
972 unsigned int length,
973 gfp_t gfp_mask)
974 {
975 struct sk_buff *skb;
976
977 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
978 if (likely(skb)) {
979 unsigned long p = (unsigned long) skb->data;
980 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
981 }
982
983 return skb;
984 }
985
986 /*
987 * Allocate and setup receiver buffer pool.
988 * In case of 64 bit dma, there are 2X as many list elements
989 * available as ring entries
990 * and need to reserve one list element so we don't wrap around.
991 */
992 static int sky2_rx_start(struct sky2_port *sky2)
993 {
994 struct sky2_hw *hw = sky2->hw;
995 unsigned rxq = rxqaddr[sky2->port];
996 int i;
997 unsigned thresh;
998
999 sky2->rx_put = sky2->rx_next = 0;
1000 sky2_qset(hw, rxq);
1001
1002 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1003 /* MAC Rx RAM Read is controlled by hardware */
1004 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1005 }
1006
1007 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1008
1009 rx_set_checksum(sky2);
1010 for (i = 0; i < sky2->rx_pending; i++) {
1011 struct ring_info *re = sky2->rx_ring + i;
1012
1013 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1014 GFP_KERNEL);
1015 if (!re->skb)
1016 goto nomem;
1017
1018 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1019 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1020 sky2_rx_add(sky2, re->mapaddr);
1021 }
1022
1023
1024 /*
1025 * The receiver hangs if it receives frames larger than the
1026 * packet buffer. As a workaround, truncate oversize frames, but
1027 * the register is limited to 9 bits, so if you do frames > 2052
1028 * you better get the MTU right!
1029 */
1030 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1031 if (thresh > 0x1ff)
1032 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1033 else {
1034 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1035 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1036 }
1037
1038
1039 /* Tell chip about available buffers */
1040 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1041 return 0;
1042 nomem:
1043 sky2_rx_clean(sky2);
1044 return -ENOMEM;
1045 }
1046
1047 /* Bring up network interface. */
1048 static int sky2_up(struct net_device *dev)
1049 {
1050 struct sky2_port *sky2 = netdev_priv(dev);
1051 struct sky2_hw *hw = sky2->hw;
1052 unsigned port = sky2->port;
1053 u32 ramsize, rxspace, imask;
1054 int cap, err = -ENOMEM;
1055 struct net_device *otherdev = hw->dev[sky2->port^1];
1056
1057 /*
1058 * On dual port PCI-X card, there is an problem where status
1059 * can be received out of order due to split transactions
1060 */
1061 if (otherdev && netif_running(otherdev) &&
1062 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1063 struct sky2_port *osky2 = netdev_priv(otherdev);
1064 u16 cmd;
1065
1066 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1067 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1068 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1069
1070 sky2->rx_csum = 0;
1071 osky2->rx_csum = 0;
1072 }
1073
1074 if (netif_msg_ifup(sky2))
1075 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1076
1077 /* must be power of 2 */
1078 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1079 TX_RING_SIZE *
1080 sizeof(struct sky2_tx_le),
1081 &sky2->tx_le_map);
1082 if (!sky2->tx_le)
1083 goto err_out;
1084
1085 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1086 GFP_KERNEL);
1087 if (!sky2->tx_ring)
1088 goto err_out;
1089 sky2->tx_prod = sky2->tx_cons = 0;
1090
1091 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1092 &sky2->rx_le_map);
1093 if (!sky2->rx_le)
1094 goto err_out;
1095 memset(sky2->rx_le, 0, RX_LE_BYTES);
1096
1097 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1098 GFP_KERNEL);
1099 if (!sky2->rx_ring)
1100 goto err_out;
1101
1102 sky2_phy_power(hw, port, 1);
1103
1104 sky2_mac_init(hw, port);
1105
1106 /* Determine available ram buffer space (in 4K blocks).
1107 * Note: not sure about the FE setting below yet
1108 */
1109 if (hw->chip_id == CHIP_ID_YUKON_FE)
1110 ramsize = 4;
1111 else
1112 ramsize = sky2_read8(hw, B2_E_0);
1113
1114 /* Give transmitter one third (rounded up) */
1115 rxspace = ramsize - (ramsize + 2) / 3;
1116
1117 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1118 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1119
1120 /* Make sure SyncQ is disabled */
1121 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1122 RB_RST_SET);
1123
1124 sky2_qset(hw, txqaddr[port]);
1125
1126 /* Set almost empty threshold */
1127 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1128 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1129
1130 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1131 TX_RING_SIZE - 1);
1132
1133 err = sky2_rx_start(sky2);
1134 if (err)
1135 goto err_out;
1136
1137 /* Enable interrupts from phy/mac for port */
1138 imask = sky2_read32(hw, B0_IMSK);
1139 imask |= portirq_msk[port];
1140 sky2_write32(hw, B0_IMSK, imask);
1141
1142 return 0;
1143
1144 err_out:
1145 if (sky2->rx_le) {
1146 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1147 sky2->rx_le, sky2->rx_le_map);
1148 sky2->rx_le = NULL;
1149 }
1150 if (sky2->tx_le) {
1151 pci_free_consistent(hw->pdev,
1152 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1153 sky2->tx_le, sky2->tx_le_map);
1154 sky2->tx_le = NULL;
1155 }
1156 kfree(sky2->tx_ring);
1157 kfree(sky2->rx_ring);
1158
1159 sky2->tx_ring = NULL;
1160 sky2->rx_ring = NULL;
1161 return err;
1162 }
1163
1164 /* Modular subtraction in ring */
1165 static inline int tx_dist(unsigned tail, unsigned head)
1166 {
1167 return (head - tail) & (TX_RING_SIZE - 1);
1168 }
1169
1170 /* Number of list elements available for next tx */
1171 static inline int tx_avail(const struct sky2_port *sky2)
1172 {
1173 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1174 }
1175
1176 /* Estimate of number of transmit list elements required */
1177 static unsigned tx_le_req(const struct sk_buff *skb)
1178 {
1179 unsigned count;
1180
1181 count = sizeof(dma_addr_t) / sizeof(u32);
1182 count += skb_shinfo(skb)->nr_frags * count;
1183
1184 if (skb_is_gso(skb))
1185 ++count;
1186
1187 if (skb->ip_summed == CHECKSUM_PARTIAL)
1188 ++count;
1189
1190 return count;
1191 }
1192
1193 /*
1194 * Put one packet in ring for transmit.
1195 * A single packet can generate multiple list elements, and
1196 * the number of ring elements will probably be less than the number
1197 * of list elements used.
1198 *
1199 * No BH disabling for tx_lock here (like tg3)
1200 */
1201 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1202 {
1203 struct sky2_port *sky2 = netdev_priv(dev);
1204 struct sky2_hw *hw = sky2->hw;
1205 struct sky2_tx_le *le = NULL;
1206 struct tx_ring_info *re;
1207 unsigned i, len;
1208 dma_addr_t mapping;
1209 u32 addr64;
1210 u16 mss;
1211 u8 ctrl;
1212
1213 /* No BH disabling for tx_lock here. We are running in BH disabled
1214 * context and TX reclaim runs via poll inside of a software
1215 * interrupt, and no related locks in IRQ processing.
1216 */
1217 if (!spin_trylock(&sky2->tx_lock))
1218 return NETDEV_TX_LOCKED;
1219
1220 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1221 /* There is a known but harmless race with lockless tx
1222 * and netif_stop_queue.
1223 */
1224 if (!netif_queue_stopped(dev)) {
1225 netif_stop_queue(dev);
1226 if (net_ratelimit())
1227 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1228 dev->name);
1229 }
1230 spin_unlock(&sky2->tx_lock);
1231
1232 return NETDEV_TX_BUSY;
1233 }
1234
1235 if (unlikely(netif_msg_tx_queued(sky2)))
1236 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1237 dev->name, sky2->tx_prod, skb->len);
1238
1239 len = skb_headlen(skb);
1240 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1241 addr64 = high32(mapping);
1242
1243 re = sky2->tx_ring + sky2->tx_prod;
1244
1245 /* Send high bits if changed or crosses boundary */
1246 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1247 le = get_tx_le(sky2);
1248 le->addr = cpu_to_le32(addr64);
1249 le->ctrl = 0;
1250 le->opcode = OP_ADDR64 | HW_OWNER;
1251 sky2->tx_addr64 = high32(mapping + len);
1252 }
1253
1254 /* Check for TCP Segmentation Offload */
1255 mss = skb_shinfo(skb)->gso_size;
1256 if (mss != 0) {
1257 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1258 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1259 mss += ETH_HLEN;
1260
1261 if (mss != sky2->tx_last_mss) {
1262 le = get_tx_le(sky2);
1263 le->addr = cpu_to_le32(mss);
1264 le->opcode = OP_LRGLEN | HW_OWNER;
1265 le->ctrl = 0;
1266 sky2->tx_last_mss = mss;
1267 }
1268 }
1269
1270 ctrl = 0;
1271 #ifdef SKY2_VLAN_TAG_USED
1272 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1273 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1274 if (!le) {
1275 le = get_tx_le(sky2);
1276 le->addr = 0;
1277 le->opcode = OP_VLAN|HW_OWNER;
1278 le->ctrl = 0;
1279 } else
1280 le->opcode |= OP_VLAN;
1281 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1282 ctrl |= INS_VLAN;
1283 }
1284 #endif
1285
1286 /* Handle TCP checksum offload */
1287 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1288 unsigned offset = skb->h.raw - skb->data;
1289 u32 tcpsum;
1290
1291 tcpsum = offset << 16; /* sum start */
1292 tcpsum |= offset + skb->csum; /* sum write */
1293
1294 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1295 if (skb->nh.iph->protocol == IPPROTO_UDP)
1296 ctrl |= UDPTCP;
1297
1298 if (tcpsum != sky2->tx_tcpsum) {
1299 sky2->tx_tcpsum = tcpsum;
1300
1301 le = get_tx_le(sky2);
1302 le->addr = cpu_to_le32(tcpsum);
1303 le->length = 0; /* initial checksum value */
1304 le->ctrl = 1; /* one packet */
1305 le->opcode = OP_TCPLISW | HW_OWNER;
1306 }
1307 }
1308
1309 le = get_tx_le(sky2);
1310 le->addr = cpu_to_le32((u32) mapping);
1311 le->length = cpu_to_le16(len);
1312 le->ctrl = ctrl;
1313 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1314
1315 /* Record the transmit mapping info */
1316 re->skb = skb;
1317 pci_unmap_addr_set(re, mapaddr, mapping);
1318
1319 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1320 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1321 struct tx_ring_info *fre;
1322
1323 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1324 frag->size, PCI_DMA_TODEVICE);
1325 addr64 = high32(mapping);
1326 if (addr64 != sky2->tx_addr64) {
1327 le = get_tx_le(sky2);
1328 le->addr = cpu_to_le32(addr64);
1329 le->ctrl = 0;
1330 le->opcode = OP_ADDR64 | HW_OWNER;
1331 sky2->tx_addr64 = addr64;
1332 }
1333
1334 le = get_tx_le(sky2);
1335 le->addr = cpu_to_le32((u32) mapping);
1336 le->length = cpu_to_le16(frag->size);
1337 le->ctrl = ctrl;
1338 le->opcode = OP_BUFFER | HW_OWNER;
1339
1340 fre = sky2->tx_ring
1341 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1342 pci_unmap_addr_set(fre, mapaddr, mapping);
1343 }
1344
1345 re->idx = sky2->tx_prod;
1346 le->ctrl |= EOP;
1347
1348 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1349 netif_stop_queue(dev);
1350
1351 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1352
1353 spin_unlock(&sky2->tx_lock);
1354
1355 dev->trans_start = jiffies;
1356 return NETDEV_TX_OK;
1357 }
1358
1359 /*
1360 * Free ring elements from starting at tx_cons until "done"
1361 *
1362 * NB: the hardware will tell us about partial completion of multi-part
1363 * buffers; these are deferred until completion.
1364 */
1365 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1366 {
1367 struct net_device *dev = sky2->netdev;
1368 struct pci_dev *pdev = sky2->hw->pdev;
1369 u16 nxt, put;
1370 unsigned i;
1371
1372 BUG_ON(done >= TX_RING_SIZE);
1373
1374 if (unlikely(netif_msg_tx_done(sky2)))
1375 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1376 dev->name, done);
1377
1378 for (put = sky2->tx_cons; put != done; put = nxt) {
1379 struct tx_ring_info *re = sky2->tx_ring + put;
1380 struct sk_buff *skb = re->skb;
1381
1382 nxt = re->idx;
1383 BUG_ON(nxt >= TX_RING_SIZE);
1384 prefetch(sky2->tx_ring + nxt);
1385
1386 /* Check for partial status */
1387 if (tx_dist(put, done) < tx_dist(put, nxt))
1388 break;
1389
1390 skb = re->skb;
1391 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1392 skb_headlen(skb), PCI_DMA_TODEVICE);
1393
1394 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1395 struct tx_ring_info *fre;
1396 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1397 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1398 skb_shinfo(skb)->frags[i].size,
1399 PCI_DMA_TODEVICE);
1400 }
1401
1402 dev_kfree_skb(skb);
1403 }
1404
1405 sky2->tx_cons = put;
1406 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1407 netif_wake_queue(dev);
1408 }
1409
1410 /* Cleanup all untransmitted buffers, assume transmitter not running */
1411 static void sky2_tx_clean(struct sky2_port *sky2)
1412 {
1413 spin_lock_bh(&sky2->tx_lock);
1414 sky2_tx_complete(sky2, sky2->tx_prod);
1415 spin_unlock_bh(&sky2->tx_lock);
1416 }
1417
1418 /* Network shutdown */
1419 static int sky2_down(struct net_device *dev)
1420 {
1421 struct sky2_port *sky2 = netdev_priv(dev);
1422 struct sky2_hw *hw = sky2->hw;
1423 unsigned port = sky2->port;
1424 u16 ctrl;
1425 u32 imask;
1426
1427 /* Never really got started! */
1428 if (!sky2->tx_le)
1429 return 0;
1430
1431 if (netif_msg_ifdown(sky2))
1432 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1433
1434 /* Stop more packets from being queued */
1435 netif_stop_queue(dev);
1436
1437 sky2_gmac_reset(hw, port);
1438
1439 /* Stop transmitter */
1440 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1441 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1442
1443 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1444 RB_RST_SET | RB_DIS_OP_MD);
1445
1446 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1447 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1448 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1449
1450 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1451
1452 /* Workaround shared GMAC reset */
1453 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1454 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1455 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1456
1457 /* Disable Force Sync bit and Enable Alloc bit */
1458 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1459 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1460
1461 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1462 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1463 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1464
1465 /* Reset the PCI FIFO of the async Tx queue */
1466 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1467 BMU_RST_SET | BMU_FIFO_RST);
1468
1469 /* Reset the Tx prefetch units */
1470 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1471 PREF_UNIT_RST_SET);
1472
1473 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1474
1475 sky2_rx_stop(sky2);
1476
1477 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1479
1480 /* Disable port IRQ */
1481 imask = sky2_read32(hw, B0_IMSK);
1482 imask &= ~portirq_msk[port];
1483 sky2_write32(hw, B0_IMSK, imask);
1484
1485 sky2_phy_power(hw, port, 0);
1486
1487 /* turn off LED's */
1488 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1489
1490 synchronize_irq(hw->pdev->irq);
1491
1492 sky2_tx_clean(sky2);
1493 sky2_rx_clean(sky2);
1494
1495 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1496 sky2->rx_le, sky2->rx_le_map);
1497 kfree(sky2->rx_ring);
1498
1499 pci_free_consistent(hw->pdev,
1500 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1501 sky2->tx_le, sky2->tx_le_map);
1502 kfree(sky2->tx_ring);
1503
1504 sky2->tx_le = NULL;
1505 sky2->rx_le = NULL;
1506
1507 sky2->rx_ring = NULL;
1508 sky2->tx_ring = NULL;
1509
1510 return 0;
1511 }
1512
1513 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1514 {
1515 if (!sky2_is_copper(hw))
1516 return SPEED_1000;
1517
1518 if (hw->chip_id == CHIP_ID_YUKON_FE)
1519 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1520
1521 switch (aux & PHY_M_PS_SPEED_MSK) {
1522 case PHY_M_PS_SPEED_1000:
1523 return SPEED_1000;
1524 case PHY_M_PS_SPEED_100:
1525 return SPEED_100;
1526 default:
1527 return SPEED_10;
1528 }
1529 }
1530
1531 static void sky2_link_up(struct sky2_port *sky2)
1532 {
1533 struct sky2_hw *hw = sky2->hw;
1534 unsigned port = sky2->port;
1535 u16 reg;
1536
1537 /* enable Rx/Tx */
1538 reg = gma_read16(hw, port, GM_GP_CTRL);
1539 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1540 gma_write16(hw, port, GM_GP_CTRL, reg);
1541
1542 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1543
1544 netif_carrier_on(sky2->netdev);
1545 netif_wake_queue(sky2->netdev);
1546
1547 /* Turn on link LED */
1548 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1549 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1550
1551 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1552 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1553 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1554
1555 switch(sky2->speed) {
1556 case SPEED_10:
1557 led |= PHY_M_LEDC_INIT_CTRL(7);
1558 break;
1559
1560 case SPEED_100:
1561 led |= PHY_M_LEDC_STA1_CTRL(7);
1562 break;
1563
1564 case SPEED_1000:
1565 led |= PHY_M_LEDC_STA0_CTRL(7);
1566 break;
1567 }
1568
1569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1570 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1571 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1572 }
1573
1574 if (netif_msg_link(sky2))
1575 printk(KERN_INFO PFX
1576 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1577 sky2->netdev->name, sky2->speed,
1578 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1579 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1580 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1581 }
1582
1583 static void sky2_link_down(struct sky2_port *sky2)
1584 {
1585 struct sky2_hw *hw = sky2->hw;
1586 unsigned port = sky2->port;
1587 u16 reg;
1588
1589 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1590
1591 reg = gma_read16(hw, port, GM_GP_CTRL);
1592 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1593 gma_write16(hw, port, GM_GP_CTRL, reg);
1594
1595 if (sky2->rx_pause && !sky2->tx_pause) {
1596 /* restore Asymmetric Pause bit */
1597 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1598 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1599 | PHY_M_AN_ASP);
1600 }
1601
1602 netif_carrier_off(sky2->netdev);
1603 netif_stop_queue(sky2->netdev);
1604
1605 /* Turn on link LED */
1606 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1607
1608 if (netif_msg_link(sky2))
1609 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1610
1611 sky2_phy_init(hw, port);
1612 }
1613
1614 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1615 {
1616 struct sky2_hw *hw = sky2->hw;
1617 unsigned port = sky2->port;
1618 u16 lpa;
1619
1620 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1621
1622 if (lpa & PHY_M_AN_RF) {
1623 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1624 return -1;
1625 }
1626
1627 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1628 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1629 sky2->netdev->name);
1630 return -1;
1631 }
1632
1633 sky2->speed = sky2_phy_speed(hw, aux);
1634 if (sky2->speed == SPEED_1000) {
1635 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1636 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1637 if (lpa2 & PHY_B_1000S_MSF) {
1638 printk(KERN_ERR PFX "%s: master/slave fault",
1639 sky2->netdev->name);
1640 return -1;
1641 }
1642
1643 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1644 sky2->duplex = DUPLEX_FULL;
1645 else
1646 sky2->duplex = DUPLEX_HALF;
1647 } else {
1648 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1649 if ((aux & adv) & PHY_AN_FULL)
1650 sky2->duplex = DUPLEX_FULL;
1651 else
1652 sky2->duplex = DUPLEX_HALF;
1653 }
1654
1655 /* Pause bits are offset (9..8) */
1656 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1657 aux >>= 6;
1658
1659 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1660 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1661
1662 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1663 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1664 sky2->rx_pause = sky2->tx_pause = 0;
1665
1666 if (sky2->rx_pause || sky2->tx_pause)
1667 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1668 else
1669 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1670
1671 return 0;
1672 }
1673
1674 /* Interrupt from PHY */
1675 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1676 {
1677 struct net_device *dev = hw->dev[port];
1678 struct sky2_port *sky2 = netdev_priv(dev);
1679 u16 istatus, phystat;
1680
1681 spin_lock(&sky2->phy_lock);
1682 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1683 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1684
1685 if (!netif_running(dev))
1686 goto out;
1687
1688 if (netif_msg_intr(sky2))
1689 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1690 sky2->netdev->name, istatus, phystat);
1691
1692 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1693 if (sky2_autoneg_done(sky2, phystat) == 0)
1694 sky2_link_up(sky2);
1695 goto out;
1696 }
1697
1698 if (istatus & PHY_M_IS_LSP_CHANGE)
1699 sky2->speed = sky2_phy_speed(hw, phystat);
1700
1701 if (istatus & PHY_M_IS_DUP_CHANGE)
1702 sky2->duplex =
1703 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1704
1705 if (istatus & PHY_M_IS_LST_CHANGE) {
1706 if (phystat & PHY_M_PS_LINK_UP)
1707 sky2_link_up(sky2);
1708 else
1709 sky2_link_down(sky2);
1710 }
1711 out:
1712 spin_unlock(&sky2->phy_lock);
1713 }
1714
1715
1716 /* Transmit timeout is only called if we are running, carries is up
1717 * and tx queue is full (stopped).
1718 */
1719 static void sky2_tx_timeout(struct net_device *dev)
1720 {
1721 struct sky2_port *sky2 = netdev_priv(dev);
1722 struct sky2_hw *hw = sky2->hw;
1723 unsigned txq = txqaddr[sky2->port];
1724 u16 report, done;
1725
1726 if (netif_msg_timer(sky2))
1727 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1728
1729 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1730 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1731
1732 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1733 dev->name,
1734 sky2->tx_cons, sky2->tx_prod, report, done);
1735
1736 if (report != done) {
1737 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1738
1739 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1741 } else if (report != sky2->tx_cons) {
1742 printk(KERN_INFO PFX "status report lost?\n");
1743
1744 spin_lock_bh(&sky2->tx_lock);
1745 sky2_tx_complete(sky2, report);
1746 spin_unlock_bh(&sky2->tx_lock);
1747 } else {
1748 printk(KERN_INFO PFX "hardware hung? flushing\n");
1749
1750 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1751 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1752
1753 sky2_tx_clean(sky2);
1754
1755 sky2_qset(hw, txq);
1756 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1757 }
1758 }
1759
1760
1761 /* Want receive buffer size to be multiple of 64 bits
1762 * and incl room for vlan and truncation
1763 */
1764 static inline unsigned sky2_buf_size(int mtu)
1765 {
1766 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1767 }
1768
1769 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1770 {
1771 struct sky2_port *sky2 = netdev_priv(dev);
1772 struct sky2_hw *hw = sky2->hw;
1773 int err;
1774 u16 ctl, mode;
1775 u32 imask;
1776
1777 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1778 return -EINVAL;
1779
1780 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1781 return -EINVAL;
1782
1783 if (!netif_running(dev)) {
1784 dev->mtu = new_mtu;
1785 return 0;
1786 }
1787
1788 imask = sky2_read32(hw, B0_IMSK);
1789 sky2_write32(hw, B0_IMSK, 0);
1790
1791 dev->trans_start = jiffies; /* prevent tx timeout */
1792 netif_stop_queue(dev);
1793 netif_poll_disable(hw->dev[0]);
1794
1795 synchronize_irq(hw->pdev->irq);
1796
1797 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1798 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1799 sky2_rx_stop(sky2);
1800 sky2_rx_clean(sky2);
1801
1802 dev->mtu = new_mtu;
1803 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1804 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1805 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1806
1807 if (dev->mtu > ETH_DATA_LEN)
1808 mode |= GM_SMOD_JUMBO_ENA;
1809
1810 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1811
1812 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1813
1814 err = sky2_rx_start(sky2);
1815 sky2_write32(hw, B0_IMSK, imask);
1816
1817 if (err)
1818 dev_close(dev);
1819 else {
1820 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1821
1822 netif_poll_enable(hw->dev[0]);
1823 netif_wake_queue(dev);
1824 }
1825
1826 return err;
1827 }
1828
1829 /*
1830 * Receive one packet.
1831 * For small packets or errors, just reuse existing skb.
1832 * For larger packets, get new buffer.
1833 */
1834 static struct sk_buff *sky2_receive(struct net_device *dev,
1835 u16 length, u32 status)
1836 {
1837 struct sky2_port *sky2 = netdev_priv(dev);
1838 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1839 struct sk_buff *skb = NULL;
1840
1841 if (unlikely(netif_msg_rx_status(sky2)))
1842 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1843 dev->name, sky2->rx_next, status, length);
1844
1845 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1846 prefetch(sky2->rx_ring + sky2->rx_next);
1847
1848 if (status & GMR_FS_ANY_ERR)
1849 goto error;
1850
1851 if (!(status & GMR_FS_RX_OK))
1852 goto resubmit;
1853
1854 if (length > dev->mtu + ETH_HLEN)
1855 goto oversize;
1856
1857 if (length < copybreak) {
1858 skb = netdev_alloc_skb(dev, length + 2);
1859 if (!skb)
1860 goto resubmit;
1861
1862 skb_reserve(skb, 2);
1863 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1864 length, PCI_DMA_FROMDEVICE);
1865 memcpy(skb->data, re->skb->data, length);
1866 skb->ip_summed = re->skb->ip_summed;
1867 skb->csum = re->skb->csum;
1868 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1869 length, PCI_DMA_FROMDEVICE);
1870 } else {
1871 struct sk_buff *nskb;
1872
1873 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
1874 if (!nskb)
1875 goto resubmit;
1876
1877 skb = re->skb;
1878 re->skb = nskb;
1879 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1880 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1881 prefetch(skb->data);
1882
1883 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1884 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1885 }
1886
1887 skb_put(skb, length);
1888 resubmit:
1889 re->skb->ip_summed = CHECKSUM_NONE;
1890 sky2_rx_add(sky2, re->mapaddr);
1891
1892 return skb;
1893
1894 oversize:
1895 ++sky2->net_stats.rx_over_errors;
1896 goto resubmit;
1897
1898 error:
1899 ++sky2->net_stats.rx_errors;
1900
1901 if (netif_msg_rx_err(sky2) && net_ratelimit())
1902 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1903 dev->name, status, length);
1904
1905 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1906 sky2->net_stats.rx_length_errors++;
1907 if (status & GMR_FS_FRAGMENT)
1908 sky2->net_stats.rx_frame_errors++;
1909 if (status & GMR_FS_CRC_ERR)
1910 sky2->net_stats.rx_crc_errors++;
1911 if (status & GMR_FS_RX_FF_OV)
1912 sky2->net_stats.rx_fifo_errors++;
1913
1914 goto resubmit;
1915 }
1916
1917 /* Transmit complete */
1918 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1919 {
1920 struct sky2_port *sky2 = netdev_priv(dev);
1921
1922 if (netif_running(dev)) {
1923 spin_lock(&sky2->tx_lock);
1924 sky2_tx_complete(sky2, last);
1925 spin_unlock(&sky2->tx_lock);
1926 }
1927 }
1928
1929 /* Process status response ring */
1930 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1931 {
1932 struct sky2_port *sky2;
1933 int work_done = 0;
1934 unsigned buf_write[2] = { 0, 0 };
1935 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1936
1937 rmb();
1938
1939 while (hw->st_idx != hwidx) {
1940 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1941 struct net_device *dev;
1942 struct sk_buff *skb;
1943 u32 status;
1944 u16 length;
1945
1946 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1947
1948 BUG_ON(le->link >= 2);
1949 dev = hw->dev[le->link];
1950
1951 sky2 = netdev_priv(dev);
1952 length = le16_to_cpu(le->length);
1953 status = le32_to_cpu(le->status);
1954
1955 switch (le->opcode & ~HW_OWNER) {
1956 case OP_RXSTAT:
1957 skb = sky2_receive(dev, length, status);
1958 if (!skb)
1959 break;
1960
1961 skb->protocol = eth_type_trans(skb, dev);
1962 dev->last_rx = jiffies;
1963
1964 #ifdef SKY2_VLAN_TAG_USED
1965 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1966 vlan_hwaccel_receive_skb(skb,
1967 sky2->vlgrp,
1968 be16_to_cpu(sky2->rx_tag));
1969 } else
1970 #endif
1971 netif_receive_skb(skb);
1972
1973 /* Update receiver after 16 frames */
1974 if (++buf_write[le->link] == RX_BUF_WRITE) {
1975 sky2_put_idx(hw, rxqaddr[le->link],
1976 sky2->rx_put);
1977 buf_write[le->link] = 0;
1978 }
1979
1980 /* Stop after net poll weight */
1981 if (++work_done >= to_do)
1982 goto exit_loop;
1983 break;
1984
1985 #ifdef SKY2_VLAN_TAG_USED
1986 case OP_RXVLAN:
1987 sky2->rx_tag = length;
1988 break;
1989
1990 case OP_RXCHKSVLAN:
1991 sky2->rx_tag = length;
1992 /* fall through */
1993 #endif
1994 case OP_RXCHKS:
1995 skb = sky2->rx_ring[sky2->rx_next].skb;
1996 skb->ip_summed = CHECKSUM_COMPLETE;
1997 skb->csum = status & 0xffff;
1998 break;
1999
2000 case OP_TXINDEXLE:
2001 /* TX index reports status for both ports */
2002 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2003 sky2_tx_done(hw->dev[0], status & 0xfff);
2004 if (hw->dev[1])
2005 sky2_tx_done(hw->dev[1],
2006 ((status >> 24) & 0xff)
2007 | (u16)(length & 0xf) << 8);
2008 break;
2009
2010 default:
2011 if (net_ratelimit())
2012 printk(KERN_WARNING PFX
2013 "unknown status opcode 0x%x\n", le->opcode);
2014 goto exit_loop;
2015 }
2016 }
2017
2018 /* Fully processed status ring so clear irq */
2019 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2020
2021 exit_loop:
2022 if (buf_write[0]) {
2023 sky2 = netdev_priv(hw->dev[0]);
2024 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2025 }
2026
2027 if (buf_write[1]) {
2028 sky2 = netdev_priv(hw->dev[1]);
2029 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2030 }
2031
2032 return work_done;
2033 }
2034
2035 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2036 {
2037 struct net_device *dev = hw->dev[port];
2038
2039 if (net_ratelimit())
2040 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2041 dev->name, status);
2042
2043 if (status & Y2_IS_PAR_RD1) {
2044 if (net_ratelimit())
2045 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2046 dev->name);
2047 /* Clear IRQ */
2048 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2049 }
2050
2051 if (status & Y2_IS_PAR_WR1) {
2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2054 dev->name);
2055
2056 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2057 }
2058
2059 if (status & Y2_IS_PAR_MAC1) {
2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2062 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2063 }
2064
2065 if (status & Y2_IS_PAR_RX1) {
2066 if (net_ratelimit())
2067 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2068 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2069 }
2070
2071 if (status & Y2_IS_TCP_TXA1) {
2072 if (net_ratelimit())
2073 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2074 dev->name);
2075 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2076 }
2077 }
2078
2079 static void sky2_hw_intr(struct sky2_hw *hw)
2080 {
2081 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2082
2083 if (status & Y2_IS_TIST_OV)
2084 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2085
2086 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2087 u16 pci_err;
2088
2089 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2090 if (net_ratelimit())
2091 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2092 pci_name(hw->pdev), pci_err);
2093
2094 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2095 sky2_pci_write16(hw, PCI_STATUS,
2096 pci_err | PCI_STATUS_ERROR_BITS);
2097 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2098 }
2099
2100 if (status & Y2_IS_PCI_EXP) {
2101 /* PCI-Express uncorrectable Error occurred */
2102 u32 pex_err;
2103
2104 pex_err = sky2_pci_read32(hw,
2105 hw->err_cap + PCI_ERR_UNCOR_STATUS);
2106
2107 if (net_ratelimit())
2108 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2109 pci_name(hw->pdev), pex_err);
2110
2111 /* clear the interrupt */
2112 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2113 sky2_pci_write32(hw,
2114 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2115 0xffffffffUL);
2116 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2117
2118
2119 /* In case of fatal error mask off to keep from getting stuck */
2120 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2121 | PCI_ERR_UNC_DLP)) {
2122 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2123 hwmsk &= ~Y2_IS_PCI_EXP;
2124 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2125 }
2126
2127 }
2128
2129 if (status & Y2_HWE_L1_MASK)
2130 sky2_hw_error(hw, 0, status);
2131 status >>= 8;
2132 if (status & Y2_HWE_L1_MASK)
2133 sky2_hw_error(hw, 1, status);
2134 }
2135
2136 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2137 {
2138 struct net_device *dev = hw->dev[port];
2139 struct sky2_port *sky2 = netdev_priv(dev);
2140 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2141
2142 if (netif_msg_intr(sky2))
2143 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2144 dev->name, status);
2145
2146 if (status & GM_IS_RX_FF_OR) {
2147 ++sky2->net_stats.rx_fifo_errors;
2148 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2149 }
2150
2151 if (status & GM_IS_TX_FF_UR) {
2152 ++sky2->net_stats.tx_fifo_errors;
2153 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2154 }
2155 }
2156
2157 /* This should never happen it is a fatal situation */
2158 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2159 const char *rxtx, u32 mask)
2160 {
2161 struct net_device *dev = hw->dev[port];
2162 struct sky2_port *sky2 = netdev_priv(dev);
2163 u32 imask;
2164
2165 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2166 dev ? dev->name : "<not registered>", rxtx);
2167
2168 imask = sky2_read32(hw, B0_IMSK);
2169 imask &= ~mask;
2170 sky2_write32(hw, B0_IMSK, imask);
2171
2172 if (dev) {
2173 spin_lock(&sky2->phy_lock);
2174 sky2_link_down(sky2);
2175 spin_unlock(&sky2->phy_lock);
2176 }
2177 }
2178
2179 /* If idle then force a fake soft NAPI poll once a second
2180 * to work around cases where sharing an edge triggered interrupt.
2181 */
2182 static inline void sky2_idle_start(struct sky2_hw *hw)
2183 {
2184 if (idle_timeout > 0)
2185 mod_timer(&hw->idle_timer,
2186 jiffies + msecs_to_jiffies(idle_timeout));
2187 }
2188
2189 static void sky2_idle(unsigned long arg)
2190 {
2191 struct sky2_hw *hw = (struct sky2_hw *) arg;
2192 struct net_device *dev = hw->dev[0];
2193
2194 if (__netif_rx_schedule_prep(dev))
2195 __netif_rx_schedule(dev);
2196
2197 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2198 }
2199
2200
2201 static int sky2_poll(struct net_device *dev0, int *budget)
2202 {
2203 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2204 int work_limit = min(dev0->quota, *budget);
2205 int work_done = 0;
2206 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2207
2208 if (status & Y2_IS_HW_ERR)
2209 sky2_hw_intr(hw);
2210
2211 if (status & Y2_IS_IRQ_PHY1)
2212 sky2_phy_intr(hw, 0);
2213
2214 if (status & Y2_IS_IRQ_PHY2)
2215 sky2_phy_intr(hw, 1);
2216
2217 if (status & Y2_IS_IRQ_MAC1)
2218 sky2_mac_intr(hw, 0);
2219
2220 if (status & Y2_IS_IRQ_MAC2)
2221 sky2_mac_intr(hw, 1);
2222
2223 if (status & Y2_IS_CHK_RX1)
2224 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2225
2226 if (status & Y2_IS_CHK_RX2)
2227 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2228
2229 if (status & Y2_IS_CHK_TXA1)
2230 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2231
2232 if (status & Y2_IS_CHK_TXA2)
2233 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2234
2235 work_done = sky2_status_intr(hw, work_limit);
2236 if (work_done < work_limit) {
2237 netif_rx_complete(dev0);
2238
2239 sky2_read32(hw, B0_Y2_SP_LISR);
2240 return 0;
2241 } else {
2242 *budget -= work_done;
2243 dev0->quota -= work_done;
2244 return 1;
2245 }
2246 }
2247
2248 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2249 {
2250 struct sky2_hw *hw = dev_id;
2251 struct net_device *dev0 = hw->dev[0];
2252 u32 status;
2253
2254 /* Reading this mask interrupts as side effect */
2255 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2256 if (status == 0 || status == ~0)
2257 return IRQ_NONE;
2258
2259 prefetch(&hw->st_le[hw->st_idx]);
2260 if (likely(__netif_rx_schedule_prep(dev0)))
2261 __netif_rx_schedule(dev0);
2262
2263 return IRQ_HANDLED;
2264 }
2265
2266 #ifdef CONFIG_NET_POLL_CONTROLLER
2267 static void sky2_netpoll(struct net_device *dev)
2268 {
2269 struct sky2_port *sky2 = netdev_priv(dev);
2270 struct net_device *dev0 = sky2->hw->dev[0];
2271
2272 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2273 __netif_rx_schedule(dev0);
2274 }
2275 #endif
2276
2277 /* Chip internal frequency for clock calculations */
2278 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2279 {
2280 switch (hw->chip_id) {
2281 case CHIP_ID_YUKON_EC:
2282 case CHIP_ID_YUKON_EC_U:
2283 return 125; /* 125 Mhz */
2284 case CHIP_ID_YUKON_FE:
2285 return 100; /* 100 Mhz */
2286 default: /* YUKON_XL */
2287 return 156; /* 156 Mhz */
2288 }
2289 }
2290
2291 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2292 {
2293 return sky2_mhz(hw) * us;
2294 }
2295
2296 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2297 {
2298 return clk / sky2_mhz(hw);
2299 }
2300
2301
2302 static int sky2_reset(struct sky2_hw *hw)
2303 {
2304 u16 status;
2305 u8 t8;
2306 int i;
2307 u32 msk;
2308
2309 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2310
2311 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2312 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2313 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2314 pci_name(hw->pdev), hw->chip_id);
2315 return -EOPNOTSUPP;
2316 }
2317
2318 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2319
2320 /* This rev is really old, and requires untested workarounds */
2321 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2322 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2323 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2324 hw->chip_id, hw->chip_rev);
2325 return -EOPNOTSUPP;
2326 }
2327
2328 /* disable ASF */
2329 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2330 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2331 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2332 }
2333
2334 /* do a SW reset */
2335 sky2_write8(hw, B0_CTST, CS_RST_SET);
2336 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2337
2338 /* clear PCI errors, if any */
2339 status = sky2_pci_read16(hw, PCI_STATUS);
2340
2341 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2342 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2343
2344
2345 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2346
2347 /* clear any PEX errors */
2348 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2349 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
2350 if (hw->err_cap)
2351 sky2_pci_write32(hw,
2352 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2353 0xffffffffUL);
2354 }
2355
2356 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2357 hw->ports = 1;
2358 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2359 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2360 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2361 ++hw->ports;
2362 }
2363
2364 sky2_set_power_state(hw, PCI_D0);
2365
2366 for (i = 0; i < hw->ports; i++) {
2367 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2368 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2369 }
2370
2371 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2372
2373 /* Clear I2C IRQ noise */
2374 sky2_write32(hw, B2_I2C_IRQ, 1);
2375
2376 /* turn off hardware timer (unused) */
2377 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2378 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2379
2380 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2381
2382 /* Turn off descriptor polling */
2383 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2384
2385 /* Turn off receive timestamp */
2386 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2387 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2388
2389 /* enable the Tx Arbiters */
2390 for (i = 0; i < hw->ports; i++)
2391 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2392
2393 /* Initialize ram interface */
2394 for (i = 0; i < hw->ports; i++) {
2395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2396
2397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2409 }
2410
2411 msk = Y2_HWE_ALL_MASK;
2412 if (!hw->err_cap)
2413 msk &= ~Y2_IS_PCI_EXP;
2414 sky2_write32(hw, B0_HWE_IMSK, msk);
2415
2416 for (i = 0; i < hw->ports; i++)
2417 sky2_gmac_reset(hw, i);
2418
2419 memset(hw->st_le, 0, STATUS_LE_BYTES);
2420 hw->st_idx = 0;
2421
2422 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2423 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2424
2425 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2426 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2427
2428 /* Set the list last index */
2429 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2430
2431 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2432 sky2_write8(hw, STAT_FIFO_WM, 16);
2433
2434 /* set Status-FIFO ISR watermark */
2435 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2436 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2437 else
2438 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2439
2440 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2441 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2442 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2443
2444 /* enable status unit */
2445 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2446
2447 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2448 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2449 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2450
2451 return 0;
2452 }
2453
2454 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2455 {
2456 if (sky2_is_copper(hw)) {
2457 u32 modes = SUPPORTED_10baseT_Half
2458 | SUPPORTED_10baseT_Full
2459 | SUPPORTED_100baseT_Half
2460 | SUPPORTED_100baseT_Full
2461 | SUPPORTED_Autoneg | SUPPORTED_TP;
2462
2463 if (hw->chip_id != CHIP_ID_YUKON_FE)
2464 modes |= SUPPORTED_1000baseT_Half
2465 | SUPPORTED_1000baseT_Full;
2466 return modes;
2467 } else
2468 return SUPPORTED_1000baseT_Half
2469 | SUPPORTED_1000baseT_Full
2470 | SUPPORTED_Autoneg
2471 | SUPPORTED_FIBRE;
2472 }
2473
2474 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2475 {
2476 struct sky2_port *sky2 = netdev_priv(dev);
2477 struct sky2_hw *hw = sky2->hw;
2478
2479 ecmd->transceiver = XCVR_INTERNAL;
2480 ecmd->supported = sky2_supported_modes(hw);
2481 ecmd->phy_address = PHY_ADDR_MARV;
2482 if (sky2_is_copper(hw)) {
2483 ecmd->supported = SUPPORTED_10baseT_Half
2484 | SUPPORTED_10baseT_Full
2485 | SUPPORTED_100baseT_Half
2486 | SUPPORTED_100baseT_Full
2487 | SUPPORTED_1000baseT_Half
2488 | SUPPORTED_1000baseT_Full
2489 | SUPPORTED_Autoneg | SUPPORTED_TP;
2490 ecmd->port = PORT_TP;
2491 ecmd->speed = sky2->speed;
2492 } else {
2493 ecmd->speed = SPEED_1000;
2494 ecmd->port = PORT_FIBRE;
2495 }
2496
2497 ecmd->advertising = sky2->advertising;
2498 ecmd->autoneg = sky2->autoneg;
2499 ecmd->duplex = sky2->duplex;
2500 return 0;
2501 }
2502
2503 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2504 {
2505 struct sky2_port *sky2 = netdev_priv(dev);
2506 const struct sky2_hw *hw = sky2->hw;
2507 u32 supported = sky2_supported_modes(hw);
2508
2509 if (ecmd->autoneg == AUTONEG_ENABLE) {
2510 ecmd->advertising = supported;
2511 sky2->duplex = -1;
2512 sky2->speed = -1;
2513 } else {
2514 u32 setting;
2515
2516 switch (ecmd->speed) {
2517 case SPEED_1000:
2518 if (ecmd->duplex == DUPLEX_FULL)
2519 setting = SUPPORTED_1000baseT_Full;
2520 else if (ecmd->duplex == DUPLEX_HALF)
2521 setting = SUPPORTED_1000baseT_Half;
2522 else
2523 return -EINVAL;
2524 break;
2525 case SPEED_100:
2526 if (ecmd->duplex == DUPLEX_FULL)
2527 setting = SUPPORTED_100baseT_Full;
2528 else if (ecmd->duplex == DUPLEX_HALF)
2529 setting = SUPPORTED_100baseT_Half;
2530 else
2531 return -EINVAL;
2532 break;
2533
2534 case SPEED_10:
2535 if (ecmd->duplex == DUPLEX_FULL)
2536 setting = SUPPORTED_10baseT_Full;
2537 else if (ecmd->duplex == DUPLEX_HALF)
2538 setting = SUPPORTED_10baseT_Half;
2539 else
2540 return -EINVAL;
2541 break;
2542 default:
2543 return -EINVAL;
2544 }
2545
2546 if ((setting & supported) == 0)
2547 return -EINVAL;
2548
2549 sky2->speed = ecmd->speed;
2550 sky2->duplex = ecmd->duplex;
2551 }
2552
2553 sky2->autoneg = ecmd->autoneg;
2554 sky2->advertising = ecmd->advertising;
2555
2556 if (netif_running(dev))
2557 sky2_phy_reinit(sky2);
2558
2559 return 0;
2560 }
2561
2562 static void sky2_get_drvinfo(struct net_device *dev,
2563 struct ethtool_drvinfo *info)
2564 {
2565 struct sky2_port *sky2 = netdev_priv(dev);
2566
2567 strcpy(info->driver, DRV_NAME);
2568 strcpy(info->version, DRV_VERSION);
2569 strcpy(info->fw_version, "N/A");
2570 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2571 }
2572
2573 static const struct sky2_stat {
2574 char name[ETH_GSTRING_LEN];
2575 u16 offset;
2576 } sky2_stats[] = {
2577 { "tx_bytes", GM_TXO_OK_HI },
2578 { "rx_bytes", GM_RXO_OK_HI },
2579 { "tx_broadcast", GM_TXF_BC_OK },
2580 { "rx_broadcast", GM_RXF_BC_OK },
2581 { "tx_multicast", GM_TXF_MC_OK },
2582 { "rx_multicast", GM_RXF_MC_OK },
2583 { "tx_unicast", GM_TXF_UC_OK },
2584 { "rx_unicast", GM_RXF_UC_OK },
2585 { "tx_mac_pause", GM_TXF_MPAUSE },
2586 { "rx_mac_pause", GM_RXF_MPAUSE },
2587 { "collisions", GM_TXF_COL },
2588 { "late_collision",GM_TXF_LAT_COL },
2589 { "aborted", GM_TXF_ABO_COL },
2590 { "single_collisions", GM_TXF_SNG_COL },
2591 { "multi_collisions", GM_TXF_MUL_COL },
2592
2593 { "rx_short", GM_RXF_SHT },
2594 { "rx_runt", GM_RXE_FRAG },
2595 { "rx_64_byte_packets", GM_RXF_64B },
2596 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2597 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2598 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2599 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2600 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2601 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2602 { "rx_too_long", GM_RXF_LNG_ERR },
2603 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2604 { "rx_jabber", GM_RXF_JAB_PKT },
2605 { "rx_fcs_error", GM_RXF_FCS_ERR },
2606
2607 { "tx_64_byte_packets", GM_TXF_64B },
2608 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2609 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2610 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2611 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2612 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2613 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2614 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2615 };
2616
2617 static u32 sky2_get_rx_csum(struct net_device *dev)
2618 {
2619 struct sky2_port *sky2 = netdev_priv(dev);
2620
2621 return sky2->rx_csum;
2622 }
2623
2624 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2625 {
2626 struct sky2_port *sky2 = netdev_priv(dev);
2627
2628 sky2->rx_csum = data;
2629
2630 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2631 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2632
2633 return 0;
2634 }
2635
2636 static u32 sky2_get_msglevel(struct net_device *netdev)
2637 {
2638 struct sky2_port *sky2 = netdev_priv(netdev);
2639 return sky2->msg_enable;
2640 }
2641
2642 static int sky2_nway_reset(struct net_device *dev)
2643 {
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645
2646 if (sky2->autoneg != AUTONEG_ENABLE)
2647 return -EINVAL;
2648
2649 sky2_phy_reinit(sky2);
2650
2651 return 0;
2652 }
2653
2654 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2655 {
2656 struct sky2_hw *hw = sky2->hw;
2657 unsigned port = sky2->port;
2658 int i;
2659
2660 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2661 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2662 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2663 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2664
2665 for (i = 2; i < count; i++)
2666 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2667 }
2668
2669 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2670 {
2671 struct sky2_port *sky2 = netdev_priv(netdev);
2672 sky2->msg_enable = value;
2673 }
2674
2675 static int sky2_get_stats_count(struct net_device *dev)
2676 {
2677 return ARRAY_SIZE(sky2_stats);
2678 }
2679
2680 static void sky2_get_ethtool_stats(struct net_device *dev,
2681 struct ethtool_stats *stats, u64 * data)
2682 {
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684
2685 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2686 }
2687
2688 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2689 {
2690 int i;
2691
2692 switch (stringset) {
2693 case ETH_SS_STATS:
2694 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2695 memcpy(data + i * ETH_GSTRING_LEN,
2696 sky2_stats[i].name, ETH_GSTRING_LEN);
2697 break;
2698 }
2699 }
2700
2701 /* Use hardware MIB variables for critical path statistics and
2702 * transmit feedback not reported at interrupt.
2703 * Other errors are accounted for in interrupt handler.
2704 */
2705 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2706 {
2707 struct sky2_port *sky2 = netdev_priv(dev);
2708 u64 data[13];
2709
2710 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2711
2712 sky2->net_stats.tx_bytes = data[0];
2713 sky2->net_stats.rx_bytes = data[1];
2714 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2715 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2716 sky2->net_stats.multicast = data[3] + data[5];
2717 sky2->net_stats.collisions = data[10];
2718 sky2->net_stats.tx_aborted_errors = data[12];
2719
2720 return &sky2->net_stats;
2721 }
2722
2723 static int sky2_set_mac_address(struct net_device *dev, void *p)
2724 {
2725 struct sky2_port *sky2 = netdev_priv(dev);
2726 struct sky2_hw *hw = sky2->hw;
2727 unsigned port = sky2->port;
2728 const struct sockaddr *addr = p;
2729
2730 if (!is_valid_ether_addr(addr->sa_data))
2731 return -EADDRNOTAVAIL;
2732
2733 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2734 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2735 dev->dev_addr, ETH_ALEN);
2736 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2737 dev->dev_addr, ETH_ALEN);
2738
2739 /* virtual address for data */
2740 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2741
2742 /* physical address: used for pause frames */
2743 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2744
2745 return 0;
2746 }
2747
2748 static void sky2_set_multicast(struct net_device *dev)
2749 {
2750 struct sky2_port *sky2 = netdev_priv(dev);
2751 struct sky2_hw *hw = sky2->hw;
2752 unsigned port = sky2->port;
2753 struct dev_mc_list *list = dev->mc_list;
2754 u16 reg;
2755 u8 filter[8];
2756
2757 memset(filter, 0, sizeof(filter));
2758
2759 reg = gma_read16(hw, port, GM_RX_CTRL);
2760 reg |= GM_RXCR_UCF_ENA;
2761
2762 if (dev->flags & IFF_PROMISC) /* promiscuous */
2763 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2764 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2765 memset(filter, 0xff, sizeof(filter));
2766 else if (dev->mc_count == 0) /* no multicast */
2767 reg &= ~GM_RXCR_MCF_ENA;
2768 else {
2769 int i;
2770 reg |= GM_RXCR_MCF_ENA;
2771
2772 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2773 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2774 filter[bit / 8] |= 1 << (bit % 8);
2775 }
2776 }
2777
2778 gma_write16(hw, port, GM_MC_ADDR_H1,
2779 (u16) filter[0] | ((u16) filter[1] << 8));
2780 gma_write16(hw, port, GM_MC_ADDR_H2,
2781 (u16) filter[2] | ((u16) filter[3] << 8));
2782 gma_write16(hw, port, GM_MC_ADDR_H3,
2783 (u16) filter[4] | ((u16) filter[5] << 8));
2784 gma_write16(hw, port, GM_MC_ADDR_H4,
2785 (u16) filter[6] | ((u16) filter[7] << 8));
2786
2787 gma_write16(hw, port, GM_RX_CTRL, reg);
2788 }
2789
2790 /* Can have one global because blinking is controlled by
2791 * ethtool and that is always under RTNL mutex
2792 */
2793 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2794 {
2795 u16 pg;
2796
2797 switch (hw->chip_id) {
2798 case CHIP_ID_YUKON_XL:
2799 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2800 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2801 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2802 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2803 PHY_M_LEDC_INIT_CTRL(7) |
2804 PHY_M_LEDC_STA1_CTRL(7) |
2805 PHY_M_LEDC_STA0_CTRL(7))
2806 : 0);
2807
2808 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2809 break;
2810
2811 default:
2812 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2813 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2814 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2815 PHY_M_LED_MO_10(MO_LED_ON) |
2816 PHY_M_LED_MO_100(MO_LED_ON) |
2817 PHY_M_LED_MO_1000(MO_LED_ON) |
2818 PHY_M_LED_MO_RX(MO_LED_ON)
2819 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2820 PHY_M_LED_MO_10(MO_LED_OFF) |
2821 PHY_M_LED_MO_100(MO_LED_OFF) |
2822 PHY_M_LED_MO_1000(MO_LED_OFF) |
2823 PHY_M_LED_MO_RX(MO_LED_OFF));
2824
2825 }
2826 }
2827
2828 /* blink LED's for finding board */
2829 static int sky2_phys_id(struct net_device *dev, u32 data)
2830 {
2831 struct sky2_port *sky2 = netdev_priv(dev);
2832 struct sky2_hw *hw = sky2->hw;
2833 unsigned port = sky2->port;
2834 u16 ledctrl, ledover = 0;
2835 long ms;
2836 int interrupted;
2837 int onoff = 1;
2838
2839 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2840 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2841 else
2842 ms = data * 1000;
2843
2844 /* save initial values */
2845 spin_lock_bh(&sky2->phy_lock);
2846 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2847 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2848 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2849 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2850 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2851 } else {
2852 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2853 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2854 }
2855
2856 interrupted = 0;
2857 while (!interrupted && ms > 0) {
2858 sky2_led(hw, port, onoff);
2859 onoff = !onoff;
2860
2861 spin_unlock_bh(&sky2->phy_lock);
2862 interrupted = msleep_interruptible(250);
2863 spin_lock_bh(&sky2->phy_lock);
2864
2865 ms -= 250;
2866 }
2867
2868 /* resume regularly scheduled programming */
2869 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2870 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2871 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2872 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2873 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2874 } else {
2875 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2876 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2877 }
2878 spin_unlock_bh(&sky2->phy_lock);
2879
2880 return 0;
2881 }
2882
2883 static void sky2_get_pauseparam(struct net_device *dev,
2884 struct ethtool_pauseparam *ecmd)
2885 {
2886 struct sky2_port *sky2 = netdev_priv(dev);
2887
2888 ecmd->tx_pause = sky2->tx_pause;
2889 ecmd->rx_pause = sky2->rx_pause;
2890 ecmd->autoneg = sky2->autoneg;
2891 }
2892
2893 static int sky2_set_pauseparam(struct net_device *dev,
2894 struct ethtool_pauseparam *ecmd)
2895 {
2896 struct sky2_port *sky2 = netdev_priv(dev);
2897
2898 sky2->autoneg = ecmd->autoneg;
2899 sky2->tx_pause = ecmd->tx_pause != 0;
2900 sky2->rx_pause = ecmd->rx_pause != 0;
2901
2902 sky2_phy_reinit(sky2);
2903
2904 return 0;
2905 }
2906
2907 static int sky2_get_coalesce(struct net_device *dev,
2908 struct ethtool_coalesce *ecmd)
2909 {
2910 struct sky2_port *sky2 = netdev_priv(dev);
2911 struct sky2_hw *hw = sky2->hw;
2912
2913 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2914 ecmd->tx_coalesce_usecs = 0;
2915 else {
2916 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2917 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2918 }
2919 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2920
2921 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2922 ecmd->rx_coalesce_usecs = 0;
2923 else {
2924 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2925 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2926 }
2927 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2928
2929 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2930 ecmd->rx_coalesce_usecs_irq = 0;
2931 else {
2932 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2933 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2934 }
2935
2936 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2937
2938 return 0;
2939 }
2940
2941 /* Note: this affect both ports */
2942 static int sky2_set_coalesce(struct net_device *dev,
2943 struct ethtool_coalesce *ecmd)
2944 {
2945 struct sky2_port *sky2 = netdev_priv(dev);
2946 struct sky2_hw *hw = sky2->hw;
2947 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2948
2949 if (ecmd->tx_coalesce_usecs > tmax ||
2950 ecmd->rx_coalesce_usecs > tmax ||
2951 ecmd->rx_coalesce_usecs_irq > tmax)
2952 return -EINVAL;
2953
2954 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2955 return -EINVAL;
2956 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2957 return -EINVAL;
2958 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2959 return -EINVAL;
2960
2961 if (ecmd->tx_coalesce_usecs == 0)
2962 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2963 else {
2964 sky2_write32(hw, STAT_TX_TIMER_INI,
2965 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2966 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2967 }
2968 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2969
2970 if (ecmd->rx_coalesce_usecs == 0)
2971 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2972 else {
2973 sky2_write32(hw, STAT_LEV_TIMER_INI,
2974 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2975 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2976 }
2977 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2978
2979 if (ecmd->rx_coalesce_usecs_irq == 0)
2980 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2981 else {
2982 sky2_write32(hw, STAT_ISR_TIMER_INI,
2983 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2984 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2985 }
2986 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2987 return 0;
2988 }
2989
2990 static void sky2_get_ringparam(struct net_device *dev,
2991 struct ethtool_ringparam *ering)
2992 {
2993 struct sky2_port *sky2 = netdev_priv(dev);
2994
2995 ering->rx_max_pending = RX_MAX_PENDING;
2996 ering->rx_mini_max_pending = 0;
2997 ering->rx_jumbo_max_pending = 0;
2998 ering->tx_max_pending = TX_RING_SIZE - 1;
2999
3000 ering->rx_pending = sky2->rx_pending;
3001 ering->rx_mini_pending = 0;
3002 ering->rx_jumbo_pending = 0;
3003 ering->tx_pending = sky2->tx_pending;
3004 }
3005
3006 static int sky2_set_ringparam(struct net_device *dev,
3007 struct ethtool_ringparam *ering)
3008 {
3009 struct sky2_port *sky2 = netdev_priv(dev);
3010 int err = 0;
3011
3012 if (ering->rx_pending > RX_MAX_PENDING ||
3013 ering->rx_pending < 8 ||
3014 ering->tx_pending < MAX_SKB_TX_LE ||
3015 ering->tx_pending > TX_RING_SIZE - 1)
3016 return -EINVAL;
3017
3018 if (netif_running(dev))
3019 sky2_down(dev);
3020
3021 sky2->rx_pending = ering->rx_pending;
3022 sky2->tx_pending = ering->tx_pending;
3023
3024 if (netif_running(dev)) {
3025 err = sky2_up(dev);
3026 if (err)
3027 dev_close(dev);
3028 else
3029 sky2_set_multicast(dev);
3030 }
3031
3032 return err;
3033 }
3034
3035 static int sky2_get_regs_len(struct net_device *dev)
3036 {
3037 return 0x4000;
3038 }
3039
3040 /*
3041 * Returns copy of control register region
3042 * Note: access to the RAM address register set will cause timeouts.
3043 */
3044 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3045 void *p)
3046 {
3047 const struct sky2_port *sky2 = netdev_priv(dev);
3048 const void __iomem *io = sky2->hw->regs;
3049
3050 BUG_ON(regs->len < B3_RI_WTO_R1);
3051 regs->version = 1;
3052 memset(p, 0, regs->len);
3053
3054 memcpy_fromio(p, io, B3_RAM_ADDR);
3055
3056 memcpy_fromio(p + B3_RI_WTO_R1,
3057 io + B3_RI_WTO_R1,
3058 regs->len - B3_RI_WTO_R1);
3059 }
3060
3061 static const struct ethtool_ops sky2_ethtool_ops = {
3062 .get_settings = sky2_get_settings,
3063 .set_settings = sky2_set_settings,
3064 .get_drvinfo = sky2_get_drvinfo,
3065 .get_msglevel = sky2_get_msglevel,
3066 .set_msglevel = sky2_set_msglevel,
3067 .nway_reset = sky2_nway_reset,
3068 .get_regs_len = sky2_get_regs_len,
3069 .get_regs = sky2_get_regs,
3070 .get_link = ethtool_op_get_link,
3071 .get_sg = ethtool_op_get_sg,
3072 .set_sg = ethtool_op_set_sg,
3073 .get_tx_csum = ethtool_op_get_tx_csum,
3074 .set_tx_csum = ethtool_op_set_tx_csum,
3075 .get_tso = ethtool_op_get_tso,
3076 .set_tso = ethtool_op_set_tso,
3077 .get_rx_csum = sky2_get_rx_csum,
3078 .set_rx_csum = sky2_set_rx_csum,
3079 .get_strings = sky2_get_strings,
3080 .get_coalesce = sky2_get_coalesce,
3081 .set_coalesce = sky2_set_coalesce,
3082 .get_ringparam = sky2_get_ringparam,
3083 .set_ringparam = sky2_set_ringparam,
3084 .get_pauseparam = sky2_get_pauseparam,
3085 .set_pauseparam = sky2_set_pauseparam,
3086 .phys_id = sky2_phys_id,
3087 .get_stats_count = sky2_get_stats_count,
3088 .get_ethtool_stats = sky2_get_ethtool_stats,
3089 .get_perm_addr = ethtool_op_get_perm_addr,
3090 };
3091
3092 /* Initialize network device */
3093 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3094 unsigned port, int highmem)
3095 {
3096 struct sky2_port *sky2;
3097 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3098
3099 if (!dev) {
3100 printk(KERN_ERR "sky2 etherdev alloc failed");
3101 return NULL;
3102 }
3103
3104 SET_MODULE_OWNER(dev);
3105 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3106 dev->irq = hw->pdev->irq;
3107 dev->open = sky2_up;
3108 dev->stop = sky2_down;
3109 dev->do_ioctl = sky2_ioctl;
3110 dev->hard_start_xmit = sky2_xmit_frame;
3111 dev->get_stats = sky2_get_stats;
3112 dev->set_multicast_list = sky2_set_multicast;
3113 dev->set_mac_address = sky2_set_mac_address;
3114 dev->change_mtu = sky2_change_mtu;
3115 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3116 dev->tx_timeout = sky2_tx_timeout;
3117 dev->watchdog_timeo = TX_WATCHDOG;
3118 if (port == 0)
3119 dev->poll = sky2_poll;
3120 dev->weight = NAPI_WEIGHT;
3121 #ifdef CONFIG_NET_POLL_CONTROLLER
3122 dev->poll_controller = sky2_netpoll;
3123 #endif
3124
3125 sky2 = netdev_priv(dev);
3126 sky2->netdev = dev;
3127 sky2->hw = hw;
3128 sky2->msg_enable = netif_msg_init(debug, default_msg);
3129
3130 spin_lock_init(&sky2->tx_lock);
3131 /* Auto speed and flow control */
3132 sky2->autoneg = AUTONEG_ENABLE;
3133 sky2->tx_pause = 1;
3134 sky2->rx_pause = 1;
3135 sky2->duplex = -1;
3136 sky2->speed = -1;
3137 sky2->advertising = sky2_supported_modes(hw);
3138 sky2->rx_csum = 1;
3139
3140 spin_lock_init(&sky2->phy_lock);
3141 sky2->tx_pending = TX_DEF_PENDING;
3142 sky2->rx_pending = RX_DEF_PENDING;
3143 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3144
3145 hw->dev[port] = dev;
3146
3147 sky2->port = port;
3148
3149 dev->features |= NETIF_F_LLTX;
3150 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3151 dev->features |= NETIF_F_TSO;
3152 if (highmem)
3153 dev->features |= NETIF_F_HIGHDMA;
3154 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3155
3156 #ifdef SKY2_VLAN_TAG_USED
3157 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3158 dev->vlan_rx_register = sky2_vlan_rx_register;
3159 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3160 #endif
3161
3162 /* read the mac address */
3163 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3164 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3165
3166 /* device is off until link detection */
3167 netif_carrier_off(dev);
3168 netif_stop_queue(dev);
3169
3170 return dev;
3171 }
3172
3173 static void __devinit sky2_show_addr(struct net_device *dev)
3174 {
3175 const struct sky2_port *sky2 = netdev_priv(dev);
3176
3177 if (netif_msg_probe(sky2))
3178 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3179 dev->name,
3180 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3181 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3182 }
3183
3184 /* Handle software interrupt used during MSI test */
3185 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3186 struct pt_regs *regs)
3187 {
3188 struct sky2_hw *hw = dev_id;
3189 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3190
3191 if (status == 0)
3192 return IRQ_NONE;
3193
3194 if (status & Y2_IS_IRQ_SW) {
3195 hw->msi_detected = 1;
3196 wake_up(&hw->msi_wait);
3197 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3198 }
3199 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3200
3201 return IRQ_HANDLED;
3202 }
3203
3204 /* Test interrupt path by forcing a a software IRQ */
3205 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3206 {
3207 struct pci_dev *pdev = hw->pdev;
3208 int err;
3209
3210 init_waitqueue_head (&hw->msi_wait);
3211
3212 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3213
3214 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3215 if (err) {
3216 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3217 pci_name(pdev), pdev->irq);
3218 return err;
3219 }
3220
3221 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3222 sky2_read8(hw, B0_CTST);
3223
3224 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3225
3226 if (!hw->msi_detected) {
3227 /* MSI test failed, go back to INTx mode */
3228 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3229 "switching to INTx mode. Please report this failure to "
3230 "the PCI maintainer and include system chipset information.\n",
3231 pci_name(pdev));
3232
3233 err = -EOPNOTSUPP;
3234 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3235 }
3236
3237 sky2_write32(hw, B0_IMSK, 0);
3238
3239 free_irq(pdev->irq, hw);
3240
3241 return err;
3242 }
3243
3244 static int __devinit sky2_probe(struct pci_dev *pdev,
3245 const struct pci_device_id *ent)
3246 {
3247 struct net_device *dev, *dev1 = NULL;
3248 struct sky2_hw *hw;
3249 int err, pm_cap, using_dac = 0;
3250
3251 err = pci_enable_device(pdev);
3252 if (err) {
3253 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3254 pci_name(pdev));
3255 goto err_out;
3256 }
3257
3258 err = pci_request_regions(pdev, DRV_NAME);
3259 if (err) {
3260 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3261 pci_name(pdev));
3262 goto err_out;
3263 }
3264
3265 pci_set_master(pdev);
3266
3267 /* Find power-management capability. */
3268 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3269 if (pm_cap == 0) {
3270 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3271 "aborting.\n");
3272 err = -EIO;
3273 goto err_out_free_regions;
3274 }
3275
3276 if (sizeof(dma_addr_t) > sizeof(u32) &&
3277 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3278 using_dac = 1;
3279 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3280 if (err < 0) {
3281 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3282 "for consistent allocations\n", pci_name(pdev));
3283 goto err_out_free_regions;
3284 }
3285
3286 } else {
3287 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3288 if (err) {
3289 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3290 pci_name(pdev));
3291 goto err_out_free_regions;
3292 }
3293 }
3294
3295 err = -ENOMEM;
3296 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3297 if (!hw) {
3298 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3299 pci_name(pdev));
3300 goto err_out_free_regions;
3301 }
3302
3303 hw->pdev = pdev;
3304
3305 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3306 if (!hw->regs) {
3307 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3308 pci_name(pdev));
3309 goto err_out_free_hw;
3310 }
3311 hw->pm_cap = pm_cap;
3312
3313 #ifdef __BIG_ENDIAN
3314 /* The sk98lin vendor driver uses hardware byte swapping but
3315 * this driver uses software swapping.
3316 */
3317 {
3318 u32 reg;
3319 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3320 reg &= ~PCI_REV_DESC;
3321 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3322 }
3323 #endif
3324
3325 /* ring for status responses */
3326 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3327 &hw->st_dma);
3328 if (!hw->st_le)
3329 goto err_out_iounmap;
3330
3331 err = sky2_reset(hw);
3332 if (err)
3333 goto err_out_iounmap;
3334
3335 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3336 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3337 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3338 hw->chip_id, hw->chip_rev);
3339
3340 dev = sky2_init_netdev(hw, 0, using_dac);
3341 if (!dev)
3342 goto err_out_free_pci;
3343
3344 err = register_netdev(dev);
3345 if (err) {
3346 printk(KERN_ERR PFX "%s: cannot register net device\n",
3347 pci_name(pdev));
3348 goto err_out_free_netdev;
3349 }
3350
3351 sky2_show_addr(dev);
3352
3353 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3354 if (register_netdev(dev1) == 0)
3355 sky2_show_addr(dev1);
3356 else {
3357 /* Failure to register second port need not be fatal */
3358 printk(KERN_WARNING PFX
3359 "register of second port failed\n");
3360 hw->dev[1] = NULL;
3361 free_netdev(dev1);
3362 }
3363 }
3364
3365 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3366 err = sky2_test_msi(hw);
3367 if (err == -EOPNOTSUPP)
3368 pci_disable_msi(pdev);
3369 else if (err)
3370 goto err_out_unregister;
3371 }
3372
3373 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
3374 if (err) {
3375 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3376 pci_name(pdev), pdev->irq);
3377 goto err_out_unregister;
3378 }
3379
3380 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3381
3382 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3383 sky2_idle_start(hw);
3384
3385 pci_set_drvdata(pdev, hw);
3386
3387 return 0;
3388
3389 err_out_unregister:
3390 pci_disable_msi(pdev);
3391 if (dev1) {
3392 unregister_netdev(dev1);
3393 free_netdev(dev1);
3394 }
3395 unregister_netdev(dev);
3396 err_out_free_netdev:
3397 free_netdev(dev);
3398 err_out_free_pci:
3399 sky2_write8(hw, B0_CTST, CS_RST_SET);
3400 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3401 err_out_iounmap:
3402 iounmap(hw->regs);
3403 err_out_free_hw:
3404 kfree(hw);
3405 err_out_free_regions:
3406 pci_release_regions(pdev);
3407 pci_disable_device(pdev);
3408 err_out:
3409 return err;
3410 }
3411
3412 static void __devexit sky2_remove(struct pci_dev *pdev)
3413 {
3414 struct sky2_hw *hw = pci_get_drvdata(pdev);
3415 struct net_device *dev0, *dev1;
3416
3417 if (!hw)
3418 return;
3419
3420 del_timer_sync(&hw->idle_timer);
3421
3422 sky2_write32(hw, B0_IMSK, 0);
3423 synchronize_irq(hw->pdev->irq);
3424
3425 dev0 = hw->dev[0];
3426 dev1 = hw->dev[1];
3427 if (dev1)
3428 unregister_netdev(dev1);
3429 unregister_netdev(dev0);
3430
3431 sky2_set_power_state(hw, PCI_D3hot);
3432 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3433 sky2_write8(hw, B0_CTST, CS_RST_SET);
3434 sky2_read8(hw, B0_CTST);
3435
3436 free_irq(pdev->irq, hw);
3437 pci_disable_msi(pdev);
3438 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3439 pci_release_regions(pdev);
3440 pci_disable_device(pdev);
3441
3442 if (dev1)
3443 free_netdev(dev1);
3444 free_netdev(dev0);
3445 iounmap(hw->regs);
3446 kfree(hw);
3447
3448 pci_set_drvdata(pdev, NULL);
3449 }
3450
3451 #ifdef CONFIG_PM
3452 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3453 {
3454 struct sky2_hw *hw = pci_get_drvdata(pdev);
3455 int i;
3456 pci_power_t pstate = pci_choose_state(pdev, state);
3457
3458 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3459 return -EINVAL;
3460
3461 del_timer_sync(&hw->idle_timer);
3462 netif_poll_disable(hw->dev[0]);
3463
3464 for (i = 0; i < hw->ports; i++) {
3465 struct net_device *dev = hw->dev[i];
3466
3467 if (netif_running(dev)) {
3468 sky2_down(dev);
3469 netif_device_detach(dev);
3470 }
3471 }
3472
3473 sky2_write32(hw, B0_IMSK, 0);
3474 pci_save_state(pdev);
3475 sky2_set_power_state(hw, pstate);
3476 return 0;
3477 }
3478
3479 static int sky2_resume(struct pci_dev *pdev)
3480 {
3481 struct sky2_hw *hw = pci_get_drvdata(pdev);
3482 int i, err;
3483
3484 pci_restore_state(pdev);
3485 pci_enable_wake(pdev, PCI_D0, 0);
3486 sky2_set_power_state(hw, PCI_D0);
3487
3488 err = sky2_reset(hw);
3489 if (err)
3490 goto out;
3491
3492 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3493
3494 for (i = 0; i < hw->ports; i++) {
3495 struct net_device *dev = hw->dev[i];
3496 if (netif_running(dev)) {
3497 netif_device_attach(dev);
3498
3499 err = sky2_up(dev);
3500 if (err) {
3501 printk(KERN_ERR PFX "%s: could not up: %d\n",
3502 dev->name, err);
3503 dev_close(dev);
3504 goto out;
3505 }
3506 }
3507 }
3508
3509 netif_poll_enable(hw->dev[0]);
3510 sky2_idle_start(hw);
3511 out:
3512 return err;
3513 }
3514 #endif
3515
3516 static struct pci_driver sky2_driver = {
3517 .name = DRV_NAME,
3518 .id_table = sky2_id_table,
3519 .probe = sky2_probe,
3520 .remove = __devexit_p(sky2_remove),
3521 #ifdef CONFIG_PM
3522 .suspend = sky2_suspend,
3523 .resume = sky2_resume,
3524 #endif
3525 };
3526
3527 static int __init sky2_init_module(void)
3528 {
3529 return pci_register_driver(&sky2_driver);
3530 }
3531
3532 static void __exit sky2_cleanup_module(void)
3533 {
3534 pci_unregister_driver(&sky2_driver);
3535 }
3536
3537 module_init(sky2_init_module);
3538 module_exit(sky2_cleanup_module);
3539
3540 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3541 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3542 MODULE_LICENSE("GPL");
3543 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)