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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/in.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
37 #include <linux/ip.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/mii.h>
42 #include <asm/irq.h>
43
44 #include "skge.h"
45
46 #define DRV_NAME "skge"
47 #define DRV_VERSION "1.6"
48 #define PFX DRV_NAME " "
49
50 #define DEFAULT_TX_RING_SIZE 128
51 #define DEFAULT_RX_RING_SIZE 512
52 #define MAX_TX_RING_SIZE 1024
53 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
54 #define MAX_RX_RING_SIZE 4096
55 #define RX_COPY_THRESHOLD 128
56 #define RX_BUF_SIZE 1536
57 #define PHY_RETRIES 1000
58 #define ETH_JUMBO_MTU 9000
59 #define TX_WATCHDOG (5 * HZ)
60 #define NAPI_WEIGHT 64
61 #define BLINK_MS 250
62
63 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65 MODULE_LICENSE("GPL");
66 MODULE_VERSION(DRV_VERSION);
67
68 static const u32 default_msg
69 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71
72 static int debug = -1; /* defaults above */
73 module_param(debug, int, 0);
74 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75
76 static const struct pci_device_id skge_id_table[] = {
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
88 { 0 }
89 };
90 MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92 static int skge_up(struct net_device *dev);
93 static int skge_down(struct net_device *dev);
94 static void skge_phy_reset(struct skge_port *skge);
95 static void skge_tx_clean(struct skge_port *skge);
96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
98 static void genesis_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_get_stats(struct skge_port *skge, u64 *data);
100 static void yukon_init(struct skge_hw *hw, int port);
101 static void genesis_mac_init(struct skge_hw *hw, int port);
102 static void genesis_link_up(struct skge_port *skge);
103
104 /* Avoid conditionals by using array */
105 static const int txqaddr[] = { Q_XA1, Q_XA2 };
106 static const int rxqaddr[] = { Q_R1, Q_R2 };
107 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
109
110 static int skge_get_regs_len(struct net_device *dev)
111 {
112 return 0x4000;
113 }
114
115 /*
116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
119 */
120 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122 {
123 const struct skge_port *skge = netdev_priv(dev);
124 const void __iomem *io = skge->hw->regs;
125
126 regs->version = 1;
127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
129
130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
132 }
133
134 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
135 static int wol_supported(const struct skge_hw *hw)
136 {
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
139 }
140
141 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142 {
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147 }
148
149 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150 {
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172 }
173
174 /* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
176 */
177 static u32 skge_supported_modes(const struct skge_hw *hw)
178 {
179 u32 supported;
180
181 if (hw->copper) {
182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
200 | SUPPORTED_Autoneg;
201
202 return supported;
203 }
204
205 static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207 {
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
212 ecmd->supported = skge_supported_modes(hw);
213
214 if (hw->copper) {
215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
217 } else
218 ecmd->port = PORT_FIBRE;
219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225 }
226
227 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228 {
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
231 u32 supported = skge_supported_modes(hw);
232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
237 } else {
238 u32 setting;
239
240 switch (ecmd->speed) {
241 case SPEED_1000:
242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
248 break;
249 case SPEED_100:
250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
258 case SPEED_10:
259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
275 }
276
277 skge->autoneg = ecmd->autoneg;
278 skge->advertising = ecmd->advertising;
279
280 if (netif_running(dev))
281 skge_phy_reset(skge);
282
283 return (0);
284 }
285
286 static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288 {
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295 }
296
297 static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301 } skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326 };
327
328 static int skge_get_stats_count(struct net_device *dev)
329 {
330 return ARRAY_SIZE(skge_stats);
331 }
332
333 static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335 {
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342 }
343
344 /* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348 static struct net_device_stats *skge_get_stats(struct net_device *dev)
349 {
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
362 skge->net_stats.multicast = data[3] + data[5];
363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367 }
368
369 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370 {
371 int i;
372
373 switch (stringset) {
374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380 }
381
382 static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384 {
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396 }
397
398 static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400 {
401 struct skge_port *skge = netdev_priv(dev);
402 int err;
403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
405 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
413 err = skge_up(dev);
414 if (err)
415 dev_close(dev);
416 }
417
418 return 0;
419 }
420
421 static u32 skge_get_msglevel(struct net_device *netdev)
422 {
423 struct skge_port *skge = netdev_priv(netdev);
424 return skge->msg_enable;
425 }
426
427 static void skge_set_msglevel(struct net_device *netdev, u32 value)
428 {
429 struct skge_port *skge = netdev_priv(netdev);
430 skge->msg_enable = value;
431 }
432
433 static int skge_nway_reset(struct net_device *dev)
434 {
435 struct skge_port *skge = netdev_priv(dev);
436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
440 skge_phy_reset(skge);
441 return 0;
442 }
443
444 static int skge_set_sg(struct net_device *dev, u32 data)
445 {
446 struct skge_port *skge = netdev_priv(dev);
447 struct skge_hw *hw = skge->hw;
448
449 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return -EOPNOTSUPP;
451 return ethtool_op_set_sg(dev, data);
452 }
453
454 static int skge_set_tx_csum(struct net_device *dev, u32 data)
455 {
456 struct skge_port *skge = netdev_priv(dev);
457 struct skge_hw *hw = skge->hw;
458
459 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return -EOPNOTSUPP;
461
462 return ethtool_op_set_tx_csum(dev, data);
463 }
464
465 static u32 skge_get_rx_csum(struct net_device *dev)
466 {
467 struct skge_port *skge = netdev_priv(dev);
468
469 return skge->rx_csum;
470 }
471
472 /* Only Yukon supports checksum offload. */
473 static int skge_set_rx_csum(struct net_device *dev, u32 data)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476
477 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 skge->rx_csum = data;
481 return 0;
482 }
483
484 static void skge_get_pauseparam(struct net_device *dev,
485 struct ethtool_pauseparam *ecmd)
486 {
487 struct skge_port *skge = netdev_priv(dev);
488
489 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
491 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
492 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
493
494 ecmd->autoneg = skge->autoneg;
495 }
496
497 static int skge_set_pauseparam(struct net_device *dev,
498 struct ethtool_pauseparam *ecmd)
499 {
500 struct skge_port *skge = netdev_priv(dev);
501
502 skge->autoneg = ecmd->autoneg;
503 if (ecmd->rx_pause && ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_SYMMETRIC;
505 else if (ecmd->rx_pause && !ecmd->tx_pause)
506 skge->flow_control = FLOW_MODE_REM_SEND;
507 else if (!ecmd->rx_pause && ecmd->tx_pause)
508 skge->flow_control = FLOW_MODE_LOC_SEND;
509 else
510 skge->flow_control = FLOW_MODE_NONE;
511
512 if (netif_running(dev))
513 skge_phy_reset(skge);
514 return 0;
515 }
516
517 /* Chip internal frequency for clock calculations */
518 static inline u32 hwkhz(const struct skge_hw *hw)
519 {
520 if (hw->chip_id == CHIP_ID_GENESIS)
521 return 53215; /* or: 53.125 MHz */
522 else
523 return 78215; /* or: 78.125 MHz */
524 }
525
526 /* Chip HZ to microseconds */
527 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
528 {
529 return (ticks * 1000) / hwkhz(hw);
530 }
531
532 /* Microseconds to chip HZ */
533 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
534 {
535 return hwkhz(hw) * usec / 1000;
536 }
537
538 static int skge_get_coalesce(struct net_device *dev,
539 struct ethtool_coalesce *ecmd)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543 int port = skge->port;
544
545 ecmd->rx_coalesce_usecs = 0;
546 ecmd->tx_coalesce_usecs = 0;
547
548 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
549 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
550 u32 msk = skge_read32(hw, B2_IRQM_MSK);
551
552 if (msk & rxirqmask[port])
553 ecmd->rx_coalesce_usecs = delay;
554 if (msk & txirqmask[port])
555 ecmd->tx_coalesce_usecs = delay;
556 }
557
558 return 0;
559 }
560
561 /* Note: interrupt timer is per board, but can turn on/off per port */
562 static int skge_set_coalesce(struct net_device *dev,
563 struct ethtool_coalesce *ecmd)
564 {
565 struct skge_port *skge = netdev_priv(dev);
566 struct skge_hw *hw = skge->hw;
567 int port = skge->port;
568 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 u32 delay = 25;
570
571 if (ecmd->rx_coalesce_usecs == 0)
572 msk &= ~rxirqmask[port];
573 else if (ecmd->rx_coalesce_usecs < 25 ||
574 ecmd->rx_coalesce_usecs > 33333)
575 return -EINVAL;
576 else {
577 msk |= rxirqmask[port];
578 delay = ecmd->rx_coalesce_usecs;
579 }
580
581 if (ecmd->tx_coalesce_usecs == 0)
582 msk &= ~txirqmask[port];
583 else if (ecmd->tx_coalesce_usecs < 25 ||
584 ecmd->tx_coalesce_usecs > 33333)
585 return -EINVAL;
586 else {
587 msk |= txirqmask[port];
588 delay = min(delay, ecmd->rx_coalesce_usecs);
589 }
590
591 skge_write32(hw, B2_IRQM_MSK, msk);
592 if (msk == 0)
593 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
594 else {
595 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
596 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
597 }
598 return 0;
599 }
600
601 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
602 static void skge_led(struct skge_port *skge, enum led_mode mode)
603 {
604 struct skge_hw *hw = skge->hw;
605 int port = skge->port;
606
607 mutex_lock(&hw->phy_mutex);
608 if (hw->chip_id == CHIP_ID_GENESIS) {
609 switch (mode) {
610 case LED_MODE_OFF:
611 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
612 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
613 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
614 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
615 break;
616
617 case LED_MODE_ON:
618 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
619 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
620
621 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
622 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
623
624 break;
625
626 case LED_MODE_TST:
627 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
628 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630
631 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
632 break;
633 }
634 } else {
635 switch (mode) {
636 case LED_MODE_OFF:
637 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
638 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
639 PHY_M_LED_MO_DUP(MO_LED_OFF) |
640 PHY_M_LED_MO_10(MO_LED_OFF) |
641 PHY_M_LED_MO_100(MO_LED_OFF) |
642 PHY_M_LED_MO_1000(MO_LED_OFF) |
643 PHY_M_LED_MO_RX(MO_LED_OFF));
644 break;
645 case LED_MODE_ON:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
647 PHY_M_LED_PULS_DUR(PULS_170MS) |
648 PHY_M_LED_BLINK_RT(BLINK_84MS) |
649 PHY_M_LEDC_TX_CTRL |
650 PHY_M_LEDC_DP_CTRL);
651
652 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
653 PHY_M_LED_MO_RX(MO_LED_OFF) |
654 (skge->speed == SPEED_100 ?
655 PHY_M_LED_MO_100(MO_LED_ON) : 0));
656 break;
657 case LED_MODE_TST:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_ON) |
661 PHY_M_LED_MO_10(MO_LED_ON) |
662 PHY_M_LED_MO_100(MO_LED_ON) |
663 PHY_M_LED_MO_1000(MO_LED_ON) |
664 PHY_M_LED_MO_RX(MO_LED_ON));
665 }
666 }
667 mutex_unlock(&hw->phy_mutex);
668 }
669
670 /* blink LED's for finding board */
671 static int skge_phys_id(struct net_device *dev, u32 data)
672 {
673 struct skge_port *skge = netdev_priv(dev);
674 unsigned long ms;
675 enum led_mode mode = LED_MODE_TST;
676
677 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
678 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
679 else
680 ms = data * 1000;
681
682 while (ms > 0) {
683 skge_led(skge, mode);
684 mode ^= LED_MODE_TST;
685
686 if (msleep_interruptible(BLINK_MS))
687 break;
688 ms -= BLINK_MS;
689 }
690
691 /* back to regular LED state */
692 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
693
694 return 0;
695 }
696
697 static struct ethtool_ops skge_ethtool_ops = {
698 .get_settings = skge_get_settings,
699 .set_settings = skge_set_settings,
700 .get_drvinfo = skge_get_drvinfo,
701 .get_regs_len = skge_get_regs_len,
702 .get_regs = skge_get_regs,
703 .get_wol = skge_get_wol,
704 .set_wol = skge_set_wol,
705 .get_msglevel = skge_get_msglevel,
706 .set_msglevel = skge_set_msglevel,
707 .nway_reset = skge_nway_reset,
708 .get_link = ethtool_op_get_link,
709 .get_ringparam = skge_get_ring_param,
710 .set_ringparam = skge_set_ring_param,
711 .get_pauseparam = skge_get_pauseparam,
712 .set_pauseparam = skge_set_pauseparam,
713 .get_coalesce = skge_get_coalesce,
714 .set_coalesce = skge_set_coalesce,
715 .get_sg = ethtool_op_get_sg,
716 .set_sg = skge_set_sg,
717 .get_tx_csum = ethtool_op_get_tx_csum,
718 .set_tx_csum = skge_set_tx_csum,
719 .get_rx_csum = skge_get_rx_csum,
720 .set_rx_csum = skge_set_rx_csum,
721 .get_strings = skge_get_strings,
722 .phys_id = skge_phys_id,
723 .get_stats_count = skge_get_stats_count,
724 .get_ethtool_stats = skge_get_ethtool_stats,
725 .get_perm_addr = ethtool_op_get_perm_addr,
726 };
727
728 /*
729 * Allocate ring elements and chain them together
730 * One-to-one association of board descriptors with ring elements
731 */
732 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
733 {
734 struct skge_tx_desc *d;
735 struct skge_element *e;
736 int i;
737
738 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
739 if (!ring->start)
740 return -ENOMEM;
741
742 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
743 e->desc = d;
744 if (i == ring->count - 1) {
745 e->next = ring->start;
746 d->next_offset = base;
747 } else {
748 e->next = e + 1;
749 d->next_offset = base + (i+1) * sizeof(*d);
750 }
751 }
752 ring->to_use = ring->to_clean = ring->start;
753
754 return 0;
755 }
756
757 /* Allocate and setup a new buffer for receiving */
758 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
759 struct sk_buff *skb, unsigned int bufsize)
760 {
761 struct skge_rx_desc *rd = e->desc;
762 u64 map;
763
764 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
765 PCI_DMA_FROMDEVICE);
766
767 rd->dma_lo = map;
768 rd->dma_hi = map >> 32;
769 e->skb = skb;
770 rd->csum1_start = ETH_HLEN;
771 rd->csum2_start = ETH_HLEN;
772 rd->csum1 = 0;
773 rd->csum2 = 0;
774
775 wmb();
776
777 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
778 pci_unmap_addr_set(e, mapaddr, map);
779 pci_unmap_len_set(e, maplen, bufsize);
780 }
781
782 /* Resume receiving using existing skb,
783 * Note: DMA address is not changed by chip.
784 * MTU not changed while receiver active.
785 */
786 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 {
788 struct skge_rx_desc *rd = e->desc;
789
790 rd->csum2 = 0;
791 rd->csum2_start = ETH_HLEN;
792
793 wmb();
794
795 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
796 }
797
798
799 /* Free all buffers in receive ring, assumes receiver stopped */
800 static void skge_rx_clean(struct skge_port *skge)
801 {
802 struct skge_hw *hw = skge->hw;
803 struct skge_ring *ring = &skge->rx_ring;
804 struct skge_element *e;
805
806 e = ring->start;
807 do {
808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
810 if (e->skb) {
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 } while ((e = e->next) != ring->start);
819 }
820
821
822 /* Allocate buffers for receive ring
823 * For receive: to_clean is next received frame.
824 */
825 static int skge_rx_fill(struct skge_port *skge)
826 {
827 struct skge_ring *ring = &skge->rx_ring;
828 struct skge_element *e;
829
830 e = ring->start;
831 do {
832 struct sk_buff *skb;
833
834 skb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_KERNEL);
835 if (!skb)
836 return -ENOMEM;
837
838 skb_reserve(skb, NET_IP_ALIGN);
839 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
840 } while ( (e = e->next) != ring->start);
841
842 ring->to_clean = ring->start;
843 return 0;
844 }
845
846 static void skge_link_up(struct skge_port *skge)
847 {
848 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
849 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850
851 netif_carrier_on(skge->netdev);
852 netif_wake_queue(skge->netdev);
853
854 if (netif_msg_link(skge))
855 printk(KERN_INFO PFX
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
863 "unknown");
864 }
865
866 static void skge_link_down(struct skge_port *skge)
867 {
868 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
869 netif_carrier_off(skge->netdev);
870 netif_stop_queue(skge->netdev);
871
872 if (netif_msg_link(skge))
873 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
874 }
875
876 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
877 {
878 int i;
879
880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
881 *val = xm_read16(hw, port, XM_PHY_DATA);
882
883 for (i = 0; i < PHY_RETRIES; i++) {
884 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
885 goto ready;
886 udelay(1);
887 }
888
889 return -ETIMEDOUT;
890 ready:
891 *val = xm_read16(hw, port, XM_PHY_DATA);
892
893 return 0;
894 }
895
896 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
897 {
898 u16 v = 0;
899 if (__xm_phy_read(hw, port, reg, &v))
900 printk(KERN_WARNING PFX "%s: phy read timed out\n",
901 hw->dev[port]->name);
902 return v;
903 }
904
905 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
906 {
907 int i;
908
909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
910 for (i = 0; i < PHY_RETRIES; i++) {
911 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
912 goto ready;
913 udelay(1);
914 }
915 return -EIO;
916
917 ready:
918 xm_write16(hw, port, XM_PHY_DATA, val);
919 for (i = 0; i < PHY_RETRIES; i++) {
920 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
921 return 0;
922 udelay(1);
923 }
924 return -ETIMEDOUT;
925 }
926
927 static void genesis_init(struct skge_hw *hw)
928 {
929 /* set blink source counter */
930 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
931 skge_write8(hw, B2_BSC_CTRL, BSC_START);
932
933 /* configure mac arbiter */
934 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
935
936 /* configure mac arbiter timeout values */
937 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
939 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
940 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
941
942 skge_write8(hw, B3_MA_RCINI_RX1, 0);
943 skge_write8(hw, B3_MA_RCINI_RX2, 0);
944 skge_write8(hw, B3_MA_RCINI_TX1, 0);
945 skge_write8(hw, B3_MA_RCINI_TX2, 0);
946
947 /* configure packet arbiter timeout */
948 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
949 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
951 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
952 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
953 }
954
955 static void genesis_reset(struct skge_hw *hw, int port)
956 {
957 const u8 zero[8] = { 0 };
958
959 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
960
961 /* reset the statistics module */
962 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
963 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
964 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
965 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
966 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
967
968 /* disable Broadcom PHY IRQ */
969 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
970
971 xm_outhash(hw, port, XM_HSM, zero);
972 }
973
974
975 /* Convert mode to MII values */
976 static const u16 phy_pause_map[] = {
977 [FLOW_MODE_NONE] = 0,
978 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
979 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
980 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
981 };
982
983
984 /* Check status of Broadcom phy link */
985 static void bcom_check_link(struct skge_hw *hw, int port)
986 {
987 struct net_device *dev = hw->dev[port];
988 struct skge_port *skge = netdev_priv(dev);
989 u16 status;
990
991 /* read twice because of latch */
992 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
993 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
994
995 if ((status & PHY_ST_LSYNC) == 0) {
996 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
997 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
998 xm_write16(hw, port, XM_MMU_CMD, cmd);
999 /* dummy read to ensure writing */
1000 (void) xm_read16(hw, port, XM_MMU_CMD);
1001
1002 if (netif_carrier_ok(dev))
1003 skge_link_down(skge);
1004 } else {
1005 if (skge->autoneg == AUTONEG_ENABLE &&
1006 (status & PHY_ST_AN_OVER)) {
1007 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1008 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1009
1010 if (lpa & PHY_B_AN_RF) {
1011 printk(KERN_NOTICE PFX "%s: remote fault\n",
1012 dev->name);
1013 return;
1014 }
1015
1016 /* Check Duplex mismatch */
1017 switch (aux & PHY_B_AS_AN_RES_MSK) {
1018 case PHY_B_RES_1000FD:
1019 skge->duplex = DUPLEX_FULL;
1020 break;
1021 case PHY_B_RES_1000HD:
1022 skge->duplex = DUPLEX_HALF;
1023 break;
1024 default:
1025 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1026 dev->name);
1027 return;
1028 }
1029
1030
1031 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1032 switch (aux & PHY_B_AS_PAUSE_MSK) {
1033 case PHY_B_AS_PAUSE_MSK:
1034 skge->flow_control = FLOW_MODE_SYMMETRIC;
1035 break;
1036 case PHY_B_AS_PRR:
1037 skge->flow_control = FLOW_MODE_REM_SEND;
1038 break;
1039 case PHY_B_AS_PRT:
1040 skge->flow_control = FLOW_MODE_LOC_SEND;
1041 break;
1042 default:
1043 skge->flow_control = FLOW_MODE_NONE;
1044 }
1045
1046 skge->speed = SPEED_1000;
1047 }
1048
1049 if (!netif_carrier_ok(dev))
1050 genesis_link_up(skge);
1051 }
1052 }
1053
1054 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1055 * Phy on for 100 or 10Mbit operation
1056 */
1057 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1058 {
1059 struct skge_hw *hw = skge->hw;
1060 int port = skge->port;
1061 int i;
1062 u16 id1, r, ext, ctl;
1063
1064 /* magic workaround patterns for Broadcom */
1065 static const struct {
1066 u16 reg;
1067 u16 val;
1068 } A1hack[] = {
1069 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1070 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1071 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1072 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1073 }, C0hack[] = {
1074 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1075 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1076 };
1077
1078 /* read Id from external PHY (all have the same address) */
1079 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1080
1081 /* Optimize MDIO transfer by suppressing preamble. */
1082 r = xm_read16(hw, port, XM_MMU_CMD);
1083 r |= XM_MMU_NO_PRE;
1084 xm_write16(hw, port, XM_MMU_CMD,r);
1085
1086 switch (id1) {
1087 case PHY_BCOM_ID1_C0:
1088 /*
1089 * Workaround BCOM Errata for the C0 type.
1090 * Write magic patterns to reserved registers.
1091 */
1092 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1093 xm_phy_write(hw, port,
1094 C0hack[i].reg, C0hack[i].val);
1095
1096 break;
1097 case PHY_BCOM_ID1_A1:
1098 /*
1099 * Workaround BCOM Errata for the A1 type.
1100 * Write magic patterns to reserved registers.
1101 */
1102 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1103 xm_phy_write(hw, port,
1104 A1hack[i].reg, A1hack[i].val);
1105 break;
1106 }
1107
1108 /*
1109 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1110 * Disable Power Management after reset.
1111 */
1112 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1113 r |= PHY_B_AC_DIS_PM;
1114 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1115
1116 /* Dummy read */
1117 xm_read16(hw, port, XM_ISRC);
1118
1119 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1120 ctl = PHY_CT_SP1000; /* always 1000mbit */
1121
1122 if (skge->autoneg == AUTONEG_ENABLE) {
1123 /*
1124 * Workaround BCOM Errata #1 for the C5 type.
1125 * 1000Base-T Link Acquisition Failure in Slave Mode
1126 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1127 */
1128 u16 adv = PHY_B_1000C_RD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Half)
1130 adv |= PHY_B_1000C_AHD;
1131 if (skge->advertising & ADVERTISED_1000baseT_Full)
1132 adv |= PHY_B_1000C_AFD;
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1134
1135 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1136 } else {
1137 if (skge->duplex == DUPLEX_FULL)
1138 ctl |= PHY_CT_DUP_MD;
1139 /* Force to slave */
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1141 }
1142
1143 /* Set autonegotiation pause parameters */
1144 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1146
1147 /* Handle Jumbo frames */
1148 if (jumbo) {
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1151
1152 ext |= PHY_B_PEC_HIGH_LA;
1153
1154 }
1155
1156 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1157 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1158
1159 /* Use link status change interrupt */
1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1161
1162 bcom_check_link(hw, port);
1163 }
1164
1165 static void genesis_mac_init(struct skge_hw *hw, int port)
1166 {
1167 struct net_device *dev = hw->dev[port];
1168 struct skge_port *skge = netdev_priv(dev);
1169 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1170 int i;
1171 u32 r;
1172 const u8 zero[6] = { 0 };
1173
1174 for (i = 0; i < 10; i++) {
1175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1176 MFF_SET_MAC_RST);
1177 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1178 goto reset_ok;
1179 udelay(1);
1180 }
1181
1182 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1183
1184 reset_ok:
1185 /* Unreset the XMAC. */
1186 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1187
1188 /*
1189 * Perform additional initialization for external PHYs,
1190 * namely for the 1000baseTX cards that use the XMAC's
1191 * GMII mode.
1192 */
1193 /* Take external Phy out of reset */
1194 r = skge_read32(hw, B2_GP_IO);
1195 if (port == 0)
1196 r |= GP_DIR_0|GP_IO_0;
1197 else
1198 r |= GP_DIR_2|GP_IO_2;
1199
1200 skge_write32(hw, B2_GP_IO, r);
1201
1202
1203 /* Enable GMII interface */
1204 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1205
1206 bcom_phy_init(skge, jumbo);
1207
1208 /* Set Station Address */
1209 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1210
1211 /* We don't use match addresses so clear */
1212 for (i = 1; i < 16; i++)
1213 xm_outaddr(hw, port, XM_EXM(i), zero);
1214
1215 /* Clear MIB counters */
1216 xm_write16(hw, port, XM_STAT_CMD,
1217 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1218 /* Clear two times according to Errata #3 */
1219 xm_write16(hw, port, XM_STAT_CMD,
1220 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1221
1222 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1223 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1224
1225 /* We don't need the FCS appended to the packet. */
1226 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1227 if (jumbo)
1228 r |= XM_RX_BIG_PK_OK;
1229
1230 if (skge->duplex == DUPLEX_HALF) {
1231 /*
1232 * If in manual half duplex mode the other side might be in
1233 * full duplex mode, so ignore if a carrier extension is not seen
1234 * on frames received
1235 */
1236 r |= XM_RX_DIS_CEXT;
1237 }
1238 xm_write16(hw, port, XM_RX_CMD, r);
1239
1240
1241 /* We want short frames padded to 60 bytes. */
1242 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1243
1244 /*
1245 * Bump up the transmit threshold. This helps hold off transmit
1246 * underruns when we're blasting traffic from both ports at once.
1247 */
1248 xm_write16(hw, port, XM_TX_THR, 512);
1249
1250 /*
1251 * Enable the reception of all error frames. This is is
1252 * a necessary evil due to the design of the XMAC. The
1253 * XMAC's receive FIFO is only 8K in size, however jumbo
1254 * frames can be up to 9000 bytes in length. When bad
1255 * frame filtering is enabled, the XMAC's RX FIFO operates
1256 * in 'store and forward' mode. For this to work, the
1257 * entire frame has to fit into the FIFO, but that means
1258 * that jumbo frames larger than 8192 bytes will be
1259 * truncated. Disabling all bad frame filtering causes
1260 * the RX FIFO to operate in streaming mode, in which
1261 * case the XMAC will start transferring frames out of the
1262 * RX FIFO as soon as the FIFO threshold is reached.
1263 */
1264 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1265
1266
1267 /*
1268 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1269 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1270 * and 'Octets Rx OK Hi Cnt Ov'.
1271 */
1272 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1273
1274 /*
1275 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1276 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1277 * and 'Octets Tx OK Hi Cnt Ov'.
1278 */
1279 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1280
1281 /* Configure MAC arbiter */
1282 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1283
1284 /* configure timeout values */
1285 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1287 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1288 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1289
1290 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1292 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1293 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1294
1295 /* Configure Rx MAC FIFO */
1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1297 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1298 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1299
1300 /* Configure Tx MAC FIFO */
1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1302 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1303 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1304
1305 if (jumbo) {
1306 /* Enable frame flushing if jumbo frames used */
1307 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1308 } else {
1309 /* enable timeout timers if normal frames */
1310 skge_write16(hw, B3_PA_CTRL,
1311 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1312 }
1313 }
1314
1315 static void genesis_stop(struct skge_port *skge)
1316 {
1317 struct skge_hw *hw = skge->hw;
1318 int port = skge->port;
1319 u32 reg;
1320
1321 genesis_reset(hw, port);
1322
1323 /* Clear Tx packet arbiter timeout IRQ */
1324 skge_write16(hw, B3_PA_CTRL,
1325 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1326
1327 /*
1328 * If the transfer sticks at the MAC the STOP command will not
1329 * terminate if we don't flush the XMAC's transmit FIFO !
1330 */
1331 xm_write32(hw, port, XM_MODE,
1332 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1333
1334
1335 /* Reset the MAC */
1336 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1337
1338 /* For external PHYs there must be special handling */
1339 reg = skge_read32(hw, B2_GP_IO);
1340 if (port == 0) {
1341 reg |= GP_DIR_0;
1342 reg &= ~GP_IO_0;
1343 } else {
1344 reg |= GP_DIR_2;
1345 reg &= ~GP_IO_2;
1346 }
1347 skge_write32(hw, B2_GP_IO, reg);
1348 skge_read32(hw, B2_GP_IO);
1349
1350 xm_write16(hw, port, XM_MMU_CMD,
1351 xm_read16(hw, port, XM_MMU_CMD)
1352 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1353
1354 xm_read16(hw, port, XM_MMU_CMD);
1355 }
1356
1357
1358 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1359 {
1360 struct skge_hw *hw = skge->hw;
1361 int port = skge->port;
1362 int i;
1363 unsigned long timeout = jiffies + HZ;
1364
1365 xm_write16(hw, port,
1366 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1367
1368 /* wait for update to complete */
1369 while (xm_read16(hw, port, XM_STAT_CMD)
1370 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1371 if (time_after(jiffies, timeout))
1372 break;
1373 udelay(10);
1374 }
1375
1376 /* special case for 64 bit octet counter */
1377 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1378 | xm_read32(hw, port, XM_TXO_OK_LO);
1379 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1380 | xm_read32(hw, port, XM_RXO_OK_LO);
1381
1382 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1383 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1384 }
1385
1386 static void genesis_mac_intr(struct skge_hw *hw, int port)
1387 {
1388 struct skge_port *skge = netdev_priv(hw->dev[port]);
1389 u16 status = xm_read16(hw, port, XM_ISRC);
1390
1391 if (netif_msg_intr(skge))
1392 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1393 skge->netdev->name, status);
1394
1395 if (status & XM_IS_TXF_UR) {
1396 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1397 ++skge->net_stats.tx_fifo_errors;
1398 }
1399 if (status & XM_IS_RXF_OV) {
1400 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1401 ++skge->net_stats.rx_fifo_errors;
1402 }
1403 }
1404
1405 static void genesis_link_up(struct skge_port *skge)
1406 {
1407 struct skge_hw *hw = skge->hw;
1408 int port = skge->port;
1409 u16 cmd;
1410 u32 mode, msk;
1411
1412 cmd = xm_read16(hw, port, XM_MMU_CMD);
1413
1414 /*
1415 * enabling pause frame reception is required for 1000BT
1416 * because the XMAC is not reset if the link is going down
1417 */
1418 if (skge->flow_control == FLOW_MODE_NONE ||
1419 skge->flow_control == FLOW_MODE_LOC_SEND)
1420 /* Disable Pause Frame Reception */
1421 cmd |= XM_MMU_IGN_PF;
1422 else
1423 /* Enable Pause Frame Reception */
1424 cmd &= ~XM_MMU_IGN_PF;
1425
1426 xm_write16(hw, port, XM_MMU_CMD, cmd);
1427
1428 mode = xm_read32(hw, port, XM_MODE);
1429 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1430 skge->flow_control == FLOW_MODE_LOC_SEND) {
1431 /*
1432 * Configure Pause Frame Generation
1433 * Use internal and external Pause Frame Generation.
1434 * Sending pause frames is edge triggered.
1435 * Send a Pause frame with the maximum pause time if
1436 * internal oder external FIFO full condition occurs.
1437 * Send a zero pause time frame to re-start transmission.
1438 */
1439 /* XM_PAUSE_DA = '010000C28001' (default) */
1440 /* XM_MAC_PTIME = 0xffff (maximum) */
1441 /* remember this value is defined in big endian (!) */
1442 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1443
1444 mode |= XM_PAUSE_MODE;
1445 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1446 } else {
1447 /*
1448 * disable pause frame generation is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1450 */
1451 /* Disable Pause Mode in Mode Register */
1452 mode &= ~XM_PAUSE_MODE;
1453
1454 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1455 }
1456
1457 xm_write32(hw, port, XM_MODE, mode);
1458
1459 msk = XM_DEF_MSK;
1460 /* disable GP0 interrupt bit for external Phy */
1461 msk |= XM_IS_INP_ASS;
1462
1463 xm_write16(hw, port, XM_IMSK, msk);
1464 xm_read16(hw, port, XM_ISRC);
1465
1466 /* get MMU Command Reg. */
1467 cmd = xm_read16(hw, port, XM_MMU_CMD);
1468 if (skge->duplex == DUPLEX_FULL)
1469 cmd |= XM_MMU_GMII_FD;
1470
1471 /*
1472 * Workaround BCOM Errata (#10523) for all BCom Phys
1473 * Enable Power Management after link up
1474 */
1475 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1476 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1477 & ~PHY_B_AC_DIS_PM);
1478 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1479
1480 /* enable Rx/Tx */
1481 xm_write16(hw, port, XM_MMU_CMD,
1482 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1483 skge_link_up(skge);
1484 }
1485
1486
1487 static inline void bcom_phy_intr(struct skge_port *skge)
1488 {
1489 struct skge_hw *hw = skge->hw;
1490 int port = skge->port;
1491 u16 isrc;
1492
1493 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1494 if (netif_msg_intr(skge))
1495 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1496 skge->netdev->name, isrc);
1497
1498 if (isrc & PHY_B_IS_PSE)
1499 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1500 hw->dev[port]->name);
1501
1502 /* Workaround BCom Errata:
1503 * enable and disable loopback mode if "NO HCD" occurs.
1504 */
1505 if (isrc & PHY_B_IS_NO_HDCL) {
1506 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1507 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1508 ctrl | PHY_CT_LOOP);
1509 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1510 ctrl & ~PHY_CT_LOOP);
1511 }
1512
1513 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1514 bcom_check_link(hw, port);
1515
1516 }
1517
1518 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1519 {
1520 int i;
1521
1522 gma_write16(hw, port, GM_SMI_DATA, val);
1523 gma_write16(hw, port, GM_SMI_CTRL,
1524 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1525 for (i = 0; i < PHY_RETRIES; i++) {
1526 udelay(1);
1527
1528 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1529 return 0;
1530 }
1531
1532 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1533 hw->dev[port]->name);
1534 return -EIO;
1535 }
1536
1537 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1538 {
1539 int i;
1540
1541 gma_write16(hw, port, GM_SMI_CTRL,
1542 GM_SMI_CT_PHY_AD(hw->phy_addr)
1543 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1544
1545 for (i = 0; i < PHY_RETRIES; i++) {
1546 udelay(1);
1547 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1548 goto ready;
1549 }
1550
1551 return -ETIMEDOUT;
1552 ready:
1553 *val = gma_read16(hw, port, GM_SMI_DATA);
1554 return 0;
1555 }
1556
1557 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1558 {
1559 u16 v = 0;
1560 if (__gm_phy_read(hw, port, reg, &v))
1561 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1562 hw->dev[port]->name);
1563 return v;
1564 }
1565
1566 /* Marvell Phy Initialization */
1567 static void yukon_init(struct skge_hw *hw, int port)
1568 {
1569 struct skge_port *skge = netdev_priv(hw->dev[port]);
1570 u16 ctrl, ct1000, adv;
1571
1572 if (skge->autoneg == AUTONEG_ENABLE) {
1573 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1574
1575 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1576 PHY_M_EC_MAC_S_MSK);
1577 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1578
1579 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1580
1581 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1582 }
1583
1584 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1585 if (skge->autoneg == AUTONEG_DISABLE)
1586 ctrl &= ~PHY_CT_ANE;
1587
1588 ctrl |= PHY_CT_RESET;
1589 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1590
1591 ctrl = 0;
1592 ct1000 = 0;
1593 adv = PHY_AN_CSMA;
1594
1595 if (skge->autoneg == AUTONEG_ENABLE) {
1596 if (hw->copper) {
1597 if (skge->advertising & ADVERTISED_1000baseT_Full)
1598 ct1000 |= PHY_M_1000C_AFD;
1599 if (skge->advertising & ADVERTISED_1000baseT_Half)
1600 ct1000 |= PHY_M_1000C_AHD;
1601 if (skge->advertising & ADVERTISED_100baseT_Full)
1602 adv |= PHY_M_AN_100_FD;
1603 if (skge->advertising & ADVERTISED_100baseT_Half)
1604 adv |= PHY_M_AN_100_HD;
1605 if (skge->advertising & ADVERTISED_10baseT_Full)
1606 adv |= PHY_M_AN_10_FD;
1607 if (skge->advertising & ADVERTISED_10baseT_Half)
1608 adv |= PHY_M_AN_10_HD;
1609 } else /* special defines for FIBER (88E1011S only) */
1610 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1611
1612 /* Set Flow-control capabilities */
1613 adv |= phy_pause_map[skge->flow_control];
1614
1615 /* Restart Auto-negotiation */
1616 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1617 } else {
1618 /* forced speed/duplex settings */
1619 ct1000 = PHY_M_1000C_MSE;
1620
1621 if (skge->duplex == DUPLEX_FULL)
1622 ctrl |= PHY_CT_DUP_MD;
1623
1624 switch (skge->speed) {
1625 case SPEED_1000:
1626 ctrl |= PHY_CT_SP1000;
1627 break;
1628 case SPEED_100:
1629 ctrl |= PHY_CT_SP100;
1630 break;
1631 }
1632
1633 ctrl |= PHY_CT_RESET;
1634 }
1635
1636 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1637
1638 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1639 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1640
1641 /* Enable phy interrupt on autonegotiation complete (or link up) */
1642 if (skge->autoneg == AUTONEG_ENABLE)
1643 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1644 else
1645 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1646 }
1647
1648 static void yukon_reset(struct skge_hw *hw, int port)
1649 {
1650 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1651 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1652 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1653 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1654 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1655
1656 gma_write16(hw, port, GM_RX_CTRL,
1657 gma_read16(hw, port, GM_RX_CTRL)
1658 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1659 }
1660
1661 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1662 static int is_yukon_lite_a0(struct skge_hw *hw)
1663 {
1664 u32 reg;
1665 int ret;
1666
1667 if (hw->chip_id != CHIP_ID_YUKON)
1668 return 0;
1669
1670 reg = skge_read32(hw, B2_FAR);
1671 skge_write8(hw, B2_FAR + 3, 0xff);
1672 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1673 skge_write32(hw, B2_FAR, reg);
1674 return ret;
1675 }
1676
1677 static void yukon_mac_init(struct skge_hw *hw, int port)
1678 {
1679 struct skge_port *skge = netdev_priv(hw->dev[port]);
1680 int i;
1681 u32 reg;
1682 const u8 *addr = hw->dev[port]->dev_addr;
1683
1684 /* WA code for COMA mode -- set PHY reset */
1685 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1686 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1687 reg = skge_read32(hw, B2_GP_IO);
1688 reg |= GP_DIR_9 | GP_IO_9;
1689 skge_write32(hw, B2_GP_IO, reg);
1690 }
1691
1692 /* hard reset */
1693 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1694 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1695
1696 /* WA code for COMA mode -- clear PHY reset */
1697 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1698 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1699 reg = skge_read32(hw, B2_GP_IO);
1700 reg |= GP_DIR_9;
1701 reg &= ~GP_IO_9;
1702 skge_write32(hw, B2_GP_IO, reg);
1703 }
1704
1705 /* Set hardware config mode */
1706 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1707 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1708 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1709
1710 /* Clear GMC reset */
1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1713 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1714
1715 if (skge->autoneg == AUTONEG_DISABLE) {
1716 reg = GM_GPCR_AU_ALL_DIS;
1717 gma_write16(hw, port, GM_GP_CTRL,
1718 gma_read16(hw, port, GM_GP_CTRL) | reg);
1719
1720 switch (skge->speed) {
1721 case SPEED_1000:
1722 reg &= ~GM_GPCR_SPEED_100;
1723 reg |= GM_GPCR_SPEED_1000;
1724 break;
1725 case SPEED_100:
1726 reg &= ~GM_GPCR_SPEED_1000;
1727 reg |= GM_GPCR_SPEED_100;
1728 break;
1729 case SPEED_10:
1730 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1731 break;
1732 }
1733
1734 if (skge->duplex == DUPLEX_FULL)
1735 reg |= GM_GPCR_DUP_FULL;
1736 } else
1737 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1738
1739 switch (skge->flow_control) {
1740 case FLOW_MODE_NONE:
1741 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1742 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1743 break;
1744 case FLOW_MODE_LOC_SEND:
1745 /* disable Rx flow-control */
1746 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1747 }
1748
1749 gma_write16(hw, port, GM_GP_CTRL, reg);
1750 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1751
1752 yukon_init(hw, port);
1753
1754 /* MIB clear */
1755 reg = gma_read16(hw, port, GM_PHY_ADDR);
1756 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1757
1758 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1759 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1760 gma_write16(hw, port, GM_PHY_ADDR, reg);
1761
1762 /* transmit control */
1763 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1764
1765 /* receive control reg: unicast + multicast + no FCS */
1766 gma_write16(hw, port, GM_RX_CTRL,
1767 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1768
1769 /* transmit flow control */
1770 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1771
1772 /* transmit parameter */
1773 gma_write16(hw, port, GM_TX_PARAM,
1774 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1775 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1776 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1777
1778 /* serial mode register */
1779 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1780 if (hw->dev[port]->mtu > 1500)
1781 reg |= GM_SMOD_JUMBO_ENA;
1782
1783 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1784
1785 /* physical address: used for pause frames */
1786 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1787 /* virtual address for data */
1788 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1789
1790 /* enable interrupt mask for counter overflows */
1791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1794
1795 /* Initialize Mac Fifo */
1796
1797 /* Configure Rx MAC FIFO */
1798 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1799 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1800
1801 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1802 if (is_yukon_lite_a0(hw))
1803 reg &= ~GMF_RX_F_FL_ON;
1804
1805 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1806 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1807 /*
1808 * because Pause Packet Truncation in GMAC is not working
1809 * we have to increase the Flush Threshold to 64 bytes
1810 * in order to flush pause packets in Rx FIFO on Yukon-1
1811 */
1812 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1813
1814 /* Configure Tx MAC FIFO */
1815 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1816 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1817 }
1818
1819 /* Go into power down mode */
1820 static void yukon_suspend(struct skge_hw *hw, int port)
1821 {
1822 u16 ctrl;
1823
1824 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1825 ctrl |= PHY_M_PC_POL_R_DIS;
1826 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1827
1828 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1829 ctrl |= PHY_CT_RESET;
1830 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1831
1832 /* switch IEEE compatible power down mode on */
1833 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1834 ctrl |= PHY_CT_PDOWN;
1835 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1836 }
1837
1838 static void yukon_stop(struct skge_port *skge)
1839 {
1840 struct skge_hw *hw = skge->hw;
1841 int port = skge->port;
1842
1843 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1844 yukon_reset(hw, port);
1845
1846 gma_write16(hw, port, GM_GP_CTRL,
1847 gma_read16(hw, port, GM_GP_CTRL)
1848 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1849 gma_read16(hw, port, GM_GP_CTRL);
1850
1851 yukon_suspend(hw, port);
1852
1853 /* set GPHY Control reset */
1854 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1855 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1856 }
1857
1858 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1859 {
1860 struct skge_hw *hw = skge->hw;
1861 int port = skge->port;
1862 int i;
1863
1864 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1865 | gma_read32(hw, port, GM_TXO_OK_LO);
1866 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1867 | gma_read32(hw, port, GM_RXO_OK_LO);
1868
1869 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1870 data[i] = gma_read32(hw, port,
1871 skge_stats[i].gma_offset);
1872 }
1873
1874 static void yukon_mac_intr(struct skge_hw *hw, int port)
1875 {
1876 struct net_device *dev = hw->dev[port];
1877 struct skge_port *skge = netdev_priv(dev);
1878 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1879
1880 if (netif_msg_intr(skge))
1881 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1882 dev->name, status);
1883
1884 if (status & GM_IS_RX_FF_OR) {
1885 ++skge->net_stats.rx_fifo_errors;
1886 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1887 }
1888
1889 if (status & GM_IS_TX_FF_UR) {
1890 ++skge->net_stats.tx_fifo_errors;
1891 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1892 }
1893
1894 }
1895
1896 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1897 {
1898 switch (aux & PHY_M_PS_SPEED_MSK) {
1899 case PHY_M_PS_SPEED_1000:
1900 return SPEED_1000;
1901 case PHY_M_PS_SPEED_100:
1902 return SPEED_100;
1903 default:
1904 return SPEED_10;
1905 }
1906 }
1907
1908 static void yukon_link_up(struct skge_port *skge)
1909 {
1910 struct skge_hw *hw = skge->hw;
1911 int port = skge->port;
1912 u16 reg;
1913
1914 /* Enable Transmit FIFO Underrun */
1915 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1916
1917 reg = gma_read16(hw, port, GM_GP_CTRL);
1918 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1919 reg |= GM_GPCR_DUP_FULL;
1920
1921 /* enable Rx/Tx */
1922 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1923 gma_write16(hw, port, GM_GP_CTRL, reg);
1924
1925 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1926 skge_link_up(skge);
1927 }
1928
1929 static void yukon_link_down(struct skge_port *skge)
1930 {
1931 struct skge_hw *hw = skge->hw;
1932 int port = skge->port;
1933 u16 ctrl;
1934
1935 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1936
1937 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1938 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1939 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1940
1941 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1942 /* restore Asymmetric Pause bit */
1943 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1944 gm_phy_read(hw, port,
1945 PHY_MARV_AUNE_ADV)
1946 | PHY_M_AN_ASP);
1947
1948 }
1949
1950 yukon_reset(hw, port);
1951 skge_link_down(skge);
1952
1953 yukon_init(hw, port);
1954 }
1955
1956 static void yukon_phy_intr(struct skge_port *skge)
1957 {
1958 struct skge_hw *hw = skge->hw;
1959 int port = skge->port;
1960 const char *reason = NULL;
1961 u16 istatus, phystat;
1962
1963 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1964 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1965
1966 if (netif_msg_intr(skge))
1967 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1968 skge->netdev->name, istatus, phystat);
1969
1970 if (istatus & PHY_M_IS_AN_COMPL) {
1971 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1972 & PHY_M_AN_RF) {
1973 reason = "remote fault";
1974 goto failed;
1975 }
1976
1977 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1978 reason = "master/slave fault";
1979 goto failed;
1980 }
1981
1982 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1983 reason = "speed/duplex";
1984 goto failed;
1985 }
1986
1987 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1988 ? DUPLEX_FULL : DUPLEX_HALF;
1989 skge->speed = yukon_speed(hw, phystat);
1990
1991 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1992 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1993 case PHY_M_PS_PAUSE_MSK:
1994 skge->flow_control = FLOW_MODE_SYMMETRIC;
1995 break;
1996 case PHY_M_PS_RX_P_EN:
1997 skge->flow_control = FLOW_MODE_REM_SEND;
1998 break;
1999 case PHY_M_PS_TX_P_EN:
2000 skge->flow_control = FLOW_MODE_LOC_SEND;
2001 break;
2002 default:
2003 skge->flow_control = FLOW_MODE_NONE;
2004 }
2005
2006 if (skge->flow_control == FLOW_MODE_NONE ||
2007 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2008 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2009 else
2010 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2011 yukon_link_up(skge);
2012 return;
2013 }
2014
2015 if (istatus & PHY_M_IS_LSP_CHANGE)
2016 skge->speed = yukon_speed(hw, phystat);
2017
2018 if (istatus & PHY_M_IS_DUP_CHANGE)
2019 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2020 if (istatus & PHY_M_IS_LST_CHANGE) {
2021 if (phystat & PHY_M_PS_LINK_UP)
2022 yukon_link_up(skge);
2023 else
2024 yukon_link_down(skge);
2025 }
2026 return;
2027 failed:
2028 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2029 skge->netdev->name, reason);
2030
2031 /* XXX restart autonegotiation? */
2032 }
2033
2034 static void skge_phy_reset(struct skge_port *skge)
2035 {
2036 struct skge_hw *hw = skge->hw;
2037 int port = skge->port;
2038
2039 netif_stop_queue(skge->netdev);
2040 netif_carrier_off(skge->netdev);
2041
2042 mutex_lock(&hw->phy_mutex);
2043 if (hw->chip_id == CHIP_ID_GENESIS) {
2044 genesis_reset(hw, port);
2045 genesis_mac_init(hw, port);
2046 } else {
2047 yukon_reset(hw, port);
2048 yukon_init(hw, port);
2049 }
2050 mutex_unlock(&hw->phy_mutex);
2051 }
2052
2053 /* Basic MII support */
2054 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2055 {
2056 struct mii_ioctl_data *data = if_mii(ifr);
2057 struct skge_port *skge = netdev_priv(dev);
2058 struct skge_hw *hw = skge->hw;
2059 int err = -EOPNOTSUPP;
2060
2061 if (!netif_running(dev))
2062 return -ENODEV; /* Phy still in reset */
2063
2064 switch(cmd) {
2065 case SIOCGMIIPHY:
2066 data->phy_id = hw->phy_addr;
2067
2068 /* fallthru */
2069 case SIOCGMIIREG: {
2070 u16 val = 0;
2071 mutex_lock(&hw->phy_mutex);
2072 if (hw->chip_id == CHIP_ID_GENESIS)
2073 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2074 else
2075 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2076 mutex_unlock(&hw->phy_mutex);
2077 data->val_out = val;
2078 break;
2079 }
2080
2081 case SIOCSMIIREG:
2082 if (!capable(CAP_NET_ADMIN))
2083 return -EPERM;
2084
2085 mutex_lock(&hw->phy_mutex);
2086 if (hw->chip_id == CHIP_ID_GENESIS)
2087 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2088 data->val_in);
2089 else
2090 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2091 data->val_in);
2092 mutex_unlock(&hw->phy_mutex);
2093 break;
2094 }
2095 return err;
2096 }
2097
2098 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2099 {
2100 u32 end;
2101
2102 start /= 8;
2103 len /= 8;
2104 end = start + len - 1;
2105
2106 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2107 skge_write32(hw, RB_ADDR(q, RB_START), start);
2108 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2109 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2110 skge_write32(hw, RB_ADDR(q, RB_END), end);
2111
2112 if (q == Q_R1 || q == Q_R2) {
2113 /* Set thresholds on receive queue's */
2114 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2115 start + (2*len)/3);
2116 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2117 start + (len/3));
2118 } else {
2119 /* Enable store & forward on Tx queue's because
2120 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2121 */
2122 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2123 }
2124
2125 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2126 }
2127
2128 /* Setup Bus Memory Interface */
2129 static void skge_qset(struct skge_port *skge, u16 q,
2130 const struct skge_element *e)
2131 {
2132 struct skge_hw *hw = skge->hw;
2133 u32 watermark = 0x600;
2134 u64 base = skge->dma + (e->desc - skge->mem);
2135
2136 /* optimization to reduce window on 32bit/33mhz */
2137 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2138 watermark /= 2;
2139
2140 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2141 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2142 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2143 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2144 }
2145
2146 static int skge_up(struct net_device *dev)
2147 {
2148 struct skge_port *skge = netdev_priv(dev);
2149 struct skge_hw *hw = skge->hw;
2150 int port = skge->port;
2151 u32 chunk, ram_addr;
2152 size_t rx_size, tx_size;
2153 int err;
2154
2155 if (netif_msg_ifup(skge))
2156 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2157
2158 if (dev->mtu > RX_BUF_SIZE)
2159 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2160 else
2161 skge->rx_buf_size = RX_BUF_SIZE;
2162
2163
2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size;
2167 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2168 if (!skge->mem)
2169 return -ENOMEM;
2170
2171 BUG_ON(skge->dma & 7);
2172
2173 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2174 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2175 err = -EINVAL;
2176 goto free_pci_mem;
2177 }
2178
2179 memset(skge->mem, 0, skge->mem_size);
2180
2181 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2182 if (err)
2183 goto free_pci_mem;
2184
2185 err = skge_rx_fill(skge);
2186 if (err)
2187 goto free_rx_ring;
2188
2189 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2190 skge->dma + rx_size);
2191 if (err)
2192 goto free_rx_ring;
2193
2194 /* Initialize MAC */
2195 mutex_lock(&hw->phy_mutex);
2196 if (hw->chip_id == CHIP_ID_GENESIS)
2197 genesis_mac_init(hw, port);
2198 else
2199 yukon_mac_init(hw, port);
2200 mutex_unlock(&hw->phy_mutex);
2201
2202 /* Configure RAMbuffers */
2203 chunk = hw->ram_size / ((hw->ports + 1)*2);
2204 ram_addr = hw->ram_offset + 2 * chunk * port;
2205
2206 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2207 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2208
2209 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2210 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2211 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2212
2213 /* Start receiver BMU */
2214 wmb();
2215 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2216 skge_led(skge, LED_MODE_ON);
2217
2218 return 0;
2219
2220 free_rx_ring:
2221 skge_rx_clean(skge);
2222 kfree(skge->rx_ring.start);
2223 free_pci_mem:
2224 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2225 skge->mem = NULL;
2226
2227 return err;
2228 }
2229
2230 static int skge_down(struct net_device *dev)
2231 {
2232 struct skge_port *skge = netdev_priv(dev);
2233 struct skge_hw *hw = skge->hw;
2234 int port = skge->port;
2235
2236 if (skge->mem == NULL)
2237 return 0;
2238
2239 if (netif_msg_ifdown(skge))
2240 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2241
2242 netif_stop_queue(dev);
2243
2244 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2245 if (hw->chip_id == CHIP_ID_GENESIS)
2246 genesis_stop(skge);
2247 else
2248 yukon_stop(skge);
2249
2250 /* Stop transmitter */
2251 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2252 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2253 RB_RST_SET|RB_DIS_OP_MD);
2254
2255
2256 /* Disable Force Sync bit and Enable Alloc bit */
2257 skge_write8(hw, SK_REG(port, TXA_CTRL),
2258 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2259
2260 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2261 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2262 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2263
2264 /* Reset PCI FIFO */
2265 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2266 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2267
2268 /* Reset the RAM Buffer async Tx queue */
2269 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2270 /* stop receiver */
2271 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2272 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2273 RB_RST_SET|RB_DIS_OP_MD);
2274 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2275
2276 if (hw->chip_id == CHIP_ID_GENESIS) {
2277 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2278 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2279 } else {
2280 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2281 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2282 }
2283
2284 skge_led(skge, LED_MODE_OFF);
2285
2286 skge_tx_clean(skge);
2287 skge_rx_clean(skge);
2288
2289 kfree(skge->rx_ring.start);
2290 kfree(skge->tx_ring.start);
2291 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2292 skge->mem = NULL;
2293 return 0;
2294 }
2295
2296 static inline int skge_avail(const struct skge_ring *ring)
2297 {
2298 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2299 + (ring->to_clean - ring->to_use) - 1;
2300 }
2301
2302 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2303 {
2304 struct skge_port *skge = netdev_priv(dev);
2305 struct skge_hw *hw = skge->hw;
2306 struct skge_element *e;
2307 struct skge_tx_desc *td;
2308 int i;
2309 u32 control, len;
2310 u64 map;
2311 unsigned long flags;
2312
2313 if (skb_padto(skb, ETH_ZLEN))
2314 return NETDEV_TX_OK;
2315
2316 if (!spin_trylock_irqsave(&skge->tx_lock, flags))
2317 /* Collision - tell upper layer to requeue */
2318 return NETDEV_TX_LOCKED;
2319
2320 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) {
2321 if (!netif_queue_stopped(dev)) {
2322 netif_stop_queue(dev);
2323
2324 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2325 dev->name);
2326 }
2327 spin_unlock_irqrestore(&skge->tx_lock, flags);
2328 return NETDEV_TX_BUSY;
2329 }
2330
2331 e = skge->tx_ring.to_use;
2332 td = e->desc;
2333 BUG_ON(td->control & BMU_OWN);
2334 e->skb = skb;
2335 len = skb_headlen(skb);
2336 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2337 pci_unmap_addr_set(e, mapaddr, map);
2338 pci_unmap_len_set(e, maplen, len);
2339
2340 td->dma_lo = map;
2341 td->dma_hi = map >> 32;
2342
2343 if (skb->ip_summed == CHECKSUM_HW) {
2344 int offset = skb->h.raw - skb->data;
2345
2346 /* This seems backwards, but it is what the sk98lin
2347 * does. Looks like hardware is wrong?
2348 */
2349 if (skb->h.ipiph->protocol == IPPROTO_UDP
2350 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2351 control = BMU_TCP_CHECK;
2352 else
2353 control = BMU_UDP_CHECK;
2354
2355 td->csum_offs = 0;
2356 td->csum_start = offset;
2357 td->csum_write = offset + skb->csum;
2358 } else
2359 control = BMU_CHECK;
2360
2361 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2362 control |= BMU_EOF| BMU_IRQ_EOF;
2363 else {
2364 struct skge_tx_desc *tf = td;
2365
2366 control |= BMU_STFWD;
2367 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2368 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2369
2370 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2371 frag->size, PCI_DMA_TODEVICE);
2372
2373 e = e->next;
2374 e->skb = skb;
2375 tf = e->desc;
2376 BUG_ON(tf->control & BMU_OWN);
2377
2378 tf->dma_lo = map;
2379 tf->dma_hi = (u64) map >> 32;
2380 pci_unmap_addr_set(e, mapaddr, map);
2381 pci_unmap_len_set(e, maplen, frag->size);
2382
2383 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2384 }
2385 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2386 }
2387 /* Make sure all the descriptors written */
2388 wmb();
2389 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2390 wmb();
2391
2392 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2393
2394 if (unlikely(netif_msg_tx_queued(skge)))
2395 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2396 dev->name, e - skge->tx_ring.start, skb->len);
2397
2398 skge->tx_ring.to_use = e->next;
2399 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2400 pr_debug("%s: transmit queue full\n", dev->name);
2401 netif_stop_queue(dev);
2402 }
2403
2404 spin_unlock_irqrestore(&skge->tx_lock, flags);
2405
2406 dev->trans_start = jiffies;
2407
2408 return NETDEV_TX_OK;
2409 }
2410
2411
2412 /* Free resources associated with this reing element */
2413 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2414 u32 control)
2415 {
2416 struct pci_dev *pdev = skge->hw->pdev;
2417
2418 BUG_ON(!e->skb);
2419
2420 /* skb header vs. fragment */
2421 if (control & BMU_STF)
2422 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2423 pci_unmap_len(e, maplen),
2424 PCI_DMA_TODEVICE);
2425 else
2426 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2427 pci_unmap_len(e, maplen),
2428 PCI_DMA_TODEVICE);
2429
2430 if (control & BMU_EOF) {
2431 if (unlikely(netif_msg_tx_done(skge)))
2432 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2433 skge->netdev->name, e - skge->tx_ring.start);
2434
2435 dev_kfree_skb_any(e->skb);
2436 }
2437 e->skb = NULL;
2438 }
2439
2440 /* Free all buffers in transmit ring */
2441 static void skge_tx_clean(struct skge_port *skge)
2442 {
2443 struct skge_element *e;
2444 unsigned long flags;
2445
2446 spin_lock_irqsave(&skge->tx_lock, flags);
2447 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2448 struct skge_tx_desc *td = e->desc;
2449 skge_tx_free(skge, e, td->control);
2450 td->control = 0;
2451 }
2452
2453 skge->tx_ring.to_clean = e;
2454 netif_wake_queue(skge->netdev);
2455 spin_unlock_irqrestore(&skge->tx_lock, flags);
2456 }
2457
2458 static void skge_tx_timeout(struct net_device *dev)
2459 {
2460 struct skge_port *skge = netdev_priv(dev);
2461
2462 if (netif_msg_timer(skge))
2463 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2464
2465 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2466 skge_tx_clean(skge);
2467 }
2468
2469 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2470 {
2471 int err;
2472
2473 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2474 return -EINVAL;
2475
2476 if (!netif_running(dev)) {
2477 dev->mtu = new_mtu;
2478 return 0;
2479 }
2480
2481 skge_down(dev);
2482
2483 dev->mtu = new_mtu;
2484
2485 err = skge_up(dev);
2486 if (err)
2487 dev_close(dev);
2488
2489 return err;
2490 }
2491
2492 static void genesis_set_multicast(struct net_device *dev)
2493 {
2494 struct skge_port *skge = netdev_priv(dev);
2495 struct skge_hw *hw = skge->hw;
2496 int port = skge->port;
2497 int i, count = dev->mc_count;
2498 struct dev_mc_list *list = dev->mc_list;
2499 u32 mode;
2500 u8 filter[8];
2501
2502 mode = xm_read32(hw, port, XM_MODE);
2503 mode |= XM_MD_ENA_HASH;
2504 if (dev->flags & IFF_PROMISC)
2505 mode |= XM_MD_ENA_PROM;
2506 else
2507 mode &= ~XM_MD_ENA_PROM;
2508
2509 if (dev->flags & IFF_ALLMULTI)
2510 memset(filter, 0xff, sizeof(filter));
2511 else {
2512 memset(filter, 0, sizeof(filter));
2513 for (i = 0; list && i < count; i++, list = list->next) {
2514 u32 crc, bit;
2515 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2516 bit = ~crc & 0x3f;
2517 filter[bit/8] |= 1 << (bit%8);
2518 }
2519 }
2520
2521 xm_write32(hw, port, XM_MODE, mode);
2522 xm_outhash(hw, port, XM_HSM, filter);
2523 }
2524
2525 static void yukon_set_multicast(struct net_device *dev)
2526 {
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 int port = skge->port;
2530 struct dev_mc_list *list = dev->mc_list;
2531 u16 reg;
2532 u8 filter[8];
2533
2534 memset(filter, 0, sizeof(filter));
2535
2536 reg = gma_read16(hw, port, GM_RX_CTRL);
2537 reg |= GM_RXCR_UCF_ENA;
2538
2539 if (dev->flags & IFF_PROMISC) /* promiscuous */
2540 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2541 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2542 memset(filter, 0xff, sizeof(filter));
2543 else if (dev->mc_count == 0) /* no multicast */
2544 reg &= ~GM_RXCR_MCF_ENA;
2545 else {
2546 int i;
2547 reg |= GM_RXCR_MCF_ENA;
2548
2549 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2550 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2551 filter[bit/8] |= 1 << (bit%8);
2552 }
2553 }
2554
2555
2556 gma_write16(hw, port, GM_MC_ADDR_H1,
2557 (u16)filter[0] | ((u16)filter[1] << 8));
2558 gma_write16(hw, port, GM_MC_ADDR_H2,
2559 (u16)filter[2] | ((u16)filter[3] << 8));
2560 gma_write16(hw, port, GM_MC_ADDR_H3,
2561 (u16)filter[4] | ((u16)filter[5] << 8));
2562 gma_write16(hw, port, GM_MC_ADDR_H4,
2563 (u16)filter[6] | ((u16)filter[7] << 8));
2564
2565 gma_write16(hw, port, GM_RX_CTRL, reg);
2566 }
2567
2568 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2569 {
2570 if (hw->chip_id == CHIP_ID_GENESIS)
2571 return status >> XMR_FS_LEN_SHIFT;
2572 else
2573 return status >> GMR_FS_LEN_SHIFT;
2574 }
2575
2576 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2577 {
2578 if (hw->chip_id == CHIP_ID_GENESIS)
2579 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2580 else
2581 return (status & GMR_FS_ANY_ERR) ||
2582 (status & GMR_FS_RX_OK) == 0;
2583 }
2584
2585
2586 /* Get receive buffer from descriptor.
2587 * Handles copy of small buffers and reallocation failures
2588 */
2589 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2590 struct skge_element *e,
2591 u32 control, u32 status, u16 csum)
2592 {
2593 struct sk_buff *skb;
2594 u16 len = control & BMU_BBC;
2595
2596 if (unlikely(netif_msg_rx_status(skge)))
2597 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2598 skge->netdev->name, e - skge->rx_ring.start,
2599 status, len);
2600
2601 if (len > skge->rx_buf_size)
2602 goto error;
2603
2604 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2605 goto error;
2606
2607 if (bad_phy_status(skge->hw, status))
2608 goto error;
2609
2610 if (phy_length(skge->hw, status) != len)
2611 goto error;
2612
2613 if (len < RX_COPY_THRESHOLD) {
2614 skb = alloc_skb(len + 2, GFP_ATOMIC);
2615 if (!skb)
2616 goto resubmit;
2617
2618 skb_reserve(skb, 2);
2619 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2620 pci_unmap_addr(e, mapaddr),
2621 len, PCI_DMA_FROMDEVICE);
2622 memcpy(skb->data, e->skb->data, len);
2623 pci_dma_sync_single_for_device(skge->hw->pdev,
2624 pci_unmap_addr(e, mapaddr),
2625 len, PCI_DMA_FROMDEVICE);
2626 skge_rx_reuse(e, skge->rx_buf_size);
2627 } else {
2628 struct sk_buff *nskb;
2629 nskb = alloc_skb(skge->rx_buf_size + NET_IP_ALIGN, GFP_ATOMIC);
2630 if (!nskb)
2631 goto resubmit;
2632
2633 skb_reserve(nskb, NET_IP_ALIGN);
2634 pci_unmap_single(skge->hw->pdev,
2635 pci_unmap_addr(e, mapaddr),
2636 pci_unmap_len(e, maplen),
2637 PCI_DMA_FROMDEVICE);
2638 skb = e->skb;
2639 prefetch(skb->data);
2640 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2641 }
2642
2643 skb_put(skb, len);
2644 skb->dev = skge->netdev;
2645 if (skge->rx_csum) {
2646 skb->csum = csum;
2647 skb->ip_summed = CHECKSUM_HW;
2648 }
2649
2650 skb->protocol = eth_type_trans(skb, skge->netdev);
2651
2652 return skb;
2653 error:
2654
2655 if (netif_msg_rx_err(skge))
2656 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2657 skge->netdev->name, e - skge->rx_ring.start,
2658 control, status);
2659
2660 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2661 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2662 skge->net_stats.rx_length_errors++;
2663 if (status & XMR_FS_FRA_ERR)
2664 skge->net_stats.rx_frame_errors++;
2665 if (status & XMR_FS_FCS_ERR)
2666 skge->net_stats.rx_crc_errors++;
2667 } else {
2668 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2669 skge->net_stats.rx_length_errors++;
2670 if (status & GMR_FS_FRAGMENT)
2671 skge->net_stats.rx_frame_errors++;
2672 if (status & GMR_FS_CRC_ERR)
2673 skge->net_stats.rx_crc_errors++;
2674 }
2675
2676 resubmit:
2677 skge_rx_reuse(e, skge->rx_buf_size);
2678 return NULL;
2679 }
2680
2681 /* Free all buffers in Tx ring which are no longer owned by device */
2682 static void skge_txirq(struct net_device *dev)
2683 {
2684 struct skge_port *skge = netdev_priv(dev);
2685 struct skge_ring *ring = &skge->tx_ring;
2686 struct skge_element *e;
2687
2688 rmb();
2689
2690 spin_lock(&skge->tx_lock);
2691 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2692 struct skge_tx_desc *td = e->desc;
2693
2694 if (td->control & BMU_OWN)
2695 break;
2696
2697 skge_tx_free(skge, e, td->control);
2698 }
2699 skge->tx_ring.to_clean = e;
2700
2701 if (netif_queue_stopped(skge->netdev)
2702 && skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2703 netif_wake_queue(skge->netdev);
2704
2705 spin_unlock(&skge->tx_lock);
2706 }
2707
2708 static int skge_poll(struct net_device *dev, int *budget)
2709 {
2710 struct skge_port *skge = netdev_priv(dev);
2711 struct skge_hw *hw = skge->hw;
2712 struct skge_ring *ring = &skge->rx_ring;
2713 struct skge_element *e;
2714 int to_do = min(dev->quota, *budget);
2715 int work_done = 0;
2716
2717 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2718 struct skge_rx_desc *rd = e->desc;
2719 struct sk_buff *skb;
2720 u32 control;
2721
2722 rmb();
2723 control = rd->control;
2724 if (control & BMU_OWN)
2725 break;
2726
2727 skb = skge_rx_get(skge, e, control, rd->status, rd->csum2);
2728 if (likely(skb)) {
2729 dev->last_rx = jiffies;
2730 netif_receive_skb(skb);
2731
2732 ++work_done;
2733 }
2734 }
2735 ring->to_clean = e;
2736
2737 /* restart receiver */
2738 wmb();
2739 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
2740
2741 *budget -= work_done;
2742 dev->quota -= work_done;
2743
2744 if (work_done >= to_do)
2745 return 1; /* not done */
2746
2747 netif_rx_complete(dev);
2748
2749 spin_lock_irq(&hw->hw_lock);
2750 hw->intr_mask |= rxirqmask[skge->port];
2751 skge_write32(hw, B0_IMSK, hw->intr_mask);
2752 mmiowb();
2753 spin_unlock_irq(&hw->hw_lock);
2754
2755 return 0;
2756 }
2757
2758 /* Parity errors seem to happen when Genesis is connected to a switch
2759 * with no other ports present. Heartbeat error??
2760 */
2761 static void skge_mac_parity(struct skge_hw *hw, int port)
2762 {
2763 struct net_device *dev = hw->dev[port];
2764
2765 if (dev) {
2766 struct skge_port *skge = netdev_priv(dev);
2767 ++skge->net_stats.tx_heartbeat_errors;
2768 }
2769
2770 if (hw->chip_id == CHIP_ID_GENESIS)
2771 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2772 MFF_CLR_PERR);
2773 else
2774 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2775 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2776 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2777 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2778 }
2779
2780 static void skge_mac_intr(struct skge_hw *hw, int port)
2781 {
2782 if (hw->chip_id == CHIP_ID_GENESIS)
2783 genesis_mac_intr(hw, port);
2784 else
2785 yukon_mac_intr(hw, port);
2786 }
2787
2788 /* Handle device specific framing and timeout interrupts */
2789 static void skge_error_irq(struct skge_hw *hw)
2790 {
2791 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2792
2793 if (hw->chip_id == CHIP_ID_GENESIS) {
2794 /* clear xmac errors */
2795 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2796 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2797 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2798 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2799 } else {
2800 /* Timestamp (unused) overflow */
2801 if (hwstatus & IS_IRQ_TIST_OV)
2802 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2803 }
2804
2805 if (hwstatus & IS_RAM_RD_PAR) {
2806 printk(KERN_ERR PFX "Ram read data parity error\n");
2807 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2808 }
2809
2810 if (hwstatus & IS_RAM_WR_PAR) {
2811 printk(KERN_ERR PFX "Ram write data parity error\n");
2812 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2813 }
2814
2815 if (hwstatus & IS_M1_PAR_ERR)
2816 skge_mac_parity(hw, 0);
2817
2818 if (hwstatus & IS_M2_PAR_ERR)
2819 skge_mac_parity(hw, 1);
2820
2821 if (hwstatus & IS_R1_PAR_ERR) {
2822 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2823 hw->dev[0]->name);
2824 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2825 }
2826
2827 if (hwstatus & IS_R2_PAR_ERR) {
2828 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2829 hw->dev[1]->name);
2830 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2831 }
2832
2833 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2834 u16 pci_status, pci_cmd;
2835
2836 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
2837 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
2838
2839 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
2840 pci_name(hw->pdev), pci_cmd, pci_status);
2841
2842 /* Write the error bits back to clear them. */
2843 pci_status &= PCI_STATUS_ERROR_BITS;
2844 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2845 pci_write_config_word(hw->pdev, PCI_COMMAND,
2846 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2847 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
2848 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2849
2850 /* if error still set then just ignore it */
2851 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2852 if (hwstatus & IS_IRQ_STAT) {
2853 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
2854 hw->intr_mask &= ~IS_HW_ERR;
2855 }
2856 }
2857 }
2858
2859 /*
2860 * Interrupt from PHY are handled in work queue
2861 * because accessing phy registers requires spin wait which might
2862 * cause excess interrupt latency.
2863 */
2864 static void skge_extirq(void *arg)
2865 {
2866 struct skge_hw *hw = arg;
2867 int port;
2868
2869 mutex_lock(&hw->phy_mutex);
2870 for (port = 0; port < hw->ports; port++) {
2871 struct net_device *dev = hw->dev[port];
2872 struct skge_port *skge = netdev_priv(dev);
2873
2874 if (netif_running(dev)) {
2875 if (hw->chip_id != CHIP_ID_GENESIS)
2876 yukon_phy_intr(skge);
2877 else
2878 bcom_phy_intr(skge);
2879 }
2880 }
2881 mutex_unlock(&hw->phy_mutex);
2882
2883 spin_lock_irq(&hw->hw_lock);
2884 hw->intr_mask |= IS_EXT_REG;
2885 skge_write32(hw, B0_IMSK, hw->intr_mask);
2886 spin_unlock_irq(&hw->hw_lock);
2887 }
2888
2889 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2890 {
2891 struct skge_hw *hw = dev_id;
2892 u32 status;
2893
2894 /* Reading this register masks IRQ */
2895 status = skge_read32(hw, B0_SP_ISRC);
2896 if (status == 0)
2897 return IRQ_NONE;
2898
2899 spin_lock(&hw->hw_lock);
2900 status &= hw->intr_mask;
2901 if (status & IS_EXT_REG) {
2902 hw->intr_mask &= ~IS_EXT_REG;
2903 schedule_work(&hw->phy_work);
2904 }
2905
2906 if (status & IS_XA1_F) {
2907 skge_write8(hw, Q_ADDR(Q_XA1, Q_CSR), CSR_IRQ_CL_F);
2908 skge_txirq(hw->dev[0]);
2909 }
2910
2911 if (status & IS_R1_F) {
2912 skge_write8(hw, Q_ADDR(Q_R1, Q_CSR), CSR_IRQ_CL_F);
2913 hw->intr_mask &= ~IS_R1_F;
2914 netif_rx_schedule(hw->dev[0]);
2915 }
2916
2917 if (status & IS_PA_TO_TX1)
2918 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2919
2920 if (status & IS_PA_TO_RX1) {
2921 struct skge_port *skge = netdev_priv(hw->dev[0]);
2922
2923 ++skge->net_stats.rx_over_errors;
2924 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2925 }
2926
2927
2928 if (status & IS_MAC1)
2929 skge_mac_intr(hw, 0);
2930
2931 if (hw->dev[1]) {
2932 if (status & IS_XA2_F) {
2933 skge_write8(hw, Q_ADDR(Q_XA2, Q_CSR), CSR_IRQ_CL_F);
2934 skge_txirq(hw->dev[1]);
2935 }
2936
2937 if (status & IS_R2_F) {
2938 skge_write8(hw, Q_ADDR(Q_R2, Q_CSR), CSR_IRQ_CL_F);
2939 hw->intr_mask &= ~IS_R2_F;
2940 netif_rx_schedule(hw->dev[1]);
2941 }
2942
2943 if (status & IS_PA_TO_RX2) {
2944 struct skge_port *skge = netdev_priv(hw->dev[1]);
2945 ++skge->net_stats.rx_over_errors;
2946 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2947 }
2948
2949 if (status & IS_PA_TO_TX2)
2950 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2951
2952 if (status & IS_MAC2)
2953 skge_mac_intr(hw, 1);
2954 }
2955
2956 if (status & IS_HW_ERR)
2957 skge_error_irq(hw);
2958
2959 skge_write32(hw, B0_IMSK, hw->intr_mask);
2960 spin_unlock(&hw->hw_lock);
2961
2962 return IRQ_HANDLED;
2963 }
2964
2965 #ifdef CONFIG_NET_POLL_CONTROLLER
2966 static void skge_netpoll(struct net_device *dev)
2967 {
2968 struct skge_port *skge = netdev_priv(dev);
2969
2970 disable_irq(dev->irq);
2971 skge_intr(dev->irq, skge->hw, NULL);
2972 enable_irq(dev->irq);
2973 }
2974 #endif
2975
2976 static int skge_set_mac_address(struct net_device *dev, void *p)
2977 {
2978 struct skge_port *skge = netdev_priv(dev);
2979 struct skge_hw *hw = skge->hw;
2980 unsigned port = skge->port;
2981 const struct sockaddr *addr = p;
2982
2983 if (!is_valid_ether_addr(addr->sa_data))
2984 return -EADDRNOTAVAIL;
2985
2986 mutex_lock(&hw->phy_mutex);
2987 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2988 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2989 dev->dev_addr, ETH_ALEN);
2990 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2991 dev->dev_addr, ETH_ALEN);
2992
2993 if (hw->chip_id == CHIP_ID_GENESIS)
2994 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2995 else {
2996 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2997 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2998 }
2999 mutex_unlock(&hw->phy_mutex);
3000
3001 return 0;
3002 }
3003
3004 static const struct {
3005 u8 id;
3006 const char *name;
3007 } skge_chips[] = {
3008 { CHIP_ID_GENESIS, "Genesis" },
3009 { CHIP_ID_YUKON, "Yukon" },
3010 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3011 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3012 };
3013
3014 static const char *skge_board_name(const struct skge_hw *hw)
3015 {
3016 int i;
3017 static char buf[16];
3018
3019 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3020 if (skge_chips[i].id == hw->chip_id)
3021 return skge_chips[i].name;
3022
3023 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3024 return buf;
3025 }
3026
3027
3028 /*
3029 * Setup the board data structure, but don't bring up
3030 * the port(s)
3031 */
3032 static int skge_reset(struct skge_hw *hw)
3033 {
3034 u32 reg;
3035 u16 ctst, pci_status;
3036 u8 t8, mac_cfg, pmd_type, phy_type;
3037 int i;
3038
3039 ctst = skge_read16(hw, B0_CTST);
3040
3041 /* do a SW reset */
3042 skge_write8(hw, B0_CTST, CS_RST_SET);
3043 skge_write8(hw, B0_CTST, CS_RST_CLR);
3044
3045 /* clear PCI errors, if any */
3046 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3047 skge_write8(hw, B2_TST_CTRL2, 0);
3048
3049 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3050 pci_write_config_word(hw->pdev, PCI_STATUS,
3051 pci_status | PCI_STATUS_ERROR_BITS);
3052 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3053 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3054
3055 /* restore CLK_RUN bits (for Yukon-Lite) */
3056 skge_write16(hw, B0_CTST,
3057 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3058
3059 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3060 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3061 pmd_type = skge_read8(hw, B2_PMD_TYP);
3062 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3063
3064 switch (hw->chip_id) {
3065 case CHIP_ID_GENESIS:
3066 switch (phy_type) {
3067 case SK_PHY_BCOM:
3068 hw->phy_addr = PHY_ADDR_BCOM;
3069 break;
3070 default:
3071 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3072 pci_name(hw->pdev), phy_type);
3073 return -EOPNOTSUPP;
3074 }
3075 break;
3076
3077 case CHIP_ID_YUKON:
3078 case CHIP_ID_YUKON_LITE:
3079 case CHIP_ID_YUKON_LP:
3080 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3081 hw->copper = 1;
3082
3083 hw->phy_addr = PHY_ADDR_MARV;
3084 break;
3085
3086 default:
3087 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3088 pci_name(hw->pdev), hw->chip_id);
3089 return -EOPNOTSUPP;
3090 }
3091
3092 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3093 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3094 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3095
3096 /* read the adapters RAM size */
3097 t8 = skge_read8(hw, B2_E_0);
3098 if (hw->chip_id == CHIP_ID_GENESIS) {
3099 if (t8 == 3) {
3100 /* special case: 4 x 64k x 36, offset = 0x80000 */
3101 hw->ram_size = 0x100000;
3102 hw->ram_offset = 0x80000;
3103 } else
3104 hw->ram_size = t8 * 512;
3105 }
3106 else if (t8 == 0)
3107 hw->ram_size = 0x20000;
3108 else
3109 hw->ram_size = t8 * 4096;
3110
3111 spin_lock_init(&hw->hw_lock);
3112 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3113 if (hw->ports > 1)
3114 hw->intr_mask |= IS_PORT_2;
3115
3116 if (hw->chip_id == CHIP_ID_GENESIS)
3117 genesis_init(hw);
3118 else {
3119 /* switch power to VCC (WA for VAUX problem) */
3120 skge_write8(hw, B0_POWER_CTRL,
3121 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3122
3123 /* avoid boards with stuck Hardware error bits */
3124 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3125 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3126 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3127 hw->intr_mask &= ~IS_HW_ERR;
3128 }
3129
3130 /* Clear PHY COMA */
3131 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3132 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3133 reg &= ~PCI_PHY_COMA;
3134 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3135 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3136
3137
3138 for (i = 0; i < hw->ports; i++) {
3139 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3140 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3141 }
3142 }
3143
3144 /* turn off hardware timer (unused) */
3145 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3146 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3147 skge_write8(hw, B0_LED, LED_STAT_ON);
3148
3149 /* enable the Tx Arbiters */
3150 for (i = 0; i < hw->ports; i++)
3151 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3152
3153 /* Initialize ram interface */
3154 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3155
3156 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3157 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3158 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3159 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3160 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3161 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3162 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3163 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3164 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3165 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3166 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3167 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3168
3169 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3170
3171 /* Set interrupt moderation for Transmit only
3172 * Receive interrupts avoided by NAPI
3173 */
3174 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3175 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3176 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3177
3178 skge_write32(hw, B0_IMSK, hw->intr_mask);
3179
3180 mutex_lock(&hw->phy_mutex);
3181 for (i = 0; i < hw->ports; i++) {
3182 if (hw->chip_id == CHIP_ID_GENESIS)
3183 genesis_reset(hw, i);
3184 else
3185 yukon_reset(hw, i);
3186 }
3187 mutex_unlock(&hw->phy_mutex);
3188
3189 return 0;
3190 }
3191
3192 /* Initialize network device */
3193 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3194 int highmem)
3195 {
3196 struct skge_port *skge;
3197 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3198
3199 if (!dev) {
3200 printk(KERN_ERR "skge etherdev alloc failed");
3201 return NULL;
3202 }
3203
3204 SET_MODULE_OWNER(dev);
3205 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3206 dev->open = skge_up;
3207 dev->stop = skge_down;
3208 dev->do_ioctl = skge_ioctl;
3209 dev->hard_start_xmit = skge_xmit_frame;
3210 dev->get_stats = skge_get_stats;
3211 if (hw->chip_id == CHIP_ID_GENESIS)
3212 dev->set_multicast_list = genesis_set_multicast;
3213 else
3214 dev->set_multicast_list = yukon_set_multicast;
3215
3216 dev->set_mac_address = skge_set_mac_address;
3217 dev->change_mtu = skge_change_mtu;
3218 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3219 dev->tx_timeout = skge_tx_timeout;
3220 dev->watchdog_timeo = TX_WATCHDOG;
3221 dev->poll = skge_poll;
3222 dev->weight = NAPI_WEIGHT;
3223 #ifdef CONFIG_NET_POLL_CONTROLLER
3224 dev->poll_controller = skge_netpoll;
3225 #endif
3226 dev->irq = hw->pdev->irq;
3227 dev->features = NETIF_F_LLTX;
3228 if (highmem)
3229 dev->features |= NETIF_F_HIGHDMA;
3230
3231 skge = netdev_priv(dev);
3232 skge->netdev = dev;
3233 skge->hw = hw;
3234 skge->msg_enable = netif_msg_init(debug, default_msg);
3235 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3236 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3237
3238 /* Auto speed and flow control */
3239 skge->autoneg = AUTONEG_ENABLE;
3240 skge->flow_control = FLOW_MODE_SYMMETRIC;
3241 skge->duplex = -1;
3242 skge->speed = -1;
3243 skge->advertising = skge_supported_modes(hw);
3244
3245 hw->dev[port] = dev;
3246
3247 skge->port = port;
3248
3249 spin_lock_init(&skge->tx_lock);
3250
3251 if (hw->chip_id != CHIP_ID_GENESIS) {
3252 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3253 skge->rx_csum = 1;
3254 }
3255
3256 /* read the mac address */
3257 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3258 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3259
3260 /* device is off until link detection */
3261 netif_carrier_off(dev);
3262 netif_stop_queue(dev);
3263
3264 return dev;
3265 }
3266
3267 static void __devinit skge_show_addr(struct net_device *dev)
3268 {
3269 const struct skge_port *skge = netdev_priv(dev);
3270
3271 if (netif_msg_probe(skge))
3272 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3273 dev->name,
3274 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3275 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3276 }
3277
3278 static int __devinit skge_probe(struct pci_dev *pdev,
3279 const struct pci_device_id *ent)
3280 {
3281 struct net_device *dev, *dev1;
3282 struct skge_hw *hw;
3283 int err, using_dac = 0;
3284
3285 err = pci_enable_device(pdev);
3286 if (err) {
3287 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3288 pci_name(pdev));
3289 goto err_out;
3290 }
3291
3292 err = pci_request_regions(pdev, DRV_NAME);
3293 if (err) {
3294 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3295 pci_name(pdev));
3296 goto err_out_disable_pdev;
3297 }
3298
3299 pci_set_master(pdev);
3300
3301 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3302 using_dac = 1;
3303 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3304 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3305 using_dac = 0;
3306 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3307 }
3308
3309 if (err) {
3310 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3311 pci_name(pdev));
3312 goto err_out_free_regions;
3313 }
3314
3315 #ifdef __BIG_ENDIAN
3316 /* byte swap descriptors in hardware */
3317 {
3318 u32 reg;
3319
3320 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3321 reg |= PCI_REV_DESC;
3322 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3323 }
3324 #endif
3325
3326 err = -ENOMEM;
3327 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3328 if (!hw) {
3329 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3330 pci_name(pdev));
3331 goto err_out_free_regions;
3332 }
3333
3334 hw->pdev = pdev;
3335 mutex_init(&hw->phy_mutex);
3336 INIT_WORK(&hw->phy_work, skge_extirq, hw);
3337
3338 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3339 if (!hw->regs) {
3340 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3341 pci_name(pdev));
3342 goto err_out_free_hw;
3343 }
3344
3345 err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw);
3346 if (err) {
3347 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3348 pci_name(pdev), pdev->irq);
3349 goto err_out_iounmap;
3350 }
3351 pci_set_drvdata(pdev, hw);
3352
3353 err = skge_reset(hw);
3354 if (err)
3355 goto err_out_free_irq;
3356
3357 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3358 pci_resource_start(pdev, 0), pdev->irq,
3359 skge_board_name(hw), hw->chip_rev);
3360
3361 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3362 goto err_out_led_off;
3363
3364 if (!is_valid_ether_addr(dev->dev_addr)) {
3365 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3366 pci_name(pdev));
3367 err = -EIO;
3368 goto err_out_free_netdev;
3369 }
3370
3371
3372 err = register_netdev(dev);
3373 if (err) {
3374 printk(KERN_ERR PFX "%s: cannot register net device\n",
3375 pci_name(pdev));
3376 goto err_out_free_netdev;
3377 }
3378
3379 skge_show_addr(dev);
3380
3381 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3382 if (register_netdev(dev1) == 0)
3383 skge_show_addr(dev1);
3384 else {
3385 /* Failure to register second port need not be fatal */
3386 printk(KERN_WARNING PFX "register of second port failed\n");
3387 hw->dev[1] = NULL;
3388 free_netdev(dev1);
3389 }
3390 }
3391
3392 return 0;
3393
3394 err_out_free_netdev:
3395 free_netdev(dev);
3396 err_out_led_off:
3397 skge_write16(hw, B0_LED, LED_STAT_OFF);
3398 err_out_free_irq:
3399 free_irq(pdev->irq, hw);
3400 err_out_iounmap:
3401 iounmap(hw->regs);
3402 err_out_free_hw:
3403 kfree(hw);
3404 err_out_free_regions:
3405 pci_release_regions(pdev);
3406 err_out_disable_pdev:
3407 pci_disable_device(pdev);
3408 pci_set_drvdata(pdev, NULL);
3409 err_out:
3410 return err;
3411 }
3412
3413 static void __devexit skge_remove(struct pci_dev *pdev)
3414 {
3415 struct skge_hw *hw = pci_get_drvdata(pdev);
3416 struct net_device *dev0, *dev1;
3417
3418 if (!hw)
3419 return;
3420
3421 if ((dev1 = hw->dev[1]))
3422 unregister_netdev(dev1);
3423 dev0 = hw->dev[0];
3424 unregister_netdev(dev0);
3425
3426 spin_lock_irq(&hw->hw_lock);
3427 hw->intr_mask = 0;
3428 skge_write32(hw, B0_IMSK, 0);
3429 spin_unlock_irq(&hw->hw_lock);
3430
3431 skge_write16(hw, B0_LED, LED_STAT_OFF);
3432 skge_write8(hw, B0_CTST, CS_RST_SET);
3433
3434 flush_scheduled_work();
3435
3436 free_irq(pdev->irq, hw);
3437 pci_release_regions(pdev);
3438 pci_disable_device(pdev);
3439 if (dev1)
3440 free_netdev(dev1);
3441 free_netdev(dev0);
3442
3443 iounmap(hw->regs);
3444 kfree(hw);
3445 pci_set_drvdata(pdev, NULL);
3446 }
3447
3448 #ifdef CONFIG_PM
3449 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3450 {
3451 struct skge_hw *hw = pci_get_drvdata(pdev);
3452 int i, wol = 0;
3453
3454 for (i = 0; i < 2; i++) {
3455 struct net_device *dev = hw->dev[i];
3456
3457 if (dev) {
3458 struct skge_port *skge = netdev_priv(dev);
3459 if (netif_running(dev)) {
3460 netif_carrier_off(dev);
3461 if (skge->wol)
3462 netif_stop_queue(dev);
3463 else
3464 skge_down(dev);
3465 }
3466 netif_device_detach(dev);
3467 wol |= skge->wol;
3468 }
3469 }
3470
3471 pci_save_state(pdev);
3472 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3473 pci_disable_device(pdev);
3474 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3475
3476 return 0;
3477 }
3478
3479 static int skge_resume(struct pci_dev *pdev)
3480 {
3481 struct skge_hw *hw = pci_get_drvdata(pdev);
3482 int i;
3483
3484 pci_set_power_state(pdev, PCI_D0);
3485 pci_restore_state(pdev);
3486 pci_enable_wake(pdev, PCI_D0, 0);
3487
3488 skge_reset(hw);
3489
3490 for (i = 0; i < 2; i++) {
3491 struct net_device *dev = hw->dev[i];
3492 if (dev) {
3493 netif_device_attach(dev);
3494 if (netif_running(dev) && skge_up(dev))
3495 dev_close(dev);
3496 }
3497 }
3498 return 0;
3499 }
3500 #endif
3501
3502 static struct pci_driver skge_driver = {
3503 .name = DRV_NAME,
3504 .id_table = skge_id_table,
3505 .probe = skge_probe,
3506 .remove = __devexit_p(skge_remove),
3507 #ifdef CONFIG_PM
3508 .suspend = skge_suspend,
3509 .resume = skge_resume,
3510 #endif
3511 };
3512
3513 static int __init skge_init_module(void)
3514 {
3515 return pci_module_init(&skge_driver);
3516 }
3517
3518 static void __exit skge_cleanup_module(void)
3519 {
3520 pci_unregister_driver(&skge_driver);
3521 }
3522
3523 module_init(skge_init_module);
3524 module_exit(skge_cleanup_module);
kernel source for telekom puls (alcatel/mediatek)