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Merge /spare/repo/linux-2.6/
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / net / skge.c
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.0"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 /* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111 #define SKGE_REGS_LEN (29*128)
112
113 static int skge_get_regs_len(struct net_device *dev)
114 {
115 return SKGE_REGS_LEN;
116 }
117
118 /*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124 {
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143 }
144
145 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
146 static int wol_supported(const struct skge_hw *hw)
147 {
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
150 }
151
152 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153 {
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158 }
159
160 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161 {
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183 }
184
185 /* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188 static u32 skge_supported_modes(const struct skge_hw *hw)
189 {
190 u32 supported;
191
192 if (hw->copper) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214 }
215
216 static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218 {
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
223 ecmd->supported = skge_supported_modes(hw);
224
225 if (hw->copper) {
226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
228 } else
229 ecmd->port = PORT_FIBRE;
230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236 }
237
238 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239 {
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
242 u32 supported = skge_supported_modes(hw);
243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
248 } else {
249 u32 setting;
250
251 switch (ecmd->speed) {
252 case SPEED_1000:
253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
259 break;
260 case SPEED_100:
261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
269 case SPEED_10:
270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
286 }
287
288 skge->autoneg = ecmd->autoneg;
289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296 }
297
298 static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300 {
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307 }
308
309 static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313 } skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338 };
339
340 static int skge_get_stats_count(struct net_device *dev)
341 {
342 return ARRAY_SIZE(skge_stats);
343 }
344
345 static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347 {
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354 }
355
356 /* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360 static struct net_device_stats *skge_get_stats(struct net_device *dev)
361 {
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379 }
380
381 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382 {
383 int i;
384
385 switch (stringset) {
386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392 }
393
394 static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396 {
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408 }
409
410 static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412 {
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428 }
429
430 static u32 skge_get_msglevel(struct net_device *netdev)
431 {
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434 }
435
436 static void skge_set_msglevel(struct net_device *netdev, u32 value)
437 {
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440 }
441
442 static int skge_nway_reset(struct net_device *dev)
443 {
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461 }
462
463 static int skge_set_sg(struct net_device *dev, u32 data)
464 {
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471 }
472
473 static int skge_set_tx_csum(struct net_device *dev, u32 data)
474 {
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482 }
483
484 static u32 skge_get_rx_csum(struct net_device *dev)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489 }
490
491 /* Only Yukon supports checksum offload. */
492 static int skge_set_rx_csum(struct net_device *dev, u32 data)
493 {
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501 }
502
503 static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514 }
515
516 static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518 {
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
524 else if (ecmd->rx_pause && !ecmd->tx_pause)
525 skge->flow_control = FLOW_MODE_REM_SEND;
526 else if (!ecmd->rx_pause && ecmd->tx_pause)
527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536 }
537
538 /* Chip internal frequency for clock calculations */
539 static inline u32 hwkhz(const struct skge_hw *hw)
540 {
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
543 else
544 return 78215; /* or: 78.125 MHz */
545 }
546
547 /* Chip hz to microseconds */
548 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549 {
550 return (ticks * 1000) / hwkhz(hw);
551 }
552
553 /* Microseconds to chip hz */
554 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555 {
556 return hwkhz(hw) * usec / 1000;
557 }
558
559 static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561 {
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580 }
581
582 /* Note: interrupt timer is per board, but can turn on/off per port */
583 static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585 {
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620 }
621
622 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
623 static void skge_led(struct skge_port *skge, enum led_mode mode)
624 {
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
627
628 spin_lock_bh(&hw->phy_lock);
629 if (hw->chip_id == CHIP_ID_GENESIS) {
630 switch (mode) {
631 case LED_MODE_OFF:
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
633 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
634 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
635 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
636 break;
637
638 case LED_MODE_ON:
639 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
640 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
641
642 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
643 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
644
645 break;
646
647 case LED_MODE_TST:
648 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
649 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
650 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
651
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
653 break;
654 }
655 } else {
656 switch (mode) {
657 case LED_MODE_OFF:
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
665 break;
666 case LED_MODE_ON:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
668 PHY_M_LED_PULS_DUR(PULS_170MS) |
669 PHY_M_LED_BLINK_RT(BLINK_84MS) |
670 PHY_M_LEDC_TX_CTRL |
671 PHY_M_LEDC_DP_CTRL);
672
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_RX(MO_LED_OFF) |
675 (skge->speed == SPEED_100 ?
676 PHY_M_LED_MO_100(MO_LED_ON) : 0));
677 break;
678 case LED_MODE_TST:
679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
681 PHY_M_LED_MO_DUP(MO_LED_ON) |
682 PHY_M_LED_MO_10(MO_LED_ON) |
683 PHY_M_LED_MO_100(MO_LED_ON) |
684 PHY_M_LED_MO_1000(MO_LED_ON) |
685 PHY_M_LED_MO_RX(MO_LED_ON));
686 }
687 }
688 spin_unlock_bh(&hw->phy_lock);
689 }
690
691 /* blink LED's for finding board */
692 static int skge_phys_id(struct net_device *dev, u32 data)
693 {
694 struct skge_port *skge = netdev_priv(dev);
695 unsigned long ms;
696 enum led_mode mode = LED_MODE_TST;
697
698 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
699 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
700 else
701 ms = data * 1000;
702
703 while (ms > 0) {
704 skge_led(skge, mode);
705 mode ^= LED_MODE_TST;
706
707 if (msleep_interruptible(BLINK_MS))
708 break;
709 ms -= BLINK_MS;
710 }
711
712 /* back to regular LED state */
713 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
714
715 return 0;
716 }
717
718 static struct ethtool_ops skge_ethtool_ops = {
719 .get_settings = skge_get_settings,
720 .set_settings = skge_set_settings,
721 .get_drvinfo = skge_get_drvinfo,
722 .get_regs_len = skge_get_regs_len,
723 .get_regs = skge_get_regs,
724 .get_wol = skge_get_wol,
725 .set_wol = skge_set_wol,
726 .get_msglevel = skge_get_msglevel,
727 .set_msglevel = skge_set_msglevel,
728 .nway_reset = skge_nway_reset,
729 .get_link = ethtool_op_get_link,
730 .get_ringparam = skge_get_ring_param,
731 .set_ringparam = skge_set_ring_param,
732 .get_pauseparam = skge_get_pauseparam,
733 .set_pauseparam = skge_set_pauseparam,
734 .get_coalesce = skge_get_coalesce,
735 .set_coalesce = skge_set_coalesce,
736 .get_sg = ethtool_op_get_sg,
737 .set_sg = skge_set_sg,
738 .get_tx_csum = ethtool_op_get_tx_csum,
739 .set_tx_csum = skge_set_tx_csum,
740 .get_rx_csum = skge_get_rx_csum,
741 .set_rx_csum = skge_set_rx_csum,
742 .get_strings = skge_get_strings,
743 .phys_id = skge_phys_id,
744 .get_stats_count = skge_get_stats_count,
745 .get_ethtool_stats = skge_get_ethtool_stats,
746 .get_perm_addr = ethtool_op_get_perm_addr,
747 };
748
749 /*
750 * Allocate ring elements and chain them together
751 * One-to-one association of board descriptors with ring elements
752 */
753 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
754 {
755 struct skge_tx_desc *d;
756 struct skge_element *e;
757 int i;
758
759 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
760 if (!ring->start)
761 return -ENOMEM;
762
763 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
764 e->desc = d;
765 e->skb = NULL;
766 if (i == ring->count - 1) {
767 e->next = ring->start;
768 d->next_offset = base;
769 } else {
770 e->next = e + 1;
771 d->next_offset = base + (i+1) * sizeof(*d);
772 }
773 }
774 ring->to_use = ring->to_clean = ring->start;
775
776 return 0;
777 }
778
779 static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
780 {
781 struct sk_buff *skb = dev_alloc_skb(size);
782
783 if (likely(skb)) {
784 skb->dev = dev;
785 skb_reserve(skb, NET_IP_ALIGN);
786 }
787 return skb;
788 }
789
790 /* Allocate and setup a new buffer for receiving */
791 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
792 struct sk_buff *skb, unsigned int bufsize)
793 {
794 struct skge_rx_desc *rd = e->desc;
795 u64 map;
796
797 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
798 PCI_DMA_FROMDEVICE);
799
800 rd->dma_lo = map;
801 rd->dma_hi = map >> 32;
802 e->skb = skb;
803 rd->csum1_start = ETH_HLEN;
804 rd->csum2_start = ETH_HLEN;
805 rd->csum1 = 0;
806 rd->csum2 = 0;
807
808 wmb();
809
810 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
811 pci_unmap_addr_set(e, mapaddr, map);
812 pci_unmap_len_set(e, maplen, bufsize);
813 }
814
815 /* Resume receiving using existing skb,
816 * Note: DMA address is not changed by chip.
817 * MTU not changed while receiver active.
818 */
819 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
820 {
821 struct skge_rx_desc *rd = e->desc;
822
823 rd->csum2 = 0;
824 rd->csum2_start = ETH_HLEN;
825
826 wmb();
827
828 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
829 }
830
831
832 /* Free all buffers in receive ring, assumes receiver stopped */
833 static void skge_rx_clean(struct skge_port *skge)
834 {
835 struct skge_hw *hw = skge->hw;
836 struct skge_ring *ring = &skge->rx_ring;
837 struct skge_element *e;
838
839 e = ring->start;
840 do {
841 struct skge_rx_desc *rd = e->desc;
842 rd->control = 0;
843 if (e->skb) {
844 pci_unmap_single(hw->pdev,
845 pci_unmap_addr(e, mapaddr),
846 pci_unmap_len(e, maplen),
847 PCI_DMA_FROMDEVICE);
848 dev_kfree_skb(e->skb);
849 e->skb = NULL;
850 }
851 } while ((e = e->next) != ring->start);
852 }
853
854
855 /* Allocate buffers for receive ring
856 * For receive: to_clean is next received frame.
857 */
858 static int skge_rx_fill(struct skge_port *skge)
859 {
860 struct skge_ring *ring = &skge->rx_ring;
861 struct skge_element *e;
862 unsigned int bufsize = skge->rx_buf_size;
863
864 e = ring->start;
865 do {
866 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
867
868 if (!skb)
869 return -ENOMEM;
870
871 skge_rx_setup(skge, e, skb, bufsize);
872 } while ( (e = e->next) != ring->start);
873
874 ring->to_clean = ring->start;
875 return 0;
876 }
877
878 static void skge_link_up(struct skge_port *skge)
879 {
880 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
881 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
882
883 netif_carrier_on(skge->netdev);
884 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
885 netif_wake_queue(skge->netdev);
886
887 if (netif_msg_link(skge))
888 printk(KERN_INFO PFX
889 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
890 skge->netdev->name, skge->speed,
891 skge->duplex == DUPLEX_FULL ? "full" : "half",
892 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
893 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
894 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
895 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
896 "unknown");
897 }
898
899 static void skge_link_down(struct skge_port *skge)
900 {
901 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
902 netif_carrier_off(skge->netdev);
903 netif_stop_queue(skge->netdev);
904
905 if (netif_msg_link(skge))
906 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
907 }
908
909 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
910 {
911 int i;
912 u16 v;
913
914 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
915 v = xm_read16(hw, port, XM_PHY_DATA);
916
917 /* Need to wait for external PHY */
918 for (i = 0; i < PHY_RETRIES; i++) {
919 udelay(1);
920 if (xm_read16(hw, port, XM_MMU_CMD)
921 & XM_MMU_PHY_RDY)
922 goto ready;
923 }
924
925 printk(KERN_WARNING PFX "%s: phy read timed out\n",
926 hw->dev[port]->name);
927 return 0;
928 ready:
929 v = xm_read16(hw, port, XM_PHY_DATA);
930
931 return v;
932 }
933
934 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
935 {
936 int i;
937
938 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
939 for (i = 0; i < PHY_RETRIES; i++) {
940 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
941 goto ready;
942 udelay(1);
943 }
944 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
945 hw->dev[port]->name);
946
947
948 ready:
949 xm_write16(hw, port, XM_PHY_DATA, val);
950 for (i = 0; i < PHY_RETRIES; i++) {
951 udelay(1);
952 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
953 return;
954 }
955 printk(KERN_WARNING PFX "%s: phy write timed out\n",
956 hw->dev[port]->name);
957 }
958
959 static void genesis_init(struct skge_hw *hw)
960 {
961 /* set blink source counter */
962 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
963 skge_write8(hw, B2_BSC_CTRL, BSC_START);
964
965 /* configure mac arbiter */
966 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
967
968 /* configure mac arbiter timeout values */
969 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
970 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
971 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
972 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
973
974 skge_write8(hw, B3_MA_RCINI_RX1, 0);
975 skge_write8(hw, B3_MA_RCINI_RX2, 0);
976 skge_write8(hw, B3_MA_RCINI_TX1, 0);
977 skge_write8(hw, B3_MA_RCINI_TX2, 0);
978
979 /* configure packet arbiter timeout */
980 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
981 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
982 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
983 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
984 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
985 }
986
987 static void genesis_reset(struct skge_hw *hw, int port)
988 {
989 const u8 zero[8] = { 0 };
990
991 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
992
993 /* reset the statistics module */
994 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
995 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
996 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
997 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
998 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
999
1000 /* disable Broadcom PHY IRQ */
1001 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1002
1003 xm_outhash(hw, port, XM_HSM, zero);
1004 }
1005
1006
1007 /* Convert mode to MII values */
1008 static const u16 phy_pause_map[] = {
1009 [FLOW_MODE_NONE] = 0,
1010 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1011 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1012 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1013 };
1014
1015
1016 /* Check status of Broadcom phy link */
1017 static void bcom_check_link(struct skge_hw *hw, int port)
1018 {
1019 struct net_device *dev = hw->dev[port];
1020 struct skge_port *skge = netdev_priv(dev);
1021 u16 status;
1022
1023 /* read twice because of latch */
1024 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1025 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1026
1027 if ((status & PHY_ST_LSYNC) == 0) {
1028 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1029 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1030 xm_write16(hw, port, XM_MMU_CMD, cmd);
1031 /* dummy read to ensure writing */
1032 (void) xm_read16(hw, port, XM_MMU_CMD);
1033
1034 if (netif_carrier_ok(dev))
1035 skge_link_down(skge);
1036 } else {
1037 if (skge->autoneg == AUTONEG_ENABLE &&
1038 (status & PHY_ST_AN_OVER)) {
1039 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1040 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1041
1042 if (lpa & PHY_B_AN_RF) {
1043 printk(KERN_NOTICE PFX "%s: remote fault\n",
1044 dev->name);
1045 return;
1046 }
1047
1048 /* Check Duplex mismatch */
1049 switch (aux & PHY_B_AS_AN_RES_MSK) {
1050 case PHY_B_RES_1000FD:
1051 skge->duplex = DUPLEX_FULL;
1052 break;
1053 case PHY_B_RES_1000HD:
1054 skge->duplex = DUPLEX_HALF;
1055 break;
1056 default:
1057 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1058 dev->name);
1059 return;
1060 }
1061
1062
1063 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1064 switch (aux & PHY_B_AS_PAUSE_MSK) {
1065 case PHY_B_AS_PAUSE_MSK:
1066 skge->flow_control = FLOW_MODE_SYMMETRIC;
1067 break;
1068 case PHY_B_AS_PRR:
1069 skge->flow_control = FLOW_MODE_REM_SEND;
1070 break;
1071 case PHY_B_AS_PRT:
1072 skge->flow_control = FLOW_MODE_LOC_SEND;
1073 break;
1074 default:
1075 skge->flow_control = FLOW_MODE_NONE;
1076 }
1077
1078 skge->speed = SPEED_1000;
1079 }
1080
1081 if (!netif_carrier_ok(dev))
1082 genesis_link_up(skge);
1083 }
1084 }
1085
1086 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1087 * Phy on for 100 or 10Mbit operation
1088 */
1089 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1090 {
1091 struct skge_hw *hw = skge->hw;
1092 int port = skge->port;
1093 int i;
1094 u16 id1, r, ext, ctl;
1095
1096 /* magic workaround patterns for Broadcom */
1097 static const struct {
1098 u16 reg;
1099 u16 val;
1100 } A1hack[] = {
1101 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1102 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1103 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1104 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1105 }, C0hack[] = {
1106 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1107 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1108 };
1109
1110 /* read Id from external PHY (all have the same address) */
1111 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1112
1113 /* Optimize MDIO transfer by suppressing preamble. */
1114 r = xm_read16(hw, port, XM_MMU_CMD);
1115 r |= XM_MMU_NO_PRE;
1116 xm_write16(hw, port, XM_MMU_CMD,r);
1117
1118 switch (id1) {
1119 case PHY_BCOM_ID1_C0:
1120 /*
1121 * Workaround BCOM Errata for the C0 type.
1122 * Write magic patterns to reserved registers.
1123 */
1124 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1125 xm_phy_write(hw, port,
1126 C0hack[i].reg, C0hack[i].val);
1127
1128 break;
1129 case PHY_BCOM_ID1_A1:
1130 /*
1131 * Workaround BCOM Errata for the A1 type.
1132 * Write magic patterns to reserved registers.
1133 */
1134 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1135 xm_phy_write(hw, port,
1136 A1hack[i].reg, A1hack[i].val);
1137 break;
1138 }
1139
1140 /*
1141 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1142 * Disable Power Management after reset.
1143 */
1144 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1145 r |= PHY_B_AC_DIS_PM;
1146 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1147
1148 /* Dummy read */
1149 xm_read16(hw, port, XM_ISRC);
1150
1151 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1152 ctl = PHY_CT_SP1000; /* always 1000mbit */
1153
1154 if (skge->autoneg == AUTONEG_ENABLE) {
1155 /*
1156 * Workaround BCOM Errata #1 for the C5 type.
1157 * 1000Base-T Link Acquisition Failure in Slave Mode
1158 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1159 */
1160 u16 adv = PHY_B_1000C_RD;
1161 if (skge->advertising & ADVERTISED_1000baseT_Half)
1162 adv |= PHY_B_1000C_AHD;
1163 if (skge->advertising & ADVERTISED_1000baseT_Full)
1164 adv |= PHY_B_1000C_AFD;
1165 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1166
1167 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1168 } else {
1169 if (skge->duplex == DUPLEX_FULL)
1170 ctl |= PHY_CT_DUP_MD;
1171 /* Force to slave */
1172 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1173 }
1174
1175 /* Set autonegotiation pause parameters */
1176 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1177 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1178
1179 /* Handle Jumbo frames */
1180 if (jumbo) {
1181 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1182 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1183
1184 ext |= PHY_B_PEC_HIGH_LA;
1185
1186 }
1187
1188 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1189 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1190
1191 /* Use link status change interrrupt */
1192 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1193
1194 bcom_check_link(hw, port);
1195 }
1196
1197 static void genesis_mac_init(struct skge_hw *hw, int port)
1198 {
1199 struct net_device *dev = hw->dev[port];
1200 struct skge_port *skge = netdev_priv(dev);
1201 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1202 int i;
1203 u32 r;
1204 const u8 zero[6] = { 0 };
1205
1206 /* Clear MIB counters */
1207 xm_write16(hw, port, XM_STAT_CMD,
1208 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1209 /* Clear two times according to Errata #3 */
1210 xm_write16(hw, port, XM_STAT_CMD,
1211 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1212
1213 /* Unreset the XMAC. */
1214 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1215
1216 /*
1217 * Perform additional initialization for external PHYs,
1218 * namely for the 1000baseTX cards that use the XMAC's
1219 * GMII mode.
1220 */
1221 /* Take external Phy out of reset */
1222 r = skge_read32(hw, B2_GP_IO);
1223 if (port == 0)
1224 r |= GP_DIR_0|GP_IO_0;
1225 else
1226 r |= GP_DIR_2|GP_IO_2;
1227
1228 skge_write32(hw, B2_GP_IO, r);
1229 skge_read32(hw, B2_GP_IO);
1230
1231 /* Enable GMII interfac */
1232 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1233
1234 bcom_phy_init(skge, jumbo);
1235
1236 /* Set Station Address */
1237 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1238
1239 /* We don't use match addresses so clear */
1240 for (i = 1; i < 16; i++)
1241 xm_outaddr(hw, port, XM_EXM(i), zero);
1242
1243 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1244 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1245
1246 /* We don't need the FCS appended to the packet. */
1247 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1248 if (jumbo)
1249 r |= XM_RX_BIG_PK_OK;
1250
1251 if (skge->duplex == DUPLEX_HALF) {
1252 /*
1253 * If in manual half duplex mode the other side might be in
1254 * full duplex mode, so ignore if a carrier extension is not seen
1255 * on frames received
1256 */
1257 r |= XM_RX_DIS_CEXT;
1258 }
1259 xm_write16(hw, port, XM_RX_CMD, r);
1260
1261
1262 /* We want short frames padded to 60 bytes. */
1263 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1264
1265 /*
1266 * Bump up the transmit threshold. This helps hold off transmit
1267 * underruns when we're blasting traffic from both ports at once.
1268 */
1269 xm_write16(hw, port, XM_TX_THR, 512);
1270
1271 /*
1272 * Enable the reception of all error frames. This is is
1273 * a necessary evil due to the design of the XMAC. The
1274 * XMAC's receive FIFO is only 8K in size, however jumbo
1275 * frames can be up to 9000 bytes in length. When bad
1276 * frame filtering is enabled, the XMAC's RX FIFO operates
1277 * in 'store and forward' mode. For this to work, the
1278 * entire frame has to fit into the FIFO, but that means
1279 * that jumbo frames larger than 8192 bytes will be
1280 * truncated. Disabling all bad frame filtering causes
1281 * the RX FIFO to operate in streaming mode, in which
1282 * case the XMAC will start transfering frames out of the
1283 * RX FIFO as soon as the FIFO threshold is reached.
1284 */
1285 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1286
1287
1288 /*
1289 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1290 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1291 * and 'Octets Rx OK Hi Cnt Ov'.
1292 */
1293 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1294
1295 /*
1296 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1297 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1298 * and 'Octets Tx OK Hi Cnt Ov'.
1299 */
1300 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1301
1302 /* Configure MAC arbiter */
1303 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1304
1305 /* configure timeout values */
1306 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1307 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1308 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1309 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1310
1311 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1312 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1313 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1314 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1315
1316 /* Configure Rx MAC FIFO */
1317 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1318 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1319 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1320
1321 /* Configure Tx MAC FIFO */
1322 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1323 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1324 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1325
1326 if (jumbo) {
1327 /* Enable frame flushing if jumbo frames used */
1328 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1329 } else {
1330 /* enable timeout timers if normal frames */
1331 skge_write16(hw, B3_PA_CTRL,
1332 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1333 }
1334 }
1335
1336 static void genesis_stop(struct skge_port *skge)
1337 {
1338 struct skge_hw *hw = skge->hw;
1339 int port = skge->port;
1340 u32 reg;
1341
1342 genesis_reset(hw, port);
1343
1344 /* Clear Tx packet arbiter timeout IRQ */
1345 skge_write16(hw, B3_PA_CTRL,
1346 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1347
1348 /*
1349 * If the transfer stucks at the MAC the STOP command will not
1350 * terminate if we don't flush the XMAC's transmit FIFO !
1351 */
1352 xm_write32(hw, port, XM_MODE,
1353 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1354
1355
1356 /* Reset the MAC */
1357 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1358
1359 /* For external PHYs there must be special handling */
1360 reg = skge_read32(hw, B2_GP_IO);
1361 if (port == 0) {
1362 reg |= GP_DIR_0;
1363 reg &= ~GP_IO_0;
1364 } else {
1365 reg |= GP_DIR_2;
1366 reg &= ~GP_IO_2;
1367 }
1368 skge_write32(hw, B2_GP_IO, reg);
1369 skge_read32(hw, B2_GP_IO);
1370
1371 xm_write16(hw, port, XM_MMU_CMD,
1372 xm_read16(hw, port, XM_MMU_CMD)
1373 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1374
1375 xm_read16(hw, port, XM_MMU_CMD);
1376 }
1377
1378
1379 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1380 {
1381 struct skge_hw *hw = skge->hw;
1382 int port = skge->port;
1383 int i;
1384 unsigned long timeout = jiffies + HZ;
1385
1386 xm_write16(hw, port,
1387 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1388
1389 /* wait for update to complete */
1390 while (xm_read16(hw, port, XM_STAT_CMD)
1391 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1392 if (time_after(jiffies, timeout))
1393 break;
1394 udelay(10);
1395 }
1396
1397 /* special case for 64 bit octet counter */
1398 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1399 | xm_read32(hw, port, XM_TXO_OK_LO);
1400 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1401 | xm_read32(hw, port, XM_RXO_OK_LO);
1402
1403 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1404 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1405 }
1406
1407 static void genesis_mac_intr(struct skge_hw *hw, int port)
1408 {
1409 struct skge_port *skge = netdev_priv(hw->dev[port]);
1410 u16 status = xm_read16(hw, port, XM_ISRC);
1411
1412 if (netif_msg_intr(skge))
1413 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1414 skge->netdev->name, status);
1415
1416 if (status & XM_IS_TXF_UR) {
1417 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1418 ++skge->net_stats.tx_fifo_errors;
1419 }
1420 if (status & XM_IS_RXF_OV) {
1421 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1422 ++skge->net_stats.rx_fifo_errors;
1423 }
1424 }
1425
1426 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1427 {
1428 int i;
1429
1430 gma_write16(hw, port, GM_SMI_DATA, val);
1431 gma_write16(hw, port, GM_SMI_CTRL,
1432 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1433 for (i = 0; i < PHY_RETRIES; i++) {
1434 udelay(1);
1435
1436 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1437 break;
1438 }
1439 }
1440
1441 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1442 {
1443 int i;
1444
1445 gma_write16(hw, port, GM_SMI_CTRL,
1446 GM_SMI_CT_PHY_AD(hw->phy_addr)
1447 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1448
1449 for (i = 0; i < PHY_RETRIES; i++) {
1450 udelay(1);
1451 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1452 goto ready;
1453 }
1454
1455 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1456 hw->dev[port]->name);
1457 return 0;
1458 ready:
1459 return gma_read16(hw, port, GM_SMI_DATA);
1460 }
1461
1462 static void genesis_link_up(struct skge_port *skge)
1463 {
1464 struct skge_hw *hw = skge->hw;
1465 int port = skge->port;
1466 u16 cmd;
1467 u32 mode, msk;
1468
1469 cmd = xm_read16(hw, port, XM_MMU_CMD);
1470
1471 /*
1472 * enabling pause frame reception is required for 1000BT
1473 * because the XMAC is not reset if the link is going down
1474 */
1475 if (skge->flow_control == FLOW_MODE_NONE ||
1476 skge->flow_control == FLOW_MODE_LOC_SEND)
1477 /* Disable Pause Frame Reception */
1478 cmd |= XM_MMU_IGN_PF;
1479 else
1480 /* Enable Pause Frame Reception */
1481 cmd &= ~XM_MMU_IGN_PF;
1482
1483 xm_write16(hw, port, XM_MMU_CMD, cmd);
1484
1485 mode = xm_read32(hw, port, XM_MODE);
1486 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1487 skge->flow_control == FLOW_MODE_LOC_SEND) {
1488 /*
1489 * Configure Pause Frame Generation
1490 * Use internal and external Pause Frame Generation.
1491 * Sending pause frames is edge triggered.
1492 * Send a Pause frame with the maximum pause time if
1493 * internal oder external FIFO full condition occurs.
1494 * Send a zero pause time frame to re-start transmission.
1495 */
1496 /* XM_PAUSE_DA = '010000C28001' (default) */
1497 /* XM_MAC_PTIME = 0xffff (maximum) */
1498 /* remember this value is defined in big endian (!) */
1499 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1500
1501 mode |= XM_PAUSE_MODE;
1502 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1503 } else {
1504 /*
1505 * disable pause frame generation is required for 1000BT
1506 * because the XMAC is not reset if the link is going down
1507 */
1508 /* Disable Pause Mode in Mode Register */
1509 mode &= ~XM_PAUSE_MODE;
1510
1511 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1512 }
1513
1514 xm_write32(hw, port, XM_MODE, mode);
1515
1516 msk = XM_DEF_MSK;
1517 /* disable GP0 interrupt bit for external Phy */
1518 msk |= XM_IS_INP_ASS;
1519
1520 xm_write16(hw, port, XM_IMSK, msk);
1521 xm_read16(hw, port, XM_ISRC);
1522
1523 /* get MMU Command Reg. */
1524 cmd = xm_read16(hw, port, XM_MMU_CMD);
1525 if (skge->duplex == DUPLEX_FULL)
1526 cmd |= XM_MMU_GMII_FD;
1527
1528 /*
1529 * Workaround BCOM Errata (#10523) for all BCom Phys
1530 * Enable Power Management after link up
1531 */
1532 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1533 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1534 & ~PHY_B_AC_DIS_PM);
1535 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1536
1537 /* enable Rx/Tx */
1538 xm_write16(hw, port, XM_MMU_CMD,
1539 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1540 skge_link_up(skge);
1541 }
1542
1543
1544 static inline void bcom_phy_intr(struct skge_port *skge)
1545 {
1546 struct skge_hw *hw = skge->hw;
1547 int port = skge->port;
1548 u16 isrc;
1549
1550 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1551 if (netif_msg_intr(skge))
1552 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1553 skge->netdev->name, isrc);
1554
1555 if (isrc & PHY_B_IS_PSE)
1556 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1557 hw->dev[port]->name);
1558
1559 /* Workaround BCom Errata:
1560 * enable and disable loopback mode if "NO HCD" occurs.
1561 */
1562 if (isrc & PHY_B_IS_NO_HDCL) {
1563 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1564 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1565 ctrl | PHY_CT_LOOP);
1566 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1567 ctrl & ~PHY_CT_LOOP);
1568 }
1569
1570 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1571 bcom_check_link(hw, port);
1572
1573 }
1574
1575 /* Marvell Phy Initailization */
1576 static void yukon_init(struct skge_hw *hw, int port)
1577 {
1578 struct skge_port *skge = netdev_priv(hw->dev[port]);
1579 u16 ctrl, ct1000, adv;
1580
1581 if (skge->autoneg == AUTONEG_ENABLE) {
1582 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1583
1584 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1585 PHY_M_EC_MAC_S_MSK);
1586 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1587
1588 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1589
1590 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1591 }
1592
1593 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1594 if (skge->autoneg == AUTONEG_DISABLE)
1595 ctrl &= ~PHY_CT_ANE;
1596
1597 ctrl |= PHY_CT_RESET;
1598 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1599
1600 ctrl = 0;
1601 ct1000 = 0;
1602 adv = PHY_AN_CSMA;
1603
1604 if (skge->autoneg == AUTONEG_ENABLE) {
1605 if (hw->copper) {
1606 if (skge->advertising & ADVERTISED_1000baseT_Full)
1607 ct1000 |= PHY_M_1000C_AFD;
1608 if (skge->advertising & ADVERTISED_1000baseT_Half)
1609 ct1000 |= PHY_M_1000C_AHD;
1610 if (skge->advertising & ADVERTISED_100baseT_Full)
1611 adv |= PHY_M_AN_100_FD;
1612 if (skge->advertising & ADVERTISED_100baseT_Half)
1613 adv |= PHY_M_AN_100_HD;
1614 if (skge->advertising & ADVERTISED_10baseT_Full)
1615 adv |= PHY_M_AN_10_FD;
1616 if (skge->advertising & ADVERTISED_10baseT_Half)
1617 adv |= PHY_M_AN_10_HD;
1618 } else /* special defines for FIBER (88E1011S only) */
1619 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1620
1621 /* Set Flow-control capabilities */
1622 adv |= phy_pause_map[skge->flow_control];
1623
1624 /* Restart Auto-negotiation */
1625 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1626 } else {
1627 /* forced speed/duplex settings */
1628 ct1000 = PHY_M_1000C_MSE;
1629
1630 if (skge->duplex == DUPLEX_FULL)
1631 ctrl |= PHY_CT_DUP_MD;
1632
1633 switch (skge->speed) {
1634 case SPEED_1000:
1635 ctrl |= PHY_CT_SP1000;
1636 break;
1637 case SPEED_100:
1638 ctrl |= PHY_CT_SP100;
1639 break;
1640 }
1641
1642 ctrl |= PHY_CT_RESET;
1643 }
1644
1645 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1646
1647 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1648 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1649
1650 /* Enable phy interrupt on autonegotiation complete (or link up) */
1651 if (skge->autoneg == AUTONEG_ENABLE)
1652 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1653 else
1654 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1655 }
1656
1657 static void yukon_reset(struct skge_hw *hw, int port)
1658 {
1659 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1660 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1661 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1662 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1663 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1664
1665 gma_write16(hw, port, GM_RX_CTRL,
1666 gma_read16(hw, port, GM_RX_CTRL)
1667 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1668 }
1669
1670 static void yukon_mac_init(struct skge_hw *hw, int port)
1671 {
1672 struct skge_port *skge = netdev_priv(hw->dev[port]);
1673 int i;
1674 u32 reg;
1675 const u8 *addr = hw->dev[port]->dev_addr;
1676
1677 /* WA code for COMA mode -- set PHY reset */
1678 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1679 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1680 reg = skge_read32(hw, B2_GP_IO);
1681 reg |= GP_DIR_9 | GP_IO_9;
1682 skge_write32(hw, B2_GP_IO, reg);
1683 }
1684
1685 /* hard reset */
1686 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1687 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1688
1689 /* WA code for COMA mode -- clear PHY reset */
1690 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1691 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1692 reg = skge_read32(hw, B2_GP_IO);
1693 reg |= GP_DIR_9;
1694 reg &= ~GP_IO_9;
1695 skge_write32(hw, B2_GP_IO, reg);
1696 }
1697
1698 /* Set hardware config mode */
1699 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1700 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1701 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1702
1703 /* Clear GMC reset */
1704 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1705 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1706 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1707 if (skge->autoneg == AUTONEG_DISABLE) {
1708 reg = GM_GPCR_AU_ALL_DIS;
1709 gma_write16(hw, port, GM_GP_CTRL,
1710 gma_read16(hw, port, GM_GP_CTRL) | reg);
1711
1712 switch (skge->speed) {
1713 case SPEED_1000:
1714 reg |= GM_GPCR_SPEED_1000;
1715 /* fallthru */
1716 case SPEED_100:
1717 reg |= GM_GPCR_SPEED_100;
1718 }
1719
1720 if (skge->duplex == DUPLEX_FULL)
1721 reg |= GM_GPCR_DUP_FULL;
1722 } else
1723 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1724 switch (skge->flow_control) {
1725 case FLOW_MODE_NONE:
1726 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1727 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1728 break;
1729 case FLOW_MODE_LOC_SEND:
1730 /* disable Rx flow-control */
1731 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1732 }
1733
1734 gma_write16(hw, port, GM_GP_CTRL, reg);
1735 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1736
1737 yukon_init(hw, port);
1738
1739 /* MIB clear */
1740 reg = gma_read16(hw, port, GM_PHY_ADDR);
1741 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1742
1743 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1744 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1745 gma_write16(hw, port, GM_PHY_ADDR, reg);
1746
1747 /* transmit control */
1748 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1749
1750 /* receive control reg: unicast + multicast + no FCS */
1751 gma_write16(hw, port, GM_RX_CTRL,
1752 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1753
1754 /* transmit flow control */
1755 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1756
1757 /* transmit parameter */
1758 gma_write16(hw, port, GM_TX_PARAM,
1759 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1760 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1761 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1762
1763 /* serial mode register */
1764 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1765 if (hw->dev[port]->mtu > 1500)
1766 reg |= GM_SMOD_JUMBO_ENA;
1767
1768 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1769
1770 /* physical address: used for pause frames */
1771 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1772 /* virtual address for data */
1773 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1774
1775 /* enable interrupt mask for counter overflows */
1776 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1777 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1778 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1779
1780 /* Initialize Mac Fifo */
1781
1782 /* Configure Rx MAC FIFO */
1783 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1784 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1785 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1786 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1787 reg &= ~GMF_RX_F_FL_ON;
1788 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1789 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1790 /*
1791 * because Pause Packet Truncation in GMAC is not working
1792 * we have to increase the Flush Threshold to 64 bytes
1793 * in order to flush pause packets in Rx FIFO on Yukon-1
1794 */
1795 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1796
1797 /* Configure Tx MAC FIFO */
1798 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1799 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1800 }
1801
1802 static void yukon_stop(struct skge_port *skge)
1803 {
1804 struct skge_hw *hw = skge->hw;
1805 int port = skge->port;
1806
1807 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1808 yukon_reset(hw, port);
1809
1810 gma_write16(hw, port, GM_GP_CTRL,
1811 gma_read16(hw, port, GM_GP_CTRL)
1812 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1813 gma_read16(hw, port, GM_GP_CTRL);
1814
1815 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1816 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1817 u32 io = skge_read32(hw, B2_GP_IO);
1818
1819 io |= GP_DIR_9 | GP_IO_9;
1820 skge_write32(hw, B2_GP_IO, io);
1821 skge_read32(hw, B2_GP_IO);
1822 }
1823
1824 /* set GPHY Control reset */
1825 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1826 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1827 }
1828
1829 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1830 {
1831 struct skge_hw *hw = skge->hw;
1832 int port = skge->port;
1833 int i;
1834
1835 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1836 | gma_read32(hw, port, GM_TXO_OK_LO);
1837 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1838 | gma_read32(hw, port, GM_RXO_OK_LO);
1839
1840 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1841 data[i] = gma_read32(hw, port,
1842 skge_stats[i].gma_offset);
1843 }
1844
1845 static void yukon_mac_intr(struct skge_hw *hw, int port)
1846 {
1847 struct net_device *dev = hw->dev[port];
1848 struct skge_port *skge = netdev_priv(dev);
1849 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1850
1851 if (netif_msg_intr(skge))
1852 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1853 dev->name, status);
1854
1855 if (status & GM_IS_RX_FF_OR) {
1856 ++skge->net_stats.rx_fifo_errors;
1857 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1858 }
1859
1860 if (status & GM_IS_TX_FF_UR) {
1861 ++skge->net_stats.tx_fifo_errors;
1862 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1863 }
1864
1865 }
1866
1867 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1868 {
1869 switch (aux & PHY_M_PS_SPEED_MSK) {
1870 case PHY_M_PS_SPEED_1000:
1871 return SPEED_1000;
1872 case PHY_M_PS_SPEED_100:
1873 return SPEED_100;
1874 default:
1875 return SPEED_10;
1876 }
1877 }
1878
1879 static void yukon_link_up(struct skge_port *skge)
1880 {
1881 struct skge_hw *hw = skge->hw;
1882 int port = skge->port;
1883 u16 reg;
1884
1885 /* Enable Transmit FIFO Underrun */
1886 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1887
1888 reg = gma_read16(hw, port, GM_GP_CTRL);
1889 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1890 reg |= GM_GPCR_DUP_FULL;
1891
1892 /* enable Rx/Tx */
1893 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1894 gma_write16(hw, port, GM_GP_CTRL, reg);
1895
1896 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1897 skge_link_up(skge);
1898 }
1899
1900 static void yukon_link_down(struct skge_port *skge)
1901 {
1902 struct skge_hw *hw = skge->hw;
1903 int port = skge->port;
1904 u16 ctrl;
1905
1906 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1907
1908 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1909 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1910 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1911
1912 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1913 /* restore Asymmetric Pause bit */
1914 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1915 gm_phy_read(hw, port,
1916 PHY_MARV_AUNE_ADV)
1917 | PHY_M_AN_ASP);
1918
1919 }
1920
1921 yukon_reset(hw, port);
1922 skge_link_down(skge);
1923
1924 yukon_init(hw, port);
1925 }
1926
1927 static void yukon_phy_intr(struct skge_port *skge)
1928 {
1929 struct skge_hw *hw = skge->hw;
1930 int port = skge->port;
1931 const char *reason = NULL;
1932 u16 istatus, phystat;
1933
1934 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1935 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1936
1937 if (netif_msg_intr(skge))
1938 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1939 skge->netdev->name, istatus, phystat);
1940
1941 if (istatus & PHY_M_IS_AN_COMPL) {
1942 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1943 & PHY_M_AN_RF) {
1944 reason = "remote fault";
1945 goto failed;
1946 }
1947
1948 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1949 reason = "master/slave fault";
1950 goto failed;
1951 }
1952
1953 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1954 reason = "speed/duplex";
1955 goto failed;
1956 }
1957
1958 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1959 ? DUPLEX_FULL : DUPLEX_HALF;
1960 skge->speed = yukon_speed(hw, phystat);
1961
1962 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1963 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1964 case PHY_M_PS_PAUSE_MSK:
1965 skge->flow_control = FLOW_MODE_SYMMETRIC;
1966 break;
1967 case PHY_M_PS_RX_P_EN:
1968 skge->flow_control = FLOW_MODE_REM_SEND;
1969 break;
1970 case PHY_M_PS_TX_P_EN:
1971 skge->flow_control = FLOW_MODE_LOC_SEND;
1972 break;
1973 default:
1974 skge->flow_control = FLOW_MODE_NONE;
1975 }
1976
1977 if (skge->flow_control == FLOW_MODE_NONE ||
1978 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1979 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1980 else
1981 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1982 yukon_link_up(skge);
1983 return;
1984 }
1985
1986 if (istatus & PHY_M_IS_LSP_CHANGE)
1987 skge->speed = yukon_speed(hw, phystat);
1988
1989 if (istatus & PHY_M_IS_DUP_CHANGE)
1990 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1991 if (istatus & PHY_M_IS_LST_CHANGE) {
1992 if (phystat & PHY_M_PS_LINK_UP)
1993 yukon_link_up(skge);
1994 else
1995 yukon_link_down(skge);
1996 }
1997 return;
1998 failed:
1999 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2000 skge->netdev->name, reason);
2001
2002 /* XXX restart autonegotiation? */
2003 }
2004
2005 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2006 {
2007 u32 end;
2008
2009 start /= 8;
2010 len /= 8;
2011 end = start + len - 1;
2012
2013 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2014 skge_write32(hw, RB_ADDR(q, RB_START), start);
2015 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2016 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2017 skge_write32(hw, RB_ADDR(q, RB_END), end);
2018
2019 if (q == Q_R1 || q == Q_R2) {
2020 /* Set thresholds on receive queue's */
2021 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2022 start + (2*len)/3);
2023 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2024 start + (len/3));
2025 } else {
2026 /* Enable store & forward on Tx queue's because
2027 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2028 */
2029 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2030 }
2031
2032 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2033 }
2034
2035 /* Setup Bus Memory Interface */
2036 static void skge_qset(struct skge_port *skge, u16 q,
2037 const struct skge_element *e)
2038 {
2039 struct skge_hw *hw = skge->hw;
2040 u32 watermark = 0x600;
2041 u64 base = skge->dma + (e->desc - skge->mem);
2042
2043 /* optimization to reduce window on 32bit/33mhz */
2044 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2045 watermark /= 2;
2046
2047 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2048 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2049 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2050 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2051 }
2052
2053 static int skge_up(struct net_device *dev)
2054 {
2055 struct skge_port *skge = netdev_priv(dev);
2056 struct skge_hw *hw = skge->hw;
2057 int port = skge->port;
2058 u32 chunk, ram_addr;
2059 size_t rx_size, tx_size;
2060 int err;
2061
2062 if (netif_msg_ifup(skge))
2063 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2064
2065 if (dev->mtu > RX_BUF_SIZE)
2066 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2067 else
2068 skge->rx_buf_size = RX_BUF_SIZE;
2069
2070
2071 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2072 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2073 skge->mem_size = tx_size + rx_size;
2074 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2075 if (!skge->mem)
2076 return -ENOMEM;
2077
2078 memset(skge->mem, 0, skge->mem_size);
2079
2080 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2081 goto free_pci_mem;
2082
2083 err = skge_rx_fill(skge);
2084 if (err)
2085 goto free_rx_ring;
2086
2087 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2088 skge->dma + rx_size)))
2089 goto free_rx_ring;
2090
2091 skge->tx_avail = skge->tx_ring.count - 1;
2092
2093 /* Enable IRQ from port */
2094 hw->intr_mask |= portirqmask[port];
2095 skge_write32(hw, B0_IMSK, hw->intr_mask);
2096
2097 /* Initialze MAC */
2098 spin_lock_bh(&hw->phy_lock);
2099 if (hw->chip_id == CHIP_ID_GENESIS)
2100 genesis_mac_init(hw, port);
2101 else
2102 yukon_mac_init(hw, port);
2103 spin_unlock_bh(&hw->phy_lock);
2104
2105 /* Configure RAMbuffers */
2106 chunk = hw->ram_size / ((hw->ports + 1)*2);
2107 ram_addr = hw->ram_offset + 2 * chunk * port;
2108
2109 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2110 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2111
2112 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2113 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2114 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2115
2116 /* Start receiver BMU */
2117 wmb();
2118 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2119 skge_led(skge, LED_MODE_ON);
2120
2121 return 0;
2122
2123 free_rx_ring:
2124 skge_rx_clean(skge);
2125 kfree(skge->rx_ring.start);
2126 free_pci_mem:
2127 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2128
2129 return err;
2130 }
2131
2132 static int skge_down(struct net_device *dev)
2133 {
2134 struct skge_port *skge = netdev_priv(dev);
2135 struct skge_hw *hw = skge->hw;
2136 int port = skge->port;
2137
2138 if (netif_msg_ifdown(skge))
2139 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2140
2141 netif_stop_queue(dev);
2142
2143 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2144 if (hw->chip_id == CHIP_ID_GENESIS)
2145 genesis_stop(skge);
2146 else
2147 yukon_stop(skge);
2148
2149 hw->intr_mask &= ~portirqmask[skge->port];
2150 skge_write32(hw, B0_IMSK, hw->intr_mask);
2151
2152 /* Stop transmitter */
2153 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2154 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2155 RB_RST_SET|RB_DIS_OP_MD);
2156
2157
2158 /* Disable Force Sync bit and Enable Alloc bit */
2159 skge_write8(hw, SK_REG(port, TXA_CTRL),
2160 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2161
2162 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2163 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2164 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2165
2166 /* Reset PCI FIFO */
2167 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2168 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2169
2170 /* Reset the RAM Buffer async Tx queue */
2171 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2172 /* stop receiver */
2173 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2174 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2175 RB_RST_SET|RB_DIS_OP_MD);
2176 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2177
2178 if (hw->chip_id == CHIP_ID_GENESIS) {
2179 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2180 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2181 } else {
2182 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2183 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2184 }
2185
2186 skge_led(skge, LED_MODE_OFF);
2187
2188 skge_tx_clean(skge);
2189 skge_rx_clean(skge);
2190
2191 kfree(skge->rx_ring.start);
2192 kfree(skge->tx_ring.start);
2193 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2194 return 0;
2195 }
2196
2197 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2198 {
2199 struct skge_port *skge = netdev_priv(dev);
2200 struct skge_hw *hw = skge->hw;
2201 struct skge_ring *ring = &skge->tx_ring;
2202 struct skge_element *e;
2203 struct skge_tx_desc *td;
2204 int i;
2205 u32 control, len;
2206 u64 map;
2207 unsigned long flags;
2208
2209 skb = skb_padto(skb, ETH_ZLEN);
2210 if (!skb)
2211 return NETDEV_TX_OK;
2212
2213 local_irq_save(flags);
2214 if (!spin_trylock(&skge->tx_lock)) {
2215 /* Collision - tell upper layer to requeue */
2216 local_irq_restore(flags);
2217 return NETDEV_TX_LOCKED;
2218 }
2219
2220 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2221 netif_stop_queue(dev);
2222 spin_unlock_irqrestore(&skge->tx_lock, flags);
2223
2224 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2225 dev->name);
2226 return NETDEV_TX_BUSY;
2227 }
2228
2229 e = ring->to_use;
2230 td = e->desc;
2231 e->skb = skb;
2232 len = skb_headlen(skb);
2233 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2234 pci_unmap_addr_set(e, mapaddr, map);
2235 pci_unmap_len_set(e, maplen, len);
2236
2237 td->dma_lo = map;
2238 td->dma_hi = map >> 32;
2239
2240 if (skb->ip_summed == CHECKSUM_HW) {
2241 const struct iphdr *ip
2242 = (const struct iphdr *) (skb->data + ETH_HLEN);
2243 int offset = skb->h.raw - skb->data;
2244
2245 /* This seems backwards, but it is what the sk98lin
2246 * does. Looks like hardware is wrong?
2247 */
2248 if (ip->protocol == IPPROTO_UDP
2249 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2250 control = BMU_TCP_CHECK;
2251 else
2252 control = BMU_UDP_CHECK;
2253
2254 td->csum_offs = 0;
2255 td->csum_start = offset;
2256 td->csum_write = offset + skb->csum;
2257 } else
2258 control = BMU_CHECK;
2259
2260 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2261 control |= BMU_EOF| BMU_IRQ_EOF;
2262 else {
2263 struct skge_tx_desc *tf = td;
2264
2265 control |= BMU_STFWD;
2266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2267 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2268
2269 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2270 frag->size, PCI_DMA_TODEVICE);
2271
2272 e = e->next;
2273 e->skb = NULL;
2274 tf = e->desc;
2275 tf->dma_lo = map;
2276 tf->dma_hi = (u64) map >> 32;
2277 pci_unmap_addr_set(e, mapaddr, map);
2278 pci_unmap_len_set(e, maplen, frag->size);
2279
2280 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2281 }
2282 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2283 }
2284 /* Make sure all the descriptors written */
2285 wmb();
2286 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2287 wmb();
2288
2289 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2290
2291 if (netif_msg_tx_queued(skge))
2292 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2293 dev->name, e - ring->start, skb->len);
2294
2295 ring->to_use = e->next;
2296 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2297 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2298 pr_debug("%s: transmit queue full\n", dev->name);
2299 netif_stop_queue(dev);
2300 }
2301
2302 dev->trans_start = jiffies;
2303 spin_unlock_irqrestore(&skge->tx_lock, flags);
2304
2305 return NETDEV_TX_OK;
2306 }
2307
2308 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2309 {
2310 /* This ring element can be skb or fragment */
2311 if (e->skb) {
2312 pci_unmap_single(hw->pdev,
2313 pci_unmap_addr(e, mapaddr),
2314 pci_unmap_len(e, maplen),
2315 PCI_DMA_TODEVICE);
2316 dev_kfree_skb_any(e->skb);
2317 e->skb = NULL;
2318 } else {
2319 pci_unmap_page(hw->pdev,
2320 pci_unmap_addr(e, mapaddr),
2321 pci_unmap_len(e, maplen),
2322 PCI_DMA_TODEVICE);
2323 }
2324 }
2325
2326 static void skge_tx_clean(struct skge_port *skge)
2327 {
2328 struct skge_ring *ring = &skge->tx_ring;
2329 struct skge_element *e;
2330 unsigned long flags;
2331
2332 spin_lock_irqsave(&skge->tx_lock, flags);
2333 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2334 ++skge->tx_avail;
2335 skge_tx_free(skge->hw, e);
2336 }
2337 ring->to_clean = e;
2338 spin_unlock_irqrestore(&skge->tx_lock, flags);
2339 }
2340
2341 static void skge_tx_timeout(struct net_device *dev)
2342 {
2343 struct skge_port *skge = netdev_priv(dev);
2344
2345 if (netif_msg_timer(skge))
2346 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2347
2348 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2349 skge_tx_clean(skge);
2350 }
2351
2352 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2353 {
2354 int err = 0;
2355 int running = netif_running(dev);
2356
2357 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2358 return -EINVAL;
2359
2360
2361 if (running)
2362 skge_down(dev);
2363 dev->mtu = new_mtu;
2364 if (running)
2365 skge_up(dev);
2366
2367 return err;
2368 }
2369
2370 static void genesis_set_multicast(struct net_device *dev)
2371 {
2372 struct skge_port *skge = netdev_priv(dev);
2373 struct skge_hw *hw = skge->hw;
2374 int port = skge->port;
2375 int i, count = dev->mc_count;
2376 struct dev_mc_list *list = dev->mc_list;
2377 u32 mode;
2378 u8 filter[8];
2379
2380 mode = xm_read32(hw, port, XM_MODE);
2381 mode |= XM_MD_ENA_HASH;
2382 if (dev->flags & IFF_PROMISC)
2383 mode |= XM_MD_ENA_PROM;
2384 else
2385 mode &= ~XM_MD_ENA_PROM;
2386
2387 if (dev->flags & IFF_ALLMULTI)
2388 memset(filter, 0xff, sizeof(filter));
2389 else {
2390 memset(filter, 0, sizeof(filter));
2391 for (i = 0; list && i < count; i++, list = list->next) {
2392 u32 crc, bit;
2393 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2394 bit = ~crc & 0x3f;
2395 filter[bit/8] |= 1 << (bit%8);
2396 }
2397 }
2398
2399 xm_write32(hw, port, XM_MODE, mode);
2400 xm_outhash(hw, port, XM_HSM, filter);
2401 }
2402
2403 static void yukon_set_multicast(struct net_device *dev)
2404 {
2405 struct skge_port *skge = netdev_priv(dev);
2406 struct skge_hw *hw = skge->hw;
2407 int port = skge->port;
2408 struct dev_mc_list *list = dev->mc_list;
2409 u16 reg;
2410 u8 filter[8];
2411
2412 memset(filter, 0, sizeof(filter));
2413
2414 reg = gma_read16(hw, port, GM_RX_CTRL);
2415 reg |= GM_RXCR_UCF_ENA;
2416
2417 if (dev->flags & IFF_PROMISC) /* promiscious */
2418 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2419 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2420 memset(filter, 0xff, sizeof(filter));
2421 else if (dev->mc_count == 0) /* no multicast */
2422 reg &= ~GM_RXCR_MCF_ENA;
2423 else {
2424 int i;
2425 reg |= GM_RXCR_MCF_ENA;
2426
2427 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2428 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2429 filter[bit/8] |= 1 << (bit%8);
2430 }
2431 }
2432
2433
2434 gma_write16(hw, port, GM_MC_ADDR_H1,
2435 (u16)filter[0] | ((u16)filter[1] << 8));
2436 gma_write16(hw, port, GM_MC_ADDR_H2,
2437 (u16)filter[2] | ((u16)filter[3] << 8));
2438 gma_write16(hw, port, GM_MC_ADDR_H3,
2439 (u16)filter[4] | ((u16)filter[5] << 8));
2440 gma_write16(hw, port, GM_MC_ADDR_H4,
2441 (u16)filter[6] | ((u16)filter[7] << 8));
2442
2443 gma_write16(hw, port, GM_RX_CTRL, reg);
2444 }
2445
2446 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2447 {
2448 if (hw->chip_id == CHIP_ID_GENESIS)
2449 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2450 else
2451 return (status & GMR_FS_ANY_ERR) ||
2452 (status & GMR_FS_RX_OK) == 0;
2453 }
2454
2455 static void skge_rx_error(struct skge_port *skge, int slot,
2456 u32 control, u32 status)
2457 {
2458 if (netif_msg_rx_err(skge))
2459 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2460 skge->netdev->name, slot, control, status);
2461
2462 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2463 skge->net_stats.rx_length_errors++;
2464 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2465 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2466 skge->net_stats.rx_length_errors++;
2467 if (status & XMR_FS_FRA_ERR)
2468 skge->net_stats.rx_frame_errors++;
2469 if (status & XMR_FS_FCS_ERR)
2470 skge->net_stats.rx_crc_errors++;
2471 } else {
2472 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2473 skge->net_stats.rx_length_errors++;
2474 if (status & GMR_FS_FRAGMENT)
2475 skge->net_stats.rx_frame_errors++;
2476 if (status & GMR_FS_CRC_ERR)
2477 skge->net_stats.rx_crc_errors++;
2478 }
2479 }
2480
2481 /* Get receive buffer from descriptor.
2482 * Handles copy of small buffers and reallocation failures
2483 */
2484 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2485 struct skge_element *e,
2486 unsigned int len)
2487 {
2488 struct sk_buff *nskb, *skb;
2489
2490 if (len < RX_COPY_THRESHOLD) {
2491 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2492 if (unlikely(!nskb))
2493 return NULL;
2494
2495 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2496 pci_unmap_addr(e, mapaddr),
2497 len, PCI_DMA_FROMDEVICE);
2498 memcpy(nskb->data, e->skb->data, len);
2499 pci_dma_sync_single_for_device(skge->hw->pdev,
2500 pci_unmap_addr(e, mapaddr),
2501 len, PCI_DMA_FROMDEVICE);
2502
2503 if (skge->rx_csum) {
2504 struct skge_rx_desc *rd = e->desc;
2505 nskb->csum = le16_to_cpu(rd->csum2);
2506 nskb->ip_summed = CHECKSUM_HW;
2507 }
2508 skge_rx_reuse(e, skge->rx_buf_size);
2509 return nskb;
2510 } else {
2511 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2512 if (unlikely(!nskb))
2513 return NULL;
2514
2515 pci_unmap_single(skge->hw->pdev,
2516 pci_unmap_addr(e, mapaddr),
2517 pci_unmap_len(e, maplen),
2518 PCI_DMA_FROMDEVICE);
2519 skb = e->skb;
2520 if (skge->rx_csum) {
2521 struct skge_rx_desc *rd = e->desc;
2522 skb->csum = le16_to_cpu(rd->csum2);
2523 skb->ip_summed = CHECKSUM_HW;
2524 }
2525
2526 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2527 return skb;
2528 }
2529 }
2530
2531
2532 static int skge_poll(struct net_device *dev, int *budget)
2533 {
2534 struct skge_port *skge = netdev_priv(dev);
2535 struct skge_hw *hw = skge->hw;
2536 struct skge_ring *ring = &skge->rx_ring;
2537 struct skge_element *e;
2538 unsigned int to_do = min(dev->quota, *budget);
2539 unsigned int work_done = 0;
2540
2541 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2542 struct skge_rx_desc *rd = e->desc;
2543 struct sk_buff *skb;
2544 u32 control, len, status;
2545
2546 rmb();
2547 control = rd->control;
2548 if (control & BMU_OWN)
2549 break;
2550
2551 len = control & BMU_BBC;
2552 status = rd->status;
2553
2554 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2555 || bad_phy_status(hw, status))) {
2556 skge_rx_error(skge, e - ring->start, control, status);
2557 skge_rx_reuse(e, skge->rx_buf_size);
2558 continue;
2559 }
2560
2561 if (netif_msg_rx_status(skge))
2562 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2563 dev->name, e - ring->start, rd->status, len);
2564
2565 skb = skge_rx_get(skge, e, len);
2566 if (likely(skb)) {
2567 skb_put(skb, len);
2568 skb->protocol = eth_type_trans(skb, dev);
2569
2570 dev->last_rx = jiffies;
2571 netif_receive_skb(skb);
2572
2573 ++work_done;
2574 } else
2575 skge_rx_reuse(e, skge->rx_buf_size);
2576 }
2577 ring->to_clean = e;
2578
2579 /* restart receiver */
2580 wmb();
2581 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2582 CSR_START | CSR_IRQ_CL_F);
2583
2584 *budget -= work_done;
2585 dev->quota -= work_done;
2586
2587 if (work_done >= to_do)
2588 return 1; /* not done */
2589
2590 local_irq_disable();
2591 __netif_rx_complete(dev);
2592 hw->intr_mask |= portirqmask[skge->port];
2593 skge_write32(hw, B0_IMSK, hw->intr_mask);
2594 local_irq_enable();
2595 return 0;
2596 }
2597
2598 static inline void skge_tx_intr(struct net_device *dev)
2599 {
2600 struct skge_port *skge = netdev_priv(dev);
2601 struct skge_hw *hw = skge->hw;
2602 struct skge_ring *ring = &skge->tx_ring;
2603 struct skge_element *e;
2604
2605 spin_lock(&skge->tx_lock);
2606 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2607 struct skge_tx_desc *td = e->desc;
2608 u32 control;
2609
2610 rmb();
2611 control = td->control;
2612 if (control & BMU_OWN)
2613 break;
2614
2615 if (unlikely(netif_msg_tx_done(skge)))
2616 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2617 dev->name, e - ring->start, td->status);
2618
2619 skge_tx_free(hw, e);
2620 e->skb = NULL;
2621 ++skge->tx_avail;
2622 }
2623 ring->to_clean = e;
2624 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2625
2626 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2627 netif_wake_queue(dev);
2628
2629 spin_unlock(&skge->tx_lock);
2630 }
2631
2632 /* Parity errors seem to happen when Genesis is connected to a switch
2633 * with no other ports present. Heartbeat error??
2634 */
2635 static void skge_mac_parity(struct skge_hw *hw, int port)
2636 {
2637 struct net_device *dev = hw->dev[port];
2638
2639 if (dev) {
2640 struct skge_port *skge = netdev_priv(dev);
2641 ++skge->net_stats.tx_heartbeat_errors;
2642 }
2643
2644 if (hw->chip_id == CHIP_ID_GENESIS)
2645 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2646 MFF_CLR_PERR);
2647 else
2648 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2649 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2650 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2651 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2652 }
2653
2654 static void skge_pci_clear(struct skge_hw *hw)
2655 {
2656 u16 status;
2657
2658 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2659 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2660 pci_write_config_word(hw->pdev, PCI_STATUS,
2661 status | PCI_STATUS_ERROR_BITS);
2662 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2663 }
2664
2665 static void skge_mac_intr(struct skge_hw *hw, int port)
2666 {
2667 if (hw->chip_id == CHIP_ID_GENESIS)
2668 genesis_mac_intr(hw, port);
2669 else
2670 yukon_mac_intr(hw, port);
2671 }
2672
2673 /* Handle device specific framing and timeout interrupts */
2674 static void skge_error_irq(struct skge_hw *hw)
2675 {
2676 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2677
2678 if (hw->chip_id == CHIP_ID_GENESIS) {
2679 /* clear xmac errors */
2680 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2681 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2682 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2683 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2684 } else {
2685 /* Timestamp (unused) overflow */
2686 if (hwstatus & IS_IRQ_TIST_OV)
2687 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2688 }
2689
2690 if (hwstatus & IS_RAM_RD_PAR) {
2691 printk(KERN_ERR PFX "Ram read data parity error\n");
2692 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2693 }
2694
2695 if (hwstatus & IS_RAM_WR_PAR) {
2696 printk(KERN_ERR PFX "Ram write data parity error\n");
2697 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2698 }
2699
2700 if (hwstatus & IS_M1_PAR_ERR)
2701 skge_mac_parity(hw, 0);
2702
2703 if (hwstatus & IS_M2_PAR_ERR)
2704 skge_mac_parity(hw, 1);
2705
2706 if (hwstatus & IS_R1_PAR_ERR)
2707 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2708
2709 if (hwstatus & IS_R2_PAR_ERR)
2710 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2711
2712 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2713 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2714 hwstatus);
2715
2716 skge_pci_clear(hw);
2717
2718 /* if error still set then just ignore it */
2719 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2720 if (hwstatus & IS_IRQ_STAT) {
2721 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2722 hwstatus);
2723 hw->intr_mask &= ~IS_HW_ERR;
2724 }
2725 }
2726 }
2727
2728 /*
2729 * Interrrupt from PHY are handled in tasklet (soft irq)
2730 * because accessing phy registers requires spin wait which might
2731 * cause excess interrupt latency.
2732 */
2733 static void skge_extirq(unsigned long data)
2734 {
2735 struct skge_hw *hw = (struct skge_hw *) data;
2736 int port;
2737
2738 spin_lock(&hw->phy_lock);
2739 for (port = 0; port < 2; port++) {
2740 struct net_device *dev = hw->dev[port];
2741
2742 if (dev && netif_running(dev)) {
2743 struct skge_port *skge = netdev_priv(dev);
2744
2745 if (hw->chip_id != CHIP_ID_GENESIS)
2746 yukon_phy_intr(skge);
2747 else
2748 bcom_phy_intr(skge);
2749 }
2750 }
2751 spin_unlock(&hw->phy_lock);
2752
2753 local_irq_disable();
2754 hw->intr_mask |= IS_EXT_REG;
2755 skge_write32(hw, B0_IMSK, hw->intr_mask);
2756 local_irq_enable();
2757 }
2758
2759 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2760 {
2761 struct skge_hw *hw = dev_id;
2762 u32 status = skge_read32(hw, B0_SP_ISRC);
2763
2764 if (status == 0 || status == ~0) /* hotplug or shared irq */
2765 return IRQ_NONE;
2766
2767 status &= hw->intr_mask;
2768 if (status & IS_R1_F) {
2769 hw->intr_mask &= ~IS_R1_F;
2770 netif_rx_schedule(hw->dev[0]);
2771 }
2772
2773 if (status & IS_R2_F) {
2774 hw->intr_mask &= ~IS_R2_F;
2775 netif_rx_schedule(hw->dev[1]);
2776 }
2777
2778 if (status & IS_XA1_F)
2779 skge_tx_intr(hw->dev[0]);
2780
2781 if (status & IS_XA2_F)
2782 skge_tx_intr(hw->dev[1]);
2783
2784 if (status & IS_PA_TO_RX1) {
2785 struct skge_port *skge = netdev_priv(hw->dev[0]);
2786 ++skge->net_stats.rx_over_errors;
2787 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2788 }
2789
2790 if (status & IS_PA_TO_RX2) {
2791 struct skge_port *skge = netdev_priv(hw->dev[1]);
2792 ++skge->net_stats.rx_over_errors;
2793 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2794 }
2795
2796 if (status & IS_PA_TO_TX1)
2797 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2798
2799 if (status & IS_PA_TO_TX2)
2800 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2801
2802 if (status & IS_MAC1)
2803 skge_mac_intr(hw, 0);
2804
2805 if (status & IS_MAC2)
2806 skge_mac_intr(hw, 1);
2807
2808 if (status & IS_HW_ERR)
2809 skge_error_irq(hw);
2810
2811 if (status & IS_EXT_REG) {
2812 hw->intr_mask &= ~IS_EXT_REG;
2813 tasklet_schedule(&hw->ext_tasklet);
2814 }
2815
2816 skge_write32(hw, B0_IMSK, hw->intr_mask);
2817
2818 return IRQ_HANDLED;
2819 }
2820
2821 #ifdef CONFIG_NET_POLL_CONTROLLER
2822 static void skge_netpoll(struct net_device *dev)
2823 {
2824 struct skge_port *skge = netdev_priv(dev);
2825
2826 disable_irq(dev->irq);
2827 skge_intr(dev->irq, skge->hw, NULL);
2828 enable_irq(dev->irq);
2829 }
2830 #endif
2831
2832 static int skge_set_mac_address(struct net_device *dev, void *p)
2833 {
2834 struct skge_port *skge = netdev_priv(dev);
2835 struct sockaddr *addr = p;
2836 int err = 0;
2837
2838 if (!is_valid_ether_addr(addr->sa_data))
2839 return -EADDRNOTAVAIL;
2840
2841 skge_down(dev);
2842 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2843 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2844 dev->dev_addr, ETH_ALEN);
2845 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2846 dev->dev_addr, ETH_ALEN);
2847 if (dev->flags & IFF_UP)
2848 err = skge_up(dev);
2849 return err;
2850 }
2851
2852 static const struct {
2853 u8 id;
2854 const char *name;
2855 } skge_chips[] = {
2856 { CHIP_ID_GENESIS, "Genesis" },
2857 { CHIP_ID_YUKON, "Yukon" },
2858 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2859 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2860 };
2861
2862 static const char *skge_board_name(const struct skge_hw *hw)
2863 {
2864 int i;
2865 static char buf[16];
2866
2867 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2868 if (skge_chips[i].id == hw->chip_id)
2869 return skge_chips[i].name;
2870
2871 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2872 return buf;
2873 }
2874
2875
2876 /*
2877 * Setup the board data structure, but don't bring up
2878 * the port(s)
2879 */
2880 static int skge_reset(struct skge_hw *hw)
2881 {
2882 u16 ctst;
2883 u8 t8, mac_cfg, pmd_type, phy_type;
2884 int i;
2885
2886 ctst = skge_read16(hw, B0_CTST);
2887
2888 /* do a SW reset */
2889 skge_write8(hw, B0_CTST, CS_RST_SET);
2890 skge_write8(hw, B0_CTST, CS_RST_CLR);
2891
2892 /* clear PCI errors, if any */
2893 skge_pci_clear(hw);
2894
2895 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2896
2897 /* restore CLK_RUN bits (for Yukon-Lite) */
2898 skge_write16(hw, B0_CTST,
2899 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2900
2901 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2902 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2903 pmd_type = skge_read8(hw, B2_PMD_TYP);
2904 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2905
2906 switch (hw->chip_id) {
2907 case CHIP_ID_GENESIS:
2908 switch (phy_type) {
2909 case SK_PHY_BCOM:
2910 hw->phy_addr = PHY_ADDR_BCOM;
2911 break;
2912 default:
2913 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2914 pci_name(hw->pdev), phy_type);
2915 return -EOPNOTSUPP;
2916 }
2917 break;
2918
2919 case CHIP_ID_YUKON:
2920 case CHIP_ID_YUKON_LITE:
2921 case CHIP_ID_YUKON_LP:
2922 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2923 hw->copper = 1;
2924
2925 hw->phy_addr = PHY_ADDR_MARV;
2926 break;
2927
2928 default:
2929 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2930 pci_name(hw->pdev), hw->chip_id);
2931 return -EOPNOTSUPP;
2932 }
2933
2934 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2935 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2936 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2937
2938 /* read the adapters RAM size */
2939 t8 = skge_read8(hw, B2_E_0);
2940 if (hw->chip_id == CHIP_ID_GENESIS) {
2941 if (t8 == 3) {
2942 /* special case: 4 x 64k x 36, offset = 0x80000 */
2943 hw->ram_size = 0x100000;
2944 hw->ram_offset = 0x80000;
2945 } else
2946 hw->ram_size = t8 * 512;
2947 }
2948 else if (t8 == 0)
2949 hw->ram_size = 0x20000;
2950 else
2951 hw->ram_size = t8 * 4096;
2952
2953 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2954 if (hw->chip_id == CHIP_ID_GENESIS)
2955 genesis_init(hw);
2956 else {
2957 /* switch power to VCC (WA for VAUX problem) */
2958 skge_write8(hw, B0_POWER_CTRL,
2959 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2960 /* avoid boards with stuck Hardware error bits */
2961 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2962 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2963 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2964 hw->intr_mask &= ~IS_HW_ERR;
2965 }
2966
2967 for (i = 0; i < hw->ports; i++) {
2968 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2969 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2970 }
2971 }
2972
2973 /* turn off hardware timer (unused) */
2974 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2975 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2976 skge_write8(hw, B0_LED, LED_STAT_ON);
2977
2978 /* enable the Tx Arbiters */
2979 for (i = 0; i < hw->ports; i++)
2980 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2981
2982 /* Initialize ram interface */
2983 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2984
2985 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2986 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2987 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2988 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2989 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2990 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2991 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2992 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2993 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2994 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2995 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2996 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2997
2998 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2999
3000 /* Set interrupt moderation for Transmit only
3001 * Receive interrupts avoided by NAPI
3002 */
3003 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3004 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3005 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3006
3007 skge_write32(hw, B0_IMSK, hw->intr_mask);
3008
3009 spin_lock_bh(&hw->phy_lock);
3010 for (i = 0; i < hw->ports; i++) {
3011 if (hw->chip_id == CHIP_ID_GENESIS)
3012 genesis_reset(hw, i);
3013 else
3014 yukon_reset(hw, i);
3015 }
3016 spin_unlock_bh(&hw->phy_lock);
3017
3018 return 0;
3019 }
3020
3021 /* Initialize network device */
3022 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3023 int highmem)
3024 {
3025 struct skge_port *skge;
3026 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3027
3028 if (!dev) {
3029 printk(KERN_ERR "skge etherdev alloc failed");
3030 return NULL;
3031 }
3032
3033 SET_MODULE_OWNER(dev);
3034 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3035 dev->open = skge_up;
3036 dev->stop = skge_down;
3037 dev->hard_start_xmit = skge_xmit_frame;
3038 dev->get_stats = skge_get_stats;
3039 if (hw->chip_id == CHIP_ID_GENESIS)
3040 dev->set_multicast_list = genesis_set_multicast;
3041 else
3042 dev->set_multicast_list = yukon_set_multicast;
3043
3044 dev->set_mac_address = skge_set_mac_address;
3045 dev->change_mtu = skge_change_mtu;
3046 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3047 dev->tx_timeout = skge_tx_timeout;
3048 dev->watchdog_timeo = TX_WATCHDOG;
3049 dev->poll = skge_poll;
3050 dev->weight = NAPI_WEIGHT;
3051 #ifdef CONFIG_NET_POLL_CONTROLLER
3052 dev->poll_controller = skge_netpoll;
3053 #endif
3054 dev->irq = hw->pdev->irq;
3055 dev->features = NETIF_F_LLTX;
3056 if (highmem)
3057 dev->features |= NETIF_F_HIGHDMA;
3058
3059 skge = netdev_priv(dev);
3060 skge->netdev = dev;
3061 skge->hw = hw;
3062 skge->msg_enable = netif_msg_init(debug, default_msg);
3063 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3064 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3065
3066 /* Auto speed and flow control */
3067 skge->autoneg = AUTONEG_ENABLE;
3068 skge->flow_control = FLOW_MODE_SYMMETRIC;
3069 skge->duplex = -1;
3070 skge->speed = -1;
3071 skge->advertising = skge_supported_modes(hw);
3072
3073 hw->dev[port] = dev;
3074
3075 skge->port = port;
3076
3077 spin_lock_init(&skge->tx_lock);
3078
3079 if (hw->chip_id != CHIP_ID_GENESIS) {
3080 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3081 skge->rx_csum = 1;
3082 }
3083
3084 /* read the mac address */
3085 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3086 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3087
3088 /* device is off until link detection */
3089 netif_carrier_off(dev);
3090 netif_stop_queue(dev);
3091
3092 return dev;
3093 }
3094
3095 static void __devinit skge_show_addr(struct net_device *dev)
3096 {
3097 const struct skge_port *skge = netdev_priv(dev);
3098
3099 if (netif_msg_probe(skge))
3100 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3101 dev->name,
3102 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3103 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3104 }
3105
3106 static int __devinit skge_probe(struct pci_dev *pdev,
3107 const struct pci_device_id *ent)
3108 {
3109 struct net_device *dev, *dev1;
3110 struct skge_hw *hw;
3111 int err, using_dac = 0;
3112
3113 if ((err = pci_enable_device(pdev))) {
3114 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3115 pci_name(pdev));
3116 goto err_out;
3117 }
3118
3119 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3120 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3121 pci_name(pdev));
3122 goto err_out_disable_pdev;
3123 }
3124
3125 pci_set_master(pdev);
3126
3127 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3128 using_dac = 1;
3129 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3130 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3131 pci_name(pdev));
3132 goto err_out_free_regions;
3133 }
3134
3135 #ifdef __BIG_ENDIAN
3136 /* byte swap decriptors in hardware */
3137 {
3138 u32 reg;
3139
3140 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3141 reg |= PCI_REV_DESC;
3142 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3143 }
3144 #endif
3145
3146 err = -ENOMEM;
3147 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3148 if (!hw) {
3149 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3150 pci_name(pdev));
3151 goto err_out_free_regions;
3152 }
3153
3154 memset(hw, 0, sizeof(*hw));
3155 hw->pdev = pdev;
3156 spin_lock_init(&hw->phy_lock);
3157 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3158
3159 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3160 if (!hw->regs) {
3161 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3162 pci_name(pdev));
3163 goto err_out_free_hw;
3164 }
3165
3166 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3167 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3168 pci_name(pdev), pdev->irq);
3169 goto err_out_iounmap;
3170 }
3171 pci_set_drvdata(pdev, hw);
3172
3173 err = skge_reset(hw);
3174 if (err)
3175 goto err_out_free_irq;
3176
3177 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3178 pci_resource_start(pdev, 0), pdev->irq,
3179 skge_board_name(hw), hw->chip_rev);
3180
3181 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3182 goto err_out_led_off;
3183
3184 if ((err = register_netdev(dev))) {
3185 printk(KERN_ERR PFX "%s: cannot register net device\n",
3186 pci_name(pdev));
3187 goto err_out_free_netdev;
3188 }
3189
3190 skge_show_addr(dev);
3191
3192 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3193 if (register_netdev(dev1) == 0)
3194 skge_show_addr(dev1);
3195 else {
3196 /* Failure to register second port need not be fatal */
3197 printk(KERN_WARNING PFX "register of second port failed\n");
3198 hw->dev[1] = NULL;
3199 free_netdev(dev1);
3200 }
3201 }
3202
3203 return 0;
3204
3205 err_out_free_netdev:
3206 free_netdev(dev);
3207 err_out_led_off:
3208 skge_write16(hw, B0_LED, LED_STAT_OFF);
3209 err_out_free_irq:
3210 free_irq(pdev->irq, hw);
3211 err_out_iounmap:
3212 iounmap(hw->regs);
3213 err_out_free_hw:
3214 kfree(hw);
3215 err_out_free_regions:
3216 pci_release_regions(pdev);
3217 err_out_disable_pdev:
3218 pci_disable_device(pdev);
3219 pci_set_drvdata(pdev, NULL);
3220 err_out:
3221 return err;
3222 }
3223
3224 static void __devexit skge_remove(struct pci_dev *pdev)
3225 {
3226 struct skge_hw *hw = pci_get_drvdata(pdev);
3227 struct net_device *dev0, *dev1;
3228
3229 if (!hw)
3230 return;
3231
3232 if ((dev1 = hw->dev[1]))
3233 unregister_netdev(dev1);
3234 dev0 = hw->dev[0];
3235 unregister_netdev(dev0);
3236
3237 skge_write32(hw, B0_IMSK, 0);
3238 skge_write16(hw, B0_LED, LED_STAT_OFF);
3239 skge_pci_clear(hw);
3240 skge_write8(hw, B0_CTST, CS_RST_SET);
3241
3242 tasklet_kill(&hw->ext_tasklet);
3243
3244 free_irq(pdev->irq, hw);
3245 pci_release_regions(pdev);
3246 pci_disable_device(pdev);
3247 if (dev1)
3248 free_netdev(dev1);
3249 free_netdev(dev0);
3250
3251 iounmap(hw->regs);
3252 kfree(hw);
3253 pci_set_drvdata(pdev, NULL);
3254 }
3255
3256 #ifdef CONFIG_PM
3257 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3258 {
3259 struct skge_hw *hw = pci_get_drvdata(pdev);
3260 int i, wol = 0;
3261
3262 for (i = 0; i < 2; i++) {
3263 struct net_device *dev = hw->dev[i];
3264
3265 if (dev) {
3266 struct skge_port *skge = netdev_priv(dev);
3267 if (netif_running(dev)) {
3268 netif_carrier_off(dev);
3269 if (skge->wol)
3270 netif_stop_queue(dev);
3271 else
3272 skge_down(dev);
3273 }
3274 netif_device_detach(dev);
3275 wol |= skge->wol;
3276 }
3277 }
3278
3279 pci_save_state(pdev);
3280 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3281 pci_disable_device(pdev);
3282 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3283
3284 return 0;
3285 }
3286
3287 static int skge_resume(struct pci_dev *pdev)
3288 {
3289 struct skge_hw *hw = pci_get_drvdata(pdev);
3290 int i;
3291
3292 pci_set_power_state(pdev, PCI_D0);
3293 pci_restore_state(pdev);
3294 pci_enable_wake(pdev, PCI_D0, 0);
3295
3296 skge_reset(hw);
3297
3298 for (i = 0; i < 2; i++) {
3299 struct net_device *dev = hw->dev[i];
3300 if (dev) {
3301 netif_device_attach(dev);
3302 if (netif_running(dev))
3303 skge_up(dev);
3304 }
3305 }
3306 return 0;
3307 }
3308 #endif
3309
3310 static struct pci_driver skge_driver = {
3311 .name = DRV_NAME,
3312 .id_table = skge_id_table,
3313 .probe = skge_probe,
3314 .remove = __devexit_p(skge_remove),
3315 #ifdef CONFIG_PM
3316 .suspend = skge_suspend,
3317 .resume = skge_resume,
3318 #endif
3319 };
3320
3321 static int __init skge_init_module(void)
3322 {
3323 return pci_module_init(&skge_driver);
3324 }
3325
3326 static void __exit skge_cleanup_module(void)
3327 {
3328 pci_unregister_driver(&skge_driver);
3329 }
3330
3331 module_init(skge_init_module);
3332 module_exit(skge_cleanup_module);