drivers/net/sfc/qt202x_phy.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2006-2009 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9 /*
  10  * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
  11  */
  12
  13 #include <linux/timer.h>
  14 #include <linux/delay.h>
  15 #include "efx.h"
  16 #include "mdio_10g.h"
  17 #include "phy.h"
  18 #include "nic.h"
  19
  20 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS |           \
  21                               MDIO_DEVS_PMAPMD |        \
  22                               MDIO_DEVS_PHYXS)
  23
  24 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) |         \
  25                           (1 << LOOPBACK_PMAPMD) |      \
  26                           (1 << LOOPBACK_PHYXS_WS))
  27
  28 /****************************************************************************/
  29 /* Quake-specific MDIO registers */
  30 #define MDIO_QUAKE_LED0_REG     (0xD006)
  31
  32 /* QT2025C only */
  33 #define PCS_FW_HEARTBEAT_REG    0xd7ee
  34 #define PCS_FW_HEARTB_LBN       0
  35 #define PCS_FW_HEARTB_WIDTH     8
  36 #define PCS_FW_PRODUCT_CODE_1   0xd7f0
  37 #define PCS_FW_VERSION_1        0xd7f3
  38 #define PCS_FW_BUILD_1          0xd7f6
  39 #define PCS_UC8051_STATUS_REG   0xd7fd
  40 #define PCS_UC_STATUS_LBN       0
  41 #define PCS_UC_STATUS_WIDTH     8
  42 #define PCS_UC_STATUS_FW_SAVE   0x20
  43 #define PMA_PMD_FTX_CTRL2_REG   0xc309
  44 #define PMA_PMD_FTX_STATIC_LBN  13
  45 #define PMA_PMD_VEND1_REG       0xc001
  46 #define PMA_PMD_VEND1_LBTXD_LBN 15
  47 #define PCS_VEND1_REG           0xc000
  48 #define PCS_VEND1_LBTXD_LBN     5
  49
  50 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
  51 {
  52         int addr = MDIO_QUAKE_LED0_REG + led;
  53         efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
  54 }
  55
  56 struct qt202x_phy_data {
  57         enum efx_phy_mode phy_mode;
  58         bool bug17190_in_bad_state;
  59         unsigned long bug17190_timer;
  60         u32 firmware_ver;
  61 };
  62
  63 #define QT2022C2_MAX_RESET_TIME 500
  64 #define QT2022C2_RESET_WAIT 10
  65
  66 #define QT2025C_MAX_HEARTB_TIME (5 * HZ)
  67 #define QT2025C_HEARTB_WAIT 100
  68 #define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
  69 #define QT2025C_FWSTART_WAIT 100
  70
  71 #define BUG17190_INTERVAL (2 * HZ)
  72
  73 static int qt2025c_wait_heartbeat(struct efx_nic *efx)
  74 {
  75         unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
  76         int reg, old_counter = 0;
  77
  78         /* Wait for firmware heartbeat to start */
  79         for (;;) {
  80                 int counter;
  81                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
  82                 if (reg < 0)
  83                         return reg;
  84                 counter = ((reg >> PCS_FW_HEARTB_LBN) &
  85                             ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  86                 if (old_counter == 0)
  87                         old_counter = counter;
  88                 else if (counter != old_counter)
  89                         break;
  90                 if (time_after(jiffies, timeout)) {
  91                         /* Some cables have EEPROMs that conflict with the
  92                          * PHY's on-board EEPROM so it cannot load firmware */
  93                         EFX_ERR(efx, "If an SFP+ direct attach cable is"
  94                                 " connected, please check that it complies"
  95                                 " with the SFP+ specification\n");
  96                         return -ETIMEDOUT;
  97                 }
  98                 msleep(QT2025C_HEARTB_WAIT);
  99         }
 100
 101         return 0;
 102 }
 103
 104 static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
 105 {
 106         unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
 107         int reg;
 108
 109         /* Wait for firmware status to look good */
 110         for (;;) {
 111                 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
 112                 if (reg < 0)
 113                         return reg;
 114                 if ((reg &
 115                      ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
 116                     PCS_UC_STATUS_FW_SAVE)
 117                         break;
 118                 if (time_after(jiffies, timeout))
 119                         return -ETIMEDOUT;
 120                 msleep(QT2025C_FWSTART_WAIT);
 121         }
 122
 123         return 0;
 124 }
 125
 126 static void qt2025c_restart_firmware(struct efx_nic *efx)
 127 {
 128         /* Restart microcontroller execution of firmware from RAM */
 129         efx_mdio_write(efx, 3, 0xe854, 0x00c0);
 130         efx_mdio_write(efx, 3, 0xe854, 0x0040);
 131         msleep(50);
 132 }
 133
 134 static int qt2025c_wait_reset(struct efx_nic *efx)
 135 {
 136         int rc;
 137
 138         rc = qt2025c_wait_heartbeat(efx);
 139         if (rc != 0)
 140                 return rc;
 141
 142         rc = qt2025c_wait_fw_status_good(efx);
 143         if (rc == -ETIMEDOUT) {
 144                 /* Bug 17689: occasionally heartbeat starts but firmware status
 145                  * code never progresses beyond 0x00.  Try again, once, after
 146                  * restarting execution of the firmware image. */
 147                 EFX_LOG(efx, "bashing QT2025C microcontroller\n");
 148                 qt2025c_restart_firmware(efx);
 149                 rc = qt2025c_wait_heartbeat(efx);
 150                 if (rc != 0)
 151                         return rc;
 152                 rc = qt2025c_wait_fw_status_good(efx);
 153         }
 154
 155         return rc;
 156 }
 157
 158 static void qt2025c_firmware_id(struct efx_nic *efx)
 159 {
 160         struct qt202x_phy_data *phy_data = efx->phy_data;
 161         u8 firmware_id[9];
 162         size_t i;
 163
 164         for (i = 0; i < sizeof(firmware_id); i++)
 165                 firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
 166                                                PCS_FW_PRODUCT_CODE_1 + i);
 167         EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
 168                  (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
 169                  firmware_id[3] >> 4, firmware_id[3] & 0xf,
 170                  firmware_id[4], firmware_id[5],
 171                  firmware_id[6], firmware_id[7], firmware_id[8]);
 172         phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
 173                                  ((firmware_id[3] & 0x0f) << 16) |
 174                                  (firmware_id[4] << 8) | firmware_id[5];
 175 }
 176
 177 static void qt2025c_bug17190_workaround(struct efx_nic *efx)
 178 {
 179         struct qt202x_phy_data *phy_data = efx->phy_data;
 180
 181         /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
 182          * layers up, but PCS down (no block_lock).  If we notice this state
 183          * persisting for a couple of seconds, we switch PMA/PMD loopback
 184          * briefly on and then off again, which is normally sufficient to
 185          * recover it.
 186          */
 187         if (efx->link_state.up ||
 188             !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
 189                 phy_data->bug17190_in_bad_state = false;
 190                 return;
 191         }
 192
 193         if (!phy_data->bug17190_in_bad_state) {
 194                 phy_data->bug17190_in_bad_state = true;
 195                 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
 196                 return;
 197         }
 198
 199         if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
 200                 EFX_LOG(efx, "bashing QT2025C PMA/PMD\n");
 201                 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
 202                                   MDIO_PMA_CTRL1_LOOPBACK, true);
 203                 msleep(100);
 204                 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
 205                                   MDIO_PMA_CTRL1_LOOPBACK, false);
 206                 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
 207         }
 208 }
 209
 210 static int qt2025c_select_phy_mode(struct efx_nic *efx)
 211 {
 212         struct qt202x_phy_data *phy_data = efx->phy_data;
 213         struct falcon_board *board = falcon_board(efx);
 214         int reg, rc, i;
 215         uint16_t phy_op_mode;
 216
 217         /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
 218          * Self-Configure mode.  Don't attempt any switching if we encounter
 219          * older firmware. */
 220         if (phy_data->firmware_ver < 0x02000100)
 221                 return 0;
 222
 223         /* In general we will get optimal behaviour in "SFP+ Self-Configure"
 224          * mode; however, that powers down most of the PHY when no module is
 225          * present, so we must use a different mode (any fixed mode will do)
 226          * to be sure that loopbacks will work. */
 227         phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
 228
 229         /* Only change mode if really necessary */
 230         reg = efx_mdio_read(efx, 1, 0xc319);
 231         if ((reg & 0x0038) == phy_op_mode)
 232                 return 0;
 233         EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode);
 234
 235         /* This sequence replicates the register writes configured in the boot
 236          * EEPROM (including the differences between board revisions), except
 237          * that the operating mode is changed, and the PHY is prevented from
 238          * unnecessarily reloading the main firmware image again. */
 239         efx_mdio_write(efx, 1, 0xc300, 0x0000);
 240         /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
 241          * STOPs onto the firmware/module I2C bus to reset it, varies across
 242          * board revisions, as the bus is connected to different GPIO/LED
 243          * outputs on the PHY.) */
 244         if (board->major == 0 && board->minor < 2) {
 245                 efx_mdio_write(efx, 1, 0xc303, 0x4498);
 246                 for (i = 0; i < 9; i++) {
 247                         efx_mdio_write(efx, 1, 0xc303, 0x4488);
 248                         efx_mdio_write(efx, 1, 0xc303, 0x4480);
 249                         efx_mdio_write(efx, 1, 0xc303, 0x4490);
 250                         efx_mdio_write(efx, 1, 0xc303, 0x4498);
 251                 }
 252         } else {
 253                 efx_mdio_write(efx, 1, 0xc303, 0x0920);
 254                 efx_mdio_write(efx, 1, 0xd008, 0x0004);
 255                 for (i = 0; i < 9; i++) {
 256                         efx_mdio_write(efx, 1, 0xc303, 0x0900);
 257                         efx_mdio_write(efx, 1, 0xd008, 0x0005);
 258                         efx_mdio_write(efx, 1, 0xc303, 0x0920);
 259                         efx_mdio_write(efx, 1, 0xd008, 0x0004);
 260                 }
 261                 efx_mdio_write(efx, 1, 0xc303, 0x4900);
 262         }
 263         efx_mdio_write(efx, 1, 0xc303, 0x4900);
 264         efx_mdio_write(efx, 1, 0xc302, 0x0004);
 265         efx_mdio_write(efx, 1, 0xc316, 0x0013);
 266         efx_mdio_write(efx, 1, 0xc318, 0x0054);
 267         efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
 268         efx_mdio_write(efx, 1, 0xc31a, 0x0098);
 269         efx_mdio_write(efx, 3, 0x0026, 0x0e00);
 270         efx_mdio_write(efx, 3, 0x0027, 0x0013);
 271         efx_mdio_write(efx, 3, 0x0028, 0xa528);
 272         efx_mdio_write(efx, 1, 0xd006, 0x000a);
 273         efx_mdio_write(efx, 1, 0xd007, 0x0009);
 274         efx_mdio_write(efx, 1, 0xd008, 0x0004);
 275         /* This additional write is not present in the boot EEPROM.  It
 276          * prevents the PHY's internal boot ROM doing another pointless (and
 277          * slow) reload of the firmware image (the microcontroller's code
 278          * memory is not affected by the microcontroller reset). */
 279         efx_mdio_write(efx, 1, 0xc317, 0x00ff);
 280         efx_mdio_write(efx, 1, 0xc300, 0x0002);
 281         msleep(20);
 282
 283         /* Restart microcontroller execution of firmware from RAM */
 284         qt2025c_restart_firmware(efx);
 285
 286         /* Wait for the microcontroller to be ready again */
 287         rc = qt2025c_wait_reset(efx);
 288         if (rc < 0) {
 289                 EFX_ERR(efx, "PHY microcontroller reset during mode switch "
 290                                 "timed out\n");
 291                 return rc;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int qt202x_reset_phy(struct efx_nic *efx)
 298 {
 299         int rc;
 300
 301         if (efx->phy_type == PHY_TYPE_QT2025C) {
 302                 /* Wait for the reset triggered by falcon_reset_hw()
 303                  * to complete */
 304                 rc = qt2025c_wait_reset(efx);
 305                 if (rc < 0)
 306                         goto fail;
 307         } else {
 308                 /* Reset the PHYXS MMD. This is documented as doing
 309                  * a complete soft reset. */
 310                 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
 311                                         QT2022C2_MAX_RESET_TIME /
 312                                         QT2022C2_RESET_WAIT,
 313                                         QT2022C2_RESET_WAIT);
 314                 if (rc < 0)
 315                         goto fail;
 316         }
 317
 318         /* Wait 250ms for the PHY to complete bootup */
 319         msleep(250);
 320
 321         falcon_board(efx)->type->init_phy(efx);
 322
 323         return 0;
 324
 325  fail:
 326         EFX_ERR(efx, "PHY reset timed out\n");
 327         return rc;
 328 }
 329
 330 static int qt202x_phy_probe(struct efx_nic *efx)
 331 {
 332         struct qt202x_phy_data *phy_data;
 333
 334         phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
 335         if (!phy_data)
 336                 return -ENOMEM;
 337         efx->phy_data = phy_data;
 338         phy_data->phy_mode = efx->phy_mode;
 339         phy_data->bug17190_in_bad_state = false;
 340         phy_data->bug17190_timer = 0;
 341
 342         efx->mdio.mmds = QT202X_REQUIRED_DEVS;
 343         efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
 344         efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
 345         return 0;
 346 }
 347
 348 static int qt202x_phy_init(struct efx_nic *efx)
 349 {
 350         u32 devid;
 351         int rc;
 352
 353         rc = qt202x_reset_phy(efx);
 354         if (rc) {
 355                 EFX_ERR(efx, "PHY init failed\n");
 356                 return rc;
 357         }
 358
 359         devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
 360         EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
 361                  devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
 362                  efx_mdio_id_rev(devid));
 363
 364         if (efx->phy_type == PHY_TYPE_QT2025C)
 365                 qt2025c_firmware_id(efx);
 366
 367         return 0;
 368 }
 369
 370 static int qt202x_link_ok(struct efx_nic *efx)
 371 {
 372         return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
 373 }
 374
 375 static bool qt202x_phy_poll(struct efx_nic *efx)
 376 {
 377         bool was_up = efx->link_state.up;
 378
 379         efx->link_state.up = qt202x_link_ok(efx);
 380         efx->link_state.speed = 10000;
 381         efx->link_state.fd = true;
 382         efx->link_state.fc = efx->wanted_fc;
 383
 384         if (efx->phy_type == PHY_TYPE_QT2025C)
 385                 qt2025c_bug17190_workaround(efx);
 386
 387         return efx->link_state.up != was_up;
 388 }
 389
 390 static int qt202x_phy_reconfigure(struct efx_nic *efx)
 391 {
 392         struct qt202x_phy_data *phy_data = efx->phy_data;
 393
 394         if (efx->phy_type == PHY_TYPE_QT2025C) {
 395                 int rc = qt2025c_select_phy_mode(efx);
 396                 if (rc)
 397                         return rc;
 398
 399                 /* There are several different register bits which can
 400                  * disable TX (and save power) on direct-attach cables
 401                  * or optical transceivers, varying somewhat between
 402                  * firmware versions.  Only 'static mode' appears to
 403                  * cover everything. */
 404                 mdio_set_flag(
 405                         &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
 406                         PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
 407                         efx->phy_mode & PHY_MODE_TX_DISABLED ||
 408                         efx->phy_mode & PHY_MODE_LOW_POWER ||
 409                         efx->loopback_mode == LOOPBACK_PCS ||
 410                         efx->loopback_mode == LOOPBACK_PMAPMD);
 411         } else {
 412                 /* Reset the PHY when moving from tx off to tx on */
 413                 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
 414                     (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
 415                         qt202x_reset_phy(efx);
 416
 417                 efx_mdio_transmit_disable(efx);
 418         }
 419
 420         efx_mdio_phy_reconfigure(efx);
 421
 422         phy_data->phy_mode = efx->phy_mode;
 423
 424         return 0;
 425 }
 426
 427 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
 428 {
 429         mdio45_ethtool_gset(&efx->mdio, ecmd);
 430 }
 431
 432 static void qt202x_phy_remove(struct efx_nic *efx)
 433 {
 434         /* Free the context block */
 435         kfree(efx->phy_data);
 436         efx->phy_data = NULL;
 437 }
 438
 439 struct efx_phy_operations falcon_qt202x_phy_ops = {
 440         .probe           = qt202x_phy_probe,
 441         .init            = qt202x_phy_init,
 442         .reconfigure     = qt202x_phy_reconfigure,
 443         .poll            = qt202x_phy_poll,
 444         .fini            = efx_port_dummy_op_void,
 445         .remove          = qt202x_phy_remove,
 446         .get_settings    = qt202x_phy_get_settings,
 447         .set_settings    = efx_mdio_set_settings,
 448 };