1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2005 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 ************************************************************************/
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/errno.h>
50 #include <linux/ioport.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/kernel.h>
54 #include <linux/netdevice.h>
55 #include <linux/etherdevice.h>
56 #include <linux/skbuff.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/stddef.h>
60 #include <linux/ioctl.h>
61 #include <linux/timex.h>
62 #include <linux/ethtool.h>
63 #include <linux/workqueue.h>
64 #include <linux/if_vlan.h>
66 #include <linux/tcp.h>
69 #include <asm/system.h>
70 #include <asm/uaccess.h>
72 #include <asm/div64.h>
77 #include "s2io-regs.h"
79 #define DRV_VERSION "2.0.16.1"
81 /* S2io Driver name & version. */
82 static char s2io_driver_name
[] = "Neterion";
83 static char s2io_driver_version
[] = DRV_VERSION
;
85 static int rxd_size
[4] = {32,48,48,64};
86 static int rxd_count
[4] = {127,85,85,63};
88 static inline int RXD_IS_UP2DT(struct RxD_t
*rxdp
)
92 ret
= ((!(rxdp
->Control_1
& RXD_OWN_XENA
)) &&
93 (GET_RXD_MARKER(rxdp
->Control_2
) != THE_RXD_MARK
));
99 * Cards with following subsystem_id have a link state indication
100 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
101 * macro below identifies these cards given the subsystem_id.
103 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
104 (dev_type == XFRAME_I_DEVICE) ? \
105 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
106 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
108 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
109 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
110 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
113 static inline int rx_buffer_level(struct s2io_nic
* sp
, int rxb_size
, int ring
)
115 struct mac_info
*mac_control
;
117 mac_control
= &sp
->mac_control
;
118 if (rxb_size
<= rxd_count
[sp
->rxd_mode
])
120 else if ((mac_control
->rings
[ring
].pkt_cnt
- rxb_size
) > 16)
125 /* Ethtool related variables and Macros. */
126 static char s2io_gstrings
[][ETH_GSTRING_LEN
] = {
127 "Register test\t(offline)",
128 "Eeprom test\t(offline)",
129 "Link test\t(online)",
130 "RLDRAM test\t(offline)",
131 "BIST Test\t(offline)"
134 static char ethtool_stats_keys
[][ETH_GSTRING_LEN
] = {
136 {"tmac_data_octets"},
140 {"tmac_pause_ctrl_frms"},
144 {"tmac_any_err_frms"},
145 {"tmac_ttl_less_fb_octets"},
146 {"tmac_vld_ip_octets"},
154 {"rmac_data_octets"},
155 {"rmac_fcs_err_frms"},
157 {"rmac_vld_mcst_frms"},
158 {"rmac_vld_bcst_frms"},
159 {"rmac_in_rng_len_err_frms"},
160 {"rmac_out_rng_len_err_frms"},
162 {"rmac_pause_ctrl_frms"},
163 {"rmac_unsup_ctrl_frms"},
165 {"rmac_accepted_ucst_frms"},
166 {"rmac_accepted_nucst_frms"},
167 {"rmac_discarded_frms"},
168 {"rmac_drop_events"},
169 {"rmac_ttl_less_fb_octets"},
171 {"rmac_usized_frms"},
172 {"rmac_osized_frms"},
174 {"rmac_jabber_frms"},
175 {"rmac_ttl_64_frms"},
176 {"rmac_ttl_65_127_frms"},
177 {"rmac_ttl_128_255_frms"},
178 {"rmac_ttl_256_511_frms"},
179 {"rmac_ttl_512_1023_frms"},
180 {"rmac_ttl_1024_1518_frms"},
188 {"rmac_err_drp_udp"},
189 {"rmac_xgmii_err_sym"},
207 {"rmac_xgmii_data_err_cnt"},
208 {"rmac_xgmii_ctrl_err_cnt"},
209 {"rmac_accepted_ip"},
213 {"new_rd_req_rtry_cnt"},
215 {"wr_rtry_rd_ack_cnt"},
218 {"new_wr_req_rtry_cnt"},
221 {"rd_rtry_wr_ack_cnt"},
229 {"rmac_ttl_1519_4095_frms"},
230 {"rmac_ttl_4096_8191_frms"},
231 {"rmac_ttl_8192_max_frms"},
232 {"rmac_ttl_gt_max_frms"},
233 {"rmac_osized_alt_frms"},
234 {"rmac_jabber_alt_frms"},
235 {"rmac_gt_max_alt_frms"},
237 {"rmac_len_discard"},
238 {"rmac_fcs_discard"},
241 {"rmac_red_discard"},
242 {"rmac_rts_discard"},
243 {"rmac_ingm_full_discard"},
245 {"\n DRIVER STATISTICS"},
246 {"single_bit_ecc_errs"},
247 {"double_bit_ecc_errs"},
253 ("alarm_transceiver_temp_high"),
254 ("alarm_transceiver_temp_low"),
255 ("alarm_laser_bias_current_high"),
256 ("alarm_laser_bias_current_low"),
257 ("alarm_laser_output_power_high"),
258 ("alarm_laser_output_power_low"),
259 ("warn_transceiver_temp_high"),
260 ("warn_transceiver_temp_low"),
261 ("warn_laser_bias_current_high"),
262 ("warn_laser_bias_current_low"),
263 ("warn_laser_output_power_high"),
264 ("warn_laser_output_power_low"),
265 ("lro_aggregated_pkts"),
266 ("lro_flush_both_count"),
267 ("lro_out_of_sequence_pkts"),
268 ("lro_flush_due_to_max_pkts"),
269 ("lro_avg_aggr_pkts"),
272 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
273 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275 #define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
276 #define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
278 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
279 init_timer(&timer); \
280 timer.function = handle; \
281 timer.data = (unsigned long) arg; \
282 mod_timer(&timer, (jiffies + exp)) \
285 static void s2io_vlan_rx_register(struct net_device
*dev
,
286 struct vlan_group
*grp
)
288 struct s2io_nic
*nic
= dev
->priv
;
291 spin_lock_irqsave(&nic
->tx_lock
, flags
);
293 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
296 /* Unregister the vlan */
297 static void s2io_vlan_rx_kill_vid(struct net_device
*dev
, unsigned long vid
)
299 struct s2io_nic
*nic
= dev
->priv
;
302 spin_lock_irqsave(&nic
->tx_lock
, flags
);
304 nic
->vlgrp
->vlan_devices
[vid
] = NULL
;
305 spin_unlock_irqrestore(&nic
->tx_lock
, flags
);
309 * Constants to be programmed into the Xena's registers, to configure
314 static const u64 herc_act_dtx_cfg
[] = {
316 0x8000051536750000ULL
, 0x80000515367500E0ULL
,
318 0x8000051536750004ULL
, 0x80000515367500E4ULL
,
320 0x80010515003F0000ULL
, 0x80010515003F00E0ULL
,
322 0x80010515003F0004ULL
, 0x80010515003F00E4ULL
,
324 0x801205150D440000ULL
, 0x801205150D4400E0ULL
,
326 0x801205150D440004ULL
, 0x801205150D4400E4ULL
,
328 0x80020515F2100000ULL
, 0x80020515F21000E0ULL
,
330 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
335 static const u64 xena_dtx_cfg
[] = {
337 0x8000051500000000ULL
, 0x80000515000000E0ULL
,
339 0x80000515D9350004ULL
, 0x80000515D93500E4ULL
,
341 0x8001051500000000ULL
, 0x80010515000000E0ULL
,
343 0x80010515001E0004ULL
, 0x80010515001E00E4ULL
,
345 0x8002051500000000ULL
, 0x80020515000000E0ULL
,
347 0x80020515F2100004ULL
, 0x80020515F21000E4ULL
,
352 * Constants for Fixing the MacAddress problem seen mostly on
355 static const u64 fix_mac
[] = {
356 0x0060000000000000ULL
, 0x0060600000000000ULL
,
357 0x0040600000000000ULL
, 0x0000600000000000ULL
,
358 0x0020600000000000ULL
, 0x0060600000000000ULL
,
359 0x0020600000000000ULL
, 0x0060600000000000ULL
,
360 0x0020600000000000ULL
, 0x0060600000000000ULL
,
361 0x0020600000000000ULL
, 0x0060600000000000ULL
,
362 0x0020600000000000ULL
, 0x0060600000000000ULL
,
363 0x0020600000000000ULL
, 0x0060600000000000ULL
,
364 0x0020600000000000ULL
, 0x0060600000000000ULL
,
365 0x0020600000000000ULL
, 0x0060600000000000ULL
,
366 0x0020600000000000ULL
, 0x0060600000000000ULL
,
367 0x0020600000000000ULL
, 0x0060600000000000ULL
,
368 0x0020600000000000ULL
, 0x0000600000000000ULL
,
369 0x0040600000000000ULL
, 0x0060600000000000ULL
,
373 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
374 MODULE_LICENSE("GPL");
375 MODULE_VERSION(DRV_VERSION
);
378 /* Module Loadable parameters. */
379 S2IO_PARM_INT(tx_fifo_num
, 1);
380 S2IO_PARM_INT(rx_ring_num
, 1);
383 S2IO_PARM_INT(rx_ring_mode
, 1);
384 S2IO_PARM_INT(use_continuous_tx_intrs
, 1);
385 S2IO_PARM_INT(rmac_pause_time
, 0x100);
386 S2IO_PARM_INT(mc_pause_threshold_q0q3
, 187);
387 S2IO_PARM_INT(mc_pause_threshold_q4q7
, 187);
388 S2IO_PARM_INT(shared_splits
, 0);
389 S2IO_PARM_INT(tmac_util_period
, 5);
390 S2IO_PARM_INT(rmac_util_period
, 5);
391 S2IO_PARM_INT(bimodal
, 0);
392 S2IO_PARM_INT(l3l4hdr_size
, 128);
393 /* Frequency of Rx desc syncs expressed as power of 2 */
394 S2IO_PARM_INT(rxsync_frequency
, 3);
395 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
396 S2IO_PARM_INT(intr_type
, 0);
397 /* Large receive offload feature */
398 S2IO_PARM_INT(lro
, 0);
399 /* Max pkts to be aggregated by LRO at one time. If not specified,
400 * aggregation happens until we hit max IP pkt size(64K)
402 S2IO_PARM_INT(lro_max_pkts
, 0xFFFF);
403 S2IO_PARM_INT(indicate_max_pkts
, 0);
405 S2IO_PARM_INT(napi
, 1);
406 S2IO_PARM_INT(ufo
, 0);
408 static unsigned int tx_fifo_len
[MAX_TX_FIFOS
] =
409 {DEFAULT_FIFO_0_LEN
, [1 ...(MAX_TX_FIFOS
- 1)] = DEFAULT_FIFO_1_7_LEN
};
410 static unsigned int rx_ring_sz
[MAX_RX_RINGS
] =
411 {[0 ...(MAX_RX_RINGS
- 1)] = SMALL_BLK_CNT
};
412 static unsigned int rts_frm_len
[MAX_RX_RINGS
] =
413 {[0 ...(MAX_RX_RINGS
- 1)] = 0 };
415 module_param_array(tx_fifo_len
, uint
, NULL
, 0);
416 module_param_array(rx_ring_sz
, uint
, NULL
, 0);
417 module_param_array(rts_frm_len
, uint
, NULL
, 0);
421 * This table lists all the devices that this driver supports.
423 static struct pci_device_id s2io_tbl
[] __devinitdata
= {
424 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_WIN
,
425 PCI_ANY_ID
, PCI_ANY_ID
},
426 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_S2IO_UNI
,
427 PCI_ANY_ID
, PCI_ANY_ID
},
428 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_WIN
,
429 PCI_ANY_ID
, PCI_ANY_ID
},
430 {PCI_VENDOR_ID_S2IO
, PCI_DEVICE_ID_HERC_UNI
,
431 PCI_ANY_ID
, PCI_ANY_ID
},
435 MODULE_DEVICE_TABLE(pci
, s2io_tbl
);
437 static struct pci_driver s2io_driver
= {
439 .id_table
= s2io_tbl
,
440 .probe
= s2io_init_nic
,
441 .remove
= __devexit_p(s2io_rem_nic
),
444 /* A simplifier macro used both by init and free shared_mem Fns(). */
445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
448 * init_shared_mem - Allocation and Initialization of Memory
449 * @nic: Device private variable.
450 * Description: The function allocates all the memory areas shared
451 * between the NIC and the driver. This includes Tx descriptors,
452 * Rx descriptors and the statistics block.
455 static int init_shared_mem(struct s2io_nic
*nic
)
458 void *tmp_v_addr
, *tmp_v_addr_next
;
459 dma_addr_t tmp_p_addr
, tmp_p_addr_next
;
460 struct RxD_block
*pre_rxd_blk
= NULL
;
462 int lst_size
, lst_per_page
;
463 struct net_device
*dev
= nic
->dev
;
467 struct mac_info
*mac_control
;
468 struct config_param
*config
;
470 mac_control
= &nic
->mac_control
;
471 config
= &nic
->config
;
474 /* Allocation and initialization of TXDLs in FIOFs */
476 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
477 size
+= config
->tx_cfg
[i
].fifo_len
;
479 if (size
> MAX_AVAILABLE_TXDS
) {
480 DBG_PRINT(ERR_DBG
, "s2io: Requested TxDs too high, ");
481 DBG_PRINT(ERR_DBG
, "Requested: %d, max supported: 8192\n", size
);
485 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
486 lst_per_page
= PAGE_SIZE
/ lst_size
;
488 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
489 int fifo_len
= config
->tx_cfg
[i
].fifo_len
;
490 int list_holder_size
= fifo_len
* sizeof(struct list_info_hold
);
491 mac_control
->fifos
[i
].list_info
= kmalloc(list_holder_size
,
493 if (!mac_control
->fifos
[i
].list_info
) {
495 "Malloc failed for list_info\n");
498 memset(mac_control
->fifos
[i
].list_info
, 0, list_holder_size
);
500 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
501 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
503 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
504 mac_control
->fifos
[i
].tx_curr_put_info
.fifo_len
=
505 config
->tx_cfg
[i
].fifo_len
- 1;
506 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
507 mac_control
->fifos
[i
].tx_curr_get_info
.fifo_len
=
508 config
->tx_cfg
[i
].fifo_len
- 1;
509 mac_control
->fifos
[i
].fifo_no
= i
;
510 mac_control
->fifos
[i
].nic
= nic
;
511 mac_control
->fifos
[i
].max_txds
= MAX_SKB_FRAGS
+ 2;
513 for (j
= 0; j
< page_num
; j
++) {
517 tmp_v
= pci_alloc_consistent(nic
->pdev
,
521 "pci_alloc_consistent ");
522 DBG_PRINT(ERR_DBG
, "failed for TxDL\n");
525 /* If we got a zero DMA address(can happen on
526 * certain platforms like PPC), reallocate.
527 * Store virtual address of page we don't want,
531 mac_control
->zerodma_virt_addr
= tmp_v
;
533 "%s: Zero DMA address for TxDL. ", dev
->name
);
535 "Virtual address %p\n", tmp_v
);
536 tmp_v
= pci_alloc_consistent(nic
->pdev
,
540 "pci_alloc_consistent ");
541 DBG_PRINT(ERR_DBG
, "failed for TxDL\n");
545 while (k
< lst_per_page
) {
546 int l
= (j
* lst_per_page
) + k
;
547 if (l
== config
->tx_cfg
[i
].fifo_len
)
549 mac_control
->fifos
[i
].list_info
[l
].list_virt_addr
=
550 tmp_v
+ (k
* lst_size
);
551 mac_control
->fifos
[i
].list_info
[l
].list_phy_addr
=
552 tmp_p
+ (k
* lst_size
);
558 nic
->ufo_in_band_v
= kcalloc(size
, sizeof(u64
), GFP_KERNEL
);
559 if (!nic
->ufo_in_band_v
)
562 /* Allocation and initialization of RXDs in Rings */
564 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
565 if (config
->rx_cfg
[i
].num_rxd
%
566 (rxd_count
[nic
->rxd_mode
] + 1)) {
567 DBG_PRINT(ERR_DBG
, "%s: RxD count of ", dev
->name
);
568 DBG_PRINT(ERR_DBG
, "Ring%d is not a multiple of ",
570 DBG_PRINT(ERR_DBG
, "RxDs per Block");
573 size
+= config
->rx_cfg
[i
].num_rxd
;
574 mac_control
->rings
[i
].block_count
=
575 config
->rx_cfg
[i
].num_rxd
/
576 (rxd_count
[nic
->rxd_mode
] + 1 );
577 mac_control
->rings
[i
].pkt_cnt
= config
->rx_cfg
[i
].num_rxd
-
578 mac_control
->rings
[i
].block_count
;
580 if (nic
->rxd_mode
== RXD_MODE_1
)
581 size
= (size
* (sizeof(struct RxD1
)));
583 size
= (size
* (sizeof(struct RxD3
)));
585 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
586 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
587 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
588 mac_control
->rings
[i
].rx_curr_get_info
.ring_len
=
589 config
->rx_cfg
[i
].num_rxd
- 1;
590 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
591 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
592 mac_control
->rings
[i
].rx_curr_put_info
.ring_len
=
593 config
->rx_cfg
[i
].num_rxd
- 1;
594 mac_control
->rings
[i
].nic
= nic
;
595 mac_control
->rings
[i
].ring_no
= i
;
597 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
598 (rxd_count
[nic
->rxd_mode
] + 1);
599 /* Allocating all the Rx blocks */
600 for (j
= 0; j
< blk_cnt
; j
++) {
601 struct rx_block_info
*rx_blocks
;
604 rx_blocks
= &mac_control
->rings
[i
].rx_blocks
[j
];
605 size
= SIZE_OF_BLOCK
; //size is always page size
606 tmp_v_addr
= pci_alloc_consistent(nic
->pdev
, size
,
608 if (tmp_v_addr
== NULL
) {
610 * In case of failure, free_shared_mem()
611 * is called, which should free any
612 * memory that was alloced till the
615 rx_blocks
->block_virt_addr
= tmp_v_addr
;
618 memset(tmp_v_addr
, 0, size
);
619 rx_blocks
->block_virt_addr
= tmp_v_addr
;
620 rx_blocks
->block_dma_addr
= tmp_p_addr
;
621 rx_blocks
->rxds
= kmalloc(sizeof(struct rxd_info
)*
622 rxd_count
[nic
->rxd_mode
],
624 if (!rx_blocks
->rxds
)
626 for (l
=0; l
<rxd_count
[nic
->rxd_mode
];l
++) {
627 rx_blocks
->rxds
[l
].virt_addr
=
628 rx_blocks
->block_virt_addr
+
629 (rxd_size
[nic
->rxd_mode
] * l
);
630 rx_blocks
->rxds
[l
].dma_addr
=
631 rx_blocks
->block_dma_addr
+
632 (rxd_size
[nic
->rxd_mode
] * l
);
635 /* Interlinking all Rx Blocks */
636 for (j
= 0; j
< blk_cnt
; j
++) {
638 mac_control
->rings
[i
].rx_blocks
[j
].block_virt_addr
;
640 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
641 blk_cnt
].block_virt_addr
;
643 mac_control
->rings
[i
].rx_blocks
[j
].block_dma_addr
;
645 mac_control
->rings
[i
].rx_blocks
[(j
+ 1) %
646 blk_cnt
].block_dma_addr
;
648 pre_rxd_blk
= (struct RxD_block
*) tmp_v_addr
;
649 pre_rxd_blk
->reserved_2_pNext_RxD_block
=
650 (unsigned long) tmp_v_addr_next
;
651 pre_rxd_blk
->pNext_RxD_Blk_physical
=
652 (u64
) tmp_p_addr_next
;
655 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
657 * Allocation of Storages for buffer addresses in 2BUFF mode
658 * and the buffers as well.
660 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
661 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
662 (rxd_count
[nic
->rxd_mode
]+ 1);
663 mac_control
->rings
[i
].ba
=
664 kmalloc((sizeof(struct buffAdd
*) * blk_cnt
),
666 if (!mac_control
->rings
[i
].ba
)
668 for (j
= 0; j
< blk_cnt
; j
++) {
670 mac_control
->rings
[i
].ba
[j
] =
671 kmalloc((sizeof(struct buffAdd
) *
672 (rxd_count
[nic
->rxd_mode
] + 1)),
674 if (!mac_control
->rings
[i
].ba
[j
])
676 while (k
!= rxd_count
[nic
->rxd_mode
]) {
677 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
679 ba
->ba_0_org
= (void *) kmalloc
680 (BUF0_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
683 tmp
= (unsigned long)ba
->ba_0_org
;
685 tmp
&= ~((unsigned long) ALIGN_SIZE
);
686 ba
->ba_0
= (void *) tmp
;
688 ba
->ba_1_org
= (void *) kmalloc
689 (BUF1_LEN
+ ALIGN_SIZE
, GFP_KERNEL
);
692 tmp
= (unsigned long) ba
->ba_1_org
;
694 tmp
&= ~((unsigned long) ALIGN_SIZE
);
695 ba
->ba_1
= (void *) tmp
;
702 /* Allocation and initialization of Statistics block */
703 size
= sizeof(struct stat_block
);
704 mac_control
->stats_mem
= pci_alloc_consistent
705 (nic
->pdev
, size
, &mac_control
->stats_mem_phy
);
707 if (!mac_control
->stats_mem
) {
709 * In case of failure, free_shared_mem() is called, which
710 * should free any memory that was alloced till the
715 mac_control
->stats_mem_sz
= size
;
717 tmp_v_addr
= mac_control
->stats_mem
;
718 mac_control
->stats_info
= (struct stat_block
*) tmp_v_addr
;
719 memset(tmp_v_addr
, 0, size
);
720 DBG_PRINT(INIT_DBG
, "%s:Ring Mem PHY: 0x%llx\n", dev
->name
,
721 (unsigned long long) tmp_p_addr
);
727 * free_shared_mem - Free the allocated Memory
728 * @nic: Device private variable.
729 * Description: This function is to free all memory locations allocated by
730 * the init_shared_mem() function and return it to the kernel.
733 static void free_shared_mem(struct s2io_nic
*nic
)
735 int i
, j
, blk_cnt
, size
;
737 dma_addr_t tmp_p_addr
;
738 struct mac_info
*mac_control
;
739 struct config_param
*config
;
740 int lst_size
, lst_per_page
;
741 struct net_device
*dev
= nic
->dev
;
746 mac_control
= &nic
->mac_control
;
747 config
= &nic
->config
;
749 lst_size
= (sizeof(struct TxD
) * config
->max_txds
);
750 lst_per_page
= PAGE_SIZE
/ lst_size
;
752 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
753 int page_num
= TXD_MEM_PAGE_CNT(config
->tx_cfg
[i
].fifo_len
,
755 for (j
= 0; j
< page_num
; j
++) {
756 int mem_blks
= (j
* lst_per_page
);
757 if (!mac_control
->fifos
[i
].list_info
)
759 if (!mac_control
->fifos
[i
].list_info
[mem_blks
].
762 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
763 mac_control
->fifos
[i
].
766 mac_control
->fifos
[i
].
770 /* If we got a zero DMA address during allocation,
773 if (mac_control
->zerodma_virt_addr
) {
774 pci_free_consistent(nic
->pdev
, PAGE_SIZE
,
775 mac_control
->zerodma_virt_addr
,
778 "%s: Freeing TxDL with zero DMA addr. ",
780 DBG_PRINT(INIT_DBG
, "Virtual address %p\n",
781 mac_control
->zerodma_virt_addr
);
783 kfree(mac_control
->fifos
[i
].list_info
);
786 size
= SIZE_OF_BLOCK
;
787 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
788 blk_cnt
= mac_control
->rings
[i
].block_count
;
789 for (j
= 0; j
< blk_cnt
; j
++) {
790 tmp_v_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
792 tmp_p_addr
= mac_control
->rings
[i
].rx_blocks
[j
].
794 if (tmp_v_addr
== NULL
)
796 pci_free_consistent(nic
->pdev
, size
,
797 tmp_v_addr
, tmp_p_addr
);
798 kfree(mac_control
->rings
[i
].rx_blocks
[j
].rxds
);
802 if (nic
->rxd_mode
>= RXD_MODE_3A
) {
803 /* Freeing buffer storage addresses in 2BUFF mode. */
804 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
805 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
806 (rxd_count
[nic
->rxd_mode
] + 1);
807 for (j
= 0; j
< blk_cnt
; j
++) {
809 if (!mac_control
->rings
[i
].ba
[j
])
811 while (k
!= rxd_count
[nic
->rxd_mode
]) {
813 &mac_control
->rings
[i
].ba
[j
][k
];
818 kfree(mac_control
->rings
[i
].ba
[j
]);
820 kfree(mac_control
->rings
[i
].ba
);
824 if (mac_control
->stats_mem
) {
825 pci_free_consistent(nic
->pdev
,
826 mac_control
->stats_mem_sz
,
827 mac_control
->stats_mem
,
828 mac_control
->stats_mem_phy
);
830 if (nic
->ufo_in_band_v
)
831 kfree(nic
->ufo_in_band_v
);
835 * s2io_verify_pci_mode -
838 static int s2io_verify_pci_mode(struct s2io_nic
*nic
)
840 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
841 register u64 val64
= 0;
844 val64
= readq(&bar0
->pci_mode
);
845 mode
= (u8
)GET_PCI_MODE(val64
);
847 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
848 return -1; /* Unknown PCI mode */
852 #define NEC_VENID 0x1033
853 #define NEC_DEVID 0x0125
854 static int s2io_on_nec_bridge(struct pci_dev
*s2io_pdev
)
856 struct pci_dev
*tdev
= NULL
;
857 while ((tdev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, tdev
)) != NULL
) {
858 if (tdev
->vendor
== NEC_VENID
&& tdev
->device
== NEC_DEVID
) {
859 if (tdev
->bus
== s2io_pdev
->bus
->parent
)
867 static int bus_speed
[8] = {33, 133, 133, 200, 266, 133, 200, 266};
869 * s2io_print_pci_mode -
871 static int s2io_print_pci_mode(struct s2io_nic
*nic
)
873 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
874 register u64 val64
= 0;
876 struct config_param
*config
= &nic
->config
;
878 val64
= readq(&bar0
->pci_mode
);
879 mode
= (u8
)GET_PCI_MODE(val64
);
881 if ( val64
& PCI_MODE_UNKNOWN_MODE
)
882 return -1; /* Unknown PCI mode */
884 config
->bus_speed
= bus_speed
[mode
];
886 if (s2io_on_nec_bridge(nic
->pdev
)) {
887 DBG_PRINT(ERR_DBG
, "%s: Device is on PCI-E bus\n",
892 if (val64
& PCI_MODE_32_BITS
) {
893 DBG_PRINT(ERR_DBG
, "%s: Device is on 32 bit ", nic
->dev
->name
);
895 DBG_PRINT(ERR_DBG
, "%s: Device is on 64 bit ", nic
->dev
->name
);
899 case PCI_MODE_PCI_33
:
900 DBG_PRINT(ERR_DBG
, "33MHz PCI bus\n");
902 case PCI_MODE_PCI_66
:
903 DBG_PRINT(ERR_DBG
, "66MHz PCI bus\n");
905 case PCI_MODE_PCIX_M1_66
:
906 DBG_PRINT(ERR_DBG
, "66MHz PCIX(M1) bus\n");
908 case PCI_MODE_PCIX_M1_100
:
909 DBG_PRINT(ERR_DBG
, "100MHz PCIX(M1) bus\n");
911 case PCI_MODE_PCIX_M1_133
:
912 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M1) bus\n");
914 case PCI_MODE_PCIX_M2_66
:
915 DBG_PRINT(ERR_DBG
, "133MHz PCIX(M2) bus\n");
917 case PCI_MODE_PCIX_M2_100
:
918 DBG_PRINT(ERR_DBG
, "200MHz PCIX(M2) bus\n");
920 case PCI_MODE_PCIX_M2_133
:
921 DBG_PRINT(ERR_DBG
, "266MHz PCIX(M2) bus\n");
924 return -1; /* Unsupported bus speed */
931 * init_nic - Initialization of hardware
932 * @nic: device peivate variable
933 * Description: The function sequentially configures every block
934 * of the H/W from their reset values.
935 * Return Value: SUCCESS on success and
936 * '-1' on failure (endian settings incorrect).
939 static int init_nic(struct s2io_nic
*nic
)
941 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
942 struct net_device
*dev
= nic
->dev
;
943 register u64 val64
= 0;
947 struct mac_info
*mac_control
;
948 struct config_param
*config
;
950 unsigned long long mem_share
;
953 mac_control
= &nic
->mac_control
;
954 config
= &nic
->config
;
956 /* to set the swapper controle on the card */
957 if(s2io_set_swapper(nic
)) {
958 DBG_PRINT(ERR_DBG
,"ERROR: Setting Swapper failed\n");
963 * Herc requires EOI to be removed from reset before XGXS, so..
965 if (nic
->device_type
& XFRAME_II_DEVICE
) {
966 val64
= 0xA500000000ULL
;
967 writeq(val64
, &bar0
->sw_reset
);
969 val64
= readq(&bar0
->sw_reset
);
972 /* Remove XGXS from reset state */
974 writeq(val64
, &bar0
->sw_reset
);
976 val64
= readq(&bar0
->sw_reset
);
978 /* Enable Receiving broadcasts */
979 add
= &bar0
->mac_cfg
;
980 val64
= readq(&bar0
->mac_cfg
);
981 val64
|= MAC_RMAC_BCAST_ENABLE
;
982 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
983 writel((u32
) val64
, add
);
984 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
985 writel((u32
) (val64
>> 32), (add
+ 4));
987 /* Read registers in all blocks */
988 val64
= readq(&bar0
->mac_int_mask
);
989 val64
= readq(&bar0
->mc_int_mask
);
990 val64
= readq(&bar0
->xgxs_int_mask
);
994 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
996 if (nic
->device_type
& XFRAME_II_DEVICE
) {
997 while (herc_act_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
998 SPECIAL_REG_WRITE(herc_act_dtx_cfg
[dtx_cnt
],
999 &bar0
->dtx_control
, UF
);
1001 msleep(1); /* Necessary!! */
1005 while (xena_dtx_cfg
[dtx_cnt
] != END_SIGN
) {
1006 SPECIAL_REG_WRITE(xena_dtx_cfg
[dtx_cnt
],
1007 &bar0
->dtx_control
, UF
);
1008 val64
= readq(&bar0
->dtx_control
);
1013 /* Tx DMA Initialization */
1015 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1016 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1017 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1018 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1021 for (i
= 0, j
= 0; i
< config
->tx_fifo_num
; i
++) {
1023 vBIT(config
->tx_cfg
[i
].fifo_len
- 1, ((i
* 32) + 19),
1024 13) | vBIT(config
->tx_cfg
[i
].fifo_priority
,
1027 if (i
== (config
->tx_fifo_num
- 1)) {
1034 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1038 writeq(val64
, &bar0
->tx_fifo_partition_1
);
1042 writeq(val64
, &bar0
->tx_fifo_partition_2
);
1046 writeq(val64
, &bar0
->tx_fifo_partition_3
);
1052 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1055 if ((nic
->device_type
== XFRAME_I_DEVICE
) &&
1056 (get_xena_rev_id(nic
->pdev
) < 4))
1057 writeq(PCC_ENABLE_FOUR
, &bar0
->pcc_enable
);
1059 val64
= readq(&bar0
->tx_fifo_partition_0
);
1060 DBG_PRINT(INIT_DBG
, "Fifo partition at: 0x%p is: 0x%llx\n",
1061 &bar0
->tx_fifo_partition_0
, (unsigned long long) val64
);
1064 * Initialization of Tx_PA_CONFIG register to ignore packet
1065 * integrity checking.
1067 val64
= readq(&bar0
->tx_pa_cfg
);
1068 val64
|= TX_PA_CFG_IGNORE_FRM_ERR
| TX_PA_CFG_IGNORE_SNAP_OUI
|
1069 TX_PA_CFG_IGNORE_LLC_CTRL
| TX_PA_CFG_IGNORE_L2_ERR
;
1070 writeq(val64
, &bar0
->tx_pa_cfg
);
1072 /* Rx DMA intialization. */
1074 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1076 vBIT(config
->rx_cfg
[i
].ring_priority
, (5 + (i
* 8)),
1079 writeq(val64
, &bar0
->rx_queue_priority
);
1082 * Allocating equal share of memory to all the
1086 if (nic
->device_type
& XFRAME_II_DEVICE
)
1091 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1094 mem_share
= (mem_size
/ config
->rx_ring_num
+
1095 mem_size
% config
->rx_ring_num
);
1096 val64
|= RX_QUEUE_CFG_Q0_SZ(mem_share
);
1099 mem_share
= (mem_size
/ config
->rx_ring_num
);
1100 val64
|= RX_QUEUE_CFG_Q1_SZ(mem_share
);
1103 mem_share
= (mem_size
/ config
->rx_ring_num
);
1104 val64
|= RX_QUEUE_CFG_Q2_SZ(mem_share
);
1107 mem_share
= (mem_size
/ config
->rx_ring_num
);
1108 val64
|= RX_QUEUE_CFG_Q3_SZ(mem_share
);
1111 mem_share
= (mem_size
/ config
->rx_ring_num
);
1112 val64
|= RX_QUEUE_CFG_Q4_SZ(mem_share
);
1115 mem_share
= (mem_size
/ config
->rx_ring_num
);
1116 val64
|= RX_QUEUE_CFG_Q5_SZ(mem_share
);
1119 mem_share
= (mem_size
/ config
->rx_ring_num
);
1120 val64
|= RX_QUEUE_CFG_Q6_SZ(mem_share
);
1123 mem_share
= (mem_size
/ config
->rx_ring_num
);
1124 val64
|= RX_QUEUE_CFG_Q7_SZ(mem_share
);
1128 writeq(val64
, &bar0
->rx_queue_cfg
);
1131 * Filling Tx round robin registers
1132 * as per the number of FIFOs
1134 switch (config
->tx_fifo_num
) {
1136 val64
= 0x0000000000000000ULL
;
1137 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1138 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1139 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1140 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1141 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1144 val64
= 0x0000010000010000ULL
;
1145 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1146 val64
= 0x0100000100000100ULL
;
1147 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1148 val64
= 0x0001000001000001ULL
;
1149 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1150 val64
= 0x0000010000010000ULL
;
1151 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1152 val64
= 0x0100000000000000ULL
;
1153 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1156 val64
= 0x0001000102000001ULL
;
1157 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1158 val64
= 0x0001020000010001ULL
;
1159 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1160 val64
= 0x0200000100010200ULL
;
1161 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1162 val64
= 0x0001000102000001ULL
;
1163 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1164 val64
= 0x0001020000000000ULL
;
1165 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1168 val64
= 0x0001020300010200ULL
;
1169 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1170 val64
= 0x0100000102030001ULL
;
1171 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1172 val64
= 0x0200010000010203ULL
;
1173 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1174 val64
= 0x0001020001000001ULL
;
1175 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1176 val64
= 0x0203000100000000ULL
;
1177 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1180 val64
= 0x0001000203000102ULL
;
1181 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1182 val64
= 0x0001020001030004ULL
;
1183 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1184 val64
= 0x0001000203000102ULL
;
1185 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1186 val64
= 0x0001020001030004ULL
;
1187 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1188 val64
= 0x0001000000000000ULL
;
1189 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1192 val64
= 0x0001020304000102ULL
;
1193 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1194 val64
= 0x0304050001020001ULL
;
1195 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1196 val64
= 0x0203000100000102ULL
;
1197 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1198 val64
= 0x0304000102030405ULL
;
1199 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1200 val64
= 0x0001000200000000ULL
;
1201 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1204 val64
= 0x0001020001020300ULL
;
1205 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1206 val64
= 0x0102030400010203ULL
;
1207 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1208 val64
= 0x0405060001020001ULL
;
1209 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1210 val64
= 0x0304050000010200ULL
;
1211 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1212 val64
= 0x0102030000000000ULL
;
1213 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1216 val64
= 0x0001020300040105ULL
;
1217 writeq(val64
, &bar0
->tx_w_round_robin_0
);
1218 val64
= 0x0200030106000204ULL
;
1219 writeq(val64
, &bar0
->tx_w_round_robin_1
);
1220 val64
= 0x0103000502010007ULL
;
1221 writeq(val64
, &bar0
->tx_w_round_robin_2
);
1222 val64
= 0x0304010002060500ULL
;
1223 writeq(val64
, &bar0
->tx_w_round_robin_3
);
1224 val64
= 0x0103020400000000ULL
;
1225 writeq(val64
, &bar0
->tx_w_round_robin_4
);
1229 /* Enable all configured Tx FIFO partitions */
1230 val64
= readq(&bar0
->tx_fifo_partition_0
);
1231 val64
|= (TX_FIFO_PARTITION_EN
);
1232 writeq(val64
, &bar0
->tx_fifo_partition_0
);
1234 /* Filling the Rx round robin registers as per the
1235 * number of Rings and steering based on QoS.
1237 switch (config
->rx_ring_num
) {
1239 val64
= 0x8080808080808080ULL
;
1240 writeq(val64
, &bar0
->rts_qos_steering
);
1243 val64
= 0x0000010000010000ULL
;
1244 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1245 val64
= 0x0100000100000100ULL
;
1246 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1247 val64
= 0x0001000001000001ULL
;
1248 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1249 val64
= 0x0000010000010000ULL
;
1250 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1251 val64
= 0x0100000000000000ULL
;
1252 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1254 val64
= 0x8080808040404040ULL
;
1255 writeq(val64
, &bar0
->rts_qos_steering
);
1258 val64
= 0x0001000102000001ULL
;
1259 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1260 val64
= 0x0001020000010001ULL
;
1261 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1262 val64
= 0x0200000100010200ULL
;
1263 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1264 val64
= 0x0001000102000001ULL
;
1265 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1266 val64
= 0x0001020000000000ULL
;
1267 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1269 val64
= 0x8080804040402020ULL
;
1270 writeq(val64
, &bar0
->rts_qos_steering
);
1273 val64
= 0x0001020300010200ULL
;
1274 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1275 val64
= 0x0100000102030001ULL
;
1276 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1277 val64
= 0x0200010000010203ULL
;
1278 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1279 val64
= 0x0001020001000001ULL
;
1280 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1281 val64
= 0x0203000100000000ULL
;
1282 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1284 val64
= 0x8080404020201010ULL
;
1285 writeq(val64
, &bar0
->rts_qos_steering
);
1288 val64
= 0x0001000203000102ULL
;
1289 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1290 val64
= 0x0001020001030004ULL
;
1291 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1292 val64
= 0x0001000203000102ULL
;
1293 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1294 val64
= 0x0001020001030004ULL
;
1295 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1296 val64
= 0x0001000000000000ULL
;
1297 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1299 val64
= 0x8080404020201008ULL
;
1300 writeq(val64
, &bar0
->rts_qos_steering
);
1303 val64
= 0x0001020304000102ULL
;
1304 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1305 val64
= 0x0304050001020001ULL
;
1306 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1307 val64
= 0x0203000100000102ULL
;
1308 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1309 val64
= 0x0304000102030405ULL
;
1310 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1311 val64
= 0x0001000200000000ULL
;
1312 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1314 val64
= 0x8080404020100804ULL
;
1315 writeq(val64
, &bar0
->rts_qos_steering
);
1318 val64
= 0x0001020001020300ULL
;
1319 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1320 val64
= 0x0102030400010203ULL
;
1321 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1322 val64
= 0x0405060001020001ULL
;
1323 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1324 val64
= 0x0304050000010200ULL
;
1325 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1326 val64
= 0x0102030000000000ULL
;
1327 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1329 val64
= 0x8080402010080402ULL
;
1330 writeq(val64
, &bar0
->rts_qos_steering
);
1333 val64
= 0x0001020300040105ULL
;
1334 writeq(val64
, &bar0
->rx_w_round_robin_0
);
1335 val64
= 0x0200030106000204ULL
;
1336 writeq(val64
, &bar0
->rx_w_round_robin_1
);
1337 val64
= 0x0103000502010007ULL
;
1338 writeq(val64
, &bar0
->rx_w_round_robin_2
);
1339 val64
= 0x0304010002060500ULL
;
1340 writeq(val64
, &bar0
->rx_w_round_robin_3
);
1341 val64
= 0x0103020400000000ULL
;
1342 writeq(val64
, &bar0
->rx_w_round_robin_4
);
1344 val64
= 0x8040201008040201ULL
;
1345 writeq(val64
, &bar0
->rts_qos_steering
);
1351 for (i
= 0; i
< 8; i
++)
1352 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1354 /* Set the default rts frame length for the rings configured */
1355 val64
= MAC_RTS_FRM_LEN_SET(dev
->mtu
+22);
1356 for (i
= 0 ; i
< config
->rx_ring_num
; i
++)
1357 writeq(val64
, &bar0
->rts_frm_len_n
[i
]);
1359 /* Set the frame length for the configured rings
1360 * desired by the user
1362 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1363 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364 * specified frame length steering.
1365 * If the user provides the frame length then program
1366 * the rts_frm_len register for those values or else
1367 * leave it as it is.
1369 if (rts_frm_len
[i
] != 0) {
1370 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len
[i
]),
1371 &bar0
->rts_frm_len_n
[i
]);
1375 /* Program statistics memory */
1376 writeq(mac_control
->stats_mem_phy
, &bar0
->stat_addr
);
1378 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1379 val64
= STAT_BC(0x320);
1380 writeq(val64
, &bar0
->stat_byte_cnt
);
1384 * Initializing the sampling rate for the device to calculate the
1385 * bandwidth utilization.
1387 val64
= MAC_TX_LINK_UTIL_VAL(tmac_util_period
) |
1388 MAC_RX_LINK_UTIL_VAL(rmac_util_period
);
1389 writeq(val64
, &bar0
->mac_link_util
);
1393 * Initializing the Transmit and Receive Traffic Interrupt
1397 * TTI Initialization. Default Tx timer gets us about
1398 * 250 interrupts per sec. Continuous interrupts are enabled
1401 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1402 int count
= (nic
->config
.bus_speed
* 125)/2;
1403 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(count
);
1406 val64
= TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1408 val64
|= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1409 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1410 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN
;
1411 if (use_continuous_tx_intrs
)
1412 val64
|= TTI_DATA1_MEM_TX_TIMER_CI_EN
;
1413 writeq(val64
, &bar0
->tti_data1_mem
);
1415 val64
= TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1417 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1418 writeq(val64
, &bar0
->tti_data2_mem
);
1420 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1421 writeq(val64
, &bar0
->tti_command_mem
);
1424 * Once the operation completes, the Strobe bit of the command
1425 * register will be reset. We poll for this particular condition
1426 * We wait for a maximum of 500ms for the operation to complete,
1427 * if it's not complete by then we return error.
1431 val64
= readq(&bar0
->tti_command_mem
);
1432 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1436 DBG_PRINT(ERR_DBG
, "%s: TTI init Failed\n",
1444 if (nic
->config
.bimodal
) {
1446 for (k
= 0; k
< config
->rx_ring_num
; k
++) {
1447 val64
= TTI_CMD_MEM_WE
| TTI_CMD_MEM_STROBE_NEW_CMD
;
1448 val64
|= TTI_CMD_MEM_OFFSET(0x38+k
);
1449 writeq(val64
, &bar0
->tti_command_mem
);
1452 * Once the operation completes, the Strobe bit of the command
1453 * register will be reset. We poll for this particular condition
1454 * We wait for a maximum of 500ms for the operation to complete,
1455 * if it's not complete by then we return error.
1459 val64
= readq(&bar0
->tti_command_mem
);
1460 if (!(val64
& TTI_CMD_MEM_STROBE_NEW_CMD
)) {
1465 "%s: TTI init Failed\n",
1475 /* RTI Initialization */
1476 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1478 * Programmed to generate Apprx 500 Intrs per
1481 int count
= (nic
->config
.bus_speed
* 125)/4;
1482 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(count
);
1484 val64
= RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1486 val64
|= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN
;
1490 writeq(val64
, &bar0
->rti_data1_mem
);
1492 val64
= RTI_DATA2_MEM_RX_UFC_A(0x1) |
1493 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494 if (nic
->intr_type
== MSI_X
)
1495 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496 RTI_DATA2_MEM_RX_UFC_D(0x40));
1498 val64
|= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499 RTI_DATA2_MEM_RX_UFC_D(0x80));
1500 writeq(val64
, &bar0
->rti_data2_mem
);
1502 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1503 val64
= RTI_CMD_MEM_WE
| RTI_CMD_MEM_STROBE_NEW_CMD
1504 | RTI_CMD_MEM_OFFSET(i
);
1505 writeq(val64
, &bar0
->rti_command_mem
);
1508 * Once the operation completes, the Strobe bit of the
1509 * command register will be reset. We poll for this
1510 * particular condition. We wait for a maximum of 500ms
1511 * for the operation to complete, if it's not complete
1512 * by then we return error.
1516 val64
= readq(&bar0
->rti_command_mem
);
1517 if (!(val64
& RTI_CMD_MEM_STROBE_NEW_CMD
)) {
1521 DBG_PRINT(ERR_DBG
, "%s: RTI init Failed\n",
1532 * Initializing proper values as Pause threshold into all
1533 * the 8 Queues on Rx side.
1535 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q0q3
);
1536 writeq(0xffbbffbbffbbffbbULL
, &bar0
->mc_pause_thresh_q4q7
);
1538 /* Disable RMAC PAD STRIPPING */
1539 add
= &bar0
->mac_cfg
;
1540 val64
= readq(&bar0
->mac_cfg
);
1541 val64
&= ~(MAC_CFG_RMAC_STRIP_PAD
);
1542 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1543 writel((u32
) (val64
), add
);
1544 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1545 writel((u32
) (val64
>> 32), (add
+ 4));
1546 val64
= readq(&bar0
->mac_cfg
);
1548 /* Enable FCS stripping by adapter */
1549 add
= &bar0
->mac_cfg
;
1550 val64
= readq(&bar0
->mac_cfg
);
1551 val64
|= MAC_CFG_RMAC_STRIP_FCS
;
1552 if (nic
->device_type
== XFRAME_II_DEVICE
)
1553 writeq(val64
, &bar0
->mac_cfg
);
1555 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1556 writel((u32
) (val64
), add
);
1557 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
1558 writel((u32
) (val64
>> 32), (add
+ 4));
1562 * Set the time value to be inserted in the pause frame
1563 * generated by xena.
1565 val64
= readq(&bar0
->rmac_pause_cfg
);
1566 val64
&= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567 val64
|= RMAC_PAUSE_HG_PTIME(nic
->mac_control
.rmac_pause_time
);
1568 writeq(val64
, &bar0
->rmac_pause_cfg
);
1571 * Set the Threshold Limit for Generating the pause frame
1572 * If the amount of data in any Queue exceeds ratio of
1573 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574 * pause frame is generated
1577 for (i
= 0; i
< 4; i
++) {
1579 (((u64
) 0xFF00 | nic
->mac_control
.
1580 mc_pause_threshold_q0q3
)
1583 writeq(val64
, &bar0
->mc_pause_thresh_q0q3
);
1586 for (i
= 0; i
< 4; i
++) {
1588 (((u64
) 0xFF00 | nic
->mac_control
.
1589 mc_pause_threshold_q4q7
)
1592 writeq(val64
, &bar0
->mc_pause_thresh_q4q7
);
1595 * TxDMA will stop Read request if the number of read split has
1596 * exceeded the limit pointed by shared_splits
1598 val64
= readq(&bar0
->pic_control
);
1599 val64
|= PIC_CNTL_SHARED_SPLITS(shared_splits
);
1600 writeq(val64
, &bar0
->pic_control
);
1602 if (nic
->config
.bus_speed
== 266) {
1603 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN
, &bar0
->txreqtimeout
);
1604 writeq(0x0, &bar0
->read_retry_delay
);
1605 writeq(0x0, &bar0
->write_retry_delay
);
1609 * Programming the Herc to split every write transaction
1610 * that does not start on an ADB to reduce disconnects.
1612 if (nic
->device_type
== XFRAME_II_DEVICE
) {
1613 val64
= FAULT_BEHAVIOUR
| EXT_REQ_EN
|
1614 MISC_LINK_STABILITY_PRD(3);
1615 writeq(val64
, &bar0
->misc_control
);
1616 val64
= readq(&bar0
->pic_control2
);
1617 val64
&= ~(BIT(13)|BIT(14)|BIT(15));
1618 writeq(val64
, &bar0
->pic_control2
);
1620 if (strstr(nic
->product_name
, "CX4")) {
1621 val64
= TMAC_AVG_IPG(0x17);
1622 writeq(val64
, &bar0
->tmac_avg_ipg
);
1627 #define LINK_UP_DOWN_INTERRUPT 1
1628 #define MAC_RMAC_ERR_TIMER 2
1630 static int s2io_link_fault_indication(struct s2io_nic
*nic
)
1632 if (nic
->intr_type
!= INTA
)
1633 return MAC_RMAC_ERR_TIMER
;
1634 if (nic
->device_type
== XFRAME_II_DEVICE
)
1635 return LINK_UP_DOWN_INTERRUPT
;
1637 return MAC_RMAC_ERR_TIMER
;
1641 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1642 * @nic: device private variable,
1643 * @mask: A mask indicating which Intr block must be modified and,
1644 * @flag: A flag indicating whether to enable or disable the Intrs.
1645 * Description: This function will either disable or enable the interrupts
1646 * depending on the flag argument. The mask argument can be used to
1647 * enable/disable any Intr block.
1648 * Return Value: NONE.
1651 static void en_dis_able_nic_intrs(struct s2io_nic
*nic
, u16 mask
, int flag
)
1653 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1654 register u64 val64
= 0, temp64
= 0;
1656 /* Top level interrupt classification */
1657 /* PIC Interrupts */
1658 if ((mask
& (TX_PIC_INTR
| RX_PIC_INTR
))) {
1659 /* Enable PIC Intrs in the general intr mask register */
1660 val64
= TXPIC_INT_M
;
1661 if (flag
== ENABLE_INTRS
) {
1662 temp64
= readq(&bar0
->general_int_mask
);
1663 temp64
&= ~((u64
) val64
);
1664 writeq(temp64
, &bar0
->general_int_mask
);
1666 * If Hercules adapter enable GPIO otherwise
1667 * disable all PCIX, Flash, MDIO, IIC and GPIO
1668 * interrupts for now.
1671 if (s2io_link_fault_indication(nic
) ==
1672 LINK_UP_DOWN_INTERRUPT
) {
1673 temp64
= readq(&bar0
->pic_int_mask
);
1674 temp64
&= ~((u64
) PIC_INT_GPIO
);
1675 writeq(temp64
, &bar0
->pic_int_mask
);
1676 temp64
= readq(&bar0
->gpio_int_mask
);
1677 temp64
&= ~((u64
) GPIO_INT_MASK_LINK_UP
);
1678 writeq(temp64
, &bar0
->gpio_int_mask
);
1680 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1683 * No MSI Support is available presently, so TTI and
1684 * RTI interrupts are also disabled.
1686 } else if (flag
== DISABLE_INTRS
) {
1688 * Disable PIC Intrs in the general
1689 * intr mask register
1691 writeq(DISABLE_ALL_INTRS
, &bar0
->pic_int_mask
);
1692 temp64
= readq(&bar0
->general_int_mask
);
1694 writeq(val64
, &bar0
->general_int_mask
);
1698 /* MAC Interrupts */
1699 /* Enabling/Disabling MAC interrupts */
1700 if (mask
& (TX_MAC_INTR
| RX_MAC_INTR
)) {
1701 val64
= TXMAC_INT_M
| RXMAC_INT_M
;
1702 if (flag
== ENABLE_INTRS
) {
1703 temp64
= readq(&bar0
->general_int_mask
);
1704 temp64
&= ~((u64
) val64
);
1705 writeq(temp64
, &bar0
->general_int_mask
);
1707 * All MAC block error interrupts are disabled for now
1710 } else if (flag
== DISABLE_INTRS
) {
1712 * Disable MAC Intrs in the general intr mask register
1714 writeq(DISABLE_ALL_INTRS
, &bar0
->mac_int_mask
);
1715 writeq(DISABLE_ALL_INTRS
,
1716 &bar0
->mac_rmac_err_mask
);
1718 temp64
= readq(&bar0
->general_int_mask
);
1720 writeq(val64
, &bar0
->general_int_mask
);
1724 /* Tx traffic interrupts */
1725 if (mask
& TX_TRAFFIC_INTR
) {
1726 val64
= TXTRAFFIC_INT_M
;
1727 if (flag
== ENABLE_INTRS
) {
1728 temp64
= readq(&bar0
->general_int_mask
);
1729 temp64
&= ~((u64
) val64
);
1730 writeq(temp64
, &bar0
->general_int_mask
);
1732 * Enable all the Tx side interrupts
1733 * writing 0 Enables all 64 TX interrupt levels
1735 writeq(0x0, &bar0
->tx_traffic_mask
);
1736 } else if (flag
== DISABLE_INTRS
) {
1738 * Disable Tx Traffic Intrs in the general intr mask
1741 writeq(DISABLE_ALL_INTRS
, &bar0
->tx_traffic_mask
);
1742 temp64
= readq(&bar0
->general_int_mask
);
1744 writeq(val64
, &bar0
->general_int_mask
);
1748 /* Rx traffic interrupts */
1749 if (mask
& RX_TRAFFIC_INTR
) {
1750 val64
= RXTRAFFIC_INT_M
;
1751 if (flag
== ENABLE_INTRS
) {
1752 temp64
= readq(&bar0
->general_int_mask
);
1753 temp64
&= ~((u64
) val64
);
1754 writeq(temp64
, &bar0
->general_int_mask
);
1755 /* writing 0 Enables all 8 RX interrupt levels */
1756 writeq(0x0, &bar0
->rx_traffic_mask
);
1757 } else if (flag
== DISABLE_INTRS
) {
1759 * Disable Rx Traffic Intrs in the general intr mask
1762 writeq(DISABLE_ALL_INTRS
, &bar0
->rx_traffic_mask
);
1763 temp64
= readq(&bar0
->general_int_mask
);
1765 writeq(val64
, &bar0
->general_int_mask
);
1771 * verify_pcc_quiescent- Checks for PCC quiescent state
1772 * Return: 1 If PCC is quiescence
1773 * 0 If PCC is not quiescence
1775 static int verify_pcc_quiescent(struct s2io_nic
*sp
, int flag
)
1778 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1779 u64 val64
= readq(&bar0
->adapter_status
);
1781 herc
= (sp
->device_type
== XFRAME_II_DEVICE
);
1783 if (flag
== FALSE
) {
1784 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1785 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
))
1788 if (!(val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1792 if ((!herc
&& (get_xena_rev_id(sp
->pdev
) >= 4)) || herc
) {
1793 if (((val64
& ADAPTER_STATUS_RMAC_PCC_IDLE
) ==
1794 ADAPTER_STATUS_RMAC_PCC_IDLE
))
1797 if (((val64
& ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
) ==
1798 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE
))
1806 * verify_xena_quiescence - Checks whether the H/W is ready
1807 * Description: Returns whether the H/W is ready to go or not. Depending
1808 * on whether adapter enable bit was written or not the comparison
1809 * differs and the calling function passes the input argument flag to
1811 * Return: 1 If xena is quiescence
1812 * 0 If Xena is not quiescence
1815 static int verify_xena_quiescence(struct s2io_nic
*sp
)
1818 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1819 u64 val64
= readq(&bar0
->adapter_status
);
1820 mode
= s2io_verify_pci_mode(sp
);
1822 if (!(val64
& ADAPTER_STATUS_TDMA_READY
)) {
1823 DBG_PRINT(ERR_DBG
, "%s", "TDMA is not ready!");
1826 if (!(val64
& ADAPTER_STATUS_RDMA_READY
)) {
1827 DBG_PRINT(ERR_DBG
, "%s", "RDMA is not ready!");
1830 if (!(val64
& ADAPTER_STATUS_PFC_READY
)) {
1831 DBG_PRINT(ERR_DBG
, "%s", "PFC is not ready!");
1834 if (!(val64
& ADAPTER_STATUS_TMAC_BUF_EMPTY
)) {
1835 DBG_PRINT(ERR_DBG
, "%s", "TMAC BUF is not empty!");
1838 if (!(val64
& ADAPTER_STATUS_PIC_QUIESCENT
)) {
1839 DBG_PRINT(ERR_DBG
, "%s", "PIC is not QUIESCENT!");
1842 if (!(val64
& ADAPTER_STATUS_MC_DRAM_READY
)) {
1843 DBG_PRINT(ERR_DBG
, "%s", "MC_DRAM is not ready!");
1846 if (!(val64
& ADAPTER_STATUS_MC_QUEUES_READY
)) {
1847 DBG_PRINT(ERR_DBG
, "%s", "MC_QUEUES is not ready!");
1850 if (!(val64
& ADAPTER_STATUS_M_PLL_LOCK
)) {
1851 DBG_PRINT(ERR_DBG
, "%s", "M_PLL is not locked!");
1856 * In PCI 33 mode, the P_PLL is not used, and therefore,
1857 * the the P_PLL_LOCK bit in the adapter_status register will
1860 if (!(val64
& ADAPTER_STATUS_P_PLL_LOCK
) &&
1861 sp
->device_type
== XFRAME_II_DEVICE
&& mode
!=
1863 DBG_PRINT(ERR_DBG
, "%s", "P_PLL is not locked!");
1866 if (!((val64
& ADAPTER_STATUS_RC_PRC_QUIESCENT
) ==
1867 ADAPTER_STATUS_RC_PRC_QUIESCENT
)) {
1868 DBG_PRINT(ERR_DBG
, "%s", "RC_PRC is not QUIESCENT!");
1875 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1876 * @sp: Pointer to device specifc structure
1878 * New procedure to clear mac address reading problems on Alpha platforms
1882 static void fix_mac_address(struct s2io_nic
* sp
)
1884 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
1888 while (fix_mac
[i
] != END_SIGN
) {
1889 writeq(fix_mac
[i
++], &bar0
->gpio_control
);
1891 val64
= readq(&bar0
->gpio_control
);
1896 * start_nic - Turns the device on
1897 * @nic : device private variable.
1899 * This function actually turns the device on. Before this function is
1900 * called,all Registers are configured from their reset states
1901 * and shared memory is allocated but the NIC is still quiescent. On
1902 * calling this function, the device interrupts are cleared and the NIC is
1903 * literally switched on by writing into the adapter control register.
1905 * SUCCESS on success and -1 on failure.
1908 static int start_nic(struct s2io_nic
*nic
)
1910 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
1911 struct net_device
*dev
= nic
->dev
;
1912 register u64 val64
= 0;
1914 struct mac_info
*mac_control
;
1915 struct config_param
*config
;
1917 mac_control
= &nic
->mac_control
;
1918 config
= &nic
->config
;
1920 /* PRC Initialization and configuration */
1921 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
1922 writeq((u64
) mac_control
->rings
[i
].rx_blocks
[0].block_dma_addr
,
1923 &bar0
->prc_rxd0_n
[i
]);
1925 val64
= readq(&bar0
->prc_ctrl_n
[i
]);
1926 if (nic
->config
.bimodal
)
1927 val64
|= PRC_CTRL_BIMODAL_INTERRUPT
;
1928 if (nic
->rxd_mode
== RXD_MODE_1
)
1929 val64
|= PRC_CTRL_RC_ENABLED
;
1931 val64
|= PRC_CTRL_RC_ENABLED
| PRC_CTRL_RING_MODE_3
;
1932 if (nic
->device_type
== XFRAME_II_DEVICE
)
1933 val64
|= PRC_CTRL_GROUP_READS
;
1934 val64
&= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1935 val64
|= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1936 writeq(val64
, &bar0
->prc_ctrl_n
[i
]);
1939 if (nic
->rxd_mode
== RXD_MODE_3B
) {
1940 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1941 val64
= readq(&bar0
->rx_pa_cfg
);
1942 val64
|= RX_PA_CFG_IGNORE_L2_ERR
;
1943 writeq(val64
, &bar0
->rx_pa_cfg
);
1947 * Enabling MC-RLDRAM. After enabling the device, we timeout
1948 * for around 100ms, which is approximately the time required
1949 * for the device to be ready for operation.
1951 val64
= readq(&bar0
->mc_rldram_mrs
);
1952 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
| MC_RLDRAM_MRS_ENABLE
;
1953 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
1954 val64
= readq(&bar0
->mc_rldram_mrs
);
1956 msleep(100); /* Delay by around 100 ms. */
1958 /* Enabling ECC Protection. */
1959 val64
= readq(&bar0
->adapter_control
);
1960 val64
&= ~ADAPTER_ECC_EN
;
1961 writeq(val64
, &bar0
->adapter_control
);
1964 * Clearing any possible Link state change interrupts that
1965 * could have popped up just before Enabling the card.
1967 val64
= readq(&bar0
->mac_rmac_err_reg
);
1969 writeq(val64
, &bar0
->mac_rmac_err_reg
);
1972 * Verify if the device is ready to be enabled, if so enable
1975 val64
= readq(&bar0
->adapter_status
);
1976 if (!verify_xena_quiescence(nic
)) {
1977 DBG_PRINT(ERR_DBG
, "%s: device is not ready, ", dev
->name
);
1978 DBG_PRINT(ERR_DBG
, "Adapter status reads: 0x%llx\n",
1979 (unsigned long long) val64
);
1984 * With some switches, link might be already up at this point.
1985 * Because of this weird behavior, when we enable laser,
1986 * we may not get link. We need to handle this. We cannot
1987 * figure out which switch is misbehaving. So we are forced to
1988 * make a global change.
1991 /* Enabling Laser. */
1992 val64
= readq(&bar0
->adapter_control
);
1993 val64
|= ADAPTER_EOI_TX_ON
;
1994 writeq(val64
, &bar0
->adapter_control
);
1996 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
1998 * Dont see link state interrupts initally on some switches,
1999 * so directly scheduling the link state task here.
2001 schedule_work(&nic
->set_link_task
);
2003 /* SXE-002: Initialize link and activity LED */
2004 subid
= nic
->pdev
->subsystem_device
;
2005 if (((subid
& 0xFF) >= 0x07) &&
2006 (nic
->device_type
== XFRAME_I_DEVICE
)) {
2007 val64
= readq(&bar0
->gpio_control
);
2008 val64
|= 0x0000800000000000ULL
;
2009 writeq(val64
, &bar0
->gpio_control
);
2010 val64
= 0x0411040400000000ULL
;
2011 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
2017 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2019 static struct sk_buff
*s2io_txdl_getskb(struct fifo_info
*fifo_data
, struct \
2020 TxD
*txdlp
, int get_off
)
2022 struct s2io_nic
*nic
= fifo_data
->nic
;
2023 struct sk_buff
*skb
;
2028 if (txds
->Host_Control
== (u64
)(long)nic
->ufo_in_band_v
) {
2029 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2030 txds
->Buffer_Pointer
, sizeof(u64
),
2035 skb
= (struct sk_buff
*) ((unsigned long)
2036 txds
->Host_Control
);
2038 memset(txdlp
, 0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2041 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2042 txds
->Buffer_Pointer
,
2043 skb
->len
- skb
->data_len
,
2045 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
2048 for (j
= 0; j
< frg_cnt
; j
++, txds
++) {
2049 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
2050 if (!txds
->Buffer_Pointer
)
2052 pci_unmap_page(nic
->pdev
, (dma_addr_t
)
2053 txds
->Buffer_Pointer
,
2054 frag
->size
, PCI_DMA_TODEVICE
);
2057 memset(txdlp
,0, (sizeof(struct TxD
) * fifo_data
->max_txds
));
2062 * free_tx_buffers - Free all queued Tx buffers
2063 * @nic : device private variable.
2065 * Free all queued Tx buffers.
2066 * Return Value: void
2069 static void free_tx_buffers(struct s2io_nic
*nic
)
2071 struct net_device
*dev
= nic
->dev
;
2072 struct sk_buff
*skb
;
2075 struct mac_info
*mac_control
;
2076 struct config_param
*config
;
2079 mac_control
= &nic
->mac_control
;
2080 config
= &nic
->config
;
2082 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
2083 for (j
= 0; j
< config
->tx_cfg
[i
].fifo_len
- 1; j
++) {
2084 txdp
= (struct TxD
*) mac_control
->fifos
[i
].list_info
[j
].
2086 skb
= s2io_txdl_getskb(&mac_control
->fifos
[i
], txdp
, j
);
2093 "%s:forcibly freeing %d skbs on FIFO%d\n",
2095 mac_control
->fifos
[i
].tx_curr_get_info
.offset
= 0;
2096 mac_control
->fifos
[i
].tx_curr_put_info
.offset
= 0;
2101 * stop_nic - To stop the nic
2102 * @nic ; device private variable.
2104 * This function does exactly the opposite of what the start_nic()
2105 * function does. This function is called to stop the device.
2110 static void stop_nic(struct s2io_nic
*nic
)
2112 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2113 register u64 val64
= 0;
2115 struct mac_info
*mac_control
;
2116 struct config_param
*config
;
2118 mac_control
= &nic
->mac_control
;
2119 config
= &nic
->config
;
2121 /* Disable all interrupts */
2122 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
2123 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
2124 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
2125 en_dis_able_nic_intrs(nic
, interruptible
, DISABLE_INTRS
);
2127 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2128 val64
= readq(&bar0
->adapter_control
);
2129 val64
&= ~(ADAPTER_CNTL_EN
);
2130 writeq(val64
, &bar0
->adapter_control
);
2133 static int fill_rxd_3buf(struct s2io_nic
*nic
, struct RxD_t
*rxdp
, struct \
2136 struct net_device
*dev
= nic
->dev
;
2137 struct sk_buff
*frag_list
;
2140 /* Buffer-1 receives L3/L4 headers */
2141 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= pci_map_single
2142 (nic
->pdev
, skb
->data
, l3l4hdr_size
+ 4,
2143 PCI_DMA_FROMDEVICE
);
2145 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2146 skb_shinfo(skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+ ALIGN_SIZE
);
2147 if (skb_shinfo(skb
)->frag_list
== NULL
) {
2148 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb failed\n ", dev
->name
);
2151 frag_list
= skb_shinfo(skb
)->frag_list
;
2152 skb
->truesize
+= frag_list
->truesize
;
2153 frag_list
->next
= NULL
;
2154 tmp
= (void *)ALIGN((long)frag_list
->data
, ALIGN_SIZE
+ 1);
2155 frag_list
->data
= tmp
;
2156 frag_list
->tail
= tmp
;
2158 /* Buffer-2 receives L4 data payload */
2159 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single(nic
->pdev
,
2160 frag_list
->data
, dev
->mtu
,
2161 PCI_DMA_FROMDEVICE
);
2162 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
2163 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
2169 * fill_rx_buffers - Allocates the Rx side skbs
2170 * @nic: device private variable
2171 * @ring_no: ring number
2173 * The function allocates Rx side skbs and puts the physical
2174 * address of these buffers into the RxD buffer pointers, so that the NIC
2175 * can DMA the received frame into these locations.
2176 * The NIC supports 3 receive modes, viz
2178 * 2. three buffer and
2179 * 3. Five buffer modes.
2180 * Each mode defines how many fragments the received frame will be split
2181 * up into by the NIC. The frame is split into L3 header, L4 Header,
2182 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2183 * is split into 3 fragments. As of now only single buffer mode is
2186 * SUCCESS on success or an appropriate -ve value on failure.
2189 static int fill_rx_buffers(struct s2io_nic
*nic
, int ring_no
)
2191 struct net_device
*dev
= nic
->dev
;
2192 struct sk_buff
*skb
;
2194 int off
, off1
, size
, block_no
, block_no1
;
2197 struct mac_info
*mac_control
;
2198 struct config_param
*config
;
2201 unsigned long flags
;
2202 struct RxD_t
*first_rxdp
= NULL
;
2204 mac_control
= &nic
->mac_control
;
2205 config
= &nic
->config
;
2206 alloc_cnt
= mac_control
->rings
[ring_no
].pkt_cnt
-
2207 atomic_read(&nic
->rx_bufs_left
[ring_no
]);
2209 block_no1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.block_index
;
2210 off1
= mac_control
->rings
[ring_no
].rx_curr_get_info
.offset
;
2211 while (alloc_tab
< alloc_cnt
) {
2212 block_no
= mac_control
->rings
[ring_no
].rx_curr_put_info
.
2214 off
= mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
;
2216 rxdp
= mac_control
->rings
[ring_no
].
2217 rx_blocks
[block_no
].rxds
[off
].virt_addr
;
2219 if ((block_no
== block_no1
) && (off
== off1
) &&
2220 (rxdp
->Host_Control
)) {
2221 DBG_PRINT(INTR_DBG
, "%s: Get and Put",
2223 DBG_PRINT(INTR_DBG
, " info equated\n");
2226 if (off
&& (off
== rxd_count
[nic
->rxd_mode
])) {
2227 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2229 if (mac_control
->rings
[ring_no
].rx_curr_put_info
.
2230 block_index
== mac_control
->rings
[ring_no
].
2232 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2234 block_no
= mac_control
->rings
[ring_no
].
2235 rx_curr_put_info
.block_index
;
2236 if (off
== rxd_count
[nic
->rxd_mode
])
2238 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2240 rxdp
= mac_control
->rings
[ring_no
].
2241 rx_blocks
[block_no
].block_virt_addr
;
2242 DBG_PRINT(INTR_DBG
, "%s: Next block at: %p\n",
2246 spin_lock_irqsave(&nic
->put_lock
, flags
);
2247 mac_control
->rings
[ring_no
].put_pos
=
2248 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2249 spin_unlock_irqrestore(&nic
->put_lock
, flags
);
2251 mac_control
->rings
[ring_no
].put_pos
=
2252 (block_no
* (rxd_count
[nic
->rxd_mode
] + 1)) + off
;
2254 if ((rxdp
->Control_1
& RXD_OWN_XENA
) &&
2255 ((nic
->rxd_mode
>= RXD_MODE_3A
) &&
2256 (rxdp
->Control_2
& BIT(0)))) {
2257 mac_control
->rings
[ring_no
].rx_curr_put_info
.
2261 /* calculate size of skb based on ring mode */
2262 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
2263 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
2264 if (nic
->rxd_mode
== RXD_MODE_1
)
2265 size
+= NET_IP_ALIGN
;
2266 else if (nic
->rxd_mode
== RXD_MODE_3B
)
2267 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2269 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
2272 skb
= dev_alloc_skb(size
);
2274 DBG_PRINT(ERR_DBG
, "%s: Out of ", dev
->name
);
2275 DBG_PRINT(ERR_DBG
, "memory to allocate SKBs\n");
2278 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2282 if (nic
->rxd_mode
== RXD_MODE_1
) {
2283 /* 1 buffer mode - normal operation mode */
2284 memset(rxdp
, 0, sizeof(struct RxD1
));
2285 skb_reserve(skb
, NET_IP_ALIGN
);
2286 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= pci_map_single
2287 (nic
->pdev
, skb
->data
, size
- NET_IP_ALIGN
,
2288 PCI_DMA_FROMDEVICE
);
2289 rxdp
->Control_2
= SET_BUFFER0_SIZE_1(size
- NET_IP_ALIGN
);
2291 } else if (nic
->rxd_mode
>= RXD_MODE_3A
) {
2293 * 2 or 3 buffer mode -
2294 * Both 2 buffer mode and 3 buffer mode provides 128
2295 * byte aligned receive buffers.
2297 * 3 buffer mode provides header separation where in
2298 * skb->data will have L3/L4 headers where as
2299 * skb_shinfo(skb)->frag_list will have the L4 data
2303 memset(rxdp
, 0, sizeof(struct RxD3
));
2304 ba
= &mac_control
->rings
[ring_no
].ba
[block_no
][off
];
2305 skb_reserve(skb
, BUF0_LEN
);
2306 tmp
= (u64
)(unsigned long) skb
->data
;
2309 skb
->data
= (void *) (unsigned long)tmp
;
2310 skb
->tail
= (void *) (unsigned long)tmp
;
2312 if (!(((struct RxD3
*)rxdp
)->Buffer0_ptr
))
2313 ((struct RxD3
*)rxdp
)->Buffer0_ptr
=
2314 pci_map_single(nic
->pdev
, ba
->ba_0
, BUF0_LEN
,
2315 PCI_DMA_FROMDEVICE
);
2317 pci_dma_sync_single_for_device(nic
->pdev
,
2318 (dma_addr_t
) ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2319 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2320 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
2321 if (nic
->rxd_mode
== RXD_MODE_3B
) {
2322 /* Two buffer mode */
2325 * Buffer2 will have L3/L4 header plus
2328 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= pci_map_single
2329 (nic
->pdev
, skb
->data
, dev
->mtu
+ 4,
2330 PCI_DMA_FROMDEVICE
);
2332 /* Buffer-1 will be dummy buffer. Not used */
2333 if (!(((struct RxD3
*)rxdp
)->Buffer1_ptr
)) {
2334 ((struct RxD3
*)rxdp
)->Buffer1_ptr
=
2335 pci_map_single(nic
->pdev
,
2337 PCI_DMA_FROMDEVICE
);
2339 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
2340 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3
2344 if (fill_rxd_3buf(nic
, rxdp
, skb
) == -ENOMEM
) {
2345 dev_kfree_skb_irq(skb
);
2348 first_rxdp
->Control_1
|=
2354 rxdp
->Control_2
|= BIT(0);
2356 rxdp
->Host_Control
= (unsigned long) (skb
);
2357 if (alloc_tab
& ((1 << rxsync_frequency
) - 1))
2358 rxdp
->Control_1
|= RXD_OWN_XENA
;
2360 if (off
== (rxd_count
[nic
->rxd_mode
] + 1))
2362 mac_control
->rings
[ring_no
].rx_curr_put_info
.offset
= off
;
2364 rxdp
->Control_2
|= SET_RXD_MARKER
;
2365 if (!(alloc_tab
& ((1 << rxsync_frequency
) - 1))) {
2368 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2372 atomic_inc(&nic
->rx_bufs_left
[ring_no
]);
2377 /* Transfer ownership of first descriptor to adapter just before
2378 * exiting. Before that, use memory barrier so that ownership
2379 * and other fields are seen by adapter correctly.
2383 first_rxdp
->Control_1
|= RXD_OWN_XENA
;
2389 static void free_rxd_blk(struct s2io_nic
*sp
, int ring_no
, int blk
)
2391 struct net_device
*dev
= sp
->dev
;
2393 struct sk_buff
*skb
;
2395 struct mac_info
*mac_control
;
2398 mac_control
= &sp
->mac_control
;
2399 for (j
= 0 ; j
< rxd_count
[sp
->rxd_mode
]; j
++) {
2400 rxdp
= mac_control
->rings
[ring_no
].
2401 rx_blocks
[blk
].rxds
[j
].virt_addr
;
2402 skb
= (struct sk_buff
*)
2403 ((unsigned long) rxdp
->Host_Control
);
2407 if (sp
->rxd_mode
== RXD_MODE_1
) {
2408 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2409 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2411 HEADER_ETHERNET_II_802_3_SIZE
2412 + HEADER_802_2_SIZE
+
2414 PCI_DMA_FROMDEVICE
);
2415 memset(rxdp
, 0, sizeof(struct RxD1
));
2416 } else if(sp
->rxd_mode
== RXD_MODE_3B
) {
2417 ba
= &mac_control
->rings
[ring_no
].
2419 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2420 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2422 PCI_DMA_FROMDEVICE
);
2423 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2424 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2426 PCI_DMA_FROMDEVICE
);
2427 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2428 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2430 PCI_DMA_FROMDEVICE
);
2431 memset(rxdp
, 0, sizeof(struct RxD3
));
2433 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2434 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2435 PCI_DMA_FROMDEVICE
);
2436 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2437 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2439 PCI_DMA_FROMDEVICE
);
2440 pci_unmap_single(sp
->pdev
, (dma_addr_t
)
2441 ((struct RxD3
*)rxdp
)->Buffer2_ptr
, dev
->mtu
,
2442 PCI_DMA_FROMDEVICE
);
2443 memset(rxdp
, 0, sizeof(struct RxD3
));
2446 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
2451 * free_rx_buffers - Frees all Rx buffers
2452 * @sp: device private variable.
2454 * This function will free all Rx buffers allocated by host.
2459 static void free_rx_buffers(struct s2io_nic
*sp
)
2461 struct net_device
*dev
= sp
->dev
;
2462 int i
, blk
= 0, buf_cnt
= 0;
2463 struct mac_info
*mac_control
;
2464 struct config_param
*config
;
2466 mac_control
= &sp
->mac_control
;
2467 config
= &sp
->config
;
2469 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2470 for (blk
= 0; blk
< rx_ring_sz
[i
]; blk
++)
2471 free_rxd_blk(sp
,i
,blk
);
2473 mac_control
->rings
[i
].rx_curr_put_info
.block_index
= 0;
2474 mac_control
->rings
[i
].rx_curr_get_info
.block_index
= 0;
2475 mac_control
->rings
[i
].rx_curr_put_info
.offset
= 0;
2476 mac_control
->rings
[i
].rx_curr_get_info
.offset
= 0;
2477 atomic_set(&sp
->rx_bufs_left
[i
], 0);
2478 DBG_PRINT(INIT_DBG
, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2479 dev
->name
, buf_cnt
, i
);
2484 * s2io_poll - Rx interrupt handler for NAPI support
2485 * @dev : pointer to the device structure.
2486 * @budget : The number of packets that were budgeted to be processed
2487 * during one pass through the 'Poll" function.
2489 * Comes into picture only if NAPI support has been incorporated. It does
2490 * the same thing that rx_intr_handler does, but not in a interrupt context
2491 * also It will process only a given number of packets.
2493 * 0 on success and 1 if there are No Rx packets to be processed.
2496 static int s2io_poll(struct net_device
*dev
, int *budget
)
2498 struct s2io_nic
*nic
= dev
->priv
;
2499 int pkt_cnt
= 0, org_pkts_to_process
;
2500 struct mac_info
*mac_control
;
2501 struct config_param
*config
;
2502 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2505 atomic_inc(&nic
->isr_cnt
);
2506 mac_control
= &nic
->mac_control
;
2507 config
= &nic
->config
;
2509 nic
->pkts_to_process
= *budget
;
2510 if (nic
->pkts_to_process
> dev
->quota
)
2511 nic
->pkts_to_process
= dev
->quota
;
2512 org_pkts_to_process
= nic
->pkts_to_process
;
2514 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
2515 readl(&bar0
->rx_traffic_int
);
2517 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2518 rx_intr_handler(&mac_control
->rings
[i
]);
2519 pkt_cnt
= org_pkts_to_process
- nic
->pkts_to_process
;
2520 if (!nic
->pkts_to_process
) {
2521 /* Quota for the current iteration has been met */
2528 dev
->quota
-= pkt_cnt
;
2530 netif_rx_complete(dev
);
2532 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2533 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2534 DBG_PRINT(ERR_DBG
, "%s:Out of memory", dev
->name
);
2535 DBG_PRINT(ERR_DBG
, " in Rx Poll!!\n");
2539 /* Re enable the Rx interrupts. */
2540 writeq(0x0, &bar0
->rx_traffic_mask
);
2541 readl(&bar0
->rx_traffic_mask
);
2542 atomic_dec(&nic
->isr_cnt
);
2546 dev
->quota
-= pkt_cnt
;
2549 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2550 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2551 DBG_PRINT(ERR_DBG
, "%s:Out of memory", dev
->name
);
2552 DBG_PRINT(ERR_DBG
, " in Rx Poll!!\n");
2556 atomic_dec(&nic
->isr_cnt
);
2560 #ifdef CONFIG_NET_POLL_CONTROLLER
2562 * s2io_netpoll - netpoll event handler entry point
2563 * @dev : pointer to the device structure.
2565 * This function will be called by upper layer to check for events on the
2566 * interface in situations where interrupts are disabled. It is used for
2567 * specific in-kernel networking tasks, such as remote consoles and kernel
2568 * debugging over the network (example netdump in RedHat).
2570 static void s2io_netpoll(struct net_device
*dev
)
2572 struct s2io_nic
*nic
= dev
->priv
;
2573 struct mac_info
*mac_control
;
2574 struct config_param
*config
;
2575 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
2576 u64 val64
= 0xFFFFFFFFFFFFFFFFULL
;
2579 disable_irq(dev
->irq
);
2581 atomic_inc(&nic
->isr_cnt
);
2582 mac_control
= &nic
->mac_control
;
2583 config
= &nic
->config
;
2585 writeq(val64
, &bar0
->rx_traffic_int
);
2586 writeq(val64
, &bar0
->tx_traffic_int
);
2588 /* we need to free up the transmitted skbufs or else netpoll will
2589 * run out of skbs and will fail and eventually netpoll application such
2590 * as netdump will fail.
2592 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
2593 tx_intr_handler(&mac_control
->fifos
[i
]);
2595 /* check for received packet and indicate up to network */
2596 for (i
= 0; i
< config
->rx_ring_num
; i
++)
2597 rx_intr_handler(&mac_control
->rings
[i
]);
2599 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
2600 if (fill_rx_buffers(nic
, i
) == -ENOMEM
) {
2601 DBG_PRINT(ERR_DBG
, "%s:Out of memory", dev
->name
);
2602 DBG_PRINT(ERR_DBG
, " in Rx Netpoll!!\n");
2606 atomic_dec(&nic
->isr_cnt
);
2607 enable_irq(dev
->irq
);
2613 * rx_intr_handler - Rx interrupt handler
2614 * @nic: device private variable.
2616 * If the interrupt is because of a received frame or if the
2617 * receive ring contains fresh as yet un-processed frames,this function is
2618 * called. It picks out the RxD at which place the last Rx processing had
2619 * stopped and sends the skb to the OSM's Rx handler and then increments
2624 static void rx_intr_handler(struct ring_info
*ring_data
)
2626 struct s2io_nic
*nic
= ring_data
->nic
;
2627 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2628 int get_block
, put_block
, put_offset
;
2629 struct rx_curr_get_info get_info
, put_info
;
2631 struct sk_buff
*skb
;
2635 spin_lock(&nic
->rx_lock
);
2636 if (atomic_read(&nic
->card_state
) == CARD_DOWN
) {
2637 DBG_PRINT(INTR_DBG
, "%s: %s going down for reset\n",
2638 __FUNCTION__
, dev
->name
);
2639 spin_unlock(&nic
->rx_lock
);
2643 get_info
= ring_data
->rx_curr_get_info
;
2644 get_block
= get_info
.block_index
;
2645 memcpy(&put_info
, &ring_data
->rx_curr_put_info
, sizeof(put_info
));
2646 put_block
= put_info
.block_index
;
2647 rxdp
= ring_data
->rx_blocks
[get_block
].rxds
[get_info
.offset
].virt_addr
;
2649 spin_lock(&nic
->put_lock
);
2650 put_offset
= ring_data
->put_pos
;
2651 spin_unlock(&nic
->put_lock
);
2653 put_offset
= ring_data
->put_pos
;
2655 while (RXD_IS_UP2DT(rxdp
)) {
2657 * If your are next to put index then it's
2658 * FIFO full condition
2660 if ((get_block
== put_block
) &&
2661 (get_info
.offset
+ 1) == put_info
.offset
) {
2662 DBG_PRINT(INTR_DBG
, "%s: Ring Full\n",dev
->name
);
2665 skb
= (struct sk_buff
*) ((unsigned long)rxdp
->Host_Control
);
2667 DBG_PRINT(ERR_DBG
, "%s: The skb is ",
2669 DBG_PRINT(ERR_DBG
, "Null in Rx Intr\n");
2670 spin_unlock(&nic
->rx_lock
);
2673 if (nic
->rxd_mode
== RXD_MODE_1
) {
2674 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2675 ((struct RxD1
*)rxdp
)->Buffer0_ptr
,
2677 HEADER_ETHERNET_II_802_3_SIZE
+
2680 PCI_DMA_FROMDEVICE
);
2681 } else if (nic
->rxd_mode
== RXD_MODE_3B
) {
2682 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2683 ((struct RxD3
*)rxdp
)->Buffer0_ptr
,
2684 BUF0_LEN
, PCI_DMA_FROMDEVICE
);
2685 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2686 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2688 PCI_DMA_FROMDEVICE
);
2690 pci_dma_sync_single_for_cpu(nic
->pdev
, (dma_addr_t
)
2691 ((struct RxD3
*)rxdp
)->Buffer0_ptr
, BUF0_LEN
,
2692 PCI_DMA_FROMDEVICE
);
2693 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2694 ((struct RxD3
*)rxdp
)->Buffer1_ptr
,
2696 PCI_DMA_FROMDEVICE
);
2697 pci_unmap_single(nic
->pdev
, (dma_addr_t
)
2698 ((struct RxD3
*)rxdp
)->Buffer2_ptr
,
2699 dev
->mtu
, PCI_DMA_FROMDEVICE
);
2701 prefetch(skb
->data
);
2702 rx_osm_handler(ring_data
, rxdp
);
2704 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2705 rxdp
= ring_data
->rx_blocks
[get_block
].
2706 rxds
[get_info
.offset
].virt_addr
;
2707 if (get_info
.offset
== rxd_count
[nic
->rxd_mode
]) {
2708 get_info
.offset
= 0;
2709 ring_data
->rx_curr_get_info
.offset
= get_info
.offset
;
2711 if (get_block
== ring_data
->block_count
)
2713 ring_data
->rx_curr_get_info
.block_index
= get_block
;
2714 rxdp
= ring_data
->rx_blocks
[get_block
].block_virt_addr
;
2717 nic
->pkts_to_process
-= 1;
2718 if ((napi
) && (!nic
->pkts_to_process
))
2721 if ((indicate_max_pkts
) && (pkt_cnt
> indicate_max_pkts
))
2725 /* Clear all LRO sessions before exiting */
2726 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
2727 struct lro
*lro
= &nic
->lro0_n
[i
];
2729 update_L3L4_header(nic
, lro
);
2730 queue_rx_frame(lro
->parent
);
2731 clear_lro_session(lro
);
2736 spin_unlock(&nic
->rx_lock
);
2740 * tx_intr_handler - Transmit interrupt handler
2741 * @nic : device private variable
2743 * If an interrupt was raised to indicate DMA complete of the
2744 * Tx packet, this function is called. It identifies the last TxD
2745 * whose buffer was freed and frees all skbs whose data have already
2746 * DMA'ed into the NICs internal memory.
2751 static void tx_intr_handler(struct fifo_info
*fifo_data
)
2753 struct s2io_nic
*nic
= fifo_data
->nic
;
2754 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
2755 struct tx_curr_get_info get_info
, put_info
;
2756 struct sk_buff
*skb
;
2759 get_info
= fifo_data
->tx_curr_get_info
;
2760 memcpy(&put_info
, &fifo_data
->tx_curr_put_info
, sizeof(put_info
));
2761 txdlp
= (struct TxD
*) fifo_data
->list_info
[get_info
.offset
].
2763 while ((!(txdlp
->Control_1
& TXD_LIST_OWN_XENA
)) &&
2764 (get_info
.offset
!= put_info
.offset
) &&
2765 (txdlp
->Host_Control
)) {
2766 /* Check for TxD errors */
2767 if (txdlp
->Control_1
& TXD_T_CODE
) {
2768 unsigned long long err
;
2769 err
= txdlp
->Control_1
& TXD_T_CODE
;
2771 nic
->mac_control
.stats_info
->sw_stat
.
2774 if ((err
>> 48) == 0xA) {
2775 DBG_PRINT(TX_DBG
, "TxD returned due \
2776 to loss of link\n");
2779 DBG_PRINT(ERR_DBG
, "***TxD error %llx\n", err
);
2783 skb
= s2io_txdl_getskb(fifo_data
, txdlp
, get_info
.offset
);
2785 DBG_PRINT(ERR_DBG
, "%s: Null skb ",
2787 DBG_PRINT(ERR_DBG
, "in Tx Free Intr\n");
2791 /* Updating the statistics block */
2792 nic
->stats
.tx_bytes
+= skb
->len
;
2793 dev_kfree_skb_irq(skb
);
2796 if (get_info
.offset
== get_info
.fifo_len
+ 1)
2797 get_info
.offset
= 0;
2798 txdlp
= (struct TxD
*) fifo_data
->list_info
2799 [get_info
.offset
].list_virt_addr
;
2800 fifo_data
->tx_curr_get_info
.offset
=
2804 spin_lock(&nic
->tx_lock
);
2805 if (netif_queue_stopped(dev
))
2806 netif_wake_queue(dev
);
2807 spin_unlock(&nic
->tx_lock
);
2811 * s2io_mdio_write - Function to write in to MDIO registers
2812 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2813 * @addr : address value
2814 * @value : data value
2815 * @dev : pointer to net_device structure
2817 * This function is used to write values to the MDIO registers
2820 static void s2io_mdio_write(u32 mmd_type
, u64 addr
, u16 value
, struct net_device
*dev
)
2823 struct s2io_nic
*sp
= dev
->priv
;
2824 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2826 //address transaction
2827 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2828 | MDIO_MMD_DEV_ADDR(mmd_type
)
2829 | MDIO_MMS_PRT_ADDR(0x0);
2830 writeq(val64
, &bar0
->mdio_control
);
2831 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2832 writeq(val64
, &bar0
->mdio_control
);
2837 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2838 | MDIO_MMD_DEV_ADDR(mmd_type
)
2839 | MDIO_MMS_PRT_ADDR(0x0)
2840 | MDIO_MDIO_DATA(value
)
2841 | MDIO_OP(MDIO_OP_WRITE_TRANS
);
2842 writeq(val64
, &bar0
->mdio_control
);
2843 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2844 writeq(val64
, &bar0
->mdio_control
);
2848 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2849 | MDIO_MMD_DEV_ADDR(mmd_type
)
2850 | MDIO_MMS_PRT_ADDR(0x0)
2851 | MDIO_OP(MDIO_OP_READ_TRANS
);
2852 writeq(val64
, &bar0
->mdio_control
);
2853 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2854 writeq(val64
, &bar0
->mdio_control
);
2860 * s2io_mdio_read - Function to write in to MDIO registers
2861 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2862 * @addr : address value
2863 * @dev : pointer to net_device structure
2865 * This function is used to read values to the MDIO registers
2868 static u64
s2io_mdio_read(u32 mmd_type
, u64 addr
, struct net_device
*dev
)
2872 struct s2io_nic
*sp
= dev
->priv
;
2873 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
2875 /* address transaction */
2876 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2877 | MDIO_MMD_DEV_ADDR(mmd_type
)
2878 | MDIO_MMS_PRT_ADDR(0x0);
2879 writeq(val64
, &bar0
->mdio_control
);
2880 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2881 writeq(val64
, &bar0
->mdio_control
);
2884 /* Data transaction */
2886 val64
= val64
| MDIO_MMD_INDX_ADDR(addr
)
2887 | MDIO_MMD_DEV_ADDR(mmd_type
)
2888 | MDIO_MMS_PRT_ADDR(0x0)
2889 | MDIO_OP(MDIO_OP_READ_TRANS
);
2890 writeq(val64
, &bar0
->mdio_control
);
2891 val64
= val64
| MDIO_CTRL_START_TRANS(0xE);
2892 writeq(val64
, &bar0
->mdio_control
);
2895 /* Read the value from regs */
2896 rval64
= readq(&bar0
->mdio_control
);
2897 rval64
= rval64
& 0xFFFF0000;
2898 rval64
= rval64
>> 16;
2902 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2903 * @counter : couter value to be updated
2904 * @flag : flag to indicate the status
2905 * @type : counter type
2907 * This function is to check the status of the xpak counters value
2911 static void s2io_chk_xpak_counter(u64
*counter
, u64
* regs_stat
, u32 index
, u16 flag
, u16 type
)
2916 for(i
= 0; i
<index
; i
++)
2921 *counter
= *counter
+ 1;
2922 val64
= *regs_stat
& mask
;
2923 val64
= val64
>> (index
* 0x2);
2930 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
2931 "service. Excessive temperatures may "
2932 "result in premature transceiver "
2936 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
2937 "service Excessive bias currents may "
2938 "indicate imminent laser diode "
2942 DBG_PRINT(ERR_DBG
, "Take Xframe NIC out of "
2943 "service Excessive laser output "
2944 "power may saturate far-end "
2948 DBG_PRINT(ERR_DBG
, "Incorrect XPAK Alarm "
2953 val64
= val64
<< (index
* 0x2);
2954 *regs_stat
= (*regs_stat
& (~mask
)) | (val64
);
2957 *regs_stat
= *regs_stat
& (~mask
);
2962 * s2io_updt_xpak_counter - Function to update the xpak counters
2963 * @dev : pointer to net_device struct
2965 * This function is to upate the status of the xpak counters value
2968 static void s2io_updt_xpak_counter(struct net_device
*dev
)
2976 struct s2io_nic
*sp
= dev
->priv
;
2977 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
2979 /* Check the communication with the MDIO slave */
2982 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
2983 if((val64
== 0xFFFF) || (val64
== 0x0000))
2985 DBG_PRINT(ERR_DBG
, "ERR: MDIO slave access failed - "
2986 "Returned %llx\n", (unsigned long long)val64
);
2990 /* Check for the expecte value of 2040 at PMA address 0x0000 */
2993 DBG_PRINT(ERR_DBG
, "Incorrect value at PMA address 0x0000 - ");
2994 DBG_PRINT(ERR_DBG
, "Returned: %llx- Expected: 0x2040\n",
2995 (unsigned long long)val64
);
2999 /* Loading the DOM register to MDIO register */
3001 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR
, addr
, val16
, dev
);
3002 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3004 /* Reading the Alarm flags */
3007 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3009 flag
= CHECKBIT(val64
, 0x7);
3011 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_transceiver_temp_high
,
3012 &stat_info
->xpak_stat
.xpak_regs_stat
,
3015 if(CHECKBIT(val64
, 0x6))
3016 stat_info
->xpak_stat
.alarm_transceiver_temp_low
++;
3018 flag
= CHECKBIT(val64
, 0x3);
3020 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_bias_current_high
,
3021 &stat_info
->xpak_stat
.xpak_regs_stat
,
3024 if(CHECKBIT(val64
, 0x2))
3025 stat_info
->xpak_stat
.alarm_laser_bias_current_low
++;
3027 flag
= CHECKBIT(val64
, 0x1);
3029 s2io_chk_xpak_counter(&stat_info
->xpak_stat
.alarm_laser_output_power_high
,
3030 &stat_info
->xpak_stat
.xpak_regs_stat
,
3033 if(CHECKBIT(val64
, 0x0))
3034 stat_info
->xpak_stat
.alarm_laser_output_power_low
++;
3036 /* Reading the Warning flags */
3039 val64
= s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR
, addr
, dev
);
3041 if(CHECKBIT(val64
, 0x7))
3042 stat_info
->xpak_stat
.warn_transceiver_temp_high
++;
3044 if(CHECKBIT(val64
, 0x6))
3045 stat_info
->xpak_stat
.warn_transceiver_temp_low
++;
3047 if(CHECKBIT(val64
, 0x3))
3048 stat_info
->xpak_stat
.warn_laser_bias_current_high
++;
3050 if(CHECKBIT(val64
, 0x2))
3051 stat_info
->xpak_stat
.warn_laser_bias_current_low
++;
3053 if(CHECKBIT(val64
, 0x1))
3054 stat_info
->xpak_stat
.warn_laser_output_power_high
++;
3056 if(CHECKBIT(val64
, 0x0))
3057 stat_info
->xpak_stat
.warn_laser_output_power_low
++;
3061 * alarm_intr_handler - Alarm Interrrupt handler
3062 * @nic: device private variable
3063 * Description: If the interrupt was neither because of Rx packet or Tx
3064 * complete, this function is called. If the interrupt was to indicate
3065 * a loss of link, the OSM link status handler is invoked for any other
3066 * alarm interrupt the block that raised the interrupt is displayed
3067 * and a H/W reset is issued.
3072 static void alarm_intr_handler(struct s2io_nic
*nic
)
3074 struct net_device
*dev
= (struct net_device
*) nic
->dev
;
3075 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3076 register u64 val64
= 0, err_reg
= 0;
3079 if (atomic_read(&nic
->card_state
) == CARD_DOWN
)
3081 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
= 0;
3082 /* Handling the XPAK counters update */
3083 if(nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
< 72000) {
3084 /* waiting for an hour */
3085 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
++;
3087 s2io_updt_xpak_counter(dev
);
3088 /* reset the count to zero */
3089 nic
->mac_control
.stats_info
->xpak_stat
.xpak_timer_count
= 0;
3092 /* Handling link status change error Intr */
3093 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
3094 err_reg
= readq(&bar0
->mac_rmac_err_reg
);
3095 writeq(err_reg
, &bar0
->mac_rmac_err_reg
);
3096 if (err_reg
& RMAC_LINK_STATE_CHANGE_INT
) {
3097 schedule_work(&nic
->set_link_task
);
3101 /* Handling Ecc errors */
3102 val64
= readq(&bar0
->mc_err_reg
);
3103 writeq(val64
, &bar0
->mc_err_reg
);
3104 if (val64
& (MC_ERR_REG_ECC_ALL_SNG
| MC_ERR_REG_ECC_ALL_DBL
)) {
3105 if (val64
& MC_ERR_REG_ECC_ALL_DBL
) {
3106 nic
->mac_control
.stats_info
->sw_stat
.
3108 DBG_PRINT(INIT_DBG
, "%s: Device indicates ",
3110 DBG_PRINT(INIT_DBG
, "double ECC error!!\n");
3111 if (nic
->device_type
!= XFRAME_II_DEVICE
) {
3112 /* Reset XframeI only if critical error */
3113 if (val64
& (MC_ERR_REG_MIRI_ECC_DB_ERR_0
|
3114 MC_ERR_REG_MIRI_ECC_DB_ERR_1
)) {
3115 netif_stop_queue(dev
);
3116 schedule_work(&nic
->rst_timer_task
);
3117 nic
->mac_control
.stats_info
->sw_stat
.
3122 nic
->mac_control
.stats_info
->sw_stat
.
3127 /* In case of a serious error, the device will be Reset. */
3128 val64
= readq(&bar0
->serr_source
);
3129 if (val64
& SERR_SOURCE_ANY
) {
3130 nic
->mac_control
.stats_info
->sw_stat
.serious_err_cnt
++;
3131 DBG_PRINT(ERR_DBG
, "%s: Device indicates ", dev
->name
);
3132 DBG_PRINT(ERR_DBG
, "serious error %llx!!\n",
3133 (unsigned long long)val64
);
3134 netif_stop_queue(dev
);
3135 schedule_work(&nic
->rst_timer_task
);
3136 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3140 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3141 * Error occurs, the adapter will be recycled by disabling the
3142 * adapter enable bit and enabling it again after the device
3143 * becomes Quiescent.
3145 val64
= readq(&bar0
->pcc_err_reg
);
3146 writeq(val64
, &bar0
->pcc_err_reg
);
3147 if (val64
& PCC_FB_ECC_DB_ERR
) {
3148 u64 ac
= readq(&bar0
->adapter_control
);
3149 ac
&= ~(ADAPTER_CNTL_EN
);
3150 writeq(ac
, &bar0
->adapter_control
);
3151 ac
= readq(&bar0
->adapter_control
);
3152 schedule_work(&nic
->set_link_task
);
3154 /* Check for data parity error */
3155 val64
= readq(&bar0
->pic_int_status
);
3156 if (val64
& PIC_INT_GPIO
) {
3157 val64
= readq(&bar0
->gpio_int_reg
);
3158 if (val64
& GPIO_INT_REG_DP_ERR_INT
) {
3159 nic
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
3160 schedule_work(&nic
->rst_timer_task
);
3161 nic
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
3165 /* Check for ring full counter */
3166 if (nic
->device_type
& XFRAME_II_DEVICE
) {
3167 val64
= readq(&bar0
->ring_bump_counter1
);
3168 for (i
=0; i
<4; i
++) {
3169 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3170 cnt
>>= 64 - ((i
+1)*16);
3171 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3175 val64
= readq(&bar0
->ring_bump_counter2
);
3176 for (i
=0; i
<4; i
++) {
3177 cnt
= ( val64
& vBIT(0xFFFF,(i
*16),16));
3178 cnt
>>= 64 - ((i
+1)*16);
3179 nic
->mac_control
.stats_info
->sw_stat
.ring_full_cnt
3184 /* Other type of interrupts are not being handled now, TODO */
3188 * wait_for_cmd_complete - waits for a command to complete.
3189 * @sp : private member of the device structure, which is a pointer to the
3190 * s2io_nic structure.
3191 * Description: Function that waits for a command to Write into RMAC
3192 * ADDR DATA registers to be completed and returns either success or
3193 * error depending on whether the command was complete or not.
3195 * SUCCESS on success and FAILURE on failure.
3198 static int wait_for_cmd_complete(void __iomem
*addr
, u64 busy_bit
)
3200 int ret
= FAILURE
, cnt
= 0;
3204 val64
= readq(addr
);
3205 if (!(val64
& busy_bit
)) {
3221 * check_pci_device_id - Checks if the device id is supported
3223 * Description: Function to check if the pci device id is supported by driver.
3224 * Return value: Actual device id if supported else PCI_ANY_ID
3226 static u16
check_pci_device_id(u16 id
)
3229 case PCI_DEVICE_ID_HERC_WIN
:
3230 case PCI_DEVICE_ID_HERC_UNI
:
3231 return XFRAME_II_DEVICE
;
3232 case PCI_DEVICE_ID_S2IO_UNI
:
3233 case PCI_DEVICE_ID_S2IO_WIN
:
3234 return XFRAME_I_DEVICE
;
3241 * s2io_reset - Resets the card.
3242 * @sp : private member of the device structure.
3243 * Description: Function to Reset the card. This function then also
3244 * restores the previously saved PCI configuration space registers as
3245 * the card reset also resets the configuration space.
3250 static void s2io_reset(struct s2io_nic
* sp
)
3252 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3257 DBG_PRINT(INIT_DBG
,"%s - Resetting XFrame card %s\n",
3258 __FUNCTION__
, sp
->dev
->name
);
3260 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3261 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, &(pci_cmd
));
3263 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3265 ret
= pci_set_power_state(sp
->pdev
, 3);
3267 ret
= pci_set_power_state(sp
->pdev
, 0);
3269 DBG_PRINT(ERR_DBG
,"%s PME based SW_Reset failed!\n",
3277 val64
= SW_RESET_ALL
;
3278 writeq(val64
, &bar0
->sw_reset
);
3280 if (strstr(sp
->product_name
, "CX4")) {
3284 for (i
= 0; i
< S2IO_MAX_PCI_CONFIG_SPACE_REINIT
; i
++) {
3286 /* Restore the PCI state saved during initialization. */
3287 pci_restore_state(sp
->pdev
);
3288 pci_read_config_word(sp
->pdev
, 0x2, &val16
);
3289 if (check_pci_device_id(val16
) != (u16
)PCI_ANY_ID
)
3294 if (check_pci_device_id(val16
) == (u16
)PCI_ANY_ID
) {
3295 DBG_PRINT(ERR_DBG
,"%s SW_Reset failed!\n", __FUNCTION__
);
3298 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
, pci_cmd
);
3302 /* Set swapper to enable I/O register access */
3303 s2io_set_swapper(sp
);
3305 /* Restore the MSIX table entries from local variables */
3306 restore_xmsi_data(sp
);
3308 /* Clear certain PCI/PCI-X fields after reset */
3309 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3310 /* Clear "detected parity error" bit */
3311 pci_write_config_word(sp
->pdev
, PCI_STATUS
, 0x8000);
3313 /* Clearing PCIX Ecc status register */
3314 pci_write_config_dword(sp
->pdev
, 0x68, 0x7C);
3316 /* Clearing PCI_STATUS error reflected here */
3317 writeq(BIT(62), &bar0
->txpic_int_reg
);
3320 /* Reset device statistics maintained by OS */
3321 memset(&sp
->stats
, 0, sizeof (struct net_device_stats
));
3323 /* SXE-002: Configure link and activity LED to turn it off */
3324 subid
= sp
->pdev
->subsystem_device
;
3325 if (((subid
& 0xFF) >= 0x07) &&
3326 (sp
->device_type
== XFRAME_I_DEVICE
)) {
3327 val64
= readq(&bar0
->gpio_control
);
3328 val64
|= 0x0000800000000000ULL
;
3329 writeq(val64
, &bar0
->gpio_control
);
3330 val64
= 0x0411040400000000ULL
;
3331 writeq(val64
, (void __iomem
*)bar0
+ 0x2700);
3335 * Clear spurious ECC interrupts that would have occured on
3336 * XFRAME II cards after reset.
3338 if (sp
->device_type
== XFRAME_II_DEVICE
) {
3339 val64
= readq(&bar0
->pcc_err_reg
);
3340 writeq(val64
, &bar0
->pcc_err_reg
);
3343 sp
->device_enabled_once
= FALSE
;
3347 * s2io_set_swapper - to set the swapper controle on the card
3348 * @sp : private member of the device structure,
3349 * pointer to the s2io_nic structure.
3350 * Description: Function to set the swapper control on the card
3351 * correctly depending on the 'endianness' of the system.
3353 * SUCCESS on success and FAILURE on failure.
3356 static int s2io_set_swapper(struct s2io_nic
* sp
)
3358 struct net_device
*dev
= sp
->dev
;
3359 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
3360 u64 val64
, valt
, valr
;
3363 * Set proper endian settings and verify the same by reading
3364 * the PIF Feed-back register.
3367 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3368 if (val64
!= 0x0123456789ABCDEFULL
) {
3370 u64 value
[] = { 0xC30000C3C30000C3ULL
, /* FE=1, SE=1 */
3371 0x8100008181000081ULL
, /* FE=1, SE=0 */
3372 0x4200004242000042ULL
, /* FE=0, SE=1 */
3373 0}; /* FE=0, SE=0 */
3376 writeq(value
[i
], &bar0
->swapper_ctrl
);
3377 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3378 if (val64
== 0x0123456789ABCDEFULL
)
3383 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3385 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3386 (unsigned long long) val64
);
3391 valr
= readq(&bar0
->swapper_ctrl
);
3394 valt
= 0x0123456789ABCDEFULL
;
3395 writeq(valt
, &bar0
->xmsi_address
);
3396 val64
= readq(&bar0
->xmsi_address
);
3400 u64 value
[] = { 0x00C3C30000C3C300ULL
, /* FE=1, SE=1 */
3401 0x0081810000818100ULL
, /* FE=1, SE=0 */
3402 0x0042420000424200ULL
, /* FE=0, SE=1 */
3403 0}; /* FE=0, SE=0 */
3406 writeq((value
[i
] | valr
), &bar0
->swapper_ctrl
);
3407 writeq(valt
, &bar0
->xmsi_address
);
3408 val64
= readq(&bar0
->xmsi_address
);
3414 unsigned long long x
= val64
;
3415 DBG_PRINT(ERR_DBG
, "Write failed, Xmsi_addr ");
3416 DBG_PRINT(ERR_DBG
, "reads:0x%llx\n", x
);
3420 val64
= readq(&bar0
->swapper_ctrl
);
3421 val64
&= 0xFFFF000000000000ULL
;
3425 * The device by default set to a big endian format, so a
3426 * big endian driver need not set anything.
3428 val64
|= (SWAPPER_CTRL_TXP_FE
|
3429 SWAPPER_CTRL_TXP_SE
|
3430 SWAPPER_CTRL_TXD_R_FE
|
3431 SWAPPER_CTRL_TXD_W_FE
|
3432 SWAPPER_CTRL_TXF_R_FE
|
3433 SWAPPER_CTRL_RXD_R_FE
|
3434 SWAPPER_CTRL_RXD_W_FE
|
3435 SWAPPER_CTRL_RXF_W_FE
|
3436 SWAPPER_CTRL_XMSI_FE
|
3437 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3438 if (sp
->intr_type
== INTA
)
3439 val64
|= SWAPPER_CTRL_XMSI_SE
;
3440 writeq(val64
, &bar0
->swapper_ctrl
);
3443 * Initially we enable all bits to make it accessible by the
3444 * driver, then we selectively enable only those bits that
3447 val64
|= (SWAPPER_CTRL_TXP_FE
|
3448 SWAPPER_CTRL_TXP_SE
|
3449 SWAPPER_CTRL_TXD_R_FE
|
3450 SWAPPER_CTRL_TXD_R_SE
|
3451 SWAPPER_CTRL_TXD_W_FE
|
3452 SWAPPER_CTRL_TXD_W_SE
|
3453 SWAPPER_CTRL_TXF_R_FE
|
3454 SWAPPER_CTRL_RXD_R_FE
|
3455 SWAPPER_CTRL_RXD_R_SE
|
3456 SWAPPER_CTRL_RXD_W_FE
|
3457 SWAPPER_CTRL_RXD_W_SE
|
3458 SWAPPER_CTRL_RXF_W_FE
|
3459 SWAPPER_CTRL_XMSI_FE
|
3460 SWAPPER_CTRL_STATS_FE
| SWAPPER_CTRL_STATS_SE
);
3461 if (sp
->intr_type
== INTA
)
3462 val64
|= SWAPPER_CTRL_XMSI_SE
;
3463 writeq(val64
, &bar0
->swapper_ctrl
);
3465 val64
= readq(&bar0
->swapper_ctrl
);
3468 * Verifying if endian settings are accurate by reading a
3469 * feedback register.
3471 val64
= readq(&bar0
->pif_rd_swapper_fb
);
3472 if (val64
!= 0x0123456789ABCDEFULL
) {
3473 /* Endian settings are incorrect, calls for another dekko. */
3474 DBG_PRINT(ERR_DBG
, "%s: Endian settings are wrong, ",
3476 DBG_PRINT(ERR_DBG
, "feedback read %llx\n",
3477 (unsigned long long) val64
);
3484 static int wait_for_msix_trans(struct s2io_nic
*nic
, int i
)
3486 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3488 int ret
= 0, cnt
= 0;
3491 val64
= readq(&bar0
->xmsi_access
);
3492 if (!(val64
& BIT(15)))
3498 DBG_PRINT(ERR_DBG
, "XMSI # %d Access failed\n", i
);
3505 static void restore_xmsi_data(struct s2io_nic
*nic
)
3507 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3511 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3512 writeq(nic
->msix_info
[i
].addr
, &bar0
->xmsi_address
);
3513 writeq(nic
->msix_info
[i
].data
, &bar0
->xmsi_data
);
3514 val64
= (BIT(7) | BIT(15) | vBIT(i
, 26, 6));
3515 writeq(val64
, &bar0
->xmsi_access
);
3516 if (wait_for_msix_trans(nic
, i
)) {
3517 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3523 static void store_xmsi_data(struct s2io_nic
*nic
)
3525 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3526 u64 val64
, addr
, data
;
3529 /* Store and display */
3530 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3531 val64
= (BIT(15) | vBIT(i
, 26, 6));
3532 writeq(val64
, &bar0
->xmsi_access
);
3533 if (wait_for_msix_trans(nic
, i
)) {
3534 DBG_PRINT(ERR_DBG
, "failed in %s\n", __FUNCTION__
);
3537 addr
= readq(&bar0
->xmsi_address
);
3538 data
= readq(&bar0
->xmsi_data
);
3540 nic
->msix_info
[i
].addr
= addr
;
3541 nic
->msix_info
[i
].data
= data
;
3546 int s2io_enable_msi(struct s2io_nic
*nic
)
3548 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3549 u16 msi_ctrl
, msg_val
;
3550 struct config_param
*config
= &nic
->config
;
3551 struct net_device
*dev
= nic
->dev
;
3552 u64 val64
, tx_mat
, rx_mat
;
3555 val64
= readq(&bar0
->pic_control
);
3557 writeq(val64
, &bar0
->pic_control
);
3559 err
= pci_enable_msi(nic
->pdev
);
3561 DBG_PRINT(ERR_DBG
, "%s: enabling MSI failed\n",
3567 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3568 * for interrupt handling.
3570 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3572 pci_write_config_word(nic
->pdev
, 0x4c, msg_val
);
3573 pci_read_config_word(nic
->pdev
, 0x4c, &msg_val
);
3575 pci_read_config_word(nic
->pdev
, 0x42, &msi_ctrl
);
3577 pci_write_config_word(nic
->pdev
, 0x42, msi_ctrl
);
3579 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3580 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3581 for (i
=0; i
<config
->tx_fifo_num
; i
++) {
3582 tx_mat
|= TX_MAT_SET(i
, 1);
3584 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3586 rx_mat
= readq(&bar0
->rx_mat
);
3587 for (i
=0; i
<config
->rx_ring_num
; i
++) {
3588 rx_mat
|= RX_MAT_SET(i
, 1);
3590 writeq(rx_mat
, &bar0
->rx_mat
);
3592 dev
->irq
= nic
->pdev
->irq
;
3596 static int s2io_enable_msi_x(struct s2io_nic
*nic
)
3598 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
3600 u16 msi_control
; /* Temp variable */
3601 int ret
, i
, j
, msix_indx
= 1;
3603 nic
->entries
= kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
),
3605 if (nic
->entries
== NULL
) {
3606 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n", __FUNCTION__
);
3609 memset(nic
->entries
, 0, MAX_REQUESTED_MSI_X
* sizeof(struct msix_entry
));
3612 kmalloc(MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
),
3614 if (nic
->s2io_entries
== NULL
) {
3615 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n", __FUNCTION__
);
3616 kfree(nic
->entries
);
3619 memset(nic
->s2io_entries
, 0,
3620 MAX_REQUESTED_MSI_X
* sizeof(struct s2io_msix_entry
));
3622 for (i
=0; i
< MAX_REQUESTED_MSI_X
; i
++) {
3623 nic
->entries
[i
].entry
= i
;
3624 nic
->s2io_entries
[i
].entry
= i
;
3625 nic
->s2io_entries
[i
].arg
= NULL
;
3626 nic
->s2io_entries
[i
].in_use
= 0;
3629 tx_mat
= readq(&bar0
->tx_mat0_n
[0]);
3630 for (i
=0; i
<nic
->config
.tx_fifo_num
; i
++, msix_indx
++) {
3631 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3632 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.fifos
[i
];
3633 nic
->s2io_entries
[msix_indx
].type
= MSIX_FIFO_TYPE
;
3634 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3636 writeq(tx_mat
, &bar0
->tx_mat0_n
[0]);
3638 if (!nic
->config
.bimodal
) {
3639 rx_mat
= readq(&bar0
->rx_mat
);
3640 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3641 rx_mat
|= RX_MAT_SET(j
, msix_indx
);
3642 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.rings
[j
];
3643 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3644 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3646 writeq(rx_mat
, &bar0
->rx_mat
);
3648 tx_mat
= readq(&bar0
->tx_mat0_n
[7]);
3649 for (j
=0; j
<nic
->config
.rx_ring_num
; j
++, msix_indx
++) {
3650 tx_mat
|= TX_MAT_SET(i
, msix_indx
);
3651 nic
->s2io_entries
[msix_indx
].arg
= &nic
->mac_control
.rings
[j
];
3652 nic
->s2io_entries
[msix_indx
].type
= MSIX_RING_TYPE
;
3653 nic
->s2io_entries
[msix_indx
].in_use
= MSIX_FLG
;
3655 writeq(tx_mat
, &bar0
->tx_mat0_n
[7]);
3658 nic
->avail_msix_vectors
= 0;
3659 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, MAX_REQUESTED_MSI_X
);
3660 /* We fail init if error or we get less vectors than min required */
3661 if (ret
>= (nic
->config
.tx_fifo_num
+ nic
->config
.rx_ring_num
+ 1)) {
3662 nic
->avail_msix_vectors
= ret
;
3663 ret
= pci_enable_msix(nic
->pdev
, nic
->entries
, ret
);
3666 DBG_PRINT(ERR_DBG
, "%s: Enabling MSIX failed\n", nic
->dev
->name
);
3667 kfree(nic
->entries
);
3668 kfree(nic
->s2io_entries
);
3669 nic
->entries
= NULL
;
3670 nic
->s2io_entries
= NULL
;
3671 nic
->avail_msix_vectors
= 0;
3674 if (!nic
->avail_msix_vectors
)
3675 nic
->avail_msix_vectors
= MAX_REQUESTED_MSI_X
;
3678 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3679 * in the herc NIC. (Temp change, needs to be removed later)
3681 pci_read_config_word(nic
->pdev
, 0x42, &msi_control
);
3682 msi_control
|= 0x1; /* Enable MSI */
3683 pci_write_config_word(nic
->pdev
, 0x42, msi_control
);
3688 /* ********************************************************* *
3689 * Functions defined below concern the OS part of the driver *
3690 * ********************************************************* */
3693 * s2io_open - open entry point of the driver
3694 * @dev : pointer to the device structure.
3696 * This function is the open entry point of the driver. It mainly calls a
3697 * function to allocate Rx buffers and inserts them into the buffer
3698 * descriptors and then enables the Rx part of the NIC.
3700 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3704 static int s2io_open(struct net_device
*dev
)
3706 struct s2io_nic
*sp
= dev
->priv
;
3710 * Make sure you have link off by default every time
3711 * Nic is initialized
3713 netif_carrier_off(dev
);
3714 sp
->last_link_state
= 0;
3716 /* Initialize H/W and enable interrupts */
3717 err
= s2io_card_up(sp
);
3719 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
3721 goto hw_init_failed
;
3724 if (s2io_set_mac_addr(dev
, dev
->dev_addr
) == FAILURE
) {
3725 DBG_PRINT(ERR_DBG
, "Set Mac Address Failed\n");
3728 goto hw_init_failed
;
3731 netif_start_queue(dev
);
3735 if (sp
->intr_type
== MSI_X
) {
3738 if (sp
->s2io_entries
)
3739 kfree(sp
->s2io_entries
);
3745 * s2io_close -close entry point of the driver
3746 * @dev : device pointer.
3748 * This is the stop entry point of the driver. It needs to undo exactly
3749 * whatever was done by the open entry point,thus it's usually referred to
3750 * as the close function.Among other things this function mainly stops the
3751 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3753 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3757 static int s2io_close(struct net_device
*dev
)
3759 struct s2io_nic
*sp
= dev
->priv
;
3761 flush_scheduled_work();
3762 netif_stop_queue(dev
);
3763 /* Reset card, kill tasklet and free Tx and Rx buffers. */
3766 sp
->device_close_flag
= TRUE
; /* Device is shut down. */
3771 * s2io_xmit - Tx entry point of te driver
3772 * @skb : the socket buffer containing the Tx data.
3773 * @dev : device pointer.
3775 * This function is the Tx entry point of the driver. S2IO NIC supports
3776 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3777 * NOTE: when device cant queue the pkt,just the trans_start variable will
3780 * 0 on success & 1 on failure.
3783 static int s2io_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3785 struct s2io_nic
*sp
= dev
->priv
;
3786 u16 frg_cnt
, frg_len
, i
, queue
, queue_len
, put_off
, get_off
;
3789 struct TxFIFO_element __iomem
*tx_fifo
;
3790 unsigned long flags
;
3792 int vlan_priority
= 0;
3793 struct mac_info
*mac_control
;
3794 struct config_param
*config
;
3797 mac_control
= &sp
->mac_control
;
3798 config
= &sp
->config
;
3800 DBG_PRINT(TX_DBG
, "%s: In Neterion Tx routine\n", dev
->name
);
3801 spin_lock_irqsave(&sp
->tx_lock
, flags
);
3802 if (atomic_read(&sp
->card_state
) == CARD_DOWN
) {
3803 DBG_PRINT(TX_DBG
, "%s: Card going down for reset\n",
3805 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3812 /* Get Fifo number to Transmit based on vlan priority */
3813 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3814 vlan_tag
= vlan_tx_tag_get(skb
);
3815 vlan_priority
= vlan_tag
>> 13;
3816 queue
= config
->fifo_mapping
[vlan_priority
];
3819 put_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_put_info
.offset
;
3820 get_off
= (u16
) mac_control
->fifos
[queue
].tx_curr_get_info
.offset
;
3821 txdp
= (struct TxD
*) mac_control
->fifos
[queue
].list_info
[put_off
].
3824 queue_len
= mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1;
3825 /* Avoid "put" pointer going beyond "get" pointer */
3826 if (txdp
->Host_Control
||
3827 ((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
3828 DBG_PRINT(TX_DBG
, "Error in xmit, No free TXDs.\n");
3829 netif_stop_queue(dev
);
3831 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3835 /* A buffer with no data will be dropped */
3837 DBG_PRINT(TX_DBG
, "%s:Buffer has no data..\n", dev
->name
);
3839 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3843 offload_type
= s2io_offload_type(skb
);
3844 if (offload_type
& (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
3845 txdp
->Control_1
|= TXD_TCP_LSO_EN
;
3846 txdp
->Control_1
|= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb
));
3848 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3850 (TXD_TX_CKO_IPV4_EN
| TXD_TX_CKO_TCP_EN
|
3853 txdp
->Control_1
|= TXD_GATHER_CODE_FIRST
;
3854 txdp
->Control_1
|= TXD_LIST_OWN_XENA
;
3855 txdp
->Control_2
|= config
->tx_intr_type
;
3857 if (sp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
3858 txdp
->Control_2
|= TXD_VLAN_ENABLE
;
3859 txdp
->Control_2
|= TXD_VLAN_TAG(vlan_tag
);
3862 frg_len
= skb
->len
- skb
->data_len
;
3863 if (offload_type
== SKB_GSO_UDP
) {
3866 ufo_size
= s2io_udp_mss(skb
);
3868 txdp
->Control_1
|= TXD_UFO_EN
;
3869 txdp
->Control_1
|= TXD_UFO_MSS(ufo_size
);
3870 txdp
->Control_1
|= TXD_BUFFER0_SIZE(8);
3872 sp
->ufo_in_band_v
[put_off
] =
3873 (u64
)skb_shinfo(skb
)->ip6_frag_id
;
3875 sp
->ufo_in_band_v
[put_off
] =
3876 (u64
)skb_shinfo(skb
)->ip6_frag_id
<< 32;
3878 txdp
->Host_Control
= (unsigned long)sp
->ufo_in_band_v
;
3879 txdp
->Buffer_Pointer
= pci_map_single(sp
->pdev
,
3881 sizeof(u64
), PCI_DMA_TODEVICE
);
3885 txdp
->Buffer_Pointer
= pci_map_single
3886 (sp
->pdev
, skb
->data
, frg_len
, PCI_DMA_TODEVICE
);
3887 txdp
->Host_Control
= (unsigned long) skb
;
3888 txdp
->Control_1
|= TXD_BUFFER0_SIZE(frg_len
);
3889 if (offload_type
== SKB_GSO_UDP
)
3890 txdp
->Control_1
|= TXD_UFO_EN
;
3892 frg_cnt
= skb_shinfo(skb
)->nr_frags
;
3893 /* For fragmented SKB. */
3894 for (i
= 0; i
< frg_cnt
; i
++) {
3895 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3896 /* A '0' length fragment will be ignored */
3900 txdp
->Buffer_Pointer
= (u64
) pci_map_page
3901 (sp
->pdev
, frag
->page
, frag
->page_offset
,
3902 frag
->size
, PCI_DMA_TODEVICE
);
3903 txdp
->Control_1
= TXD_BUFFER0_SIZE(frag
->size
);
3904 if (offload_type
== SKB_GSO_UDP
)
3905 txdp
->Control_1
|= TXD_UFO_EN
;
3907 txdp
->Control_1
|= TXD_GATHER_CODE_LAST
;
3909 if (offload_type
== SKB_GSO_UDP
)
3910 frg_cnt
++; /* as Txd0 was used for inband header */
3912 tx_fifo
= mac_control
->tx_FIFO_start
[queue
];
3913 val64
= mac_control
->fifos
[queue
].list_info
[put_off
].list_phy_addr
;
3914 writeq(val64
, &tx_fifo
->TxDL_Pointer
);
3916 val64
= (TX_FIFO_LAST_TXD_NUM(frg_cnt
) | TX_FIFO_FIRST_LIST
|
3919 val64
|= TX_FIFO_SPECIAL_FUNC
;
3921 writeq(val64
, &tx_fifo
->List_Control
);
3926 if (put_off
== mac_control
->fifos
[queue
].tx_curr_put_info
.fifo_len
+ 1)
3928 mac_control
->fifos
[queue
].tx_curr_put_info
.offset
= put_off
;
3930 /* Avoid "put" pointer going beyond "get" pointer */
3931 if (((put_off
+1) == queue_len
? 0 : (put_off
+1)) == get_off
) {
3932 sp
->mac_control
.stats_info
->sw_stat
.fifo_full_cnt
++;
3934 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3936 netif_stop_queue(dev
);
3939 dev
->trans_start
= jiffies
;
3940 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
3946 s2io_alarm_handle(unsigned long data
)
3948 struct s2io_nic
*sp
= (struct s2io_nic
*)data
;
3950 alarm_intr_handler(sp
);
3951 mod_timer(&sp
->alarm_timer
, jiffies
+ HZ
/ 2);
3954 static int s2io_chk_rx_buffers(struct s2io_nic
*sp
, int rng_n
)
3956 int rxb_size
, level
;
3959 rxb_size
= atomic_read(&sp
->rx_bufs_left
[rng_n
]);
3960 level
= rx_buffer_level(sp
, rxb_size
, rng_n
);
3962 if ((level
== PANIC
) && (!TASKLET_IN_USE
)) {
3964 DBG_PRINT(INTR_DBG
, "%s: Rx BD hit ", __FUNCTION__
);
3965 DBG_PRINT(INTR_DBG
, "PANIC levels\n");
3966 if ((ret
= fill_rx_buffers(sp
, rng_n
)) == -ENOMEM
) {
3967 DBG_PRINT(ERR_DBG
, "Out of memory in %s",
3969 clear_bit(0, (&sp
->tasklet_status
));
3972 clear_bit(0, (&sp
->tasklet_status
));
3973 } else if (level
== LOW
)
3974 tasklet_schedule(&sp
->task
);
3976 } else if (fill_rx_buffers(sp
, rng_n
) == -ENOMEM
) {
3977 DBG_PRINT(ERR_DBG
, "%s:Out of memory", sp
->dev
->name
);
3978 DBG_PRINT(ERR_DBG
, " in Rx Intr!!\n");
3983 static irqreturn_t
s2io_msi_handle(int irq
, void *dev_id
)
3985 struct net_device
*dev
= (struct net_device
*) dev_id
;
3986 struct s2io_nic
*sp
= dev
->priv
;
3988 struct mac_info
*mac_control
;
3989 struct config_param
*config
;
3991 atomic_inc(&sp
->isr_cnt
);
3992 mac_control
= &sp
->mac_control
;
3993 config
= &sp
->config
;
3994 DBG_PRINT(INTR_DBG
, "%s: MSI handler\n", __FUNCTION__
);
3996 /* If Intr is because of Rx Traffic */
3997 for (i
= 0; i
< config
->rx_ring_num
; i
++)
3998 rx_intr_handler(&mac_control
->rings
[i
]);
4000 /* If Intr is because of Tx Traffic */
4001 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4002 tx_intr_handler(&mac_control
->fifos
[i
]);
4005 * If the Rx buffer count is below the panic threshold then
4006 * reallocate the buffers from the interrupt handler itself,
4007 * else schedule a tasklet to reallocate the buffers.
4009 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4010 s2io_chk_rx_buffers(sp
, i
);
4012 atomic_dec(&sp
->isr_cnt
);
4016 static irqreturn_t
s2io_msix_ring_handle(int irq
, void *dev_id
)
4018 struct ring_info
*ring
= (struct ring_info
*)dev_id
;
4019 struct s2io_nic
*sp
= ring
->nic
;
4021 atomic_inc(&sp
->isr_cnt
);
4023 rx_intr_handler(ring
);
4024 s2io_chk_rx_buffers(sp
, ring
->ring_no
);
4026 atomic_dec(&sp
->isr_cnt
);
4030 static irqreturn_t
s2io_msix_fifo_handle(int irq
, void *dev_id
)
4032 struct fifo_info
*fifo
= (struct fifo_info
*)dev_id
;
4033 struct s2io_nic
*sp
= fifo
->nic
;
4035 atomic_inc(&sp
->isr_cnt
);
4036 tx_intr_handler(fifo
);
4037 atomic_dec(&sp
->isr_cnt
);
4040 static void s2io_txpic_intr_handle(struct s2io_nic
*sp
)
4042 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4045 val64
= readq(&bar0
->pic_int_status
);
4046 if (val64
& PIC_INT_GPIO
) {
4047 val64
= readq(&bar0
->gpio_int_reg
);
4048 if ((val64
& GPIO_INT_REG_LINK_DOWN
) &&
4049 (val64
& GPIO_INT_REG_LINK_UP
)) {
4051 * This is unstable state so clear both up/down
4052 * interrupt and adapter to re-evaluate the link state.
4054 val64
|= GPIO_INT_REG_LINK_DOWN
;
4055 val64
|= GPIO_INT_REG_LINK_UP
;
4056 writeq(val64
, &bar0
->gpio_int_reg
);
4057 val64
= readq(&bar0
->gpio_int_mask
);
4058 val64
&= ~(GPIO_INT_MASK_LINK_UP
|
4059 GPIO_INT_MASK_LINK_DOWN
);
4060 writeq(val64
, &bar0
->gpio_int_mask
);
4062 else if (val64
& GPIO_INT_REG_LINK_UP
) {
4063 val64
= readq(&bar0
->adapter_status
);
4064 /* Enable Adapter */
4065 val64
= readq(&bar0
->adapter_control
);
4066 val64
|= ADAPTER_CNTL_EN
;
4067 writeq(val64
, &bar0
->adapter_control
);
4068 val64
|= ADAPTER_LED_ON
;
4069 writeq(val64
, &bar0
->adapter_control
);
4070 if (!sp
->device_enabled_once
)
4071 sp
->device_enabled_once
= 1;
4073 s2io_link(sp
, LINK_UP
);
4075 * unmask link down interrupt and mask link-up
4078 val64
= readq(&bar0
->gpio_int_mask
);
4079 val64
&= ~GPIO_INT_MASK_LINK_DOWN
;
4080 val64
|= GPIO_INT_MASK_LINK_UP
;
4081 writeq(val64
, &bar0
->gpio_int_mask
);
4083 }else if (val64
& GPIO_INT_REG_LINK_DOWN
) {
4084 val64
= readq(&bar0
->adapter_status
);
4085 s2io_link(sp
, LINK_DOWN
);
4086 /* Link is down so unmaks link up interrupt */
4087 val64
= readq(&bar0
->gpio_int_mask
);
4088 val64
&= ~GPIO_INT_MASK_LINK_UP
;
4089 val64
|= GPIO_INT_MASK_LINK_DOWN
;
4090 writeq(val64
, &bar0
->gpio_int_mask
);
4093 val64
= readq(&bar0
->gpio_int_mask
);
4097 * s2io_isr - ISR handler of the device .
4098 * @irq: the irq of the device.
4099 * @dev_id: a void pointer to the dev structure of the NIC.
4100 * Description: This function is the ISR handler of the device. It
4101 * identifies the reason for the interrupt and calls the relevant
4102 * service routines. As a contongency measure, this ISR allocates the
4103 * recv buffers, if their numbers are below the panic value which is
4104 * presently set to 25% of the original number of rcv buffers allocated.
4106 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4107 * IRQ_NONE: will be returned if interrupt is not from our device
4109 static irqreturn_t
s2io_isr(int irq
, void *dev_id
)
4111 struct net_device
*dev
= (struct net_device
*) dev_id
;
4112 struct s2io_nic
*sp
= dev
->priv
;
4113 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4116 struct mac_info
*mac_control
;
4117 struct config_param
*config
;
4119 atomic_inc(&sp
->isr_cnt
);
4120 mac_control
= &sp
->mac_control
;
4121 config
= &sp
->config
;
4124 * Identify the cause for interrupt and call the appropriate
4125 * interrupt handler. Causes for the interrupt could be;
4129 * 4. Error in any functional blocks of the NIC.
4131 reason
= readq(&bar0
->general_int_status
);
4134 /* The interrupt was not raised by us. */
4135 atomic_dec(&sp
->isr_cnt
);
4138 else if (unlikely(reason
== S2IO_MINUS_ONE
) ) {
4139 /* Disable device and get out */
4140 atomic_dec(&sp
->isr_cnt
);
4145 if (reason
& GEN_INTR_RXTRAFFIC
) {
4146 if ( likely ( netif_rx_schedule_prep(dev
)) ) {
4147 __netif_rx_schedule(dev
);
4148 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_mask
);
4151 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4155 * Rx handler is called by default, without checking for the
4156 * cause of interrupt.
4157 * rx_traffic_int reg is an R1 register, writing all 1's
4158 * will ensure that the actual interrupt causing bit get's
4159 * cleared and hence a read can be avoided.
4161 if (reason
& GEN_INTR_RXTRAFFIC
)
4162 writeq(S2IO_MINUS_ONE
, &bar0
->rx_traffic_int
);
4164 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
4165 rx_intr_handler(&mac_control
->rings
[i
]);
4170 * tx_traffic_int reg is an R1 register, writing all 1's
4171 * will ensure that the actual interrupt causing bit get's
4172 * cleared and hence a read can be avoided.
4174 if (reason
& GEN_INTR_TXTRAFFIC
)
4175 writeq(S2IO_MINUS_ONE
, &bar0
->tx_traffic_int
);
4177 for (i
= 0; i
< config
->tx_fifo_num
; i
++)
4178 tx_intr_handler(&mac_control
->fifos
[i
]);
4180 if (reason
& GEN_INTR_TXPIC
)
4181 s2io_txpic_intr_handle(sp
);
4183 * If the Rx buffer count is below the panic threshold then
4184 * reallocate the buffers from the interrupt handler itself,
4185 * else schedule a tasklet to reallocate the buffers.
4188 for (i
= 0; i
< config
->rx_ring_num
; i
++)
4189 s2io_chk_rx_buffers(sp
, i
);
4192 writeq(0, &bar0
->general_int_mask
);
4193 readl(&bar0
->general_int_status
);
4195 atomic_dec(&sp
->isr_cnt
);
4202 static void s2io_updt_stats(struct s2io_nic
*sp
)
4204 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4208 if (atomic_read(&sp
->card_state
) == CARD_UP
) {
4209 /* Apprx 30us on a 133 MHz bus */
4210 val64
= SET_UPDT_CLICKS(10) |
4211 STAT_CFG_ONE_SHOT_EN
| STAT_CFG_STAT_EN
;
4212 writeq(val64
, &bar0
->stat_cfg
);
4215 val64
= readq(&bar0
->stat_cfg
);
4216 if (!(val64
& BIT(0)))
4220 break; /* Updt failed */
4223 memset(sp
->mac_control
.stats_info
, 0, sizeof(struct stat_block
));
4228 * s2io_get_stats - Updates the device statistics structure.
4229 * @dev : pointer to the device structure.
4231 * This function updates the device statistics structure in the s2io_nic
4232 * structure and returns a pointer to the same.
4234 * pointer to the updated net_device_stats structure.
4237 static struct net_device_stats
*s2io_get_stats(struct net_device
*dev
)
4239 struct s2io_nic
*sp
= dev
->priv
;
4240 struct mac_info
*mac_control
;
4241 struct config_param
*config
;
4244 mac_control
= &sp
->mac_control
;
4245 config
= &sp
->config
;
4247 /* Configure Stats for immediate updt */
4248 s2io_updt_stats(sp
);
4250 sp
->stats
.tx_packets
=
4251 le32_to_cpu(mac_control
->stats_info
->tmac_frms
);
4252 sp
->stats
.tx_errors
=
4253 le32_to_cpu(mac_control
->stats_info
->tmac_any_err_frms
);
4254 sp
->stats
.rx_errors
=
4255 le64_to_cpu(mac_control
->stats_info
->rmac_drop_frms
);
4256 sp
->stats
.multicast
=
4257 le32_to_cpu(mac_control
->stats_info
->rmac_vld_mcst_frms
);
4258 sp
->stats
.rx_length_errors
=
4259 le64_to_cpu(mac_control
->stats_info
->rmac_long_frms
);
4261 return (&sp
->stats
);
4265 * s2io_set_multicast - entry point for multicast address enable/disable.
4266 * @dev : pointer to the device structure
4268 * This function is a driver entry point which gets called by the kernel
4269 * whenever multicast addresses must be enabled/disabled. This also gets
4270 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4271 * determine, if multicast address must be enabled or if promiscuous mode
4272 * is to be disabled etc.
4277 static void s2io_set_multicast(struct net_device
*dev
)
4280 struct dev_mc_list
*mclist
;
4281 struct s2io_nic
*sp
= dev
->priv
;
4282 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4283 u64 val64
= 0, multi_mac
= 0x010203040506ULL
, mask
=
4285 u64 dis_addr
= 0xffffffffffffULL
, mac_addr
= 0;
4288 if ((dev
->flags
& IFF_ALLMULTI
) && (!sp
->m_cast_flg
)) {
4289 /* Enable all Multicast addresses */
4290 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac
),
4291 &bar0
->rmac_addr_data0_mem
);
4292 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask
),
4293 &bar0
->rmac_addr_data1_mem
);
4294 val64
= RMAC_ADDR_CMD_MEM_WE
|
4295 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4296 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET
);
4297 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4298 /* Wait till command completes */
4299 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4300 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
);
4303 sp
->all_multi_pos
= MAC_MC_ALL_MC_ADDR_OFFSET
;
4304 } else if ((dev
->flags
& IFF_ALLMULTI
) && (sp
->m_cast_flg
)) {
4305 /* Disable all Multicast addresses */
4306 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4307 &bar0
->rmac_addr_data0_mem
);
4308 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4309 &bar0
->rmac_addr_data1_mem
);
4310 val64
= RMAC_ADDR_CMD_MEM_WE
|
4311 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4312 RMAC_ADDR_CMD_MEM_OFFSET(sp
->all_multi_pos
);
4313 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4314 /* Wait till command completes */
4315 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4316 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
);
4319 sp
->all_multi_pos
= 0;
4322 if ((dev
->flags
& IFF_PROMISC
) && (!sp
->promisc_flg
)) {
4323 /* Put the NIC into promiscuous mode */
4324 add
= &bar0
->mac_cfg
;
4325 val64
= readq(&bar0
->mac_cfg
);
4326 val64
|= MAC_CFG_RMAC_PROM_ENABLE
;
4328 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4329 writel((u32
) val64
, add
);
4330 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4331 writel((u32
) (val64
>> 32), (add
+ 4));
4333 val64
= readq(&bar0
->mac_cfg
);
4334 sp
->promisc_flg
= 1;
4335 DBG_PRINT(INFO_DBG
, "%s: entered promiscuous mode\n",
4337 } else if (!(dev
->flags
& IFF_PROMISC
) && (sp
->promisc_flg
)) {
4338 /* Remove the NIC from promiscuous mode */
4339 add
= &bar0
->mac_cfg
;
4340 val64
= readq(&bar0
->mac_cfg
);
4341 val64
&= ~MAC_CFG_RMAC_PROM_ENABLE
;
4343 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4344 writel((u32
) val64
, add
);
4345 writeq(RMAC_CFG_KEY(0x4C0D), &bar0
->rmac_cfg_key
);
4346 writel((u32
) (val64
>> 32), (add
+ 4));
4348 val64
= readq(&bar0
->mac_cfg
);
4349 sp
->promisc_flg
= 0;
4350 DBG_PRINT(INFO_DBG
, "%s: left promiscuous mode\n",
4354 /* Update individual M_CAST address list */
4355 if ((!sp
->m_cast_flg
) && dev
->mc_count
) {
4357 (MAX_ADDRS_SUPPORTED
- MAC_MC_ADDR_START_OFFSET
- 1)) {
4358 DBG_PRINT(ERR_DBG
, "%s: No more Rx filters ",
4360 DBG_PRINT(ERR_DBG
, "can be added, please enable ");
4361 DBG_PRINT(ERR_DBG
, "ALL_MULTI instead\n");
4365 prev_cnt
= sp
->mc_addr_count
;
4366 sp
->mc_addr_count
= dev
->mc_count
;
4368 /* Clear out the previous list of Mc in the H/W. */
4369 for (i
= 0; i
< prev_cnt
; i
++) {
4370 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr
),
4371 &bar0
->rmac_addr_data0_mem
);
4372 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4373 &bar0
->rmac_addr_data1_mem
);
4374 val64
= RMAC_ADDR_CMD_MEM_WE
|
4375 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4376 RMAC_ADDR_CMD_MEM_OFFSET
4377 (MAC_MC_ADDR_START_OFFSET
+ i
);
4378 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4380 /* Wait for command completes */
4381 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4382 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
)) {
4383 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4385 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4390 /* Create the new Rx filter list and update the same in H/W. */
4391 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
4392 i
++, mclist
= mclist
->next
) {
4393 memcpy(sp
->usr_addrs
[i
].addr
, mclist
->dmi_addr
,
4396 for (j
= 0; j
< ETH_ALEN
; j
++) {
4397 mac_addr
|= mclist
->dmi_addr
[j
];
4401 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4402 &bar0
->rmac_addr_data0_mem
);
4403 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4404 &bar0
->rmac_addr_data1_mem
);
4405 val64
= RMAC_ADDR_CMD_MEM_WE
|
4406 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4407 RMAC_ADDR_CMD_MEM_OFFSET
4408 (i
+ MAC_MC_ADDR_START_OFFSET
);
4409 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4411 /* Wait for command completes */
4412 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4413 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
)) {
4414 DBG_PRINT(ERR_DBG
, "%s: Adding ",
4416 DBG_PRINT(ERR_DBG
, "Multicasts failed\n");
4424 * s2io_set_mac_addr - Programs the Xframe mac address
4425 * @dev : pointer to the device structure.
4426 * @addr: a uchar pointer to the new mac address which is to be set.
4427 * Description : This procedure will program the Xframe to receive
4428 * frames with new Mac Address
4429 * Return value: SUCCESS on success and an appropriate (-)ve integer
4430 * as defined in errno.h file on failure.
4433 static int s2io_set_mac_addr(struct net_device
*dev
, u8
* addr
)
4435 struct s2io_nic
*sp
= dev
->priv
;
4436 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4437 register u64 val64
, mac_addr
= 0;
4441 * Set the new MAC address as the new unicast filter and reflect this
4442 * change on the device address registered with the OS. It will be
4445 for (i
= 0; i
< ETH_ALEN
; i
++) {
4447 mac_addr
|= addr
[i
];
4450 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr
),
4451 &bar0
->rmac_addr_data0_mem
);
4454 RMAC_ADDR_CMD_MEM_WE
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
4455 RMAC_ADDR_CMD_MEM_OFFSET(0);
4456 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
4457 /* Wait till command completes */
4458 if (wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
4459 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
)) {
4460 DBG_PRINT(ERR_DBG
, "%s: set_mac_addr failed\n", dev
->name
);
4468 * s2io_ethtool_sset - Sets different link parameters.
4469 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4470 * @info: pointer to the structure with parameters given by ethtool to set
4473 * The function sets different link parameters provided by the user onto
4479 static int s2io_ethtool_sset(struct net_device
*dev
,
4480 struct ethtool_cmd
*info
)
4482 struct s2io_nic
*sp
= dev
->priv
;
4483 if ((info
->autoneg
== AUTONEG_ENABLE
) ||
4484 (info
->speed
!= SPEED_10000
) || (info
->duplex
!= DUPLEX_FULL
))
4487 s2io_close(sp
->dev
);
4495 * s2io_ethtol_gset - Return link specific information.
4496 * @sp : private member of the device structure, pointer to the
4497 * s2io_nic structure.
4498 * @info : pointer to the structure with parameters given by ethtool
4499 * to return link information.
4501 * Returns link specific information like speed, duplex etc.. to ethtool.
4503 * return 0 on success.
4506 static int s2io_ethtool_gset(struct net_device
*dev
, struct ethtool_cmd
*info
)
4508 struct s2io_nic
*sp
= dev
->priv
;
4509 info
->supported
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4510 info
->advertising
= (SUPPORTED_10000baseT_Full
| SUPPORTED_FIBRE
);
4511 info
->port
= PORT_FIBRE
;
4512 /* info->transceiver?? TODO */
4514 if (netif_carrier_ok(sp
->dev
)) {
4515 info
->speed
= 10000;
4516 info
->duplex
= DUPLEX_FULL
;
4522 info
->autoneg
= AUTONEG_DISABLE
;
4527 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4528 * @sp : private member of the device structure, which is a pointer to the
4529 * s2io_nic structure.
4530 * @info : pointer to the structure with parameters given by ethtool to
4531 * return driver information.
4533 * Returns driver specefic information like name, version etc.. to ethtool.
4538 static void s2io_ethtool_gdrvinfo(struct net_device
*dev
,
4539 struct ethtool_drvinfo
*info
)
4541 struct s2io_nic
*sp
= dev
->priv
;
4543 strncpy(info
->driver
, s2io_driver_name
, sizeof(info
->driver
));
4544 strncpy(info
->version
, s2io_driver_version
, sizeof(info
->version
));
4545 strncpy(info
->fw_version
, "", sizeof(info
->fw_version
));
4546 strncpy(info
->bus_info
, pci_name(sp
->pdev
), sizeof(info
->bus_info
));
4547 info
->regdump_len
= XENA_REG_SPACE
;
4548 info
->eedump_len
= XENA_EEPROM_SPACE
;
4549 info
->testinfo_len
= S2IO_TEST_LEN
;
4550 info
->n_stats
= S2IO_STAT_LEN
;
4554 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4555 * @sp: private member of the device structure, which is a pointer to the
4556 * s2io_nic structure.
4557 * @regs : pointer to the structure with parameters given by ethtool for
4558 * dumping the registers.
4559 * @reg_space: The input argumnet into which all the registers are dumped.
4561 * Dumps the entire register space of xFrame NIC into the user given
4567 static void s2io_ethtool_gregs(struct net_device
*dev
,
4568 struct ethtool_regs
*regs
, void *space
)
4572 u8
*reg_space
= (u8
*) space
;
4573 struct s2io_nic
*sp
= dev
->priv
;
4575 regs
->len
= XENA_REG_SPACE
;
4576 regs
->version
= sp
->pdev
->subsystem_device
;
4578 for (i
= 0; i
< regs
->len
; i
+= 8) {
4579 reg
= readq(sp
->bar0
+ i
);
4580 memcpy((reg_space
+ i
), ®
, 8);
4585 * s2io_phy_id - timer function that alternates adapter LED.
4586 * @data : address of the private member of the device structure, which
4587 * is a pointer to the s2io_nic structure, provided as an u32.
4588 * Description: This is actually the timer function that alternates the
4589 * adapter LED bit of the adapter control bit to set/reset every time on
4590 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4591 * once every second.
4593 static void s2io_phy_id(unsigned long data
)
4595 struct s2io_nic
*sp
= (struct s2io_nic
*) data
;
4596 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4600 subid
= sp
->pdev
->subsystem_device
;
4601 if ((sp
->device_type
== XFRAME_II_DEVICE
) ||
4602 ((subid
& 0xFF) >= 0x07)) {
4603 val64
= readq(&bar0
->gpio_control
);
4604 val64
^= GPIO_CTRL_GPIO_0
;
4605 writeq(val64
, &bar0
->gpio_control
);
4607 val64
= readq(&bar0
->adapter_control
);
4608 val64
^= ADAPTER_LED_ON
;
4609 writeq(val64
, &bar0
->adapter_control
);
4612 mod_timer(&sp
->id_timer
, jiffies
+ HZ
/ 2);
4616 * s2io_ethtool_idnic - To physically identify the nic on the system.
4617 * @sp : private member of the device structure, which is a pointer to the
4618 * s2io_nic structure.
4619 * @id : pointer to the structure with identification parameters given by
4621 * Description: Used to physically identify the NIC on the system.
4622 * The Link LED will blink for a time specified by the user for
4624 * NOTE: The Link has to be Up to be able to blink the LED. Hence
4625 * identification is possible only if it's link is up.
4627 * int , returns 0 on success
4630 static int s2io_ethtool_idnic(struct net_device
*dev
, u32 data
)
4632 u64 val64
= 0, last_gpio_ctrl_val
;
4633 struct s2io_nic
*sp
= dev
->priv
;
4634 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4637 subid
= sp
->pdev
->subsystem_device
;
4638 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4639 if ((sp
->device_type
== XFRAME_I_DEVICE
) &&
4640 ((subid
& 0xFF) < 0x07)) {
4641 val64
= readq(&bar0
->adapter_control
);
4642 if (!(val64
& ADAPTER_CNTL_EN
)) {
4644 "Adapter Link down, cannot blink LED\n");
4648 if (sp
->id_timer
.function
== NULL
) {
4649 init_timer(&sp
->id_timer
);
4650 sp
->id_timer
.function
= s2io_phy_id
;
4651 sp
->id_timer
.data
= (unsigned long) sp
;
4653 mod_timer(&sp
->id_timer
, jiffies
);
4655 msleep_interruptible(data
* HZ
);
4657 msleep_interruptible(MAX_FLICKER_TIME
);
4658 del_timer_sync(&sp
->id_timer
);
4660 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp
->device_type
, subid
)) {
4661 writeq(last_gpio_ctrl_val
, &bar0
->gpio_control
);
4662 last_gpio_ctrl_val
= readq(&bar0
->gpio_control
);
4669 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4670 * @sp : private member of the device structure, which is a pointer to the
4671 * s2io_nic structure.
4672 * @ep : pointer to the structure with pause parameters given by ethtool.
4674 * Returns the Pause frame generation and reception capability of the NIC.
4678 static void s2io_ethtool_getpause_data(struct net_device
*dev
,
4679 struct ethtool_pauseparam
*ep
)
4682 struct s2io_nic
*sp
= dev
->priv
;
4683 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4685 val64
= readq(&bar0
->rmac_pause_cfg
);
4686 if (val64
& RMAC_PAUSE_GEN_ENABLE
)
4687 ep
->tx_pause
= TRUE
;
4688 if (val64
& RMAC_PAUSE_RX_ENABLE
)
4689 ep
->rx_pause
= TRUE
;
4690 ep
->autoneg
= FALSE
;
4694 * s2io_ethtool_setpause_data - set/reset pause frame generation.
4695 * @sp : private member of the device structure, which is a pointer to the
4696 * s2io_nic structure.
4697 * @ep : pointer to the structure with pause parameters given by ethtool.
4699 * It can be used to set or reset Pause frame generation or reception
4700 * support of the NIC.
4702 * int, returns 0 on Success
4705 static int s2io_ethtool_setpause_data(struct net_device
*dev
,
4706 struct ethtool_pauseparam
*ep
)
4709 struct s2io_nic
*sp
= dev
->priv
;
4710 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4712 val64
= readq(&bar0
->rmac_pause_cfg
);
4714 val64
|= RMAC_PAUSE_GEN_ENABLE
;
4716 val64
&= ~RMAC_PAUSE_GEN_ENABLE
;
4718 val64
|= RMAC_PAUSE_RX_ENABLE
;
4720 val64
&= ~RMAC_PAUSE_RX_ENABLE
;
4721 writeq(val64
, &bar0
->rmac_pause_cfg
);
4726 * read_eeprom - reads 4 bytes of data from user given offset.
4727 * @sp : private member of the device structure, which is a pointer to the
4728 * s2io_nic structure.
4729 * @off : offset at which the data must be written
4730 * @data : Its an output parameter where the data read at the given
4733 * Will read 4 bytes of data from the user given offset and return the
4735 * NOTE: Will allow to read only part of the EEPROM visible through the
4738 * -1 on failure and 0 on success.
4741 #define S2IO_DEV_ID 5
4742 static int read_eeprom(struct s2io_nic
* sp
, int off
, u64
* data
)
4747 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4749 if (sp
->device_type
== XFRAME_I_DEVICE
) {
4750 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
4751 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ
|
4752 I2C_CONTROL_CNTL_START
;
4753 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
4755 while (exit_cnt
< 5) {
4756 val64
= readq(&bar0
->i2c_control
);
4757 if (I2C_CONTROL_CNTL_END(val64
)) {
4758 *data
= I2C_CONTROL_GET_DATA(val64
);
4767 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4768 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
4769 SPI_CONTROL_BYTECNT(0x3) |
4770 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off
);
4771 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4772 val64
|= SPI_CONTROL_REQ
;
4773 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4774 while (exit_cnt
< 5) {
4775 val64
= readq(&bar0
->spi_control
);
4776 if (val64
& SPI_CONTROL_NACK
) {
4779 } else if (val64
& SPI_CONTROL_DONE
) {
4780 *data
= readq(&bar0
->spi_data
);
4793 * write_eeprom - actually writes the relevant part of the data value.
4794 * @sp : private member of the device structure, which is a pointer to the
4795 * s2io_nic structure.
4796 * @off : offset at which the data must be written
4797 * @data : The data that is to be written
4798 * @cnt : Number of bytes of the data that are actually to be written into
4799 * the Eeprom. (max of 3)
4801 * Actually writes the relevant part of the data value into the Eeprom
4802 * through the I2C bus.
4804 * 0 on success, -1 on failure.
4807 static int write_eeprom(struct s2io_nic
* sp
, int off
, u64 data
, int cnt
)
4809 int exit_cnt
= 0, ret
= -1;
4811 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
4813 if (sp
->device_type
== XFRAME_I_DEVICE
) {
4814 val64
= I2C_CONTROL_DEV_ID(S2IO_DEV_ID
) | I2C_CONTROL_ADDR(off
) |
4815 I2C_CONTROL_BYTE_CNT(cnt
) | I2C_CONTROL_SET_DATA((u32
)data
) |
4816 I2C_CONTROL_CNTL_START
;
4817 SPECIAL_REG_WRITE(val64
, &bar0
->i2c_control
, LF
);
4819 while (exit_cnt
< 5) {
4820 val64
= readq(&bar0
->i2c_control
);
4821 if (I2C_CONTROL_CNTL_END(val64
)) {
4822 if (!(val64
& I2C_CONTROL_NACK
))
4831 if (sp
->device_type
== XFRAME_II_DEVICE
) {
4832 int write_cnt
= (cnt
== 8) ? 0 : cnt
;
4833 writeq(SPI_DATA_WRITE(data
,(cnt
<<3)), &bar0
->spi_data
);
4835 val64
= SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1
|
4836 SPI_CONTROL_BYTECNT(write_cnt
) |
4837 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off
);
4838 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4839 val64
|= SPI_CONTROL_REQ
;
4840 SPECIAL_REG_WRITE(val64
, &bar0
->spi_control
, LF
);
4841 while (exit_cnt
< 5) {
4842 val64
= readq(&bar0
->spi_control
);
4843 if (val64
& SPI_CONTROL_NACK
) {
4846 } else if (val64
& SPI_CONTROL_DONE
) {
4856 static void s2io_vpd_read(struct s2io_nic
*nic
)
4860 int i
=0, cnt
, fail
= 0;
4861 int vpd_addr
= 0x80;
4863 if (nic
->device_type
== XFRAME_II_DEVICE
) {
4864 strcpy(nic
->product_name
, "Xframe II 10GbE network adapter");
4868 strcpy(nic
->product_name
, "Xframe I 10GbE network adapter");
4871 strcpy(nic
->serial_num
, "NOT AVAILABLE");
4873 vpd_data
= kmalloc(256, GFP_KERNEL
);
4877 for (i
= 0; i
< 256; i
+=4 ) {
4878 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 2), i
);
4879 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 2), &data
);
4880 pci_write_config_byte(nic
->pdev
, (vpd_addr
+ 3), 0);
4881 for (cnt
= 0; cnt
<5; cnt
++) {
4883 pci_read_config_byte(nic
->pdev
, (vpd_addr
+ 3), &data
);
4888 DBG_PRINT(ERR_DBG
, "Read of VPD data failed\n");
4892 pci_read_config_dword(nic
->pdev
, (vpd_addr
+ 4),
4893 (u32
*)&vpd_data
[i
]);
4897 /* read serial number of adapter */
4898 for (cnt
= 0; cnt
< 256; cnt
++) {
4899 if ((vpd_data
[cnt
] == 'S') &&
4900 (vpd_data
[cnt
+1] == 'N') &&
4901 (vpd_data
[cnt
+2] < VPD_STRING_LEN
)) {
4902 memset(nic
->serial_num
, 0, VPD_STRING_LEN
);
4903 memcpy(nic
->serial_num
, &vpd_data
[cnt
+ 3],
4910 if ((!fail
) && (vpd_data
[1] < VPD_STRING_LEN
)) {
4911 memset(nic
->product_name
, 0, vpd_data
[1]);
4912 memcpy(nic
->product_name
, &vpd_data
[3], vpd_data
[1]);
4918 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4919 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4920 * @eeprom : pointer to the user level structure provided by ethtool,
4921 * containing all relevant information.
4922 * @data_buf : user defined value to be written into Eeprom.
4923 * Description: Reads the values stored in the Eeprom at given offset
4924 * for a given length. Stores these values int the input argument data
4925 * buffer 'data_buf' and returns these to the caller (ethtool.)
4930 static int s2io_ethtool_geeprom(struct net_device
*dev
,
4931 struct ethtool_eeprom
*eeprom
, u8
* data_buf
)
4935 struct s2io_nic
*sp
= dev
->priv
;
4937 eeprom
->magic
= sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16);
4939 if ((eeprom
->offset
+ eeprom
->len
) > (XENA_EEPROM_SPACE
))
4940 eeprom
->len
= XENA_EEPROM_SPACE
- eeprom
->offset
;
4942 for (i
= 0; i
< eeprom
->len
; i
+= 4) {
4943 if (read_eeprom(sp
, (eeprom
->offset
+ i
), &data
)) {
4944 DBG_PRINT(ERR_DBG
, "Read of EEPROM failed\n");
4948 memcpy((data_buf
+ i
), &valid
, 4);
4954 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4955 * @sp : private member of the device structure, which is a pointer to the
4956 * s2io_nic structure.
4957 * @eeprom : pointer to the user level structure provided by ethtool,
4958 * containing all relevant information.
4959 * @data_buf ; user defined value to be written into Eeprom.
4961 * Tries to write the user provided value in the Eeprom, at the offset
4962 * given by the user.
4964 * 0 on success, -EFAULT on failure.
4967 static int s2io_ethtool_seeprom(struct net_device
*dev
,
4968 struct ethtool_eeprom
*eeprom
,
4971 int len
= eeprom
->len
, cnt
= 0;
4972 u64 valid
= 0, data
;
4973 struct s2io_nic
*sp
= dev
->priv
;
4975 if (eeprom
->magic
!= (sp
->pdev
->vendor
| (sp
->pdev
->device
<< 16))) {
4977 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
4978 DBG_PRINT(ERR_DBG
, "is wrong, Its not 0x%x\n",
4984 data
= (u32
) data_buf
[cnt
] & 0x000000FF;
4986 valid
= (u32
) (data
<< 24);
4990 if (write_eeprom(sp
, (eeprom
->offset
+ cnt
), valid
, 0)) {
4992 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
4994 "write into the specified offset\n");
5005 * s2io_register_test - reads and writes into all clock domains.
5006 * @sp : private member of the device structure, which is a pointer to the
5007 * s2io_nic structure.
5008 * @data : variable that returns the result of each of the test conducted b
5011 * Read and write into all clock domains. The NIC has 3 clock domains,
5012 * see that registers in all the three regions are accessible.
5017 static int s2io_register_test(struct s2io_nic
* sp
, uint64_t * data
)
5019 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5020 u64 val64
= 0, exp_val
;
5023 val64
= readq(&bar0
->pif_rd_swapper_fb
);
5024 if (val64
!= 0x123456789abcdefULL
) {
5026 DBG_PRINT(INFO_DBG
, "Read Test level 1 fails\n");
5029 val64
= readq(&bar0
->rmac_pause_cfg
);
5030 if (val64
!= 0xc000ffff00000000ULL
) {
5032 DBG_PRINT(INFO_DBG
, "Read Test level 2 fails\n");
5035 val64
= readq(&bar0
->rx_queue_cfg
);
5036 if (sp
->device_type
== XFRAME_II_DEVICE
)
5037 exp_val
= 0x0404040404040404ULL
;
5039 exp_val
= 0x0808080808080808ULL
;
5040 if (val64
!= exp_val
) {
5042 DBG_PRINT(INFO_DBG
, "Read Test level 3 fails\n");
5045 val64
= readq(&bar0
->xgxs_efifo_cfg
);
5046 if (val64
!= 0x000000001923141EULL
) {
5048 DBG_PRINT(INFO_DBG
, "Read Test level 4 fails\n");
5051 val64
= 0x5A5A5A5A5A5A5A5AULL
;
5052 writeq(val64
, &bar0
->xmsi_data
);
5053 val64
= readq(&bar0
->xmsi_data
);
5054 if (val64
!= 0x5A5A5A5A5A5A5A5AULL
) {
5056 DBG_PRINT(ERR_DBG
, "Write Test level 1 fails\n");
5059 val64
= 0xA5A5A5A5A5A5A5A5ULL
;
5060 writeq(val64
, &bar0
->xmsi_data
);
5061 val64
= readq(&bar0
->xmsi_data
);
5062 if (val64
!= 0xA5A5A5A5A5A5A5A5ULL
) {
5064 DBG_PRINT(ERR_DBG
, "Write Test level 2 fails\n");
5072 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5073 * @sp : private member of the device structure, which is a pointer to the
5074 * s2io_nic structure.
5075 * @data:variable that returns the result of each of the test conducted by
5078 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5084 static int s2io_eeprom_test(struct s2io_nic
* sp
, uint64_t * data
)
5087 u64 ret_data
, org_4F0
, org_7F0
;
5088 u8 saved_4F0
= 0, saved_7F0
= 0;
5089 struct net_device
*dev
= sp
->dev
;
5091 /* Test Write Error at offset 0 */
5092 /* Note that SPI interface allows write access to all areas
5093 * of EEPROM. Hence doing all negative testing only for Xframe I.
5095 if (sp
->device_type
== XFRAME_I_DEVICE
)
5096 if (!write_eeprom(sp
, 0, 0, 3))
5099 /* Save current values at offsets 0x4F0 and 0x7F0 */
5100 if (!read_eeprom(sp
, 0x4F0, &org_4F0
))
5102 if (!read_eeprom(sp
, 0x7F0, &org_7F0
))
5105 /* Test Write at offset 4f0 */
5106 if (write_eeprom(sp
, 0x4F0, 0x012345, 3))
5108 if (read_eeprom(sp
, 0x4F0, &ret_data
))
5111 if (ret_data
!= 0x012345) {
5112 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x4F0. "
5113 "Data written %llx Data read %llx\n",
5114 dev
->name
, (unsigned long long)0x12345,
5115 (unsigned long long)ret_data
);
5119 /* Reset the EEPROM data go FFFF */
5120 write_eeprom(sp
, 0x4F0, 0xFFFFFF, 3);
5122 /* Test Write Request Error at offset 0x7c */
5123 if (sp
->device_type
== XFRAME_I_DEVICE
)
5124 if (!write_eeprom(sp
, 0x07C, 0, 3))
5127 /* Test Write Request at offset 0x7f0 */
5128 if (write_eeprom(sp
, 0x7F0, 0x012345, 3))
5130 if (read_eeprom(sp
, 0x7F0, &ret_data
))
5133 if (ret_data
!= 0x012345) {
5134 DBG_PRINT(ERR_DBG
, "%s: eeprom test error at offset 0x7F0. "
5135 "Data written %llx Data read %llx\n",
5136 dev
->name
, (unsigned long long)0x12345,
5137 (unsigned long long)ret_data
);
5141 /* Reset the EEPROM data go FFFF */
5142 write_eeprom(sp
, 0x7F0, 0xFFFFFF, 3);
5144 if (sp
->device_type
== XFRAME_I_DEVICE
) {
5145 /* Test Write Error at offset 0x80 */
5146 if (!write_eeprom(sp
, 0x080, 0, 3))
5149 /* Test Write Error at offset 0xfc */
5150 if (!write_eeprom(sp
, 0x0FC, 0, 3))
5153 /* Test Write Error at offset 0x100 */
5154 if (!write_eeprom(sp
, 0x100, 0, 3))
5157 /* Test Write Error at offset 4ec */
5158 if (!write_eeprom(sp
, 0x4EC, 0, 3))
5162 /* Restore values at offsets 0x4F0 and 0x7F0 */
5164 write_eeprom(sp
, 0x4F0, org_4F0
, 3);
5166 write_eeprom(sp
, 0x7F0, org_7F0
, 3);
5173 * s2io_bist_test - invokes the MemBist test of the card .
5174 * @sp : private member of the device structure, which is a pointer to the
5175 * s2io_nic structure.
5176 * @data:variable that returns the result of each of the test conducted by
5179 * This invokes the MemBist test of the card. We give around
5180 * 2 secs time for the Test to complete. If it's still not complete
5181 * within this peiod, we consider that the test failed.
5183 * 0 on success and -1 on failure.
5186 static int s2io_bist_test(struct s2io_nic
* sp
, uint64_t * data
)
5189 int cnt
= 0, ret
= -1;
5191 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5192 bist
|= PCI_BIST_START
;
5193 pci_write_config_word(sp
->pdev
, PCI_BIST
, bist
);
5196 pci_read_config_byte(sp
->pdev
, PCI_BIST
, &bist
);
5197 if (!(bist
& PCI_BIST_START
)) {
5198 *data
= (bist
& PCI_BIST_CODE_MASK
);
5210 * s2io-link_test - verifies the link state of the nic
5211 * @sp ; private member of the device structure, which is a pointer to the
5212 * s2io_nic structure.
5213 * @data: variable that returns the result of each of the test conducted by
5216 * The function verifies the link state of the NIC and updates the input
5217 * argument 'data' appropriately.
5222 static int s2io_link_test(struct s2io_nic
* sp
, uint64_t * data
)
5224 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5227 val64
= readq(&bar0
->adapter_status
);
5228 if(!(LINK_IS_UP(val64
)))
5237 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5238 * @sp - private member of the device structure, which is a pointer to the
5239 * s2io_nic structure.
5240 * @data - variable that returns the result of each of the test
5241 * conducted by the driver.
5243 * This is one of the offline test that tests the read and write
5244 * access to the RldRam chip on the NIC.
5249 static int s2io_rldram_test(struct s2io_nic
* sp
, uint64_t * data
)
5251 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5253 int cnt
, iteration
= 0, test_fail
= 0;
5255 val64
= readq(&bar0
->adapter_control
);
5256 val64
&= ~ADAPTER_ECC_EN
;
5257 writeq(val64
, &bar0
->adapter_control
);
5259 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5260 val64
|= MC_RLDRAM_TEST_MODE
;
5261 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5263 val64
= readq(&bar0
->mc_rldram_mrs
);
5264 val64
|= MC_RLDRAM_QUEUE_SIZE_ENABLE
;
5265 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5267 val64
|= MC_RLDRAM_MRS_ENABLE
;
5268 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_mrs
, UF
);
5270 while (iteration
< 2) {
5271 val64
= 0x55555555aaaa0000ULL
;
5272 if (iteration
== 1) {
5273 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5275 writeq(val64
, &bar0
->mc_rldram_test_d0
);
5277 val64
= 0xaaaa5a5555550000ULL
;
5278 if (iteration
== 1) {
5279 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5281 writeq(val64
, &bar0
->mc_rldram_test_d1
);
5283 val64
= 0x55aaaaaaaa5a0000ULL
;
5284 if (iteration
== 1) {
5285 val64
^= 0xFFFFFFFFFFFF0000ULL
;
5287 writeq(val64
, &bar0
->mc_rldram_test_d2
);
5289 val64
= (u64
) (0x0000003ffffe0100ULL
);
5290 writeq(val64
, &bar0
->mc_rldram_test_add
);
5292 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_WRITE
|
5294 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5296 for (cnt
= 0; cnt
< 5; cnt
++) {
5297 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5298 if (val64
& MC_RLDRAM_TEST_DONE
)
5306 val64
= MC_RLDRAM_TEST_MODE
| MC_RLDRAM_TEST_GO
;
5307 SPECIAL_REG_WRITE(val64
, &bar0
->mc_rldram_test_ctrl
, LF
);
5309 for (cnt
= 0; cnt
< 5; cnt
++) {
5310 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5311 if (val64
& MC_RLDRAM_TEST_DONE
)
5319 val64
= readq(&bar0
->mc_rldram_test_ctrl
);
5320 if (!(val64
& MC_RLDRAM_TEST_PASS
))
5328 /* Bring the adapter out of test mode */
5329 SPECIAL_REG_WRITE(0, &bar0
->mc_rldram_test_ctrl
, LF
);
5335 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5336 * @sp : private member of the device structure, which is a pointer to the
5337 * s2io_nic structure.
5338 * @ethtest : pointer to a ethtool command specific structure that will be
5339 * returned to the user.
5340 * @data : variable that returns the result of each of the test
5341 * conducted by the driver.
5343 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5344 * the health of the card.
5349 static void s2io_ethtool_test(struct net_device
*dev
,
5350 struct ethtool_test
*ethtest
,
5353 struct s2io_nic
*sp
= dev
->priv
;
5354 int orig_state
= netif_running(sp
->dev
);
5356 if (ethtest
->flags
== ETH_TEST_FL_OFFLINE
) {
5357 /* Offline Tests. */
5359 s2io_close(sp
->dev
);
5361 if (s2io_register_test(sp
, &data
[0]))
5362 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5366 if (s2io_rldram_test(sp
, &data
[3]))
5367 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5371 if (s2io_eeprom_test(sp
, &data
[1]))
5372 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5374 if (s2io_bist_test(sp
, &data
[4]))
5375 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5385 "%s: is not up, cannot run test\n",
5394 if (s2io_link_test(sp
, &data
[2]))
5395 ethtest
->flags
|= ETH_TEST_FL_FAILED
;
5404 static void s2io_get_ethtool_stats(struct net_device
*dev
,
5405 struct ethtool_stats
*estats
,
5409 struct s2io_nic
*sp
= dev
->priv
;
5410 struct stat_block
*stat_info
= sp
->mac_control
.stats_info
;
5412 s2io_updt_stats(sp
);
5414 (u64
)le32_to_cpu(stat_info
->tmac_frms_oflow
) << 32 |
5415 le32_to_cpu(stat_info
->tmac_frms
);
5417 (u64
)le32_to_cpu(stat_info
->tmac_data_octets_oflow
) << 32 |
5418 le32_to_cpu(stat_info
->tmac_data_octets
);
5419 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_drop_frms
);
5421 (u64
)le32_to_cpu(stat_info
->tmac_mcst_frms_oflow
) << 32 |
5422 le32_to_cpu(stat_info
->tmac_mcst_frms
);
5424 (u64
)le32_to_cpu(stat_info
->tmac_bcst_frms_oflow
) << 32 |
5425 le32_to_cpu(stat_info
->tmac_bcst_frms
);
5426 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_pause_ctrl_frms
);
5428 (u64
)le32_to_cpu(stat_info
->tmac_ttl_octets_oflow
) << 32 |
5429 le32_to_cpu(stat_info
->tmac_ttl_octets
);
5431 (u64
)le32_to_cpu(stat_info
->tmac_ucst_frms_oflow
) << 32 |
5432 le32_to_cpu(stat_info
->tmac_ucst_frms
);
5434 (u64
)le32_to_cpu(stat_info
->tmac_nucst_frms_oflow
) << 32 |
5435 le32_to_cpu(stat_info
->tmac_nucst_frms
);
5437 (u64
)le32_to_cpu(stat_info
->tmac_any_err_frms_oflow
) << 32 |
5438 le32_to_cpu(stat_info
->tmac_any_err_frms
);
5439 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_ttl_less_fb_octets
);
5440 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_vld_ip_octets
);
5442 (u64
)le32_to_cpu(stat_info
->tmac_vld_ip_oflow
) << 32 |
5443 le32_to_cpu(stat_info
->tmac_vld_ip
);
5445 (u64
)le32_to_cpu(stat_info
->tmac_drop_ip_oflow
) << 32 |
5446 le32_to_cpu(stat_info
->tmac_drop_ip
);
5448 (u64
)le32_to_cpu(stat_info
->tmac_icmp_oflow
) << 32 |
5449 le32_to_cpu(stat_info
->tmac_icmp
);
5451 (u64
)le32_to_cpu(stat_info
->tmac_rst_tcp_oflow
) << 32 |
5452 le32_to_cpu(stat_info
->tmac_rst_tcp
);
5453 tmp_stats
[i
++] = le64_to_cpu(stat_info
->tmac_tcp
);
5454 tmp_stats
[i
++] = (u64
)le32_to_cpu(stat_info
->tmac_udp_oflow
) << 32 |
5455 le32_to_cpu(stat_info
->tmac_udp
);
5457 (u64
)le32_to_cpu(stat_info
->rmac_vld_frms_oflow
) << 32 |
5458 le32_to_cpu(stat_info
->rmac_vld_frms
);
5460 (u64
)le32_to_cpu(stat_info
->rmac_data_octets_oflow
) << 32 |
5461 le32_to_cpu(stat_info
->rmac_data_octets
);
5462 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_fcs_err_frms
);
5463 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_drop_frms
);
5465 (u64
)le32_to_cpu(stat_info
->rmac_vld_mcst_frms_oflow
) << 32 |
5466 le32_to_cpu(stat_info
->rmac_vld_mcst_frms
);
5468 (u64
)le32_to_cpu(stat_info
->rmac_vld_bcst_frms_oflow
) << 32 |
5469 le32_to_cpu(stat_info
->rmac_vld_bcst_frms
);
5470 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_in_rng_len_err_frms
);
5471 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_out_rng_len_err_frms
);
5472 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_long_frms
);
5473 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_pause_ctrl_frms
);
5474 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_unsup_ctrl_frms
);
5476 (u64
)le32_to_cpu(stat_info
->rmac_ttl_octets_oflow
) << 32 |
5477 le32_to_cpu(stat_info
->rmac_ttl_octets
);
5479 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ucst_frms_oflow
)
5480 << 32 | le32_to_cpu(stat_info
->rmac_accepted_ucst_frms
);
5482 (u64
)le32_to_cpu(stat_info
->rmac_accepted_nucst_frms_oflow
)
5483 << 32 | le32_to_cpu(stat_info
->rmac_accepted_nucst_frms
);
5485 (u64
)le32_to_cpu(stat_info
->rmac_discarded_frms_oflow
) << 32 |
5486 le32_to_cpu(stat_info
->rmac_discarded_frms
);
5488 (u64
)le32_to_cpu(stat_info
->rmac_drop_events_oflow
)
5489 << 32 | le32_to_cpu(stat_info
->rmac_drop_events
);
5490 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_less_fb_octets
);
5491 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_frms
);
5493 (u64
)le32_to_cpu(stat_info
->rmac_usized_frms_oflow
) << 32 |
5494 le32_to_cpu(stat_info
->rmac_usized_frms
);
5496 (u64
)le32_to_cpu(stat_info
->rmac_osized_frms_oflow
) << 32 |
5497 le32_to_cpu(stat_info
->rmac_osized_frms
);
5499 (u64
)le32_to_cpu(stat_info
->rmac_frag_frms_oflow
) << 32 |
5500 le32_to_cpu(stat_info
->rmac_frag_frms
);
5502 (u64
)le32_to_cpu(stat_info
->rmac_jabber_frms_oflow
) << 32 |
5503 le32_to_cpu(stat_info
->rmac_jabber_frms
);
5504 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_64_frms
);
5505 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_65_127_frms
);
5506 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_128_255_frms
);
5507 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_256_511_frms
);
5508 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_512_1023_frms
);
5509 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1024_1518_frms
);
5511 (u64
)le32_to_cpu(stat_info
->rmac_ip_oflow
) << 32 |
5512 le32_to_cpu(stat_info
->rmac_ip
);
5513 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ip_octets
);
5514 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_hdr_err_ip
);
5516 (u64
)le32_to_cpu(stat_info
->rmac_drop_ip_oflow
) << 32 |
5517 le32_to_cpu(stat_info
->rmac_drop_ip
);
5519 (u64
)le32_to_cpu(stat_info
->rmac_icmp_oflow
) << 32 |
5520 le32_to_cpu(stat_info
->rmac_icmp
);
5521 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_tcp
);
5523 (u64
)le32_to_cpu(stat_info
->rmac_udp_oflow
) << 32 |
5524 le32_to_cpu(stat_info
->rmac_udp
);
5526 (u64
)le32_to_cpu(stat_info
->rmac_err_drp_udp_oflow
) << 32 |
5527 le32_to_cpu(stat_info
->rmac_err_drp_udp
);
5528 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_err_sym
);
5529 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q0
);
5530 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q1
);
5531 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q2
);
5532 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q3
);
5533 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q4
);
5534 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q5
);
5535 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q6
);
5536 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_frms_q7
);
5537 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q0
);
5538 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q1
);
5539 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q2
);
5540 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q3
);
5541 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q4
);
5542 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q5
);
5543 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q6
);
5544 tmp_stats
[i
++] = le16_to_cpu(stat_info
->rmac_full_q7
);
5546 (u64
)le32_to_cpu(stat_info
->rmac_pause_cnt_oflow
) << 32 |
5547 le32_to_cpu(stat_info
->rmac_pause_cnt
);
5548 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_data_err_cnt
);
5549 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_xgmii_ctrl_err_cnt
);
5551 (u64
)le32_to_cpu(stat_info
->rmac_accepted_ip_oflow
) << 32 |
5552 le32_to_cpu(stat_info
->rmac_accepted_ip
);
5553 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_err_tcp
);
5554 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_req_cnt
);
5555 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_cnt
);
5556 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_rd_req_rtry_cnt
);
5557 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_cnt
);
5558 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_rd_ack_cnt
);
5559 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_req_cnt
);
5560 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_cnt
);
5561 tmp_stats
[i
++] = le32_to_cpu(stat_info
->new_wr_req_rtry_cnt
);
5562 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_rtry_cnt
);
5563 tmp_stats
[i
++] = le32_to_cpu(stat_info
->wr_disc_cnt
);
5564 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rd_rtry_wr_ack_cnt
);
5565 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txp_wr_cnt
);
5566 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_rd_cnt
);
5567 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txd_wr_cnt
);
5568 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_rd_cnt
);
5569 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxd_wr_cnt
);
5570 tmp_stats
[i
++] = le32_to_cpu(stat_info
->txf_rd_cnt
);
5571 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rxf_wr_cnt
);
5572 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_1519_4095_frms
);
5573 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_4096_8191_frms
);
5574 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_8192_max_frms
);
5575 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_ttl_gt_max_frms
);
5576 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_osized_alt_frms
);
5577 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_jabber_alt_frms
);
5578 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_gt_max_alt_frms
);
5579 tmp_stats
[i
++] = le64_to_cpu(stat_info
->rmac_vlan_frms
);
5580 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_len_discard
);
5581 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_fcs_discard
);
5582 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_pf_discard
);
5583 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_da_discard
);
5584 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_red_discard
);
5585 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_rts_discard
);
5586 tmp_stats
[i
++] = le32_to_cpu(stat_info
->rmac_ingm_full_discard
);
5587 tmp_stats
[i
++] = le32_to_cpu(stat_info
->link_fault_cnt
);
5589 tmp_stats
[i
++] = stat_info
->sw_stat
.single_ecc_errs
;
5590 tmp_stats
[i
++] = stat_info
->sw_stat
.double_ecc_errs
;
5591 tmp_stats
[i
++] = stat_info
->sw_stat
.parity_err_cnt
;
5592 tmp_stats
[i
++] = stat_info
->sw_stat
.serious_err_cnt
;
5593 tmp_stats
[i
++] = stat_info
->sw_stat
.soft_reset_cnt
;
5594 tmp_stats
[i
++] = stat_info
->sw_stat
.fifo_full_cnt
;
5595 tmp_stats
[i
++] = stat_info
->sw_stat
.ring_full_cnt
;
5596 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_high
;
5597 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_transceiver_temp_low
;
5598 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_high
;
5599 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_bias_current_low
;
5600 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_high
;
5601 tmp_stats
[i
++] = stat_info
->xpak_stat
.alarm_laser_output_power_low
;
5602 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_high
;
5603 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_transceiver_temp_low
;
5604 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_high
;
5605 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_bias_current_low
;
5606 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_high
;
5607 tmp_stats
[i
++] = stat_info
->xpak_stat
.warn_laser_output_power_low
;
5608 tmp_stats
[i
++] = stat_info
->sw_stat
.clubbed_frms_cnt
;
5609 tmp_stats
[i
++] = stat_info
->sw_stat
.sending_both
;
5610 tmp_stats
[i
++] = stat_info
->sw_stat
.outof_sequence_pkts
;
5611 tmp_stats
[i
++] = stat_info
->sw_stat
.flush_max_pkts
;
5612 if (stat_info
->sw_stat
.num_aggregations
) {
5613 u64 tmp
= stat_info
->sw_stat
.sum_avg_pkts_aggregated
;
5616 * Since 64-bit divide does not work on all platforms,
5617 * do repeated subtraction.
5619 while (tmp
>= stat_info
->sw_stat
.num_aggregations
) {
5620 tmp
-= stat_info
->sw_stat
.num_aggregations
;
5623 tmp_stats
[i
++] = count
;
5629 static int s2io_ethtool_get_regs_len(struct net_device
*dev
)
5631 return (XENA_REG_SPACE
);
5635 static u32
s2io_ethtool_get_rx_csum(struct net_device
* dev
)
5637 struct s2io_nic
*sp
= dev
->priv
;
5639 return (sp
->rx_csum
);
5642 static int s2io_ethtool_set_rx_csum(struct net_device
*dev
, u32 data
)
5644 struct s2io_nic
*sp
= dev
->priv
;
5654 static int s2io_get_eeprom_len(struct net_device
*dev
)
5656 return (XENA_EEPROM_SPACE
);
5659 static int s2io_ethtool_self_test_count(struct net_device
*dev
)
5661 return (S2IO_TEST_LEN
);
5664 static void s2io_ethtool_get_strings(struct net_device
*dev
,
5665 u32 stringset
, u8
* data
)
5667 switch (stringset
) {
5669 memcpy(data
, s2io_gstrings
, S2IO_STRINGS_LEN
);
5672 memcpy(data
, ðtool_stats_keys
,
5673 sizeof(ethtool_stats_keys
));
5676 static int s2io_ethtool_get_stats_count(struct net_device
*dev
)
5678 return (S2IO_STAT_LEN
);
5681 static int s2io_ethtool_op_set_tx_csum(struct net_device
*dev
, u32 data
)
5684 dev
->features
|= NETIF_F_IP_CSUM
;
5686 dev
->features
&= ~NETIF_F_IP_CSUM
;
5691 static u32
s2io_ethtool_op_get_tso(struct net_device
*dev
)
5693 return (dev
->features
& NETIF_F_TSO
) != 0;
5695 static int s2io_ethtool_op_set_tso(struct net_device
*dev
, u32 data
)
5698 dev
->features
|= (NETIF_F_TSO
| NETIF_F_TSO6
);
5700 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
5705 static const struct ethtool_ops netdev_ethtool_ops
= {
5706 .get_settings
= s2io_ethtool_gset
,
5707 .set_settings
= s2io_ethtool_sset
,
5708 .get_drvinfo
= s2io_ethtool_gdrvinfo
,
5709 .get_regs_len
= s2io_ethtool_get_regs_len
,
5710 .get_regs
= s2io_ethtool_gregs
,
5711 .get_link
= ethtool_op_get_link
,
5712 .get_eeprom_len
= s2io_get_eeprom_len
,
5713 .get_eeprom
= s2io_ethtool_geeprom
,
5714 .set_eeprom
= s2io_ethtool_seeprom
,
5715 .get_pauseparam
= s2io_ethtool_getpause_data
,
5716 .set_pauseparam
= s2io_ethtool_setpause_data
,
5717 .get_rx_csum
= s2io_ethtool_get_rx_csum
,
5718 .set_rx_csum
= s2io_ethtool_set_rx_csum
,
5719 .get_tx_csum
= ethtool_op_get_tx_csum
,
5720 .set_tx_csum
= s2io_ethtool_op_set_tx_csum
,
5721 .get_sg
= ethtool_op_get_sg
,
5722 .set_sg
= ethtool_op_set_sg
,
5723 .get_tso
= s2io_ethtool_op_get_tso
,
5724 .set_tso
= s2io_ethtool_op_set_tso
,
5725 .get_ufo
= ethtool_op_get_ufo
,
5726 .set_ufo
= ethtool_op_set_ufo
,
5727 .self_test_count
= s2io_ethtool_self_test_count
,
5728 .self_test
= s2io_ethtool_test
,
5729 .get_strings
= s2io_ethtool_get_strings
,
5730 .phys_id
= s2io_ethtool_idnic
,
5731 .get_stats_count
= s2io_ethtool_get_stats_count
,
5732 .get_ethtool_stats
= s2io_get_ethtool_stats
5736 * s2io_ioctl - Entry point for the Ioctl
5737 * @dev : Device pointer.
5738 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5739 * a proprietary structure used to pass information to the driver.
5740 * @cmd : This is used to distinguish between the different commands that
5741 * can be passed to the IOCTL functions.
5743 * Currently there are no special functionality supported in IOCTL, hence
5744 * function always return EOPNOTSUPPORTED
5747 static int s2io_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
5753 * s2io_change_mtu - entry point to change MTU size for the device.
5754 * @dev : device pointer.
5755 * @new_mtu : the new MTU size for the device.
5756 * Description: A driver entry point to change MTU size for the device.
5757 * Before changing the MTU the device must be stopped.
5759 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5763 static int s2io_change_mtu(struct net_device
*dev
, int new_mtu
)
5765 struct s2io_nic
*sp
= dev
->priv
;
5767 if ((new_mtu
< MIN_MTU
) || (new_mtu
> S2IO_JUMBO_SIZE
)) {
5768 DBG_PRINT(ERR_DBG
, "%s: MTU size is invalid.\n",
5774 if (netif_running(dev
)) {
5776 netif_stop_queue(dev
);
5777 if (s2io_card_up(sp
)) {
5778 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
5781 if (netif_queue_stopped(dev
))
5782 netif_wake_queue(dev
);
5783 } else { /* Device is down */
5784 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
5785 u64 val64
= new_mtu
;
5787 writeq(vBIT(val64
, 2, 14), &bar0
->rmac_max_pyld_len
);
5794 * s2io_tasklet - Bottom half of the ISR.
5795 * @dev_adr : address of the device structure in dma_addr_t format.
5797 * This is the tasklet or the bottom half of the ISR. This is
5798 * an extension of the ISR which is scheduled by the scheduler to be run
5799 * when the load on the CPU is low. All low priority tasks of the ISR can
5800 * be pushed into the tasklet. For now the tasklet is used only to
5801 * replenish the Rx buffers in the Rx buffer descriptors.
5806 static void s2io_tasklet(unsigned long dev_addr
)
5808 struct net_device
*dev
= (struct net_device
*) dev_addr
;
5809 struct s2io_nic
*sp
= dev
->priv
;
5811 struct mac_info
*mac_control
;
5812 struct config_param
*config
;
5814 mac_control
= &sp
->mac_control
;
5815 config
= &sp
->config
;
5817 if (!TASKLET_IN_USE
) {
5818 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
5819 ret
= fill_rx_buffers(sp
, i
);
5820 if (ret
== -ENOMEM
) {
5821 DBG_PRINT(ERR_DBG
, "%s: Out of ",
5823 DBG_PRINT(ERR_DBG
, "memory in tasklet\n");
5825 } else if (ret
== -EFILL
) {
5827 "%s: Rx Ring %d is full\n",
5832 clear_bit(0, (&sp
->tasklet_status
));
5837 * s2io_set_link - Set the LInk status
5838 * @data: long pointer to device private structue
5839 * Description: Sets the link status for the adapter
5842 static void s2io_set_link(struct work_struct
*work
)
5844 struct s2io_nic
*nic
= container_of(work
, struct s2io_nic
, set_link_task
);
5845 struct net_device
*dev
= nic
->dev
;
5846 struct XENA_dev_config __iomem
*bar0
= nic
->bar0
;
5850 if (test_and_set_bit(0, &(nic
->link_state
))) {
5851 /* The card is being reset, no point doing anything */
5855 subid
= nic
->pdev
->subsystem_device
;
5856 if (s2io_link_fault_indication(nic
) == MAC_RMAC_ERR_TIMER
) {
5858 * Allow a small delay for the NICs self initiated
5859 * cleanup to complete.
5864 val64
= readq(&bar0
->adapter_status
);
5865 if (LINK_IS_UP(val64
)) {
5866 if (!(readq(&bar0
->adapter_control
) & ADAPTER_CNTL_EN
)) {
5867 if (verify_xena_quiescence(nic
)) {
5868 val64
= readq(&bar0
->adapter_control
);
5869 val64
|= ADAPTER_CNTL_EN
;
5870 writeq(val64
, &bar0
->adapter_control
);
5871 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
5872 nic
->device_type
, subid
)) {
5873 val64
= readq(&bar0
->gpio_control
);
5874 val64
|= GPIO_CTRL_GPIO_0
;
5875 writeq(val64
, &bar0
->gpio_control
);
5876 val64
= readq(&bar0
->gpio_control
);
5878 val64
|= ADAPTER_LED_ON
;
5879 writeq(val64
, &bar0
->adapter_control
);
5881 nic
->device_enabled_once
= TRUE
;
5883 DBG_PRINT(ERR_DBG
, "%s: Error: ", dev
->name
);
5884 DBG_PRINT(ERR_DBG
, "device is not Quiescent\n");
5885 netif_stop_queue(dev
);
5888 val64
= readq(&bar0
->adapter_status
);
5889 if (!LINK_IS_UP(val64
)) {
5890 DBG_PRINT(ERR_DBG
, "%s:", dev
->name
);
5891 DBG_PRINT(ERR_DBG
, " Link down after enabling ");
5892 DBG_PRINT(ERR_DBG
, "device \n");
5894 s2io_link(nic
, LINK_UP
);
5896 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic
->device_type
,
5898 val64
= readq(&bar0
->gpio_control
);
5899 val64
&= ~GPIO_CTRL_GPIO_0
;
5900 writeq(val64
, &bar0
->gpio_control
);
5901 val64
= readq(&bar0
->gpio_control
);
5903 s2io_link(nic
, LINK_DOWN
);
5905 clear_bit(0, &(nic
->link_state
));
5908 static int set_rxd_buffer_pointer(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
5910 struct sk_buff
**skb
, u64
*temp0
, u64
*temp1
,
5911 u64
*temp2
, int size
)
5913 struct net_device
*dev
= sp
->dev
;
5914 struct sk_buff
*frag_list
;
5916 if ((sp
->rxd_mode
== RXD_MODE_1
) && (rxdp
->Host_Control
== 0)) {
5919 DBG_PRINT(INFO_DBG
, "SKB is not NULL\n");
5921 * As Rx frame are not going to be processed,
5922 * using same mapped address for the Rxd
5925 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
;
5927 *skb
= dev_alloc_skb(size
);
5929 DBG_PRINT(ERR_DBG
, "%s: Out of ", dev
->name
);
5930 DBG_PRINT(ERR_DBG
, "memory to allocate SKBs\n");
5933 /* storing the mapped addr in a temp variable
5934 * such it will be used for next rxd whose
5935 * Host Control is NULL
5937 ((struct RxD1
*)rxdp
)->Buffer0_ptr
= *temp0
=
5938 pci_map_single( sp
->pdev
, (*skb
)->data
,
5939 size
- NET_IP_ALIGN
,
5940 PCI_DMA_FROMDEVICE
);
5941 rxdp
->Host_Control
= (unsigned long) (*skb
);
5943 } else if ((sp
->rxd_mode
== RXD_MODE_3B
) && (rxdp
->Host_Control
== 0)) {
5944 /* Two buffer Mode */
5946 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
5947 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
5948 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
5950 *skb
= dev_alloc_skb(size
);
5952 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb failed\n",
5956 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
5957 pci_map_single(sp
->pdev
, (*skb
)->data
,
5959 PCI_DMA_FROMDEVICE
);
5960 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
5961 pci_map_single( sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
5962 PCI_DMA_FROMDEVICE
);
5963 rxdp
->Host_Control
= (unsigned long) (*skb
);
5965 /* Buffer-1 will be dummy buffer not used */
5966 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
5967 pci_map_single(sp
->pdev
, ba
->ba_1
, BUF1_LEN
,
5968 PCI_DMA_FROMDEVICE
);
5970 } else if ((rxdp
->Host_Control
== 0)) {
5971 /* Three buffer mode */
5973 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
;
5974 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
;
5975 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
;
5977 *skb
= dev_alloc_skb(size
);
5979 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb failed\n",
5983 ((struct RxD3
*)rxdp
)->Buffer0_ptr
= *temp0
=
5984 pci_map_single(sp
->pdev
, ba
->ba_0
, BUF0_LEN
,
5985 PCI_DMA_FROMDEVICE
);
5986 /* Buffer-1 receives L3/L4 headers */
5987 ((struct RxD3
*)rxdp
)->Buffer1_ptr
= *temp1
=
5988 pci_map_single( sp
->pdev
, (*skb
)->data
,
5990 PCI_DMA_FROMDEVICE
);
5992 * skb_shinfo(skb)->frag_list will have L4
5995 skb_shinfo(*skb
)->frag_list
= dev_alloc_skb(dev
->mtu
+
5997 if (skb_shinfo(*skb
)->frag_list
== NULL
) {
5998 DBG_PRINT(ERR_DBG
, "%s: dev_alloc_skb \
5999 failed\n ", dev
->name
);
6002 frag_list
= skb_shinfo(*skb
)->frag_list
;
6003 frag_list
->next
= NULL
;
6005 * Buffer-2 receives L4 data payload
6007 ((struct RxD3
*)rxdp
)->Buffer2_ptr
= *temp2
=
6008 pci_map_single( sp
->pdev
, frag_list
->data
,
6009 dev
->mtu
, PCI_DMA_FROMDEVICE
);
6014 static void set_rxd_buffer_size(struct s2io_nic
*sp
, struct RxD_t
*rxdp
,
6017 struct net_device
*dev
= sp
->dev
;
6018 if (sp
->rxd_mode
== RXD_MODE_1
) {
6019 rxdp
->Control_2
= SET_BUFFER0_SIZE_1( size
- NET_IP_ALIGN
);
6020 } else if (sp
->rxd_mode
== RXD_MODE_3B
) {
6021 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6022 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(1);
6023 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3( dev
->mtu
+ 4);
6025 rxdp
->Control_2
= SET_BUFFER0_SIZE_3(BUF0_LEN
);
6026 rxdp
->Control_2
|= SET_BUFFER1_SIZE_3(l3l4hdr_size
+ 4);
6027 rxdp
->Control_2
|= SET_BUFFER2_SIZE_3(dev
->mtu
);
6031 static int rxd_owner_bit_reset(struct s2io_nic
*sp
)
6033 int i
, j
, k
, blk_cnt
= 0, size
;
6034 struct mac_info
* mac_control
= &sp
->mac_control
;
6035 struct config_param
*config
= &sp
->config
;
6036 struct net_device
*dev
= sp
->dev
;
6037 struct RxD_t
*rxdp
= NULL
;
6038 struct sk_buff
*skb
= NULL
;
6039 struct buffAdd
*ba
= NULL
;
6040 u64 temp0_64
= 0, temp1_64
= 0, temp2_64
= 0;
6042 /* Calculate the size based on ring mode */
6043 size
= dev
->mtu
+ HEADER_ETHERNET_II_802_3_SIZE
+
6044 HEADER_802_2_SIZE
+ HEADER_SNAP_SIZE
;
6045 if (sp
->rxd_mode
== RXD_MODE_1
)
6046 size
+= NET_IP_ALIGN
;
6047 else if (sp
->rxd_mode
== RXD_MODE_3B
)
6048 size
= dev
->mtu
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6050 size
= l3l4hdr_size
+ ALIGN_SIZE
+ BUF0_LEN
+ 4;
6052 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6053 blk_cnt
= config
->rx_cfg
[i
].num_rxd
/
6054 (rxd_count
[sp
->rxd_mode
] +1);
6056 for (j
= 0; j
< blk_cnt
; j
++) {
6057 for (k
= 0; k
< rxd_count
[sp
->rxd_mode
]; k
++) {
6058 rxdp
= mac_control
->rings
[i
].
6059 rx_blocks
[j
].rxds
[k
].virt_addr
;
6060 if(sp
->rxd_mode
>= RXD_MODE_3A
)
6061 ba
= &mac_control
->rings
[i
].ba
[j
][k
];
6062 set_rxd_buffer_pointer(sp
, rxdp
, ba
,
6063 &skb
,(u64
*)&temp0_64
,
6065 (u64
*)&temp2_64
, size
);
6067 set_rxd_buffer_size(sp
, rxdp
, size
);
6069 /* flip the Ownership bit to Hardware */
6070 rxdp
->Control_1
|= RXD_OWN_XENA
;
6078 static int s2io_add_isr(struct s2io_nic
* sp
)
6081 struct net_device
*dev
= sp
->dev
;
6084 if (sp
->intr_type
== MSI
)
6085 ret
= s2io_enable_msi(sp
);
6086 else if (sp
->intr_type
== MSI_X
)
6087 ret
= s2io_enable_msi_x(sp
);
6089 DBG_PRINT(ERR_DBG
, "%s: Defaulting to INTA\n", dev
->name
);
6090 sp
->intr_type
= INTA
;
6093 /* Store the values of the MSIX table in the struct s2io_nic structure */
6094 store_xmsi_data(sp
);
6096 /* After proper initialization of H/W, register ISR */
6097 if (sp
->intr_type
== MSI
) {
6098 err
= request_irq((int) sp
->pdev
->irq
, s2io_msi_handle
,
6099 IRQF_SHARED
, sp
->name
, dev
);
6101 pci_disable_msi(sp
->pdev
);
6102 DBG_PRINT(ERR_DBG
, "%s: MSI registration failed\n",
6107 if (sp
->intr_type
== MSI_X
) {
6110 for (i
=1; (sp
->s2io_entries
[i
].in_use
== MSIX_FLG
); i
++) {
6111 if (sp
->s2io_entries
[i
].type
== MSIX_FIFO_TYPE
) {
6112 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-TX",
6114 err
= request_irq(sp
->entries
[i
].vector
,
6115 s2io_msix_fifo_handle
, 0, sp
->desc
[i
],
6116 sp
->s2io_entries
[i
].arg
);
6117 DBG_PRINT(ERR_DBG
, "%s @ 0x%llx\n", sp
->desc
[i
],
6118 (unsigned long long)sp
->msix_info
[i
].addr
);
6120 sprintf(sp
->desc
[i
], "%s:MSI-X-%d-RX",
6122 err
= request_irq(sp
->entries
[i
].vector
,
6123 s2io_msix_ring_handle
, 0, sp
->desc
[i
],
6124 sp
->s2io_entries
[i
].arg
);
6125 DBG_PRINT(ERR_DBG
, "%s @ 0x%llx\n", sp
->desc
[i
],
6126 (unsigned long long)sp
->msix_info
[i
].addr
);
6129 DBG_PRINT(ERR_DBG
,"%s:MSI-X-%d registration "
6130 "failed\n", dev
->name
, i
);
6131 DBG_PRINT(ERR_DBG
, "Returned: %d\n", err
);
6134 sp
->s2io_entries
[i
].in_use
= MSIX_REGISTERED_SUCCESS
;
6137 if (sp
->intr_type
== INTA
) {
6138 err
= request_irq((int) sp
->pdev
->irq
, s2io_isr
, IRQF_SHARED
,
6141 DBG_PRINT(ERR_DBG
, "%s: ISR registration failed\n",
6148 static void s2io_rem_isr(struct s2io_nic
* sp
)
6151 struct net_device
*dev
= sp
->dev
;
6153 if (sp
->intr_type
== MSI_X
) {
6157 for (i
=1; (sp
->s2io_entries
[i
].in_use
==
6158 MSIX_REGISTERED_SUCCESS
); i
++) {
6159 int vector
= sp
->entries
[i
].vector
;
6160 void *arg
= sp
->s2io_entries
[i
].arg
;
6162 free_irq(vector
, arg
);
6164 pci_read_config_word(sp
->pdev
, 0x42, &msi_control
);
6165 msi_control
&= 0xFFFE; /* Disable MSI */
6166 pci_write_config_word(sp
->pdev
, 0x42, msi_control
);
6168 pci_disable_msix(sp
->pdev
);
6170 free_irq(sp
->pdev
->irq
, dev
);
6171 if (sp
->intr_type
== MSI
) {
6174 pci_disable_msi(sp
->pdev
);
6175 pci_read_config_word(sp
->pdev
, 0x4c, &val
);
6177 pci_write_config_word(sp
->pdev
, 0x4c, val
);
6180 /* Waiting till all Interrupt handlers are complete */
6184 if (!atomic_read(&sp
->isr_cnt
))
6190 static void s2io_card_down(struct s2io_nic
* sp
)
6193 struct XENA_dev_config __iomem
*bar0
= sp
->bar0
;
6194 unsigned long flags
;
6195 register u64 val64
= 0;
6197 del_timer_sync(&sp
->alarm_timer
);
6198 /* If s2io_set_link task is executing, wait till it completes. */
6199 while (test_and_set_bit(0, &(sp
->link_state
))) {
6202 atomic_set(&sp
->card_state
, CARD_DOWN
);
6204 /* disable Tx and Rx traffic on the NIC */
6210 tasklet_kill(&sp
->task
);
6212 /* Check if the device is Quiescent and then Reset the NIC */
6214 /* As per the HW requirement we need to replenish the
6215 * receive buffer to avoid the ring bump. Since there is
6216 * no intention of processing the Rx frame at this pointwe are
6217 * just settting the ownership bit of rxd in Each Rx
6218 * ring to HW and set the appropriate buffer size
6219 * based on the ring mode
6221 rxd_owner_bit_reset(sp
);
6223 val64
= readq(&bar0
->adapter_status
);
6224 if (verify_xena_quiescence(sp
)) {
6225 if(verify_pcc_quiescent(sp
, sp
->device_enabled_once
))
6233 "s2io_close:Device not Quiescent ");
6234 DBG_PRINT(ERR_DBG
, "adaper status reads 0x%llx\n",
6235 (unsigned long long) val64
);
6241 spin_lock_irqsave(&sp
->tx_lock
, flags
);
6242 /* Free all Tx buffers */
6243 free_tx_buffers(sp
);
6244 spin_unlock_irqrestore(&sp
->tx_lock
, flags
);
6246 /* Free all Rx buffers */
6247 spin_lock_irqsave(&sp
->rx_lock
, flags
);
6248 free_rx_buffers(sp
);
6249 spin_unlock_irqrestore(&sp
->rx_lock
, flags
);
6251 clear_bit(0, &(sp
->link_state
));
6254 static int s2io_card_up(struct s2io_nic
* sp
)
6257 struct mac_info
*mac_control
;
6258 struct config_param
*config
;
6259 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6262 /* Initialize the H/W I/O registers */
6263 if (init_nic(sp
) != 0) {
6264 DBG_PRINT(ERR_DBG
, "%s: H/W initialization failed\n",
6271 * Initializing the Rx buffers. For now we are considering only 1
6272 * Rx ring and initializing buffers into 30 Rx blocks
6274 mac_control
= &sp
->mac_control
;
6275 config
= &sp
->config
;
6277 for (i
= 0; i
< config
->rx_ring_num
; i
++) {
6278 if ((ret
= fill_rx_buffers(sp
, i
))) {
6279 DBG_PRINT(ERR_DBG
, "%s: Out of memory in Open\n",
6282 free_rx_buffers(sp
);
6285 DBG_PRINT(INFO_DBG
, "Buf in ring:%d is %d:\n", i
,
6286 atomic_read(&sp
->rx_bufs_left
[i
]));
6288 /* Maintain the state prior to the open */
6289 if (sp
->promisc_flg
)
6290 sp
->promisc_flg
= 0;
6291 if (sp
->m_cast_flg
) {
6293 sp
->all_multi_pos
= 0;
6296 /* Setting its receive mode */
6297 s2io_set_multicast(dev
);
6300 /* Initialize max aggregatable pkts per session based on MTU */
6301 sp
->lro_max_aggr_per_sess
= ((1<<16) - 1) / dev
->mtu
;
6302 /* Check if we can use(if specified) user provided value */
6303 if (lro_max_pkts
< sp
->lro_max_aggr_per_sess
)
6304 sp
->lro_max_aggr_per_sess
= lro_max_pkts
;
6307 /* Enable Rx Traffic and interrupts on the NIC */
6308 if (start_nic(sp
)) {
6309 DBG_PRINT(ERR_DBG
, "%s: Starting NIC failed\n", dev
->name
);
6311 free_rx_buffers(sp
);
6315 /* Add interrupt service routine */
6316 if (s2io_add_isr(sp
) != 0) {
6317 if (sp
->intr_type
== MSI_X
)
6320 free_rx_buffers(sp
);
6324 S2IO_TIMER_CONF(sp
->alarm_timer
, s2io_alarm_handle
, sp
, (HZ
/2));
6326 /* Enable tasklet for the device */
6327 tasklet_init(&sp
->task
, s2io_tasklet
, (unsigned long) dev
);
6329 /* Enable select interrupts */
6330 if (sp
->intr_type
!= INTA
)
6331 en_dis_able_nic_intrs(sp
, ENA_ALL_INTRS
, DISABLE_INTRS
);
6333 interruptible
= TX_TRAFFIC_INTR
| RX_TRAFFIC_INTR
;
6334 interruptible
|= TX_PIC_INTR
| RX_PIC_INTR
;
6335 interruptible
|= TX_MAC_INTR
| RX_MAC_INTR
;
6336 en_dis_able_nic_intrs(sp
, interruptible
, ENABLE_INTRS
);
6340 atomic_set(&sp
->card_state
, CARD_UP
);
6345 * s2io_restart_nic - Resets the NIC.
6346 * @data : long pointer to the device private structure
6348 * This function is scheduled to be run by the s2io_tx_watchdog
6349 * function after 0.5 secs to reset the NIC. The idea is to reduce
6350 * the run time of the watch dog routine which is run holding a
6354 static void s2io_restart_nic(struct work_struct
*work
)
6356 struct s2io_nic
*sp
= container_of(work
, struct s2io_nic
, rst_timer_task
);
6357 struct net_device
*dev
= sp
->dev
;
6360 if (s2io_card_up(sp
)) {
6361 DBG_PRINT(ERR_DBG
, "%s: Device bring up failed\n",
6364 netif_wake_queue(dev
);
6365 DBG_PRINT(ERR_DBG
, "%s: was reset by Tx watchdog timer\n",
6371 * s2io_tx_watchdog - Watchdog for transmit side.
6372 * @dev : Pointer to net device structure
6374 * This function is triggered if the Tx Queue is stopped
6375 * for a pre-defined amount of time when the Interface is still up.
6376 * If the Interface is jammed in such a situation, the hardware is
6377 * reset (by s2io_close) and restarted again (by s2io_open) to
6378 * overcome any problem that might have been caused in the hardware.
6383 static void s2io_tx_watchdog(struct net_device
*dev
)
6385 struct s2io_nic
*sp
= dev
->priv
;
6387 if (netif_carrier_ok(dev
)) {
6388 schedule_work(&sp
->rst_timer_task
);
6389 sp
->mac_control
.stats_info
->sw_stat
.soft_reset_cnt
++;
6394 * rx_osm_handler - To perform some OS related operations on SKB.
6395 * @sp: private member of the device structure,pointer to s2io_nic structure.
6396 * @skb : the socket buffer pointer.
6397 * @len : length of the packet
6398 * @cksum : FCS checksum of the frame.
6399 * @ring_no : the ring from which this RxD was extracted.
6401 * This function is called by the Rx interrupt serivce routine to perform
6402 * some OS related operations on the SKB before passing it to the upper
6403 * layers. It mainly checks if the checksum is OK, if so adds it to the
6404 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6405 * to the upper layer. If the checksum is wrong, it increments the Rx
6406 * packet error count, frees the SKB and returns error.
6408 * SUCCESS on success and -1 on failure.
6410 static int rx_osm_handler(struct ring_info
*ring_data
, struct RxD_t
* rxdp
)
6412 struct s2io_nic
*sp
= ring_data
->nic
;
6413 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6414 struct sk_buff
*skb
= (struct sk_buff
*)
6415 ((unsigned long) rxdp
->Host_Control
);
6416 int ring_no
= ring_data
->ring_no
;
6417 u16 l3_csum
, l4_csum
;
6418 unsigned long long err
= rxdp
->Control_1
& RXD_T_CODE
;
6424 /* Check for parity error */
6426 sp
->mac_control
.stats_info
->sw_stat
.parity_err_cnt
++;
6430 * Drop the packet if bad transfer code. Exception being
6431 * 0x5, which could be due to unsupported IPv6 extension header.
6432 * In this case, we let stack handle the packet.
6433 * Note that in this case, since checksum will be incorrect,
6434 * stack will validate the same.
6436 if (err
&& ((err
>> 48) != 0x5)) {
6437 DBG_PRINT(ERR_DBG
, "%s: Rx error Value: 0x%llx\n",
6439 sp
->stats
.rx_crc_errors
++;
6441 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
6442 rxdp
->Host_Control
= 0;
6447 /* Updating statistics */
6448 rxdp
->Host_Control
= 0;
6450 sp
->stats
.rx_packets
++;
6451 if (sp
->rxd_mode
== RXD_MODE_1
) {
6452 int len
= RXD_GET_BUFFER0_SIZE_1(rxdp
->Control_2
);
6454 sp
->stats
.rx_bytes
+= len
;
6457 } else if (sp
->rxd_mode
>= RXD_MODE_3A
) {
6458 int get_block
= ring_data
->rx_curr_get_info
.block_index
;
6459 int get_off
= ring_data
->rx_curr_get_info
.offset
;
6460 int buf0_len
= RXD_GET_BUFFER0_SIZE_3(rxdp
->Control_2
);
6461 int buf2_len
= RXD_GET_BUFFER2_SIZE_3(rxdp
->Control_2
);
6462 unsigned char *buff
= skb_push(skb
, buf0_len
);
6464 struct buffAdd
*ba
= &ring_data
->ba
[get_block
][get_off
];
6465 sp
->stats
.rx_bytes
+= buf0_len
+ buf2_len
;
6466 memcpy(buff
, ba
->ba_0
, buf0_len
);
6468 if (sp
->rxd_mode
== RXD_MODE_3A
) {
6469 int buf1_len
= RXD_GET_BUFFER1_SIZE_3(rxdp
->Control_2
);
6471 skb_put(skb
, buf1_len
);
6472 skb
->len
+= buf2_len
;
6473 skb
->data_len
+= buf2_len
;
6474 skb_put(skb_shinfo(skb
)->frag_list
, buf2_len
);
6475 sp
->stats
.rx_bytes
+= buf1_len
;
6478 skb_put(skb
, buf2_len
);
6481 if ((rxdp
->Control_1
& TCP_OR_UDP_FRAME
) && ((!sp
->lro
) ||
6482 (sp
->lro
&& (!(rxdp
->Control_1
& RXD_FRAME_IP_FRAG
)))) &&
6484 l3_csum
= RXD_GET_L3_CKSUM(rxdp
->Control_1
);
6485 l4_csum
= RXD_GET_L4_CKSUM(rxdp
->Control_1
);
6486 if ((l3_csum
== L3_CKSUM_OK
) && (l4_csum
== L4_CKSUM_OK
)) {
6488 * NIC verifies if the Checksum of the received
6489 * frame is Ok or not and accordingly returns
6490 * a flag in the RxD.
6492 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6498 ret
= s2io_club_tcp_session(skb
->data
, &tcp
,
6499 &tcp_len
, &lro
, rxdp
, sp
);
6501 case 3: /* Begin anew */
6504 case 1: /* Aggregate */
6506 lro_append_pkt(sp
, lro
,
6510 case 4: /* Flush session */
6512 lro_append_pkt(sp
, lro
,
6514 queue_rx_frame(lro
->parent
);
6515 clear_lro_session(lro
);
6516 sp
->mac_control
.stats_info
->
6517 sw_stat
.flush_max_pkts
++;
6520 case 2: /* Flush both */
6521 lro
->parent
->data_len
=
6523 sp
->mac_control
.stats_info
->
6524 sw_stat
.sending_both
++;
6525 queue_rx_frame(lro
->parent
);
6526 clear_lro_session(lro
);
6528 case 0: /* sessions exceeded */
6529 case -1: /* non-TCP or not
6533 * First pkt in session not
6534 * L3/L4 aggregatable
6539 "%s: Samadhana!!\n",
6546 * Packet with erroneous checksum, let the
6547 * upper layers deal with it.
6549 skb
->ip_summed
= CHECKSUM_NONE
;
6552 skb
->ip_summed
= CHECKSUM_NONE
;
6556 skb
->protocol
= eth_type_trans(skb
, dev
);
6557 if (sp
->vlgrp
&& RXD_GET_VLAN_TAG(rxdp
->Control_2
)) {
6558 /* Queueing the vlan frame to the upper layer */
6560 vlan_hwaccel_receive_skb(skb
, sp
->vlgrp
,
6561 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
6563 vlan_hwaccel_rx(skb
, sp
->vlgrp
,
6564 RXD_GET_VLAN_TAG(rxdp
->Control_2
));
6567 netif_receive_skb(skb
);
6573 queue_rx_frame(skb
);
6575 dev
->last_rx
= jiffies
;
6577 atomic_dec(&sp
->rx_bufs_left
[ring_no
]);
6582 * s2io_link - stops/starts the Tx queue.
6583 * @sp : private member of the device structure, which is a pointer to the
6584 * s2io_nic structure.
6585 * @link : inidicates whether link is UP/DOWN.
6587 * This function stops/starts the Tx queue depending on whether the link
6588 * status of the NIC is is down or up. This is called by the Alarm
6589 * interrupt handler whenever a link change interrupt comes up.
6594 static void s2io_link(struct s2io_nic
* sp
, int link
)
6596 struct net_device
*dev
= (struct net_device
*) sp
->dev
;
6598 if (link
!= sp
->last_link_state
) {
6599 if (link
== LINK_DOWN
) {
6600 DBG_PRINT(ERR_DBG
, "%s: Link down\n", dev
->name
);
6601 netif_carrier_off(dev
);
6603 DBG_PRINT(ERR_DBG
, "%s: Link Up\n", dev
->name
);
6604 netif_carrier_on(dev
);
6607 sp
->last_link_state
= link
;
6611 * get_xena_rev_id - to identify revision ID of xena.
6612 * @pdev : PCI Dev structure
6614 * Function to identify the Revision ID of xena.
6616 * returns the revision ID of the device.
6619 static int get_xena_rev_id(struct pci_dev
*pdev
)
6623 ret
= pci_read_config_byte(pdev
, PCI_REVISION_ID
, (u8
*) & id
);
6628 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6629 * @sp : private member of the device structure, which is a pointer to the
6630 * s2io_nic structure.
6632 * This function initializes a few of the PCI and PCI-X configuration registers
6633 * with recommended values.
6638 static void s2io_init_pci(struct s2io_nic
* sp
)
6640 u16 pci_cmd
= 0, pcix_cmd
= 0;
6642 /* Enable Data Parity Error Recovery in PCI-X command register. */
6643 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
6645 pci_write_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
6647 pci_read_config_word(sp
->pdev
, PCIX_COMMAND_REGISTER
,
6650 /* Set the PErr Response bit in PCI command register. */
6651 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
6652 pci_write_config_word(sp
->pdev
, PCI_COMMAND
,
6653 (pci_cmd
| PCI_COMMAND_PARITY
));
6654 pci_read_config_word(sp
->pdev
, PCI_COMMAND
, &pci_cmd
);
6657 static int s2io_verify_parm(struct pci_dev
*pdev
, u8
*dev_intr_type
)
6659 if ( tx_fifo_num
> 8) {
6660 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Tx fifos not "
6662 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Tx fifos\n");
6665 if ( rx_ring_num
> 8) {
6666 DBG_PRINT(ERR_DBG
, "s2io: Requested number of Rx rings not "
6668 DBG_PRINT(ERR_DBG
, "s2io: Default to 8 Rx rings\n");
6671 if (*dev_intr_type
!= INTA
)
6674 #ifndef CONFIG_PCI_MSI
6675 if (*dev_intr_type
!= INTA
) {
6676 DBG_PRINT(ERR_DBG
, "s2io: This kernel does not support"
6677 "MSI/MSI-X. Defaulting to INTA\n");
6678 *dev_intr_type
= INTA
;
6681 if (*dev_intr_type
> MSI_X
) {
6682 DBG_PRINT(ERR_DBG
, "s2io: Wrong intr_type requested. "
6683 "Defaulting to INTA\n");
6684 *dev_intr_type
= INTA
;
6687 if ((*dev_intr_type
== MSI_X
) &&
6688 ((pdev
->device
!= PCI_DEVICE_ID_HERC_WIN
) &&
6689 (pdev
->device
!= PCI_DEVICE_ID_HERC_UNI
))) {
6690 DBG_PRINT(ERR_DBG
, "s2io: Xframe I does not support MSI_X. "
6691 "Defaulting to INTA\n");
6692 *dev_intr_type
= INTA
;
6694 if ( (rx_ring_num
> 1) && (*dev_intr_type
!= INTA
) )
6696 if (rx_ring_mode
> 3) {
6697 DBG_PRINT(ERR_DBG
, "s2io: Requested ring mode not supported\n");
6698 DBG_PRINT(ERR_DBG
, "s2io: Defaulting to 3-buffer mode\n");
6705 * s2io_init_nic - Initialization of the adapter .
6706 * @pdev : structure containing the PCI related information of the device.
6707 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6709 * The function initializes an adapter identified by the pci_dec structure.
6710 * All OS related initialization including memory and device structure and
6711 * initlaization of the device private variable is done. Also the swapper
6712 * control register is initialized to enable read and write into the I/O
6713 * registers of the device.
6715 * returns 0 on success and negative on failure.
6718 static int __devinit
6719 s2io_init_nic(struct pci_dev
*pdev
, const struct pci_device_id
*pre
)
6721 struct s2io_nic
*sp
;
6722 struct net_device
*dev
;
6724 int dma_flag
= FALSE
;
6725 u32 mac_up
, mac_down
;
6726 u64 val64
= 0, tmp64
= 0;
6727 struct XENA_dev_config __iomem
*bar0
= NULL
;
6729 struct mac_info
*mac_control
;
6730 struct config_param
*config
;
6732 u8 dev_intr_type
= intr_type
;
6734 if ((ret
= s2io_verify_parm(pdev
, &dev_intr_type
)))
6737 if ((ret
= pci_enable_device(pdev
))) {
6739 "s2io_init_nic: pci_enable_device failed\n");
6743 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
6744 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 64bit DMA\n");
6746 if (pci_set_consistent_dma_mask
6747 (pdev
, DMA_64BIT_MASK
)) {
6749 "Unable to obtain 64bit DMA for \
6750 consistent allocations\n");
6751 pci_disable_device(pdev
);
6754 } else if (!pci_set_dma_mask(pdev
, DMA_32BIT_MASK
)) {
6755 DBG_PRINT(INIT_DBG
, "s2io_init_nic: Using 32bit DMA\n");
6757 pci_disable_device(pdev
);
6760 if (dev_intr_type
!= MSI_X
) {
6761 if (pci_request_regions(pdev
, s2io_driver_name
)) {
6762 DBG_PRINT(ERR_DBG
, "Request Regions failed\n");
6763 pci_disable_device(pdev
);
6768 if (!(request_mem_region(pci_resource_start(pdev
, 0),
6769 pci_resource_len(pdev
, 0), s2io_driver_name
))) {
6770 DBG_PRINT(ERR_DBG
, "bar0 Request Regions failed\n");
6771 pci_disable_device(pdev
);
6774 if (!(request_mem_region(pci_resource_start(pdev
, 2),
6775 pci_resource_len(pdev
, 2), s2io_driver_name
))) {
6776 DBG_PRINT(ERR_DBG
, "bar1 Request Regions failed\n");
6777 release_mem_region(pci_resource_start(pdev
, 0),
6778 pci_resource_len(pdev
, 0));
6779 pci_disable_device(pdev
);
6784 dev
= alloc_etherdev(sizeof(struct s2io_nic
));
6786 DBG_PRINT(ERR_DBG
, "Device allocation failed\n");
6787 pci_disable_device(pdev
);
6788 pci_release_regions(pdev
);
6792 pci_set_master(pdev
);
6793 pci_set_drvdata(pdev
, dev
);
6794 SET_MODULE_OWNER(dev
);
6795 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6797 /* Private member variable initialized to s2io NIC structure */
6799 memset(sp
, 0, sizeof(struct s2io_nic
));
6802 sp
->high_dma_flag
= dma_flag
;
6803 sp
->device_enabled_once
= FALSE
;
6804 if (rx_ring_mode
== 1)
6805 sp
->rxd_mode
= RXD_MODE_1
;
6806 if (rx_ring_mode
== 2)
6807 sp
->rxd_mode
= RXD_MODE_3B
;
6808 if (rx_ring_mode
== 3)
6809 sp
->rxd_mode
= RXD_MODE_3A
;
6811 sp
->intr_type
= dev_intr_type
;
6813 if ((pdev
->device
== PCI_DEVICE_ID_HERC_WIN
) ||
6814 (pdev
->device
== PCI_DEVICE_ID_HERC_UNI
))
6815 sp
->device_type
= XFRAME_II_DEVICE
;
6817 sp
->device_type
= XFRAME_I_DEVICE
;
6821 /* Initialize some PCI/PCI-X fields of the NIC. */
6825 * Setting the device configuration parameters.
6826 * Most of these parameters can be specified by the user during
6827 * module insertion as they are module loadable parameters. If
6828 * these parameters are not not specified during load time, they
6829 * are initialized with default values.
6831 mac_control
= &sp
->mac_control
;
6832 config
= &sp
->config
;
6834 /* Tx side parameters. */
6835 config
->tx_fifo_num
= tx_fifo_num
;
6836 for (i
= 0; i
< MAX_TX_FIFOS
; i
++) {
6837 config
->tx_cfg
[i
].fifo_len
= tx_fifo_len
[i
];
6838 config
->tx_cfg
[i
].fifo_priority
= i
;
6841 /* mapping the QoS priority to the configured fifos */
6842 for (i
= 0; i
< MAX_TX_FIFOS
; i
++)
6843 config
->fifo_mapping
[i
] = fifo_map
[config
->tx_fifo_num
][i
];
6845 config
->tx_intr_type
= TXD_INT_TYPE_UTILZ
;
6846 for (i
= 0; i
< config
->tx_fifo_num
; i
++) {
6847 config
->tx_cfg
[i
].f_no_snoop
=
6848 (NO_SNOOP_TXD
| NO_SNOOP_TXD_BUFFER
);
6849 if (config
->tx_cfg
[i
].fifo_len
< 65) {
6850 config
->tx_intr_type
= TXD_INT_TYPE_PER_LIST
;
6854 /* + 2 because one Txd for skb->data and one Txd for UFO */
6855 config
->max_txds
= MAX_SKB_FRAGS
+ 2;
6857 /* Rx side parameters. */
6858 config
->rx_ring_num
= rx_ring_num
;
6859 for (i
= 0; i
< MAX_RX_RINGS
; i
++) {
6860 config
->rx_cfg
[i
].num_rxd
= rx_ring_sz
[i
] *
6861 (rxd_count
[sp
->rxd_mode
] + 1);
6862 config
->rx_cfg
[i
].ring_priority
= i
;
6865 for (i
= 0; i
< rx_ring_num
; i
++) {
6866 config
->rx_cfg
[i
].ring_org
= RING_ORG_BUFF1
;
6867 config
->rx_cfg
[i
].f_no_snoop
=
6868 (NO_SNOOP_RXD
| NO_SNOOP_RXD_BUFFER
);
6871 /* Setting Mac Control parameters */
6872 mac_control
->rmac_pause_time
= rmac_pause_time
;
6873 mac_control
->mc_pause_threshold_q0q3
= mc_pause_threshold_q0q3
;
6874 mac_control
->mc_pause_threshold_q4q7
= mc_pause_threshold_q4q7
;
6877 /* Initialize Ring buffer parameters. */
6878 for (i
= 0; i
< config
->rx_ring_num
; i
++)
6879 atomic_set(&sp
->rx_bufs_left
[i
], 0);
6881 /* Initialize the number of ISRs currently running */
6882 atomic_set(&sp
->isr_cnt
, 0);
6884 /* initialize the shared memory used by the NIC and the host */
6885 if (init_shared_mem(sp
)) {
6886 DBG_PRINT(ERR_DBG
, "%s: Memory allocation failed\n",
6889 goto mem_alloc_failed
;
6892 sp
->bar0
= ioremap(pci_resource_start(pdev
, 0),
6893 pci_resource_len(pdev
, 0));
6895 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem1\n",
6898 goto bar0_remap_failed
;
6901 sp
->bar1
= ioremap(pci_resource_start(pdev
, 2),
6902 pci_resource_len(pdev
, 2));
6904 DBG_PRINT(ERR_DBG
, "%s: Neterion: cannot remap io mem2\n",
6907 goto bar1_remap_failed
;
6910 dev
->irq
= pdev
->irq
;
6911 dev
->base_addr
= (unsigned long) sp
->bar0
;
6913 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6914 for (j
= 0; j
< MAX_TX_FIFOS
; j
++) {
6915 mac_control
->tx_FIFO_start
[j
] = (struct TxFIFO_element __iomem
*)
6916 (sp
->bar1
+ (j
* 0x00020000));
6919 /* Driver entry points */
6920 dev
->open
= &s2io_open
;
6921 dev
->stop
= &s2io_close
;
6922 dev
->hard_start_xmit
= &s2io_xmit
;
6923 dev
->get_stats
= &s2io_get_stats
;
6924 dev
->set_multicast_list
= &s2io_set_multicast
;
6925 dev
->do_ioctl
= &s2io_ioctl
;
6926 dev
->change_mtu
= &s2io_change_mtu
;
6927 SET_ETHTOOL_OPS(dev
, &netdev_ethtool_ops
);
6928 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
6929 dev
->vlan_rx_register
= s2io_vlan_rx_register
;
6930 dev
->vlan_rx_kill_vid
= (void *)s2io_vlan_rx_kill_vid
;
6933 * will use eth_mac_addr() for dev->set_mac_address
6934 * mac address will be set every time dev->open() is called
6936 dev
->poll
= s2io_poll
;
6939 #ifdef CONFIG_NET_POLL_CONTROLLER
6940 dev
->poll_controller
= s2io_netpoll
;
6943 dev
->features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
;
6944 if (sp
->high_dma_flag
== TRUE
)
6945 dev
->features
|= NETIF_F_HIGHDMA
;
6946 dev
->features
|= NETIF_F_TSO
;
6947 dev
->features
|= NETIF_F_TSO6
;
6948 if ((sp
->device_type
& XFRAME_II_DEVICE
) && (ufo
)) {
6949 dev
->features
|= NETIF_F_UFO
;
6950 dev
->features
|= NETIF_F_HW_CSUM
;
6953 dev
->tx_timeout
= &s2io_tx_watchdog
;
6954 dev
->watchdog_timeo
= WATCH_DOG_TIMEOUT
;
6955 INIT_WORK(&sp
->rst_timer_task
, s2io_restart_nic
);
6956 INIT_WORK(&sp
->set_link_task
, s2io_set_link
);
6958 pci_save_state(sp
->pdev
);
6960 /* Setting swapper control on the NIC, for proper reset operation */
6961 if (s2io_set_swapper(sp
)) {
6962 DBG_PRINT(ERR_DBG
, "%s:swapper settings are wrong\n",
6965 goto set_swap_failed
;
6968 /* Verify if the Herc works on the slot its placed into */
6969 if (sp
->device_type
& XFRAME_II_DEVICE
) {
6970 mode
= s2io_verify_pci_mode(sp
);
6972 DBG_PRINT(ERR_DBG
, "%s: ", __FUNCTION__
);
6973 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
6975 goto set_swap_failed
;
6979 /* Not needed for Herc */
6980 if (sp
->device_type
& XFRAME_I_DEVICE
) {
6982 * Fix for all "FFs" MAC address problems observed on
6985 fix_mac_address(sp
);
6990 * MAC address initialization.
6991 * For now only one mac address will be read and used.
6994 val64
= RMAC_ADDR_CMD_MEM_RD
| RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
|
6995 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET
);
6996 writeq(val64
, &bar0
->rmac_addr_cmd_mem
);
6997 wait_for_cmd_complete(&bar0
->rmac_addr_cmd_mem
,
6998 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
);
6999 tmp64
= readq(&bar0
->rmac_addr_data0_mem
);
7000 mac_down
= (u32
) tmp64
;
7001 mac_up
= (u32
) (tmp64
>> 32);
7003 memset(sp
->def_mac_addr
[0].mac_addr
, 0, sizeof(ETH_ALEN
));
7005 sp
->def_mac_addr
[0].mac_addr
[3] = (u8
) (mac_up
);
7006 sp
->def_mac_addr
[0].mac_addr
[2] = (u8
) (mac_up
>> 8);
7007 sp
->def_mac_addr
[0].mac_addr
[1] = (u8
) (mac_up
>> 16);
7008 sp
->def_mac_addr
[0].mac_addr
[0] = (u8
) (mac_up
>> 24);
7009 sp
->def_mac_addr
[0].mac_addr
[5] = (u8
) (mac_down
>> 16);
7010 sp
->def_mac_addr
[0].mac_addr
[4] = (u8
) (mac_down
>> 24);
7012 /* Set the factory defined MAC address initially */
7013 dev
->addr_len
= ETH_ALEN
;
7014 memcpy(dev
->dev_addr
, sp
->def_mac_addr
, ETH_ALEN
);
7016 /* reset Nic and bring it to known state */
7020 * Initialize the tasklet status and link state flags
7021 * and the card state parameter
7023 atomic_set(&(sp
->card_state
), 0);
7024 sp
->tasklet_status
= 0;
7027 /* Initialize spinlocks */
7028 spin_lock_init(&sp
->tx_lock
);
7031 spin_lock_init(&sp
->put_lock
);
7032 spin_lock_init(&sp
->rx_lock
);
7035 * SXE-002: Configure link and activity LED to init state
7038 subid
= sp
->pdev
->subsystem_device
;
7039 if ((subid
& 0xFF) >= 0x07) {
7040 val64
= readq(&bar0
->gpio_control
);
7041 val64
|= 0x0000800000000000ULL
;
7042 writeq(val64
, &bar0
->gpio_control
);
7043 val64
= 0x0411040400000000ULL
;
7044 writeq(val64
, (void __iomem
*) bar0
+ 0x2700);
7045 val64
= readq(&bar0
->gpio_control
);
7048 sp
->rx_csum
= 1; /* Rx chksum verify enabled by default */
7050 if (register_netdev(dev
)) {
7051 DBG_PRINT(ERR_DBG
, "Device registration failed\n");
7053 goto register_failed
;
7056 DBG_PRINT(ERR_DBG
, "Copyright(c) 2002-2005 Neterion Inc.\n");
7057 DBG_PRINT(ERR_DBG
, "%s: Neterion %s (rev %d)\n",dev
->name
,
7058 sp
->product_name
, get_xena_rev_id(sp
->pdev
));
7059 DBG_PRINT(ERR_DBG
, "%s: Driver version %s\n", dev
->name
,
7060 s2io_driver_version
);
7061 DBG_PRINT(ERR_DBG
, "%s: MAC ADDR: "
7062 "%02x:%02x:%02x:%02x:%02x:%02x", dev
->name
,
7063 sp
->def_mac_addr
[0].mac_addr
[0],
7064 sp
->def_mac_addr
[0].mac_addr
[1],
7065 sp
->def_mac_addr
[0].mac_addr
[2],
7066 sp
->def_mac_addr
[0].mac_addr
[3],
7067 sp
->def_mac_addr
[0].mac_addr
[4],
7068 sp
->def_mac_addr
[0].mac_addr
[5]);
7069 DBG_PRINT(ERR_DBG
, "SERIAL NUMBER: %s\n", sp
->serial_num
);
7070 if (sp
->device_type
& XFRAME_II_DEVICE
) {
7071 mode
= s2io_print_pci_mode(sp
);
7073 DBG_PRINT(ERR_DBG
, " Unsupported PCI bus mode\n");
7075 unregister_netdev(dev
);
7076 goto set_swap_failed
;
7079 switch(sp
->rxd_mode
) {
7081 DBG_PRINT(ERR_DBG
, "%s: 1-Buffer receive mode enabled\n",
7085 DBG_PRINT(ERR_DBG
, "%s: 2-Buffer receive mode enabled\n",
7089 DBG_PRINT(ERR_DBG
, "%s: 3-Buffer receive mode enabled\n",
7095 DBG_PRINT(ERR_DBG
, "%s: NAPI enabled\n", dev
->name
);
7096 switch(sp
->intr_type
) {
7098 DBG_PRINT(ERR_DBG
, "%s: Interrupt type INTA\n", dev
->name
);
7101 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI\n", dev
->name
);
7104 DBG_PRINT(ERR_DBG
, "%s: Interrupt type MSI-X\n", dev
->name
);
7108 DBG_PRINT(ERR_DBG
, "%s: Large receive offload enabled\n",
7111 DBG_PRINT(ERR_DBG
, "%s: UDP Fragmentation Offload(UFO)"
7112 " enabled\n", dev
->name
);
7113 /* Initialize device name */
7114 sprintf(sp
->name
, "%s Neterion %s", dev
->name
, sp
->product_name
);
7116 /* Initialize bimodal Interrupts */
7117 sp
->config
.bimodal
= bimodal
;
7118 if (!(sp
->device_type
& XFRAME_II_DEVICE
) && bimodal
) {
7119 sp
->config
.bimodal
= 0;
7120 DBG_PRINT(ERR_DBG
,"%s:Bimodal intr not supported by Xframe I\n",
7125 * Make Link state as off at this point, when the Link change
7126 * interrupt comes the state will be automatically changed to
7129 netif_carrier_off(dev
);
7140 free_shared_mem(sp
);
7141 pci_disable_device(pdev
);
7142 if (dev_intr_type
!= MSI_X
)
7143 pci_release_regions(pdev
);
7145 release_mem_region(pci_resource_start(pdev
, 0),
7146 pci_resource_len(pdev
, 0));
7147 release_mem_region(pci_resource_start(pdev
, 2),
7148 pci_resource_len(pdev
, 2));
7150 pci_set_drvdata(pdev
, NULL
);
7157 * s2io_rem_nic - Free the PCI device
7158 * @pdev: structure containing the PCI related information of the device.
7159 * Description: This function is called by the Pci subsystem to release a
7160 * PCI device and free up all resource held up by the device. This could
7161 * be in response to a Hot plug event or when the driver is to be removed
7165 static void __devexit
s2io_rem_nic(struct pci_dev
*pdev
)
7167 struct net_device
*dev
=
7168 (struct net_device
*) pci_get_drvdata(pdev
);
7169 struct s2io_nic
*sp
;
7172 DBG_PRINT(ERR_DBG
, "Driver Data is NULL!!\n");
7177 unregister_netdev(dev
);
7179 free_shared_mem(sp
);
7182 if (sp
->intr_type
!= MSI_X
)
7183 pci_release_regions(pdev
);
7185 release_mem_region(pci_resource_start(pdev
, 0),
7186 pci_resource_len(pdev
, 0));
7187 release_mem_region(pci_resource_start(pdev
, 2),
7188 pci_resource_len(pdev
, 2));
7190 pci_set_drvdata(pdev
, NULL
);
7192 pci_disable_device(pdev
);
7196 * s2io_starter - Entry point for the driver
7197 * Description: This function is the entry point for the driver. It verifies
7198 * the module loadable parameters and initializes PCI configuration space.
7201 int __init
s2io_starter(void)
7203 return pci_register_driver(&s2io_driver
);
7207 * s2io_closer - Cleanup routine for the driver
7208 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7211 static __exit
void s2io_closer(void)
7213 pci_unregister_driver(&s2io_driver
);
7214 DBG_PRINT(INIT_DBG
, "cleanup done\n");
7217 module_init(s2io_starter
);
7218 module_exit(s2io_closer
);
7220 static int check_L2_lro_capable(u8
*buffer
, struct iphdr
**ip
,
7221 struct tcphdr
**tcp
, struct RxD_t
*rxdp
)
7224 u8 l2_type
= (u8
)((rxdp
->Control_1
>> 37) & 0x7), ip_len
;
7226 if (!(rxdp
->Control_1
& RXD_FRAME_PROTO_TCP
)) {
7227 DBG_PRINT(INIT_DBG
,"%s: Non-TCP frames not supported for LRO\n",
7233 * By default the VLAN field in the MAC is stripped by the card, if this
7234 * feature is turned off in rx_pa_cfg register, then the ip_off field
7235 * has to be shifted by a further 2 bytes
7238 case 0: /* DIX type */
7239 case 4: /* DIX type with VLAN */
7240 ip_off
= HEADER_ETHERNET_II_802_3_SIZE
;
7242 /* LLC, SNAP etc are considered non-mergeable */
7247 *ip
= (struct iphdr
*)((u8
*)buffer
+ ip_off
);
7248 ip_len
= (u8
)((*ip
)->ihl
);
7250 *tcp
= (struct tcphdr
*)((unsigned long)*ip
+ ip_len
);
7255 static int check_for_socket_match(struct lro
*lro
, struct iphdr
*ip
,
7258 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7259 if ((lro
->iph
->saddr
!= ip
->saddr
) || (lro
->iph
->daddr
!= ip
->daddr
) ||
7260 (lro
->tcph
->source
!= tcp
->source
) || (lro
->tcph
->dest
!= tcp
->dest
))
7265 static inline int get_l4_pyld_length(struct iphdr
*ip
, struct tcphdr
*tcp
)
7267 return(ntohs(ip
->tot_len
) - (ip
->ihl
<< 2) - (tcp
->doff
<< 2));
7270 static void initiate_new_session(struct lro
*lro
, u8
*l2h
,
7271 struct iphdr
*ip
, struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7273 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7277 lro
->tcp_next_seq
= tcp_pyld_len
+ ntohl(tcp
->seq
);
7278 lro
->tcp_ack
= ntohl(tcp
->ack_seq
);
7280 lro
->total_len
= ntohs(ip
->tot_len
);
7283 * check if we saw TCP timestamp. Other consistency checks have
7284 * already been done.
7286 if (tcp
->doff
== 8) {
7288 ptr
= (u32
*)(tcp
+1);
7290 lro
->cur_tsval
= *(ptr
+1);
7291 lro
->cur_tsecr
= *(ptr
+2);
7296 static void update_L3L4_header(struct s2io_nic
*sp
, struct lro
*lro
)
7298 struct iphdr
*ip
= lro
->iph
;
7299 struct tcphdr
*tcp
= lro
->tcph
;
7301 struct stat_block
*statinfo
= sp
->mac_control
.stats_info
;
7302 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7304 /* Update L3 header */
7305 ip
->tot_len
= htons(lro
->total_len
);
7307 nchk
= ip_fast_csum((u8
*)lro
->iph
, ip
->ihl
);
7310 /* Update L4 header */
7311 tcp
->ack_seq
= lro
->tcp_ack
;
7312 tcp
->window
= lro
->window
;
7314 /* Update tsecr field if this session has timestamps enabled */
7316 u32
*ptr
= (u32
*)(tcp
+ 1);
7317 *(ptr
+2) = lro
->cur_tsecr
;
7320 /* Update counters required for calculation of
7321 * average no. of packets aggregated.
7323 statinfo
->sw_stat
.sum_avg_pkts_aggregated
+= lro
->sg_num
;
7324 statinfo
->sw_stat
.num_aggregations
++;
7327 static void aggregate_new_rx(struct lro
*lro
, struct iphdr
*ip
,
7328 struct tcphdr
*tcp
, u32 l4_pyld
)
7330 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7331 lro
->total_len
+= l4_pyld
;
7332 lro
->frags_len
+= l4_pyld
;
7333 lro
->tcp_next_seq
+= l4_pyld
;
7336 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7337 lro
->tcp_ack
= tcp
->ack_seq
;
7338 lro
->window
= tcp
->window
;
7342 /* Update tsecr and tsval from this packet */
7343 ptr
= (u32
*) (tcp
+ 1);
7344 lro
->cur_tsval
= *(ptr
+ 1);
7345 lro
->cur_tsecr
= *(ptr
+ 2);
7349 static int verify_l3_l4_lro_capable(struct lro
*l_lro
, struct iphdr
*ip
,
7350 struct tcphdr
*tcp
, u32 tcp_pyld_len
)
7354 DBG_PRINT(INFO_DBG
,"%s: Been here...\n", __FUNCTION__
);
7356 if (!tcp_pyld_len
) {
7357 /* Runt frame or a pure ack */
7361 if (ip
->ihl
!= 5) /* IP has options */
7364 /* If we see CE codepoint in IP header, packet is not mergeable */
7365 if (INET_ECN_is_ce(ipv4_get_dsfield(ip
)))
7368 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7369 if (tcp
->urg
|| tcp
->psh
|| tcp
->rst
|| tcp
->syn
|| tcp
->fin
||
7370 tcp
->ece
|| tcp
->cwr
|| !tcp
->ack
) {
7372 * Currently recognize only the ack control word and
7373 * any other control field being set would result in
7374 * flushing the LRO session
7380 * Allow only one TCP timestamp option. Don't aggregate if
7381 * any other options are detected.
7383 if (tcp
->doff
!= 5 && tcp
->doff
!= 8)
7386 if (tcp
->doff
== 8) {
7387 ptr
= (u8
*)(tcp
+ 1);
7388 while (*ptr
== TCPOPT_NOP
)
7390 if (*ptr
!= TCPOPT_TIMESTAMP
|| *(ptr
+1) != TCPOLEN_TIMESTAMP
)
7393 /* Ensure timestamp value increases monotonically */
7395 if (l_lro
->cur_tsval
> *((u32
*)(ptr
+2)))
7398 /* timestamp echo reply should be non-zero */
7399 if (*((u32
*)(ptr
+6)) == 0)
7407 s2io_club_tcp_session(u8
*buffer
, u8
**tcp
, u32
*tcp_len
, struct lro
**lro
,
7408 struct RxD_t
*rxdp
, struct s2io_nic
*sp
)
7411 struct tcphdr
*tcph
;
7414 if (!(ret
= check_L2_lro_capable(buffer
, &ip
, (struct tcphdr
**)tcp
,
7416 DBG_PRINT(INFO_DBG
,"IP Saddr: %x Daddr: %x\n",
7417 ip
->saddr
, ip
->daddr
);
7422 tcph
= (struct tcphdr
*)*tcp
;
7423 *tcp_len
= get_l4_pyld_length(ip
, tcph
);
7424 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7425 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7426 if (l_lro
->in_use
) {
7427 if (check_for_socket_match(l_lro
, ip
, tcph
))
7429 /* Sock pair matched */
7432 if ((*lro
)->tcp_next_seq
!= ntohl(tcph
->seq
)) {
7433 DBG_PRINT(INFO_DBG
, "%s:Out of order. expected "
7434 "0x%x, actual 0x%x\n", __FUNCTION__
,
7435 (*lro
)->tcp_next_seq
,
7438 sp
->mac_control
.stats_info
->
7439 sw_stat
.outof_sequence_pkts
++;
7444 if (!verify_l3_l4_lro_capable(l_lro
, ip
, tcph
,*tcp_len
))
7445 ret
= 1; /* Aggregate */
7447 ret
= 2; /* Flush both */
7453 /* Before searching for available LRO objects,
7454 * check if the pkt is L3/L4 aggregatable. If not
7455 * don't create new LRO session. Just send this
7458 if (verify_l3_l4_lro_capable(NULL
, ip
, tcph
, *tcp_len
)) {
7462 for (i
=0; i
<MAX_LRO_SESSIONS
; i
++) {
7463 struct lro
*l_lro
= &sp
->lro0_n
[i
];
7464 if (!(l_lro
->in_use
)) {
7466 ret
= 3; /* Begin anew */
7472 if (ret
== 0) { /* sessions exceeded */
7473 DBG_PRINT(INFO_DBG
,"%s:All LRO sessions already in use\n",
7481 initiate_new_session(*lro
, buffer
, ip
, tcph
, *tcp_len
);
7484 update_L3L4_header(sp
, *lro
);
7487 aggregate_new_rx(*lro
, ip
, tcph
, *tcp_len
);
7488 if ((*lro
)->sg_num
== sp
->lro_max_aggr_per_sess
) {
7489 update_L3L4_header(sp
, *lro
);
7490 ret
= 4; /* Flush the LRO */
7494 DBG_PRINT(ERR_DBG
,"%s:Dont know, can't say!!\n",
7502 static void clear_lro_session(struct lro
*lro
)
7504 static u16 lro_struct_size
= sizeof(struct lro
);
7506 memset(lro
, 0, lro_struct_size
);
7509 static void queue_rx_frame(struct sk_buff
*skb
)
7511 struct net_device
*dev
= skb
->dev
;
7513 skb
->protocol
= eth_type_trans(skb
, dev
);
7515 netif_receive_skb(skb
);
7520 static void lro_append_pkt(struct s2io_nic
*sp
, struct lro
*lro
,
7521 struct sk_buff
*skb
,
7524 struct sk_buff
*first
= lro
->parent
;
7526 first
->len
+= tcp_len
;
7527 first
->data_len
= lro
->frags_len
;
7528 skb_pull(skb
, (skb
->len
- tcp_len
));
7529 if (skb_shinfo(first
)->frag_list
)
7530 lro
->last_frag
->next
= skb
;
7532 skb_shinfo(first
)->frag_list
= skb
;
7533 first
->truesize
+= skb
->truesize
;
7534 lro
->last_frag
= skb
;
7535 sp
->mac_control
.stats_info
->sw_stat
.clubbed_frms_cnt
++;