2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit
= 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE
= 0x00,
94 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
95 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25
= 0x19 // 8168D
121 #define _R(NAME,MAC,MASK) \
122 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
124 static const struct {
127 u32 RxConfigMask
; /* Clears the bits supported by this chip */
128 } rtl_chip_info
[] = {
129 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
130 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
131 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
132 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
134 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
135 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
137 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
146 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
153 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880) // PCI-E
163 static void rtl_hw_start_8169(struct net_device
*);
164 static void rtl_hw_start_8168(struct net_device
*);
165 static void rtl_hw_start_8101(struct net_device
*);
167 static struct pci_device_id rtl8169_pci_tbl
[] = {
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
173 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
175 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
176 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
177 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
179 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
183 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
185 static int rx_copybreak
= 200;
192 MAC0
= 0, /* Ethernet hardware address. */
194 MAR0
= 8, /* Multicast filter. */
195 CounterAddrLow
= 0x10,
196 CounterAddrHigh
= 0x14,
197 TxDescStartAddrLow
= 0x20,
198 TxDescStartAddrHigh
= 0x24,
199 TxHDescStartAddrLow
= 0x28,
200 TxHDescStartAddrHigh
= 0x2c,
223 RxDescAddrLow
= 0xe4,
224 RxDescAddrHigh
= 0xe8,
227 FuncEventMask
= 0xf4,
228 FuncPresetState
= 0xf8,
229 FuncForceEvent
= 0xfc,
232 enum rtl8110_registers
{
238 enum rtl8168_8101_registers
{
241 #define CSIAR_FLAG 0x80000000
242 #define CSIAR_WRITE_CMD 0x80000000
243 #define CSIAR_BYTE_ENABLE 0x0f
244 #define CSIAR_BYTE_ENABLE_SHIFT 12
245 #define CSIAR_ADDR_MASK 0x0fff
248 #define EPHYAR_FLAG 0x80000000
249 #define EPHYAR_WRITE_CMD 0x80000000
250 #define EPHYAR_REG_MASK 0x1f
251 #define EPHYAR_REG_SHIFT 16
252 #define EPHYAR_DATA_MASK 0xffff
254 #define FIX_NAK_1 (1 << 4)
255 #define FIX_NAK_2 (1 << 3)
258 enum rtl_register_content
{
259 /* InterruptStatusBits */
263 TxDescUnavail
= 0x0080,
285 /* TXPoll register p.5 */
286 HPQ
= 0x80, /* Poll cmd on the high prio queue */
287 NPQ
= 0x40, /* Poll cmd on the low prio queue */
288 FSWInt
= 0x01, /* Forced software interrupt */
292 Cfg9346_Unlock
= 0xc0,
297 AcceptBroadcast
= 0x08,
298 AcceptMulticast
= 0x04,
300 AcceptAllPhys
= 0x01,
307 TxInterFrameGapShift
= 24,
308 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
310 /* Config1 register p.24 */
313 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
314 Speed_down
= (1 << 4),
318 PMEnable
= (1 << 0), /* Power Management Enable */
320 /* Config2 register p. 25 */
321 PCI_Clock_66MHz
= 0x01,
322 PCI_Clock_33MHz
= 0x00,
324 /* Config3 register p.25 */
325 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
327 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
329 /* Config5 register p.27 */
330 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
332 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake
= (1 << 1), /* LanWake enable/disable */
334 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
337 TBIReset
= 0x80000000,
338 TBILoopback
= 0x40000000,
339 TBINwEnable
= 0x20000000,
340 TBINwRestart
= 0x10000000,
341 TBILinkOk
= 0x02000000,
342 TBINwComplete
= 0x01000000,
345 EnableBist
= (1 << 15), // 8168 8101
346 Mac_dbgo_oe
= (1 << 14), // 8168 8101
347 Normal_mode
= (1 << 13), // unused
348 Force_half_dup
= (1 << 12), // 8168 8101
349 Force_rxflow_en
= (1 << 11), // 8168 8101
350 Force_txflow_en
= (1 << 10), // 8168 8101
351 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
352 ASF
= (1 << 8), // 8168 8101
353 PktCntrDisable
= (1 << 7), // 8168 8101
354 Mac_dbgo_sel
= 0x001c, // 8168
359 INTT_0
= 0x0000, // 8168
360 INTT_1
= 0x0001, // 8168
361 INTT_2
= 0x0002, // 8168
362 INTT_3
= 0x0003, // 8168
364 /* rtl8169_PHYstatus */
375 TBILinkOK
= 0x02000000,
377 /* DumpCounterCommand */
381 enum desc_status_bit
{
382 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd
= (1 << 30), /* End of descriptor ring */
384 FirstFrag
= (1 << 29), /* First segment of a packet */
385 LastFrag
= (1 << 28), /* Final segment of a packet */
388 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift
= 16, /* MSS value position */
390 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS
= (1 << 18), /* Calculate IP checksum */
392 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag
= (1 << 17), /* Add VLAN tag */
397 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
398 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
400 #define RxProtoUDP (PID1)
401 #define RxProtoTCP (PID0)
402 #define RxProtoIP (PID1 | PID0)
403 #define RxProtoMask RxProtoIP
405 IPFail
= (1 << 16), /* IP checksum failed */
406 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
407 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag
= (1 << 16), /* VLAN tag available */
411 #define RsvdMask 0x3fffc000
428 u8 __pad
[sizeof(void *) - sizeof(u32
)];
432 RTL_FEATURE_WOL
= (1 << 0),
433 RTL_FEATURE_MSI
= (1 << 1),
434 RTL_FEATURE_GMII
= (1 << 2),
437 struct rtl8169_counters
{
444 __le32 tx_one_collision
;
445 __le32 tx_multi_collision
;
453 struct rtl8169_private
{
454 void __iomem
*mmio_addr
; /* memory map physical address */
455 struct pci_dev
*pci_dev
; /* Index of PCI device */
456 struct net_device
*dev
;
457 struct napi_struct napi
;
458 spinlock_t lock
; /* spin lock flag */
462 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
463 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
466 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
467 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
468 dma_addr_t TxPhyAddr
;
469 dma_addr_t RxPhyAddr
;
470 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
471 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
474 struct timer_list timer
;
479 int phy_1000_ctrl_reg
;
480 #ifdef CONFIG_R8169_VLAN
481 struct vlan_group
*vlgrp
;
483 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
484 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
485 void (*phy_reset_enable
)(void __iomem
*);
486 void (*hw_start
)(struct net_device
*);
487 unsigned int (*phy_reset_pending
)(void __iomem
*);
488 unsigned int (*link_ok
)(void __iomem
*);
489 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
491 struct delayed_work task
;
494 struct mii_if_info mii
;
495 struct rtl8169_counters counters
;
498 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
499 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
500 module_param(rx_copybreak
, int, 0);
501 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
502 module_param(use_dac
, int, 0);
503 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
504 module_param_named(debug
, debug
.msg_enable
, int, 0);
505 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
506 MODULE_LICENSE("GPL");
507 MODULE_VERSION(RTL8169_VERSION
);
509 static int rtl8169_open(struct net_device
*dev
);
510 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
511 struct net_device
*dev
);
512 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
513 static int rtl8169_init_ring(struct net_device
*dev
);
514 static void rtl_hw_start(struct net_device
*dev
);
515 static int rtl8169_close(struct net_device
*dev
);
516 static void rtl_set_rx_mode(struct net_device
*dev
);
517 static void rtl8169_tx_timeout(struct net_device
*dev
);
518 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
519 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
520 void __iomem
*, u32 budget
);
521 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
522 static void rtl8169_down(struct net_device
*dev
);
523 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
524 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
526 static const unsigned int rtl8169_rx_config
=
527 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
529 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
533 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
535 for (i
= 20; i
> 0; i
--) {
537 * Check if the RTL8169 has completed writing to the specified
540 if (!(RTL_R32(PHYAR
) & 0x80000000))
546 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
550 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
552 for (i
= 20; i
> 0; i
--) {
554 * Check if the RTL8169 has completed retrieving data from
555 * the specified MII register.
557 if (RTL_R32(PHYAR
) & 0x80000000) {
558 value
= RTL_R32(PHYAR
) & 0xffff;
566 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
568 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
571 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
574 struct rtl8169_private
*tp
= netdev_priv(dev
);
575 void __iomem
*ioaddr
= tp
->mmio_addr
;
577 mdio_write(ioaddr
, location
, val
);
580 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
582 struct rtl8169_private
*tp
= netdev_priv(dev
);
583 void __iomem
*ioaddr
= tp
->mmio_addr
;
585 return mdio_read(ioaddr
, location
);
588 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
592 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
593 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
595 for (i
= 0; i
< 100; i
++) {
596 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
602 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
607 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
609 for (i
= 0; i
< 100; i
++) {
610 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
611 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
620 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
624 RTL_W32(CSIDR
, value
);
625 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
626 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
628 for (i
= 0; i
< 100; i
++) {
629 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
635 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
640 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
641 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
643 for (i
= 0; i
< 100; i
++) {
644 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
645 value
= RTL_R32(CSIDR
);
654 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
656 RTL_W16(IntrMask
, 0x0000);
658 RTL_W16(IntrStatus
, 0xffff);
661 static void rtl8169_asic_down(void __iomem
*ioaddr
)
663 RTL_W8(ChipCmd
, 0x00);
664 rtl8169_irq_mask_and_ack(ioaddr
);
668 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
670 return RTL_R32(TBICSR
) & TBIReset
;
673 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
675 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
678 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
680 return RTL_R32(TBICSR
) & TBILinkOk
;
683 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
685 return RTL_R8(PHYstatus
) & LinkStatus
;
688 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
690 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
693 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
697 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
698 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
701 static void rtl8169_check_link_status(struct net_device
*dev
,
702 struct rtl8169_private
*tp
,
703 void __iomem
*ioaddr
)
707 spin_lock_irqsave(&tp
->lock
, flags
);
708 if (tp
->link_ok(ioaddr
)) {
709 netif_carrier_on(dev
);
710 if (netif_msg_ifup(tp
))
711 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
713 if (netif_msg_ifdown(tp
))
714 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
715 netif_carrier_off(dev
);
717 spin_unlock_irqrestore(&tp
->lock
, flags
);
720 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
722 struct rtl8169_private
*tp
= netdev_priv(dev
);
723 void __iomem
*ioaddr
= tp
->mmio_addr
;
728 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
729 wol
->supported
= WAKE_ANY
;
731 spin_lock_irq(&tp
->lock
);
733 options
= RTL_R8(Config1
);
734 if (!(options
& PMEnable
))
737 options
= RTL_R8(Config3
);
738 if (options
& LinkUp
)
739 wol
->wolopts
|= WAKE_PHY
;
740 if (options
& MagicPacket
)
741 wol
->wolopts
|= WAKE_MAGIC
;
743 options
= RTL_R8(Config5
);
745 wol
->wolopts
|= WAKE_UCAST
;
747 wol
->wolopts
|= WAKE_BCAST
;
749 wol
->wolopts
|= WAKE_MCAST
;
752 spin_unlock_irq(&tp
->lock
);
755 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
757 struct rtl8169_private
*tp
= netdev_priv(dev
);
758 void __iomem
*ioaddr
= tp
->mmio_addr
;
765 { WAKE_ANY
, Config1
, PMEnable
},
766 { WAKE_PHY
, Config3
, LinkUp
},
767 { WAKE_MAGIC
, Config3
, MagicPacket
},
768 { WAKE_UCAST
, Config5
, UWF
},
769 { WAKE_BCAST
, Config5
, BWF
},
770 { WAKE_MCAST
, Config5
, MWF
},
771 { WAKE_ANY
, Config5
, LanWake
}
774 spin_lock_irq(&tp
->lock
);
776 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
778 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
779 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
780 if (wol
->wolopts
& cfg
[i
].opt
)
781 options
|= cfg
[i
].mask
;
782 RTL_W8(cfg
[i
].reg
, options
);
785 RTL_W8(Cfg9346
, Cfg9346_Lock
);
788 tp
->features
|= RTL_FEATURE_WOL
;
790 tp
->features
&= ~RTL_FEATURE_WOL
;
791 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
793 spin_unlock_irq(&tp
->lock
);
798 static void rtl8169_get_drvinfo(struct net_device
*dev
,
799 struct ethtool_drvinfo
*info
)
801 struct rtl8169_private
*tp
= netdev_priv(dev
);
803 strcpy(info
->driver
, MODULENAME
);
804 strcpy(info
->version
, RTL8169_VERSION
);
805 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
808 static int rtl8169_get_regs_len(struct net_device
*dev
)
810 return R8169_REGS_SIZE
;
813 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
814 u8 autoneg
, u16 speed
, u8 duplex
)
816 struct rtl8169_private
*tp
= netdev_priv(dev
);
817 void __iomem
*ioaddr
= tp
->mmio_addr
;
821 reg
= RTL_R32(TBICSR
);
822 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
823 (duplex
== DUPLEX_FULL
)) {
824 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
825 } else if (autoneg
== AUTONEG_ENABLE
)
826 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
828 if (netif_msg_link(tp
)) {
829 printk(KERN_WARNING
"%s: "
830 "incorrect speed setting refused in TBI mode\n",
839 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
840 u8 autoneg
, u16 speed
, u8 duplex
)
842 struct rtl8169_private
*tp
= netdev_priv(dev
);
843 void __iomem
*ioaddr
= tp
->mmio_addr
;
846 if (autoneg
== AUTONEG_ENABLE
) {
849 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
850 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
851 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
852 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
854 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
855 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
857 /* The 8100e/8101e/8102e do Fast Ethernet only. */
858 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
859 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
860 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
861 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
862 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
863 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
864 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
865 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
866 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
867 } else if (netif_msg_link(tp
)) {
868 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
872 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
874 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
875 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
876 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
879 * Vendor specific (0x1f) and reserved (0x0e) MII
882 mdio_write(ioaddr
, 0x1f, 0x0000);
883 mdio_write(ioaddr
, 0x0e, 0x0000);
886 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
887 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
891 if (speed
== SPEED_10
)
893 else if (speed
== SPEED_100
)
894 bmcr
= BMCR_SPEED100
;
898 if (duplex
== DUPLEX_FULL
)
899 bmcr
|= BMCR_FULLDPLX
;
901 mdio_write(ioaddr
, 0x1f, 0x0000);
904 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
906 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
908 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
909 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
910 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
911 mdio_write(ioaddr
, 0x17, 0x2138);
912 mdio_write(ioaddr
, 0x0e, 0x0260);
914 mdio_write(ioaddr
, 0x17, 0x2108);
915 mdio_write(ioaddr
, 0x0e, 0x0000);
922 static int rtl8169_set_speed(struct net_device
*dev
,
923 u8 autoneg
, u16 speed
, u8 duplex
)
925 struct rtl8169_private
*tp
= netdev_priv(dev
);
928 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
930 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
931 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
936 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
938 struct rtl8169_private
*tp
= netdev_priv(dev
);
942 spin_lock_irqsave(&tp
->lock
, flags
);
943 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
944 spin_unlock_irqrestore(&tp
->lock
, flags
);
949 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
951 struct rtl8169_private
*tp
= netdev_priv(dev
);
953 return tp
->cp_cmd
& RxChkSum
;
956 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
958 struct rtl8169_private
*tp
= netdev_priv(dev
);
959 void __iomem
*ioaddr
= tp
->mmio_addr
;
962 spin_lock_irqsave(&tp
->lock
, flags
);
965 tp
->cp_cmd
|= RxChkSum
;
967 tp
->cp_cmd
&= ~RxChkSum
;
969 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
972 spin_unlock_irqrestore(&tp
->lock
, flags
);
977 #ifdef CONFIG_R8169_VLAN
979 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
982 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
983 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
986 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
987 struct vlan_group
*grp
)
989 struct rtl8169_private
*tp
= netdev_priv(dev
);
990 void __iomem
*ioaddr
= tp
->mmio_addr
;
993 spin_lock_irqsave(&tp
->lock
, flags
);
996 tp
->cp_cmd
|= RxVlan
;
998 tp
->cp_cmd
&= ~RxVlan
;
999 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1001 spin_unlock_irqrestore(&tp
->lock
, flags
);
1004 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1005 struct sk_buff
*skb
)
1007 u32 opts2
= le32_to_cpu(desc
->opts2
);
1008 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1011 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1012 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1020 #else /* !CONFIG_R8169_VLAN */
1022 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1023 struct sk_buff
*skb
)
1028 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1029 struct sk_buff
*skb
)
1036 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1038 struct rtl8169_private
*tp
= netdev_priv(dev
);
1039 void __iomem
*ioaddr
= tp
->mmio_addr
;
1043 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1044 cmd
->port
= PORT_FIBRE
;
1045 cmd
->transceiver
= XCVR_INTERNAL
;
1047 status
= RTL_R32(TBICSR
);
1048 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1049 cmd
->autoneg
= !!(status
& TBINwEnable
);
1051 cmd
->speed
= SPEED_1000
;
1052 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1057 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1059 struct rtl8169_private
*tp
= netdev_priv(dev
);
1061 return mii_ethtool_gset(&tp
->mii
, cmd
);
1064 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1066 struct rtl8169_private
*tp
= netdev_priv(dev
);
1067 unsigned long flags
;
1070 spin_lock_irqsave(&tp
->lock
, flags
);
1072 rc
= tp
->get_settings(dev
, cmd
);
1074 spin_unlock_irqrestore(&tp
->lock
, flags
);
1078 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1081 struct rtl8169_private
*tp
= netdev_priv(dev
);
1082 unsigned long flags
;
1084 if (regs
->len
> R8169_REGS_SIZE
)
1085 regs
->len
= R8169_REGS_SIZE
;
1087 spin_lock_irqsave(&tp
->lock
, flags
);
1088 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1089 spin_unlock_irqrestore(&tp
->lock
, flags
);
1092 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1094 struct rtl8169_private
*tp
= netdev_priv(dev
);
1096 return tp
->msg_enable
;
1099 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1101 struct rtl8169_private
*tp
= netdev_priv(dev
);
1103 tp
->msg_enable
= value
;
1106 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1113 "tx_single_collisions",
1114 "tx_multi_collisions",
1122 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1126 return ARRAY_SIZE(rtl8169_gstrings
);
1132 static void rtl8169_update_counters(struct net_device
*dev
)
1134 struct rtl8169_private
*tp
= netdev_priv(dev
);
1135 void __iomem
*ioaddr
= tp
->mmio_addr
;
1136 struct rtl8169_counters
*counters
;
1142 * Some chips are unable to dump tally counters when the receiver
1145 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1148 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1152 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1153 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1154 RTL_W32(CounterAddrLow
, cmd
);
1155 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1158 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1159 /* copy updated counters */
1160 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1166 RTL_W32(CounterAddrLow
, 0);
1167 RTL_W32(CounterAddrHigh
, 0);
1169 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1172 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1173 struct ethtool_stats
*stats
, u64
*data
)
1175 struct rtl8169_private
*tp
= netdev_priv(dev
);
1179 rtl8169_update_counters(dev
);
1181 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1182 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1183 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1184 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1185 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1186 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1187 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1188 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1189 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1190 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1191 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1192 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1193 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1196 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1200 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1205 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1206 .get_drvinfo
= rtl8169_get_drvinfo
,
1207 .get_regs_len
= rtl8169_get_regs_len
,
1208 .get_link
= ethtool_op_get_link
,
1209 .get_settings
= rtl8169_get_settings
,
1210 .set_settings
= rtl8169_set_settings
,
1211 .get_msglevel
= rtl8169_get_msglevel
,
1212 .set_msglevel
= rtl8169_set_msglevel
,
1213 .get_rx_csum
= rtl8169_get_rx_csum
,
1214 .set_rx_csum
= rtl8169_set_rx_csum
,
1215 .set_tx_csum
= ethtool_op_set_tx_csum
,
1216 .set_sg
= ethtool_op_set_sg
,
1217 .set_tso
= ethtool_op_set_tso
,
1218 .get_regs
= rtl8169_get_regs
,
1219 .get_wol
= rtl8169_get_wol
,
1220 .set_wol
= rtl8169_set_wol
,
1221 .get_strings
= rtl8169_get_strings
,
1222 .get_sset_count
= rtl8169_get_sset_count
,
1223 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1226 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1227 void __iomem
*ioaddr
)
1230 * The driver currently handles the 8168Bf and the 8168Be identically
1231 * but they can be identified more specifically through the test below
1234 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1236 * Same thing for the 8101Eb and the 8101Ec:
1238 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1246 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25
},
1249 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1250 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1251 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1252 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1253 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1254 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1255 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1256 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1257 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1260 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1261 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1262 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1263 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1266 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1267 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1268 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1269 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1270 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1271 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1272 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1273 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1274 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1275 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1276 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1277 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1278 /* FIXME: where did these entries come from ? -- FR */
1279 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1280 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1283 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1284 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1285 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1286 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1287 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1288 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1291 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1295 reg
= RTL_R32(TxConfig
);
1296 while ((reg
& p
->mask
) != p
->val
)
1298 tp
->mac_version
= p
->mac_version
;
1301 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1303 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1311 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1314 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1319 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1321 struct phy_reg phy_reg_init
[] = {
1383 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1386 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1388 struct phy_reg phy_reg_init
[] = {
1394 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1397 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1398 void __iomem
*ioaddr
)
1400 struct pci_dev
*pdev
= tp
->pci_dev
;
1401 u16 vendor_id
, device_id
;
1403 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1404 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1406 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1409 mdio_write(ioaddr
, 0x1f, 0x0001);
1410 mdio_write(ioaddr
, 0x10, 0xf01b);
1411 mdio_write(ioaddr
, 0x1f, 0x0000);
1414 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1415 void __iomem
*ioaddr
)
1417 struct phy_reg phy_reg_init
[] = {
1457 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1459 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1462 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1464 struct phy_reg phy_reg_init
[] = {
1512 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1515 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1517 struct phy_reg phy_reg_init
[] = {
1522 mdio_write(ioaddr
, 0x1f, 0x0001);
1523 mdio_patch(ioaddr
, 0x16, 1 << 0);
1525 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1528 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1530 struct phy_reg phy_reg_init
[] = {
1536 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1539 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1541 struct phy_reg phy_reg_init
[] = {
1549 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1552 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1554 struct phy_reg phy_reg_init
[] = {
1560 mdio_write(ioaddr
, 0x1f, 0x0000);
1561 mdio_patch(ioaddr
, 0x14, 1 << 5);
1562 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1564 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1567 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1569 struct phy_reg phy_reg_init
[] = {
1589 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1591 mdio_patch(ioaddr
, 0x14, 1 << 5);
1592 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1593 mdio_write(ioaddr
, 0x1f, 0x0000);
1596 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1598 struct phy_reg phy_reg_init
[] = {
1616 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1618 mdio_patch(ioaddr
, 0x16, 1 << 0);
1619 mdio_patch(ioaddr
, 0x14, 1 << 5);
1620 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1621 mdio_write(ioaddr
, 0x1f, 0x0000);
1624 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1626 struct phy_reg phy_reg_init
[] = {
1638 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1640 mdio_patch(ioaddr
, 0x16, 1 << 0);
1641 mdio_patch(ioaddr
, 0x14, 1 << 5);
1642 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1643 mdio_write(ioaddr
, 0x1f, 0x0000);
1646 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1648 rtl8168c_3_hw_phy_config(ioaddr
);
1651 static void rtl8168d_hw_phy_config(void __iomem
*ioaddr
)
1653 struct phy_reg phy_reg_init_0
[] = {
1679 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
1681 if (mdio_read(ioaddr
, 0x06) == 0xc400) {
1682 struct phy_reg phy_reg_init_1
[] = {
1714 rtl_phy_write(ioaddr
, phy_reg_init_1
,
1715 ARRAY_SIZE(phy_reg_init_1
));
1718 mdio_write(ioaddr
, 0x1f, 0x0000);
1721 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1723 struct phy_reg phy_reg_init
[] = {
1730 mdio_write(ioaddr
, 0x1f, 0x0000);
1731 mdio_patch(ioaddr
, 0x11, 1 << 12);
1732 mdio_patch(ioaddr
, 0x19, 1 << 13);
1733 mdio_patch(ioaddr
, 0x10, 1 << 15);
1735 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1738 static void rtl_hw_phy_config(struct net_device
*dev
)
1740 struct rtl8169_private
*tp
= netdev_priv(dev
);
1741 void __iomem
*ioaddr
= tp
->mmio_addr
;
1743 rtl8169_print_mac_version(tp
);
1745 switch (tp
->mac_version
) {
1746 case RTL_GIGA_MAC_VER_01
:
1748 case RTL_GIGA_MAC_VER_02
:
1749 case RTL_GIGA_MAC_VER_03
:
1750 rtl8169s_hw_phy_config(ioaddr
);
1752 case RTL_GIGA_MAC_VER_04
:
1753 rtl8169sb_hw_phy_config(ioaddr
);
1755 case RTL_GIGA_MAC_VER_05
:
1756 rtl8169scd_hw_phy_config(tp
, ioaddr
);
1758 case RTL_GIGA_MAC_VER_06
:
1759 rtl8169sce_hw_phy_config(ioaddr
);
1761 case RTL_GIGA_MAC_VER_07
:
1762 case RTL_GIGA_MAC_VER_08
:
1763 case RTL_GIGA_MAC_VER_09
:
1764 rtl8102e_hw_phy_config(ioaddr
);
1766 case RTL_GIGA_MAC_VER_11
:
1767 rtl8168bb_hw_phy_config(ioaddr
);
1769 case RTL_GIGA_MAC_VER_12
:
1770 rtl8168bef_hw_phy_config(ioaddr
);
1772 case RTL_GIGA_MAC_VER_17
:
1773 rtl8168bef_hw_phy_config(ioaddr
);
1775 case RTL_GIGA_MAC_VER_18
:
1776 rtl8168cp_1_hw_phy_config(ioaddr
);
1778 case RTL_GIGA_MAC_VER_19
:
1779 rtl8168c_1_hw_phy_config(ioaddr
);
1781 case RTL_GIGA_MAC_VER_20
:
1782 rtl8168c_2_hw_phy_config(ioaddr
);
1784 case RTL_GIGA_MAC_VER_21
:
1785 rtl8168c_3_hw_phy_config(ioaddr
);
1787 case RTL_GIGA_MAC_VER_22
:
1788 rtl8168c_4_hw_phy_config(ioaddr
);
1790 case RTL_GIGA_MAC_VER_23
:
1791 case RTL_GIGA_MAC_VER_24
:
1792 rtl8168cp_2_hw_phy_config(ioaddr
);
1794 case RTL_GIGA_MAC_VER_25
:
1795 rtl8168d_hw_phy_config(ioaddr
);
1803 static void rtl8169_phy_timer(unsigned long __opaque
)
1805 struct net_device
*dev
= (struct net_device
*)__opaque
;
1806 struct rtl8169_private
*tp
= netdev_priv(dev
);
1807 struct timer_list
*timer
= &tp
->timer
;
1808 void __iomem
*ioaddr
= tp
->mmio_addr
;
1809 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1811 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1813 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1816 spin_lock_irq(&tp
->lock
);
1818 if (tp
->phy_reset_pending(ioaddr
)) {
1820 * A busy loop could burn quite a few cycles on nowadays CPU.
1821 * Let's delay the execution of the timer for a few ticks.
1827 if (tp
->link_ok(ioaddr
))
1830 if (netif_msg_link(tp
))
1831 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1833 tp
->phy_reset_enable(ioaddr
);
1836 mod_timer(timer
, jiffies
+ timeout
);
1838 spin_unlock_irq(&tp
->lock
);
1841 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1843 struct rtl8169_private
*tp
= netdev_priv(dev
);
1844 struct timer_list
*timer
= &tp
->timer
;
1846 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1849 del_timer_sync(timer
);
1852 static inline void rtl8169_request_timer(struct net_device
*dev
)
1854 struct rtl8169_private
*tp
= netdev_priv(dev
);
1855 struct timer_list
*timer
= &tp
->timer
;
1857 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1860 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1863 #ifdef CONFIG_NET_POLL_CONTROLLER
1865 * Polling 'interrupt' - used by things like netconsole to send skbs
1866 * without having to re-enable interrupts. It's not called while
1867 * the interrupt routine is executing.
1869 static void rtl8169_netpoll(struct net_device
*dev
)
1871 struct rtl8169_private
*tp
= netdev_priv(dev
);
1872 struct pci_dev
*pdev
= tp
->pci_dev
;
1874 disable_irq(pdev
->irq
);
1875 rtl8169_interrupt(pdev
->irq
, dev
);
1876 enable_irq(pdev
->irq
);
1880 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1881 void __iomem
*ioaddr
)
1884 pci_release_regions(pdev
);
1885 pci_disable_device(pdev
);
1889 static void rtl8169_phy_reset(struct net_device
*dev
,
1890 struct rtl8169_private
*tp
)
1892 void __iomem
*ioaddr
= tp
->mmio_addr
;
1895 tp
->phy_reset_enable(ioaddr
);
1896 for (i
= 0; i
< 100; i
++) {
1897 if (!tp
->phy_reset_pending(ioaddr
))
1901 if (netif_msg_link(tp
))
1902 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1905 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1907 void __iomem
*ioaddr
= tp
->mmio_addr
;
1909 rtl_hw_phy_config(dev
);
1911 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1912 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1916 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1918 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1919 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1921 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1922 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1924 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1925 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1928 rtl8169_phy_reset(dev
, tp
);
1931 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1932 * only 8101. Don't panic.
1934 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1936 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1937 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1940 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1942 void __iomem
*ioaddr
= tp
->mmio_addr
;
1946 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1947 high
= addr
[4] | (addr
[5] << 8);
1949 spin_lock_irq(&tp
->lock
);
1951 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1953 RTL_W32(MAC4
, high
);
1954 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1956 spin_unlock_irq(&tp
->lock
);
1959 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1961 struct rtl8169_private
*tp
= netdev_priv(dev
);
1962 struct sockaddr
*addr
= p
;
1964 if (!is_valid_ether_addr(addr
->sa_data
))
1965 return -EADDRNOTAVAIL
;
1967 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1969 rtl_rar_set(tp
, dev
->dev_addr
);
1974 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1976 struct rtl8169_private
*tp
= netdev_priv(dev
);
1977 struct mii_ioctl_data
*data
= if_mii(ifr
);
1979 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
1982 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
1986 data
->phy_id
= 32; /* Internal PHY */
1990 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1994 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2000 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2005 static const struct rtl_cfg_info
{
2006 void (*hw_start
)(struct net_device
*);
2007 unsigned int region
;
2013 } rtl_cfg_infos
[] = {
2015 .hw_start
= rtl_hw_start_8169
,
2018 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2019 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2020 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2021 .features
= RTL_FEATURE_GMII
,
2022 .default_ver
= RTL_GIGA_MAC_VER_01
,
2025 .hw_start
= rtl_hw_start_8168
,
2028 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2029 TxErr
| TxOK
| RxOK
| RxErr
,
2030 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2031 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2032 .default_ver
= RTL_GIGA_MAC_VER_11
,
2035 .hw_start
= rtl_hw_start_8101
,
2038 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2039 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2040 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2041 .features
= RTL_FEATURE_MSI
,
2042 .default_ver
= RTL_GIGA_MAC_VER_13
,
2046 /* Cfg9346_Unlock assumed. */
2047 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2048 const struct rtl_cfg_info
*cfg
)
2053 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2054 if (cfg
->features
& RTL_FEATURE_MSI
) {
2055 if (pci_enable_msi(pdev
)) {
2056 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2059 msi
= RTL_FEATURE_MSI
;
2062 RTL_W8(Config2
, cfg2
);
2066 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2068 if (tp
->features
& RTL_FEATURE_MSI
) {
2069 pci_disable_msi(pdev
);
2070 tp
->features
&= ~RTL_FEATURE_MSI
;
2074 static const struct net_device_ops rtl8169_netdev_ops
= {
2075 .ndo_open
= rtl8169_open
,
2076 .ndo_stop
= rtl8169_close
,
2077 .ndo_get_stats
= rtl8169_get_stats
,
2078 .ndo_start_xmit
= rtl8169_start_xmit
,
2079 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2080 .ndo_validate_addr
= eth_validate_addr
,
2081 .ndo_change_mtu
= rtl8169_change_mtu
,
2082 .ndo_set_mac_address
= rtl_set_mac_address
,
2083 .ndo_do_ioctl
= rtl8169_ioctl
,
2084 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2085 #ifdef CONFIG_R8169_VLAN
2086 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2088 #ifdef CONFIG_NET_POLL_CONTROLLER
2089 .ndo_poll_controller
= rtl8169_netpoll
,
2094 static int __devinit
2095 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2097 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2098 const unsigned int region
= cfg
->region
;
2099 struct rtl8169_private
*tp
;
2100 struct mii_if_info
*mii
;
2101 struct net_device
*dev
;
2102 void __iomem
*ioaddr
;
2106 if (netif_msg_drv(&debug
)) {
2107 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
2108 MODULENAME
, RTL8169_VERSION
);
2111 dev
= alloc_etherdev(sizeof (*tp
));
2113 if (netif_msg_drv(&debug
))
2114 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
2119 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2120 dev
->netdev_ops
= &rtl8169_netdev_ops
;
2121 tp
= netdev_priv(dev
);
2124 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
2128 mii
->mdio_read
= rtl_mdio_read
;
2129 mii
->mdio_write
= rtl_mdio_write
;
2130 mii
->phy_id_mask
= 0x1f;
2131 mii
->reg_num_mask
= 0x1f;
2132 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
2134 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2135 rc
= pci_enable_device(pdev
);
2137 if (netif_msg_probe(tp
))
2138 dev_err(&pdev
->dev
, "enable failure\n");
2139 goto err_out_free_dev_1
;
2142 rc
= pci_set_mwi(pdev
);
2144 goto err_out_disable_2
;
2146 /* make sure PCI base addr 1 is MMIO */
2147 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
2148 if (netif_msg_probe(tp
)) {
2150 "region #%d not an MMIO resource, aborting\n",
2157 /* check for weird/broken PCI region reporting */
2158 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
2159 if (netif_msg_probe(tp
)) {
2161 "Invalid PCI region size(s), aborting\n");
2167 rc
= pci_request_regions(pdev
, MODULENAME
);
2169 if (netif_msg_probe(tp
))
2170 dev_err(&pdev
->dev
, "could not request regions.\n");
2174 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
2176 if ((sizeof(dma_addr_t
) > 4) &&
2177 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
2178 tp
->cp_cmd
|= PCIDAC
;
2179 dev
->features
|= NETIF_F_HIGHDMA
;
2181 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2183 if (netif_msg_probe(tp
)) {
2185 "DMA configuration failed.\n");
2187 goto err_out_free_res_4
;
2191 /* ioremap MMIO region */
2192 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
2194 if (netif_msg_probe(tp
))
2195 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
2197 goto err_out_free_res_4
;
2200 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2201 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
2202 dev_info(&pdev
->dev
, "no PCI Express capability\n");
2204 RTL_W16(IntrMask
, 0x0000);
2206 /* Soft reset the chip. */
2207 RTL_W8(ChipCmd
, CmdReset
);
2209 /* Check that the chip has finished the reset. */
2210 for (i
= 0; i
< 100; i
++) {
2211 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2213 msleep_interruptible(1);
2216 RTL_W16(IntrStatus
, 0xffff);
2218 pci_set_master(pdev
);
2220 /* Identify chip attached to board */
2221 rtl8169_get_mac_version(tp
, ioaddr
);
2223 /* Use appropriate default if unknown */
2224 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2225 if (netif_msg_probe(tp
)) {
2226 dev_notice(&pdev
->dev
,
2227 "unknown MAC, using family default\n");
2229 tp
->mac_version
= cfg
->default_ver
;
2232 rtl8169_print_mac_version(tp
);
2234 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
2235 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
2238 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
2240 "driver bug, MAC version not found in rtl_chip_info\n");
2245 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2246 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
2247 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
2248 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
2249 tp
->features
|= RTL_FEATURE_WOL
;
2250 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
2251 tp
->features
|= RTL_FEATURE_WOL
;
2252 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
2253 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2255 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
2256 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
2257 tp
->set_speed
= rtl8169_set_speed_tbi
;
2258 tp
->get_settings
= rtl8169_gset_tbi
;
2259 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
2260 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
2261 tp
->link_ok
= rtl8169_tbi_link_ok
;
2262 tp
->do_ioctl
= rtl_tbi_ioctl
;
2264 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2266 tp
->set_speed
= rtl8169_set_speed_xmii
;
2267 tp
->get_settings
= rtl8169_gset_xmii
;
2268 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2269 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2270 tp
->link_ok
= rtl8169_xmii_link_ok
;
2271 tp
->do_ioctl
= rtl_xmii_ioctl
;
2274 spin_lock_init(&tp
->lock
);
2276 tp
->mmio_addr
= ioaddr
;
2278 /* Get MAC address */
2279 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2280 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2281 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2283 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2284 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2285 dev
->irq
= pdev
->irq
;
2286 dev
->base_addr
= (unsigned long) ioaddr
;
2288 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2290 #ifdef CONFIG_R8169_VLAN
2291 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2294 tp
->intr_mask
= 0xffff;
2295 tp
->align
= cfg
->align
;
2296 tp
->hw_start
= cfg
->hw_start
;
2297 tp
->intr_event
= cfg
->intr_event
;
2298 tp
->napi_event
= cfg
->napi_event
;
2300 init_timer(&tp
->timer
);
2301 tp
->timer
.data
= (unsigned long) dev
;
2302 tp
->timer
.function
= rtl8169_phy_timer
;
2304 rc
= register_netdev(dev
);
2308 pci_set_drvdata(pdev
, dev
);
2310 if (netif_msg_probe(tp
)) {
2311 u32 xid
= RTL_R32(TxConfig
) & 0x9cf0f8ff;
2313 printk(KERN_INFO
"%s: %s at 0x%lx, "
2314 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2315 "XID %08x IRQ %d\n",
2317 rtl_chip_info
[tp
->chipset
].name
,
2319 dev
->dev_addr
[0], dev
->dev_addr
[1],
2320 dev
->dev_addr
[2], dev
->dev_addr
[3],
2321 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2324 rtl8169_init_phy(dev
, tp
);
2325 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2331 rtl_disable_msi(pdev
, tp
);
2334 pci_release_regions(pdev
);
2336 pci_clear_mwi(pdev
);
2338 pci_disable_device(pdev
);
2344 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2346 struct net_device
*dev
= pci_get_drvdata(pdev
);
2347 struct rtl8169_private
*tp
= netdev_priv(dev
);
2349 flush_scheduled_work();
2351 unregister_netdev(dev
);
2352 rtl_disable_msi(pdev
, tp
);
2353 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2354 pci_set_drvdata(pdev
, NULL
);
2357 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2358 struct net_device
*dev
)
2360 unsigned int mtu
= dev
->mtu
;
2362 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2365 static int rtl8169_open(struct net_device
*dev
)
2367 struct rtl8169_private
*tp
= netdev_priv(dev
);
2368 struct pci_dev
*pdev
= tp
->pci_dev
;
2369 int retval
= -ENOMEM
;
2372 rtl8169_set_rxbufsize(tp
, dev
);
2375 * Rx and Tx desscriptors needs 256 bytes alignment.
2376 * pci_alloc_consistent provides more.
2378 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2380 if (!tp
->TxDescArray
)
2383 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2385 if (!tp
->RxDescArray
)
2388 retval
= rtl8169_init_ring(dev
);
2392 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2396 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2397 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2400 goto err_release_ring_2
;
2402 napi_enable(&tp
->napi
);
2406 rtl8169_request_timer(dev
);
2408 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2413 rtl8169_rx_clear(tp
);
2415 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2418 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2423 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2425 /* Disable interrupts */
2426 rtl8169_irq_mask_and_ack(ioaddr
);
2428 /* Reset the chipset */
2429 RTL_W8(ChipCmd
, CmdReset
);
2435 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2437 void __iomem
*ioaddr
= tp
->mmio_addr
;
2438 u32 cfg
= rtl8169_rx_config
;
2440 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2441 RTL_W32(RxConfig
, cfg
);
2443 /* Set DMA burst size and Interframe Gap Time */
2444 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2445 (InterFrameGap
<< TxInterFrameGapShift
));
2448 static void rtl_hw_start(struct net_device
*dev
)
2450 struct rtl8169_private
*tp
= netdev_priv(dev
);
2451 void __iomem
*ioaddr
= tp
->mmio_addr
;
2454 /* Soft reset the chip. */
2455 RTL_W8(ChipCmd
, CmdReset
);
2457 /* Check that the chip has finished the reset. */
2458 for (i
= 0; i
< 100; i
++) {
2459 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2461 msleep_interruptible(1);
2466 netif_start_queue(dev
);
2470 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2471 void __iomem
*ioaddr
)
2474 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2475 * register to be written before TxDescAddrLow to work.
2476 * Switching from MMIO to I/O access fixes the issue as well.
2478 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2479 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
2480 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2481 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
2484 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2488 cmd
= RTL_R16(CPlusCmd
);
2489 RTL_W16(CPlusCmd
, cmd
);
2493 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
2495 /* Low hurts. Let's disable the filtering. */
2496 RTL_W16(RxMaxSize
, rx_buf_sz
);
2499 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2506 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2507 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2508 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2509 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2514 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2515 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2516 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2517 RTL_W32(0x7c, p
->val
);
2523 static void rtl_hw_start_8169(struct net_device
*dev
)
2525 struct rtl8169_private
*tp
= netdev_priv(dev
);
2526 void __iomem
*ioaddr
= tp
->mmio_addr
;
2527 struct pci_dev
*pdev
= tp
->pci_dev
;
2529 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2530 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2531 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2534 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2535 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2536 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2537 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2538 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2539 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2541 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2543 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2545 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2546 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2547 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2548 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2549 rtl_set_rx_tx_config_registers(tp
);
2551 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2553 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2554 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2555 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2556 "Bit-3 and bit-14 MUST be 1\n");
2557 tp
->cp_cmd
|= (1 << 14);
2560 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2562 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2565 * Undocumented corner. Supposedly:
2566 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2568 RTL_W16(IntrMitigate
, 0x0000);
2570 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2572 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2573 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2574 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2575 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2576 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2577 rtl_set_rx_tx_config_registers(tp
);
2580 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2582 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2585 RTL_W32(RxMissed
, 0);
2587 rtl_set_rx_mode(dev
);
2589 /* no early-rx interrupts */
2590 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2592 /* Enable all known interrupts by setting the interrupt mask. */
2593 RTL_W16(IntrMask
, tp
->intr_event
);
2596 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2598 struct net_device
*dev
= pci_get_drvdata(pdev
);
2599 struct rtl8169_private
*tp
= netdev_priv(dev
);
2600 int cap
= tp
->pcie_cap
;
2605 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2606 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2607 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2611 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2615 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2616 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2620 unsigned int offset
;
2625 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2630 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2631 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2636 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
2638 struct net_device
*dev
= pci_get_drvdata(pdev
);
2639 struct rtl8169_private
*tp
= netdev_priv(dev
);
2640 int cap
= tp
->pcie_cap
;
2645 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
2646 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2647 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
2651 #define R8168_CPCMD_QUIRK_MASK (\
2662 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2664 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2666 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2668 rtl_tx_performance_tweak(pdev
,
2669 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2672 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2674 rtl_hw_start_8168bb(ioaddr
, pdev
);
2676 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2678 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
2681 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2683 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
2685 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2687 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2689 rtl_disable_clock_request(pdev
);
2691 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2694 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2696 static struct ephy_info e_info_8168cp
[] = {
2697 { 0x01, 0, 0x0001 },
2698 { 0x02, 0x0800, 0x1000 },
2699 { 0x03, 0, 0x0042 },
2700 { 0x06, 0x0080, 0x0000 },
2704 rtl_csi_access_enable(ioaddr
);
2706 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
2708 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2711 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2713 rtl_csi_access_enable(ioaddr
);
2715 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2717 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2719 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2722 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2724 rtl_csi_access_enable(ioaddr
);
2726 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2729 RTL_W8(DBG_REG
, 0x20);
2731 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2733 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2735 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2738 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2740 static struct ephy_info e_info_8168c_1
[] = {
2741 { 0x02, 0x0800, 0x1000 },
2742 { 0x03, 0, 0x0002 },
2743 { 0x06, 0x0080, 0x0000 }
2746 rtl_csi_access_enable(ioaddr
);
2748 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2750 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
2752 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2755 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2757 static struct ephy_info e_info_8168c_2
[] = {
2758 { 0x01, 0, 0x0001 },
2759 { 0x03, 0x0400, 0x0220 }
2762 rtl_csi_access_enable(ioaddr
);
2764 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
2766 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2769 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2771 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2774 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2776 rtl_csi_access_enable(ioaddr
);
2778 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2781 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2783 rtl_csi_access_enable(ioaddr
);
2785 rtl_disable_clock_request(pdev
);
2787 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2789 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2791 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2794 static void rtl_hw_start_8168(struct net_device
*dev
)
2796 struct rtl8169_private
*tp
= netdev_priv(dev
);
2797 void __iomem
*ioaddr
= tp
->mmio_addr
;
2798 struct pci_dev
*pdev
= tp
->pci_dev
;
2800 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2802 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2804 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2806 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2808 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2810 RTL_W16(IntrMitigate
, 0x5151);
2812 /* Work around for RxFIFO overflow. */
2813 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2814 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2815 tp
->intr_event
&= ~RxOverflow
;
2818 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2820 rtl_set_rx_mode(dev
);
2822 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2823 (InterFrameGap
<< TxInterFrameGapShift
));
2827 switch (tp
->mac_version
) {
2828 case RTL_GIGA_MAC_VER_11
:
2829 rtl_hw_start_8168bb(ioaddr
, pdev
);
2832 case RTL_GIGA_MAC_VER_12
:
2833 case RTL_GIGA_MAC_VER_17
:
2834 rtl_hw_start_8168bef(ioaddr
, pdev
);
2837 case RTL_GIGA_MAC_VER_18
:
2838 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
2841 case RTL_GIGA_MAC_VER_19
:
2842 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2845 case RTL_GIGA_MAC_VER_20
:
2846 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2849 case RTL_GIGA_MAC_VER_21
:
2850 rtl_hw_start_8168c_3(ioaddr
, pdev
);
2853 case RTL_GIGA_MAC_VER_22
:
2854 rtl_hw_start_8168c_4(ioaddr
, pdev
);
2857 case RTL_GIGA_MAC_VER_23
:
2858 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
2861 case RTL_GIGA_MAC_VER_24
:
2862 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
2865 case RTL_GIGA_MAC_VER_25
:
2866 rtl_hw_start_8168d(ioaddr
, pdev
);
2870 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2871 dev
->name
, tp
->mac_version
);
2875 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2877 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2879 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2881 RTL_W16(IntrMask
, tp
->intr_event
);
2884 #define R810X_CPCMD_QUIRK_MASK (\
2896 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2898 static struct ephy_info e_info_8102e_1
[] = {
2899 { 0x01, 0, 0x6e65 },
2900 { 0x02, 0, 0x091f },
2901 { 0x03, 0, 0xc2f9 },
2902 { 0x06, 0, 0xafb5 },
2903 { 0x07, 0, 0x0e00 },
2904 { 0x19, 0, 0xec80 },
2905 { 0x01, 0, 0x2e65 },
2910 rtl_csi_access_enable(ioaddr
);
2912 RTL_W8(DBG_REG
, FIX_NAK_1
);
2914 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2917 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2918 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2920 cfg1
= RTL_R8(Config1
);
2921 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2922 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2924 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2926 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2929 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2931 rtl_csi_access_enable(ioaddr
);
2933 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2935 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2936 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2938 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2941 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2943 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2945 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2948 static void rtl_hw_start_8101(struct net_device
*dev
)
2950 struct rtl8169_private
*tp
= netdev_priv(dev
);
2951 void __iomem
*ioaddr
= tp
->mmio_addr
;
2952 struct pci_dev
*pdev
= tp
->pci_dev
;
2954 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2955 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2956 int cap
= tp
->pcie_cap
;
2959 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2960 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2964 switch (tp
->mac_version
) {
2965 case RTL_GIGA_MAC_VER_07
:
2966 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2969 case RTL_GIGA_MAC_VER_08
:
2970 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2973 case RTL_GIGA_MAC_VER_09
:
2974 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2978 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2980 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2982 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2984 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2986 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2988 RTL_W16(IntrMitigate
, 0x0000);
2990 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2992 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2993 rtl_set_rx_tx_config_registers(tp
);
2995 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2999 rtl_set_rx_mode(dev
);
3001 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3003 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3005 RTL_W16(IntrMask
, tp
->intr_event
);
3008 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3010 struct rtl8169_private
*tp
= netdev_priv(dev
);
3013 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3018 if (!netif_running(dev
))
3023 rtl8169_set_rxbufsize(tp
, dev
);
3025 ret
= rtl8169_init_ring(dev
);
3029 napi_enable(&tp
->napi
);
3033 rtl8169_request_timer(dev
);
3039 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3041 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3042 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3045 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
3046 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
3048 struct pci_dev
*pdev
= tp
->pci_dev
;
3050 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
3051 PCI_DMA_FROMDEVICE
);
3052 dev_kfree_skb(*sk_buff
);
3054 rtl8169_make_unusable_by_asic(desc
);
3057 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3059 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3061 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3064 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3067 desc
->addr
= cpu_to_le64(mapping
);
3069 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3072 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
3073 struct net_device
*dev
,
3074 struct RxDesc
*desc
, int rx_buf_sz
,
3077 struct sk_buff
*skb
;
3081 pad
= align
? align
: NET_IP_ALIGN
;
3083 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
3087 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
3089 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
3090 PCI_DMA_FROMDEVICE
);
3092 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
3097 rtl8169_make_unusable_by_asic(desc
);
3101 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
3105 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
3106 if (tp
->Rx_skbuff
[i
]) {
3107 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
3108 tp
->RxDescArray
+ i
);
3113 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
3118 for (cur
= start
; end
- cur
!= 0; cur
++) {
3119 struct sk_buff
*skb
;
3120 unsigned int i
= cur
% NUM_RX_DESC
;
3122 WARN_ON((s32
)(end
- cur
) < 0);
3124 if (tp
->Rx_skbuff
[i
])
3127 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
3128 tp
->RxDescArray
+ i
,
3129 tp
->rx_buf_sz
, tp
->align
);
3133 tp
->Rx_skbuff
[i
] = skb
;
3138 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
3140 desc
->opts1
|= cpu_to_le32(RingEnd
);
3143 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3145 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3148 static int rtl8169_init_ring(struct net_device
*dev
)
3150 struct rtl8169_private
*tp
= netdev_priv(dev
);
3152 rtl8169_init_ring_indexes(tp
);
3154 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
3155 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
3157 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
3160 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
3165 rtl8169_rx_clear(tp
);
3169 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
3170 struct TxDesc
*desc
)
3172 unsigned int len
= tx_skb
->len
;
3174 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
3181 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
3185 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
3186 unsigned int entry
= i
% NUM_TX_DESC
;
3187 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3188 unsigned int len
= tx_skb
->len
;
3191 struct sk_buff
*skb
= tx_skb
->skb
;
3193 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
3194 tp
->TxDescArray
+ entry
);
3199 tp
->dev
->stats
.tx_dropped
++;
3202 tp
->cur_tx
= tp
->dirty_tx
= 0;
3205 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
3207 struct rtl8169_private
*tp
= netdev_priv(dev
);
3209 PREPARE_DELAYED_WORK(&tp
->task
, task
);
3210 schedule_delayed_work(&tp
->task
, 4);
3213 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
3215 struct rtl8169_private
*tp
= netdev_priv(dev
);
3216 void __iomem
*ioaddr
= tp
->mmio_addr
;
3218 synchronize_irq(dev
->irq
);
3220 /* Wait for any pending NAPI task to complete */
3221 napi_disable(&tp
->napi
);
3223 rtl8169_irq_mask_and_ack(ioaddr
);
3225 tp
->intr_mask
= 0xffff;
3226 RTL_W16(IntrMask
, tp
->intr_event
);
3227 napi_enable(&tp
->napi
);
3230 static void rtl8169_reinit_task(struct work_struct
*work
)
3232 struct rtl8169_private
*tp
=
3233 container_of(work
, struct rtl8169_private
, task
.work
);
3234 struct net_device
*dev
= tp
->dev
;
3239 if (!netif_running(dev
))
3242 rtl8169_wait_for_quiescence(dev
);
3245 ret
= rtl8169_open(dev
);
3246 if (unlikely(ret
< 0)) {
3247 if (net_ratelimit() && netif_msg_drv(tp
)) {
3248 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
3249 " Rescheduling.\n", dev
->name
, ret
);
3251 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3258 static void rtl8169_reset_task(struct work_struct
*work
)
3260 struct rtl8169_private
*tp
=
3261 container_of(work
, struct rtl8169_private
, task
.work
);
3262 struct net_device
*dev
= tp
->dev
;
3266 if (!netif_running(dev
))
3269 rtl8169_wait_for_quiescence(dev
);
3271 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
3272 rtl8169_tx_clear(tp
);
3274 if (tp
->dirty_rx
== tp
->cur_rx
) {
3275 rtl8169_init_ring_indexes(tp
);
3277 netif_wake_queue(dev
);
3278 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3280 if (net_ratelimit() && netif_msg_intr(tp
)) {
3281 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
3284 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3291 static void rtl8169_tx_timeout(struct net_device
*dev
)
3293 struct rtl8169_private
*tp
= netdev_priv(dev
);
3295 rtl8169_hw_reset(tp
->mmio_addr
);
3297 /* Let's wait a bit while any (async) irq lands on */
3298 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3301 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
3304 struct skb_shared_info
*info
= skb_shinfo(skb
);
3305 unsigned int cur_frag
, entry
;
3306 struct TxDesc
* uninitialized_var(txd
);
3309 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
3310 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
3315 entry
= (entry
+ 1) % NUM_TX_DESC
;
3317 txd
= tp
->TxDescArray
+ entry
;
3319 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
3320 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
3322 /* anti gcc 2.95.3 bugware (sic) */
3323 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3325 txd
->opts1
= cpu_to_le32(status
);
3326 txd
->addr
= cpu_to_le64(mapping
);
3328 tp
->tx_skb
[entry
].len
= len
;
3332 tp
->tx_skb
[entry
].skb
= skb
;
3333 txd
->opts1
|= cpu_to_le32(LastFrag
);
3339 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
3341 if (dev
->features
& NETIF_F_TSO
) {
3342 u32 mss
= skb_shinfo(skb
)->gso_size
;
3345 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
3347 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3348 const struct iphdr
*ip
= ip_hdr(skb
);
3350 if (ip
->protocol
== IPPROTO_TCP
)
3351 return IPCS
| TCPCS
;
3352 else if (ip
->protocol
== IPPROTO_UDP
)
3353 return IPCS
| UDPCS
;
3354 WARN_ON(1); /* we need a WARN() */
3359 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
3360 struct net_device
*dev
)
3362 struct rtl8169_private
*tp
= netdev_priv(dev
);
3363 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
3364 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
3365 void __iomem
*ioaddr
= tp
->mmio_addr
;
3370 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
3371 if (netif_msg_drv(tp
)) {
3373 "%s: BUG! Tx Ring full when queue awake!\n",
3379 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
3382 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
3384 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
3386 len
= skb_headlen(skb
);
3390 opts1
|= FirstFrag
| LastFrag
;
3391 tp
->tx_skb
[entry
].skb
= skb
;
3394 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3396 tp
->tx_skb
[entry
].len
= len
;
3397 txd
->addr
= cpu_to_le64(mapping
);
3398 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3402 /* anti gcc 2.95.3 bugware (sic) */
3403 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3404 txd
->opts1
= cpu_to_le32(status
);
3406 tp
->cur_tx
+= frags
+ 1;
3410 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3412 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3413 netif_stop_queue(dev
);
3415 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3416 netif_wake_queue(dev
);
3420 return NETDEV_TX_OK
;
3423 netif_stop_queue(dev
);
3424 dev
->stats
.tx_dropped
++;
3425 return NETDEV_TX_BUSY
;
3428 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3430 struct rtl8169_private
*tp
= netdev_priv(dev
);
3431 struct pci_dev
*pdev
= tp
->pci_dev
;
3432 void __iomem
*ioaddr
= tp
->mmio_addr
;
3433 u16 pci_status
, pci_cmd
;
3435 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3436 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3438 if (netif_msg_intr(tp
)) {
3440 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3441 dev
->name
, pci_cmd
, pci_status
);
3445 * The recovery sequence below admits a very elaborated explanation:
3446 * - it seems to work;
3447 * - I did not see what else could be done;
3448 * - it makes iop3xx happy.
3450 * Feel free to adjust to your needs.
3452 if (pdev
->broken_parity_status
)
3453 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3455 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3457 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3459 pci_write_config_word(pdev
, PCI_STATUS
,
3460 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3461 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3462 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3464 /* The infamous DAC f*ckup only happens at boot time */
3465 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3466 if (netif_msg_intr(tp
))
3467 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3468 tp
->cp_cmd
&= ~PCIDAC
;
3469 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3470 dev
->features
&= ~NETIF_F_HIGHDMA
;
3473 rtl8169_hw_reset(ioaddr
);
3475 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3478 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3479 struct rtl8169_private
*tp
,
3480 void __iomem
*ioaddr
)
3482 unsigned int dirty_tx
, tx_left
;
3484 dirty_tx
= tp
->dirty_tx
;
3486 tx_left
= tp
->cur_tx
- dirty_tx
;
3488 while (tx_left
> 0) {
3489 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3490 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3491 u32 len
= tx_skb
->len
;
3495 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3496 if (status
& DescOwn
)
3499 dev
->stats
.tx_bytes
+= len
;
3500 dev
->stats
.tx_packets
++;
3502 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3504 if (status
& LastFrag
) {
3505 dev_kfree_skb(tx_skb
->skb
);
3512 if (tp
->dirty_tx
!= dirty_tx
) {
3513 tp
->dirty_tx
= dirty_tx
;
3515 if (netif_queue_stopped(dev
) &&
3516 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3517 netif_wake_queue(dev
);
3520 * 8168 hack: TxPoll requests are lost when the Tx packets are
3521 * too close. Let's kick an extra TxPoll request when a burst
3522 * of start_xmit activity is detected (if it is not detected,
3523 * it is slow enough). -- FR
3526 if (tp
->cur_tx
!= dirty_tx
)
3527 RTL_W8(TxPoll
, NPQ
);
3531 static inline int rtl8169_fragmented_frame(u32 status
)
3533 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3536 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3538 u32 opts1
= le32_to_cpu(desc
->opts1
);
3539 u32 status
= opts1
& RxProtoMask
;
3541 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3542 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3543 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3544 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3546 skb
->ip_summed
= CHECKSUM_NONE
;
3549 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3550 struct rtl8169_private
*tp
, int pkt_size
,
3553 struct sk_buff
*skb
;
3556 if (pkt_size
>= rx_copybreak
)
3559 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3563 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3564 PCI_DMA_FROMDEVICE
);
3565 skb_reserve(skb
, NET_IP_ALIGN
);
3566 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3573 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3574 struct rtl8169_private
*tp
,
3575 void __iomem
*ioaddr
, u32 budget
)
3577 unsigned int cur_rx
, rx_left
;
3578 unsigned int delta
, count
;
3580 cur_rx
= tp
->cur_rx
;
3581 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3582 rx_left
= min(rx_left
, budget
);
3584 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3585 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3586 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3590 status
= le32_to_cpu(desc
->opts1
);
3592 if (status
& DescOwn
)
3594 if (unlikely(status
& RxRES
)) {
3595 if (netif_msg_rx_err(tp
)) {
3597 "%s: Rx ERROR. status = %08x\n",
3600 dev
->stats
.rx_errors
++;
3601 if (status
& (RxRWT
| RxRUNT
))
3602 dev
->stats
.rx_length_errors
++;
3604 dev
->stats
.rx_crc_errors
++;
3605 if (status
& RxFOVF
) {
3606 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3607 dev
->stats
.rx_fifo_errors
++;
3609 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3611 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3612 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3613 int pkt_size
= (status
& 0x00001FFF) - 4;
3614 struct pci_dev
*pdev
= tp
->pci_dev
;
3617 * The driver does not support incoming fragmented
3618 * frames. They are seen as a symptom of over-mtu
3621 if (unlikely(rtl8169_fragmented_frame(status
))) {
3622 dev
->stats
.rx_dropped
++;
3623 dev
->stats
.rx_length_errors
++;
3624 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3628 rtl8169_rx_csum(skb
, desc
);
3630 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3631 pci_dma_sync_single_for_device(pdev
, addr
,
3632 pkt_size
, PCI_DMA_FROMDEVICE
);
3633 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3635 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3636 PCI_DMA_FROMDEVICE
);
3637 tp
->Rx_skbuff
[entry
] = NULL
;
3640 skb_put(skb
, pkt_size
);
3641 skb
->protocol
= eth_type_trans(skb
, dev
);
3643 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3644 netif_receive_skb(skb
);
3646 dev
->stats
.rx_bytes
+= pkt_size
;
3647 dev
->stats
.rx_packets
++;
3650 /* Work around for AMD plateform. */
3651 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3652 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3658 count
= cur_rx
- tp
->cur_rx
;
3659 tp
->cur_rx
= cur_rx
;
3661 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3662 if (!delta
&& count
&& netif_msg_intr(tp
))
3663 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3664 tp
->dirty_rx
+= delta
;
3667 * FIXME: until there is periodic timer to try and refill the ring,
3668 * a temporary shortage may definitely kill the Rx process.
3669 * - disable the asic to try and avoid an overflow and kick it again
3671 * - how do others driver handle this condition (Uh oh...).
3673 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3674 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3679 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3681 struct net_device
*dev
= dev_instance
;
3682 struct rtl8169_private
*tp
= netdev_priv(dev
);
3683 void __iomem
*ioaddr
= tp
->mmio_addr
;
3687 /* loop handling interrupts until we have no new ones or
3688 * we hit a invalid/hotplug case.
3690 status
= RTL_R16(IntrStatus
);
3691 while (status
&& status
!= 0xffff) {
3694 /* Handle all of the error cases first. These will reset
3695 * the chip, so just exit the loop.
3697 if (unlikely(!netif_running(dev
))) {
3698 rtl8169_asic_down(ioaddr
);
3702 /* Work around for rx fifo overflow */
3703 if (unlikely(status
& RxFIFOOver
) &&
3704 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3705 netif_stop_queue(dev
);
3706 rtl8169_tx_timeout(dev
);
3710 if (unlikely(status
& SYSErr
)) {
3711 rtl8169_pcierr_interrupt(dev
);
3715 if (status
& LinkChg
)
3716 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3718 /* We need to see the lastest version of tp->intr_mask to
3719 * avoid ignoring an MSI interrupt and having to wait for
3720 * another event which may never come.
3723 if (status
& tp
->intr_mask
& tp
->napi_event
) {
3724 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3725 tp
->intr_mask
= ~tp
->napi_event
;
3727 if (likely(napi_schedule_prep(&tp
->napi
)))
3728 __napi_schedule(&tp
->napi
);
3729 else if (netif_msg_intr(tp
)) {
3730 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3735 /* We only get a new MSI interrupt when all active irq
3736 * sources on the chip have been acknowledged. So, ack
3737 * everything we've seen and check if new sources have become
3738 * active to avoid blocking all interrupts from the chip.
3741 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3742 status
= RTL_R16(IntrStatus
);
3745 return IRQ_RETVAL(handled
);
3748 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3750 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3751 struct net_device
*dev
= tp
->dev
;
3752 void __iomem
*ioaddr
= tp
->mmio_addr
;
3755 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3756 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3758 if (work_done
< budget
) {
3759 napi_complete(napi
);
3761 /* We need for force the visibility of tp->intr_mask
3762 * for other CPUs, as we can loose an MSI interrupt
3763 * and potentially wait for a retransmit timeout if we don't.
3764 * The posted write to IntrMask is safe, as it will
3765 * eventually make it to the chip and we won't loose anything
3768 tp
->intr_mask
= 0xffff;
3770 RTL_W16(IntrMask
, tp
->intr_event
);
3776 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3778 struct rtl8169_private
*tp
= netdev_priv(dev
);
3780 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3783 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3784 RTL_W32(RxMissed
, 0);
3787 static void rtl8169_down(struct net_device
*dev
)
3789 struct rtl8169_private
*tp
= netdev_priv(dev
);
3790 void __iomem
*ioaddr
= tp
->mmio_addr
;
3791 unsigned int intrmask
;
3793 rtl8169_delete_timer(dev
);
3795 netif_stop_queue(dev
);
3797 napi_disable(&tp
->napi
);
3800 spin_lock_irq(&tp
->lock
);
3802 rtl8169_asic_down(ioaddr
);
3804 rtl8169_rx_missed(dev
, ioaddr
);
3806 spin_unlock_irq(&tp
->lock
);
3808 synchronize_irq(dev
->irq
);
3810 /* Give a racing hard_start_xmit a few cycles to complete. */
3811 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3814 * And now for the 50k$ question: are IRQ disabled or not ?
3816 * Two paths lead here:
3818 * -> netif_running() is available to sync the current code and the
3819 * IRQ handler. See rtl8169_interrupt for details.
3820 * 2) dev->change_mtu
3821 * -> rtl8169_poll can not be issued again and re-enable the
3822 * interruptions. Let's simply issue the IRQ down sequence again.
3824 * No loop if hotpluged or major error (0xffff).
3826 intrmask
= RTL_R16(IntrMask
);
3827 if (intrmask
&& (intrmask
!= 0xffff))
3830 rtl8169_tx_clear(tp
);
3832 rtl8169_rx_clear(tp
);
3835 static int rtl8169_close(struct net_device
*dev
)
3837 struct rtl8169_private
*tp
= netdev_priv(dev
);
3838 struct pci_dev
*pdev
= tp
->pci_dev
;
3840 /* update counters before going down */
3841 rtl8169_update_counters(dev
);
3845 free_irq(dev
->irq
, dev
);
3847 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3849 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3851 tp
->TxDescArray
= NULL
;
3852 tp
->RxDescArray
= NULL
;
3857 static void rtl_set_rx_mode(struct net_device
*dev
)
3859 struct rtl8169_private
*tp
= netdev_priv(dev
);
3860 void __iomem
*ioaddr
= tp
->mmio_addr
;
3861 unsigned long flags
;
3862 u32 mc_filter
[2]; /* Multicast hash filter */
3866 if (dev
->flags
& IFF_PROMISC
) {
3867 /* Unconditionally log net taps. */
3868 if (netif_msg_link(tp
)) {
3869 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3873 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3875 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3876 } else if ((dev
->mc_count
> multicast_filter_limit
)
3877 || (dev
->flags
& IFF_ALLMULTI
)) {
3878 /* Too many to filter perfectly -- accept all multicasts. */
3879 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3880 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3882 struct dev_mc_list
*mclist
;
3885 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3886 mc_filter
[1] = mc_filter
[0] = 0;
3887 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3888 i
++, mclist
= mclist
->next
) {
3889 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3890 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3891 rx_mode
|= AcceptMulticast
;
3895 spin_lock_irqsave(&tp
->lock
, flags
);
3897 tmp
= rtl8169_rx_config
| rx_mode
|
3898 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3900 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3901 u32 data
= mc_filter
[0];
3903 mc_filter
[0] = swab32(mc_filter
[1]);
3904 mc_filter
[1] = swab32(data
);
3907 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3908 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3910 RTL_W32(RxConfig
, tmp
);
3912 spin_unlock_irqrestore(&tp
->lock
, flags
);
3916 * rtl8169_get_stats - Get rtl8169 read/write statistics
3917 * @dev: The Ethernet Device to get statistics for
3919 * Get TX/RX statistics for rtl8169
3921 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3923 struct rtl8169_private
*tp
= netdev_priv(dev
);
3924 void __iomem
*ioaddr
= tp
->mmio_addr
;
3925 unsigned long flags
;
3927 if (netif_running(dev
)) {
3928 spin_lock_irqsave(&tp
->lock
, flags
);
3929 rtl8169_rx_missed(dev
, ioaddr
);
3930 spin_unlock_irqrestore(&tp
->lock
, flags
);
3936 static void rtl8169_net_suspend(struct net_device
*dev
)
3938 if (!netif_running(dev
))
3941 netif_device_detach(dev
);
3942 netif_stop_queue(dev
);
3947 static int rtl8169_suspend(struct device
*device
)
3949 struct pci_dev
*pdev
= to_pci_dev(device
);
3950 struct net_device
*dev
= pci_get_drvdata(pdev
);
3952 rtl8169_net_suspend(dev
);
3957 static int rtl8169_resume(struct device
*device
)
3959 struct pci_dev
*pdev
= to_pci_dev(device
);
3960 struct net_device
*dev
= pci_get_drvdata(pdev
);
3962 if (!netif_running(dev
))
3965 netif_device_attach(dev
);
3967 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3972 static struct dev_pm_ops rtl8169_pm_ops
= {
3973 .suspend
= rtl8169_suspend
,
3974 .resume
= rtl8169_resume
,
3975 .freeze
= rtl8169_suspend
,
3976 .thaw
= rtl8169_resume
,
3977 .poweroff
= rtl8169_suspend
,
3978 .restore
= rtl8169_resume
,
3981 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
3983 #else /* !CONFIG_PM */
3985 #define RTL8169_PM_OPS NULL
3987 #endif /* !CONFIG_PM */
3989 static void rtl_shutdown(struct pci_dev
*pdev
)
3991 struct net_device
*dev
= pci_get_drvdata(pdev
);
3992 struct rtl8169_private
*tp
= netdev_priv(dev
);
3993 void __iomem
*ioaddr
= tp
->mmio_addr
;
3995 rtl8169_net_suspend(dev
);
3997 spin_lock_irq(&tp
->lock
);
3999 rtl8169_asic_down(ioaddr
);
4001 spin_unlock_irq(&tp
->lock
);
4003 if (system_state
== SYSTEM_POWER_OFF
) {
4004 /* WoL fails with some 8168 when the receiver is disabled. */
4005 if (tp
->features
& RTL_FEATURE_WOL
) {
4006 pci_clear_master(pdev
);
4008 RTL_W8(ChipCmd
, CmdRxEnb
);
4013 pci_wake_from_d3(pdev
, true);
4014 pci_set_power_state(pdev
, PCI_D3hot
);
4018 static struct pci_driver rtl8169_pci_driver
= {
4020 .id_table
= rtl8169_pci_tbl
,
4021 .probe
= rtl8169_init_one
,
4022 .remove
= __devexit_p(rtl8169_remove_one
),
4023 .shutdown
= rtl_shutdown
,
4024 .driver
.pm
= RTL8169_PM_OPS
,
4027 static int __init
rtl8169_init_module(void)
4029 return pci_register_driver(&rtl8169_pci_driver
);
4032 static void __exit
rtl8169_cleanup_module(void)
4034 pci_unregister_driver(&rtl8169_pci_driver
);
4037 module_init(rtl8169_init_module
);
4038 module_exit(rtl8169_cleanup_module
);