2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit
= 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE
= 0x00,
94 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
95 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25
= 0x19 // 8168D
121 #define _R(NAME,MAC,MASK) \
122 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
124 static const struct {
127 u32 RxConfigMask
; /* Clears the bits supported by this chip */
128 } rtl_chip_info
[] = {
129 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
130 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
131 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
132 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
134 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
135 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
137 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
142 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
146 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
153 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880) // PCI-E
163 static void rtl_hw_start_8169(struct net_device
*);
164 static void rtl_hw_start_8168(struct net_device
*);
165 static void rtl_hw_start_8101(struct net_device
*);
167 static struct pci_device_id rtl8169_pci_tbl
[] = {
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
173 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
175 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
176 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
177 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
179 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
183 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
185 static int rx_copybreak
= 200;
192 MAC0
= 0, /* Ethernet hardware address. */
194 MAR0
= 8, /* Multicast filter. */
195 CounterAddrLow
= 0x10,
196 CounterAddrHigh
= 0x14,
197 TxDescStartAddrLow
= 0x20,
198 TxDescStartAddrHigh
= 0x24,
199 TxHDescStartAddrLow
= 0x28,
200 TxHDescStartAddrHigh
= 0x2c,
223 RxDescAddrLow
= 0xe4,
224 RxDescAddrHigh
= 0xe8,
227 FuncEventMask
= 0xf4,
228 FuncPresetState
= 0xf8,
229 FuncForceEvent
= 0xfc,
232 enum rtl8110_registers
{
238 enum rtl8168_8101_registers
{
241 #define CSIAR_FLAG 0x80000000
242 #define CSIAR_WRITE_CMD 0x80000000
243 #define CSIAR_BYTE_ENABLE 0x0f
244 #define CSIAR_BYTE_ENABLE_SHIFT 12
245 #define CSIAR_ADDR_MASK 0x0fff
248 #define EPHYAR_FLAG 0x80000000
249 #define EPHYAR_WRITE_CMD 0x80000000
250 #define EPHYAR_REG_MASK 0x1f
251 #define EPHYAR_REG_SHIFT 16
252 #define EPHYAR_DATA_MASK 0xffff
254 #define FIX_NAK_1 (1 << 4)
255 #define FIX_NAK_2 (1 << 3)
258 enum rtl_register_content
{
259 /* InterruptStatusBits */
263 TxDescUnavail
= 0x0080,
285 /* TXPoll register p.5 */
286 HPQ
= 0x80, /* Poll cmd on the high prio queue */
287 NPQ
= 0x40, /* Poll cmd on the low prio queue */
288 FSWInt
= 0x01, /* Forced software interrupt */
292 Cfg9346_Unlock
= 0xc0,
297 AcceptBroadcast
= 0x08,
298 AcceptMulticast
= 0x04,
300 AcceptAllPhys
= 0x01,
307 TxInterFrameGapShift
= 24,
308 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
310 /* Config1 register p.24 */
313 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
314 Speed_down
= (1 << 4),
318 PMEnable
= (1 << 0), /* Power Management Enable */
320 /* Config2 register p. 25 */
321 PCI_Clock_66MHz
= 0x01,
322 PCI_Clock_33MHz
= 0x00,
324 /* Config3 register p.25 */
325 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
326 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
327 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
329 /* Config5 register p.27 */
330 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
331 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
332 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
333 LanWake
= (1 << 1), /* LanWake enable/disable */
334 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
337 TBIReset
= 0x80000000,
338 TBILoopback
= 0x40000000,
339 TBINwEnable
= 0x20000000,
340 TBINwRestart
= 0x10000000,
341 TBILinkOk
= 0x02000000,
342 TBINwComplete
= 0x01000000,
345 EnableBist
= (1 << 15), // 8168 8101
346 Mac_dbgo_oe
= (1 << 14), // 8168 8101
347 Normal_mode
= (1 << 13), // unused
348 Force_half_dup
= (1 << 12), // 8168 8101
349 Force_rxflow_en
= (1 << 11), // 8168 8101
350 Force_txflow_en
= (1 << 10), // 8168 8101
351 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
352 ASF
= (1 << 8), // 8168 8101
353 PktCntrDisable
= (1 << 7), // 8168 8101
354 Mac_dbgo_sel
= 0x001c, // 8168
359 INTT_0
= 0x0000, // 8168
360 INTT_1
= 0x0001, // 8168
361 INTT_2
= 0x0002, // 8168
362 INTT_3
= 0x0003, // 8168
364 /* rtl8169_PHYstatus */
375 TBILinkOK
= 0x02000000,
377 /* DumpCounterCommand */
381 enum desc_status_bit
{
382 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
383 RingEnd
= (1 << 30), /* End of descriptor ring */
384 FirstFrag
= (1 << 29), /* First segment of a packet */
385 LastFrag
= (1 << 28), /* Final segment of a packet */
388 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
389 MSSShift
= 16, /* MSS value position */
390 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
391 IPCS
= (1 << 18), /* Calculate IP checksum */
392 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
393 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
394 TxVlanTag
= (1 << 17), /* Add VLAN tag */
397 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
398 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
400 #define RxProtoUDP (PID1)
401 #define RxProtoTCP (PID0)
402 #define RxProtoIP (PID1 | PID0)
403 #define RxProtoMask RxProtoIP
405 IPFail
= (1 << 16), /* IP checksum failed */
406 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
407 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
408 RxVlanTag
= (1 << 16), /* VLAN tag available */
411 #define RsvdMask 0x3fffc000
428 u8 __pad
[sizeof(void *) - sizeof(u32
)];
432 RTL_FEATURE_WOL
= (1 << 0),
433 RTL_FEATURE_MSI
= (1 << 1),
434 RTL_FEATURE_GMII
= (1 << 2),
437 struct rtl8169_counters
{
444 __le32 tx_one_collision
;
445 __le32 tx_multi_collision
;
453 struct rtl8169_private
{
454 void __iomem
*mmio_addr
; /* memory map physical address */
455 struct pci_dev
*pci_dev
; /* Index of PCI device */
456 struct net_device
*dev
;
457 struct napi_struct napi
;
458 spinlock_t lock
; /* spin lock flag */
462 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
463 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
466 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
467 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
468 dma_addr_t TxPhyAddr
;
469 dma_addr_t RxPhyAddr
;
470 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
471 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
474 struct timer_list timer
;
479 int phy_1000_ctrl_reg
;
480 #ifdef CONFIG_R8169_VLAN
481 struct vlan_group
*vlgrp
;
483 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
484 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
485 void (*phy_reset_enable
)(void __iomem
*);
486 void (*hw_start
)(struct net_device
*);
487 unsigned int (*phy_reset_pending
)(void __iomem
*);
488 unsigned int (*link_ok
)(void __iomem
*);
489 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
491 struct delayed_work task
;
494 struct mii_if_info mii
;
495 struct rtl8169_counters counters
;
498 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
499 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
500 module_param(rx_copybreak
, int, 0);
501 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
502 module_param(use_dac
, int, 0);
503 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
504 module_param_named(debug
, debug
.msg_enable
, int, 0);
505 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
506 MODULE_LICENSE("GPL");
507 MODULE_VERSION(RTL8169_VERSION
);
509 static int rtl8169_open(struct net_device
*dev
);
510 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
511 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
512 static int rtl8169_init_ring(struct net_device
*dev
);
513 static void rtl_hw_start(struct net_device
*dev
);
514 static int rtl8169_close(struct net_device
*dev
);
515 static void rtl_set_rx_mode(struct net_device
*dev
);
516 static void rtl8169_tx_timeout(struct net_device
*dev
);
517 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
518 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
519 void __iomem
*, u32 budget
);
520 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
521 static void rtl8169_down(struct net_device
*dev
);
522 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
523 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
525 static const unsigned int rtl8169_rx_config
=
526 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
528 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
532 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
534 for (i
= 20; i
> 0; i
--) {
536 * Check if the RTL8169 has completed writing to the specified
539 if (!(RTL_R32(PHYAR
) & 0x80000000))
545 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
549 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
551 for (i
= 20; i
> 0; i
--) {
553 * Check if the RTL8169 has completed retrieving data from
554 * the specified MII register.
556 if (RTL_R32(PHYAR
) & 0x80000000) {
557 value
= RTL_R32(PHYAR
) & 0xffff;
565 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
567 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
570 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
573 struct rtl8169_private
*tp
= netdev_priv(dev
);
574 void __iomem
*ioaddr
= tp
->mmio_addr
;
576 mdio_write(ioaddr
, location
, val
);
579 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
581 struct rtl8169_private
*tp
= netdev_priv(dev
);
582 void __iomem
*ioaddr
= tp
->mmio_addr
;
584 return mdio_read(ioaddr
, location
);
587 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
591 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
592 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
594 for (i
= 0; i
< 100; i
++) {
595 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
601 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
606 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
608 for (i
= 0; i
< 100; i
++) {
609 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
610 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
619 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
623 RTL_W32(CSIDR
, value
);
624 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
625 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
627 for (i
= 0; i
< 100; i
++) {
628 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
634 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
639 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
640 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
642 for (i
= 0; i
< 100; i
++) {
643 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
644 value
= RTL_R32(CSIDR
);
653 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
655 RTL_W16(IntrMask
, 0x0000);
657 RTL_W16(IntrStatus
, 0xffff);
660 static void rtl8169_asic_down(void __iomem
*ioaddr
)
662 RTL_W8(ChipCmd
, 0x00);
663 rtl8169_irq_mask_and_ack(ioaddr
);
667 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
669 return RTL_R32(TBICSR
) & TBIReset
;
672 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
674 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
677 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
679 return RTL_R32(TBICSR
) & TBILinkOk
;
682 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
684 return RTL_R8(PHYstatus
) & LinkStatus
;
687 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
689 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
692 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
696 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
697 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
700 static void rtl8169_check_link_status(struct net_device
*dev
,
701 struct rtl8169_private
*tp
,
702 void __iomem
*ioaddr
)
706 spin_lock_irqsave(&tp
->lock
, flags
);
707 if (tp
->link_ok(ioaddr
)) {
708 netif_carrier_on(dev
);
709 if (netif_msg_ifup(tp
))
710 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
712 if (netif_msg_ifdown(tp
))
713 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
714 netif_carrier_off(dev
);
716 spin_unlock_irqrestore(&tp
->lock
, flags
);
719 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
721 struct rtl8169_private
*tp
= netdev_priv(dev
);
722 void __iomem
*ioaddr
= tp
->mmio_addr
;
727 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
728 wol
->supported
= WAKE_ANY
;
730 spin_lock_irq(&tp
->lock
);
732 options
= RTL_R8(Config1
);
733 if (!(options
& PMEnable
))
736 options
= RTL_R8(Config3
);
737 if (options
& LinkUp
)
738 wol
->wolopts
|= WAKE_PHY
;
739 if (options
& MagicPacket
)
740 wol
->wolopts
|= WAKE_MAGIC
;
742 options
= RTL_R8(Config5
);
744 wol
->wolopts
|= WAKE_UCAST
;
746 wol
->wolopts
|= WAKE_BCAST
;
748 wol
->wolopts
|= WAKE_MCAST
;
751 spin_unlock_irq(&tp
->lock
);
754 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
756 struct rtl8169_private
*tp
= netdev_priv(dev
);
757 void __iomem
*ioaddr
= tp
->mmio_addr
;
764 { WAKE_ANY
, Config1
, PMEnable
},
765 { WAKE_PHY
, Config3
, LinkUp
},
766 { WAKE_MAGIC
, Config3
, MagicPacket
},
767 { WAKE_UCAST
, Config5
, UWF
},
768 { WAKE_BCAST
, Config5
, BWF
},
769 { WAKE_MCAST
, Config5
, MWF
},
770 { WAKE_ANY
, Config5
, LanWake
}
773 spin_lock_irq(&tp
->lock
);
775 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
777 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
778 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
779 if (wol
->wolopts
& cfg
[i
].opt
)
780 options
|= cfg
[i
].mask
;
781 RTL_W8(cfg
[i
].reg
, options
);
784 RTL_W8(Cfg9346
, Cfg9346_Lock
);
787 tp
->features
|= RTL_FEATURE_WOL
;
789 tp
->features
&= ~RTL_FEATURE_WOL
;
790 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
792 spin_unlock_irq(&tp
->lock
);
797 static void rtl8169_get_drvinfo(struct net_device
*dev
,
798 struct ethtool_drvinfo
*info
)
800 struct rtl8169_private
*tp
= netdev_priv(dev
);
802 strcpy(info
->driver
, MODULENAME
);
803 strcpy(info
->version
, RTL8169_VERSION
);
804 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
807 static int rtl8169_get_regs_len(struct net_device
*dev
)
809 return R8169_REGS_SIZE
;
812 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
813 u8 autoneg
, u16 speed
, u8 duplex
)
815 struct rtl8169_private
*tp
= netdev_priv(dev
);
816 void __iomem
*ioaddr
= tp
->mmio_addr
;
820 reg
= RTL_R32(TBICSR
);
821 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
822 (duplex
== DUPLEX_FULL
)) {
823 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
824 } else if (autoneg
== AUTONEG_ENABLE
)
825 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
827 if (netif_msg_link(tp
)) {
828 printk(KERN_WARNING
"%s: "
829 "incorrect speed setting refused in TBI mode\n",
838 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
839 u8 autoneg
, u16 speed
, u8 duplex
)
841 struct rtl8169_private
*tp
= netdev_priv(dev
);
842 void __iomem
*ioaddr
= tp
->mmio_addr
;
845 if (autoneg
== AUTONEG_ENABLE
) {
848 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
849 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
850 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
851 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
853 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
854 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
856 /* The 8100e/8101e/8102e do Fast Ethernet only. */
857 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
858 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
859 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
860 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
861 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
862 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
863 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
864 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
865 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
866 } else if (netif_msg_link(tp
)) {
867 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
871 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
873 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
874 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
875 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
878 * Vendor specific (0x1f) and reserved (0x0e) MII
881 mdio_write(ioaddr
, 0x1f, 0x0000);
882 mdio_write(ioaddr
, 0x0e, 0x0000);
885 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
886 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
890 if (speed
== SPEED_10
)
892 else if (speed
== SPEED_100
)
893 bmcr
= BMCR_SPEED100
;
897 if (duplex
== DUPLEX_FULL
)
898 bmcr
|= BMCR_FULLDPLX
;
900 mdio_write(ioaddr
, 0x1f, 0x0000);
903 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
905 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
907 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
908 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
909 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
910 mdio_write(ioaddr
, 0x17, 0x2138);
911 mdio_write(ioaddr
, 0x0e, 0x0260);
913 mdio_write(ioaddr
, 0x17, 0x2108);
914 mdio_write(ioaddr
, 0x0e, 0x0000);
921 static int rtl8169_set_speed(struct net_device
*dev
,
922 u8 autoneg
, u16 speed
, u8 duplex
)
924 struct rtl8169_private
*tp
= netdev_priv(dev
);
927 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
929 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
930 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
935 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
937 struct rtl8169_private
*tp
= netdev_priv(dev
);
941 spin_lock_irqsave(&tp
->lock
, flags
);
942 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
943 spin_unlock_irqrestore(&tp
->lock
, flags
);
948 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
950 struct rtl8169_private
*tp
= netdev_priv(dev
);
952 return tp
->cp_cmd
& RxChkSum
;
955 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
957 struct rtl8169_private
*tp
= netdev_priv(dev
);
958 void __iomem
*ioaddr
= tp
->mmio_addr
;
961 spin_lock_irqsave(&tp
->lock
, flags
);
964 tp
->cp_cmd
|= RxChkSum
;
966 tp
->cp_cmd
&= ~RxChkSum
;
968 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
971 spin_unlock_irqrestore(&tp
->lock
, flags
);
976 #ifdef CONFIG_R8169_VLAN
978 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
981 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
982 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
985 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
986 struct vlan_group
*grp
)
988 struct rtl8169_private
*tp
= netdev_priv(dev
);
989 void __iomem
*ioaddr
= tp
->mmio_addr
;
992 spin_lock_irqsave(&tp
->lock
, flags
);
995 tp
->cp_cmd
|= RxVlan
;
997 tp
->cp_cmd
&= ~RxVlan
;
998 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1000 spin_unlock_irqrestore(&tp
->lock
, flags
);
1003 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1004 struct sk_buff
*skb
)
1006 u32 opts2
= le32_to_cpu(desc
->opts2
);
1007 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1010 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1011 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1019 #else /* !CONFIG_R8169_VLAN */
1021 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1022 struct sk_buff
*skb
)
1027 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1028 struct sk_buff
*skb
)
1035 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1037 struct rtl8169_private
*tp
= netdev_priv(dev
);
1038 void __iomem
*ioaddr
= tp
->mmio_addr
;
1042 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1043 cmd
->port
= PORT_FIBRE
;
1044 cmd
->transceiver
= XCVR_INTERNAL
;
1046 status
= RTL_R32(TBICSR
);
1047 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1048 cmd
->autoneg
= !!(status
& TBINwEnable
);
1050 cmd
->speed
= SPEED_1000
;
1051 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1056 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1058 struct rtl8169_private
*tp
= netdev_priv(dev
);
1060 return mii_ethtool_gset(&tp
->mii
, cmd
);
1063 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1065 struct rtl8169_private
*tp
= netdev_priv(dev
);
1066 unsigned long flags
;
1069 spin_lock_irqsave(&tp
->lock
, flags
);
1071 rc
= tp
->get_settings(dev
, cmd
);
1073 spin_unlock_irqrestore(&tp
->lock
, flags
);
1077 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1080 struct rtl8169_private
*tp
= netdev_priv(dev
);
1081 unsigned long flags
;
1083 if (regs
->len
> R8169_REGS_SIZE
)
1084 regs
->len
= R8169_REGS_SIZE
;
1086 spin_lock_irqsave(&tp
->lock
, flags
);
1087 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1088 spin_unlock_irqrestore(&tp
->lock
, flags
);
1091 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1093 struct rtl8169_private
*tp
= netdev_priv(dev
);
1095 return tp
->msg_enable
;
1098 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1100 struct rtl8169_private
*tp
= netdev_priv(dev
);
1102 tp
->msg_enable
= value
;
1105 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1112 "tx_single_collisions",
1113 "tx_multi_collisions",
1121 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1125 return ARRAY_SIZE(rtl8169_gstrings
);
1131 static void rtl8169_update_counters(struct net_device
*dev
)
1133 struct rtl8169_private
*tp
= netdev_priv(dev
);
1134 void __iomem
*ioaddr
= tp
->mmio_addr
;
1135 struct rtl8169_counters
*counters
;
1141 * Some chips are unable to dump tally counters when the receiver
1144 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1147 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1151 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1152 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1153 RTL_W32(CounterAddrLow
, cmd
);
1154 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1157 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1158 /* copy updated counters */
1159 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1165 RTL_W32(CounterAddrLow
, 0);
1166 RTL_W32(CounterAddrHigh
, 0);
1168 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1171 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1172 struct ethtool_stats
*stats
, u64
*data
)
1174 struct rtl8169_private
*tp
= netdev_priv(dev
);
1178 rtl8169_update_counters(dev
);
1180 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1181 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1182 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1183 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1184 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1185 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1186 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1187 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1188 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1189 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1190 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1191 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1192 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1195 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1199 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1204 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1205 .get_drvinfo
= rtl8169_get_drvinfo
,
1206 .get_regs_len
= rtl8169_get_regs_len
,
1207 .get_link
= ethtool_op_get_link
,
1208 .get_settings
= rtl8169_get_settings
,
1209 .set_settings
= rtl8169_set_settings
,
1210 .get_msglevel
= rtl8169_get_msglevel
,
1211 .set_msglevel
= rtl8169_set_msglevel
,
1212 .get_rx_csum
= rtl8169_get_rx_csum
,
1213 .set_rx_csum
= rtl8169_set_rx_csum
,
1214 .set_tx_csum
= ethtool_op_set_tx_csum
,
1215 .set_sg
= ethtool_op_set_sg
,
1216 .set_tso
= ethtool_op_set_tso
,
1217 .get_regs
= rtl8169_get_regs
,
1218 .get_wol
= rtl8169_get_wol
,
1219 .set_wol
= rtl8169_set_wol
,
1220 .get_strings
= rtl8169_get_strings
,
1221 .get_sset_count
= rtl8169_get_sset_count
,
1222 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1225 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1226 int bitnum
, int bitval
)
1230 val
= mdio_read(ioaddr
, reg
);
1231 val
= (bitval
== 1) ?
1232 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1233 mdio_write(ioaddr
, reg
, val
& 0xffff);
1236 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1237 void __iomem
*ioaddr
)
1240 * The driver currently handles the 8168Bf and the 8168Be identically
1241 * but they can be identified more specifically through the test below
1244 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1246 * Same thing for the 8101Eb and the 8101Ec:
1248 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1256 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25
},
1259 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1260 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1261 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1262 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1263 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1264 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1265 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1266 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1267 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1270 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1271 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1272 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1273 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1276 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1277 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1278 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1279 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1280 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1281 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1282 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1283 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1284 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1285 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1286 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1287 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1288 /* FIXME: where did these entries come from ? -- FR */
1289 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1290 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1293 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1294 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1295 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1296 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1297 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1298 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1301 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1305 reg
= RTL_R32(TxConfig
);
1306 while ((reg
& p
->mask
) != p
->val
)
1308 tp
->mac_version
= p
->mac_version
;
1311 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1313 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1321 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1324 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1329 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1332 u16 regs
[5]; /* Beware of bit-sign propagation */
1333 } phy_magic
[5] = { {
1334 { 0x0000, //w 4 15 12 0
1335 0x00a1, //w 3 15 0 00a1
1336 0x0008, //w 2 15 0 0008
1337 0x1020, //w 1 15 0 1020
1338 0x1000 } },{ //w 0 15 0 1000
1339 { 0x7000, //w 4 15 12 7
1340 0xff41, //w 3 15 0 ff41
1341 0xde60, //w 2 15 0 de60
1342 0x0140, //w 1 15 0 0140
1343 0x0077 } },{ //w 0 15 0 0077
1344 { 0xa000, //w 4 15 12 a
1345 0xdf01, //w 3 15 0 df01
1346 0xdf20, //w 2 15 0 df20
1347 0xff95, //w 1 15 0 ff95
1348 0xfa00 } },{ //w 0 15 0 fa00
1349 { 0xb000, //w 4 15 12 b
1350 0xff41, //w 3 15 0 ff41
1351 0xde20, //w 2 15 0 de20
1352 0x0140, //w 1 15 0 0140
1353 0x00bb } },{ //w 0 15 0 00bb
1354 { 0xf000, //w 4 15 12 f
1355 0xdf01, //w 3 15 0 df01
1356 0xdf20, //w 2 15 0 df20
1357 0xff95, //w 1 15 0 ff95
1358 0xbf00 } //w 0 15 0 bf00
1363 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1364 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1365 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1366 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1368 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1371 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1372 mdio_write(ioaddr
, pos
, val
);
1374 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1375 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1376 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1378 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1381 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1383 struct phy_reg phy_reg_init
[] = {
1389 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1392 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1394 struct phy_reg phy_reg_init
[] = {
1399 mdio_write(ioaddr
, 0x1f, 0x0001);
1400 mdio_patch(ioaddr
, 0x16, 1 << 0);
1402 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1405 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1407 struct phy_reg phy_reg_init
[] = {
1413 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1416 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1418 struct phy_reg phy_reg_init
[] = {
1426 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1429 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1431 struct phy_reg phy_reg_init
[] = {
1437 mdio_write(ioaddr
, 0x1f, 0x0000);
1438 mdio_patch(ioaddr
, 0x14, 1 << 5);
1439 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1441 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1444 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1446 struct phy_reg phy_reg_init
[] = {
1466 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1468 mdio_patch(ioaddr
, 0x14, 1 << 5);
1469 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1470 mdio_write(ioaddr
, 0x1f, 0x0000);
1473 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1475 struct phy_reg phy_reg_init
[] = {
1493 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1495 mdio_patch(ioaddr
, 0x16, 1 << 0);
1496 mdio_patch(ioaddr
, 0x14, 1 << 5);
1497 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1498 mdio_write(ioaddr
, 0x1f, 0x0000);
1501 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1503 struct phy_reg phy_reg_init
[] = {
1515 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1517 mdio_patch(ioaddr
, 0x16, 1 << 0);
1518 mdio_patch(ioaddr
, 0x14, 1 << 5);
1519 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1520 mdio_write(ioaddr
, 0x1f, 0x0000);
1523 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1525 rtl8168c_3_hw_phy_config(ioaddr
);
1528 static void rtl8168d_hw_phy_config(void __iomem
*ioaddr
)
1530 struct phy_reg phy_reg_init_0
[] = {
1556 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
1558 if (mdio_read(ioaddr
, 0x06) == 0xc400) {
1559 struct phy_reg phy_reg_init_1
[] = {
1591 rtl_phy_write(ioaddr
, phy_reg_init_1
,
1592 ARRAY_SIZE(phy_reg_init_1
));
1595 mdio_write(ioaddr
, 0x1f, 0x0000);
1598 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1600 struct phy_reg phy_reg_init
[] = {
1607 mdio_write(ioaddr
, 0x1f, 0x0000);
1608 mdio_patch(ioaddr
, 0x11, 1 << 12);
1609 mdio_patch(ioaddr
, 0x19, 1 << 13);
1611 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1614 static void rtl_hw_phy_config(struct net_device
*dev
)
1616 struct rtl8169_private
*tp
= netdev_priv(dev
);
1617 void __iomem
*ioaddr
= tp
->mmio_addr
;
1619 rtl8169_print_mac_version(tp
);
1621 switch (tp
->mac_version
) {
1622 case RTL_GIGA_MAC_VER_01
:
1624 case RTL_GIGA_MAC_VER_02
:
1625 case RTL_GIGA_MAC_VER_03
:
1626 rtl8169s_hw_phy_config(ioaddr
);
1628 case RTL_GIGA_MAC_VER_04
:
1629 rtl8169sb_hw_phy_config(ioaddr
);
1631 case RTL_GIGA_MAC_VER_07
:
1632 case RTL_GIGA_MAC_VER_08
:
1633 case RTL_GIGA_MAC_VER_09
:
1634 rtl8102e_hw_phy_config(ioaddr
);
1636 case RTL_GIGA_MAC_VER_11
:
1637 rtl8168bb_hw_phy_config(ioaddr
);
1639 case RTL_GIGA_MAC_VER_12
:
1640 rtl8168bef_hw_phy_config(ioaddr
);
1642 case RTL_GIGA_MAC_VER_17
:
1643 rtl8168bef_hw_phy_config(ioaddr
);
1645 case RTL_GIGA_MAC_VER_18
:
1646 rtl8168cp_1_hw_phy_config(ioaddr
);
1648 case RTL_GIGA_MAC_VER_19
:
1649 rtl8168c_1_hw_phy_config(ioaddr
);
1651 case RTL_GIGA_MAC_VER_20
:
1652 rtl8168c_2_hw_phy_config(ioaddr
);
1654 case RTL_GIGA_MAC_VER_21
:
1655 rtl8168c_3_hw_phy_config(ioaddr
);
1657 case RTL_GIGA_MAC_VER_22
:
1658 rtl8168c_4_hw_phy_config(ioaddr
);
1660 case RTL_GIGA_MAC_VER_23
:
1661 case RTL_GIGA_MAC_VER_24
:
1662 rtl8168cp_2_hw_phy_config(ioaddr
);
1664 case RTL_GIGA_MAC_VER_25
:
1665 rtl8168d_hw_phy_config(ioaddr
);
1673 static void rtl8169_phy_timer(unsigned long __opaque
)
1675 struct net_device
*dev
= (struct net_device
*)__opaque
;
1676 struct rtl8169_private
*tp
= netdev_priv(dev
);
1677 struct timer_list
*timer
= &tp
->timer
;
1678 void __iomem
*ioaddr
= tp
->mmio_addr
;
1679 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1681 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1683 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1686 spin_lock_irq(&tp
->lock
);
1688 if (tp
->phy_reset_pending(ioaddr
)) {
1690 * A busy loop could burn quite a few cycles on nowadays CPU.
1691 * Let's delay the execution of the timer for a few ticks.
1697 if (tp
->link_ok(ioaddr
))
1700 if (netif_msg_link(tp
))
1701 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1703 tp
->phy_reset_enable(ioaddr
);
1706 mod_timer(timer
, jiffies
+ timeout
);
1708 spin_unlock_irq(&tp
->lock
);
1711 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1713 struct rtl8169_private
*tp
= netdev_priv(dev
);
1714 struct timer_list
*timer
= &tp
->timer
;
1716 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1719 del_timer_sync(timer
);
1722 static inline void rtl8169_request_timer(struct net_device
*dev
)
1724 struct rtl8169_private
*tp
= netdev_priv(dev
);
1725 struct timer_list
*timer
= &tp
->timer
;
1727 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1730 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1733 #ifdef CONFIG_NET_POLL_CONTROLLER
1735 * Polling 'interrupt' - used by things like netconsole to send skbs
1736 * without having to re-enable interrupts. It's not called while
1737 * the interrupt routine is executing.
1739 static void rtl8169_netpoll(struct net_device
*dev
)
1741 struct rtl8169_private
*tp
= netdev_priv(dev
);
1742 struct pci_dev
*pdev
= tp
->pci_dev
;
1744 disable_irq(pdev
->irq
);
1745 rtl8169_interrupt(pdev
->irq
, dev
);
1746 enable_irq(pdev
->irq
);
1750 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1751 void __iomem
*ioaddr
)
1754 pci_release_regions(pdev
);
1755 pci_disable_device(pdev
);
1759 static void rtl8169_phy_reset(struct net_device
*dev
,
1760 struct rtl8169_private
*tp
)
1762 void __iomem
*ioaddr
= tp
->mmio_addr
;
1765 tp
->phy_reset_enable(ioaddr
);
1766 for (i
= 0; i
< 100; i
++) {
1767 if (!tp
->phy_reset_pending(ioaddr
))
1771 if (netif_msg_link(tp
))
1772 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1775 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1777 void __iomem
*ioaddr
= tp
->mmio_addr
;
1779 rtl_hw_phy_config(dev
);
1781 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1782 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1786 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1788 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1789 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1791 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1792 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1794 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1795 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1798 rtl8169_phy_reset(dev
, tp
);
1801 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1802 * only 8101. Don't panic.
1804 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1806 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1807 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1810 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1812 void __iomem
*ioaddr
= tp
->mmio_addr
;
1816 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1817 high
= addr
[4] | (addr
[5] << 8);
1819 spin_lock_irq(&tp
->lock
);
1821 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1823 RTL_W32(MAC4
, high
);
1824 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1826 spin_unlock_irq(&tp
->lock
);
1829 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1831 struct rtl8169_private
*tp
= netdev_priv(dev
);
1832 struct sockaddr
*addr
= p
;
1834 if (!is_valid_ether_addr(addr
->sa_data
))
1835 return -EADDRNOTAVAIL
;
1837 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1839 rtl_rar_set(tp
, dev
->dev_addr
);
1844 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1846 struct rtl8169_private
*tp
= netdev_priv(dev
);
1847 struct mii_ioctl_data
*data
= if_mii(ifr
);
1849 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
1852 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
1856 data
->phy_id
= 32; /* Internal PHY */
1860 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1864 if (!capable(CAP_NET_ADMIN
))
1866 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1872 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
1877 static const struct rtl_cfg_info
{
1878 void (*hw_start
)(struct net_device
*);
1879 unsigned int region
;
1885 } rtl_cfg_infos
[] = {
1887 .hw_start
= rtl_hw_start_8169
,
1890 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1891 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1892 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1893 .features
= RTL_FEATURE_GMII
,
1894 .default_ver
= RTL_GIGA_MAC_VER_01
,
1897 .hw_start
= rtl_hw_start_8168
,
1900 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1901 TxErr
| TxOK
| RxOK
| RxErr
,
1902 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1903 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
1904 .default_ver
= RTL_GIGA_MAC_VER_11
,
1907 .hw_start
= rtl_hw_start_8101
,
1910 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1911 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1912 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1913 .features
= RTL_FEATURE_MSI
,
1914 .default_ver
= RTL_GIGA_MAC_VER_13
,
1918 /* Cfg9346_Unlock assumed. */
1919 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1920 const struct rtl_cfg_info
*cfg
)
1925 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1926 if (cfg
->features
& RTL_FEATURE_MSI
) {
1927 if (pci_enable_msi(pdev
)) {
1928 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1931 msi
= RTL_FEATURE_MSI
;
1934 RTL_W8(Config2
, cfg2
);
1938 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1940 if (tp
->features
& RTL_FEATURE_MSI
) {
1941 pci_disable_msi(pdev
);
1942 tp
->features
&= ~RTL_FEATURE_MSI
;
1946 static const struct net_device_ops rtl8169_netdev_ops
= {
1947 .ndo_open
= rtl8169_open
,
1948 .ndo_stop
= rtl8169_close
,
1949 .ndo_get_stats
= rtl8169_get_stats
,
1950 .ndo_start_xmit
= rtl8169_start_xmit
,
1951 .ndo_tx_timeout
= rtl8169_tx_timeout
,
1952 .ndo_validate_addr
= eth_validate_addr
,
1953 .ndo_change_mtu
= rtl8169_change_mtu
,
1954 .ndo_set_mac_address
= rtl_set_mac_address
,
1955 .ndo_do_ioctl
= rtl8169_ioctl
,
1956 .ndo_set_multicast_list
= rtl_set_rx_mode
,
1957 #ifdef CONFIG_R8169_VLAN
1958 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
1960 #ifdef CONFIG_NET_POLL_CONTROLLER
1961 .ndo_poll_controller
= rtl8169_netpoll
,
1966 static int __devinit
1967 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1969 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
1970 const unsigned int region
= cfg
->region
;
1971 struct rtl8169_private
*tp
;
1972 struct mii_if_info
*mii
;
1973 struct net_device
*dev
;
1974 void __iomem
*ioaddr
;
1978 if (netif_msg_drv(&debug
)) {
1979 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
1980 MODULENAME
, RTL8169_VERSION
);
1983 dev
= alloc_etherdev(sizeof (*tp
));
1985 if (netif_msg_drv(&debug
))
1986 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
1991 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1992 dev
->netdev_ops
= &rtl8169_netdev_ops
;
1993 tp
= netdev_priv(dev
);
1996 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
2000 mii
->mdio_read
= rtl_mdio_read
;
2001 mii
->mdio_write
= rtl_mdio_write
;
2002 mii
->phy_id_mask
= 0x1f;
2003 mii
->reg_num_mask
= 0x1f;
2004 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
2006 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2007 rc
= pci_enable_device(pdev
);
2009 if (netif_msg_probe(tp
))
2010 dev_err(&pdev
->dev
, "enable failure\n");
2011 goto err_out_free_dev_1
;
2014 rc
= pci_set_mwi(pdev
);
2016 goto err_out_disable_2
;
2018 /* make sure PCI base addr 1 is MMIO */
2019 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
2020 if (netif_msg_probe(tp
)) {
2022 "region #%d not an MMIO resource, aborting\n",
2029 /* check for weird/broken PCI region reporting */
2030 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
2031 if (netif_msg_probe(tp
)) {
2033 "Invalid PCI region size(s), aborting\n");
2039 rc
= pci_request_regions(pdev
, MODULENAME
);
2041 if (netif_msg_probe(tp
))
2042 dev_err(&pdev
->dev
, "could not request regions.\n");
2046 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
2048 if ((sizeof(dma_addr_t
) > 4) &&
2049 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
2050 tp
->cp_cmd
|= PCIDAC
;
2051 dev
->features
|= NETIF_F_HIGHDMA
;
2053 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2055 if (netif_msg_probe(tp
)) {
2057 "DMA configuration failed.\n");
2059 goto err_out_free_res_4
;
2063 /* ioremap MMIO region */
2064 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
2066 if (netif_msg_probe(tp
))
2067 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
2069 goto err_out_free_res_4
;
2072 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2073 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
2074 dev_info(&pdev
->dev
, "no PCI Express capability\n");
2076 RTL_W16(IntrMask
, 0x0000);
2078 /* Soft reset the chip. */
2079 RTL_W8(ChipCmd
, CmdReset
);
2081 /* Check that the chip has finished the reset. */
2082 for (i
= 0; i
< 100; i
++) {
2083 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2085 msleep_interruptible(1);
2088 RTL_W16(IntrStatus
, 0xffff);
2090 pci_set_master(pdev
);
2092 /* Identify chip attached to board */
2093 rtl8169_get_mac_version(tp
, ioaddr
);
2095 /* Use appropriate default if unknown */
2096 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2097 if (netif_msg_probe(tp
)) {
2098 dev_notice(&pdev
->dev
,
2099 "unknown MAC, using family default\n");
2101 tp
->mac_version
= cfg
->default_ver
;
2104 rtl8169_print_mac_version(tp
);
2106 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
2107 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
2110 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
2112 "driver bug, MAC version not found in rtl_chip_info\n");
2117 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2118 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
2119 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
2120 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
2121 tp
->features
|= RTL_FEATURE_WOL
;
2122 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
2123 tp
->features
|= RTL_FEATURE_WOL
;
2124 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
2125 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2127 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
2128 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
2129 tp
->set_speed
= rtl8169_set_speed_tbi
;
2130 tp
->get_settings
= rtl8169_gset_tbi
;
2131 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
2132 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
2133 tp
->link_ok
= rtl8169_tbi_link_ok
;
2134 tp
->do_ioctl
= rtl_tbi_ioctl
;
2136 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2138 tp
->set_speed
= rtl8169_set_speed_xmii
;
2139 tp
->get_settings
= rtl8169_gset_xmii
;
2140 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2141 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2142 tp
->link_ok
= rtl8169_xmii_link_ok
;
2143 tp
->do_ioctl
= rtl_xmii_ioctl
;
2146 spin_lock_init(&tp
->lock
);
2148 tp
->mmio_addr
= ioaddr
;
2150 /* Get MAC address */
2151 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2152 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2153 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2155 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2156 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2157 dev
->irq
= pdev
->irq
;
2158 dev
->base_addr
= (unsigned long) ioaddr
;
2160 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2162 #ifdef CONFIG_R8169_VLAN
2163 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2166 tp
->intr_mask
= 0xffff;
2167 tp
->align
= cfg
->align
;
2168 tp
->hw_start
= cfg
->hw_start
;
2169 tp
->intr_event
= cfg
->intr_event
;
2170 tp
->napi_event
= cfg
->napi_event
;
2172 init_timer(&tp
->timer
);
2173 tp
->timer
.data
= (unsigned long) dev
;
2174 tp
->timer
.function
= rtl8169_phy_timer
;
2176 rc
= register_netdev(dev
);
2180 pci_set_drvdata(pdev
, dev
);
2182 if (netif_msg_probe(tp
)) {
2183 u32 xid
= RTL_R32(TxConfig
) & 0x9cf0f8ff;
2185 printk(KERN_INFO
"%s: %s at 0x%lx, "
2186 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2187 "XID %08x IRQ %d\n",
2189 rtl_chip_info
[tp
->chipset
].name
,
2191 dev
->dev_addr
[0], dev
->dev_addr
[1],
2192 dev
->dev_addr
[2], dev
->dev_addr
[3],
2193 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2196 rtl8169_init_phy(dev
, tp
);
2197 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2203 rtl_disable_msi(pdev
, tp
);
2206 pci_release_regions(pdev
);
2208 pci_clear_mwi(pdev
);
2210 pci_disable_device(pdev
);
2216 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2218 struct net_device
*dev
= pci_get_drvdata(pdev
);
2219 struct rtl8169_private
*tp
= netdev_priv(dev
);
2221 flush_scheduled_work();
2223 unregister_netdev(dev
);
2224 rtl_disable_msi(pdev
, tp
);
2225 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2226 pci_set_drvdata(pdev
, NULL
);
2229 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2230 struct net_device
*dev
)
2232 unsigned int mtu
= dev
->mtu
;
2234 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2237 static int rtl8169_open(struct net_device
*dev
)
2239 struct rtl8169_private
*tp
= netdev_priv(dev
);
2240 struct pci_dev
*pdev
= tp
->pci_dev
;
2241 int retval
= -ENOMEM
;
2244 rtl8169_set_rxbufsize(tp
, dev
);
2247 * Rx and Tx desscriptors needs 256 bytes alignment.
2248 * pci_alloc_consistent provides more.
2250 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2252 if (!tp
->TxDescArray
)
2255 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2257 if (!tp
->RxDescArray
)
2260 retval
= rtl8169_init_ring(dev
);
2264 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2268 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2269 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2272 goto err_release_ring_2
;
2274 napi_enable(&tp
->napi
);
2278 rtl8169_request_timer(dev
);
2280 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2285 rtl8169_rx_clear(tp
);
2287 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2290 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2295 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2297 /* Disable interrupts */
2298 rtl8169_irq_mask_and_ack(ioaddr
);
2300 /* Reset the chipset */
2301 RTL_W8(ChipCmd
, CmdReset
);
2307 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2309 void __iomem
*ioaddr
= tp
->mmio_addr
;
2310 u32 cfg
= rtl8169_rx_config
;
2312 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2313 RTL_W32(RxConfig
, cfg
);
2315 /* Set DMA burst size and Interframe Gap Time */
2316 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2317 (InterFrameGap
<< TxInterFrameGapShift
));
2320 static void rtl_hw_start(struct net_device
*dev
)
2322 struct rtl8169_private
*tp
= netdev_priv(dev
);
2323 void __iomem
*ioaddr
= tp
->mmio_addr
;
2326 /* Soft reset the chip. */
2327 RTL_W8(ChipCmd
, CmdReset
);
2329 /* Check that the chip has finished the reset. */
2330 for (i
= 0; i
< 100; i
++) {
2331 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2333 msleep_interruptible(1);
2338 netif_start_queue(dev
);
2342 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2343 void __iomem
*ioaddr
)
2346 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2347 * register to be written before TxDescAddrLow to work.
2348 * Switching from MMIO to I/O access fixes the issue as well.
2350 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2351 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
2352 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2353 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
2356 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2360 cmd
= RTL_R16(CPlusCmd
);
2361 RTL_W16(CPlusCmd
, cmd
);
2365 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
2367 /* Low hurts. Let's disable the filtering. */
2368 RTL_W16(RxMaxSize
, rx_buf_sz
);
2371 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2378 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2379 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2380 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2381 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2386 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2387 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2388 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2389 RTL_W32(0x7c, p
->val
);
2395 static void rtl_hw_start_8169(struct net_device
*dev
)
2397 struct rtl8169_private
*tp
= netdev_priv(dev
);
2398 void __iomem
*ioaddr
= tp
->mmio_addr
;
2399 struct pci_dev
*pdev
= tp
->pci_dev
;
2401 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2402 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2403 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2406 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2407 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2408 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2409 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2410 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2411 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2413 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2415 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2417 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2418 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2419 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2420 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2421 rtl_set_rx_tx_config_registers(tp
);
2423 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2425 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2426 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2427 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2428 "Bit-3 and bit-14 MUST be 1\n");
2429 tp
->cp_cmd
|= (1 << 14);
2432 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2434 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2437 * Undocumented corner. Supposedly:
2438 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2440 RTL_W16(IntrMitigate
, 0x0000);
2442 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2444 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2445 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2446 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2447 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2448 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2449 rtl_set_rx_tx_config_registers(tp
);
2452 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2454 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2457 RTL_W32(RxMissed
, 0);
2459 rtl_set_rx_mode(dev
);
2461 /* no early-rx interrupts */
2462 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2464 /* Enable all known interrupts by setting the interrupt mask. */
2465 RTL_W16(IntrMask
, tp
->intr_event
);
2468 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2470 struct net_device
*dev
= pci_get_drvdata(pdev
);
2471 struct rtl8169_private
*tp
= netdev_priv(dev
);
2472 int cap
= tp
->pcie_cap
;
2477 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2478 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2479 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2483 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2487 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2488 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2492 unsigned int offset
;
2497 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2502 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2503 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2508 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
2510 struct net_device
*dev
= pci_get_drvdata(pdev
);
2511 struct rtl8169_private
*tp
= netdev_priv(dev
);
2512 int cap
= tp
->pcie_cap
;
2517 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
2518 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2519 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
2523 #define R8168_CPCMD_QUIRK_MASK (\
2534 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2536 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2538 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2540 rtl_tx_performance_tweak(pdev
,
2541 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2544 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2546 rtl_hw_start_8168bb(ioaddr
, pdev
);
2548 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2550 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
2553 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2555 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
2557 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2559 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2561 rtl_disable_clock_request(pdev
);
2563 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2566 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2568 static struct ephy_info e_info_8168cp
[] = {
2569 { 0x01, 0, 0x0001 },
2570 { 0x02, 0x0800, 0x1000 },
2571 { 0x03, 0, 0x0042 },
2572 { 0x06, 0x0080, 0x0000 },
2576 rtl_csi_access_enable(ioaddr
);
2578 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
2580 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2583 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2585 rtl_csi_access_enable(ioaddr
);
2587 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2589 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2591 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2594 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2596 rtl_csi_access_enable(ioaddr
);
2598 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2601 RTL_W8(DBG_REG
, 0x20);
2603 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2605 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2607 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2610 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2612 static struct ephy_info e_info_8168c_1
[] = {
2613 { 0x02, 0x0800, 0x1000 },
2614 { 0x03, 0, 0x0002 },
2615 { 0x06, 0x0080, 0x0000 }
2618 rtl_csi_access_enable(ioaddr
);
2620 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2622 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
2624 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2627 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2629 static struct ephy_info e_info_8168c_2
[] = {
2630 { 0x01, 0, 0x0001 },
2631 { 0x03, 0x0400, 0x0220 }
2634 rtl_csi_access_enable(ioaddr
);
2636 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
2638 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2641 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2643 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2646 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2648 rtl_csi_access_enable(ioaddr
);
2650 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2653 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2655 rtl_csi_access_enable(ioaddr
);
2657 rtl_disable_clock_request(pdev
);
2659 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2661 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2663 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2666 static void rtl_hw_start_8168(struct net_device
*dev
)
2668 struct rtl8169_private
*tp
= netdev_priv(dev
);
2669 void __iomem
*ioaddr
= tp
->mmio_addr
;
2670 struct pci_dev
*pdev
= tp
->pci_dev
;
2672 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2674 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2676 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2678 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2680 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2682 RTL_W16(IntrMitigate
, 0x5151);
2684 /* Work around for RxFIFO overflow. */
2685 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2686 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2687 tp
->intr_event
&= ~RxOverflow
;
2690 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2692 rtl_set_rx_mode(dev
);
2694 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2695 (InterFrameGap
<< TxInterFrameGapShift
));
2699 switch (tp
->mac_version
) {
2700 case RTL_GIGA_MAC_VER_11
:
2701 rtl_hw_start_8168bb(ioaddr
, pdev
);
2704 case RTL_GIGA_MAC_VER_12
:
2705 case RTL_GIGA_MAC_VER_17
:
2706 rtl_hw_start_8168bef(ioaddr
, pdev
);
2709 case RTL_GIGA_MAC_VER_18
:
2710 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
2713 case RTL_GIGA_MAC_VER_19
:
2714 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2717 case RTL_GIGA_MAC_VER_20
:
2718 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2721 case RTL_GIGA_MAC_VER_21
:
2722 rtl_hw_start_8168c_3(ioaddr
, pdev
);
2725 case RTL_GIGA_MAC_VER_22
:
2726 rtl_hw_start_8168c_4(ioaddr
, pdev
);
2729 case RTL_GIGA_MAC_VER_23
:
2730 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
2733 case RTL_GIGA_MAC_VER_24
:
2734 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
2737 case RTL_GIGA_MAC_VER_25
:
2738 rtl_hw_start_8168d(ioaddr
, pdev
);
2742 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2743 dev
->name
, tp
->mac_version
);
2747 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2749 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2751 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2753 RTL_W16(IntrMask
, tp
->intr_event
);
2756 #define R810X_CPCMD_QUIRK_MASK (\
2768 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2770 static struct ephy_info e_info_8102e_1
[] = {
2771 { 0x01, 0, 0x6e65 },
2772 { 0x02, 0, 0x091f },
2773 { 0x03, 0, 0xc2f9 },
2774 { 0x06, 0, 0xafb5 },
2775 { 0x07, 0, 0x0e00 },
2776 { 0x19, 0, 0xec80 },
2777 { 0x01, 0, 0x2e65 },
2782 rtl_csi_access_enable(ioaddr
);
2784 RTL_W8(DBG_REG
, FIX_NAK_1
);
2786 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2789 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2790 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2792 cfg1
= RTL_R8(Config1
);
2793 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2794 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2796 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2798 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2801 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2803 rtl_csi_access_enable(ioaddr
);
2805 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2807 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2808 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2810 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2813 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2815 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2817 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2820 static void rtl_hw_start_8101(struct net_device
*dev
)
2822 struct rtl8169_private
*tp
= netdev_priv(dev
);
2823 void __iomem
*ioaddr
= tp
->mmio_addr
;
2824 struct pci_dev
*pdev
= tp
->pci_dev
;
2826 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2827 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2828 int cap
= tp
->pcie_cap
;
2831 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2832 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2836 switch (tp
->mac_version
) {
2837 case RTL_GIGA_MAC_VER_07
:
2838 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2841 case RTL_GIGA_MAC_VER_08
:
2842 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2845 case RTL_GIGA_MAC_VER_09
:
2846 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2850 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2852 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2854 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
2856 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2858 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2860 RTL_W16(IntrMitigate
, 0x0000);
2862 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2864 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2865 rtl_set_rx_tx_config_registers(tp
);
2867 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2871 rtl_set_rx_mode(dev
);
2873 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2875 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2877 RTL_W16(IntrMask
, tp
->intr_event
);
2880 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2882 struct rtl8169_private
*tp
= netdev_priv(dev
);
2885 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2890 if (!netif_running(dev
))
2895 rtl8169_set_rxbufsize(tp
, dev
);
2897 ret
= rtl8169_init_ring(dev
);
2901 napi_enable(&tp
->napi
);
2905 rtl8169_request_timer(dev
);
2911 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2913 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2914 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2917 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2918 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2920 struct pci_dev
*pdev
= tp
->pci_dev
;
2922 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2923 PCI_DMA_FROMDEVICE
);
2924 dev_kfree_skb(*sk_buff
);
2926 rtl8169_make_unusable_by_asic(desc
);
2929 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2931 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2933 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2936 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2939 desc
->addr
= cpu_to_le64(mapping
);
2941 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2944 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2945 struct net_device
*dev
,
2946 struct RxDesc
*desc
, int rx_buf_sz
,
2949 struct sk_buff
*skb
;
2953 pad
= align
? align
: NET_IP_ALIGN
;
2955 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
2959 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
2961 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
2962 PCI_DMA_FROMDEVICE
);
2964 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
2969 rtl8169_make_unusable_by_asic(desc
);
2973 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
2977 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
2978 if (tp
->Rx_skbuff
[i
]) {
2979 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
2980 tp
->RxDescArray
+ i
);
2985 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
2990 for (cur
= start
; end
- cur
!= 0; cur
++) {
2991 struct sk_buff
*skb
;
2992 unsigned int i
= cur
% NUM_RX_DESC
;
2994 WARN_ON((s32
)(end
- cur
) < 0);
2996 if (tp
->Rx_skbuff
[i
])
2999 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
3000 tp
->RxDescArray
+ i
,
3001 tp
->rx_buf_sz
, tp
->align
);
3005 tp
->Rx_skbuff
[i
] = skb
;
3010 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
3012 desc
->opts1
|= cpu_to_le32(RingEnd
);
3015 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3017 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3020 static int rtl8169_init_ring(struct net_device
*dev
)
3022 struct rtl8169_private
*tp
= netdev_priv(dev
);
3024 rtl8169_init_ring_indexes(tp
);
3026 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
3027 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
3029 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
3032 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
3037 rtl8169_rx_clear(tp
);
3041 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
3042 struct TxDesc
*desc
)
3044 unsigned int len
= tx_skb
->len
;
3046 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
3053 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
3057 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
3058 unsigned int entry
= i
% NUM_TX_DESC
;
3059 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3060 unsigned int len
= tx_skb
->len
;
3063 struct sk_buff
*skb
= tx_skb
->skb
;
3065 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
3066 tp
->TxDescArray
+ entry
);
3071 tp
->dev
->stats
.tx_dropped
++;
3074 tp
->cur_tx
= tp
->dirty_tx
= 0;
3077 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
3079 struct rtl8169_private
*tp
= netdev_priv(dev
);
3081 PREPARE_DELAYED_WORK(&tp
->task
, task
);
3082 schedule_delayed_work(&tp
->task
, 4);
3085 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
3087 struct rtl8169_private
*tp
= netdev_priv(dev
);
3088 void __iomem
*ioaddr
= tp
->mmio_addr
;
3090 synchronize_irq(dev
->irq
);
3092 /* Wait for any pending NAPI task to complete */
3093 napi_disable(&tp
->napi
);
3095 rtl8169_irq_mask_and_ack(ioaddr
);
3097 tp
->intr_mask
= 0xffff;
3098 RTL_W16(IntrMask
, tp
->intr_event
);
3099 napi_enable(&tp
->napi
);
3102 static void rtl8169_reinit_task(struct work_struct
*work
)
3104 struct rtl8169_private
*tp
=
3105 container_of(work
, struct rtl8169_private
, task
.work
);
3106 struct net_device
*dev
= tp
->dev
;
3111 if (!netif_running(dev
))
3114 rtl8169_wait_for_quiescence(dev
);
3117 ret
= rtl8169_open(dev
);
3118 if (unlikely(ret
< 0)) {
3119 if (net_ratelimit() && netif_msg_drv(tp
)) {
3120 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
3121 " Rescheduling.\n", dev
->name
, ret
);
3123 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3130 static void rtl8169_reset_task(struct work_struct
*work
)
3132 struct rtl8169_private
*tp
=
3133 container_of(work
, struct rtl8169_private
, task
.work
);
3134 struct net_device
*dev
= tp
->dev
;
3138 if (!netif_running(dev
))
3141 rtl8169_wait_for_quiescence(dev
);
3143 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
3144 rtl8169_tx_clear(tp
);
3146 if (tp
->dirty_rx
== tp
->cur_rx
) {
3147 rtl8169_init_ring_indexes(tp
);
3149 netif_wake_queue(dev
);
3150 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3152 if (net_ratelimit() && netif_msg_intr(tp
)) {
3153 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
3156 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3163 static void rtl8169_tx_timeout(struct net_device
*dev
)
3165 struct rtl8169_private
*tp
= netdev_priv(dev
);
3167 rtl8169_hw_reset(tp
->mmio_addr
);
3169 /* Let's wait a bit while any (async) irq lands on */
3170 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3173 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
3176 struct skb_shared_info
*info
= skb_shinfo(skb
);
3177 unsigned int cur_frag
, entry
;
3178 struct TxDesc
* uninitialized_var(txd
);
3181 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
3182 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
3187 entry
= (entry
+ 1) % NUM_TX_DESC
;
3189 txd
= tp
->TxDescArray
+ entry
;
3191 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
3192 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
3194 /* anti gcc 2.95.3 bugware (sic) */
3195 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3197 txd
->opts1
= cpu_to_le32(status
);
3198 txd
->addr
= cpu_to_le64(mapping
);
3200 tp
->tx_skb
[entry
].len
= len
;
3204 tp
->tx_skb
[entry
].skb
= skb
;
3205 txd
->opts1
|= cpu_to_le32(LastFrag
);
3211 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
3213 if (dev
->features
& NETIF_F_TSO
) {
3214 u32 mss
= skb_shinfo(skb
)->gso_size
;
3217 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
3219 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3220 const struct iphdr
*ip
= ip_hdr(skb
);
3222 if (ip
->protocol
== IPPROTO_TCP
)
3223 return IPCS
| TCPCS
;
3224 else if (ip
->protocol
== IPPROTO_UDP
)
3225 return IPCS
| UDPCS
;
3226 WARN_ON(1); /* we need a WARN() */
3231 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3233 struct rtl8169_private
*tp
= netdev_priv(dev
);
3234 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
3235 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
3236 void __iomem
*ioaddr
= tp
->mmio_addr
;
3240 int ret
= NETDEV_TX_OK
;
3242 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
3243 if (netif_msg_drv(tp
)) {
3245 "%s: BUG! Tx Ring full when queue awake!\n",
3251 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
3254 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
3256 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
3258 len
= skb_headlen(skb
);
3262 opts1
|= FirstFrag
| LastFrag
;
3263 tp
->tx_skb
[entry
].skb
= skb
;
3266 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3268 tp
->tx_skb
[entry
].len
= len
;
3269 txd
->addr
= cpu_to_le64(mapping
);
3270 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3274 /* anti gcc 2.95.3 bugware (sic) */
3275 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3276 txd
->opts1
= cpu_to_le32(status
);
3278 tp
->cur_tx
+= frags
+ 1;
3282 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3284 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3285 netif_stop_queue(dev
);
3287 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3288 netif_wake_queue(dev
);
3295 netif_stop_queue(dev
);
3296 ret
= NETDEV_TX_BUSY
;
3297 dev
->stats
.tx_dropped
++;
3301 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3303 struct rtl8169_private
*tp
= netdev_priv(dev
);
3304 struct pci_dev
*pdev
= tp
->pci_dev
;
3305 void __iomem
*ioaddr
= tp
->mmio_addr
;
3306 u16 pci_status
, pci_cmd
;
3308 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3309 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3311 if (netif_msg_intr(tp
)) {
3313 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3314 dev
->name
, pci_cmd
, pci_status
);
3318 * The recovery sequence below admits a very elaborated explanation:
3319 * - it seems to work;
3320 * - I did not see what else could be done;
3321 * - it makes iop3xx happy.
3323 * Feel free to adjust to your needs.
3325 if (pdev
->broken_parity_status
)
3326 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3328 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3330 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3332 pci_write_config_word(pdev
, PCI_STATUS
,
3333 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3334 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3335 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3337 /* The infamous DAC f*ckup only happens at boot time */
3338 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3339 if (netif_msg_intr(tp
))
3340 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3341 tp
->cp_cmd
&= ~PCIDAC
;
3342 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3343 dev
->features
&= ~NETIF_F_HIGHDMA
;
3346 rtl8169_hw_reset(ioaddr
);
3348 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3351 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3352 struct rtl8169_private
*tp
,
3353 void __iomem
*ioaddr
)
3355 unsigned int dirty_tx
, tx_left
;
3357 dirty_tx
= tp
->dirty_tx
;
3359 tx_left
= tp
->cur_tx
- dirty_tx
;
3361 while (tx_left
> 0) {
3362 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3363 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3364 u32 len
= tx_skb
->len
;
3368 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3369 if (status
& DescOwn
)
3372 dev
->stats
.tx_bytes
+= len
;
3373 dev
->stats
.tx_packets
++;
3375 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3377 if (status
& LastFrag
) {
3378 dev_kfree_skb(tx_skb
->skb
);
3385 if (tp
->dirty_tx
!= dirty_tx
) {
3386 tp
->dirty_tx
= dirty_tx
;
3388 if (netif_queue_stopped(dev
) &&
3389 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3390 netif_wake_queue(dev
);
3393 * 8168 hack: TxPoll requests are lost when the Tx packets are
3394 * too close. Let's kick an extra TxPoll request when a burst
3395 * of start_xmit activity is detected (if it is not detected,
3396 * it is slow enough). -- FR
3399 if (tp
->cur_tx
!= dirty_tx
)
3400 RTL_W8(TxPoll
, NPQ
);
3404 static inline int rtl8169_fragmented_frame(u32 status
)
3406 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3409 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3411 u32 opts1
= le32_to_cpu(desc
->opts1
);
3412 u32 status
= opts1
& RxProtoMask
;
3414 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3415 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3416 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3417 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3419 skb
->ip_summed
= CHECKSUM_NONE
;
3422 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3423 struct rtl8169_private
*tp
, int pkt_size
,
3426 struct sk_buff
*skb
;
3429 if (pkt_size
>= rx_copybreak
)
3432 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3436 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3437 PCI_DMA_FROMDEVICE
);
3438 skb_reserve(skb
, NET_IP_ALIGN
);
3439 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3446 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3447 struct rtl8169_private
*tp
,
3448 void __iomem
*ioaddr
, u32 budget
)
3450 unsigned int cur_rx
, rx_left
;
3451 unsigned int delta
, count
;
3453 cur_rx
= tp
->cur_rx
;
3454 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3455 rx_left
= min(rx_left
, budget
);
3457 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3458 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3459 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3463 status
= le32_to_cpu(desc
->opts1
);
3465 if (status
& DescOwn
)
3467 if (unlikely(status
& RxRES
)) {
3468 if (netif_msg_rx_err(tp
)) {
3470 "%s: Rx ERROR. status = %08x\n",
3473 dev
->stats
.rx_errors
++;
3474 if (status
& (RxRWT
| RxRUNT
))
3475 dev
->stats
.rx_length_errors
++;
3477 dev
->stats
.rx_crc_errors
++;
3478 if (status
& RxFOVF
) {
3479 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3480 dev
->stats
.rx_fifo_errors
++;
3482 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3484 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3485 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3486 int pkt_size
= (status
& 0x00001FFF) - 4;
3487 struct pci_dev
*pdev
= tp
->pci_dev
;
3490 * The driver does not support incoming fragmented
3491 * frames. They are seen as a symptom of over-mtu
3494 if (unlikely(rtl8169_fragmented_frame(status
))) {
3495 dev
->stats
.rx_dropped
++;
3496 dev
->stats
.rx_length_errors
++;
3497 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3501 rtl8169_rx_csum(skb
, desc
);
3503 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3504 pci_dma_sync_single_for_device(pdev
, addr
,
3505 pkt_size
, PCI_DMA_FROMDEVICE
);
3506 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3508 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3509 PCI_DMA_FROMDEVICE
);
3510 tp
->Rx_skbuff
[entry
] = NULL
;
3513 skb_put(skb
, pkt_size
);
3514 skb
->protocol
= eth_type_trans(skb
, dev
);
3516 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3517 netif_receive_skb(skb
);
3519 dev
->stats
.rx_bytes
+= pkt_size
;
3520 dev
->stats
.rx_packets
++;
3523 /* Work around for AMD plateform. */
3524 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3525 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3531 count
= cur_rx
- tp
->cur_rx
;
3532 tp
->cur_rx
= cur_rx
;
3534 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3535 if (!delta
&& count
&& netif_msg_intr(tp
))
3536 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3537 tp
->dirty_rx
+= delta
;
3540 * FIXME: until there is periodic timer to try and refill the ring,
3541 * a temporary shortage may definitely kill the Rx process.
3542 * - disable the asic to try and avoid an overflow and kick it again
3544 * - how do others driver handle this condition (Uh oh...).
3546 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3547 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3552 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3554 struct net_device
*dev
= dev_instance
;
3555 struct rtl8169_private
*tp
= netdev_priv(dev
);
3556 void __iomem
*ioaddr
= tp
->mmio_addr
;
3560 /* loop handling interrupts until we have no new ones or
3561 * we hit a invalid/hotplug case.
3563 status
= RTL_R16(IntrStatus
);
3564 while (status
&& status
!= 0xffff) {
3567 /* Handle all of the error cases first. These will reset
3568 * the chip, so just exit the loop.
3570 if (unlikely(!netif_running(dev
))) {
3571 rtl8169_asic_down(ioaddr
);
3575 /* Work around for rx fifo overflow */
3576 if (unlikely(status
& RxFIFOOver
) &&
3577 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3578 netif_stop_queue(dev
);
3579 rtl8169_tx_timeout(dev
);
3583 if (unlikely(status
& SYSErr
)) {
3584 rtl8169_pcierr_interrupt(dev
);
3588 if (status
& LinkChg
)
3589 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3591 /* We need to see the lastest version of tp->intr_mask to
3592 * avoid ignoring an MSI interrupt and having to wait for
3593 * another event which may never come.
3596 if (status
& tp
->intr_mask
& tp
->napi_event
) {
3597 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3598 tp
->intr_mask
= ~tp
->napi_event
;
3600 if (likely(napi_schedule_prep(&tp
->napi
)))
3601 __napi_schedule(&tp
->napi
);
3602 else if (netif_msg_intr(tp
)) {
3603 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3608 /* We only get a new MSI interrupt when all active irq
3609 * sources on the chip have been acknowledged. So, ack
3610 * everything we've seen and check if new sources have become
3611 * active to avoid blocking all interrupts from the chip.
3614 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3615 status
= RTL_R16(IntrStatus
);
3618 return IRQ_RETVAL(handled
);
3621 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3623 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3624 struct net_device
*dev
= tp
->dev
;
3625 void __iomem
*ioaddr
= tp
->mmio_addr
;
3628 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3629 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3631 if (work_done
< budget
) {
3632 napi_complete(napi
);
3634 /* We need for force the visibility of tp->intr_mask
3635 * for other CPUs, as we can loose an MSI interrupt
3636 * and potentially wait for a retransmit timeout if we don't.
3637 * The posted write to IntrMask is safe, as it will
3638 * eventually make it to the chip and we won't loose anything
3641 tp
->intr_mask
= 0xffff;
3643 RTL_W16(IntrMask
, tp
->intr_event
);
3649 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3651 struct rtl8169_private
*tp
= netdev_priv(dev
);
3653 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3656 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3657 RTL_W32(RxMissed
, 0);
3660 static void rtl8169_down(struct net_device
*dev
)
3662 struct rtl8169_private
*tp
= netdev_priv(dev
);
3663 void __iomem
*ioaddr
= tp
->mmio_addr
;
3664 unsigned int intrmask
;
3666 rtl8169_delete_timer(dev
);
3668 netif_stop_queue(dev
);
3670 napi_disable(&tp
->napi
);
3673 spin_lock_irq(&tp
->lock
);
3675 rtl8169_asic_down(ioaddr
);
3677 rtl8169_rx_missed(dev
, ioaddr
);
3679 spin_unlock_irq(&tp
->lock
);
3681 synchronize_irq(dev
->irq
);
3683 /* Give a racing hard_start_xmit a few cycles to complete. */
3684 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3687 * And now for the 50k$ question: are IRQ disabled or not ?
3689 * Two paths lead here:
3691 * -> netif_running() is available to sync the current code and the
3692 * IRQ handler. See rtl8169_interrupt for details.
3693 * 2) dev->change_mtu
3694 * -> rtl8169_poll can not be issued again and re-enable the
3695 * interruptions. Let's simply issue the IRQ down sequence again.
3697 * No loop if hotpluged or major error (0xffff).
3699 intrmask
= RTL_R16(IntrMask
);
3700 if (intrmask
&& (intrmask
!= 0xffff))
3703 rtl8169_tx_clear(tp
);
3705 rtl8169_rx_clear(tp
);
3708 static int rtl8169_close(struct net_device
*dev
)
3710 struct rtl8169_private
*tp
= netdev_priv(dev
);
3711 struct pci_dev
*pdev
= tp
->pci_dev
;
3713 /* update counters before going down */
3714 rtl8169_update_counters(dev
);
3718 free_irq(dev
->irq
, dev
);
3720 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3722 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3724 tp
->TxDescArray
= NULL
;
3725 tp
->RxDescArray
= NULL
;
3730 static void rtl_set_rx_mode(struct net_device
*dev
)
3732 struct rtl8169_private
*tp
= netdev_priv(dev
);
3733 void __iomem
*ioaddr
= tp
->mmio_addr
;
3734 unsigned long flags
;
3735 u32 mc_filter
[2]; /* Multicast hash filter */
3739 if (dev
->flags
& IFF_PROMISC
) {
3740 /* Unconditionally log net taps. */
3741 if (netif_msg_link(tp
)) {
3742 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3746 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3748 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3749 } else if ((dev
->mc_count
> multicast_filter_limit
)
3750 || (dev
->flags
& IFF_ALLMULTI
)) {
3751 /* Too many to filter perfectly -- accept all multicasts. */
3752 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3753 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3755 struct dev_mc_list
*mclist
;
3758 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3759 mc_filter
[1] = mc_filter
[0] = 0;
3760 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3761 i
++, mclist
= mclist
->next
) {
3762 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3763 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3764 rx_mode
|= AcceptMulticast
;
3768 spin_lock_irqsave(&tp
->lock
, flags
);
3770 tmp
= rtl8169_rx_config
| rx_mode
|
3771 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3773 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3774 u32 data
= mc_filter
[0];
3776 mc_filter
[0] = swab32(mc_filter
[1]);
3777 mc_filter
[1] = swab32(data
);
3780 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3781 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3783 RTL_W32(RxConfig
, tmp
);
3785 spin_unlock_irqrestore(&tp
->lock
, flags
);
3789 * rtl8169_get_stats - Get rtl8169 read/write statistics
3790 * @dev: The Ethernet Device to get statistics for
3792 * Get TX/RX statistics for rtl8169
3794 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3796 struct rtl8169_private
*tp
= netdev_priv(dev
);
3797 void __iomem
*ioaddr
= tp
->mmio_addr
;
3798 unsigned long flags
;
3800 if (netif_running(dev
)) {
3801 spin_lock_irqsave(&tp
->lock
, flags
);
3802 rtl8169_rx_missed(dev
, ioaddr
);
3803 spin_unlock_irqrestore(&tp
->lock
, flags
);
3809 static void rtl8169_net_suspend(struct net_device
*dev
)
3811 if (!netif_running(dev
))
3814 netif_device_detach(dev
);
3815 netif_stop_queue(dev
);
3820 static int rtl8169_suspend(struct device
*device
)
3822 struct pci_dev
*pdev
= to_pci_dev(device
);
3823 struct net_device
*dev
= pci_get_drvdata(pdev
);
3825 rtl8169_net_suspend(dev
);
3830 static int rtl8169_resume(struct device
*device
)
3832 struct pci_dev
*pdev
= to_pci_dev(device
);
3833 struct net_device
*dev
= pci_get_drvdata(pdev
);
3835 if (!netif_running(dev
))
3838 netif_device_attach(dev
);
3840 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3845 static struct dev_pm_ops rtl8169_pm_ops
= {
3846 .suspend
= rtl8169_suspend
,
3847 .resume
= rtl8169_resume
,
3848 .freeze
= rtl8169_suspend
,
3849 .thaw
= rtl8169_resume
,
3850 .poweroff
= rtl8169_suspend
,
3851 .restore
= rtl8169_resume
,
3854 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
3856 #else /* !CONFIG_PM */
3858 #define RTL8169_PM_OPS NULL
3860 #endif /* !CONFIG_PM */
3862 static void rtl_shutdown(struct pci_dev
*pdev
)
3864 struct net_device
*dev
= pci_get_drvdata(pdev
);
3865 struct rtl8169_private
*tp
= netdev_priv(dev
);
3866 void __iomem
*ioaddr
= tp
->mmio_addr
;
3868 rtl8169_net_suspend(dev
);
3870 spin_lock_irq(&tp
->lock
);
3872 rtl8169_asic_down(ioaddr
);
3874 spin_unlock_irq(&tp
->lock
);
3876 if (system_state
== SYSTEM_POWER_OFF
) {
3877 /* WoL fails with some 8168 when the receiver is disabled. */
3878 if (tp
->features
& RTL_FEATURE_WOL
) {
3879 pci_clear_master(pdev
);
3881 RTL_W8(ChipCmd
, CmdRxEnb
);
3886 pci_wake_from_d3(pdev
, true);
3887 pci_set_power_state(pdev
, PCI_D3hot
);
3891 static struct pci_driver rtl8169_pci_driver
= {
3893 .id_table
= rtl8169_pci_tbl
,
3894 .probe
= rtl8169_init_one
,
3895 .remove
= __devexit_p(rtl8169_remove_one
),
3896 .shutdown
= rtl_shutdown
,
3897 .driver
.pm
= RTL8169_PM_OPS
,
3900 static int __init
rtl8169_init_module(void)
3902 return pci_register_driver(&rtl8169_pci_driver
);
3905 static void __exit
rtl8169_cleanup_module(void)
3907 pci_unregister_driver(&rtl8169_pci_driver
);
3910 module_init(rtl8169_init_module
);
3911 module_exit(rtl8169_cleanup_module
);