2 * drivers/net/phy/micrel.c
4 * Driver for Micrel PHYs
6 * Author: David J. Choi
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
22 * Switch : ksz8873, ksz886x
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/phy.h>
28 #include <linux/micrel_phy.h>
30 #include <linux/clk.h>
32 /* Operation Mode Strap Override */
33 #define MII_KSZPHY_OMSO 0x16
34 #define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35 #define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36 #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37 #define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39 /* general Interrupt control/status reg in vendor specific block. */
40 #define MII_KSZPHY_INTCS 0x1B
41 #define KSZPHY_INTCS_JABBER BIT(15)
42 #define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43 #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44 #define KSZPHY_INTCS_PARELLEL BIT(12)
45 #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46 #define KSZPHY_INTCS_LINK_DOWN BIT(10)
47 #define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48 #define KSZPHY_INTCS_LINK_UP BIT(8)
49 #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
53 #define MII_KSZPHY_CTRL_1 0x1e
55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
56 #define MII_KSZPHY_CTRL_2 0x1f
57 #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58 /* bitmap of PHY register to set interrupt mode */
59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60 #define KSZPHY_RMII_REF_CLK_SEL BIT(7)
62 /* Write/read to/from extended registers */
63 #define MII_KSZPHY_EXTREG 0x0b
64 #define KSZPHY_EXTREG_WRITE 0x8000
66 #define MII_KSZPHY_EXTREG_WRITE 0x0c
67 #define MII_KSZPHY_EXTREG_READ 0x0d
69 /* Extended registers */
70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71 #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72 #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
76 struct kszphy_hw_stat
{
82 static struct kszphy_hw_stat kszphy_hw_stats
[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
89 u16 interrupt_level_mask
;
90 bool has_broadcast_disable
;
91 bool has_nand_tree_disable
;
92 bool has_rmii_ref_clk_sel
;
96 const struct kszphy_type
*type
;
98 bool rmii_ref_clk_sel
;
99 bool rmii_ref_clk_sel_val
;
100 u64 stats
[ARRAY_SIZE(kszphy_hw_stats
)];
103 static const struct kszphy_type ksz8021_type
= {
104 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
105 .has_broadcast_disable
= true,
106 .has_nand_tree_disable
= true,
107 .has_rmii_ref_clk_sel
= true,
110 static const struct kszphy_type ksz8041_type
= {
111 .led_mode_reg
= MII_KSZPHY_CTRL_1
,
114 static const struct kszphy_type ksz8051_type
= {
115 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
116 .has_nand_tree_disable
= true,
119 static const struct kszphy_type ksz8081_type
= {
120 .led_mode_reg
= MII_KSZPHY_CTRL_2
,
121 .has_broadcast_disable
= true,
122 .has_nand_tree_disable
= true,
123 .has_rmii_ref_clk_sel
= true,
126 static const struct kszphy_type ks8737_type
= {
127 .interrupt_level_mask
= BIT(14),
130 static const struct kszphy_type ksz9021_type
= {
131 .interrupt_level_mask
= BIT(14),
134 static int kszphy_extended_write(struct phy_device
*phydev
,
137 phy_write(phydev
, MII_KSZPHY_EXTREG
, KSZPHY_EXTREG_WRITE
| regnum
);
138 return phy_write(phydev
, MII_KSZPHY_EXTREG_WRITE
, val
);
141 static int kszphy_extended_read(struct phy_device
*phydev
,
144 phy_write(phydev
, MII_KSZPHY_EXTREG
, regnum
);
145 return phy_read(phydev
, MII_KSZPHY_EXTREG_READ
);
148 static int kszphy_ack_interrupt(struct phy_device
*phydev
)
150 /* bit[7..0] int status, which is a read and clear register. */
153 rc
= phy_read(phydev
, MII_KSZPHY_INTCS
);
155 return (rc
< 0) ? rc
: 0;
158 static int kszphy_config_intr(struct phy_device
*phydev
)
160 const struct kszphy_type
*type
= phydev
->drv
->driver_data
;
164 if (type
&& type
->interrupt_level_mask
)
165 mask
= type
->interrupt_level_mask
;
167 mask
= KSZPHY_CTRL_INT_ACTIVE_HIGH
;
169 /* set the interrupt pin active low */
170 temp
= phy_read(phydev
, MII_KSZPHY_CTRL
);
174 phy_write(phydev
, MII_KSZPHY_CTRL
, temp
);
176 /* enable / disable interrupts */
177 if (phydev
->interrupts
== PHY_INTERRUPT_ENABLED
)
178 temp
= KSZPHY_INTCS_ALL
;
182 return phy_write(phydev
, MII_KSZPHY_INTCS
, temp
);
185 static int kszphy_rmii_clk_sel(struct phy_device
*phydev
, bool val
)
189 ctrl
= phy_read(phydev
, MII_KSZPHY_CTRL
);
194 ctrl
|= KSZPHY_RMII_REF_CLK_SEL
;
196 ctrl
&= ~KSZPHY_RMII_REF_CLK_SEL
;
198 return phy_write(phydev
, MII_KSZPHY_CTRL
, ctrl
);
201 static int kszphy_setup_led(struct phy_device
*phydev
, u32 reg
, int val
)
206 case MII_KSZPHY_CTRL_1
:
209 case MII_KSZPHY_CTRL_2
:
216 temp
= phy_read(phydev
, reg
);
222 temp
&= ~(3 << shift
);
223 temp
|= val
<< shift
;
224 rc
= phy_write(phydev
, reg
, temp
);
227 phydev_err(phydev
, "failed to set led mode\n");
232 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
235 static int kszphy_broadcast_disable(struct phy_device
*phydev
)
239 ret
= phy_read(phydev
, MII_KSZPHY_OMSO
);
243 ret
= phy_write(phydev
, MII_KSZPHY_OMSO
, ret
| KSZPHY_OMSO_B_CAST_OFF
);
246 phydev_err(phydev
, "failed to disable broadcast address\n");
251 static int kszphy_nand_tree_disable(struct phy_device
*phydev
)
255 ret
= phy_read(phydev
, MII_KSZPHY_OMSO
);
259 if (!(ret
& KSZPHY_OMSO_NAND_TREE_ON
))
262 ret
= phy_write(phydev
, MII_KSZPHY_OMSO
,
263 ret
& ~KSZPHY_OMSO_NAND_TREE_ON
);
266 phydev_err(phydev
, "failed to disable NAND tree mode\n");
271 static int kszphy_config_init(struct phy_device
*phydev
)
273 struct kszphy_priv
*priv
= phydev
->priv
;
274 const struct kszphy_type
*type
;
282 if (type
->has_broadcast_disable
)
283 kszphy_broadcast_disable(phydev
);
285 if (type
->has_nand_tree_disable
)
286 kszphy_nand_tree_disable(phydev
);
288 if (priv
->rmii_ref_clk_sel
) {
289 ret
= kszphy_rmii_clk_sel(phydev
, priv
->rmii_ref_clk_sel_val
);
292 "failed to set rmii reference clock\n");
297 if (priv
->led_mode
>= 0)
298 kszphy_setup_led(phydev
, type
->led_mode_reg
, priv
->led_mode
);
300 if (phy_interrupt_is_valid(phydev
)) {
301 int ctl
= phy_read(phydev
, MII_BMCR
);
306 ret
= phy_write(phydev
, MII_BMCR
, ctl
& ~BMCR_ANENABLE
);
314 static int ksz8041_config_init(struct phy_device
*phydev
)
316 struct device_node
*of_node
= phydev
->mdio
.dev
.of_node
;
318 /* Limit supported and advertised modes in fiber mode */
319 if (of_property_read_bool(of_node
, "micrel,fiber-mode")) {
320 phydev
->dev_flags
|= MICREL_PHY_FXEN
;
321 phydev
->supported
&= SUPPORTED_100baseT_Full
|
322 SUPPORTED_100baseT_Half
;
323 phydev
->supported
|= SUPPORTED_FIBRE
;
324 phydev
->advertising
&= ADVERTISED_100baseT_Full
|
325 ADVERTISED_100baseT_Half
;
326 phydev
->advertising
|= ADVERTISED_FIBRE
;
327 phydev
->autoneg
= AUTONEG_DISABLE
;
330 return kszphy_config_init(phydev
);
333 static int ksz8041_config_aneg(struct phy_device
*phydev
)
335 /* Skip auto-negotiation in fiber mode */
336 if (phydev
->dev_flags
& MICREL_PHY_FXEN
) {
337 phydev
->speed
= SPEED_100
;
341 return genphy_config_aneg(phydev
);
344 static int ksz9021_load_values_from_of(struct phy_device
*phydev
,
345 const struct device_node
*of_node
,
347 const char *field1
, const char *field2
,
348 const char *field3
, const char *field4
)
357 if (!of_property_read_u32(of_node
, field1
, &val1
))
360 if (!of_property_read_u32(of_node
, field2
, &val2
))
363 if (!of_property_read_u32(of_node
, field3
, &val3
))
366 if (!of_property_read_u32(of_node
, field4
, &val4
))
373 newval
= kszphy_extended_read(phydev
, reg
);
378 newval
= ((newval
& 0xfff0) | ((val1
/ PS_TO_REG
) & 0xf) << 0);
381 newval
= ((newval
& 0xff0f) | ((val2
/ PS_TO_REG
) & 0xf) << 4);
384 newval
= ((newval
& 0xf0ff) | ((val3
/ PS_TO_REG
) & 0xf) << 8);
387 newval
= ((newval
& 0x0fff) | ((val4
/ PS_TO_REG
) & 0xf) << 12);
389 return kszphy_extended_write(phydev
, reg
, newval
);
392 static int ksz9021_config_init(struct phy_device
*phydev
)
394 const struct device
*dev
= &phydev
->mdio
.dev
;
395 const struct device_node
*of_node
= dev
->of_node
;
396 const struct device
*dev_walker
;
398 /* The Micrel driver has a deprecated option to place phy OF
399 * properties in the MAC node. Walk up the tree of devices to
400 * find a device with an OF node.
402 dev_walker
= &phydev
->mdio
.dev
;
404 of_node
= dev_walker
->of_node
;
405 dev_walker
= dev_walker
->parent
;
407 } while (!of_node
&& dev_walker
);
410 ksz9021_load_values_from_of(phydev
, of_node
,
411 MII_KSZPHY_CLK_CONTROL_PAD_SKEW
,
412 "txen-skew-ps", "txc-skew-ps",
413 "rxdv-skew-ps", "rxc-skew-ps");
414 ksz9021_load_values_from_of(phydev
, of_node
,
415 MII_KSZPHY_RX_DATA_PAD_SKEW
,
416 "rxd0-skew-ps", "rxd1-skew-ps",
417 "rxd2-skew-ps", "rxd3-skew-ps");
418 ksz9021_load_values_from_of(phydev
, of_node
,
419 MII_KSZPHY_TX_DATA_PAD_SKEW
,
420 "txd0-skew-ps", "txd1-skew-ps",
421 "txd2-skew-ps", "txd3-skew-ps");
426 #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
427 #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
429 #define KSZ9031_PS_TO_REG 60
431 /* Extended registers */
432 /* MMD Address 0x0 */
433 #define MII_KSZ9031RN_FLP_BURST_TX_LO 3
434 #define MII_KSZ9031RN_FLP_BURST_TX_HI 4
436 /* MMD Address 0x2 */
437 #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
438 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
439 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
440 #define MII_KSZ9031RN_CLK_PAD_SKEW 8
442 /* MMD Address 0x1C */
443 #define MII_KSZ9031RN_EDPD 0x23
444 #define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
446 static int ksz9031_extended_write(struct phy_device
*phydev
,
447 u8 mode
, u32 dev_addr
, u32 regnum
, u16 val
)
449 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, dev_addr
);
450 phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, regnum
);
451 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, (mode
<< 14) | dev_addr
);
452 return phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, val
);
455 static int ksz9031_extended_read(struct phy_device
*phydev
,
456 u8 mode
, u32 dev_addr
, u32 regnum
)
458 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, dev_addr
);
459 phy_write(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
, regnum
);
460 phy_write(phydev
, MII_KSZ9031RN_MMD_CTRL_REG
, (mode
<< 14) | dev_addr
);
461 return phy_read(phydev
, MII_KSZ9031RN_MMD_REGDATA_REG
);
464 static int ksz9031_of_load_skew_values(struct phy_device
*phydev
,
465 const struct device_node
*of_node
,
466 u16 reg
, size_t field_sz
,
467 const char *field
[], u8 numfields
)
469 int val
[4] = {-1, -2, -3, -4};
476 for (i
= 0; i
< numfields
; i
++)
477 if (!of_property_read_u32(of_node
, field
[i
], val
+ i
))
483 if (matches
< numfields
)
484 newval
= ksz9031_extended_read(phydev
, OP_DATA
, 2, reg
);
488 maxval
= (field_sz
== 4) ? 0xf : 0x1f;
489 for (i
= 0; i
< numfields
; i
++)
490 if (val
[i
] != -(i
+ 1)) {
492 mask
^= maxval
<< (field_sz
* i
);
493 newval
= (newval
& mask
) |
494 (((val
[i
] / KSZ9031_PS_TO_REG
) & maxval
)
498 return ksz9031_extended_write(phydev
, OP_DATA
, 2, reg
, newval
);
501 static int ksz9031_center_flp_timing(struct phy_device
*phydev
)
505 /* Center KSZ9031RNX FLP timing at 16ms. */
506 result
= ksz9031_extended_write(phydev
, OP_DATA
, 0,
507 MII_KSZ9031RN_FLP_BURST_TX_HI
, 0x0006);
508 result
= ksz9031_extended_write(phydev
, OP_DATA
, 0,
509 MII_KSZ9031RN_FLP_BURST_TX_LO
, 0x1A80);
514 return genphy_restart_aneg(phydev
);
517 /* Enable energy-detect power-down mode */
518 static int ksz9031_enable_edpd(struct phy_device
*phydev
)
522 reg
= ksz9031_extended_read(phydev
, OP_DATA
, 0x1C, MII_KSZ9031RN_EDPD
);
525 return ksz9031_extended_write(phydev
, OP_DATA
, 0x1C, MII_KSZ9031RN_EDPD
,
526 reg
| MII_KSZ9031RN_EDPD_ENABLE
);
529 static int ksz9031_config_init(struct phy_device
*phydev
)
531 const struct device
*dev
= &phydev
->mdio
.dev
;
532 const struct device_node
*of_node
= dev
->of_node
;
533 static const char *clk_skews
[2] = {"rxc-skew-ps", "txc-skew-ps"};
534 static const char *rx_data_skews
[4] = {
535 "rxd0-skew-ps", "rxd1-skew-ps",
536 "rxd2-skew-ps", "rxd3-skew-ps"
538 static const char *tx_data_skews
[4] = {
539 "txd0-skew-ps", "txd1-skew-ps",
540 "txd2-skew-ps", "txd3-skew-ps"
542 static const char *control_skews
[2] = {"txen-skew-ps", "rxdv-skew-ps"};
543 const struct device
*dev_walker
;
546 result
= ksz9031_enable_edpd(phydev
);
550 /* The Micrel driver has a deprecated option to place phy OF
551 * properties in the MAC node. Walk up the tree of devices to
552 * find a device with an OF node.
554 dev_walker
= &phydev
->mdio
.dev
;
556 of_node
= dev_walker
->of_node
;
557 dev_walker
= dev_walker
->parent
;
558 } while (!of_node
&& dev_walker
);
561 ksz9031_of_load_skew_values(phydev
, of_node
,
562 MII_KSZ9031RN_CLK_PAD_SKEW
, 5,
565 ksz9031_of_load_skew_values(phydev
, of_node
,
566 MII_KSZ9031RN_CONTROL_PAD_SKEW
, 4,
569 ksz9031_of_load_skew_values(phydev
, of_node
,
570 MII_KSZ9031RN_RX_DATA_PAD_SKEW
, 4,
573 ksz9031_of_load_skew_values(phydev
, of_node
,
574 MII_KSZ9031RN_TX_DATA_PAD_SKEW
, 4,
578 return ksz9031_center_flp_timing(phydev
);
581 #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
582 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
583 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
584 static int ksz8873mll_read_status(struct phy_device
*phydev
)
589 regval
= phy_read(phydev
, KSZ8873MLL_GLOBAL_CONTROL_4
);
591 regval
= phy_read(phydev
, KSZ8873MLL_GLOBAL_CONTROL_4
);
593 if (regval
& KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX
)
594 phydev
->duplex
= DUPLEX_HALF
;
596 phydev
->duplex
= DUPLEX_FULL
;
598 if (regval
& KSZ8873MLL_GLOBAL_CONTROL_4_SPEED
)
599 phydev
->speed
= SPEED_10
;
601 phydev
->speed
= SPEED_100
;
604 phydev
->pause
= phydev
->asym_pause
= 0;
609 static int ksz9031_read_status(struct phy_device
*phydev
)
614 err
= genphy_read_status(phydev
);
618 /* Make sure the PHY is not broken. Read idle error count,
619 * and reset the PHY if it is maxed out.
621 regval
= phy_read(phydev
, MII_STAT1000
);
622 if ((regval
& 0xFF) == 0xFF) {
630 static int ksz8873mll_config_aneg(struct phy_device
*phydev
)
635 /* This routine returns -1 as an indication to the caller that the
636 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
637 * MMD extended PHY registers.
640 ksz9021_rd_mmd_phyreg(struct phy_device
*phydev
, int ptrad
, int devnum
,
646 /* This routine does nothing since the Micrel ksz9021 does not support
647 * standard IEEE MMD extended PHY registers.
650 ksz9021_wr_mmd_phyreg(struct phy_device
*phydev
, int ptrad
, int devnum
,
655 static int kszphy_get_sset_count(struct phy_device
*phydev
)
657 return ARRAY_SIZE(kszphy_hw_stats
);
660 static void kszphy_get_strings(struct phy_device
*phydev
, u8
*data
)
664 for (i
= 0; i
< ARRAY_SIZE(kszphy_hw_stats
); i
++) {
665 memcpy(data
+ i
* ETH_GSTRING_LEN
,
666 kszphy_hw_stats
[i
].string
, ETH_GSTRING_LEN
);
671 #define UINT64_MAX (u64)(~((u64)0))
673 static u64
kszphy_get_stat(struct phy_device
*phydev
, int i
)
675 struct kszphy_hw_stat stat
= kszphy_hw_stats
[i
];
676 struct kszphy_priv
*priv
= phydev
->priv
;
680 val
= phy_read(phydev
, stat
.reg
);
684 val
= val
& ((1 << stat
.bits
) - 1);
685 priv
->stats
[i
] += val
;
686 ret
= priv
->stats
[i
];
692 static void kszphy_get_stats(struct phy_device
*phydev
,
693 struct ethtool_stats
*stats
, u64
*data
)
697 for (i
= 0; i
< ARRAY_SIZE(kszphy_hw_stats
); i
++)
698 data
[i
] = kszphy_get_stat(phydev
, i
);
701 static int kszphy_suspend(struct phy_device
*phydev
)
703 /* Disable PHY Interrupts */
704 if (phy_interrupt_is_valid(phydev
)) {
705 phydev
->interrupts
= PHY_INTERRUPT_DISABLED
;
706 if (phydev
->drv
->config_intr
)
707 phydev
->drv
->config_intr(phydev
);
710 return genphy_suspend(phydev
);
713 static int kszphy_resume(struct phy_device
*phydev
)
715 genphy_resume(phydev
);
717 /* Enable PHY Interrupts */
718 if (phy_interrupt_is_valid(phydev
)) {
719 phydev
->interrupts
= PHY_INTERRUPT_ENABLED
;
720 if (phydev
->drv
->config_intr
)
721 phydev
->drv
->config_intr(phydev
);
727 static int kszphy_probe(struct phy_device
*phydev
)
729 const struct kszphy_type
*type
= phydev
->drv
->driver_data
;
730 const struct device_node
*np
= phydev
->mdio
.dev
.of_node
;
731 struct kszphy_priv
*priv
;
735 priv
= devm_kzalloc(&phydev
->mdio
.dev
, sizeof(*priv
), GFP_KERNEL
);
743 if (type
->led_mode_reg
) {
744 ret
= of_property_read_u32(np
, "micrel,led-mode",
749 if (priv
->led_mode
> 3) {
750 phydev_err(phydev
, "invalid led mode: 0x%02x\n",
758 clk
= devm_clk_get(&phydev
->mdio
.dev
, "rmii-ref");
759 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
760 if (!IS_ERR_OR_NULL(clk
)) {
761 unsigned long rate
= clk_get_rate(clk
);
762 bool rmii_ref_clk_sel_25_mhz
;
764 priv
->rmii_ref_clk_sel
= type
->has_rmii_ref_clk_sel
;
765 rmii_ref_clk_sel_25_mhz
= of_property_read_bool(np
,
766 "micrel,rmii-reference-clock-select-25-mhz");
768 if (rate
> 24500000 && rate
< 25500000) {
769 priv
->rmii_ref_clk_sel_val
= rmii_ref_clk_sel_25_mhz
;
770 } else if (rate
> 49500000 && rate
< 50500000) {
771 priv
->rmii_ref_clk_sel_val
= !rmii_ref_clk_sel_25_mhz
;
773 phydev_err(phydev
, "Clock rate out of range: %ld\n",
779 /* Support legacy board-file configuration */
780 if (phydev
->dev_flags
& MICREL_PHY_50MHZ_CLK
) {
781 priv
->rmii_ref_clk_sel
= true;
782 priv
->rmii_ref_clk_sel_val
= true;
788 static struct phy_driver ksphy_driver
[] = {
790 .phy_id
= PHY_ID_KS8737
,
791 .phy_id_mask
= MICREL_PHY_ID_MASK
,
792 .name
= "Micrel KS8737",
793 .features
= PHY_BASIC_FEATURES
,
794 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
795 .driver_data
= &ks8737_type
,
796 .config_init
= kszphy_config_init
,
797 .config_aneg
= genphy_config_aneg
,
798 .read_status
= genphy_read_status
,
799 .ack_interrupt
= kszphy_ack_interrupt
,
800 .config_intr
= kszphy_config_intr
,
801 .get_sset_count
= kszphy_get_sset_count
,
802 .get_strings
= kszphy_get_strings
,
803 .get_stats
= kszphy_get_stats
,
804 .suspend
= genphy_suspend
,
805 .resume
= genphy_resume
,
807 .phy_id
= PHY_ID_KSZ8021
,
808 .phy_id_mask
= 0x00ffffff,
809 .name
= "Micrel KSZ8021 or KSZ8031",
810 .features
= PHY_BASIC_FEATURES
,
811 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
812 .driver_data
= &ksz8021_type
,
813 .probe
= kszphy_probe
,
814 .config_init
= kszphy_config_init
,
815 .config_aneg
= genphy_config_aneg
,
816 .read_status
= genphy_read_status
,
817 .ack_interrupt
= kszphy_ack_interrupt
,
818 .config_intr
= kszphy_config_intr
,
819 .get_sset_count
= kszphy_get_sset_count
,
820 .get_strings
= kszphy_get_strings
,
821 .get_stats
= kszphy_get_stats
,
822 .suspend
= genphy_suspend
,
823 .resume
= genphy_resume
,
825 .phy_id
= PHY_ID_KSZ8031
,
826 .phy_id_mask
= 0x00ffffff,
827 .name
= "Micrel KSZ8031",
828 .features
= PHY_BASIC_FEATURES
,
829 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
830 .driver_data
= &ksz8021_type
,
831 .probe
= kszphy_probe
,
832 .config_init
= kszphy_config_init
,
833 .config_aneg
= genphy_config_aneg
,
834 .read_status
= genphy_read_status
,
835 .ack_interrupt
= kszphy_ack_interrupt
,
836 .config_intr
= kszphy_config_intr
,
837 .get_sset_count
= kszphy_get_sset_count
,
838 .get_strings
= kszphy_get_strings
,
839 .get_stats
= kszphy_get_stats
,
840 .suspend
= genphy_suspend
,
841 .resume
= genphy_resume
,
843 .phy_id
= PHY_ID_KSZ8041
,
844 .phy_id_mask
= MICREL_PHY_ID_MASK
,
845 .name
= "Micrel KSZ8041",
846 .features
= PHY_BASIC_FEATURES
,
847 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
848 .driver_data
= &ksz8041_type
,
849 .probe
= kszphy_probe
,
850 .config_init
= ksz8041_config_init
,
851 .config_aneg
= ksz8041_config_aneg
,
852 .read_status
= genphy_read_status
,
853 .ack_interrupt
= kszphy_ack_interrupt
,
854 .config_intr
= kszphy_config_intr
,
855 .get_sset_count
= kszphy_get_sset_count
,
856 .get_strings
= kszphy_get_strings
,
857 .get_stats
= kszphy_get_stats
,
858 .suspend
= genphy_suspend
,
859 .resume
= genphy_resume
,
861 .phy_id
= PHY_ID_KSZ8041RNLI
,
862 .phy_id_mask
= MICREL_PHY_ID_MASK
,
863 .name
= "Micrel KSZ8041RNLI",
864 .features
= PHY_BASIC_FEATURES
,
865 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
866 .driver_data
= &ksz8041_type
,
867 .probe
= kszphy_probe
,
868 .config_init
= kszphy_config_init
,
869 .config_aneg
= genphy_config_aneg
,
870 .read_status
= genphy_read_status
,
871 .ack_interrupt
= kszphy_ack_interrupt
,
872 .config_intr
= kszphy_config_intr
,
873 .get_sset_count
= kszphy_get_sset_count
,
874 .get_strings
= kszphy_get_strings
,
875 .get_stats
= kszphy_get_stats
,
876 .suspend
= genphy_suspend
,
877 .resume
= genphy_resume
,
879 .phy_id
= PHY_ID_KSZ8051
,
880 .phy_id_mask
= MICREL_PHY_ID_MASK
,
881 .name
= "Micrel KSZ8051",
882 .features
= PHY_BASIC_FEATURES
,
883 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
884 .driver_data
= &ksz8051_type
,
885 .probe
= kszphy_probe
,
886 .config_init
= kszphy_config_init
,
887 .config_aneg
= genphy_config_aneg
,
888 .read_status
= genphy_read_status
,
889 .ack_interrupt
= kszphy_ack_interrupt
,
890 .config_intr
= kszphy_config_intr
,
891 .get_sset_count
= kszphy_get_sset_count
,
892 .get_strings
= kszphy_get_strings
,
893 .get_stats
= kszphy_get_stats
,
894 .suspend
= genphy_suspend
,
895 .resume
= genphy_resume
,
897 .phy_id
= PHY_ID_KSZ8001
,
898 .name
= "Micrel KSZ8001 or KS8721",
899 .phy_id_mask
= 0x00fffffc,
900 .features
= PHY_BASIC_FEATURES
,
901 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
902 .driver_data
= &ksz8041_type
,
903 .probe
= kszphy_probe
,
904 .config_init
= kszphy_config_init
,
905 .config_aneg
= genphy_config_aneg
,
906 .read_status
= genphy_read_status
,
907 .ack_interrupt
= kszphy_ack_interrupt
,
908 .config_intr
= kszphy_config_intr
,
909 .get_sset_count
= kszphy_get_sset_count
,
910 .get_strings
= kszphy_get_strings
,
911 .get_stats
= kszphy_get_stats
,
912 .suspend
= genphy_suspend
,
913 .resume
= genphy_resume
,
915 .phy_id
= PHY_ID_KSZ8081
,
916 .name
= "Micrel KSZ8081 or KSZ8091",
917 .phy_id_mask
= MICREL_PHY_ID_MASK
,
918 .features
= PHY_BASIC_FEATURES
,
919 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
920 .driver_data
= &ksz8081_type
,
921 .probe
= kszphy_probe
,
922 .config_init
= kszphy_config_init
,
923 .config_aneg
= genphy_config_aneg
,
924 .read_status
= genphy_read_status
,
925 .ack_interrupt
= kszphy_ack_interrupt
,
926 .config_intr
= kszphy_config_intr
,
927 .get_sset_count
= kszphy_get_sset_count
,
928 .get_strings
= kszphy_get_strings
,
929 .get_stats
= kszphy_get_stats
,
930 .suspend
= kszphy_suspend
,
931 .resume
= kszphy_resume
,
933 .phy_id
= PHY_ID_KSZ8061
,
934 .name
= "Micrel KSZ8061",
935 .phy_id_mask
= MICREL_PHY_ID_MASK
,
936 .features
= PHY_BASIC_FEATURES
,
937 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
938 .config_init
= kszphy_config_init
,
939 .config_aneg
= genphy_config_aneg
,
940 .read_status
= genphy_read_status
,
941 .ack_interrupt
= kszphy_ack_interrupt
,
942 .config_intr
= kszphy_config_intr
,
943 .get_sset_count
= kszphy_get_sset_count
,
944 .get_strings
= kszphy_get_strings
,
945 .get_stats
= kszphy_get_stats
,
946 .suspend
= genphy_suspend
,
947 .resume
= genphy_resume
,
949 .phy_id
= PHY_ID_KSZ9021
,
950 .phy_id_mask
= 0x000ffffe,
951 .name
= "Micrel KSZ9021 Gigabit PHY",
952 .features
= PHY_GBIT_FEATURES
,
953 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
954 .driver_data
= &ksz9021_type
,
955 .config_init
= ksz9021_config_init
,
956 .config_aneg
= genphy_config_aneg
,
957 .read_status
= genphy_read_status
,
958 .ack_interrupt
= kszphy_ack_interrupt
,
959 .config_intr
= kszphy_config_intr
,
960 .get_sset_count
= kszphy_get_sset_count
,
961 .get_strings
= kszphy_get_strings
,
962 .get_stats
= kszphy_get_stats
,
963 .suspend
= genphy_suspend
,
964 .resume
= genphy_resume
,
965 .read_mmd_indirect
= ksz9021_rd_mmd_phyreg
,
966 .write_mmd_indirect
= ksz9021_wr_mmd_phyreg
,
968 .phy_id
= PHY_ID_KSZ9031
,
969 .phy_id_mask
= MICREL_PHY_ID_MASK
,
970 .name
= "Micrel KSZ9031 Gigabit PHY",
971 .features
= PHY_GBIT_FEATURES
,
972 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
973 .driver_data
= &ksz9021_type
,
974 .config_init
= ksz9031_config_init
,
975 .config_aneg
= genphy_config_aneg
,
976 .read_status
= ksz9031_read_status
,
977 .ack_interrupt
= kszphy_ack_interrupt
,
978 .config_intr
= kszphy_config_intr
,
979 .get_sset_count
= kszphy_get_sset_count
,
980 .get_strings
= kszphy_get_strings
,
981 .get_stats
= kszphy_get_stats
,
982 .suspend
= genphy_suspend
,
983 .resume
= kszphy_resume
,
985 .phy_id
= PHY_ID_KSZ8873MLL
,
986 .phy_id_mask
= MICREL_PHY_ID_MASK
,
987 .name
= "Micrel KSZ8873MLL Switch",
988 .flags
= PHY_HAS_MAGICANEG
,
989 .config_init
= kszphy_config_init
,
990 .config_aneg
= ksz8873mll_config_aneg
,
991 .read_status
= ksz8873mll_read_status
,
992 .get_sset_count
= kszphy_get_sset_count
,
993 .get_strings
= kszphy_get_strings
,
994 .get_stats
= kszphy_get_stats
,
995 .suspend
= genphy_suspend
,
996 .resume
= genphy_resume
,
998 .phy_id
= PHY_ID_KSZ886X
,
999 .phy_id_mask
= MICREL_PHY_ID_MASK
,
1000 .name
= "Micrel KSZ886X Switch",
1001 .features
= PHY_BASIC_FEATURES
,
1002 .flags
= PHY_HAS_MAGICANEG
| PHY_HAS_INTERRUPT
,
1003 .config_init
= kszphy_config_init
,
1004 .config_aneg
= genphy_config_aneg
,
1005 .read_status
= genphy_read_status
,
1006 .get_sset_count
= kszphy_get_sset_count
,
1007 .get_strings
= kszphy_get_strings
,
1008 .get_stats
= kszphy_get_stats
,
1009 .suspend
= genphy_suspend
,
1010 .resume
= genphy_resume
,
1013 module_phy_driver(ksphy_driver
);
1015 MODULE_DESCRIPTION("Micrel PHY driver");
1016 MODULE_AUTHOR("David J. Choi");
1017 MODULE_LICENSE("GPL");
1019 static struct mdio_device_id __maybe_unused micrel_tbl
[] = {
1020 { PHY_ID_KSZ9021
, 0x000ffffe },
1021 { PHY_ID_KSZ9031
, MICREL_PHY_ID_MASK
},
1022 { PHY_ID_KSZ8001
, 0x00fffffc },
1023 { PHY_ID_KS8737
, MICREL_PHY_ID_MASK
},
1024 { PHY_ID_KSZ8021
, 0x00ffffff },
1025 { PHY_ID_KSZ8031
, 0x00ffffff },
1026 { PHY_ID_KSZ8041
, MICREL_PHY_ID_MASK
},
1027 { PHY_ID_KSZ8051
, MICREL_PHY_ID_MASK
},
1028 { PHY_ID_KSZ8061
, MICREL_PHY_ID_MASK
},
1029 { PHY_ID_KSZ8081
, MICREL_PHY_ID_MASK
},
1030 { PHY_ID_KSZ8873MLL
, MICREL_PHY_ID_MASK
},
1031 { PHY_ID_KSZ886X
, MICREL_PHY_ID_MASK
},
1035 MODULE_DEVICE_TABLE(mdio
, micrel_tbl
);