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drivers/net: return operator cleanup
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / niu.c
1 /* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
21 #include <linux/ip.h>
22 #include <linux/in.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
29
30 #include <linux/io.h>
31 #include <linux/of_device.h>
32
33 #include "niu.h"
34
35 #define DRV_MODULE_NAME "niu"
36 #define DRV_MODULE_VERSION "1.1"
37 #define DRV_MODULE_RELDATE "Apr 22, 2010"
38
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef readq
48 static u64 readq(void __iomem *reg)
49 {
50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
51 }
52
53 static void writeq(u64 val, void __iomem *reg)
54 {
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
57 }
58 #endif
59
60 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62 {}
63 };
64
65 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67 #define NIU_TX_TIMEOUT (5 * HZ)
68
69 #define nr64(reg) readq(np->regs + (reg))
70 #define nw64(reg, val) writeq((val), np->regs + (reg))
71
72 #define nr64_mac(reg) readq(np->mac_regs + (reg))
73 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
74
75 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
77
78 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
80
81 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
83
84 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86 static int niu_debug;
87 static int debug = -1;
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "NIU debug level");
90
91 #define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93 #define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
95
96 static int serdes_init_10g_serdes(struct niu *np);
97
98 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
100 {
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
103
104 if (!(val & bits))
105 break;
106 udelay(delay);
107 }
108 if (limit < 0)
109 return -ENODEV;
110 return 0;
111 }
112
113 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
116 {
117 int err;
118
119 nw64_mac(reg, bits);
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121 if (err)
122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
125 return err;
126 }
127
128 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131 })
132
133 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
135 {
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
138
139 if (!(val & bits))
140 break;
141 udelay(delay);
142 }
143 if (limit < 0)
144 return -ENODEV;
145 return 0;
146 }
147
148 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
151 {
152 int err;
153 u64 val;
154
155 val = nr64_ipp(reg);
156 val |= bits;
157 nw64_ipp(reg, val);
158
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160 if (err)
161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
164 return err;
165 }
166
167 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170 })
171
172 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
174 {
175 while (--limit >= 0) {
176 u64 val = nr64(reg);
177
178 if (!(val & bits))
179 break;
180 udelay(delay);
181 }
182 if (limit < 0)
183 return -ENODEV;
184 return 0;
185 }
186
187 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190 })
191
192 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
195 {
196 int err;
197
198 nw64(reg, bits);
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200 if (err)
201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
204 return err;
205 }
206
207 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210 })
211
212 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213 {
214 u64 val = (u64) lp->timer;
215
216 if (on)
217 val |= LDG_IMGMT_ARM;
218
219 nw64(LDG_IMGMT(lp->ldg_num), val);
220 }
221
222 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223 {
224 unsigned long mask_reg, bits;
225 u64 val;
226
227 if (ldn < 0 || ldn > LDN_MAX)
228 return -EINVAL;
229
230 if (ldn < 64) {
231 mask_reg = LD_IM0(ldn);
232 bits = LD_IM0_MASK;
233 } else {
234 mask_reg = LD_IM1(ldn - 64);
235 bits = LD_IM1_MASK;
236 }
237
238 val = nr64(mask_reg);
239 if (on)
240 val &= ~bits;
241 else
242 val |= bits;
243 nw64(mask_reg, val);
244
245 return 0;
246 }
247
248 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249 {
250 struct niu_parent *parent = np->parent;
251 int i;
252
253 for (i = 0; i <= LDN_MAX; i++) {
254 int err;
255
256 if (parent->ldg_map[i] != lp->ldg_num)
257 continue;
258
259 err = niu_ldn_irq_enable(np, i, on);
260 if (err)
261 return err;
262 }
263 return 0;
264 }
265
266 static int niu_enable_interrupts(struct niu *np, int on)
267 {
268 int i;
269
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
272 int err;
273
274 err = niu_enable_ldn_in_ldg(np, lp, on);
275 if (err)
276 return err;
277 }
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
280
281 return 0;
282 }
283
284 static u32 phy_encode(u32 type, int port)
285 {
286 return type << (port * 2);
287 }
288
289 static u32 phy_decode(u32 val, int port)
290 {
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
292 }
293
294 static int mdio_wait(struct niu *np)
295 {
296 int limit = 1000;
297 u64 val;
298
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
303
304 udelay(10);
305 }
306
307 return -ENODEV;
308 }
309
310 static int mdio_read(struct niu *np, int port, int dev, int reg)
311 {
312 int err;
313
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315 err = mdio_wait(np);
316 if (err < 0)
317 return err;
318
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
321 }
322
323 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324 {
325 int err;
326
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328 err = mdio_wait(np);
329 if (err < 0)
330 return err;
331
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333 err = mdio_wait(np);
334 if (err < 0)
335 return err;
336
337 return 0;
338 }
339
340 static int mii_read(struct niu *np, int port, int reg)
341 {
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
344 }
345
346 static int mii_write(struct niu *np, int port, int reg, int data)
347 {
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 return 0;
356 }
357
358 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359 {
360 int err;
361
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
364 val & 0xffff);
365 if (!err)
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
368 val >> 16);
369 return err;
370 }
371
372 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373 {
374 int err;
375
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
378 val & 0xffff);
379 if (!err)
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
382 val >> 16);
383 return err;
384 }
385
386 /* Mode is always 10G fiber. */
387 static int serdes_init_niu_10g_fiber(struct niu *np)
388 {
389 struct niu_link_config *lp = &np->link_config;
390 u32 tx_cfg, rx_cfg;
391 unsigned long i;
392
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
406 }
407
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411 if (err)
412 return err;
413 }
414
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417 if (err)
418 return err;
419 }
420
421 return 0;
422 }
423
424 static int serdes_init_niu_1g_serdes(struct niu *np)
425 {
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
428 int max_retry = 100;
429 u64 uninitialized_var(sig), mask, val;
430 u32 tx_cfg, rx_cfg;
431 unsigned long i;
432 int err;
433
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
439
440 if (np->port == 0)
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
451 }
452
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
458 if (err) {
459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460 np->port, __func__);
461 return err;
462 }
463
464 pll_sts = PLL_CFG_ENPLL;
465
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
468 if (err) {
469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470 np->port, __func__);
471 return err;
472 }
473
474 udelay(200);
475
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
479 if (err)
480 return err;
481 }
482
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
485 if (err)
486 return err;
487 }
488
489 switch (np->port) {
490 case 0:
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492 mask = val;
493 break;
494
495 case 1:
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497 mask = val;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
507 break;
508
509 mdelay(500);
510 }
511
512 if ((sig & mask) != val) {
513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
515 return -ENODEV;
516 }
517
518 return 0;
519 }
520
521 static int serdes_init_niu_10g_serdes(struct niu *np)
522 {
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525 int max_retry = 100;
526 u64 uninitialized_var(sig), mask, val;
527 unsigned long i;
528 int err;
529
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
543 }
544
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550 if (err) {
551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552 np->port, __func__);
553 return err;
554 }
555
556 pll_sts = PLL_CFG_ENPLL;
557
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560 if (err) {
561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562 np->port, __func__);
563 return err;
564 }
565
566 udelay(200);
567
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
571 if (err)
572 return err;
573 }
574
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
577 if (err)
578 return err;
579 }
580
581 /* check if serdes is ready */
582
583 switch (np->port) {
584 case 0:
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
587 ESR_INT_DET0_P0 |
588 ESR_INT_XSRDY_P0 |
589 ESR_INT_XDP_P0_CH3 |
590 ESR_INT_XDP_P0_CH2 |
591 ESR_INT_XDP_P0_CH1 |
592 ESR_INT_XDP_P0_CH0);
593 break;
594
595 case 1:
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
598 ESR_INT_DET0_P1 |
599 ESR_INT_XSRDY_P1 |
600 ESR_INT_XDP_P1_CH3 |
601 ESR_INT_XDP_P1_CH2 |
602 ESR_INT_XDP_P1_CH1 |
603 ESR_INT_XDP_P1_CH0);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
613 break;
614
615 mdelay(500);
616 }
617
618 if ((sig & mask) != val) {
619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
621
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
624 if (!err) {
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
627 } else {
628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629 np->port);
630 return -ENODEV;
631 }
632 }
633 return 0;
634 }
635
636 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637 {
638 int err;
639
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641 if (err >= 0) {
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
645 if (err >= 0)
646 *val |= ((err & 0xffff) << 16);
647 err = 0;
648 }
649 return err;
650 }
651
652 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653 {
654 int err;
655
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
658 if (err >= 0) {
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
662 if (err >= 0) {
663 *val |= ((err & 0xffff) << 16);
664 err = 0;
665 }
666 }
667 return err;
668 }
669
670 static int esr_read_reset(struct niu *np, u32 *val)
671 {
672 int err;
673
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
676 if (err >= 0) {
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
680 if (err >= 0) {
681 *val |= ((err & 0xffff) << 16);
682 err = 0;
683 }
684 }
685 return err;
686 }
687
688 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689 {
690 int err;
691
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
694 if (!err)
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
697 return err;
698 }
699
700 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701 {
702 int err;
703
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706 if (!err)
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
709 return err;
710 }
711
712 static int esr_reset(struct niu *np)
713 {
714 u32 uninitialized_var(reset);
715 int err;
716
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
719 if (err)
720 return err;
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
723 if (err)
724 return err;
725 udelay(200);
726
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
729 if (err)
730 return err;
731 udelay(200);
732
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
735 if (err)
736 return err;
737 udelay(200);
738
739 err = esr_read_reset(np, &reset);
740 if (err)
741 return err;
742 if (reset != 0) {
743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744 np->port, reset);
745 return -ENODEV;
746 }
747
748 return 0;
749 }
750
751 static int serdes_init_10g(struct niu *np)
752 {
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
756 int err;
757
758 switch (np->port) {
759 case 0:
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762 break;
763 case 1:
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766 break;
767
768 default:
769 return -EINVAL;
770 }
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783 test_cfg_val = 0;
784
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
794 }
795
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
798
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
802
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_read_glue0(np, i, &glue0);
807 if (err)
808 return err;
809
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824 if (err)
825 return err;
826 err = esr_write_glue0(np, i, glue0);
827 if (err)
828 return err;
829 }
830
831 err = esr_reset(np);
832 if (err)
833 return err;
834
835 sig = nr64(ESR_INT_SIGNALS);
836 switch (np->port) {
837 case 0:
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
840 ESR_INT_DET0_P0 |
841 ESR_INT_XSRDY_P0 |
842 ESR_INT_XDP_P0_CH3 |
843 ESR_INT_XDP_P0_CH2 |
844 ESR_INT_XDP_P0_CH1 |
845 ESR_INT_XDP_P0_CH0);
846 break;
847
848 case 1:
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
851 ESR_INT_DET0_P1 |
852 ESR_INT_XSRDY_P1 |
853 ESR_INT_XDP_P1_CH3 |
854 ESR_INT_XDP_P1_CH2 |
855 ESR_INT_XDP_P1_CH1 |
856 ESR_INT_XDP_P1_CH0);
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
863 if ((sig & mask) != val) {
864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866 return 0;
867 }
868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
870 return -ENODEV;
871 }
872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
874 return 0;
875 }
876
877 static int serdes_init_1g(struct niu *np)
878 {
879 u64 val;
880
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
883 switch (np->port) {
884 case 0:
885 val |= ENET_SERDES_PLL_HRATE0;
886 break;
887 case 1:
888 val |= ENET_SERDES_PLL_HRATE1;
889 break;
890 case 2:
891 val |= ENET_SERDES_PLL_HRATE2;
892 break;
893 case 3:
894 val |= ENET_SERDES_PLL_HRATE3;
895 break;
896 default:
897 return -EINVAL;
898 }
899 nw64(ENET_SERDES_1_PLL_CFG, val);
900
901 return 0;
902 }
903
904 static int serdes_init_1g_serdes(struct niu *np)
905 {
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
909 int err;
910 u64 reset_val, val_rd;
911
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
915 switch (np->port) {
916 case 0:
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
921 break;
922 case 1:
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
927 break;
928
929 default:
930 return -EINVAL;
931 }
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944 test_cfg_val = 0;
945
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
955 }
956
957 nw64(ENET_SERDES_RESET, reset_val);
958 mdelay(20);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
961 nw64(pll_cfg, val);
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
965 mdelay(2000);
966
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
970
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972 if (err)
973 return err;
974 err = esr_read_glue0(np, i, &glue0);
975 if (err)
976 return err;
977
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992 if (err)
993 return err;
994 err = esr_write_glue0(np, i, glue0);
995 if (err)
996 return err;
997 }
998
999
1000 sig = nr64(ESR_INT_SIGNALS);
1001 switch (np->port) {
1002 case 0:
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004 mask = val;
1005 break;
1006
1007 case 1:
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009 mask = val;
1010 break;
1011
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 if ((sig & mask) != val) {
1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023 }
1024
1025 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026 {
1027 struct niu_link_config *lp = &np->link_config;
1028 int link_up;
1029 u64 val;
1030 u16 current_speed;
1031 unsigned long flags;
1032 u8 current_duplex;
1033
1034 link_up = 0;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1037
1038 spin_lock_irqsave(&np->lock, flags);
1039
1040 val = nr64_pcs(PCS_MII_STAT);
1041
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1043 link_up = 1;
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1046 }
1047
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1051
1052 *link_up_p = link_up;
1053 return 0;
1054 }
1055
1056 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057 {
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1060 int link_up = 0;
1061 int link_ok = 1;
1062 u64 val, val2;
1063 u16 current_speed;
1064 u8 current_duplex;
1065
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1068
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1072
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1076 link_ok = 0;
1077
1078 if ((val & 0x1000ULL) && link_ok) {
1079 link_up = 1;
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1082 }
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1087 return 0;
1088 }
1089
1090 static int link_status_mii(struct niu *np, int *link_up_p)
1091 {
1092 struct niu_link_config *lp = &np->link_config;
1093 int err;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1099 return err;
1100 bmcr = err;
1101
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1104 return err;
1105 bmsr = err;
1106
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1109 return err;
1110 advert = err;
1111
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1114 return err;
1115 lpa = err;
1116
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1120 return err;
1121 estatus = err;
1122
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1125 return err;
1126 ctrl1000 = err;
1127
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1130 return err;
1131 stat1000 = err;
1132 } else
1133 estatus = ctrl1000 = stat1000 = 0;
1134
1135 supported = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1151
1152 advertising = 0;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1165
1166 if (bmcr & BMCR_ANENABLE) {
1167 int neg, neg1000;
1168
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1171
1172 neg = advert & lpa;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1181 else
1182 active_speed = SPEED_INVALID;
1183
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1188 else
1189 active_duplex = DUPLEX_INVALID;
1190 } else {
1191 lp->active_autoneg = 0;
1192
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1197 else
1198 active_speed = SPEED_10;
1199
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1202 else
1203 active_duplex = DUPLEX_HALF;
1204 }
1205
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211 return 0;
1212 }
1213
1214 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215 {
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1219 u8 current_duplex;
1220 int err, link_up;
1221
1222 link_up = 0;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1225
1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 err = -EINVAL;
1229
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1231 if (err < 0)
1232 goto out;
1233
1234 bmsr = err;
1235 if (bmsr & BMSR_LSTATUS) {
1236 u16 adv, lpa, common, estat;
1237
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239 if (err < 0)
1240 goto out;
1241 adv = err;
1242
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1244 if (err < 0)
1245 goto out;
1246 lpa = err;
1247
1248 common = adv & lpa;
1249
1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
1253 estat = err;
1254 link_up = 1;
1255 current_speed = SPEED_1000;
1256 current_duplex = DUPLEX_FULL;
1257
1258 }
1259 lp->active_speed = current_speed;
1260 lp->active_duplex = current_duplex;
1261 err = 0;
1262
1263 out:
1264 spin_unlock_irqrestore(&np->lock, flags);
1265
1266 *link_up_p = link_up;
1267 return err;
1268 }
1269
1270 static int link_status_1g(struct niu *np, int *link_up_p)
1271 {
1272 struct niu_link_config *lp = &np->link_config;
1273 unsigned long flags;
1274 int err;
1275
1276 spin_lock_irqsave(&np->lock, flags);
1277
1278 err = link_status_mii(np, link_up_p);
1279 lp->supported |= SUPPORTED_TP;
1280 lp->active_advertising |= ADVERTISED_TP;
1281
1282 spin_unlock_irqrestore(&np->lock, flags);
1283 return err;
1284 }
1285
1286 static int bcm8704_reset(struct niu *np)
1287 {
1288 int err, limit;
1289
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292 if (err < 0 || err == 0xffff)
1293 return err;
1294 err |= BMCR_RESET;
1295 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296 MII_BMCR, err);
1297 if (err)
1298 return err;
1299
1300 limit = 1000;
1301 while (--limit >= 0) {
1302 err = mdio_read(np, np->phy_addr,
1303 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304 if (err < 0)
1305 return err;
1306 if (!(err & BMCR_RESET))
1307 break;
1308 }
1309 if (limit < 0) {
1310 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np->port, (err & 0xffff));
1312 return -ENODEV;
1313 }
1314 return 0;
1315 }
1316
1317 /* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1319 */
1320 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321 {
1322 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 if (err < 0)
1324 return err;
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326 if (err < 0)
1327 return err;
1328 return 0;
1329 }
1330
1331 static int bcm8706_init_user_dev3(struct niu *np)
1332 {
1333 int err;
1334
1335
1336 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337 BCM8704_USER_OPT_DIGITAL_CTRL);
1338 if (err < 0)
1339 return err;
1340 err &= ~USER_ODIG_CTRL_GPIOS;
1341 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342 err |= USER_ODIG_CTRL_RESV2;
1343 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345 if (err)
1346 return err;
1347
1348 mdelay(1000);
1349
1350 return 0;
1351 }
1352
1353 static int bcm8704_init_user_dev3(struct niu *np)
1354 {
1355 int err;
1356
1357 err = mdio_write(np, np->phy_addr,
1358 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359 (USER_CONTROL_OPTXRST_LVL |
1360 USER_CONTROL_OPBIASFLT_LVL |
1361 USER_CONTROL_OBTMPFLT_LVL |
1362 USER_CONTROL_OPPRFLT_LVL |
1363 USER_CONTROL_OPTXFLT_LVL |
1364 USER_CONTROL_OPRXLOS_LVL |
1365 USER_CONTROL_OPRXFLT_LVL |
1366 USER_CONTROL_OPTXON_LVL |
1367 (0x3f << USER_CONTROL_RES1_SHIFT)));
1368 if (err)
1369 return err;
1370
1371 err = mdio_write(np, np->phy_addr,
1372 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373 (USER_PMD_TX_CTL_XFP_CLKEN |
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN));
1377 if (err)
1378 return err;
1379
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381 if (err)
1382 return err;
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384 if (err)
1385 return err;
1386
1387 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388 BCM8704_USER_OPT_DIGITAL_CTRL);
1389 if (err < 0)
1390 return err;
1391 err &= ~USER_ODIG_CTRL_GPIOS;
1392 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395 if (err)
1396 return err;
1397
1398 mdelay(1000);
1399
1400 return 0;
1401 }
1402
1403 static int mrvl88x2011_act_led(struct niu *np, int val)
1404 {
1405 int err;
1406
1407 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408 MRVL88X2011_LED_8_TO_11_CTL);
1409 if (err < 0)
1410 return err;
1411
1412 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416 MRVL88X2011_LED_8_TO_11_CTL, err);
1417 }
1418
1419 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420 {
1421 int err;
1422
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424 MRVL88X2011_LED_BLINK_CTL);
1425 if (err >= 0) {
1426 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427 err |= (rate << 4);
1428
1429 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430 MRVL88X2011_LED_BLINK_CTL, err);
1431 }
1432
1433 return err;
1434 }
1435
1436 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437 {
1438 int err;
1439
1440 /* Set LED functions */
1441 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442 if (err)
1443 return err;
1444
1445 /* led activity */
1446 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447 if (err)
1448 return err;
1449
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451 MRVL88X2011_GENERAL_CTL);
1452 if (err < 0)
1453 return err;
1454
1455 err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458 MRVL88X2011_GENERAL_CTL, err);
1459 if (err < 0)
1460 return err;
1461
1462 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1);
1464 if (err < 0)
1465 return err;
1466
1467 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468 err |= MRVL88X2011_LOOPBACK;
1469 else
1470 err &= ~MRVL88X2011_LOOPBACK;
1471
1472 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473 MRVL88X2011_PMA_PMD_CTL_1, err);
1474 if (err < 0)
1475 return err;
1476
1477 /* Enable PMD */
1478 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480 }
1481
1482
1483 static int xcvr_diag_bcm870x(struct niu *np)
1484 {
1485 u16 analog_stat0, tx_alarm_status;
1486 int err = 0;
1487
1488 #if 1
1489 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490 MII_STAT1000);
1491 if (err < 0)
1492 return err;
1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1494
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496 if (err < 0)
1497 return err;
1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1499
1500 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501 MII_NWAYTEST);
1502 if (err < 0)
1503 return err;
1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1505 #endif
1506
1507 /* XXX dig this out it might not be so useful XXX */
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509 BCM8704_USER_ANALOG_STATUS0);
1510 if (err < 0)
1511 return err;
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513 BCM8704_USER_ANALOG_STATUS0);
1514 if (err < 0)
1515 return err;
1516 analog_stat0 = err;
1517
1518 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519 BCM8704_USER_TX_ALARM_STATUS);
1520 if (err < 0)
1521 return err;
1522 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523 BCM8704_USER_TX_ALARM_STATUS);
1524 if (err < 0)
1525 return err;
1526 tx_alarm_status = err;
1527
1528 if (analog_stat0 != 0x03fc) {
1529 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1530 pr_info("Port %u cable not connected or bad cable\n",
1531 np->port);
1532 } else if (analog_stat0 == 0x639c) {
1533 pr_info("Port %u optical module is bad or missing\n",
1534 np->port);
1535 }
1536 }
1537
1538 return 0;
1539 }
1540
1541 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542 {
1543 struct niu_link_config *lp = &np->link_config;
1544 int err;
1545
1546 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547 MII_BMCR);
1548 if (err < 0)
1549 return err;
1550
1551 err &= ~BMCR_LOOPBACK;
1552
1553 if (lp->loopback_mode == LOOPBACK_MAC)
1554 err |= BMCR_LOOPBACK;
1555
1556 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557 MII_BMCR, err);
1558 if (err)
1559 return err;
1560
1561 return 0;
1562 }
1563
1564 static int xcvr_init_10g_bcm8706(struct niu *np)
1565 {
1566 int err = 0;
1567 u64 val;
1568
1569 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571 return err;
1572
1573 val = nr64_mac(XMAC_CONFIG);
1574 val &= ~XMAC_CONFIG_LED_POLARITY;
1575 val |= XMAC_CONFIG_FORCE_LED_ON;
1576 nw64_mac(XMAC_CONFIG, val);
1577
1578 val = nr64(MIF_CONFIG);
1579 val |= MIF_CONFIG_INDIRECT_MODE;
1580 nw64(MIF_CONFIG, val);
1581
1582 err = bcm8704_reset(np);
1583 if (err)
1584 return err;
1585
1586 err = xcvr_10g_set_lb_bcm870x(np);
1587 if (err)
1588 return err;
1589
1590 err = bcm8706_init_user_dev3(np);
1591 if (err)
1592 return err;
1593
1594 err = xcvr_diag_bcm870x(np);
1595 if (err)
1596 return err;
1597
1598 return 0;
1599 }
1600
1601 static int xcvr_init_10g_bcm8704(struct niu *np)
1602 {
1603 int err;
1604
1605 err = bcm8704_reset(np);
1606 if (err)
1607 return err;
1608
1609 err = bcm8704_init_user_dev3(np);
1610 if (err)
1611 return err;
1612
1613 err = xcvr_10g_set_lb_bcm870x(np);
1614 if (err)
1615 return err;
1616
1617 err = xcvr_diag_bcm870x(np);
1618 if (err)
1619 return err;
1620
1621 return 0;
1622 }
1623
1624 static int xcvr_init_10g(struct niu *np)
1625 {
1626 int phy_id, err;
1627 u64 val;
1628
1629 val = nr64_mac(XMAC_CONFIG);
1630 val &= ~XMAC_CONFIG_LED_POLARITY;
1631 val |= XMAC_CONFIG_FORCE_LED_ON;
1632 nw64_mac(XMAC_CONFIG, val);
1633
1634 /* XXX shared resource, lock parent XXX */
1635 val = nr64(MIF_CONFIG);
1636 val |= MIF_CONFIG_INDIRECT_MODE;
1637 nw64(MIF_CONFIG, val);
1638
1639 phy_id = phy_decode(np->parent->port_phy, np->port);
1640 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642 /* handle different phy types */
1643 switch (phy_id & NIU_PHY_ID_MASK) {
1644 case NIU_PHY_ID_MRVL88X2011:
1645 err = xcvr_init_10g_mrvl88x2011(np);
1646 break;
1647
1648 default: /* bcom 8704 */
1649 err = xcvr_init_10g_bcm8704(np);
1650 break;
1651 }
1652
1653 return 0;
1654 }
1655
1656 static int mii_reset(struct niu *np)
1657 {
1658 int limit, err;
1659
1660 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661 if (err)
1662 return err;
1663
1664 limit = 1000;
1665 while (--limit >= 0) {
1666 udelay(500);
1667 err = mii_read(np, np->phy_addr, MII_BMCR);
1668 if (err < 0)
1669 return err;
1670 if (!(err & BMCR_RESET))
1671 break;
1672 }
1673 if (limit < 0) {
1674 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675 np->port, err);
1676 return -ENODEV;
1677 }
1678
1679 return 0;
1680 }
1681
1682 static int xcvr_init_1g_rgmii(struct niu *np)
1683 {
1684 int err;
1685 u64 val;
1686 u16 bmcr, bmsr, estat;
1687
1688 val = nr64(MIF_CONFIG);
1689 val &= ~MIF_CONFIG_INDIRECT_MODE;
1690 nw64(MIF_CONFIG, val);
1691
1692 err = mii_reset(np);
1693 if (err)
1694 return err;
1695
1696 err = mii_read(np, np->phy_addr, MII_BMSR);
1697 if (err < 0)
1698 return err;
1699 bmsr = err;
1700
1701 estat = 0;
1702 if (bmsr & BMSR_ESTATEN) {
1703 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704 if (err < 0)
1705 return err;
1706 estat = err;
1707 }
1708
1709 bmcr = 0;
1710 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711 if (err)
1712 return err;
1713
1714 if (bmsr & BMSR_ESTATEN) {
1715 u16 ctrl1000 = 0;
1716
1717 if (estat & ESTATUS_1000_TFULL)
1718 ctrl1000 |= ADVERTISE_1000FULL;
1719 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720 if (err)
1721 return err;
1722 }
1723
1724 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727 if (err)
1728 return err;
1729
1730 err = mii_read(np, np->phy_addr, MII_BMCR);
1731 if (err < 0)
1732 return err;
1733 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735 err = mii_read(np, np->phy_addr, MII_BMSR);
1736 if (err < 0)
1737 return err;
1738
1739 return 0;
1740 }
1741
1742 static int mii_init_common(struct niu *np)
1743 {
1744 struct niu_link_config *lp = &np->link_config;
1745 u16 bmcr, bmsr, adv, estat;
1746 int err;
1747
1748 err = mii_reset(np);
1749 if (err)
1750 return err;
1751
1752 err = mii_read(np, np->phy_addr, MII_BMSR);
1753 if (err < 0)
1754 return err;
1755 bmsr = err;
1756
1757 estat = 0;
1758 if (bmsr & BMSR_ESTATEN) {
1759 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760 if (err < 0)
1761 return err;
1762 estat = err;
1763 }
1764
1765 bmcr = 0;
1766 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767 if (err)
1768 return err;
1769
1770 if (lp->loopback_mode == LOOPBACK_MAC) {
1771 bmcr |= BMCR_LOOPBACK;
1772 if (lp->active_speed == SPEED_1000)
1773 bmcr |= BMCR_SPEED1000;
1774 if (lp->active_duplex == DUPLEX_FULL)
1775 bmcr |= BMCR_FULLDPLX;
1776 }
1777
1778 if (lp->loopback_mode == LOOPBACK_PHY) {
1779 u16 aux;
1780
1781 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782 BCM5464R_AUX_CTL_WRITE_1);
1783 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784 if (err)
1785 return err;
1786 }
1787
1788 if (lp->autoneg) {
1789 u16 ctrl1000;
1790
1791 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792 if ((bmsr & BMSR_10HALF) &&
1793 (lp->advertising & ADVERTISED_10baseT_Half))
1794 adv |= ADVERTISE_10HALF;
1795 if ((bmsr & BMSR_10FULL) &&
1796 (lp->advertising & ADVERTISED_10baseT_Full))
1797 adv |= ADVERTISE_10FULL;
1798 if ((bmsr & BMSR_100HALF) &&
1799 (lp->advertising & ADVERTISED_100baseT_Half))
1800 adv |= ADVERTISE_100HALF;
1801 if ((bmsr & BMSR_100FULL) &&
1802 (lp->advertising & ADVERTISED_100baseT_Full))
1803 adv |= ADVERTISE_100FULL;
1804 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1805 if (err)
1806 return err;
1807
1808 if (likely(bmsr & BMSR_ESTATEN)) {
1809 ctrl1000 = 0;
1810 if ((estat & ESTATUS_1000_THALF) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Half))
1812 ctrl1000 |= ADVERTISE_1000HALF;
1813 if ((estat & ESTATUS_1000_TFULL) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Full))
1815 ctrl1000 |= ADVERTISE_1000FULL;
1816 err = mii_write(np, np->phy_addr,
1817 MII_CTRL1000, ctrl1000);
1818 if (err)
1819 return err;
1820 }
1821
1822 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823 } else {
1824 /* !lp->autoneg */
1825 int fulldpx;
1826
1827 if (lp->duplex == DUPLEX_FULL) {
1828 bmcr |= BMCR_FULLDPLX;
1829 fulldpx = 1;
1830 } else if (lp->duplex == DUPLEX_HALF)
1831 fulldpx = 0;
1832 else
1833 return -EINVAL;
1834
1835 if (lp->speed == SPEED_1000) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840 return -EINVAL;
1841 bmcr |= BMCR_SPEED1000;
1842 } else if (lp->speed == SPEED_100) {
1843 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845 return -EINVAL;
1846 bmcr |= BMCR_SPEED100;
1847 } else if (lp->speed == SPEED_10) {
1848 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850 return -EINVAL;
1851 } else
1852 return -EINVAL;
1853 }
1854
1855 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856 if (err)
1857 return err;
1858
1859 #if 0
1860 err = mii_read(np, np->phy_addr, MII_BMCR);
1861 if (err < 0)
1862 return err;
1863 bmcr = err;
1864
1865 err = mii_read(np, np->phy_addr, MII_BMSR);
1866 if (err < 0)
1867 return err;
1868 bmsr = err;
1869
1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1871 np->port, bmcr, bmsr);
1872 #endif
1873
1874 return 0;
1875 }
1876
1877 static int xcvr_init_1g(struct niu *np)
1878 {
1879 u64 val;
1880
1881 /* XXX shared resource, lock parent XXX */
1882 val = nr64(MIF_CONFIG);
1883 val &= ~MIF_CONFIG_INDIRECT_MODE;
1884 nw64(MIF_CONFIG, val);
1885
1886 return mii_init_common(np);
1887 }
1888
1889 static int niu_xcvr_init(struct niu *np)
1890 {
1891 const struct niu_phy_ops *ops = np->phy_ops;
1892 int err;
1893
1894 err = 0;
1895 if (ops->xcvr_init)
1896 err = ops->xcvr_init(np);
1897
1898 return err;
1899 }
1900
1901 static int niu_serdes_init(struct niu *np)
1902 {
1903 const struct niu_phy_ops *ops = np->phy_ops;
1904 int err;
1905
1906 err = 0;
1907 if (ops->serdes_init)
1908 err = ops->serdes_init(np);
1909
1910 return err;
1911 }
1912
1913 static void niu_init_xif(struct niu *);
1914 static void niu_handle_led(struct niu *, int status);
1915
1916 static int niu_link_status_common(struct niu *np, int link_up)
1917 {
1918 struct niu_link_config *lp = &np->link_config;
1919 struct net_device *dev = np->dev;
1920 unsigned long flags;
1921
1922 if (!netif_carrier_ok(dev) && link_up) {
1923 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927 "10Mbit/sec",
1928 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1929
1930 spin_lock_irqsave(&np->lock, flags);
1931 niu_init_xif(np);
1932 niu_handle_led(np, 1);
1933 spin_unlock_irqrestore(&np->lock, flags);
1934
1935 netif_carrier_on(dev);
1936 } else if (netif_carrier_ok(dev) && !link_up) {
1937 netif_warn(np, link, dev, "Link is down\n");
1938 spin_lock_irqsave(&np->lock, flags);
1939 niu_handle_led(np, 0);
1940 spin_unlock_irqrestore(&np->lock, flags);
1941 netif_carrier_off(dev);
1942 }
1943
1944 return 0;
1945 }
1946
1947 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1948 {
1949 int err, link_up, pma_status, pcs_status;
1950
1951 link_up = 0;
1952
1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954 MRVL88X2011_10G_PMD_STATUS_2);
1955 if (err < 0)
1956 goto out;
1957
1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960 MRVL88X2011_PMA_PMD_STATUS_1);
1961 if (err < 0)
1962 goto out;
1963
1964 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968 MRVL88X2011_PMA_PMD_STATUS_1);
1969 if (err < 0)
1970 goto out;
1971
1972 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973 MRVL88X2011_PMA_PMD_STATUS_1);
1974 if (err < 0)
1975 goto out;
1976
1977 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981 MRVL88X2011_10G_XGXS_LANE_STAT);
1982 if (err < 0)
1983 goto out;
1984
1985 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988 0x800))
1989 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991 np->link_config.active_speed = SPEED_10000;
1992 np->link_config.active_duplex = DUPLEX_FULL;
1993 err = 0;
1994 out:
1995 mrvl88x2011_act_led(np, (link_up ?
1996 MRVL88X2011_LED_CTL_PCS_ACT :
1997 MRVL88X2011_LED_CTL_OFF));
1998
1999 *link_up_p = link_up;
2000 return err;
2001 }
2002
2003 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004 {
2005 int err, link_up;
2006 link_up = 0;
2007
2008 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009 BCM8704_PMD_RCV_SIGDET);
2010 if (err < 0 || err == 0xffff)
2011 goto out;
2012 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013 err = 0;
2014 goto out;
2015 }
2016
2017 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018 BCM8704_PCS_10G_R_STATUS);
2019 if (err < 0)
2020 goto out;
2021
2022 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023 err = 0;
2024 goto out;
2025 }
2026
2027 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028 BCM8704_PHYXS_XGXS_LANE_STAT);
2029 if (err < 0)
2030 goto out;
2031 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032 PHYXS_XGXS_LANE_STAT_MAGIC |
2033 PHYXS_XGXS_LANE_STAT_PATTEST |
2034 PHYXS_XGXS_LANE_STAT_LANE3 |
2035 PHYXS_XGXS_LANE_STAT_LANE2 |
2036 PHYXS_XGXS_LANE_STAT_LANE1 |
2037 PHYXS_XGXS_LANE_STAT_LANE0)) {
2038 err = 0;
2039 np->link_config.active_speed = SPEED_INVALID;
2040 np->link_config.active_duplex = DUPLEX_INVALID;
2041 goto out;
2042 }
2043
2044 link_up = 1;
2045 np->link_config.active_speed = SPEED_10000;
2046 np->link_config.active_duplex = DUPLEX_FULL;
2047 err = 0;
2048
2049 out:
2050 *link_up_p = link_up;
2051 return err;
2052 }
2053
2054 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055 {
2056 int err, link_up;
2057
2058 link_up = 0;
2059
2060 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061 BCM8704_PMD_RCV_SIGDET);
2062 if (err < 0)
2063 goto out;
2064 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065 err = 0;
2066 goto out;
2067 }
2068
2069 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070 BCM8704_PCS_10G_R_STATUS);
2071 if (err < 0)
2072 goto out;
2073 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074 err = 0;
2075 goto out;
2076 }
2077
2078 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079 BCM8704_PHYXS_XGXS_LANE_STAT);
2080 if (err < 0)
2081 goto out;
2082
2083 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084 PHYXS_XGXS_LANE_STAT_MAGIC |
2085 PHYXS_XGXS_LANE_STAT_LANE3 |
2086 PHYXS_XGXS_LANE_STAT_LANE2 |
2087 PHYXS_XGXS_LANE_STAT_LANE1 |
2088 PHYXS_XGXS_LANE_STAT_LANE0)) {
2089 err = 0;
2090 goto out;
2091 }
2092
2093 link_up = 1;
2094 np->link_config.active_speed = SPEED_10000;
2095 np->link_config.active_duplex = DUPLEX_FULL;
2096 err = 0;
2097
2098 out:
2099 *link_up_p = link_up;
2100 return err;
2101 }
2102
2103 static int link_status_10g(struct niu *np, int *link_up_p)
2104 {
2105 unsigned long flags;
2106 int err = -EINVAL;
2107
2108 spin_lock_irqsave(&np->lock, flags);
2109
2110 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111 int phy_id;
2112
2113 phy_id = phy_decode(np->parent->port_phy, np->port);
2114 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116 /* handle different phy types */
2117 switch (phy_id & NIU_PHY_ID_MASK) {
2118 case NIU_PHY_ID_MRVL88X2011:
2119 err = link_status_10g_mrvl(np, link_up_p);
2120 break;
2121
2122 default: /* bcom 8704 */
2123 err = link_status_10g_bcom(np, link_up_p);
2124 break;
2125 }
2126 }
2127
2128 spin_unlock_irqrestore(&np->lock, flags);
2129
2130 return err;
2131 }
2132
2133 static int niu_10g_phy_present(struct niu *np)
2134 {
2135 u64 sig, mask, val;
2136
2137 sig = nr64(ESR_INT_SIGNALS);
2138 switch (np->port) {
2139 case 0:
2140 mask = ESR_INT_SIGNALS_P0_BITS;
2141 val = (ESR_INT_SRDY0_P0 |
2142 ESR_INT_DET0_P0 |
2143 ESR_INT_XSRDY_P0 |
2144 ESR_INT_XDP_P0_CH3 |
2145 ESR_INT_XDP_P0_CH2 |
2146 ESR_INT_XDP_P0_CH1 |
2147 ESR_INT_XDP_P0_CH0);
2148 break;
2149
2150 case 1:
2151 mask = ESR_INT_SIGNALS_P1_BITS;
2152 val = (ESR_INT_SRDY0_P1 |
2153 ESR_INT_DET0_P1 |
2154 ESR_INT_XSRDY_P1 |
2155 ESR_INT_XDP_P1_CH3 |
2156 ESR_INT_XDP_P1_CH2 |
2157 ESR_INT_XDP_P1_CH1 |
2158 ESR_INT_XDP_P1_CH0);
2159 break;
2160
2161 default:
2162 return 0;
2163 }
2164
2165 if ((sig & mask) != val)
2166 return 0;
2167 return 1;
2168 }
2169
2170 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171 {
2172 unsigned long flags;
2173 int err = 0;
2174 int phy_present;
2175 int phy_present_prev;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181 1 : 0;
2182 phy_present = niu_10g_phy_present(np);
2183 if (phy_present != phy_present_prev) {
2184 /* state change */
2185 if (phy_present) {
2186 /* A NEM was just plugged in */
2187 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 if (np->phy_ops->xcvr_init)
2189 err = np->phy_ops->xcvr_init(np);
2190 if (err) {
2191 err = mdio_read(np, np->phy_addr,
2192 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193 if (err == 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2195 goto out;
2196 }
2197 /* debounce */
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 }
2200 } else {
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202 *link_up_p = 0;
2203 netif_warn(np, link, np->dev,
2204 "Hotplug PHY Removed\n");
2205 }
2206 }
2207 out:
2208 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2209 err = link_status_10g_bcm8706(np, link_up_p);
2210 if (err == 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2212 *link_up_p = 1;
2213 np->link_config.active_speed = SPEED_10000;
2214 np->link_config.active_duplex = DUPLEX_FULL;
2215 }
2216 }
2217 }
2218
2219 spin_unlock_irqrestore(&np->lock, flags);
2220
2221 return 0;
2222 }
2223
2224 static int niu_link_status(struct niu *np, int *link_up_p)
2225 {
2226 const struct niu_phy_ops *ops = np->phy_ops;
2227 int err;
2228
2229 err = 0;
2230 if (ops->link_status)
2231 err = ops->link_status(np, link_up_p);
2232
2233 return err;
2234 }
2235
2236 static void niu_timer(unsigned long __opaque)
2237 {
2238 struct niu *np = (struct niu *) __opaque;
2239 unsigned long off;
2240 int err, link_up;
2241
2242 err = niu_link_status(np, &link_up);
2243 if (!err)
2244 niu_link_status_common(np, link_up);
2245
2246 if (netif_carrier_ok(np->dev))
2247 off = 5 * HZ;
2248 else
2249 off = 1 * HZ;
2250 np->timer.expires = jiffies + off;
2251
2252 add_timer(&np->timer);
2253 }
2254
2255 static const struct niu_phy_ops phy_ops_10g_serdes = {
2256 .serdes_init = serdes_init_10g_serdes,
2257 .link_status = link_status_10g_serdes,
2258 };
2259
2260 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261 .serdes_init = serdes_init_niu_10g_serdes,
2262 .link_status = link_status_10g_serdes,
2263 };
2264
2265 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266 .serdes_init = serdes_init_niu_1g_serdes,
2267 .link_status = link_status_1g_serdes,
2268 };
2269
2270 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271 .xcvr_init = xcvr_init_1g_rgmii,
2272 .link_status = link_status_1g_rgmii,
2273 };
2274
2275 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2276 .serdes_init = serdes_init_niu_10g_fiber,
2277 .xcvr_init = xcvr_init_10g,
2278 .link_status = link_status_10g,
2279 };
2280
2281 static const struct niu_phy_ops phy_ops_10g_fiber = {
2282 .serdes_init = serdes_init_10g,
2283 .xcvr_init = xcvr_init_10g,
2284 .link_status = link_status_10g,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288 .serdes_init = serdes_init_10g,
2289 .xcvr_init = xcvr_init_10g_bcm8706,
2290 .link_status = link_status_10g_hotplug,
2291 };
2292
2293 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294 .serdes_init = serdes_init_niu_10g_fiber,
2295 .xcvr_init = xcvr_init_10g_bcm8706,
2296 .link_status = link_status_10g_hotplug,
2297 };
2298
2299 static const struct niu_phy_ops phy_ops_10g_copper = {
2300 .serdes_init = serdes_init_10g,
2301 .link_status = link_status_10g, /* XXX */
2302 };
2303
2304 static const struct niu_phy_ops phy_ops_1g_fiber = {
2305 .serdes_init = serdes_init_1g,
2306 .xcvr_init = xcvr_init_1g,
2307 .link_status = link_status_1g,
2308 };
2309
2310 static const struct niu_phy_ops phy_ops_1g_copper = {
2311 .xcvr_init = xcvr_init_1g,
2312 .link_status = link_status_1g,
2313 };
2314
2315 struct niu_phy_template {
2316 const struct niu_phy_ops *ops;
2317 u32 phy_addr_base;
2318 };
2319
2320 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2321 .ops = &phy_ops_10g_fiber_niu,
2322 .phy_addr_base = 16,
2323 };
2324
2325 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326 .ops = &phy_ops_10g_serdes_niu,
2327 .phy_addr_base = 0,
2328 };
2329
2330 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331 .ops = &phy_ops_1g_serdes_niu,
2332 .phy_addr_base = 0,
2333 };
2334
2335 static const struct niu_phy_template phy_template_10g_fiber = {
2336 .ops = &phy_ops_10g_fiber,
2337 .phy_addr_base = 8,
2338 };
2339
2340 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341 .ops = &phy_ops_10g_fiber_hotplug,
2342 .phy_addr_base = 8,
2343 };
2344
2345 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346 .ops = &phy_ops_niu_10g_hotplug,
2347 .phy_addr_base = 8,
2348 };
2349
2350 static const struct niu_phy_template phy_template_10g_copper = {
2351 .ops = &phy_ops_10g_copper,
2352 .phy_addr_base = 10,
2353 };
2354
2355 static const struct niu_phy_template phy_template_1g_fiber = {
2356 .ops = &phy_ops_1g_fiber,
2357 .phy_addr_base = 0,
2358 };
2359
2360 static const struct niu_phy_template phy_template_1g_copper = {
2361 .ops = &phy_ops_1g_copper,
2362 .phy_addr_base = 0,
2363 };
2364
2365 static const struct niu_phy_template phy_template_1g_rgmii = {
2366 .ops = &phy_ops_1g_rgmii,
2367 .phy_addr_base = 0,
2368 };
2369
2370 static const struct niu_phy_template phy_template_10g_serdes = {
2371 .ops = &phy_ops_10g_serdes,
2372 .phy_addr_base = 0,
2373 };
2374
2375 static int niu_atca_port_num[4] = {
2376 0, 0, 11, 10
2377 };
2378
2379 static int serdes_init_10g_serdes(struct niu *np)
2380 {
2381 struct niu_link_config *lp = &np->link_config;
2382 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383 u64 ctrl_val, test_cfg_val, sig, mask, val;
2384 u64 reset_val;
2385
2386 switch (np->port) {
2387 case 0:
2388 reset_val = ENET_SERDES_RESET_0;
2389 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392 break;
2393 case 1:
2394 reset_val = ENET_SERDES_RESET_1;
2395 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398 break;
2399
2400 default:
2401 return -EINVAL;
2402 }
2403 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404 ENET_SERDES_CTRL_SDET_1 |
2405 ENET_SERDES_CTRL_SDET_2 |
2406 ENET_SERDES_CTRL_SDET_3 |
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415 test_cfg_val = 0;
2416
2417 if (lp->loopback_mode == LOOPBACK_PHY) {
2418 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_0_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_1_SHIFT) |
2422 (ENET_TEST_MD_PAD_LOOPBACK <<
2423 ENET_SERDES_TEST_MD_2_SHIFT) |
2424 (ENET_TEST_MD_PAD_LOOPBACK <<
2425 ENET_SERDES_TEST_MD_3_SHIFT));
2426 }
2427
2428 esr_reset(np);
2429 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430 nw64(ctrl_reg, ctrl_val);
2431 nw64(test_cfg_reg, test_cfg_val);
2432
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i = 0; i < 4; i++) {
2435 u32 rxtx_ctrl, glue0;
2436 int err;
2437
2438 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439 if (err)
2440 return err;
2441 err = esr_read_glue0(np, i, &glue0);
2442 if (err)
2443 return err;
2444
2445 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450 ESR_GLUE_CTRL0_THCNT |
2451 ESR_GLUE_CTRL0_BLTIME);
2452 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455 (BLTIME_300_CYCLES <<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459 if (err)
2460 return err;
2461 err = esr_write_glue0(np, i, glue0);
2462 if (err)
2463 return err;
2464 }
2465
2466
2467 sig = nr64(ESR_INT_SIGNALS);
2468 switch (np->port) {
2469 case 0:
2470 mask = ESR_INT_SIGNALS_P0_BITS;
2471 val = (ESR_INT_SRDY0_P0 |
2472 ESR_INT_DET0_P0 |
2473 ESR_INT_XSRDY_P0 |
2474 ESR_INT_XDP_P0_CH3 |
2475 ESR_INT_XDP_P0_CH2 |
2476 ESR_INT_XDP_P0_CH1 |
2477 ESR_INT_XDP_P0_CH0);
2478 break;
2479
2480 case 1:
2481 mask = ESR_INT_SIGNALS_P1_BITS;
2482 val = (ESR_INT_SRDY0_P1 |
2483 ESR_INT_DET0_P1 |
2484 ESR_INT_XSRDY_P1 |
2485 ESR_INT_XDP_P1_CH3 |
2486 ESR_INT_XDP_P1_CH2 |
2487 ESR_INT_XDP_P1_CH1 |
2488 ESR_INT_XDP_P1_CH0);
2489 break;
2490
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 if ((sig & mask) != val) {
2496 int err;
2497 err = serdes_init_1g_serdes(np);
2498 if (!err) {
2499 np->flags &= ~NIU_FLAGS_10G;
2500 np->mac_xcvr = MAC_XCVR_PCS;
2501 } else {
2502 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503 np->port);
2504 return -ENODEV;
2505 }
2506 }
2507
2508 return 0;
2509 }
2510
2511 static int niu_determine_phy_disposition(struct niu *np)
2512 {
2513 struct niu_parent *parent = np->parent;
2514 u8 plat_type = parent->plat_type;
2515 const struct niu_phy_template *tp;
2516 u32 phy_addr_off = 0;
2517
2518 if (plat_type == PLAT_TYPE_NIU) {
2519 switch (np->flags &
2520 (NIU_FLAGS_10G |
2521 NIU_FLAGS_FIBER |
2522 NIU_FLAGS_XCVR_SERDES)) {
2523 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524 /* 10G Serdes */
2525 tp = &phy_template_niu_10g_serdes;
2526 break;
2527 case NIU_FLAGS_XCVR_SERDES:
2528 /* 1G Serdes */
2529 tp = &phy_template_niu_1g_serdes;
2530 break;
2531 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532 /* 10G Fiber */
2533 default:
2534 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535 tp = &phy_template_niu_10g_hotplug;
2536 if (np->port == 0)
2537 phy_addr_off = 8;
2538 if (np->port == 1)
2539 phy_addr_off = 12;
2540 } else {
2541 tp = &phy_template_niu_10g_fiber;
2542 phy_addr_off += np->port;
2543 }
2544 break;
2545 }
2546 } else {
2547 switch (np->flags &
2548 (NIU_FLAGS_10G |
2549 NIU_FLAGS_FIBER |
2550 NIU_FLAGS_XCVR_SERDES)) {
2551 case 0:
2552 /* 1G copper */
2553 tp = &phy_template_1g_copper;
2554 if (plat_type == PLAT_TYPE_VF_P0)
2555 phy_addr_off = 10;
2556 else if (plat_type == PLAT_TYPE_VF_P1)
2557 phy_addr_off = 26;
2558
2559 phy_addr_off += (np->port ^ 0x3);
2560 break;
2561
2562 case NIU_FLAGS_10G:
2563 /* 10G copper */
2564 tp = &phy_template_10g_copper;
2565 break;
2566
2567 case NIU_FLAGS_FIBER:
2568 /* 1G fiber */
2569 tp = &phy_template_1g_fiber;
2570 break;
2571
2572 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573 /* 10G fiber */
2574 tp = &phy_template_10g_fiber;
2575 if (plat_type == PLAT_TYPE_VF_P0 ||
2576 plat_type == PLAT_TYPE_VF_P1)
2577 phy_addr_off = 8;
2578 phy_addr_off += np->port;
2579 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580 tp = &phy_template_10g_fiber_hotplug;
2581 if (np->port == 0)
2582 phy_addr_off = 8;
2583 if (np->port == 1)
2584 phy_addr_off = 12;
2585 }
2586 break;
2587
2588 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590 case NIU_FLAGS_XCVR_SERDES:
2591 switch(np->port) {
2592 case 0:
2593 case 1:
2594 tp = &phy_template_10g_serdes;
2595 break;
2596 case 2:
2597 case 3:
2598 tp = &phy_template_1g_rgmii;
2599 break;
2600 default:
2601 return -EINVAL;
2602 break;
2603 }
2604 phy_addr_off = niu_atca_port_num[np->port];
2605 break;
2606
2607 default:
2608 return -EINVAL;
2609 }
2610 }
2611
2612 np->phy_ops = tp->ops;
2613 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615 return 0;
2616 }
2617
2618 static int niu_init_link(struct niu *np)
2619 {
2620 struct niu_parent *parent = np->parent;
2621 int err, ignore;
2622
2623 if (parent->plat_type == PLAT_TYPE_NIU) {
2624 err = niu_xcvr_init(np);
2625 if (err)
2626 return err;
2627 msleep(200);
2628 }
2629 err = niu_serdes_init(np);
2630 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2631 return err;
2632 msleep(200);
2633 err = niu_xcvr_init(np);
2634 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2635 niu_link_status(np, &ignore);
2636 return 0;
2637 }
2638
2639 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640 {
2641 u16 reg0 = addr[4] << 8 | addr[5];
2642 u16 reg1 = addr[2] << 8 | addr[3];
2643 u16 reg2 = addr[0] << 8 | addr[1];
2644
2645 if (np->flags & NIU_FLAGS_XMAC) {
2646 nw64_mac(XMAC_ADDR0, reg0);
2647 nw64_mac(XMAC_ADDR1, reg1);
2648 nw64_mac(XMAC_ADDR2, reg2);
2649 } else {
2650 nw64_mac(BMAC_ADDR0, reg0);
2651 nw64_mac(BMAC_ADDR1, reg1);
2652 nw64_mac(BMAC_ADDR2, reg2);
2653 }
2654 }
2655
2656 static int niu_num_alt_addr(struct niu *np)
2657 {
2658 if (np->flags & NIU_FLAGS_XMAC)
2659 return XMAC_NUM_ALT_ADDR;
2660 else
2661 return BMAC_NUM_ALT_ADDR;
2662 }
2663
2664 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665 {
2666 u16 reg0 = addr[4] << 8 | addr[5];
2667 u16 reg1 = addr[2] << 8 | addr[3];
2668 u16 reg2 = addr[0] << 8 | addr[1];
2669
2670 if (index >= niu_num_alt_addr(np))
2671 return -EINVAL;
2672
2673 if (np->flags & NIU_FLAGS_XMAC) {
2674 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677 } else {
2678 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681 }
2682
2683 return 0;
2684 }
2685
2686 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687 {
2688 unsigned long reg;
2689 u64 val, mask;
2690
2691 if (index >= niu_num_alt_addr(np))
2692 return -EINVAL;
2693
2694 if (np->flags & NIU_FLAGS_XMAC) {
2695 reg = XMAC_ADDR_CMPEN;
2696 mask = 1 << index;
2697 } else {
2698 reg = BMAC_ADDR_CMPEN;
2699 mask = 1 << (index + 1);
2700 }
2701
2702 val = nr64_mac(reg);
2703 if (on)
2704 val |= mask;
2705 else
2706 val &= ~mask;
2707 nw64_mac(reg, val);
2708
2709 return 0;
2710 }
2711
2712 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713 int num, int mac_pref)
2714 {
2715 u64 val = nr64_mac(reg);
2716 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717 val |= num;
2718 if (mac_pref)
2719 val |= HOST_INFO_MPR;
2720 nw64_mac(reg, val);
2721 }
2722
2723 static int __set_rdc_table_num(struct niu *np,
2724 int xmac_index, int bmac_index,
2725 int rdc_table_num, int mac_pref)
2726 {
2727 unsigned long reg;
2728
2729 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730 return -EINVAL;
2731 if (np->flags & NIU_FLAGS_XMAC)
2732 reg = XMAC_HOST_INFO(xmac_index);
2733 else
2734 reg = BMAC_HOST_INFO(bmac_index);
2735 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736 return 0;
2737 }
2738
2739 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740 int mac_pref)
2741 {
2742 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743 }
2744
2745 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746 int mac_pref)
2747 {
2748 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749 }
2750
2751 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752 int table_num, int mac_pref)
2753 {
2754 if (idx >= niu_num_alt_addr(np))
2755 return -EINVAL;
2756 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757 }
2758
2759 static u64 vlan_entry_set_parity(u64 reg_val)
2760 {
2761 u64 port01_mask;
2762 u64 port23_mask;
2763
2764 port01_mask = 0x00ff;
2765 port23_mask = 0xff00;
2766
2767 if (hweight64(reg_val & port01_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY0;
2769 else
2770 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772 if (hweight64(reg_val & port23_mask) & 1)
2773 reg_val |= ENET_VLAN_TBL_PARITY1;
2774 else
2775 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777 return reg_val;
2778 }
2779
2780 static void vlan_tbl_write(struct niu *np, unsigned long index,
2781 int port, int vpr, int rdc_table)
2782 {
2783 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785 reg_val &= ~((ENET_VLAN_TBL_VPR |
2786 ENET_VLAN_TBL_VLANRDCTBLN) <<
2787 ENET_VLAN_TBL_SHIFT(port));
2788 if (vpr)
2789 reg_val |= (ENET_VLAN_TBL_VPR <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793 reg_val = vlan_entry_set_parity(reg_val);
2794
2795 nw64(ENET_VLAN_TBL(index), reg_val);
2796 }
2797
2798 static void vlan_tbl_clear(struct niu *np)
2799 {
2800 int i;
2801
2802 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803 nw64(ENET_VLAN_TBL(i), 0);
2804 }
2805
2806 static int tcam_wait_bit(struct niu *np, u64 bit)
2807 {
2808 int limit = 1000;
2809
2810 while (--limit > 0) {
2811 if (nr64(TCAM_CTL) & bit)
2812 break;
2813 udelay(1);
2814 }
2815 if (limit <= 0)
2816 return -ENODEV;
2817
2818 return 0;
2819 }
2820
2821 static int tcam_flush(struct niu *np, int index)
2822 {
2823 nw64(TCAM_KEY_0, 0x00);
2824 nw64(TCAM_KEY_MASK_0, 0xff);
2825 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827 return tcam_wait_bit(np, TCAM_CTL_STAT);
2828 }
2829
2830 #if 0
2831 static int tcam_read(struct niu *np, int index,
2832 u64 *key, u64 *mask)
2833 {
2834 int err;
2835
2836 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838 if (!err) {
2839 key[0] = nr64(TCAM_KEY_0);
2840 key[1] = nr64(TCAM_KEY_1);
2841 key[2] = nr64(TCAM_KEY_2);
2842 key[3] = nr64(TCAM_KEY_3);
2843 mask[0] = nr64(TCAM_KEY_MASK_0);
2844 mask[1] = nr64(TCAM_KEY_MASK_1);
2845 mask[2] = nr64(TCAM_KEY_MASK_2);
2846 mask[3] = nr64(TCAM_KEY_MASK_3);
2847 }
2848 return err;
2849 }
2850 #endif
2851
2852 static int tcam_write(struct niu *np, int index,
2853 u64 *key, u64 *mask)
2854 {
2855 nw64(TCAM_KEY_0, key[0]);
2856 nw64(TCAM_KEY_1, key[1]);
2857 nw64(TCAM_KEY_2, key[2]);
2858 nw64(TCAM_KEY_3, key[3]);
2859 nw64(TCAM_KEY_MASK_0, mask[0]);
2860 nw64(TCAM_KEY_MASK_1, mask[1]);
2861 nw64(TCAM_KEY_MASK_2, mask[2]);
2862 nw64(TCAM_KEY_MASK_3, mask[3]);
2863 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865 return tcam_wait_bit(np, TCAM_CTL_STAT);
2866 }
2867
2868 #if 0
2869 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870 {
2871 int err;
2872
2873 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875 if (!err)
2876 *data = nr64(TCAM_KEY_1);
2877
2878 return err;
2879 }
2880 #endif
2881
2882 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883 {
2884 nw64(TCAM_KEY_1, assoc_data);
2885 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887 return tcam_wait_bit(np, TCAM_CTL_STAT);
2888 }
2889
2890 static void tcam_enable(struct niu *np, int on)
2891 {
2892 u64 val = nr64(FFLP_CFG_1);
2893
2894 if (on)
2895 val &= ~FFLP_CFG_1_TCAM_DIS;
2896 else
2897 val |= FFLP_CFG_1_TCAM_DIS;
2898 nw64(FFLP_CFG_1, val);
2899 }
2900
2901 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902 {
2903 u64 val = nr64(FFLP_CFG_1);
2904
2905 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906 FFLP_CFG_1_CAMLAT |
2907 FFLP_CFG_1_CAMRATIO);
2908 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910 nw64(FFLP_CFG_1, val);
2911
2912 val = nr64(FFLP_CFG_1);
2913 val |= FFLP_CFG_1_FFLPINITDONE;
2914 nw64(FFLP_CFG_1, val);
2915 }
2916
2917 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918 int on)
2919 {
2920 unsigned long reg;
2921 u64 val;
2922
2923 if (class < CLASS_CODE_ETHERTYPE1 ||
2924 class > CLASS_CODE_ETHERTYPE2)
2925 return -EINVAL;
2926
2927 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928 val = nr64(reg);
2929 if (on)
2930 val |= L2_CLS_VLD;
2931 else
2932 val &= ~L2_CLS_VLD;
2933 nw64(reg, val);
2934
2935 return 0;
2936 }
2937
2938 #if 0
2939 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940 u64 ether_type)
2941 {
2942 unsigned long reg;
2943 u64 val;
2944
2945 if (class < CLASS_CODE_ETHERTYPE1 ||
2946 class > CLASS_CODE_ETHERTYPE2 ||
2947 (ether_type & ~(u64)0xffff) != 0)
2948 return -EINVAL;
2949
2950 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951 val = nr64(reg);
2952 val &= ~L2_CLS_ETYPE;
2953 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954 nw64(reg, val);
2955
2956 return 0;
2957 }
2958 #endif
2959
2960 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961 int on)
2962 {
2963 unsigned long reg;
2964 u64 val;
2965
2966 if (class < CLASS_CODE_USER_PROG1 ||
2967 class > CLASS_CODE_USER_PROG4)
2968 return -EINVAL;
2969
2970 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971 val = nr64(reg);
2972 if (on)
2973 val |= L3_CLS_VALID;
2974 else
2975 val &= ~L3_CLS_VALID;
2976 nw64(reg, val);
2977
2978 return 0;
2979 }
2980
2981 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982 int ipv6, u64 protocol_id,
2983 u64 tos_mask, u64 tos_val)
2984 {
2985 unsigned long reg;
2986 u64 val;
2987
2988 if (class < CLASS_CODE_USER_PROG1 ||
2989 class > CLASS_CODE_USER_PROG4 ||
2990 (protocol_id & ~(u64)0xff) != 0 ||
2991 (tos_mask & ~(u64)0xff) != 0 ||
2992 (tos_val & ~(u64)0xff) != 0)
2993 return -EINVAL;
2994
2995 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996 val = nr64(reg);
2997 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998 L3_CLS_TOSMASK | L3_CLS_TOS);
2999 if (ipv6)
3000 val |= L3_CLS_IPVER;
3001 val |= (protocol_id << L3_CLS_PID_SHIFT);
3002 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003 val |= (tos_val << L3_CLS_TOS_SHIFT);
3004 nw64(reg, val);
3005
3006 return 0;
3007 }
3008
3009 static int tcam_early_init(struct niu *np)
3010 {
3011 unsigned long i;
3012 int err;
3013
3014 tcam_enable(np, 0);
3015 tcam_set_lat_and_ratio(np,
3016 DEFAULT_TCAM_LATENCY,
3017 DEFAULT_TCAM_ACCESS_RATIO);
3018 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019 err = tcam_user_eth_class_enable(np, i, 0);
3020 if (err)
3021 return err;
3022 }
3023 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024 err = tcam_user_ip_class_enable(np, i, 0);
3025 if (err)
3026 return err;
3027 }
3028
3029 return 0;
3030 }
3031
3032 static int tcam_flush_all(struct niu *np)
3033 {
3034 unsigned long i;
3035
3036 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037 int err = tcam_flush(np, i);
3038 if (err)
3039 return err;
3040 }
3041 return 0;
3042 }
3043
3044 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045 {
3046 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3047 }
3048
3049 #if 0
3050 static int hash_read(struct niu *np, unsigned long partition,
3051 unsigned long index, unsigned long num_entries,
3052 u64 *data)
3053 {
3054 u64 val = hash_addr_regval(index, num_entries);
3055 unsigned long i;
3056
3057 if (partition >= FCRAM_NUM_PARTITIONS ||
3058 index + num_entries > FCRAM_SIZE)
3059 return -EINVAL;
3060
3061 nw64(HASH_TBL_ADDR(partition), val);
3062 for (i = 0; i < num_entries; i++)
3063 data[i] = nr64(HASH_TBL_DATA(partition));
3064
3065 return 0;
3066 }
3067 #endif
3068
3069 static int hash_write(struct niu *np, unsigned long partition,
3070 unsigned long index, unsigned long num_entries,
3071 u64 *data)
3072 {
3073 u64 val = hash_addr_regval(index, num_entries);
3074 unsigned long i;
3075
3076 if (partition >= FCRAM_NUM_PARTITIONS ||
3077 index + (num_entries * 8) > FCRAM_SIZE)
3078 return -EINVAL;
3079
3080 nw64(HASH_TBL_ADDR(partition), val);
3081 for (i = 0; i < num_entries; i++)
3082 nw64(HASH_TBL_DATA(partition), data[i]);
3083
3084 return 0;
3085 }
3086
3087 static void fflp_reset(struct niu *np)
3088 {
3089 u64 val;
3090
3091 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3092 udelay(10);
3093 nw64(FFLP_CFG_1, 0);
3094
3095 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3096 nw64(FFLP_CFG_1, val);
3097 }
3098
3099 static void fflp_set_timings(struct niu *np)
3100 {
3101 u64 val = nr64(FFLP_CFG_1);
3102
3103 val &= ~FFLP_CFG_1_FFLPINITDONE;
3104 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3105 nw64(FFLP_CFG_1, val);
3106
3107 val = nr64(FFLP_CFG_1);
3108 val |= FFLP_CFG_1_FFLPINITDONE;
3109 nw64(FFLP_CFG_1, val);
3110
3111 val = nr64(FCRAM_REF_TMR);
3112 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3113 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3114 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3115 nw64(FCRAM_REF_TMR, val);
3116 }
3117
3118 static int fflp_set_partition(struct niu *np, u64 partition,
3119 u64 mask, u64 base, int enable)
3120 {
3121 unsigned long reg;
3122 u64 val;
3123
3124 if (partition >= FCRAM_NUM_PARTITIONS ||
3125 (mask & ~(u64)0x1f) != 0 ||
3126 (base & ~(u64)0x1f) != 0)
3127 return -EINVAL;
3128
3129 reg = FLW_PRT_SEL(partition);
3130
3131 val = nr64(reg);
3132 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3133 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3134 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3135 if (enable)
3136 val |= FLW_PRT_SEL_EXT;
3137 nw64(reg, val);
3138
3139 return 0;
3140 }
3141
3142 static int fflp_disable_all_partitions(struct niu *np)
3143 {
3144 unsigned long i;
3145
3146 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3147 int err = fflp_set_partition(np, 0, 0, 0, 0);
3148 if (err)
3149 return err;
3150 }
3151 return 0;
3152 }
3153
3154 static void fflp_llcsnap_enable(struct niu *np, int on)
3155 {
3156 u64 val = nr64(FFLP_CFG_1);
3157
3158 if (on)
3159 val |= FFLP_CFG_1_LLCSNAP;
3160 else
3161 val &= ~FFLP_CFG_1_LLCSNAP;
3162 nw64(FFLP_CFG_1, val);
3163 }
3164
3165 static void fflp_errors_enable(struct niu *np, int on)
3166 {
3167 u64 val = nr64(FFLP_CFG_1);
3168
3169 if (on)
3170 val &= ~FFLP_CFG_1_ERRORDIS;
3171 else
3172 val |= FFLP_CFG_1_ERRORDIS;
3173 nw64(FFLP_CFG_1, val);
3174 }
3175
3176 static int fflp_hash_clear(struct niu *np)
3177 {
3178 struct fcram_hash_ipv4 ent;
3179 unsigned long i;
3180
3181 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3182 memset(&ent, 0, sizeof(ent));
3183 ent.header = HASH_HEADER_EXT;
3184
3185 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3186 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3187 if (err)
3188 return err;
3189 }
3190 return 0;
3191 }
3192
3193 static int fflp_early_init(struct niu *np)
3194 {
3195 struct niu_parent *parent;
3196 unsigned long flags;
3197 int err;
3198
3199 niu_lock_parent(np, flags);
3200
3201 parent = np->parent;
3202 err = 0;
3203 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3204 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3205 fflp_reset(np);
3206 fflp_set_timings(np);
3207 err = fflp_disable_all_partitions(np);
3208 if (err) {
3209 netif_printk(np, probe, KERN_DEBUG, np->dev,
3210 "fflp_disable_all_partitions failed, err=%d\n",
3211 err);
3212 goto out;
3213 }
3214 }
3215
3216 err = tcam_early_init(np);
3217 if (err) {
3218 netif_printk(np, probe, KERN_DEBUG, np->dev,
3219 "tcam_early_init failed, err=%d\n", err);
3220 goto out;
3221 }
3222 fflp_llcsnap_enable(np, 1);
3223 fflp_errors_enable(np, 0);
3224 nw64(H1POLY, 0);
3225 nw64(H2POLY, 0);
3226
3227 err = tcam_flush_all(np);
3228 if (err) {
3229 netif_printk(np, probe, KERN_DEBUG, np->dev,
3230 "tcam_flush_all failed, err=%d\n", err);
3231 goto out;
3232 }
3233 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3234 err = fflp_hash_clear(np);
3235 if (err) {
3236 netif_printk(np, probe, KERN_DEBUG, np->dev,
3237 "fflp_hash_clear failed, err=%d\n",
3238 err);
3239 goto out;
3240 }
3241 }
3242
3243 vlan_tbl_clear(np);
3244
3245 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3246 }
3247 out:
3248 niu_unlock_parent(np, flags);
3249 return err;
3250 }
3251
3252 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3253 {
3254 if (class_code < CLASS_CODE_USER_PROG1 ||
3255 class_code > CLASS_CODE_SCTP_IPV6)
3256 return -EINVAL;
3257
3258 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3259 return 0;
3260 }
3261
3262 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3263 {
3264 if (class_code < CLASS_CODE_USER_PROG1 ||
3265 class_code > CLASS_CODE_SCTP_IPV6)
3266 return -EINVAL;
3267
3268 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3269 return 0;
3270 }
3271
3272 /* Entries for the ports are interleaved in the TCAM */
3273 static u16 tcam_get_index(struct niu *np, u16 idx)
3274 {
3275 /* One entry reserved for IP fragment rule */
3276 if (idx >= (np->clas.tcam_sz - 1))
3277 idx = 0;
3278 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3279 }
3280
3281 static u16 tcam_get_size(struct niu *np)
3282 {
3283 /* One entry reserved for IP fragment rule */
3284 return np->clas.tcam_sz - 1;
3285 }
3286
3287 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3288 {
3289 /* One entry reserved for IP fragment rule */
3290 return np->clas.tcam_valid_entries - 1;
3291 }
3292
3293 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3294 u32 offset, u32 size)
3295 {
3296 int i = skb_shinfo(skb)->nr_frags;
3297 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3298
3299 frag->page = page;
3300 frag->page_offset = offset;
3301 frag->size = size;
3302
3303 skb->len += size;
3304 skb->data_len += size;
3305 skb->truesize += size;
3306
3307 skb_shinfo(skb)->nr_frags = i + 1;
3308 }
3309
3310 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3311 {
3312 a >>= PAGE_SHIFT;
3313 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3314
3315 return a & (MAX_RBR_RING_SIZE - 1);
3316 }
3317
3318 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3319 struct page ***link)
3320 {
3321 unsigned int h = niu_hash_rxaddr(rp, addr);
3322 struct page *p, **pp;
3323
3324 addr &= PAGE_MASK;
3325 pp = &rp->rxhash[h];
3326 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3327 if (p->index == addr) {
3328 *link = pp;
3329 goto found;
3330 }
3331 }
3332 BUG();
3333
3334 found:
3335 return p;
3336 }
3337
3338 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3339 {
3340 unsigned int h = niu_hash_rxaddr(rp, base);
3341
3342 page->index = base;
3343 page->mapping = (struct address_space *) rp->rxhash[h];
3344 rp->rxhash[h] = page;
3345 }
3346
3347 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3348 gfp_t mask, int start_index)
3349 {
3350 struct page *page;
3351 u64 addr;
3352 int i;
3353
3354 page = alloc_page(mask);
3355 if (!page)
3356 return -ENOMEM;
3357
3358 addr = np->ops->map_page(np->device, page, 0,
3359 PAGE_SIZE, DMA_FROM_DEVICE);
3360
3361 niu_hash_page(rp, page, addr);
3362 if (rp->rbr_blocks_per_page > 1)
3363 atomic_add(rp->rbr_blocks_per_page - 1,
3364 &compound_head(page)->_count);
3365
3366 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3367 __le32 *rbr = &rp->rbr[start_index + i];
3368
3369 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3370 addr += rp->rbr_block_size;
3371 }
3372
3373 return 0;
3374 }
3375
3376 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3377 {
3378 int index = rp->rbr_index;
3379
3380 rp->rbr_pending++;
3381 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3382 int err = niu_rbr_add_page(np, rp, mask, index);
3383
3384 if (unlikely(err)) {
3385 rp->rbr_pending--;
3386 return;
3387 }
3388
3389 rp->rbr_index += rp->rbr_blocks_per_page;
3390 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3391 if (rp->rbr_index == rp->rbr_table_size)
3392 rp->rbr_index = 0;
3393
3394 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3395 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3396 rp->rbr_pending = 0;
3397 }
3398 }
3399 }
3400
3401 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3402 {
3403 unsigned int index = rp->rcr_index;
3404 int num_rcr = 0;
3405
3406 rp->rx_dropped++;
3407 while (1) {
3408 struct page *page, **link;
3409 u64 addr, val;
3410 u32 rcr_size;
3411
3412 num_rcr++;
3413
3414 val = le64_to_cpup(&rp->rcr[index]);
3415 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3416 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3417 page = niu_find_rxpage(rp, addr, &link);
3418
3419 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3420 RCR_ENTRY_PKTBUFSZ_SHIFT];
3421 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3422 *link = (struct page *) page->mapping;
3423 np->ops->unmap_page(np->device, page->index,
3424 PAGE_SIZE, DMA_FROM_DEVICE);
3425 page->index = 0;
3426 page->mapping = NULL;
3427 __free_page(page);
3428 rp->rbr_refill_pending++;
3429 }
3430
3431 index = NEXT_RCR(rp, index);
3432 if (!(val & RCR_ENTRY_MULTI))
3433 break;
3434
3435 }
3436 rp->rcr_index = index;
3437
3438 return num_rcr;
3439 }
3440
3441 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3442 struct rx_ring_info *rp)
3443 {
3444 unsigned int index = rp->rcr_index;
3445 struct rx_pkt_hdr1 *rh;
3446 struct sk_buff *skb;
3447 int len, num_rcr;
3448
3449 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3450 if (unlikely(!skb))
3451 return niu_rx_pkt_ignore(np, rp);
3452
3453 num_rcr = 0;
3454 while (1) {
3455 struct page *page, **link;
3456 u32 rcr_size, append_size;
3457 u64 addr, val, off;
3458
3459 num_rcr++;
3460
3461 val = le64_to_cpup(&rp->rcr[index]);
3462
3463 len = (val & RCR_ENTRY_L2_LEN) >>
3464 RCR_ENTRY_L2_LEN_SHIFT;
3465 len -= ETH_FCS_LEN;
3466
3467 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3468 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3469 page = niu_find_rxpage(rp, addr, &link);
3470
3471 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3472 RCR_ENTRY_PKTBUFSZ_SHIFT];
3473
3474 off = addr & ~PAGE_MASK;
3475 append_size = rcr_size;
3476 if (num_rcr == 1) {
3477 int ptype;
3478
3479 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3480 if ((ptype == RCR_PKT_TYPE_TCP ||
3481 ptype == RCR_PKT_TYPE_UDP) &&
3482 !(val & (RCR_ENTRY_NOPORT |
3483 RCR_ENTRY_ERROR)))
3484 skb->ip_summed = CHECKSUM_UNNECESSARY;
3485 else
3486 skb_checksum_none_assert(skb);
3487 } else if (!(val & RCR_ENTRY_MULTI))
3488 append_size = len - skb->len;
3489
3490 niu_rx_skb_append(skb, page, off, append_size);
3491 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3492 *link = (struct page *) page->mapping;
3493 np->ops->unmap_page(np->device, page->index,
3494 PAGE_SIZE, DMA_FROM_DEVICE);
3495 page->index = 0;
3496 page->mapping = NULL;
3497 rp->rbr_refill_pending++;
3498 } else
3499 get_page(page);
3500
3501 index = NEXT_RCR(rp, index);
3502 if (!(val & RCR_ENTRY_MULTI))
3503 break;
3504
3505 }
3506 rp->rcr_index = index;
3507
3508 len += sizeof(*rh);
3509 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3510 __pskb_pull_tail(skb, len);
3511
3512 rh = (struct rx_pkt_hdr1 *) skb->data;
3513 if (np->dev->features & NETIF_F_RXHASH)
3514 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3515 (u32)rh->hashval2_1 << 16 |
3516 (u32)rh->hashval1_1 << 8 |
3517 (u32)rh->hashval1_2 << 0);
3518 skb_pull(skb, sizeof(*rh));
3519
3520 rp->rx_packets++;
3521 rp->rx_bytes += skb->len;
3522
3523 skb->protocol = eth_type_trans(skb, np->dev);
3524 skb_record_rx_queue(skb, rp->rx_channel);
3525 napi_gro_receive(napi, skb);
3526
3527 return num_rcr;
3528 }
3529
3530 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3531 {
3532 int blocks_per_page = rp->rbr_blocks_per_page;
3533 int err, index = rp->rbr_index;
3534
3535 err = 0;
3536 while (index < (rp->rbr_table_size - blocks_per_page)) {
3537 err = niu_rbr_add_page(np, rp, mask, index);
3538 if (err)
3539 break;
3540
3541 index += blocks_per_page;
3542 }
3543
3544 rp->rbr_index = index;
3545 return err;
3546 }
3547
3548 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3549 {
3550 int i;
3551
3552 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3553 struct page *page;
3554
3555 page = rp->rxhash[i];
3556 while (page) {
3557 struct page *next = (struct page *) page->mapping;
3558 u64 base = page->index;
3559
3560 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3561 DMA_FROM_DEVICE);
3562 page->index = 0;
3563 page->mapping = NULL;
3564
3565 __free_page(page);
3566
3567 page = next;
3568 }
3569 }
3570
3571 for (i = 0; i < rp->rbr_table_size; i++)
3572 rp->rbr[i] = cpu_to_le32(0);
3573 rp->rbr_index = 0;
3574 }
3575
3576 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3577 {
3578 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3579 struct sk_buff *skb = tb->skb;
3580 struct tx_pkt_hdr *tp;
3581 u64 tx_flags;
3582 int i, len;
3583
3584 tp = (struct tx_pkt_hdr *) skb->data;
3585 tx_flags = le64_to_cpup(&tp->flags);
3586
3587 rp->tx_packets++;
3588 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3589 ((tx_flags & TXHDR_PAD) / 2));
3590
3591 len = skb_headlen(skb);
3592 np->ops->unmap_single(np->device, tb->mapping,
3593 len, DMA_TO_DEVICE);
3594
3595 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3596 rp->mark_pending--;
3597
3598 tb->skb = NULL;
3599 do {
3600 idx = NEXT_TX(rp, idx);
3601 len -= MAX_TX_DESC_LEN;
3602 } while (len > 0);
3603
3604 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3605 tb = &rp->tx_buffs[idx];
3606 BUG_ON(tb->skb != NULL);
3607 np->ops->unmap_page(np->device, tb->mapping,
3608 skb_shinfo(skb)->frags[i].size,
3609 DMA_TO_DEVICE);
3610 idx = NEXT_TX(rp, idx);
3611 }
3612
3613 dev_kfree_skb(skb);
3614
3615 return idx;
3616 }
3617
3618 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3619
3620 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3621 {
3622 struct netdev_queue *txq;
3623 u16 pkt_cnt, tmp;
3624 int cons, index;
3625 u64 cs;
3626
3627 index = (rp - np->tx_rings);
3628 txq = netdev_get_tx_queue(np->dev, index);
3629
3630 cs = rp->tx_cs;
3631 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3632 goto out;
3633
3634 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3635 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3636 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3637
3638 rp->last_pkt_cnt = tmp;
3639
3640 cons = rp->cons;
3641
3642 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3643 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3644
3645 while (pkt_cnt--)
3646 cons = release_tx_packet(np, rp, cons);
3647
3648 rp->cons = cons;
3649 smp_mb();
3650
3651 out:
3652 if (unlikely(netif_tx_queue_stopped(txq) &&
3653 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3654 __netif_tx_lock(txq, smp_processor_id());
3655 if (netif_tx_queue_stopped(txq) &&
3656 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3657 netif_tx_wake_queue(txq);
3658 __netif_tx_unlock(txq);
3659 }
3660 }
3661
3662 static inline void niu_sync_rx_discard_stats(struct niu *np,
3663 struct rx_ring_info *rp,
3664 const int limit)
3665 {
3666 /* This elaborate scheme is needed for reading the RX discard
3667 * counters, as they are only 16-bit and can overflow quickly,
3668 * and because the overflow indication bit is not usable as
3669 * the counter value does not wrap, but remains at max value
3670 * 0xFFFF.
3671 *
3672 * In theory and in practice counters can be lost in between
3673 * reading nr64() and clearing the counter nw64(). For this
3674 * reason, the number of counter clearings nw64() is
3675 * limited/reduced though the limit parameter.
3676 */
3677 int rx_channel = rp->rx_channel;
3678 u32 misc, wred;
3679
3680 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3681 * following discard events: IPP (Input Port Process),
3682 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3683 * Block Ring) prefetch buffer is empty.
3684 */
3685 misc = nr64(RXMISC(rx_channel));
3686 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3687 nw64(RXMISC(rx_channel), 0);
3688 rp->rx_errors += misc & RXMISC_COUNT;
3689
3690 if (unlikely(misc & RXMISC_OFLOW))
3691 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3692 rx_channel);
3693
3694 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3695 "rx-%d: MISC drop=%u over=%u\n",
3696 rx_channel, misc, misc-limit);
3697 }
3698
3699 /* WRED (Weighted Random Early Discard) by hardware */
3700 wred = nr64(RED_DIS_CNT(rx_channel));
3701 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3702 nw64(RED_DIS_CNT(rx_channel), 0);
3703 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3704
3705 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3706 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3707
3708 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3709 "rx-%d: WRED drop=%u over=%u\n",
3710 rx_channel, wred, wred-limit);
3711 }
3712 }
3713
3714 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3715 struct rx_ring_info *rp, int budget)
3716 {
3717 int qlen, rcr_done = 0, work_done = 0;
3718 struct rxdma_mailbox *mbox = rp->mbox;
3719 u64 stat;
3720
3721 #if 1
3722 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3723 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3724 #else
3725 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3726 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3727 #endif
3728 mbox->rx_dma_ctl_stat = 0;
3729 mbox->rcrstat_a = 0;
3730
3731 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3732 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3733 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3734
3735 rcr_done = work_done = 0;
3736 qlen = min(qlen, budget);
3737 while (work_done < qlen) {
3738 rcr_done += niu_process_rx_pkt(napi, np, rp);
3739 work_done++;
3740 }
3741
3742 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3743 unsigned int i;
3744
3745 for (i = 0; i < rp->rbr_refill_pending; i++)
3746 niu_rbr_refill(np, rp, GFP_ATOMIC);
3747 rp->rbr_refill_pending = 0;
3748 }
3749
3750 stat = (RX_DMA_CTL_STAT_MEX |
3751 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3752 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3753
3754 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3755
3756 /* Only sync discards stats when qlen indicate potential for drops */
3757 if (qlen > 10)
3758 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3759
3760 return work_done;
3761 }
3762
3763 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3764 {
3765 u64 v0 = lp->v0;
3766 u32 tx_vec = (v0 >> 32);
3767 u32 rx_vec = (v0 & 0xffffffff);
3768 int i, work_done = 0;
3769
3770 netif_printk(np, intr, KERN_DEBUG, np->dev,
3771 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3772
3773 for (i = 0; i < np->num_tx_rings; i++) {
3774 struct tx_ring_info *rp = &np->tx_rings[i];
3775 if (tx_vec & (1 << rp->tx_channel))
3776 niu_tx_work(np, rp);
3777 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3778 }
3779
3780 for (i = 0; i < np->num_rx_rings; i++) {
3781 struct rx_ring_info *rp = &np->rx_rings[i];
3782
3783 if (rx_vec & (1 << rp->rx_channel)) {
3784 int this_work_done;
3785
3786 this_work_done = niu_rx_work(&lp->napi, np, rp,
3787 budget);
3788
3789 budget -= this_work_done;
3790 work_done += this_work_done;
3791 }
3792 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3793 }
3794
3795 return work_done;
3796 }
3797
3798 static int niu_poll(struct napi_struct *napi, int budget)
3799 {
3800 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3801 struct niu *np = lp->np;
3802 int work_done;
3803
3804 work_done = niu_poll_core(np, lp, budget);
3805
3806 if (work_done < budget) {
3807 napi_complete(napi);
3808 niu_ldg_rearm(np, lp, 1);
3809 }
3810 return work_done;
3811 }
3812
3813 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3814 u64 stat)
3815 {
3816 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3817
3818 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3819 pr_cont("RBR_TMOUT ");
3820 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3821 pr_cont("RSP_CNT ");
3822 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3823 pr_cont("BYTE_EN_BUS ");
3824 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3825 pr_cont("RSP_DAT ");
3826 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3827 pr_cont("RCR_ACK ");
3828 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3829 pr_cont("RCR_SHA_PAR ");
3830 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3831 pr_cont("RBR_PRE_PAR ");
3832 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3833 pr_cont("CONFIG ");
3834 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3835 pr_cont("RCRINCON ");
3836 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3837 pr_cont("RCRFULL ");
3838 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3839 pr_cont("RBRFULL ");
3840 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3841 pr_cont("RBRLOGPAGE ");
3842 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3843 pr_cont("CFIGLOGPAGE ");
3844 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3845 pr_cont("DC_FIDO ");
3846
3847 pr_cont(")\n");
3848 }
3849
3850 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3851 {
3852 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3853 int err = 0;
3854
3855
3856 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3857 RX_DMA_CTL_STAT_PORT_FATAL))
3858 err = -EINVAL;
3859
3860 if (err) {
3861 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3862 rp->rx_channel,
3863 (unsigned long long) stat);
3864
3865 niu_log_rxchan_errors(np, rp, stat);
3866 }
3867
3868 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3869 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3870
3871 return err;
3872 }
3873
3874 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3875 u64 cs)
3876 {
3877 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3878
3879 if (cs & TX_CS_MBOX_ERR)
3880 pr_cont("MBOX ");
3881 if (cs & TX_CS_PKT_SIZE_ERR)
3882 pr_cont("PKT_SIZE ");
3883 if (cs & TX_CS_TX_RING_OFLOW)
3884 pr_cont("TX_RING_OFLOW ");
3885 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3886 pr_cont("PREF_BUF_PAR ");
3887 if (cs & TX_CS_NACK_PREF)
3888 pr_cont("NACK_PREF ");
3889 if (cs & TX_CS_NACK_PKT_RD)
3890 pr_cont("NACK_PKT_RD ");
3891 if (cs & TX_CS_CONF_PART_ERR)
3892 pr_cont("CONF_PART ");
3893 if (cs & TX_CS_PKT_PRT_ERR)
3894 pr_cont("PKT_PTR ");
3895
3896 pr_cont(")\n");
3897 }
3898
3899 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3900 {
3901 u64 cs, logh, logl;
3902
3903 cs = nr64(TX_CS(rp->tx_channel));
3904 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3905 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3906
3907 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3908 rp->tx_channel,
3909 (unsigned long long)cs,
3910 (unsigned long long)logh,
3911 (unsigned long long)logl);
3912
3913 niu_log_txchan_errors(np, rp, cs);
3914
3915 return -ENODEV;
3916 }
3917
3918 static int niu_mif_interrupt(struct niu *np)
3919 {
3920 u64 mif_status = nr64(MIF_STATUS);
3921 int phy_mdint = 0;
3922
3923 if (np->flags & NIU_FLAGS_XMAC) {
3924 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3925
3926 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3927 phy_mdint = 1;
3928 }
3929
3930 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3931 (unsigned long long)mif_status, phy_mdint);
3932
3933 return -ENODEV;
3934 }
3935
3936 static void niu_xmac_interrupt(struct niu *np)
3937 {
3938 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3939 u64 val;
3940
3941 val = nr64_mac(XTXMAC_STATUS);
3942 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3943 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3944 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3945 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3946 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3947 mp->tx_fifo_errors++;
3948 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3949 mp->tx_overflow_errors++;
3950 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3951 mp->tx_max_pkt_size_errors++;
3952 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3953 mp->tx_underflow_errors++;
3954
3955 val = nr64_mac(XRXMAC_STATUS);
3956 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3957 mp->rx_local_faults++;
3958 if (val & XRXMAC_STATUS_RFLT_DET)
3959 mp->rx_remote_faults++;
3960 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3961 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3962 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3963 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3964 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3965 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3967 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3969 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3970 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3971 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3972 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3973 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3974 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3975 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3976 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3977 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3978 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3979 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3980 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3981 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3982 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3983 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3984 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3985 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3986 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3987 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3988 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3989 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3990 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3991 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3992 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3993 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3994 if (val & XRXMAC_STATUS_RXUFLOW)
3995 mp->rx_underflows++;
3996 if (val & XRXMAC_STATUS_RXOFLOW)
3997 mp->rx_overflows++;
3998
3999 val = nr64_mac(XMAC_FC_STAT);
4000 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4001 mp->pause_off_state++;
4002 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4003 mp->pause_on_state++;
4004 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4005 mp->pause_received++;
4006 }
4007
4008 static void niu_bmac_interrupt(struct niu *np)
4009 {
4010 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4011 u64 val;
4012
4013 val = nr64_mac(BTXMAC_STATUS);
4014 if (val & BTXMAC_STATUS_UNDERRUN)
4015 mp->tx_underflow_errors++;
4016 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4017 mp->tx_max_pkt_size_errors++;
4018 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4019 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4020 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4021 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4022
4023 val = nr64_mac(BRXMAC_STATUS);
4024 if (val & BRXMAC_STATUS_OVERFLOW)
4025 mp->rx_overflows++;
4026 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4027 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4028 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4029 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4030 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4031 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4032 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4033 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4034
4035 val = nr64_mac(BMAC_CTRL_STATUS);
4036 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4037 mp->pause_off_state++;
4038 if (val & BMAC_CTRL_STATUS_PAUSE)
4039 mp->pause_on_state++;
4040 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4041 mp->pause_received++;
4042 }
4043
4044 static int niu_mac_interrupt(struct niu *np)
4045 {
4046 if (np->flags & NIU_FLAGS_XMAC)
4047 niu_xmac_interrupt(np);
4048 else
4049 niu_bmac_interrupt(np);
4050
4051 return 0;
4052 }
4053
4054 static void niu_log_device_error(struct niu *np, u64 stat)
4055 {
4056 netdev_err(np->dev, "Core device errors ( ");
4057
4058 if (stat & SYS_ERR_MASK_META2)
4059 pr_cont("META2 ");
4060 if (stat & SYS_ERR_MASK_META1)
4061 pr_cont("META1 ");
4062 if (stat & SYS_ERR_MASK_PEU)
4063 pr_cont("PEU ");
4064 if (stat & SYS_ERR_MASK_TXC)
4065 pr_cont("TXC ");
4066 if (stat & SYS_ERR_MASK_RDMC)
4067 pr_cont("RDMC ");
4068 if (stat & SYS_ERR_MASK_TDMC)
4069 pr_cont("TDMC ");
4070 if (stat & SYS_ERR_MASK_ZCP)
4071 pr_cont("ZCP ");
4072 if (stat & SYS_ERR_MASK_FFLP)
4073 pr_cont("FFLP ");
4074 if (stat & SYS_ERR_MASK_IPP)
4075 pr_cont("IPP ");
4076 if (stat & SYS_ERR_MASK_MAC)
4077 pr_cont("MAC ");
4078 if (stat & SYS_ERR_MASK_SMX)
4079 pr_cont("SMX ");
4080
4081 pr_cont(")\n");
4082 }
4083
4084 static int niu_device_error(struct niu *np)
4085 {
4086 u64 stat = nr64(SYS_ERR_STAT);
4087
4088 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4089 (unsigned long long)stat);
4090
4091 niu_log_device_error(np, stat);
4092
4093 return -ENODEV;
4094 }
4095
4096 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4097 u64 v0, u64 v1, u64 v2)
4098 {
4099
4100 int i, err = 0;
4101
4102 lp->v0 = v0;
4103 lp->v1 = v1;
4104 lp->v2 = v2;
4105
4106 if (v1 & 0x00000000ffffffffULL) {
4107 u32 rx_vec = (v1 & 0xffffffff);
4108
4109 for (i = 0; i < np->num_rx_rings; i++) {
4110 struct rx_ring_info *rp = &np->rx_rings[i];
4111
4112 if (rx_vec & (1 << rp->rx_channel)) {
4113 int r = niu_rx_error(np, rp);
4114 if (r) {
4115 err = r;
4116 } else {
4117 if (!v0)
4118 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4119 RX_DMA_CTL_STAT_MEX);
4120 }
4121 }
4122 }
4123 }
4124 if (v1 & 0x7fffffff00000000ULL) {
4125 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4126
4127 for (i = 0; i < np->num_tx_rings; i++) {
4128 struct tx_ring_info *rp = &np->tx_rings[i];
4129
4130 if (tx_vec & (1 << rp->tx_channel)) {
4131 int r = niu_tx_error(np, rp);
4132 if (r)
4133 err = r;
4134 }
4135 }
4136 }
4137 if ((v0 | v1) & 0x8000000000000000ULL) {
4138 int r = niu_mif_interrupt(np);
4139 if (r)
4140 err = r;
4141 }
4142 if (v2) {
4143 if (v2 & 0x01ef) {
4144 int r = niu_mac_interrupt(np);
4145 if (r)
4146 err = r;
4147 }
4148 if (v2 & 0x0210) {
4149 int r = niu_device_error(np);
4150 if (r)
4151 err = r;
4152 }
4153 }
4154
4155 if (err)
4156 niu_enable_interrupts(np, 0);
4157
4158 return err;
4159 }
4160
4161 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4162 int ldn)
4163 {
4164 struct rxdma_mailbox *mbox = rp->mbox;
4165 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4166
4167 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4168 RX_DMA_CTL_STAT_RCRTO);
4169 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4170
4171 netif_printk(np, intr, KERN_DEBUG, np->dev,
4172 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4173 }
4174
4175 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4176 int ldn)
4177 {
4178 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4179
4180 netif_printk(np, intr, KERN_DEBUG, np->dev,
4181 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4182 }
4183
4184 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4185 {
4186 struct niu_parent *parent = np->parent;
4187 u32 rx_vec, tx_vec;
4188 int i;
4189
4190 tx_vec = (v0 >> 32);
4191 rx_vec = (v0 & 0xffffffff);
4192
4193 for (i = 0; i < np->num_rx_rings; i++) {
4194 struct rx_ring_info *rp = &np->rx_rings[i];
4195 int ldn = LDN_RXDMA(rp->rx_channel);
4196
4197 if (parent->ldg_map[ldn] != ldg)
4198 continue;
4199
4200 nw64(LD_IM0(ldn), LD_IM0_MASK);
4201 if (rx_vec & (1 << rp->rx_channel))
4202 niu_rxchan_intr(np, rp, ldn);
4203 }
4204
4205 for (i = 0; i < np->num_tx_rings; i++) {
4206 struct tx_ring_info *rp = &np->tx_rings[i];
4207 int ldn = LDN_TXDMA(rp->tx_channel);
4208
4209 if (parent->ldg_map[ldn] != ldg)
4210 continue;
4211
4212 nw64(LD_IM0(ldn), LD_IM0_MASK);
4213 if (tx_vec & (1 << rp->tx_channel))
4214 niu_txchan_intr(np, rp, ldn);
4215 }
4216 }
4217
4218 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4219 u64 v0, u64 v1, u64 v2)
4220 {
4221 if (likely(napi_schedule_prep(&lp->napi))) {
4222 lp->v0 = v0;
4223 lp->v1 = v1;
4224 lp->v2 = v2;
4225 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4226 __napi_schedule(&lp->napi);
4227 }
4228 }
4229
4230 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4231 {
4232 struct niu_ldg *lp = dev_id;
4233 struct niu *np = lp->np;
4234 int ldg = lp->ldg_num;
4235 unsigned long flags;
4236 u64 v0, v1, v2;
4237
4238 if (netif_msg_intr(np))
4239 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4240 __func__, lp, ldg);
4241
4242 spin_lock_irqsave(&np->lock, flags);
4243
4244 v0 = nr64(LDSV0(ldg));
4245 v1 = nr64(LDSV1(ldg));
4246 v2 = nr64(LDSV2(ldg));
4247
4248 if (netif_msg_intr(np))
4249 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4250 (unsigned long long) v0,
4251 (unsigned long long) v1,
4252 (unsigned long long) v2);
4253
4254 if (unlikely(!v0 && !v1 && !v2)) {
4255 spin_unlock_irqrestore(&np->lock, flags);
4256 return IRQ_NONE;
4257 }
4258
4259 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4260 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4261 if (err)
4262 goto out;
4263 }
4264 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4265 niu_schedule_napi(np, lp, v0, v1, v2);
4266 else
4267 niu_ldg_rearm(np, lp, 1);
4268 out:
4269 spin_unlock_irqrestore(&np->lock, flags);
4270
4271 return IRQ_HANDLED;
4272 }
4273
4274 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4275 {
4276 if (rp->mbox) {
4277 np->ops->free_coherent(np->device,
4278 sizeof(struct rxdma_mailbox),
4279 rp->mbox, rp->mbox_dma);
4280 rp->mbox = NULL;
4281 }
4282 if (rp->rcr) {
4283 np->ops->free_coherent(np->device,
4284 MAX_RCR_RING_SIZE * sizeof(__le64),
4285 rp->rcr, rp->rcr_dma);
4286 rp->rcr = NULL;
4287 rp->rcr_table_size = 0;
4288 rp->rcr_index = 0;
4289 }
4290 if (rp->rbr) {
4291 niu_rbr_free(np, rp);
4292
4293 np->ops->free_coherent(np->device,
4294 MAX_RBR_RING_SIZE * sizeof(__le32),
4295 rp->rbr, rp->rbr_dma);
4296 rp->rbr = NULL;
4297 rp->rbr_table_size = 0;
4298 rp->rbr_index = 0;
4299 }
4300 kfree(rp->rxhash);
4301 rp->rxhash = NULL;
4302 }
4303
4304 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4305 {
4306 if (rp->mbox) {
4307 np->ops->free_coherent(np->device,
4308 sizeof(struct txdma_mailbox),
4309 rp->mbox, rp->mbox_dma);
4310 rp->mbox = NULL;
4311 }
4312 if (rp->descr) {
4313 int i;
4314
4315 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4316 if (rp->tx_buffs[i].skb)
4317 (void) release_tx_packet(np, rp, i);
4318 }
4319
4320 np->ops->free_coherent(np->device,
4321 MAX_TX_RING_SIZE * sizeof(__le64),
4322 rp->descr, rp->descr_dma);
4323 rp->descr = NULL;
4324 rp->pending = 0;
4325 rp->prod = 0;
4326 rp->cons = 0;
4327 rp->wrap_bit = 0;
4328 }
4329 }
4330
4331 static void niu_free_channels(struct niu *np)
4332 {
4333 int i;
4334
4335 if (np->rx_rings) {
4336 for (i = 0; i < np->num_rx_rings; i++) {
4337 struct rx_ring_info *rp = &np->rx_rings[i];
4338
4339 niu_free_rx_ring_info(np, rp);
4340 }
4341 kfree(np->rx_rings);
4342 np->rx_rings = NULL;
4343 np->num_rx_rings = 0;
4344 }
4345
4346 if (np->tx_rings) {
4347 for (i = 0; i < np->num_tx_rings; i++) {
4348 struct tx_ring_info *rp = &np->tx_rings[i];
4349
4350 niu_free_tx_ring_info(np, rp);
4351 }
4352 kfree(np->tx_rings);
4353 np->tx_rings = NULL;
4354 np->num_tx_rings = 0;
4355 }
4356 }
4357
4358 static int niu_alloc_rx_ring_info(struct niu *np,
4359 struct rx_ring_info *rp)
4360 {
4361 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4362
4363 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4364 GFP_KERNEL);
4365 if (!rp->rxhash)
4366 return -ENOMEM;
4367
4368 rp->mbox = np->ops->alloc_coherent(np->device,
4369 sizeof(struct rxdma_mailbox),
4370 &rp->mbox_dma, GFP_KERNEL);
4371 if (!rp->mbox)
4372 return -ENOMEM;
4373 if ((unsigned long)rp->mbox & (64UL - 1)) {
4374 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4375 rp->mbox);
4376 return -EINVAL;
4377 }
4378
4379 rp->rcr = np->ops->alloc_coherent(np->device,
4380 MAX_RCR_RING_SIZE * sizeof(__le64),
4381 &rp->rcr_dma, GFP_KERNEL);
4382 if (!rp->rcr)
4383 return -ENOMEM;
4384 if ((unsigned long)rp->rcr & (64UL - 1)) {
4385 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4386 rp->rcr);
4387 return -EINVAL;
4388 }
4389 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4390 rp->rcr_index = 0;
4391
4392 rp->rbr = np->ops->alloc_coherent(np->device,
4393 MAX_RBR_RING_SIZE * sizeof(__le32),
4394 &rp->rbr_dma, GFP_KERNEL);
4395 if (!rp->rbr)
4396 return -ENOMEM;
4397 if ((unsigned long)rp->rbr & (64UL - 1)) {
4398 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4399 rp->rbr);
4400 return -EINVAL;
4401 }
4402 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4403 rp->rbr_index = 0;
4404 rp->rbr_pending = 0;
4405
4406 return 0;
4407 }
4408
4409 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4410 {
4411 int mtu = np->dev->mtu;
4412
4413 /* These values are recommended by the HW designers for fair
4414 * utilization of DRR amongst the rings.
4415 */
4416 rp->max_burst = mtu + 32;
4417 if (rp->max_burst > 4096)
4418 rp->max_burst = 4096;
4419 }
4420
4421 static int niu_alloc_tx_ring_info(struct niu *np,
4422 struct tx_ring_info *rp)
4423 {
4424 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4425
4426 rp->mbox = np->ops->alloc_coherent(np->device,
4427 sizeof(struct txdma_mailbox),
4428 &rp->mbox_dma, GFP_KERNEL);
4429 if (!rp->mbox)
4430 return -ENOMEM;
4431 if ((unsigned long)rp->mbox & (64UL - 1)) {
4432 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4433 rp->mbox);
4434 return -EINVAL;
4435 }
4436
4437 rp->descr = np->ops->alloc_coherent(np->device,
4438 MAX_TX_RING_SIZE * sizeof(__le64),
4439 &rp->descr_dma, GFP_KERNEL);
4440 if (!rp->descr)
4441 return -ENOMEM;
4442 if ((unsigned long)rp->descr & (64UL - 1)) {
4443 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4444 rp->descr);
4445 return -EINVAL;
4446 }
4447
4448 rp->pending = MAX_TX_RING_SIZE;
4449 rp->prod = 0;
4450 rp->cons = 0;
4451 rp->wrap_bit = 0;
4452
4453 /* XXX make these configurable... XXX */
4454 rp->mark_freq = rp->pending / 4;
4455
4456 niu_set_max_burst(np, rp);
4457
4458 return 0;
4459 }
4460
4461 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4462 {
4463 u16 bss;
4464
4465 bss = min(PAGE_SHIFT, 15);
4466
4467 rp->rbr_block_size = 1 << bss;
4468 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4469
4470 rp->rbr_sizes[0] = 256;
4471 rp->rbr_sizes[1] = 1024;
4472 if (np->dev->mtu > ETH_DATA_LEN) {
4473 switch (PAGE_SIZE) {
4474 case 4 * 1024:
4475 rp->rbr_sizes[2] = 4096;
4476 break;
4477
4478 default:
4479 rp->rbr_sizes[2] = 8192;
4480 break;
4481 }
4482 } else {
4483 rp->rbr_sizes[2] = 2048;
4484 }
4485 rp->rbr_sizes[3] = rp->rbr_block_size;
4486 }
4487
4488 static int niu_alloc_channels(struct niu *np)
4489 {
4490 struct niu_parent *parent = np->parent;
4491 int first_rx_channel, first_tx_channel;
4492 int i, port, err;
4493
4494 port = np->port;
4495 first_rx_channel = first_tx_channel = 0;
4496 for (i = 0; i < port; i++) {
4497 first_rx_channel += parent->rxchan_per_port[i];
4498 first_tx_channel += parent->txchan_per_port[i];
4499 }
4500
4501 np->num_rx_rings = parent->rxchan_per_port[port];
4502 np->num_tx_rings = parent->txchan_per_port[port];
4503
4504 np->dev->real_num_tx_queues = np->num_tx_rings;
4505
4506 np->rx_rings = kcalloc(np->num_rx_rings, sizeof(struct rx_ring_info),
4507 GFP_KERNEL);
4508 err = -ENOMEM;
4509 if (!np->rx_rings)
4510 goto out_err;
4511
4512 for (i = 0; i < np->num_rx_rings; i++) {
4513 struct rx_ring_info *rp = &np->rx_rings[i];
4514
4515 rp->np = np;
4516 rp->rx_channel = first_rx_channel + i;
4517
4518 err = niu_alloc_rx_ring_info(np, rp);
4519 if (err)
4520 goto out_err;
4521
4522 niu_size_rbr(np, rp);
4523
4524 /* XXX better defaults, configurable, etc... XXX */
4525 rp->nonsyn_window = 64;
4526 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4527 rp->syn_window = 64;
4528 rp->syn_threshold = rp->rcr_table_size - 64;
4529 rp->rcr_pkt_threshold = 16;
4530 rp->rcr_timeout = 8;
4531 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4532 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4533 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4534
4535 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4536 if (err)
4537 return err;
4538 }
4539
4540 np->tx_rings = kcalloc(np->num_tx_rings, sizeof(struct tx_ring_info),
4541 GFP_KERNEL);
4542 err = -ENOMEM;
4543 if (!np->tx_rings)
4544 goto out_err;
4545
4546 for (i = 0; i < np->num_tx_rings; i++) {
4547 struct tx_ring_info *rp = &np->tx_rings[i];
4548
4549 rp->np = np;
4550 rp->tx_channel = first_tx_channel + i;
4551
4552 err = niu_alloc_tx_ring_info(np, rp);
4553 if (err)
4554 goto out_err;
4555 }
4556
4557 return 0;
4558
4559 out_err:
4560 niu_free_channels(np);
4561 return err;
4562 }
4563
4564 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4565 {
4566 int limit = 1000;
4567
4568 while (--limit > 0) {
4569 u64 val = nr64(TX_CS(channel));
4570 if (val & TX_CS_SNG_STATE)
4571 return 0;
4572 }
4573 return -ENODEV;
4574 }
4575
4576 static int niu_tx_channel_stop(struct niu *np, int channel)
4577 {
4578 u64 val = nr64(TX_CS(channel));
4579
4580 val |= TX_CS_STOP_N_GO;
4581 nw64(TX_CS(channel), val);
4582
4583 return niu_tx_cs_sng_poll(np, channel);
4584 }
4585
4586 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4587 {
4588 int limit = 1000;
4589
4590 while (--limit > 0) {
4591 u64 val = nr64(TX_CS(channel));
4592 if (!(val & TX_CS_RST))
4593 return 0;
4594 }
4595 return -ENODEV;
4596 }
4597
4598 static int niu_tx_channel_reset(struct niu *np, int channel)
4599 {
4600 u64 val = nr64(TX_CS(channel));
4601 int err;
4602
4603 val |= TX_CS_RST;
4604 nw64(TX_CS(channel), val);
4605
4606 err = niu_tx_cs_reset_poll(np, channel);
4607 if (!err)
4608 nw64(TX_RING_KICK(channel), 0);
4609
4610 return err;
4611 }
4612
4613 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4614 {
4615 u64 val;
4616
4617 nw64(TX_LOG_MASK1(channel), 0);
4618 nw64(TX_LOG_VAL1(channel), 0);
4619 nw64(TX_LOG_MASK2(channel), 0);
4620 nw64(TX_LOG_VAL2(channel), 0);
4621 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4622 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4623 nw64(TX_LOG_PAGE_HDL(channel), 0);
4624
4625 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4626 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4627 nw64(TX_LOG_PAGE_VLD(channel), val);
4628
4629 /* XXX TXDMA 32bit mode? XXX */
4630
4631 return 0;
4632 }
4633
4634 static void niu_txc_enable_port(struct niu *np, int on)
4635 {
4636 unsigned long flags;
4637 u64 val, mask;
4638
4639 niu_lock_parent(np, flags);
4640 val = nr64(TXC_CONTROL);
4641 mask = (u64)1 << np->port;
4642 if (on) {
4643 val |= TXC_CONTROL_ENABLE | mask;
4644 } else {
4645 val &= ~mask;
4646 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4647 val &= ~TXC_CONTROL_ENABLE;
4648 }
4649 nw64(TXC_CONTROL, val);
4650 niu_unlock_parent(np, flags);
4651 }
4652
4653 static void niu_txc_set_imask(struct niu *np, u64 imask)
4654 {
4655 unsigned long flags;
4656 u64 val;
4657
4658 niu_lock_parent(np, flags);
4659 val = nr64(TXC_INT_MASK);
4660 val &= ~TXC_INT_MASK_VAL(np->port);
4661 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4662 niu_unlock_parent(np, flags);
4663 }
4664
4665 static void niu_txc_port_dma_enable(struct niu *np, int on)
4666 {
4667 u64 val = 0;
4668
4669 if (on) {
4670 int i;
4671
4672 for (i = 0; i < np->num_tx_rings; i++)
4673 val |= (1 << np->tx_rings[i].tx_channel);
4674 }
4675 nw64(TXC_PORT_DMA(np->port), val);
4676 }
4677
4678 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4679 {
4680 int err, channel = rp->tx_channel;
4681 u64 val, ring_len;
4682
4683 err = niu_tx_channel_stop(np, channel);
4684 if (err)
4685 return err;
4686
4687 err = niu_tx_channel_reset(np, channel);
4688 if (err)
4689 return err;
4690
4691 err = niu_tx_channel_lpage_init(np, channel);
4692 if (err)
4693 return err;
4694
4695 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4696 nw64(TX_ENT_MSK(channel), 0);
4697
4698 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4699 TX_RNG_CFIG_STADDR)) {
4700 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4701 channel, (unsigned long long)rp->descr_dma);
4702 return -EINVAL;
4703 }
4704
4705 /* The length field in TX_RNG_CFIG is measured in 64-byte
4706 * blocks. rp->pending is the number of TX descriptors in
4707 * our ring, 8 bytes each, thus we divide by 8 bytes more
4708 * to get the proper value the chip wants.
4709 */
4710 ring_len = (rp->pending / 8);
4711
4712 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4713 rp->descr_dma);
4714 nw64(TX_RNG_CFIG(channel), val);
4715
4716 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4717 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4718 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4719 channel, (unsigned long long)rp->mbox_dma);
4720 return -EINVAL;
4721 }
4722 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4723 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4724
4725 nw64(TX_CS(channel), 0);
4726
4727 rp->last_pkt_cnt = 0;
4728
4729 return 0;
4730 }
4731
4732 static void niu_init_rdc_groups(struct niu *np)
4733 {
4734 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4735 int i, first_table_num = tp->first_table_num;
4736
4737 for (i = 0; i < tp->num_tables; i++) {
4738 struct rdc_table *tbl = &tp->tables[i];
4739 int this_table = first_table_num + i;
4740 int slot;
4741
4742 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4743 nw64(RDC_TBL(this_table, slot),
4744 tbl->rxdma_channel[slot]);
4745 }
4746
4747 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4748 }
4749
4750 static void niu_init_drr_weight(struct niu *np)
4751 {
4752 int type = phy_decode(np->parent->port_phy, np->port);
4753 u64 val;
4754
4755 switch (type) {
4756 case PORT_TYPE_10G:
4757 val = PT_DRR_WEIGHT_DEFAULT_10G;
4758 break;
4759
4760 case PORT_TYPE_1G:
4761 default:
4762 val = PT_DRR_WEIGHT_DEFAULT_1G;
4763 break;
4764 }
4765 nw64(PT_DRR_WT(np->port), val);
4766 }
4767
4768 static int niu_init_hostinfo(struct niu *np)
4769 {
4770 struct niu_parent *parent = np->parent;
4771 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4772 int i, err, num_alt = niu_num_alt_addr(np);
4773 int first_rdc_table = tp->first_table_num;
4774
4775 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4776 if (err)
4777 return err;
4778
4779 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4780 if (err)
4781 return err;
4782
4783 for (i = 0; i < num_alt; i++) {
4784 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4785 if (err)
4786 return err;
4787 }
4788
4789 return 0;
4790 }
4791
4792 static int niu_rx_channel_reset(struct niu *np, int channel)
4793 {
4794 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4795 RXDMA_CFIG1_RST, 1000, 10,
4796 "RXDMA_CFIG1");
4797 }
4798
4799 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4800 {
4801 u64 val;
4802
4803 nw64(RX_LOG_MASK1(channel), 0);
4804 nw64(RX_LOG_VAL1(channel), 0);
4805 nw64(RX_LOG_MASK2(channel), 0);
4806 nw64(RX_LOG_VAL2(channel), 0);
4807 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4808 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4809 nw64(RX_LOG_PAGE_HDL(channel), 0);
4810
4811 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4812 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4813 nw64(RX_LOG_PAGE_VLD(channel), val);
4814
4815 return 0;
4816 }
4817
4818 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4819 {
4820 u64 val;
4821
4822 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4823 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4824 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4825 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4826 nw64(RDC_RED_PARA(rp->rx_channel), val);
4827 }
4828
4829 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4830 {
4831 u64 val = 0;
4832
4833 *ret = 0;
4834 switch (rp->rbr_block_size) {
4835 case 4 * 1024:
4836 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4837 break;
4838 case 8 * 1024:
4839 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4840 break;
4841 case 16 * 1024:
4842 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4843 break;
4844 case 32 * 1024:
4845 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4846 break;
4847 default:
4848 return -EINVAL;
4849 }
4850 val |= RBR_CFIG_B_VLD2;
4851 switch (rp->rbr_sizes[2]) {
4852 case 2 * 1024:
4853 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4854 break;
4855 case 4 * 1024:
4856 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4857 break;
4858 case 8 * 1024:
4859 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4860 break;
4861 case 16 * 1024:
4862 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4863 break;
4864
4865 default:
4866 return -EINVAL;
4867 }
4868 val |= RBR_CFIG_B_VLD1;
4869 switch (rp->rbr_sizes[1]) {
4870 case 1 * 1024:
4871 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4872 break;
4873 case 2 * 1024:
4874 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4875 break;
4876 case 4 * 1024:
4877 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4878 break;
4879 case 8 * 1024:
4880 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4881 break;
4882
4883 default:
4884 return -EINVAL;
4885 }
4886 val |= RBR_CFIG_B_VLD0;
4887 switch (rp->rbr_sizes[0]) {
4888 case 256:
4889 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4890 break;
4891 case 512:
4892 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4893 break;
4894 case 1 * 1024:
4895 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4896 break;
4897 case 2 * 1024:
4898 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4899 break;
4900
4901 default:
4902 return -EINVAL;
4903 }
4904
4905 *ret = val;
4906 return 0;
4907 }
4908
4909 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4910 {
4911 u64 val = nr64(RXDMA_CFIG1(channel));
4912 int limit;
4913
4914 if (on)
4915 val |= RXDMA_CFIG1_EN;
4916 else
4917 val &= ~RXDMA_CFIG1_EN;
4918 nw64(RXDMA_CFIG1(channel), val);
4919
4920 limit = 1000;
4921 while (--limit > 0) {
4922 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4923 break;
4924 udelay(10);
4925 }
4926 if (limit <= 0)
4927 return -ENODEV;
4928 return 0;
4929 }
4930
4931 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4932 {
4933 int err, channel = rp->rx_channel;
4934 u64 val;
4935
4936 err = niu_rx_channel_reset(np, channel);
4937 if (err)
4938 return err;
4939
4940 err = niu_rx_channel_lpage_init(np, channel);
4941 if (err)
4942 return err;
4943
4944 niu_rx_channel_wred_init(np, rp);
4945
4946 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4947 nw64(RX_DMA_CTL_STAT(channel),
4948 (RX_DMA_CTL_STAT_MEX |
4949 RX_DMA_CTL_STAT_RCRTHRES |
4950 RX_DMA_CTL_STAT_RCRTO |
4951 RX_DMA_CTL_STAT_RBR_EMPTY));
4952 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4953 nw64(RXDMA_CFIG2(channel),
4954 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4955 RXDMA_CFIG2_FULL_HDR));
4956 nw64(RBR_CFIG_A(channel),
4957 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4958 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4959 err = niu_compute_rbr_cfig_b(rp, &val);
4960 if (err)
4961 return err;
4962 nw64(RBR_CFIG_B(channel), val);
4963 nw64(RCRCFIG_A(channel),
4964 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4965 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4966 nw64(RCRCFIG_B(channel),
4967 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4968 RCRCFIG_B_ENTOUT |
4969 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4970
4971 err = niu_enable_rx_channel(np, channel, 1);
4972 if (err)
4973 return err;
4974
4975 nw64(RBR_KICK(channel), rp->rbr_index);
4976
4977 val = nr64(RX_DMA_CTL_STAT(channel));
4978 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4979 nw64(RX_DMA_CTL_STAT(channel), val);
4980
4981 return 0;
4982 }
4983
4984 static int niu_init_rx_channels(struct niu *np)
4985 {
4986 unsigned long flags;
4987 u64 seed = jiffies_64;
4988 int err, i;
4989
4990 niu_lock_parent(np, flags);
4991 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4992 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4993 niu_unlock_parent(np, flags);
4994
4995 /* XXX RXDMA 32bit mode? XXX */
4996
4997 niu_init_rdc_groups(np);
4998 niu_init_drr_weight(np);
4999
5000 err = niu_init_hostinfo(np);
5001 if (err)
5002 return err;
5003
5004 for (i = 0; i < np->num_rx_rings; i++) {
5005 struct rx_ring_info *rp = &np->rx_rings[i];
5006
5007 err = niu_init_one_rx_channel(np, rp);
5008 if (err)
5009 return err;
5010 }
5011
5012 return 0;
5013 }
5014
5015 static int niu_set_ip_frag_rule(struct niu *np)
5016 {
5017 struct niu_parent *parent = np->parent;
5018 struct niu_classifier *cp = &np->clas;
5019 struct niu_tcam_entry *tp;
5020 int index, err;
5021
5022 index = cp->tcam_top;
5023 tp = &parent->tcam[index];
5024
5025 /* Note that the noport bit is the same in both ipv4 and
5026 * ipv6 format TCAM entries.
5027 */
5028 memset(tp, 0, sizeof(*tp));
5029 tp->key[1] = TCAM_V4KEY1_NOPORT;
5030 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5031 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5032 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5033 err = tcam_write(np, index, tp->key, tp->key_mask);
5034 if (err)
5035 return err;
5036 err = tcam_assoc_write(np, index, tp->assoc_data);
5037 if (err)
5038 return err;
5039 tp->valid = 1;
5040 cp->tcam_valid_entries++;
5041
5042 return 0;
5043 }
5044
5045 static int niu_init_classifier_hw(struct niu *np)
5046 {
5047 struct niu_parent *parent = np->parent;
5048 struct niu_classifier *cp = &np->clas;
5049 int i, err;
5050
5051 nw64(H1POLY, cp->h1_init);
5052 nw64(H2POLY, cp->h2_init);
5053
5054 err = niu_init_hostinfo(np);
5055 if (err)
5056 return err;
5057
5058 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5059 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5060
5061 vlan_tbl_write(np, i, np->port,
5062 vp->vlan_pref, vp->rdc_num);
5063 }
5064
5065 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5066 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5067
5068 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5069 ap->rdc_num, ap->mac_pref);
5070 if (err)
5071 return err;
5072 }
5073
5074 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5075 int index = i - CLASS_CODE_USER_PROG1;
5076
5077 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5078 if (err)
5079 return err;
5080 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5081 if (err)
5082 return err;
5083 }
5084
5085 err = niu_set_ip_frag_rule(np);
5086 if (err)
5087 return err;
5088
5089 tcam_enable(np, 1);
5090
5091 return 0;
5092 }
5093
5094 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5095 {
5096 nw64(ZCP_RAM_DATA0, data[0]);
5097 nw64(ZCP_RAM_DATA1, data[1]);
5098 nw64(ZCP_RAM_DATA2, data[2]);
5099 nw64(ZCP_RAM_DATA3, data[3]);
5100 nw64(ZCP_RAM_DATA4, data[4]);
5101 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5102 nw64(ZCP_RAM_ACC,
5103 (ZCP_RAM_ACC_WRITE |
5104 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5105 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5106
5107 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5108 1000, 100);
5109 }
5110
5111 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5112 {
5113 int err;
5114
5115 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5116 1000, 100);
5117 if (err) {
5118 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5119 (unsigned long long)nr64(ZCP_RAM_ACC));
5120 return err;
5121 }
5122
5123 nw64(ZCP_RAM_ACC,
5124 (ZCP_RAM_ACC_READ |
5125 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5126 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5127
5128 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5129 1000, 100);
5130 if (err) {
5131 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5132 (unsigned long long)nr64(ZCP_RAM_ACC));
5133 return err;
5134 }
5135
5136 data[0] = nr64(ZCP_RAM_DATA0);
5137 data[1] = nr64(ZCP_RAM_DATA1);
5138 data[2] = nr64(ZCP_RAM_DATA2);
5139 data[3] = nr64(ZCP_RAM_DATA3);
5140 data[4] = nr64(ZCP_RAM_DATA4);
5141
5142 return 0;
5143 }
5144
5145 static void niu_zcp_cfifo_reset(struct niu *np)
5146 {
5147 u64 val = nr64(RESET_CFIFO);
5148
5149 val |= RESET_CFIFO_RST(np->port);
5150 nw64(RESET_CFIFO, val);
5151 udelay(10);
5152
5153 val &= ~RESET_CFIFO_RST(np->port);
5154 nw64(RESET_CFIFO, val);
5155 }
5156
5157 static int niu_init_zcp(struct niu *np)
5158 {
5159 u64 data[5], rbuf[5];
5160 int i, max, err;
5161
5162 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5163 if (np->port == 0 || np->port == 1)
5164 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5165 else
5166 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5167 } else
5168 max = NIU_CFIFO_ENTRIES;
5169
5170 data[0] = 0;
5171 data[1] = 0;
5172 data[2] = 0;
5173 data[3] = 0;
5174 data[4] = 0;
5175
5176 for (i = 0; i < max; i++) {
5177 err = niu_zcp_write(np, i, data);
5178 if (err)
5179 return err;
5180 err = niu_zcp_read(np, i, rbuf);
5181 if (err)
5182 return err;
5183 }
5184
5185 niu_zcp_cfifo_reset(np);
5186 nw64(CFIFO_ECC(np->port), 0);
5187 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5188 (void) nr64(ZCP_INT_STAT);
5189 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5190
5191 return 0;
5192 }
5193
5194 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5195 {
5196 u64 val = nr64_ipp(IPP_CFIG);
5197
5198 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5199 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5200 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5201 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5202 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5203 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5204 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5205 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5206 }
5207
5208 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5209 {
5210 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5211 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5212 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5213 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5214 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5215 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5216 }
5217
5218 static int niu_ipp_reset(struct niu *np)
5219 {
5220 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5221 1000, 100, "IPP_CFIG");
5222 }
5223
5224 static int niu_init_ipp(struct niu *np)
5225 {
5226 u64 data[5], rbuf[5], val;
5227 int i, max, err;
5228
5229 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5230 if (np->port == 0 || np->port == 1)
5231 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5232 else
5233 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5234 } else
5235 max = NIU_DFIFO_ENTRIES;
5236
5237 data[0] = 0;
5238 data[1] = 0;
5239 data[2] = 0;
5240 data[3] = 0;
5241 data[4] = 0;
5242
5243 for (i = 0; i < max; i++) {
5244 niu_ipp_write(np, i, data);
5245 niu_ipp_read(np, i, rbuf);
5246 }
5247
5248 (void) nr64_ipp(IPP_INT_STAT);
5249 (void) nr64_ipp(IPP_INT_STAT);
5250
5251 err = niu_ipp_reset(np);
5252 if (err)
5253 return err;
5254
5255 (void) nr64_ipp(IPP_PKT_DIS);
5256 (void) nr64_ipp(IPP_BAD_CS_CNT);
5257 (void) nr64_ipp(IPP_ECC);
5258
5259 (void) nr64_ipp(IPP_INT_STAT);
5260
5261 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5262
5263 val = nr64_ipp(IPP_CFIG);
5264 val &= ~IPP_CFIG_IP_MAX_PKT;
5265 val |= (IPP_CFIG_IPP_ENABLE |
5266 IPP_CFIG_DFIFO_ECC_EN |
5267 IPP_CFIG_DROP_BAD_CRC |
5268 IPP_CFIG_CKSUM_EN |
5269 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5270 nw64_ipp(IPP_CFIG, val);
5271
5272 return 0;
5273 }
5274
5275 static void niu_handle_led(struct niu *np, int status)
5276 {
5277 u64 val;
5278 val = nr64_mac(XMAC_CONFIG);
5279
5280 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5281 (np->flags & NIU_FLAGS_FIBER) != 0) {
5282 if (status) {
5283 val |= XMAC_CONFIG_LED_POLARITY;
5284 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5285 } else {
5286 val |= XMAC_CONFIG_FORCE_LED_ON;
5287 val &= ~XMAC_CONFIG_LED_POLARITY;
5288 }
5289 }
5290
5291 nw64_mac(XMAC_CONFIG, val);
5292 }
5293
5294 static void niu_init_xif_xmac(struct niu *np)
5295 {
5296 struct niu_link_config *lp = &np->link_config;
5297 u64 val;
5298
5299 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5300 val = nr64(MIF_CONFIG);
5301 val |= MIF_CONFIG_ATCA_GE;
5302 nw64(MIF_CONFIG, val);
5303 }
5304
5305 val = nr64_mac(XMAC_CONFIG);
5306 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5307
5308 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5309
5310 if (lp->loopback_mode == LOOPBACK_MAC) {
5311 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5312 val |= XMAC_CONFIG_LOOPBACK;
5313 } else {
5314 val &= ~XMAC_CONFIG_LOOPBACK;
5315 }
5316
5317 if (np->flags & NIU_FLAGS_10G) {
5318 val &= ~XMAC_CONFIG_LFS_DISABLE;
5319 } else {
5320 val |= XMAC_CONFIG_LFS_DISABLE;
5321 if (!(np->flags & NIU_FLAGS_FIBER) &&
5322 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5323 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5324 else
5325 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5326 }
5327
5328 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5329
5330 if (lp->active_speed == SPEED_100)
5331 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5332 else
5333 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5334
5335 nw64_mac(XMAC_CONFIG, val);
5336
5337 val = nr64_mac(XMAC_CONFIG);
5338 val &= ~XMAC_CONFIG_MODE_MASK;
5339 if (np->flags & NIU_FLAGS_10G) {
5340 val |= XMAC_CONFIG_MODE_XGMII;
5341 } else {
5342 if (lp->active_speed == SPEED_1000)
5343 val |= XMAC_CONFIG_MODE_GMII;
5344 else
5345 val |= XMAC_CONFIG_MODE_MII;
5346 }
5347
5348 nw64_mac(XMAC_CONFIG, val);
5349 }
5350
5351 static void niu_init_xif_bmac(struct niu *np)
5352 {
5353 struct niu_link_config *lp = &np->link_config;
5354 u64 val;
5355
5356 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5357
5358 if (lp->loopback_mode == LOOPBACK_MAC)
5359 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5360 else
5361 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5362
5363 if (lp->active_speed == SPEED_1000)
5364 val |= BMAC_XIF_CONFIG_GMII_MODE;
5365 else
5366 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5367
5368 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5369 BMAC_XIF_CONFIG_LED_POLARITY);
5370
5371 if (!(np->flags & NIU_FLAGS_10G) &&
5372 !(np->flags & NIU_FLAGS_FIBER) &&
5373 lp->active_speed == SPEED_100)
5374 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5375 else
5376 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5377
5378 nw64_mac(BMAC_XIF_CONFIG, val);
5379 }
5380
5381 static void niu_init_xif(struct niu *np)
5382 {
5383 if (np->flags & NIU_FLAGS_XMAC)
5384 niu_init_xif_xmac(np);
5385 else
5386 niu_init_xif_bmac(np);
5387 }
5388
5389 static void niu_pcs_mii_reset(struct niu *np)
5390 {
5391 int limit = 1000;
5392 u64 val = nr64_pcs(PCS_MII_CTL);
5393 val |= PCS_MII_CTL_RST;
5394 nw64_pcs(PCS_MII_CTL, val);
5395 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5396 udelay(100);
5397 val = nr64_pcs(PCS_MII_CTL);
5398 }
5399 }
5400
5401 static void niu_xpcs_reset(struct niu *np)
5402 {
5403 int limit = 1000;
5404 u64 val = nr64_xpcs(XPCS_CONTROL1);
5405 val |= XPCS_CONTROL1_RESET;
5406 nw64_xpcs(XPCS_CONTROL1, val);
5407 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5408 udelay(100);
5409 val = nr64_xpcs(XPCS_CONTROL1);
5410 }
5411 }
5412
5413 static int niu_init_pcs(struct niu *np)
5414 {
5415 struct niu_link_config *lp = &np->link_config;
5416 u64 val;
5417
5418 switch (np->flags & (NIU_FLAGS_10G |
5419 NIU_FLAGS_FIBER |
5420 NIU_FLAGS_XCVR_SERDES)) {
5421 case NIU_FLAGS_FIBER:
5422 /* 1G fiber */
5423 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5424 nw64_pcs(PCS_DPATH_MODE, 0);
5425 niu_pcs_mii_reset(np);
5426 break;
5427
5428 case NIU_FLAGS_10G:
5429 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5430 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5431 /* 10G SERDES */
5432 if (!(np->flags & NIU_FLAGS_XMAC))
5433 return -EINVAL;
5434
5435 /* 10G copper or fiber */
5436 val = nr64_mac(XMAC_CONFIG);
5437 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5438 nw64_mac(XMAC_CONFIG, val);
5439
5440 niu_xpcs_reset(np);
5441
5442 val = nr64_xpcs(XPCS_CONTROL1);
5443 if (lp->loopback_mode == LOOPBACK_PHY)
5444 val |= XPCS_CONTROL1_LOOPBACK;
5445 else
5446 val &= ~XPCS_CONTROL1_LOOPBACK;
5447 nw64_xpcs(XPCS_CONTROL1, val);
5448
5449 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5450 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5452 break;
5453
5454
5455 case NIU_FLAGS_XCVR_SERDES:
5456 /* 1G SERDES */
5457 niu_pcs_mii_reset(np);
5458 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5459 nw64_pcs(PCS_DPATH_MODE, 0);
5460 break;
5461
5462 case 0:
5463 /* 1G copper */
5464 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5465 /* 1G RGMII FIBER */
5466 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5467 niu_pcs_mii_reset(np);
5468 break;
5469
5470 default:
5471 return -EINVAL;
5472 }
5473
5474 return 0;
5475 }
5476
5477 static int niu_reset_tx_xmac(struct niu *np)
5478 {
5479 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5480 (XTXMAC_SW_RST_REG_RS |
5481 XTXMAC_SW_RST_SOFT_RST),
5482 1000, 100, "XTXMAC_SW_RST");
5483 }
5484
5485 static int niu_reset_tx_bmac(struct niu *np)
5486 {
5487 int limit;
5488
5489 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5490 limit = 1000;
5491 while (--limit >= 0) {
5492 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5493 break;
5494 udelay(100);
5495 }
5496 if (limit < 0) {
5497 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5498 np->port,
5499 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5500 return -ENODEV;
5501 }
5502
5503 return 0;
5504 }
5505
5506 static int niu_reset_tx_mac(struct niu *np)
5507 {
5508 if (np->flags & NIU_FLAGS_XMAC)
5509 return niu_reset_tx_xmac(np);
5510 else
5511 return niu_reset_tx_bmac(np);
5512 }
5513
5514 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5515 {
5516 u64 val;
5517
5518 val = nr64_mac(XMAC_MIN);
5519 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5520 XMAC_MIN_RX_MIN_PKT_SIZE);
5521 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5522 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5523 nw64_mac(XMAC_MIN, val);
5524
5525 nw64_mac(XMAC_MAX, max);
5526
5527 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5528
5529 val = nr64_mac(XMAC_IPG);
5530 if (np->flags & NIU_FLAGS_10G) {
5531 val &= ~XMAC_IPG_IPG_XGMII;
5532 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5533 } else {
5534 val &= ~XMAC_IPG_IPG_MII_GMII;
5535 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5536 }
5537 nw64_mac(XMAC_IPG, val);
5538
5539 val = nr64_mac(XMAC_CONFIG);
5540 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5541 XMAC_CONFIG_STRETCH_MODE |
5542 XMAC_CONFIG_VAR_MIN_IPG_EN |
5543 XMAC_CONFIG_TX_ENABLE);
5544 nw64_mac(XMAC_CONFIG, val);
5545
5546 nw64_mac(TXMAC_FRM_CNT, 0);
5547 nw64_mac(TXMAC_BYTE_CNT, 0);
5548 }
5549
5550 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5551 {
5552 u64 val;
5553
5554 nw64_mac(BMAC_MIN_FRAME, min);
5555 nw64_mac(BMAC_MAX_FRAME, max);
5556
5557 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5558 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5559 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5560
5561 val = nr64_mac(BTXMAC_CONFIG);
5562 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5563 BTXMAC_CONFIG_ENABLE);
5564 nw64_mac(BTXMAC_CONFIG, val);
5565 }
5566
5567 static void niu_init_tx_mac(struct niu *np)
5568 {
5569 u64 min, max;
5570
5571 min = 64;
5572 if (np->dev->mtu > ETH_DATA_LEN)
5573 max = 9216;
5574 else
5575 max = 1522;
5576
5577 /* The XMAC_MIN register only accepts values for TX min which
5578 * have the low 3 bits cleared.
5579 */
5580 BUG_ON(min & 0x7);
5581
5582 if (np->flags & NIU_FLAGS_XMAC)
5583 niu_init_tx_xmac(np, min, max);
5584 else
5585 niu_init_tx_bmac(np, min, max);
5586 }
5587
5588 static int niu_reset_rx_xmac(struct niu *np)
5589 {
5590 int limit;
5591
5592 nw64_mac(XRXMAC_SW_RST,
5593 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5594 limit = 1000;
5595 while (--limit >= 0) {
5596 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5597 XRXMAC_SW_RST_SOFT_RST)))
5598 break;
5599 udelay(100);
5600 }
5601 if (limit < 0) {
5602 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5603 np->port,
5604 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5605 return -ENODEV;
5606 }
5607
5608 return 0;
5609 }
5610
5611 static int niu_reset_rx_bmac(struct niu *np)
5612 {
5613 int limit;
5614
5615 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5616 limit = 1000;
5617 while (--limit >= 0) {
5618 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5619 break;
5620 udelay(100);
5621 }
5622 if (limit < 0) {
5623 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5624 np->port,
5625 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5626 return -ENODEV;
5627 }
5628
5629 return 0;
5630 }
5631
5632 static int niu_reset_rx_mac(struct niu *np)
5633 {
5634 if (np->flags & NIU_FLAGS_XMAC)
5635 return niu_reset_rx_xmac(np);
5636 else
5637 return niu_reset_rx_bmac(np);
5638 }
5639
5640 static void niu_init_rx_xmac(struct niu *np)
5641 {
5642 struct niu_parent *parent = np->parent;
5643 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5644 int first_rdc_table = tp->first_table_num;
5645 unsigned long i;
5646 u64 val;
5647
5648 nw64_mac(XMAC_ADD_FILT0, 0);
5649 nw64_mac(XMAC_ADD_FILT1, 0);
5650 nw64_mac(XMAC_ADD_FILT2, 0);
5651 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5652 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5653 for (i = 0; i < MAC_NUM_HASH; i++)
5654 nw64_mac(XMAC_HASH_TBL(i), 0);
5655 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5656 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5657 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5658
5659 val = nr64_mac(XMAC_CONFIG);
5660 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5661 XMAC_CONFIG_PROMISCUOUS |
5662 XMAC_CONFIG_PROMISC_GROUP |
5663 XMAC_CONFIG_ERR_CHK_DIS |
5664 XMAC_CONFIG_RX_CRC_CHK_DIS |
5665 XMAC_CONFIG_RESERVED_MULTICAST |
5666 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5667 XMAC_CONFIG_ADDR_FILTER_EN |
5668 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5669 XMAC_CONFIG_STRIP_CRC |
5670 XMAC_CONFIG_PASS_FLOW_CTRL |
5671 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5672 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5673 nw64_mac(XMAC_CONFIG, val);
5674
5675 nw64_mac(RXMAC_BT_CNT, 0);
5676 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5677 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5678 nw64_mac(RXMAC_FRAG_CNT, 0);
5679 nw64_mac(RXMAC_HIST_CNT1, 0);
5680 nw64_mac(RXMAC_HIST_CNT2, 0);
5681 nw64_mac(RXMAC_HIST_CNT3, 0);
5682 nw64_mac(RXMAC_HIST_CNT4, 0);
5683 nw64_mac(RXMAC_HIST_CNT5, 0);
5684 nw64_mac(RXMAC_HIST_CNT6, 0);
5685 nw64_mac(RXMAC_HIST_CNT7, 0);
5686 nw64_mac(RXMAC_MPSZER_CNT, 0);
5687 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5688 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5689 nw64_mac(LINK_FAULT_CNT, 0);
5690 }
5691
5692 static void niu_init_rx_bmac(struct niu *np)
5693 {
5694 struct niu_parent *parent = np->parent;
5695 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5696 int first_rdc_table = tp->first_table_num;
5697 unsigned long i;
5698 u64 val;
5699
5700 nw64_mac(BMAC_ADD_FILT0, 0);
5701 nw64_mac(BMAC_ADD_FILT1, 0);
5702 nw64_mac(BMAC_ADD_FILT2, 0);
5703 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5704 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5705 for (i = 0; i < MAC_NUM_HASH; i++)
5706 nw64_mac(BMAC_HASH_TBL(i), 0);
5707 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5708 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5709 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5710
5711 val = nr64_mac(BRXMAC_CONFIG);
5712 val &= ~(BRXMAC_CONFIG_ENABLE |
5713 BRXMAC_CONFIG_STRIP_PAD |
5714 BRXMAC_CONFIG_STRIP_FCS |
5715 BRXMAC_CONFIG_PROMISC |
5716 BRXMAC_CONFIG_PROMISC_GRP |
5717 BRXMAC_CONFIG_ADDR_FILT_EN |
5718 BRXMAC_CONFIG_DISCARD_DIS);
5719 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5720 nw64_mac(BRXMAC_CONFIG, val);
5721
5722 val = nr64_mac(BMAC_ADDR_CMPEN);
5723 val |= BMAC_ADDR_CMPEN_EN0;
5724 nw64_mac(BMAC_ADDR_CMPEN, val);
5725 }
5726
5727 static void niu_init_rx_mac(struct niu *np)
5728 {
5729 niu_set_primary_mac(np, np->dev->dev_addr);
5730
5731 if (np->flags & NIU_FLAGS_XMAC)
5732 niu_init_rx_xmac(np);
5733 else
5734 niu_init_rx_bmac(np);
5735 }
5736
5737 static void niu_enable_tx_xmac(struct niu *np, int on)
5738 {
5739 u64 val = nr64_mac(XMAC_CONFIG);
5740
5741 if (on)
5742 val |= XMAC_CONFIG_TX_ENABLE;
5743 else
5744 val &= ~XMAC_CONFIG_TX_ENABLE;
5745 nw64_mac(XMAC_CONFIG, val);
5746 }
5747
5748 static void niu_enable_tx_bmac(struct niu *np, int on)
5749 {
5750 u64 val = nr64_mac(BTXMAC_CONFIG);
5751
5752 if (on)
5753 val |= BTXMAC_CONFIG_ENABLE;
5754 else
5755 val &= ~BTXMAC_CONFIG_ENABLE;
5756 nw64_mac(BTXMAC_CONFIG, val);
5757 }
5758
5759 static void niu_enable_tx_mac(struct niu *np, int on)
5760 {
5761 if (np->flags & NIU_FLAGS_XMAC)
5762 niu_enable_tx_xmac(np, on);
5763 else
5764 niu_enable_tx_bmac(np, on);
5765 }
5766
5767 static void niu_enable_rx_xmac(struct niu *np, int on)
5768 {
5769 u64 val = nr64_mac(XMAC_CONFIG);
5770
5771 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5772 XMAC_CONFIG_PROMISCUOUS);
5773
5774 if (np->flags & NIU_FLAGS_MCAST)
5775 val |= XMAC_CONFIG_HASH_FILTER_EN;
5776 if (np->flags & NIU_FLAGS_PROMISC)
5777 val |= XMAC_CONFIG_PROMISCUOUS;
5778
5779 if (on)
5780 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5781 else
5782 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5783 nw64_mac(XMAC_CONFIG, val);
5784 }
5785
5786 static void niu_enable_rx_bmac(struct niu *np, int on)
5787 {
5788 u64 val = nr64_mac(BRXMAC_CONFIG);
5789
5790 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5791 BRXMAC_CONFIG_PROMISC);
5792
5793 if (np->flags & NIU_FLAGS_MCAST)
5794 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5795 if (np->flags & NIU_FLAGS_PROMISC)
5796 val |= BRXMAC_CONFIG_PROMISC;
5797
5798 if (on)
5799 val |= BRXMAC_CONFIG_ENABLE;
5800 else
5801 val &= ~BRXMAC_CONFIG_ENABLE;
5802 nw64_mac(BRXMAC_CONFIG, val);
5803 }
5804
5805 static void niu_enable_rx_mac(struct niu *np, int on)
5806 {
5807 if (np->flags & NIU_FLAGS_XMAC)
5808 niu_enable_rx_xmac(np, on);
5809 else
5810 niu_enable_rx_bmac(np, on);
5811 }
5812
5813 static int niu_init_mac(struct niu *np)
5814 {
5815 int err;
5816
5817 niu_init_xif(np);
5818 err = niu_init_pcs(np);
5819 if (err)
5820 return err;
5821
5822 err = niu_reset_tx_mac(np);
5823 if (err)
5824 return err;
5825 niu_init_tx_mac(np);
5826 err = niu_reset_rx_mac(np);
5827 if (err)
5828 return err;
5829 niu_init_rx_mac(np);
5830
5831 /* This looks hookey but the RX MAC reset we just did will
5832 * undo some of the state we setup in niu_init_tx_mac() so we
5833 * have to call it again. In particular, the RX MAC reset will
5834 * set the XMAC_MAX register back to it's default value.
5835 */
5836 niu_init_tx_mac(np);
5837 niu_enable_tx_mac(np, 1);
5838
5839 niu_enable_rx_mac(np, 1);
5840
5841 return 0;
5842 }
5843
5844 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5845 {
5846 (void) niu_tx_channel_stop(np, rp->tx_channel);
5847 }
5848
5849 static void niu_stop_tx_channels(struct niu *np)
5850 {
5851 int i;
5852
5853 for (i = 0; i < np->num_tx_rings; i++) {
5854 struct tx_ring_info *rp = &np->tx_rings[i];
5855
5856 niu_stop_one_tx_channel(np, rp);
5857 }
5858 }
5859
5860 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5861 {
5862 (void) niu_tx_channel_reset(np, rp->tx_channel);
5863 }
5864
5865 static void niu_reset_tx_channels(struct niu *np)
5866 {
5867 int i;
5868
5869 for (i = 0; i < np->num_tx_rings; i++) {
5870 struct tx_ring_info *rp = &np->tx_rings[i];
5871
5872 niu_reset_one_tx_channel(np, rp);
5873 }
5874 }
5875
5876 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5877 {
5878 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5879 }
5880
5881 static void niu_stop_rx_channels(struct niu *np)
5882 {
5883 int i;
5884
5885 for (i = 0; i < np->num_rx_rings; i++) {
5886 struct rx_ring_info *rp = &np->rx_rings[i];
5887
5888 niu_stop_one_rx_channel(np, rp);
5889 }
5890 }
5891
5892 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5893 {
5894 int channel = rp->rx_channel;
5895
5896 (void) niu_rx_channel_reset(np, channel);
5897 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5898 nw64(RX_DMA_CTL_STAT(channel), 0);
5899 (void) niu_enable_rx_channel(np, channel, 0);
5900 }
5901
5902 static void niu_reset_rx_channels(struct niu *np)
5903 {
5904 int i;
5905
5906 for (i = 0; i < np->num_rx_rings; i++) {
5907 struct rx_ring_info *rp = &np->rx_rings[i];
5908
5909 niu_reset_one_rx_channel(np, rp);
5910 }
5911 }
5912
5913 static void niu_disable_ipp(struct niu *np)
5914 {
5915 u64 rd, wr, val;
5916 int limit;
5917
5918 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5919 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5920 limit = 100;
5921 while (--limit >= 0 && (rd != wr)) {
5922 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5923 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5924 }
5925 if (limit < 0 &&
5926 (rd != 0 && wr != 1)) {
5927 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5928 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5929 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5930 }
5931
5932 val = nr64_ipp(IPP_CFIG);
5933 val &= ~(IPP_CFIG_IPP_ENABLE |
5934 IPP_CFIG_DFIFO_ECC_EN |
5935 IPP_CFIG_DROP_BAD_CRC |
5936 IPP_CFIG_CKSUM_EN);
5937 nw64_ipp(IPP_CFIG, val);
5938
5939 (void) niu_ipp_reset(np);
5940 }
5941
5942 static int niu_init_hw(struct niu *np)
5943 {
5944 int i, err;
5945
5946 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5947 niu_txc_enable_port(np, 1);
5948 niu_txc_port_dma_enable(np, 1);
5949 niu_txc_set_imask(np, 0);
5950
5951 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5952 for (i = 0; i < np->num_tx_rings; i++) {
5953 struct tx_ring_info *rp = &np->tx_rings[i];
5954
5955 err = niu_init_one_tx_channel(np, rp);
5956 if (err)
5957 return err;
5958 }
5959
5960 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5961 err = niu_init_rx_channels(np);
5962 if (err)
5963 goto out_uninit_tx_channels;
5964
5965 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5966 err = niu_init_classifier_hw(np);
5967 if (err)
5968 goto out_uninit_rx_channels;
5969
5970 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5971 err = niu_init_zcp(np);
5972 if (err)
5973 goto out_uninit_rx_channels;
5974
5975 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5976 err = niu_init_ipp(np);
5977 if (err)
5978 goto out_uninit_rx_channels;
5979
5980 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5981 err = niu_init_mac(np);
5982 if (err)
5983 goto out_uninit_ipp;
5984
5985 return 0;
5986
5987 out_uninit_ipp:
5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5989 niu_disable_ipp(np);
5990
5991 out_uninit_rx_channels:
5992 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5993 niu_stop_rx_channels(np);
5994 niu_reset_rx_channels(np);
5995
5996 out_uninit_tx_channels:
5997 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5998 niu_stop_tx_channels(np);
5999 niu_reset_tx_channels(np);
6000
6001 return err;
6002 }
6003
6004 static void niu_stop_hw(struct niu *np)
6005 {
6006 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6007 niu_enable_interrupts(np, 0);
6008
6009 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6010 niu_enable_rx_mac(np, 0);
6011
6012 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6013 niu_disable_ipp(np);
6014
6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6016 niu_stop_tx_channels(np);
6017
6018 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6019 niu_stop_rx_channels(np);
6020
6021 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6022 niu_reset_tx_channels(np);
6023
6024 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6025 niu_reset_rx_channels(np);
6026 }
6027
6028 static void niu_set_irq_name(struct niu *np)
6029 {
6030 int port = np->port;
6031 int i, j = 1;
6032
6033 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6034
6035 if (port == 0) {
6036 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6037 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6038 j = 3;
6039 }
6040
6041 for (i = 0; i < np->num_ldg - j; i++) {
6042 if (i < np->num_rx_rings)
6043 sprintf(np->irq_name[i+j], "%s-rx-%d",
6044 np->dev->name, i);
6045 else if (i < np->num_tx_rings + np->num_rx_rings)
6046 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6047 i - np->num_rx_rings);
6048 }
6049 }
6050
6051 static int niu_request_irq(struct niu *np)
6052 {
6053 int i, j, err;
6054
6055 niu_set_irq_name(np);
6056
6057 err = 0;
6058 for (i = 0; i < np->num_ldg; i++) {
6059 struct niu_ldg *lp = &np->ldg[i];
6060
6061 err = request_irq(lp->irq, niu_interrupt,
6062 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
6063 np->irq_name[i], lp);
6064 if (err)
6065 goto out_free_irqs;
6066
6067 }
6068
6069 return 0;
6070
6071 out_free_irqs:
6072 for (j = 0; j < i; j++) {
6073 struct niu_ldg *lp = &np->ldg[j];
6074
6075 free_irq(lp->irq, lp);
6076 }
6077 return err;
6078 }
6079
6080 static void niu_free_irq(struct niu *np)
6081 {
6082 int i;
6083
6084 for (i = 0; i < np->num_ldg; i++) {
6085 struct niu_ldg *lp = &np->ldg[i];
6086
6087 free_irq(lp->irq, lp);
6088 }
6089 }
6090
6091 static void niu_enable_napi(struct niu *np)
6092 {
6093 int i;
6094
6095 for (i = 0; i < np->num_ldg; i++)
6096 napi_enable(&np->ldg[i].napi);
6097 }
6098
6099 static void niu_disable_napi(struct niu *np)
6100 {
6101 int i;
6102
6103 for (i = 0; i < np->num_ldg; i++)
6104 napi_disable(&np->ldg[i].napi);
6105 }
6106
6107 static int niu_open(struct net_device *dev)
6108 {
6109 struct niu *np = netdev_priv(dev);
6110 int err;
6111
6112 netif_carrier_off(dev);
6113
6114 err = niu_alloc_channels(np);
6115 if (err)
6116 goto out_err;
6117
6118 err = niu_enable_interrupts(np, 0);
6119 if (err)
6120 goto out_free_channels;
6121
6122 err = niu_request_irq(np);
6123 if (err)
6124 goto out_free_channels;
6125
6126 niu_enable_napi(np);
6127
6128 spin_lock_irq(&np->lock);
6129
6130 err = niu_init_hw(np);
6131 if (!err) {
6132 init_timer(&np->timer);
6133 np->timer.expires = jiffies + HZ;
6134 np->timer.data = (unsigned long) np;
6135 np->timer.function = niu_timer;
6136
6137 err = niu_enable_interrupts(np, 1);
6138 if (err)
6139 niu_stop_hw(np);
6140 }
6141
6142 spin_unlock_irq(&np->lock);
6143
6144 if (err) {
6145 niu_disable_napi(np);
6146 goto out_free_irq;
6147 }
6148
6149 netif_tx_start_all_queues(dev);
6150
6151 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6152 netif_carrier_on(dev);
6153
6154 add_timer(&np->timer);
6155
6156 return 0;
6157
6158 out_free_irq:
6159 niu_free_irq(np);
6160
6161 out_free_channels:
6162 niu_free_channels(np);
6163
6164 out_err:
6165 return err;
6166 }
6167
6168 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6169 {
6170 cancel_work_sync(&np->reset_task);
6171
6172 niu_disable_napi(np);
6173 netif_tx_stop_all_queues(dev);
6174
6175 del_timer_sync(&np->timer);
6176
6177 spin_lock_irq(&np->lock);
6178
6179 niu_stop_hw(np);
6180
6181 spin_unlock_irq(&np->lock);
6182 }
6183
6184 static int niu_close(struct net_device *dev)
6185 {
6186 struct niu *np = netdev_priv(dev);
6187
6188 niu_full_shutdown(np, dev);
6189
6190 niu_free_irq(np);
6191
6192 niu_free_channels(np);
6193
6194 niu_handle_led(np, 0);
6195
6196 return 0;
6197 }
6198
6199 static void niu_sync_xmac_stats(struct niu *np)
6200 {
6201 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6202
6203 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6204 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6205
6206 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6207 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6208 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6209 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6210 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6211 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6212 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6213 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6214 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6215 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6216 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6217 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6218 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6219 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6220 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6221 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6222 }
6223
6224 static void niu_sync_bmac_stats(struct niu *np)
6225 {
6226 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6227
6228 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6229 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6230
6231 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6232 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6233 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6235 }
6236
6237 static void niu_sync_mac_stats(struct niu *np)
6238 {
6239 if (np->flags & NIU_FLAGS_XMAC)
6240 niu_sync_xmac_stats(np);
6241 else
6242 niu_sync_bmac_stats(np);
6243 }
6244
6245 static void niu_get_rx_stats(struct niu *np)
6246 {
6247 unsigned long pkts, dropped, errors, bytes;
6248 int i;
6249
6250 pkts = dropped = errors = bytes = 0;
6251 for (i = 0; i < np->num_rx_rings; i++) {
6252 struct rx_ring_info *rp = &np->rx_rings[i];
6253
6254 niu_sync_rx_discard_stats(np, rp, 0);
6255
6256 pkts += rp->rx_packets;
6257 bytes += rp->rx_bytes;
6258 dropped += rp->rx_dropped;
6259 errors += rp->rx_errors;
6260 }
6261 np->dev->stats.rx_packets = pkts;
6262 np->dev->stats.rx_bytes = bytes;
6263 np->dev->stats.rx_dropped = dropped;
6264 np->dev->stats.rx_errors = errors;
6265 }
6266
6267 static void niu_get_tx_stats(struct niu *np)
6268 {
6269 unsigned long pkts, errors, bytes;
6270 int i;
6271
6272 pkts = errors = bytes = 0;
6273 for (i = 0; i < np->num_tx_rings; i++) {
6274 struct tx_ring_info *rp = &np->tx_rings[i];
6275
6276 pkts += rp->tx_packets;
6277 bytes += rp->tx_bytes;
6278 errors += rp->tx_errors;
6279 }
6280 np->dev->stats.tx_packets = pkts;
6281 np->dev->stats.tx_bytes = bytes;
6282 np->dev->stats.tx_errors = errors;
6283 }
6284
6285 static struct net_device_stats *niu_get_stats(struct net_device *dev)
6286 {
6287 struct niu *np = netdev_priv(dev);
6288
6289 niu_get_rx_stats(np);
6290 niu_get_tx_stats(np);
6291
6292 return &dev->stats;
6293 }
6294
6295 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6296 {
6297 int i;
6298
6299 for (i = 0; i < 16; i++)
6300 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6301 }
6302
6303 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6304 {
6305 int i;
6306
6307 for (i = 0; i < 16; i++)
6308 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6309 }
6310
6311 static void niu_load_hash(struct niu *np, u16 *hash)
6312 {
6313 if (np->flags & NIU_FLAGS_XMAC)
6314 niu_load_hash_xmac(np, hash);
6315 else
6316 niu_load_hash_bmac(np, hash);
6317 }
6318
6319 static void niu_set_rx_mode(struct net_device *dev)
6320 {
6321 struct niu *np = netdev_priv(dev);
6322 int i, alt_cnt, err;
6323 struct netdev_hw_addr *ha;
6324 unsigned long flags;
6325 u16 hash[16] = { 0, };
6326
6327 spin_lock_irqsave(&np->lock, flags);
6328 niu_enable_rx_mac(np, 0);
6329
6330 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6331 if (dev->flags & IFF_PROMISC)
6332 np->flags |= NIU_FLAGS_PROMISC;
6333 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6334 np->flags |= NIU_FLAGS_MCAST;
6335
6336 alt_cnt = netdev_uc_count(dev);
6337 if (alt_cnt > niu_num_alt_addr(np)) {
6338 alt_cnt = 0;
6339 np->flags |= NIU_FLAGS_PROMISC;
6340 }
6341
6342 if (alt_cnt) {
6343 int index = 0;
6344
6345 netdev_for_each_uc_addr(ha, dev) {
6346 err = niu_set_alt_mac(np, index, ha->addr);
6347 if (err)
6348 netdev_warn(dev, "Error %d adding alt mac %d\n",
6349 err, index);
6350 err = niu_enable_alt_mac(np, index, 1);
6351 if (err)
6352 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6353 err, index);
6354
6355 index++;
6356 }
6357 } else {
6358 int alt_start;
6359 if (np->flags & NIU_FLAGS_XMAC)
6360 alt_start = 0;
6361 else
6362 alt_start = 1;
6363 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6364 err = niu_enable_alt_mac(np, i, 0);
6365 if (err)
6366 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6367 err, i);
6368 }
6369 }
6370 if (dev->flags & IFF_ALLMULTI) {
6371 for (i = 0; i < 16; i++)
6372 hash[i] = 0xffff;
6373 } else if (!netdev_mc_empty(dev)) {
6374 netdev_for_each_mc_addr(ha, dev) {
6375 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6376
6377 crc >>= 24;
6378 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6379 }
6380 }
6381
6382 if (np->flags & NIU_FLAGS_MCAST)
6383 niu_load_hash(np, hash);
6384
6385 niu_enable_rx_mac(np, 1);
6386 spin_unlock_irqrestore(&np->lock, flags);
6387 }
6388
6389 static int niu_set_mac_addr(struct net_device *dev, void *p)
6390 {
6391 struct niu *np = netdev_priv(dev);
6392 struct sockaddr *addr = p;
6393 unsigned long flags;
6394
6395 if (!is_valid_ether_addr(addr->sa_data))
6396 return -EINVAL;
6397
6398 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6399
6400 if (!netif_running(dev))
6401 return 0;
6402
6403 spin_lock_irqsave(&np->lock, flags);
6404 niu_enable_rx_mac(np, 0);
6405 niu_set_primary_mac(np, dev->dev_addr);
6406 niu_enable_rx_mac(np, 1);
6407 spin_unlock_irqrestore(&np->lock, flags);
6408
6409 return 0;
6410 }
6411
6412 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6413 {
6414 return -EOPNOTSUPP;
6415 }
6416
6417 static void niu_netif_stop(struct niu *np)
6418 {
6419 np->dev->trans_start = jiffies; /* prevent tx timeout */
6420
6421 niu_disable_napi(np);
6422
6423 netif_tx_disable(np->dev);
6424 }
6425
6426 static void niu_netif_start(struct niu *np)
6427 {
6428 /* NOTE: unconditional netif_wake_queue is only appropriate
6429 * so long as all callers are assured to have free tx slots
6430 * (such as after niu_init_hw).
6431 */
6432 netif_tx_wake_all_queues(np->dev);
6433
6434 niu_enable_napi(np);
6435
6436 niu_enable_interrupts(np, 1);
6437 }
6438
6439 static void niu_reset_buffers(struct niu *np)
6440 {
6441 int i, j, k, err;
6442
6443 if (np->rx_rings) {
6444 for (i = 0; i < np->num_rx_rings; i++) {
6445 struct rx_ring_info *rp = &np->rx_rings[i];
6446
6447 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6448 struct page *page;
6449
6450 page = rp->rxhash[j];
6451 while (page) {
6452 struct page *next =
6453 (struct page *) page->mapping;
6454 u64 base = page->index;
6455 base = base >> RBR_DESCR_ADDR_SHIFT;
6456 rp->rbr[k++] = cpu_to_le32(base);
6457 page = next;
6458 }
6459 }
6460 for (; k < MAX_RBR_RING_SIZE; k++) {
6461 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6462 if (unlikely(err))
6463 break;
6464 }
6465
6466 rp->rbr_index = rp->rbr_table_size - 1;
6467 rp->rcr_index = 0;
6468 rp->rbr_pending = 0;
6469 rp->rbr_refill_pending = 0;
6470 }
6471 }
6472 if (np->tx_rings) {
6473 for (i = 0; i < np->num_tx_rings; i++) {
6474 struct tx_ring_info *rp = &np->tx_rings[i];
6475
6476 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6477 if (rp->tx_buffs[j].skb)
6478 (void) release_tx_packet(np, rp, j);
6479 }
6480
6481 rp->pending = MAX_TX_RING_SIZE;
6482 rp->prod = 0;
6483 rp->cons = 0;
6484 rp->wrap_bit = 0;
6485 }
6486 }
6487 }
6488
6489 static void niu_reset_task(struct work_struct *work)
6490 {
6491 struct niu *np = container_of(work, struct niu, reset_task);
6492 unsigned long flags;
6493 int err;
6494
6495 spin_lock_irqsave(&np->lock, flags);
6496 if (!netif_running(np->dev)) {
6497 spin_unlock_irqrestore(&np->lock, flags);
6498 return;
6499 }
6500
6501 spin_unlock_irqrestore(&np->lock, flags);
6502
6503 del_timer_sync(&np->timer);
6504
6505 niu_netif_stop(np);
6506
6507 spin_lock_irqsave(&np->lock, flags);
6508
6509 niu_stop_hw(np);
6510
6511 spin_unlock_irqrestore(&np->lock, flags);
6512
6513 niu_reset_buffers(np);
6514
6515 spin_lock_irqsave(&np->lock, flags);
6516
6517 err = niu_init_hw(np);
6518 if (!err) {
6519 np->timer.expires = jiffies + HZ;
6520 add_timer(&np->timer);
6521 niu_netif_start(np);
6522 }
6523
6524 spin_unlock_irqrestore(&np->lock, flags);
6525 }
6526
6527 static void niu_tx_timeout(struct net_device *dev)
6528 {
6529 struct niu *np = netdev_priv(dev);
6530
6531 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6532 dev->name);
6533
6534 schedule_work(&np->reset_task);
6535 }
6536
6537 static void niu_set_txd(struct tx_ring_info *rp, int index,
6538 u64 mapping, u64 len, u64 mark,
6539 u64 n_frags)
6540 {
6541 __le64 *desc = &rp->descr[index];
6542
6543 *desc = cpu_to_le64(mark |
6544 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6545 (len << TX_DESC_TR_LEN_SHIFT) |
6546 (mapping & TX_DESC_SAD));
6547 }
6548
6549 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6550 u64 pad_bytes, u64 len)
6551 {
6552 u16 eth_proto, eth_proto_inner;
6553 u64 csum_bits, l3off, ihl, ret;
6554 u8 ip_proto;
6555 int ipv6;
6556
6557 eth_proto = be16_to_cpu(ehdr->h_proto);
6558 eth_proto_inner = eth_proto;
6559 if (eth_proto == ETH_P_8021Q) {
6560 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6561 __be16 val = vp->h_vlan_encapsulated_proto;
6562
6563 eth_proto_inner = be16_to_cpu(val);
6564 }
6565
6566 ipv6 = ihl = 0;
6567 switch (skb->protocol) {
6568 case cpu_to_be16(ETH_P_IP):
6569 ip_proto = ip_hdr(skb)->protocol;
6570 ihl = ip_hdr(skb)->ihl;
6571 break;
6572 case cpu_to_be16(ETH_P_IPV6):
6573 ip_proto = ipv6_hdr(skb)->nexthdr;
6574 ihl = (40 >> 2);
6575 ipv6 = 1;
6576 break;
6577 default:
6578 ip_proto = ihl = 0;
6579 break;
6580 }
6581
6582 csum_bits = TXHDR_CSUM_NONE;
6583 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6584 u64 start, stuff;
6585
6586 csum_bits = (ip_proto == IPPROTO_TCP ?
6587 TXHDR_CSUM_TCP :
6588 (ip_proto == IPPROTO_UDP ?
6589 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6590
6591 start = skb_transport_offset(skb) -
6592 (pad_bytes + sizeof(struct tx_pkt_hdr));
6593 stuff = start + skb->csum_offset;
6594
6595 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6596 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6597 }
6598
6599 l3off = skb_network_offset(skb) -
6600 (pad_bytes + sizeof(struct tx_pkt_hdr));
6601
6602 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6603 (len << TXHDR_LEN_SHIFT) |
6604 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6605 (ihl << TXHDR_IHL_SHIFT) |
6606 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6607 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6608 (ipv6 ? TXHDR_IP_VER : 0) |
6609 csum_bits);
6610
6611 return ret;
6612 }
6613
6614 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6615 struct net_device *dev)
6616 {
6617 struct niu *np = netdev_priv(dev);
6618 unsigned long align, headroom;
6619 struct netdev_queue *txq;
6620 struct tx_ring_info *rp;
6621 struct tx_pkt_hdr *tp;
6622 unsigned int len, nfg;
6623 struct ethhdr *ehdr;
6624 int prod, i, tlen;
6625 u64 mapping, mrk;
6626
6627 i = skb_get_queue_mapping(skb);
6628 rp = &np->tx_rings[i];
6629 txq = netdev_get_tx_queue(dev, i);
6630
6631 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6632 netif_tx_stop_queue(txq);
6633 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6634 rp->tx_errors++;
6635 return NETDEV_TX_BUSY;
6636 }
6637
6638 if (skb->len < ETH_ZLEN) {
6639 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6640
6641 if (skb_pad(skb, pad_bytes))
6642 goto out;
6643 skb_put(skb, pad_bytes);
6644 }
6645
6646 len = sizeof(struct tx_pkt_hdr) + 15;
6647 if (skb_headroom(skb) < len) {
6648 struct sk_buff *skb_new;
6649
6650 skb_new = skb_realloc_headroom(skb, len);
6651 if (!skb_new) {
6652 rp->tx_errors++;
6653 goto out_drop;
6654 }
6655 kfree_skb(skb);
6656 skb = skb_new;
6657 } else
6658 skb_orphan(skb);
6659
6660 align = ((unsigned long) skb->data & (16 - 1));
6661 headroom = align + sizeof(struct tx_pkt_hdr);
6662
6663 ehdr = (struct ethhdr *) skb->data;
6664 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6665
6666 len = skb->len - sizeof(struct tx_pkt_hdr);
6667 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6668 tp->resv = 0;
6669
6670 len = skb_headlen(skb);
6671 mapping = np->ops->map_single(np->device, skb->data,
6672 len, DMA_TO_DEVICE);
6673
6674 prod = rp->prod;
6675
6676 rp->tx_buffs[prod].skb = skb;
6677 rp->tx_buffs[prod].mapping = mapping;
6678
6679 mrk = TX_DESC_SOP;
6680 if (++rp->mark_counter == rp->mark_freq) {
6681 rp->mark_counter = 0;
6682 mrk |= TX_DESC_MARK;
6683 rp->mark_pending++;
6684 }
6685
6686 tlen = len;
6687 nfg = skb_shinfo(skb)->nr_frags;
6688 while (tlen > 0) {
6689 tlen -= MAX_TX_DESC_LEN;
6690 nfg++;
6691 }
6692
6693 while (len > 0) {
6694 unsigned int this_len = len;
6695
6696 if (this_len > MAX_TX_DESC_LEN)
6697 this_len = MAX_TX_DESC_LEN;
6698
6699 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6700 mrk = nfg = 0;
6701
6702 prod = NEXT_TX(rp, prod);
6703 mapping += this_len;
6704 len -= this_len;
6705 }
6706
6707 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6708 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6709
6710 len = frag->size;
6711 mapping = np->ops->map_page(np->device, frag->page,
6712 frag->page_offset, len,
6713 DMA_TO_DEVICE);
6714
6715 rp->tx_buffs[prod].skb = NULL;
6716 rp->tx_buffs[prod].mapping = mapping;
6717
6718 niu_set_txd(rp, prod, mapping, len, 0, 0);
6719
6720 prod = NEXT_TX(rp, prod);
6721 }
6722
6723 if (prod < rp->prod)
6724 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6725 rp->prod = prod;
6726
6727 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6728
6729 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6730 netif_tx_stop_queue(txq);
6731 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6732 netif_tx_wake_queue(txq);
6733 }
6734
6735 out:
6736 return NETDEV_TX_OK;
6737
6738 out_drop:
6739 rp->tx_errors++;
6740 kfree_skb(skb);
6741 goto out;
6742 }
6743
6744 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6745 {
6746 struct niu *np = netdev_priv(dev);
6747 int err, orig_jumbo, new_jumbo;
6748
6749 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6750 return -EINVAL;
6751
6752 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6753 new_jumbo = (new_mtu > ETH_DATA_LEN);
6754
6755 dev->mtu = new_mtu;
6756
6757 if (!netif_running(dev) ||
6758 (orig_jumbo == new_jumbo))
6759 return 0;
6760
6761 niu_full_shutdown(np, dev);
6762
6763 niu_free_channels(np);
6764
6765 niu_enable_napi(np);
6766
6767 err = niu_alloc_channels(np);
6768 if (err)
6769 return err;
6770
6771 spin_lock_irq(&np->lock);
6772
6773 err = niu_init_hw(np);
6774 if (!err) {
6775 init_timer(&np->timer);
6776 np->timer.expires = jiffies + HZ;
6777 np->timer.data = (unsigned long) np;
6778 np->timer.function = niu_timer;
6779
6780 err = niu_enable_interrupts(np, 1);
6781 if (err)
6782 niu_stop_hw(np);
6783 }
6784
6785 spin_unlock_irq(&np->lock);
6786
6787 if (!err) {
6788 netif_tx_start_all_queues(dev);
6789 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6790 netif_carrier_on(dev);
6791
6792 add_timer(&np->timer);
6793 }
6794
6795 return err;
6796 }
6797
6798 static void niu_get_drvinfo(struct net_device *dev,
6799 struct ethtool_drvinfo *info)
6800 {
6801 struct niu *np = netdev_priv(dev);
6802 struct niu_vpd *vpd = &np->vpd;
6803
6804 strcpy(info->driver, DRV_MODULE_NAME);
6805 strcpy(info->version, DRV_MODULE_VERSION);
6806 sprintf(info->fw_version, "%d.%d",
6807 vpd->fcode_major, vpd->fcode_minor);
6808 if (np->parent->plat_type != PLAT_TYPE_NIU)
6809 strcpy(info->bus_info, pci_name(np->pdev));
6810 }
6811
6812 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6813 {
6814 struct niu *np = netdev_priv(dev);
6815 struct niu_link_config *lp;
6816
6817 lp = &np->link_config;
6818
6819 memset(cmd, 0, sizeof(*cmd));
6820 cmd->phy_address = np->phy_addr;
6821 cmd->supported = lp->supported;
6822 cmd->advertising = lp->active_advertising;
6823 cmd->autoneg = lp->active_autoneg;
6824 cmd->speed = lp->active_speed;
6825 cmd->duplex = lp->active_duplex;
6826 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6827 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6828 XCVR_EXTERNAL : XCVR_INTERNAL;
6829
6830 return 0;
6831 }
6832
6833 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6834 {
6835 struct niu *np = netdev_priv(dev);
6836 struct niu_link_config *lp = &np->link_config;
6837
6838 lp->advertising = cmd->advertising;
6839 lp->speed = cmd->speed;
6840 lp->duplex = cmd->duplex;
6841 lp->autoneg = cmd->autoneg;
6842 return niu_init_link(np);
6843 }
6844
6845 static u32 niu_get_msglevel(struct net_device *dev)
6846 {
6847 struct niu *np = netdev_priv(dev);
6848 return np->msg_enable;
6849 }
6850
6851 static void niu_set_msglevel(struct net_device *dev, u32 value)
6852 {
6853 struct niu *np = netdev_priv(dev);
6854 np->msg_enable = value;
6855 }
6856
6857 static int niu_nway_reset(struct net_device *dev)
6858 {
6859 struct niu *np = netdev_priv(dev);
6860
6861 if (np->link_config.autoneg)
6862 return niu_init_link(np);
6863
6864 return 0;
6865 }
6866
6867 static int niu_get_eeprom_len(struct net_device *dev)
6868 {
6869 struct niu *np = netdev_priv(dev);
6870
6871 return np->eeprom_len;
6872 }
6873
6874 static int niu_get_eeprom(struct net_device *dev,
6875 struct ethtool_eeprom *eeprom, u8 *data)
6876 {
6877 struct niu *np = netdev_priv(dev);
6878 u32 offset, len, val;
6879
6880 offset = eeprom->offset;
6881 len = eeprom->len;
6882
6883 if (offset + len < offset)
6884 return -EINVAL;
6885 if (offset >= np->eeprom_len)
6886 return -EINVAL;
6887 if (offset + len > np->eeprom_len)
6888 len = eeprom->len = np->eeprom_len - offset;
6889
6890 if (offset & 3) {
6891 u32 b_offset, b_count;
6892
6893 b_offset = offset & 3;
6894 b_count = 4 - b_offset;
6895 if (b_count > len)
6896 b_count = len;
6897
6898 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6899 memcpy(data, ((char *)&val) + b_offset, b_count);
6900 data += b_count;
6901 len -= b_count;
6902 offset += b_count;
6903 }
6904 while (len >= 4) {
6905 val = nr64(ESPC_NCR(offset / 4));
6906 memcpy(data, &val, 4);
6907 data += 4;
6908 len -= 4;
6909 offset += 4;
6910 }
6911 if (len) {
6912 val = nr64(ESPC_NCR(offset / 4));
6913 memcpy(data, &val, len);
6914 }
6915 return 0;
6916 }
6917
6918 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6919 {
6920 switch (flow_type) {
6921 case TCP_V4_FLOW:
6922 case TCP_V6_FLOW:
6923 *pid = IPPROTO_TCP;
6924 break;
6925 case UDP_V4_FLOW:
6926 case UDP_V6_FLOW:
6927 *pid = IPPROTO_UDP;
6928 break;
6929 case SCTP_V4_FLOW:
6930 case SCTP_V6_FLOW:
6931 *pid = IPPROTO_SCTP;
6932 break;
6933 case AH_V4_FLOW:
6934 case AH_V6_FLOW:
6935 *pid = IPPROTO_AH;
6936 break;
6937 case ESP_V4_FLOW:
6938 case ESP_V6_FLOW:
6939 *pid = IPPROTO_ESP;
6940 break;
6941 default:
6942 *pid = 0;
6943 break;
6944 }
6945 }
6946
6947 static int niu_class_to_ethflow(u64 class, int *flow_type)
6948 {
6949 switch (class) {
6950 case CLASS_CODE_TCP_IPV4:
6951 *flow_type = TCP_V4_FLOW;
6952 break;
6953 case CLASS_CODE_UDP_IPV4:
6954 *flow_type = UDP_V4_FLOW;
6955 break;
6956 case CLASS_CODE_AH_ESP_IPV4:
6957 *flow_type = AH_V4_FLOW;
6958 break;
6959 case CLASS_CODE_SCTP_IPV4:
6960 *flow_type = SCTP_V4_FLOW;
6961 break;
6962 case CLASS_CODE_TCP_IPV6:
6963 *flow_type = TCP_V6_FLOW;
6964 break;
6965 case CLASS_CODE_UDP_IPV6:
6966 *flow_type = UDP_V6_FLOW;
6967 break;
6968 case CLASS_CODE_AH_ESP_IPV6:
6969 *flow_type = AH_V6_FLOW;
6970 break;
6971 case CLASS_CODE_SCTP_IPV6:
6972 *flow_type = SCTP_V6_FLOW;
6973 break;
6974 case CLASS_CODE_USER_PROG1:
6975 case CLASS_CODE_USER_PROG2:
6976 case CLASS_CODE_USER_PROG3:
6977 case CLASS_CODE_USER_PROG4:
6978 *flow_type = IP_USER_FLOW;
6979 break;
6980 default:
6981 return 0;
6982 }
6983
6984 return 1;
6985 }
6986
6987 static int niu_ethflow_to_class(int flow_type, u64 *class)
6988 {
6989 switch (flow_type) {
6990 case TCP_V4_FLOW:
6991 *class = CLASS_CODE_TCP_IPV4;
6992 break;
6993 case UDP_V4_FLOW:
6994 *class = CLASS_CODE_UDP_IPV4;
6995 break;
6996 case AH_V4_FLOW:
6997 case ESP_V4_FLOW:
6998 *class = CLASS_CODE_AH_ESP_IPV4;
6999 break;
7000 case SCTP_V4_FLOW:
7001 *class = CLASS_CODE_SCTP_IPV4;
7002 break;
7003 case TCP_V6_FLOW:
7004 *class = CLASS_CODE_TCP_IPV6;
7005 break;
7006 case UDP_V6_FLOW:
7007 *class = CLASS_CODE_UDP_IPV6;
7008 break;
7009 case AH_V6_FLOW:
7010 case ESP_V6_FLOW:
7011 *class = CLASS_CODE_AH_ESP_IPV6;
7012 break;
7013 case SCTP_V6_FLOW:
7014 *class = CLASS_CODE_SCTP_IPV6;
7015 break;
7016 default:
7017 return 0;
7018 }
7019
7020 return 1;
7021 }
7022
7023 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7024 {
7025 u64 ethflow = 0;
7026
7027 if (flow_key & FLOW_KEY_L2DA)
7028 ethflow |= RXH_L2DA;
7029 if (flow_key & FLOW_KEY_VLAN)
7030 ethflow |= RXH_VLAN;
7031 if (flow_key & FLOW_KEY_IPSA)
7032 ethflow |= RXH_IP_SRC;
7033 if (flow_key & FLOW_KEY_IPDA)
7034 ethflow |= RXH_IP_DST;
7035 if (flow_key & FLOW_KEY_PROTO)
7036 ethflow |= RXH_L3_PROTO;
7037 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7038 ethflow |= RXH_L4_B_0_1;
7039 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7040 ethflow |= RXH_L4_B_2_3;
7041
7042 return ethflow;
7043
7044 }
7045
7046 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7047 {
7048 u64 key = 0;
7049
7050 if (ethflow & RXH_L2DA)
7051 key |= FLOW_KEY_L2DA;
7052 if (ethflow & RXH_VLAN)
7053 key |= FLOW_KEY_VLAN;
7054 if (ethflow & RXH_IP_SRC)
7055 key |= FLOW_KEY_IPSA;
7056 if (ethflow & RXH_IP_DST)
7057 key |= FLOW_KEY_IPDA;
7058 if (ethflow & RXH_L3_PROTO)
7059 key |= FLOW_KEY_PROTO;
7060 if (ethflow & RXH_L4_B_0_1)
7061 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7062 if (ethflow & RXH_L4_B_2_3)
7063 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7064
7065 *flow_key = key;
7066
7067 return 1;
7068
7069 }
7070
7071 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7072 {
7073 u64 class;
7074
7075 nfc->data = 0;
7076
7077 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7078 return -EINVAL;
7079
7080 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7081 TCAM_KEY_DISC)
7082 nfc->data = RXH_DISCARD;
7083 else
7084 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7085 CLASS_CODE_USER_PROG1]);
7086 return 0;
7087 }
7088
7089 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7090 struct ethtool_rx_flow_spec *fsp)
7091 {
7092
7093 fsp->h_u.tcp_ip4_spec.ip4src = (tp->key[3] & TCAM_V4KEY3_SADDR) >>
7094 TCAM_V4KEY3_SADDR_SHIFT;
7095 fsp->h_u.tcp_ip4_spec.ip4dst = (tp->key[3] & TCAM_V4KEY3_DADDR) >>
7096 TCAM_V4KEY3_DADDR_SHIFT;
7097 fsp->m_u.tcp_ip4_spec.ip4src = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >>
7098 TCAM_V4KEY3_SADDR_SHIFT;
7099 fsp->m_u.tcp_ip4_spec.ip4dst = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >>
7100 TCAM_V4KEY3_DADDR_SHIFT;
7101
7102 fsp->h_u.tcp_ip4_spec.ip4src =
7103 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4src);
7104 fsp->m_u.tcp_ip4_spec.ip4src =
7105 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4src);
7106 fsp->h_u.tcp_ip4_spec.ip4dst =
7107 cpu_to_be32(fsp->h_u.tcp_ip4_spec.ip4dst);
7108 fsp->m_u.tcp_ip4_spec.ip4dst =
7109 cpu_to_be32(fsp->m_u.tcp_ip4_spec.ip4dst);
7110
7111 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7112 TCAM_V4KEY2_TOS_SHIFT;
7113 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7114 TCAM_V4KEY2_TOS_SHIFT;
7115
7116 switch (fsp->flow_type) {
7117 case TCP_V4_FLOW:
7118 case UDP_V4_FLOW:
7119 case SCTP_V4_FLOW:
7120 fsp->h_u.tcp_ip4_spec.psrc =
7121 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7122 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7123 fsp->h_u.tcp_ip4_spec.pdst =
7124 ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7125 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7126 fsp->m_u.tcp_ip4_spec.psrc =
7127 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7128 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7129 fsp->m_u.tcp_ip4_spec.pdst =
7130 ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7131 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7132
7133 fsp->h_u.tcp_ip4_spec.psrc =
7134 cpu_to_be16(fsp->h_u.tcp_ip4_spec.psrc);
7135 fsp->h_u.tcp_ip4_spec.pdst =
7136 cpu_to_be16(fsp->h_u.tcp_ip4_spec.pdst);
7137 fsp->m_u.tcp_ip4_spec.psrc =
7138 cpu_to_be16(fsp->m_u.tcp_ip4_spec.psrc);
7139 fsp->m_u.tcp_ip4_spec.pdst =
7140 cpu_to_be16(fsp->m_u.tcp_ip4_spec.pdst);
7141 break;
7142 case AH_V4_FLOW:
7143 case ESP_V4_FLOW:
7144 fsp->h_u.ah_ip4_spec.spi =
7145 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7146 TCAM_V4KEY2_PORT_SPI_SHIFT;
7147 fsp->m_u.ah_ip4_spec.spi =
7148 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT;
7150
7151 fsp->h_u.ah_ip4_spec.spi =
7152 cpu_to_be32(fsp->h_u.ah_ip4_spec.spi);
7153 fsp->m_u.ah_ip4_spec.spi =
7154 cpu_to_be32(fsp->m_u.ah_ip4_spec.spi);
7155 break;
7156 case IP_USER_FLOW:
7157 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7158 (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7159 TCAM_V4KEY2_PORT_SPI_SHIFT;
7160 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7161 (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7162 TCAM_V4KEY2_PORT_SPI_SHIFT;
7163
7164 fsp->h_u.usr_ip4_spec.l4_4_bytes =
7165 cpu_to_be32(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7166 fsp->m_u.usr_ip4_spec.l4_4_bytes =
7167 cpu_to_be32(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7168
7169 fsp->h_u.usr_ip4_spec.proto =
7170 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7171 TCAM_V4KEY2_PROTO_SHIFT;
7172 fsp->m_u.usr_ip4_spec.proto =
7173 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7174 TCAM_V4KEY2_PROTO_SHIFT;
7175
7176 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7177 break;
7178 default:
7179 break;
7180 }
7181 }
7182
7183 static int niu_get_ethtool_tcam_entry(struct niu *np,
7184 struct ethtool_rxnfc *nfc)
7185 {
7186 struct niu_parent *parent = np->parent;
7187 struct niu_tcam_entry *tp;
7188 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7189 u16 idx;
7190 u64 class;
7191 int ret = 0;
7192
7193 idx = tcam_get_index(np, (u16)nfc->fs.location);
7194
7195 tp = &parent->tcam[idx];
7196 if (!tp->valid) {
7197 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7198 parent->index, (u16)nfc->fs.location, idx);
7199 return -EINVAL;
7200 }
7201
7202 /* fill the flow spec entry */
7203 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7204 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7205 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7206
7207 if (ret < 0) {
7208 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7209 parent->index);
7210 ret = -EINVAL;
7211 goto out;
7212 }
7213
7214 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7215 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7216 TCAM_V4KEY2_PROTO_SHIFT;
7217 if (proto == IPPROTO_ESP) {
7218 if (fsp->flow_type == AH_V4_FLOW)
7219 fsp->flow_type = ESP_V4_FLOW;
7220 else
7221 fsp->flow_type = ESP_V6_FLOW;
7222 }
7223 }
7224
7225 switch (fsp->flow_type) {
7226 case TCP_V4_FLOW:
7227 case UDP_V4_FLOW:
7228 case SCTP_V4_FLOW:
7229 case AH_V4_FLOW:
7230 case ESP_V4_FLOW:
7231 niu_get_ip4fs_from_tcam_key(tp, fsp);
7232 break;
7233 case TCP_V6_FLOW:
7234 case UDP_V6_FLOW:
7235 case SCTP_V6_FLOW:
7236 case AH_V6_FLOW:
7237 case ESP_V6_FLOW:
7238 /* Not yet implemented */
7239 ret = -EINVAL;
7240 break;
7241 case IP_USER_FLOW:
7242 niu_get_ip4fs_from_tcam_key(tp, fsp);
7243 break;
7244 default:
7245 ret = -EINVAL;
7246 break;
7247 }
7248
7249 if (ret < 0)
7250 goto out;
7251
7252 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7253 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7254 else
7255 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7256 TCAM_ASSOCDATA_OFFSET_SHIFT;
7257
7258 /* put the tcam size here */
7259 nfc->data = tcam_get_size(np);
7260 out:
7261 return ret;
7262 }
7263
7264 static int niu_get_ethtool_tcam_all(struct niu *np,
7265 struct ethtool_rxnfc *nfc,
7266 u32 *rule_locs)
7267 {
7268 struct niu_parent *parent = np->parent;
7269 struct niu_tcam_entry *tp;
7270 int i, idx, cnt;
7271 unsigned long flags;
7272 int ret = 0;
7273
7274 /* put the tcam size here */
7275 nfc->data = tcam_get_size(np);
7276
7277 niu_lock_parent(np, flags);
7278 for (cnt = 0, i = 0; i < nfc->data; i++) {
7279 idx = tcam_get_index(np, i);
7280 tp = &parent->tcam[idx];
7281 if (!tp->valid)
7282 continue;
7283 if (cnt == nfc->rule_cnt) {
7284 ret = -EMSGSIZE;
7285 break;
7286 }
7287 rule_locs[cnt] = i;
7288 cnt++;
7289 }
7290 niu_unlock_parent(np, flags);
7291
7292 return ret;
7293 }
7294
7295 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7296 void *rule_locs)
7297 {
7298 struct niu *np = netdev_priv(dev);
7299 int ret = 0;
7300
7301 switch (cmd->cmd) {
7302 case ETHTOOL_GRXFH:
7303 ret = niu_get_hash_opts(np, cmd);
7304 break;
7305 case ETHTOOL_GRXRINGS:
7306 cmd->data = np->num_rx_rings;
7307 break;
7308 case ETHTOOL_GRXCLSRLCNT:
7309 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7310 break;
7311 case ETHTOOL_GRXCLSRULE:
7312 ret = niu_get_ethtool_tcam_entry(np, cmd);
7313 break;
7314 case ETHTOOL_GRXCLSRLALL:
7315 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7316 break;
7317 default:
7318 ret = -EINVAL;
7319 break;
7320 }
7321
7322 return ret;
7323 }
7324
7325 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7326 {
7327 u64 class;
7328 u64 flow_key = 0;
7329 unsigned long flags;
7330
7331 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7332 return -EINVAL;
7333
7334 if (class < CLASS_CODE_USER_PROG1 ||
7335 class > CLASS_CODE_SCTP_IPV6)
7336 return -EINVAL;
7337
7338 if (nfc->data & RXH_DISCARD) {
7339 niu_lock_parent(np, flags);
7340 flow_key = np->parent->tcam_key[class -
7341 CLASS_CODE_USER_PROG1];
7342 flow_key |= TCAM_KEY_DISC;
7343 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7344 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7345 niu_unlock_parent(np, flags);
7346 return 0;
7347 } else {
7348 /* Discard was set before, but is not set now */
7349 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7350 TCAM_KEY_DISC) {
7351 niu_lock_parent(np, flags);
7352 flow_key = np->parent->tcam_key[class -
7353 CLASS_CODE_USER_PROG1];
7354 flow_key &= ~TCAM_KEY_DISC;
7355 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7356 flow_key);
7357 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7358 flow_key;
7359 niu_unlock_parent(np, flags);
7360 }
7361 }
7362
7363 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7364 return -EINVAL;
7365
7366 niu_lock_parent(np, flags);
7367 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7368 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7369 niu_unlock_parent(np, flags);
7370
7371 return 0;
7372 }
7373
7374 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7375 struct niu_tcam_entry *tp,
7376 int l2_rdc_tab, u64 class)
7377 {
7378 u8 pid = 0;
7379 u32 sip, dip, sipm, dipm, spi, spim;
7380 u16 sport, dport, spm, dpm;
7381
7382 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7383 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7384 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7385 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7386
7387 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7388 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7389 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7390 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7391
7392 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7393 tp->key[3] |= dip;
7394
7395 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7396 tp->key_mask[3] |= dipm;
7397
7398 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7399 TCAM_V4KEY2_TOS_SHIFT);
7400 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7401 TCAM_V4KEY2_TOS_SHIFT);
7402 switch (fsp->flow_type) {
7403 case TCP_V4_FLOW:
7404 case UDP_V4_FLOW:
7405 case SCTP_V4_FLOW:
7406 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7407 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7408 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7409 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7410
7411 tp->key[2] |= (((u64)sport << 16) | dport);
7412 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7413 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7414 break;
7415 case AH_V4_FLOW:
7416 case ESP_V4_FLOW:
7417 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7418 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7419
7420 tp->key[2] |= spi;
7421 tp->key_mask[2] |= spim;
7422 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7423 break;
7424 case IP_USER_FLOW:
7425 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7426 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7427
7428 tp->key[2] |= spi;
7429 tp->key_mask[2] |= spim;
7430 pid = fsp->h_u.usr_ip4_spec.proto;
7431 break;
7432 default:
7433 break;
7434 }
7435
7436 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7437 if (pid) {
7438 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7439 }
7440 }
7441
7442 static int niu_add_ethtool_tcam_entry(struct niu *np,
7443 struct ethtool_rxnfc *nfc)
7444 {
7445 struct niu_parent *parent = np->parent;
7446 struct niu_tcam_entry *tp;
7447 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7448 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7449 int l2_rdc_table = rdc_table->first_table_num;
7450 u16 idx;
7451 u64 class;
7452 unsigned long flags;
7453 int err, ret;
7454
7455 ret = 0;
7456
7457 idx = nfc->fs.location;
7458 if (idx >= tcam_get_size(np))
7459 return -EINVAL;
7460
7461 if (fsp->flow_type == IP_USER_FLOW) {
7462 int i;
7463 int add_usr_cls = 0;
7464 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7465 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7466
7467 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7468 return -EINVAL;
7469
7470 niu_lock_parent(np, flags);
7471
7472 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7473 if (parent->l3_cls[i]) {
7474 if (uspec->proto == parent->l3_cls_pid[i]) {
7475 class = parent->l3_cls[i];
7476 parent->l3_cls_refcnt[i]++;
7477 add_usr_cls = 1;
7478 break;
7479 }
7480 } else {
7481 /* Program new user IP class */
7482 switch (i) {
7483 case 0:
7484 class = CLASS_CODE_USER_PROG1;
7485 break;
7486 case 1:
7487 class = CLASS_CODE_USER_PROG2;
7488 break;
7489 case 2:
7490 class = CLASS_CODE_USER_PROG3;
7491 break;
7492 case 3:
7493 class = CLASS_CODE_USER_PROG4;
7494 break;
7495 default:
7496 break;
7497 }
7498 ret = tcam_user_ip_class_set(np, class, 0,
7499 uspec->proto,
7500 uspec->tos,
7501 umask->tos);
7502 if (ret)
7503 goto out;
7504
7505 ret = tcam_user_ip_class_enable(np, class, 1);
7506 if (ret)
7507 goto out;
7508 parent->l3_cls[i] = class;
7509 parent->l3_cls_pid[i] = uspec->proto;
7510 parent->l3_cls_refcnt[i]++;
7511 add_usr_cls = 1;
7512 break;
7513 }
7514 }
7515 if (!add_usr_cls) {
7516 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7517 parent->index, __func__, uspec->proto);
7518 ret = -EINVAL;
7519 goto out;
7520 }
7521 niu_unlock_parent(np, flags);
7522 } else {
7523 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7524 return -EINVAL;
7525 }
7526 }
7527
7528 niu_lock_parent(np, flags);
7529
7530 idx = tcam_get_index(np, idx);
7531 tp = &parent->tcam[idx];
7532
7533 memset(tp, 0, sizeof(*tp));
7534
7535 /* fill in the tcam key and mask */
7536 switch (fsp->flow_type) {
7537 case TCP_V4_FLOW:
7538 case UDP_V4_FLOW:
7539 case SCTP_V4_FLOW:
7540 case AH_V4_FLOW:
7541 case ESP_V4_FLOW:
7542 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7543 break;
7544 case TCP_V6_FLOW:
7545 case UDP_V6_FLOW:
7546 case SCTP_V6_FLOW:
7547 case AH_V6_FLOW:
7548 case ESP_V6_FLOW:
7549 /* Not yet implemented */
7550 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7551 parent->index, __func__, fsp->flow_type);
7552 ret = -EINVAL;
7553 goto out;
7554 case IP_USER_FLOW:
7555 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7556 break;
7557 default:
7558 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7559 parent->index, __func__, fsp->flow_type);
7560 ret = -EINVAL;
7561 goto out;
7562 }
7563
7564 /* fill in the assoc data */
7565 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7566 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7567 } else {
7568 if (fsp->ring_cookie >= np->num_rx_rings) {
7569 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7570 parent->index, __func__,
7571 (long long)fsp->ring_cookie);
7572 ret = -EINVAL;
7573 goto out;
7574 }
7575 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7576 (fsp->ring_cookie <<
7577 TCAM_ASSOCDATA_OFFSET_SHIFT));
7578 }
7579
7580 err = tcam_write(np, idx, tp->key, tp->key_mask);
7581 if (err) {
7582 ret = -EINVAL;
7583 goto out;
7584 }
7585 err = tcam_assoc_write(np, idx, tp->assoc_data);
7586 if (err) {
7587 ret = -EINVAL;
7588 goto out;
7589 }
7590
7591 /* validate the entry */
7592 tp->valid = 1;
7593 np->clas.tcam_valid_entries++;
7594 out:
7595 niu_unlock_parent(np, flags);
7596
7597 return ret;
7598 }
7599
7600 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7601 {
7602 struct niu_parent *parent = np->parent;
7603 struct niu_tcam_entry *tp;
7604 u16 idx;
7605 unsigned long flags;
7606 u64 class;
7607 int ret = 0;
7608
7609 if (loc >= tcam_get_size(np))
7610 return -EINVAL;
7611
7612 niu_lock_parent(np, flags);
7613
7614 idx = tcam_get_index(np, loc);
7615 tp = &parent->tcam[idx];
7616
7617 /* if the entry is of a user defined class, then update*/
7618 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7619 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7620
7621 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7622 int i;
7623 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7624 if (parent->l3_cls[i] == class) {
7625 parent->l3_cls_refcnt[i]--;
7626 if (!parent->l3_cls_refcnt[i]) {
7627 /* disable class */
7628 ret = tcam_user_ip_class_enable(np,
7629 class,
7630 0);
7631 if (ret)
7632 goto out;
7633 parent->l3_cls[i] = 0;
7634 parent->l3_cls_pid[i] = 0;
7635 }
7636 break;
7637 }
7638 }
7639 if (i == NIU_L3_PROG_CLS) {
7640 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7641 parent->index, __func__,
7642 (unsigned long long)class);
7643 ret = -EINVAL;
7644 goto out;
7645 }
7646 }
7647
7648 ret = tcam_flush(np, idx);
7649 if (ret)
7650 goto out;
7651
7652 /* invalidate the entry */
7653 tp->valid = 0;
7654 np->clas.tcam_valid_entries--;
7655 out:
7656 niu_unlock_parent(np, flags);
7657
7658 return ret;
7659 }
7660
7661 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7662 {
7663 struct niu *np = netdev_priv(dev);
7664 int ret = 0;
7665
7666 switch (cmd->cmd) {
7667 case ETHTOOL_SRXFH:
7668 ret = niu_set_hash_opts(np, cmd);
7669 break;
7670 case ETHTOOL_SRXCLSRLINS:
7671 ret = niu_add_ethtool_tcam_entry(np, cmd);
7672 break;
7673 case ETHTOOL_SRXCLSRLDEL:
7674 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7675 break;
7676 default:
7677 ret = -EINVAL;
7678 break;
7679 }
7680
7681 return ret;
7682 }
7683
7684 static const struct {
7685 const char string[ETH_GSTRING_LEN];
7686 } niu_xmac_stat_keys[] = {
7687 { "tx_frames" },
7688 { "tx_bytes" },
7689 { "tx_fifo_errors" },
7690 { "tx_overflow_errors" },
7691 { "tx_max_pkt_size_errors" },
7692 { "tx_underflow_errors" },
7693 { "rx_local_faults" },
7694 { "rx_remote_faults" },
7695 { "rx_link_faults" },
7696 { "rx_align_errors" },
7697 { "rx_frags" },
7698 { "rx_mcasts" },
7699 { "rx_bcasts" },
7700 { "rx_hist_cnt1" },
7701 { "rx_hist_cnt2" },
7702 { "rx_hist_cnt3" },
7703 { "rx_hist_cnt4" },
7704 { "rx_hist_cnt5" },
7705 { "rx_hist_cnt6" },
7706 { "rx_hist_cnt7" },
7707 { "rx_octets" },
7708 { "rx_code_violations" },
7709 { "rx_len_errors" },
7710 { "rx_crc_errors" },
7711 { "rx_underflows" },
7712 { "rx_overflows" },
7713 { "pause_off_state" },
7714 { "pause_on_state" },
7715 { "pause_received" },
7716 };
7717
7718 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7719
7720 static const struct {
7721 const char string[ETH_GSTRING_LEN];
7722 } niu_bmac_stat_keys[] = {
7723 { "tx_underflow_errors" },
7724 { "tx_max_pkt_size_errors" },
7725 { "tx_bytes" },
7726 { "tx_frames" },
7727 { "rx_overflows" },
7728 { "rx_frames" },
7729 { "rx_align_errors" },
7730 { "rx_crc_errors" },
7731 { "rx_len_errors" },
7732 { "pause_off_state" },
7733 { "pause_on_state" },
7734 { "pause_received" },
7735 };
7736
7737 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7738
7739 static const struct {
7740 const char string[ETH_GSTRING_LEN];
7741 } niu_rxchan_stat_keys[] = {
7742 { "rx_channel" },
7743 { "rx_packets" },
7744 { "rx_bytes" },
7745 { "rx_dropped" },
7746 { "rx_errors" },
7747 };
7748
7749 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7750
7751 static const struct {
7752 const char string[ETH_GSTRING_LEN];
7753 } niu_txchan_stat_keys[] = {
7754 { "tx_channel" },
7755 { "tx_packets" },
7756 { "tx_bytes" },
7757 { "tx_errors" },
7758 };
7759
7760 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7761
7762 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7763 {
7764 struct niu *np = netdev_priv(dev);
7765 int i;
7766
7767 if (stringset != ETH_SS_STATS)
7768 return;
7769
7770 if (np->flags & NIU_FLAGS_XMAC) {
7771 memcpy(data, niu_xmac_stat_keys,
7772 sizeof(niu_xmac_stat_keys));
7773 data += sizeof(niu_xmac_stat_keys);
7774 } else {
7775 memcpy(data, niu_bmac_stat_keys,
7776 sizeof(niu_bmac_stat_keys));
7777 data += sizeof(niu_bmac_stat_keys);
7778 }
7779 for (i = 0; i < np->num_rx_rings; i++) {
7780 memcpy(data, niu_rxchan_stat_keys,
7781 sizeof(niu_rxchan_stat_keys));
7782 data += sizeof(niu_rxchan_stat_keys);
7783 }
7784 for (i = 0; i < np->num_tx_rings; i++) {
7785 memcpy(data, niu_txchan_stat_keys,
7786 sizeof(niu_txchan_stat_keys));
7787 data += sizeof(niu_txchan_stat_keys);
7788 }
7789 }
7790
7791 static int niu_get_sset_count(struct net_device *dev, int stringset)
7792 {
7793 struct niu *np = netdev_priv(dev);
7794
7795 if (stringset != ETH_SS_STATS)
7796 return -EINVAL;
7797
7798 return (np->flags & NIU_FLAGS_XMAC ?
7799 NUM_XMAC_STAT_KEYS :
7800 NUM_BMAC_STAT_KEYS) +
7801 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7802 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7803 }
7804
7805 static void niu_get_ethtool_stats(struct net_device *dev,
7806 struct ethtool_stats *stats, u64 *data)
7807 {
7808 struct niu *np = netdev_priv(dev);
7809 int i;
7810
7811 niu_sync_mac_stats(np);
7812 if (np->flags & NIU_FLAGS_XMAC) {
7813 memcpy(data, &np->mac_stats.xmac,
7814 sizeof(struct niu_xmac_stats));
7815 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7816 } else {
7817 memcpy(data, &np->mac_stats.bmac,
7818 sizeof(struct niu_bmac_stats));
7819 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7820 }
7821 for (i = 0; i < np->num_rx_rings; i++) {
7822 struct rx_ring_info *rp = &np->rx_rings[i];
7823
7824 niu_sync_rx_discard_stats(np, rp, 0);
7825
7826 data[0] = rp->rx_channel;
7827 data[1] = rp->rx_packets;
7828 data[2] = rp->rx_bytes;
7829 data[3] = rp->rx_dropped;
7830 data[4] = rp->rx_errors;
7831 data += 5;
7832 }
7833 for (i = 0; i < np->num_tx_rings; i++) {
7834 struct tx_ring_info *rp = &np->tx_rings[i];
7835
7836 data[0] = rp->tx_channel;
7837 data[1] = rp->tx_packets;
7838 data[2] = rp->tx_bytes;
7839 data[3] = rp->tx_errors;
7840 data += 4;
7841 }
7842 }
7843
7844 static u64 niu_led_state_save(struct niu *np)
7845 {
7846 if (np->flags & NIU_FLAGS_XMAC)
7847 return nr64_mac(XMAC_CONFIG);
7848 else
7849 return nr64_mac(BMAC_XIF_CONFIG);
7850 }
7851
7852 static void niu_led_state_restore(struct niu *np, u64 val)
7853 {
7854 if (np->flags & NIU_FLAGS_XMAC)
7855 nw64_mac(XMAC_CONFIG, val);
7856 else
7857 nw64_mac(BMAC_XIF_CONFIG, val);
7858 }
7859
7860 static void niu_force_led(struct niu *np, int on)
7861 {
7862 u64 val, reg, bit;
7863
7864 if (np->flags & NIU_FLAGS_XMAC) {
7865 reg = XMAC_CONFIG;
7866 bit = XMAC_CONFIG_FORCE_LED_ON;
7867 } else {
7868 reg = BMAC_XIF_CONFIG;
7869 bit = BMAC_XIF_CONFIG_LINK_LED;
7870 }
7871
7872 val = nr64_mac(reg);
7873 if (on)
7874 val |= bit;
7875 else
7876 val &= ~bit;
7877 nw64_mac(reg, val);
7878 }
7879
7880 static int niu_phys_id(struct net_device *dev, u32 data)
7881 {
7882 struct niu *np = netdev_priv(dev);
7883 u64 orig_led_state;
7884 int i;
7885
7886 if (!netif_running(dev))
7887 return -EAGAIN;
7888
7889 if (data == 0)
7890 data = 2;
7891
7892 orig_led_state = niu_led_state_save(np);
7893 for (i = 0; i < (data * 2); i++) {
7894 int on = ((i % 2) == 0);
7895
7896 niu_force_led(np, on);
7897
7898 if (msleep_interruptible(500))
7899 break;
7900 }
7901 niu_led_state_restore(np, orig_led_state);
7902
7903 return 0;
7904 }
7905
7906 static int niu_set_flags(struct net_device *dev, u32 data)
7907 {
7908 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7909 }
7910
7911 static const struct ethtool_ops niu_ethtool_ops = {
7912 .get_drvinfo = niu_get_drvinfo,
7913 .get_link = ethtool_op_get_link,
7914 .get_msglevel = niu_get_msglevel,
7915 .set_msglevel = niu_set_msglevel,
7916 .nway_reset = niu_nway_reset,
7917 .get_eeprom_len = niu_get_eeprom_len,
7918 .get_eeprom = niu_get_eeprom,
7919 .get_settings = niu_get_settings,
7920 .set_settings = niu_set_settings,
7921 .get_strings = niu_get_strings,
7922 .get_sset_count = niu_get_sset_count,
7923 .get_ethtool_stats = niu_get_ethtool_stats,
7924 .phys_id = niu_phys_id,
7925 .get_rxnfc = niu_get_nfc,
7926 .set_rxnfc = niu_set_nfc,
7927 .set_flags = niu_set_flags,
7928 .get_flags = ethtool_op_get_flags,
7929 };
7930
7931 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7932 int ldg, int ldn)
7933 {
7934 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7935 return -EINVAL;
7936 if (ldn < 0 || ldn > LDN_MAX)
7937 return -EINVAL;
7938
7939 parent->ldg_map[ldn] = ldg;
7940
7941 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7942 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7943 * the firmware, and we're not supposed to change them.
7944 * Validate the mapping, because if it's wrong we probably
7945 * won't get any interrupts and that's painful to debug.
7946 */
7947 if (nr64(LDG_NUM(ldn)) != ldg) {
7948 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7949 np->port, ldn, ldg,
7950 (unsigned long long) nr64(LDG_NUM(ldn)));
7951 return -EINVAL;
7952 }
7953 } else
7954 nw64(LDG_NUM(ldn), ldg);
7955
7956 return 0;
7957 }
7958
7959 static int niu_set_ldg_timer_res(struct niu *np, int res)
7960 {
7961 if (res < 0 || res > LDG_TIMER_RES_VAL)
7962 return -EINVAL;
7963
7964
7965 nw64(LDG_TIMER_RES, res);
7966
7967 return 0;
7968 }
7969
7970 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7971 {
7972 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7973 (func < 0 || func > 3) ||
7974 (vector < 0 || vector > 0x1f))
7975 return -EINVAL;
7976
7977 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7978
7979 return 0;
7980 }
7981
7982 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7983 {
7984 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7985 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7986 int limit;
7987
7988 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7989 return -EINVAL;
7990
7991 frame = frame_base;
7992 nw64(ESPC_PIO_STAT, frame);
7993 limit = 64;
7994 do {
7995 udelay(5);
7996 frame = nr64(ESPC_PIO_STAT);
7997 if (frame & ESPC_PIO_STAT_READ_END)
7998 break;
7999 } while (limit--);
8000 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8001 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8002 (unsigned long long) frame);
8003 return -ENODEV;
8004 }
8005
8006 frame = frame_base;
8007 nw64(ESPC_PIO_STAT, frame);
8008 limit = 64;
8009 do {
8010 udelay(5);
8011 frame = nr64(ESPC_PIO_STAT);
8012 if (frame & ESPC_PIO_STAT_READ_END)
8013 break;
8014 } while (limit--);
8015 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8016 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8017 (unsigned long long) frame);
8018 return -ENODEV;
8019 }
8020
8021 frame = nr64(ESPC_PIO_STAT);
8022 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8023 }
8024
8025 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8026 {
8027 int err = niu_pci_eeprom_read(np, off);
8028 u16 val;
8029
8030 if (err < 0)
8031 return err;
8032 val = (err << 8);
8033 err = niu_pci_eeprom_read(np, off + 1);
8034 if (err < 0)
8035 return err;
8036 val |= (err & 0xff);
8037
8038 return val;
8039 }
8040
8041 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8042 {
8043 int err = niu_pci_eeprom_read(np, off);
8044 u16 val;
8045
8046 if (err < 0)
8047 return err;
8048
8049 val = (err & 0xff);
8050 err = niu_pci_eeprom_read(np, off + 1);
8051 if (err < 0)
8052 return err;
8053
8054 val |= (err & 0xff) << 8;
8055
8056 return val;
8057 }
8058
8059 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8060 u32 off,
8061 char *namebuf,
8062 int namebuf_len)
8063 {
8064 int i;
8065
8066 for (i = 0; i < namebuf_len; i++) {
8067 int err = niu_pci_eeprom_read(np, off + i);
8068 if (err < 0)
8069 return err;
8070 *namebuf++ = err;
8071 if (!err)
8072 break;
8073 }
8074 if (i >= namebuf_len)
8075 return -EINVAL;
8076
8077 return i + 1;
8078 }
8079
8080 static void __devinit niu_vpd_parse_version(struct niu *np)
8081 {
8082 struct niu_vpd *vpd = &np->vpd;
8083 int len = strlen(vpd->version) + 1;
8084 const char *s = vpd->version;
8085 int i;
8086
8087 for (i = 0; i < len - 5; i++) {
8088 if (!strncmp(s + i, "FCode ", 6))
8089 break;
8090 }
8091 if (i >= len - 5)
8092 return;
8093
8094 s += i + 5;
8095 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8096
8097 netif_printk(np, probe, KERN_DEBUG, np->dev,
8098 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8099 vpd->fcode_major, vpd->fcode_minor);
8100 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8101 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8102 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8103 np->flags |= NIU_FLAGS_VPD_VALID;
8104 }
8105
8106 /* ESPC_PIO_EN_ENABLE must be set */
8107 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8108 u32 start, u32 end)
8109 {
8110 unsigned int found_mask = 0;
8111 #define FOUND_MASK_MODEL 0x00000001
8112 #define FOUND_MASK_BMODEL 0x00000002
8113 #define FOUND_MASK_VERS 0x00000004
8114 #define FOUND_MASK_MAC 0x00000008
8115 #define FOUND_MASK_NMAC 0x00000010
8116 #define FOUND_MASK_PHY 0x00000020
8117 #define FOUND_MASK_ALL 0x0000003f
8118
8119 netif_printk(np, probe, KERN_DEBUG, np->dev,
8120 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8121 while (start < end) {
8122 int len, err, instance, type, prop_len;
8123 char namebuf[64];
8124 u8 *prop_buf;
8125 int max_len;
8126
8127 if (found_mask == FOUND_MASK_ALL) {
8128 niu_vpd_parse_version(np);
8129 return 1;
8130 }
8131
8132 err = niu_pci_eeprom_read(np, start + 2);
8133 if (err < 0)
8134 return err;
8135 len = err;
8136 start += 3;
8137
8138 instance = niu_pci_eeprom_read(np, start);
8139 type = niu_pci_eeprom_read(np, start + 3);
8140 prop_len = niu_pci_eeprom_read(np, start + 4);
8141 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8142 if (err < 0)
8143 return err;
8144
8145 prop_buf = NULL;
8146 max_len = 0;
8147 if (!strcmp(namebuf, "model")) {
8148 prop_buf = np->vpd.model;
8149 max_len = NIU_VPD_MODEL_MAX;
8150 found_mask |= FOUND_MASK_MODEL;
8151 } else if (!strcmp(namebuf, "board-model")) {
8152 prop_buf = np->vpd.board_model;
8153 max_len = NIU_VPD_BD_MODEL_MAX;
8154 found_mask |= FOUND_MASK_BMODEL;
8155 } else if (!strcmp(namebuf, "version")) {
8156 prop_buf = np->vpd.version;
8157 max_len = NIU_VPD_VERSION_MAX;
8158 found_mask |= FOUND_MASK_VERS;
8159 } else if (!strcmp(namebuf, "local-mac-address")) {
8160 prop_buf = np->vpd.local_mac;
8161 max_len = ETH_ALEN;
8162 found_mask |= FOUND_MASK_MAC;
8163 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8164 prop_buf = &np->vpd.mac_num;
8165 max_len = 1;
8166 found_mask |= FOUND_MASK_NMAC;
8167 } else if (!strcmp(namebuf, "phy-type")) {
8168 prop_buf = np->vpd.phy_type;
8169 max_len = NIU_VPD_PHY_TYPE_MAX;
8170 found_mask |= FOUND_MASK_PHY;
8171 }
8172
8173 if (max_len && prop_len > max_len) {
8174 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8175 return -EINVAL;
8176 }
8177
8178 if (prop_buf) {
8179 u32 off = start + 5 + err;
8180 int i;
8181
8182 netif_printk(np, probe, KERN_DEBUG, np->dev,
8183 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8184 namebuf, prop_len);
8185 for (i = 0; i < prop_len; i++)
8186 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8187 }
8188
8189 start += len;
8190 }
8191
8192 return 0;
8193 }
8194
8195 /* ESPC_PIO_EN_ENABLE must be set */
8196 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8197 {
8198 u32 offset;
8199 int err;
8200
8201 err = niu_pci_eeprom_read16_swp(np, start + 1);
8202 if (err < 0)
8203 return;
8204
8205 offset = err + 3;
8206
8207 while (start + offset < ESPC_EEPROM_SIZE) {
8208 u32 here = start + offset;
8209 u32 end;
8210
8211 err = niu_pci_eeprom_read(np, here);
8212 if (err != 0x90)
8213 return;
8214
8215 err = niu_pci_eeprom_read16_swp(np, here + 1);
8216 if (err < 0)
8217 return;
8218
8219 here = start + offset + 3;
8220 end = start + offset + err;
8221
8222 offset += err;
8223
8224 err = niu_pci_vpd_scan_props(np, here, end);
8225 if (err < 0 || err == 1)
8226 return;
8227 }
8228 }
8229
8230 /* ESPC_PIO_EN_ENABLE must be set */
8231 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8232 {
8233 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8234 int err;
8235
8236 while (start < end) {
8237 ret = start;
8238
8239 /* ROM header signature? */
8240 err = niu_pci_eeprom_read16(np, start + 0);
8241 if (err != 0x55aa)
8242 return 0;
8243
8244 /* Apply offset to PCI data structure. */
8245 err = niu_pci_eeprom_read16(np, start + 23);
8246 if (err < 0)
8247 return 0;
8248 start += err;
8249
8250 /* Check for "PCIR" signature. */
8251 err = niu_pci_eeprom_read16(np, start + 0);
8252 if (err != 0x5043)
8253 return 0;
8254 err = niu_pci_eeprom_read16(np, start + 2);
8255 if (err != 0x4952)
8256 return 0;
8257
8258 /* Check for OBP image type. */
8259 err = niu_pci_eeprom_read(np, start + 20);
8260 if (err < 0)
8261 return 0;
8262 if (err != 0x01) {
8263 err = niu_pci_eeprom_read(np, ret + 2);
8264 if (err < 0)
8265 return 0;
8266
8267 start = ret + (err * 512);
8268 continue;
8269 }
8270
8271 err = niu_pci_eeprom_read16_swp(np, start + 8);
8272 if (err < 0)
8273 return err;
8274 ret += err;
8275
8276 err = niu_pci_eeprom_read(np, ret + 0);
8277 if (err != 0x82)
8278 return 0;
8279
8280 return ret;
8281 }
8282
8283 return 0;
8284 }
8285
8286 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8287 const char *phy_prop)
8288 {
8289 if (!strcmp(phy_prop, "mif")) {
8290 /* 1G copper, MII */
8291 np->flags &= ~(NIU_FLAGS_FIBER |
8292 NIU_FLAGS_10G);
8293 np->mac_xcvr = MAC_XCVR_MII;
8294 } else if (!strcmp(phy_prop, "xgf")) {
8295 /* 10G fiber, XPCS */
8296 np->flags |= (NIU_FLAGS_10G |
8297 NIU_FLAGS_FIBER);
8298 np->mac_xcvr = MAC_XCVR_XPCS;
8299 } else if (!strcmp(phy_prop, "pcs")) {
8300 /* 1G fiber, PCS */
8301 np->flags &= ~NIU_FLAGS_10G;
8302 np->flags |= NIU_FLAGS_FIBER;
8303 np->mac_xcvr = MAC_XCVR_PCS;
8304 } else if (!strcmp(phy_prop, "xgc")) {
8305 /* 10G copper, XPCS */
8306 np->flags |= NIU_FLAGS_10G;
8307 np->flags &= ~NIU_FLAGS_FIBER;
8308 np->mac_xcvr = MAC_XCVR_XPCS;
8309 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8310 /* 10G Serdes or 1G Serdes, default to 10G */
8311 np->flags |= NIU_FLAGS_10G;
8312 np->flags &= ~NIU_FLAGS_FIBER;
8313 np->flags |= NIU_FLAGS_XCVR_SERDES;
8314 np->mac_xcvr = MAC_XCVR_XPCS;
8315 } else {
8316 return -EINVAL;
8317 }
8318 return 0;
8319 }
8320
8321 static int niu_pci_vpd_get_nports(struct niu *np)
8322 {
8323 int ports = 0;
8324
8325 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8326 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8327 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8328 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8329 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8330 ports = 4;
8331 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8332 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8333 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8335 ports = 2;
8336 }
8337
8338 return ports;
8339 }
8340
8341 static void __devinit niu_pci_vpd_validate(struct niu *np)
8342 {
8343 struct net_device *dev = np->dev;
8344 struct niu_vpd *vpd = &np->vpd;
8345 u8 val8;
8346
8347 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8348 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8349
8350 np->flags &= ~NIU_FLAGS_VPD_VALID;
8351 return;
8352 }
8353
8354 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8355 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8356 np->flags |= NIU_FLAGS_10G;
8357 np->flags &= ~NIU_FLAGS_FIBER;
8358 np->flags |= NIU_FLAGS_XCVR_SERDES;
8359 np->mac_xcvr = MAC_XCVR_PCS;
8360 if (np->port > 1) {
8361 np->flags |= NIU_FLAGS_FIBER;
8362 np->flags &= ~NIU_FLAGS_10G;
8363 }
8364 if (np->flags & NIU_FLAGS_10G)
8365 np->mac_xcvr = MAC_XCVR_XPCS;
8366 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8367 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8368 NIU_FLAGS_HOTPLUG_PHY);
8369 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8370 dev_err(np->device, "Illegal phy string [%s]\n",
8371 np->vpd.phy_type);
8372 dev_err(np->device, "Falling back to SPROM\n");
8373 np->flags &= ~NIU_FLAGS_VPD_VALID;
8374 return;
8375 }
8376
8377 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8378
8379 val8 = dev->perm_addr[5];
8380 dev->perm_addr[5] += np->port;
8381 if (dev->perm_addr[5] < val8)
8382 dev->perm_addr[4]++;
8383
8384 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8385 }
8386
8387 static int __devinit niu_pci_probe_sprom(struct niu *np)
8388 {
8389 struct net_device *dev = np->dev;
8390 int len, i;
8391 u64 val, sum;
8392 u8 val8;
8393
8394 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8395 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8396 len = val / 4;
8397
8398 np->eeprom_len = len;
8399
8400 netif_printk(np, probe, KERN_DEBUG, np->dev,
8401 "SPROM: Image size %llu\n", (unsigned long long)val);
8402
8403 sum = 0;
8404 for (i = 0; i < len; i++) {
8405 val = nr64(ESPC_NCR(i));
8406 sum += (val >> 0) & 0xff;
8407 sum += (val >> 8) & 0xff;
8408 sum += (val >> 16) & 0xff;
8409 sum += (val >> 24) & 0xff;
8410 }
8411 netif_printk(np, probe, KERN_DEBUG, np->dev,
8412 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8413 if ((sum & 0xff) != 0xab) {
8414 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8415 return -EINVAL;
8416 }
8417
8418 val = nr64(ESPC_PHY_TYPE);
8419 switch (np->port) {
8420 case 0:
8421 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8422 ESPC_PHY_TYPE_PORT0_SHIFT;
8423 break;
8424 case 1:
8425 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8426 ESPC_PHY_TYPE_PORT1_SHIFT;
8427 break;
8428 case 2:
8429 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8430 ESPC_PHY_TYPE_PORT2_SHIFT;
8431 break;
8432 case 3:
8433 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8434 ESPC_PHY_TYPE_PORT3_SHIFT;
8435 break;
8436 default:
8437 dev_err(np->device, "Bogus port number %u\n",
8438 np->port);
8439 return -EINVAL;
8440 }
8441 netif_printk(np, probe, KERN_DEBUG, np->dev,
8442 "SPROM: PHY type %x\n", val8);
8443
8444 switch (val8) {
8445 case ESPC_PHY_TYPE_1G_COPPER:
8446 /* 1G copper, MII */
8447 np->flags &= ~(NIU_FLAGS_FIBER |
8448 NIU_FLAGS_10G);
8449 np->mac_xcvr = MAC_XCVR_MII;
8450 break;
8451
8452 case ESPC_PHY_TYPE_1G_FIBER:
8453 /* 1G fiber, PCS */
8454 np->flags &= ~NIU_FLAGS_10G;
8455 np->flags |= NIU_FLAGS_FIBER;
8456 np->mac_xcvr = MAC_XCVR_PCS;
8457 break;
8458
8459 case ESPC_PHY_TYPE_10G_COPPER:
8460 /* 10G copper, XPCS */
8461 np->flags |= NIU_FLAGS_10G;
8462 np->flags &= ~NIU_FLAGS_FIBER;
8463 np->mac_xcvr = MAC_XCVR_XPCS;
8464 break;
8465
8466 case ESPC_PHY_TYPE_10G_FIBER:
8467 /* 10G fiber, XPCS */
8468 np->flags |= (NIU_FLAGS_10G |
8469 NIU_FLAGS_FIBER);
8470 np->mac_xcvr = MAC_XCVR_XPCS;
8471 break;
8472
8473 default:
8474 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8475 return -EINVAL;
8476 }
8477
8478 val = nr64(ESPC_MAC_ADDR0);
8479 netif_printk(np, probe, KERN_DEBUG, np->dev,
8480 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8481 dev->perm_addr[0] = (val >> 0) & 0xff;
8482 dev->perm_addr[1] = (val >> 8) & 0xff;
8483 dev->perm_addr[2] = (val >> 16) & 0xff;
8484 dev->perm_addr[3] = (val >> 24) & 0xff;
8485
8486 val = nr64(ESPC_MAC_ADDR1);
8487 netif_printk(np, probe, KERN_DEBUG, np->dev,
8488 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8489 dev->perm_addr[4] = (val >> 0) & 0xff;
8490 dev->perm_addr[5] = (val >> 8) & 0xff;
8491
8492 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8493 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8494 dev->perm_addr);
8495 return -EINVAL;
8496 }
8497
8498 val8 = dev->perm_addr[5];
8499 dev->perm_addr[5] += np->port;
8500 if (dev->perm_addr[5] < val8)
8501 dev->perm_addr[4]++;
8502
8503 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8504
8505 val = nr64(ESPC_MOD_STR_LEN);
8506 netif_printk(np, probe, KERN_DEBUG, np->dev,
8507 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8508 if (val >= 8 * 4)
8509 return -EINVAL;
8510
8511 for (i = 0; i < val; i += 4) {
8512 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8513
8514 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8515 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8516 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8517 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8518 }
8519 np->vpd.model[val] = '\0';
8520
8521 val = nr64(ESPC_BD_MOD_STR_LEN);
8522 netif_printk(np, probe, KERN_DEBUG, np->dev,
8523 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8524 if (val >= 4 * 4)
8525 return -EINVAL;
8526
8527 for (i = 0; i < val; i += 4) {
8528 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8529
8530 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8531 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8532 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8533 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8534 }
8535 np->vpd.board_model[val] = '\0';
8536
8537 np->vpd.mac_num =
8538 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8539 netif_printk(np, probe, KERN_DEBUG, np->dev,
8540 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8541
8542 return 0;
8543 }
8544
8545 static int __devinit niu_get_and_validate_port(struct niu *np)
8546 {
8547 struct niu_parent *parent = np->parent;
8548
8549 if (np->port <= 1)
8550 np->flags |= NIU_FLAGS_XMAC;
8551
8552 if (!parent->num_ports) {
8553 if (parent->plat_type == PLAT_TYPE_NIU) {
8554 parent->num_ports = 2;
8555 } else {
8556 parent->num_ports = niu_pci_vpd_get_nports(np);
8557 if (!parent->num_ports) {
8558 /* Fall back to SPROM as last resort.
8559 * This will fail on most cards.
8560 */
8561 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8562 ESPC_NUM_PORTS_MACS_VAL;
8563
8564 /* All of the current probing methods fail on
8565 * Maramba on-board parts.
8566 */
8567 if (!parent->num_ports)
8568 parent->num_ports = 4;
8569 }
8570 }
8571 }
8572
8573 if (np->port >= parent->num_ports)
8574 return -ENODEV;
8575
8576 return 0;
8577 }
8578
8579 static int __devinit phy_record(struct niu_parent *parent,
8580 struct phy_probe_info *p,
8581 int dev_id_1, int dev_id_2, u8 phy_port,
8582 int type)
8583 {
8584 u32 id = (dev_id_1 << 16) | dev_id_2;
8585 u8 idx;
8586
8587 if (dev_id_1 < 0 || dev_id_2 < 0)
8588 return 0;
8589 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8590 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8591 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8592 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
8593 return 0;
8594 } else {
8595 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8596 return 0;
8597 }
8598
8599 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8600 parent->index, id,
8601 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8602 type == PHY_TYPE_PCS ? "PCS" : "MII",
8603 phy_port);
8604
8605 if (p->cur[type] >= NIU_MAX_PORTS) {
8606 pr_err("Too many PHY ports\n");
8607 return -EINVAL;
8608 }
8609 idx = p->cur[type];
8610 p->phy_id[type][idx] = id;
8611 p->phy_port[type][idx] = phy_port;
8612 p->cur[type] = idx + 1;
8613 return 0;
8614 }
8615
8616 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8617 {
8618 int i;
8619
8620 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8621 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8622 return 1;
8623 }
8624 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8625 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8626 return 1;
8627 }
8628
8629 return 0;
8630 }
8631
8632 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8633 {
8634 int port, cnt;
8635
8636 cnt = 0;
8637 *lowest = 32;
8638 for (port = 8; port < 32; port++) {
8639 if (port_has_10g(p, port)) {
8640 if (!cnt)
8641 *lowest = port;
8642 cnt++;
8643 }
8644 }
8645
8646 return cnt;
8647 }
8648
8649 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8650 {
8651 *lowest = 32;
8652 if (p->cur[PHY_TYPE_MII])
8653 *lowest = p->phy_port[PHY_TYPE_MII][0];
8654
8655 return p->cur[PHY_TYPE_MII];
8656 }
8657
8658 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8659 {
8660 int num_ports = parent->num_ports;
8661 int i;
8662
8663 for (i = 0; i < num_ports; i++) {
8664 parent->rxchan_per_port[i] = (16 / num_ports);
8665 parent->txchan_per_port[i] = (16 / num_ports);
8666
8667 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8668 parent->index, i,
8669 parent->rxchan_per_port[i],
8670 parent->txchan_per_port[i]);
8671 }
8672 }
8673
8674 static void __devinit niu_divide_channels(struct niu_parent *parent,
8675 int num_10g, int num_1g)
8676 {
8677 int num_ports = parent->num_ports;
8678 int rx_chans_per_10g, rx_chans_per_1g;
8679 int tx_chans_per_10g, tx_chans_per_1g;
8680 int i, tot_rx, tot_tx;
8681
8682 if (!num_10g || !num_1g) {
8683 rx_chans_per_10g = rx_chans_per_1g =
8684 (NIU_NUM_RXCHAN / num_ports);
8685 tx_chans_per_10g = tx_chans_per_1g =
8686 (NIU_NUM_TXCHAN / num_ports);
8687 } else {
8688 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8689 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8690 (rx_chans_per_1g * num_1g)) /
8691 num_10g;
8692
8693 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8694 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8695 (tx_chans_per_1g * num_1g)) /
8696 num_10g;
8697 }
8698
8699 tot_rx = tot_tx = 0;
8700 for (i = 0; i < num_ports; i++) {
8701 int type = phy_decode(parent->port_phy, i);
8702
8703 if (type == PORT_TYPE_10G) {
8704 parent->rxchan_per_port[i] = rx_chans_per_10g;
8705 parent->txchan_per_port[i] = tx_chans_per_10g;
8706 } else {
8707 parent->rxchan_per_port[i] = rx_chans_per_1g;
8708 parent->txchan_per_port[i] = tx_chans_per_1g;
8709 }
8710 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8711 parent->index, i,
8712 parent->rxchan_per_port[i],
8713 parent->txchan_per_port[i]);
8714 tot_rx += parent->rxchan_per_port[i];
8715 tot_tx += parent->txchan_per_port[i];
8716 }
8717
8718 if (tot_rx > NIU_NUM_RXCHAN) {
8719 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8720 parent->index, tot_rx);
8721 for (i = 0; i < num_ports; i++)
8722 parent->rxchan_per_port[i] = 1;
8723 }
8724 if (tot_tx > NIU_NUM_TXCHAN) {
8725 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8726 parent->index, tot_tx);
8727 for (i = 0; i < num_ports; i++)
8728 parent->txchan_per_port[i] = 1;
8729 }
8730 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8731 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8732 parent->index, tot_rx, tot_tx);
8733 }
8734 }
8735
8736 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8737 int num_10g, int num_1g)
8738 {
8739 int i, num_ports = parent->num_ports;
8740 int rdc_group, rdc_groups_per_port;
8741 int rdc_channel_base;
8742
8743 rdc_group = 0;
8744 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8745
8746 rdc_channel_base = 0;
8747
8748 for (i = 0; i < num_ports; i++) {
8749 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8750 int grp, num_channels = parent->rxchan_per_port[i];
8751 int this_channel_offset;
8752
8753 tp->first_table_num = rdc_group;
8754 tp->num_tables = rdc_groups_per_port;
8755 this_channel_offset = 0;
8756 for (grp = 0; grp < tp->num_tables; grp++) {
8757 struct rdc_table *rt = &tp->tables[grp];
8758 int slot;
8759
8760 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8761 parent->index, i, tp->first_table_num + grp);
8762 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8763 rt->rxdma_channel[slot] =
8764 rdc_channel_base + this_channel_offset;
8765
8766 pr_cont("%d ", rt->rxdma_channel[slot]);
8767
8768 if (++this_channel_offset == num_channels)
8769 this_channel_offset = 0;
8770 }
8771 pr_cont("]\n");
8772 }
8773
8774 parent->rdc_default[i] = rdc_channel_base;
8775
8776 rdc_channel_base += num_channels;
8777 rdc_group += rdc_groups_per_port;
8778 }
8779 }
8780
8781 static int __devinit fill_phy_probe_info(struct niu *np,
8782 struct niu_parent *parent,
8783 struct phy_probe_info *info)
8784 {
8785 unsigned long flags;
8786 int port, err;
8787
8788 memset(info, 0, sizeof(*info));
8789
8790 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8791 niu_lock_parent(np, flags);
8792 err = 0;
8793 for (port = 8; port < 32; port++) {
8794 int dev_id_1, dev_id_2;
8795
8796 dev_id_1 = mdio_read(np, port,
8797 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8798 dev_id_2 = mdio_read(np, port,
8799 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8800 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8801 PHY_TYPE_PMA_PMD);
8802 if (err)
8803 break;
8804 dev_id_1 = mdio_read(np, port,
8805 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8806 dev_id_2 = mdio_read(np, port,
8807 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8808 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8809 PHY_TYPE_PCS);
8810 if (err)
8811 break;
8812 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8813 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8814 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8815 PHY_TYPE_MII);
8816 if (err)
8817 break;
8818 }
8819 niu_unlock_parent(np, flags);
8820
8821 return err;
8822 }
8823
8824 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8825 {
8826 struct phy_probe_info *info = &parent->phy_probe_info;
8827 int lowest_10g, lowest_1g;
8828 int num_10g, num_1g;
8829 u32 val;
8830 int err;
8831
8832 num_10g = num_1g = 0;
8833
8834 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8835 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8836 num_10g = 0;
8837 num_1g = 2;
8838 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8839 parent->num_ports = 4;
8840 val = (phy_encode(PORT_TYPE_1G, 0) |
8841 phy_encode(PORT_TYPE_1G, 1) |
8842 phy_encode(PORT_TYPE_1G, 2) |
8843 phy_encode(PORT_TYPE_1G, 3));
8844 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8845 num_10g = 2;
8846 num_1g = 0;
8847 parent->num_ports = 2;
8848 val = (phy_encode(PORT_TYPE_10G, 0) |
8849 phy_encode(PORT_TYPE_10G, 1));
8850 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8851 (parent->plat_type == PLAT_TYPE_NIU)) {
8852 /* this is the Monza case */
8853 if (np->flags & NIU_FLAGS_10G) {
8854 val = (phy_encode(PORT_TYPE_10G, 0) |
8855 phy_encode(PORT_TYPE_10G, 1));
8856 } else {
8857 val = (phy_encode(PORT_TYPE_1G, 0) |
8858 phy_encode(PORT_TYPE_1G, 1));
8859 }
8860 } else {
8861 err = fill_phy_probe_info(np, parent, info);
8862 if (err)
8863 return err;
8864
8865 num_10g = count_10g_ports(info, &lowest_10g);
8866 num_1g = count_1g_ports(info, &lowest_1g);
8867
8868 switch ((num_10g << 4) | num_1g) {
8869 case 0x24:
8870 if (lowest_1g == 10)
8871 parent->plat_type = PLAT_TYPE_VF_P0;
8872 else if (lowest_1g == 26)
8873 parent->plat_type = PLAT_TYPE_VF_P1;
8874 else
8875 goto unknown_vg_1g_port;
8876
8877 /* fallthru */
8878 case 0x22:
8879 val = (phy_encode(PORT_TYPE_10G, 0) |
8880 phy_encode(PORT_TYPE_10G, 1) |
8881 phy_encode(PORT_TYPE_1G, 2) |
8882 phy_encode(PORT_TYPE_1G, 3));
8883 break;
8884
8885 case 0x20:
8886 val = (phy_encode(PORT_TYPE_10G, 0) |
8887 phy_encode(PORT_TYPE_10G, 1));
8888 break;
8889
8890 case 0x10:
8891 val = phy_encode(PORT_TYPE_10G, np->port);
8892 break;
8893
8894 case 0x14:
8895 if (lowest_1g == 10)
8896 parent->plat_type = PLAT_TYPE_VF_P0;
8897 else if (lowest_1g == 26)
8898 parent->plat_type = PLAT_TYPE_VF_P1;
8899 else
8900 goto unknown_vg_1g_port;
8901
8902 /* fallthru */
8903 case 0x13:
8904 if ((lowest_10g & 0x7) == 0)
8905 val = (phy_encode(PORT_TYPE_10G, 0) |
8906 phy_encode(PORT_TYPE_1G, 1) |
8907 phy_encode(PORT_TYPE_1G, 2) |
8908 phy_encode(PORT_TYPE_1G, 3));
8909 else
8910 val = (phy_encode(PORT_TYPE_1G, 0) |
8911 phy_encode(PORT_TYPE_10G, 1) |
8912 phy_encode(PORT_TYPE_1G, 2) |
8913 phy_encode(PORT_TYPE_1G, 3));
8914 break;
8915
8916 case 0x04:
8917 if (lowest_1g == 10)
8918 parent->plat_type = PLAT_TYPE_VF_P0;
8919 else if (lowest_1g == 26)
8920 parent->plat_type = PLAT_TYPE_VF_P1;
8921 else
8922 goto unknown_vg_1g_port;
8923
8924 val = (phy_encode(PORT_TYPE_1G, 0) |
8925 phy_encode(PORT_TYPE_1G, 1) |
8926 phy_encode(PORT_TYPE_1G, 2) |
8927 phy_encode(PORT_TYPE_1G, 3));
8928 break;
8929
8930 default:
8931 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8932 num_10g, num_1g);
8933 return -EINVAL;
8934 }
8935 }
8936
8937 parent->port_phy = val;
8938
8939 if (parent->plat_type == PLAT_TYPE_NIU)
8940 niu_n2_divide_channels(parent);
8941 else
8942 niu_divide_channels(parent, num_10g, num_1g);
8943
8944 niu_divide_rdc_groups(parent, num_10g, num_1g);
8945
8946 return 0;
8947
8948 unknown_vg_1g_port:
8949 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8950 return -EINVAL;
8951 }
8952
8953 static int __devinit niu_probe_ports(struct niu *np)
8954 {
8955 struct niu_parent *parent = np->parent;
8956 int err, i;
8957
8958 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8959 err = walk_phys(np, parent);
8960 if (err)
8961 return err;
8962
8963 niu_set_ldg_timer_res(np, 2);
8964 for (i = 0; i <= LDN_MAX; i++)
8965 niu_ldn_irq_enable(np, i, 0);
8966 }
8967
8968 if (parent->port_phy == PORT_PHY_INVALID)
8969 return -EINVAL;
8970
8971 return 0;
8972 }
8973
8974 static int __devinit niu_classifier_swstate_init(struct niu *np)
8975 {
8976 struct niu_classifier *cp = &np->clas;
8977
8978 cp->tcam_top = (u16) np->port;
8979 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8980 cp->h1_init = 0xffffffff;
8981 cp->h2_init = 0xffff;
8982
8983 return fflp_early_init(np);
8984 }
8985
8986 static void __devinit niu_link_config_init(struct niu *np)
8987 {
8988 struct niu_link_config *lp = &np->link_config;
8989
8990 lp->advertising = (ADVERTISED_10baseT_Half |
8991 ADVERTISED_10baseT_Full |
8992 ADVERTISED_100baseT_Half |
8993 ADVERTISED_100baseT_Full |
8994 ADVERTISED_1000baseT_Half |
8995 ADVERTISED_1000baseT_Full |
8996 ADVERTISED_10000baseT_Full |
8997 ADVERTISED_Autoneg);
8998 lp->speed = lp->active_speed = SPEED_INVALID;
8999 lp->duplex = DUPLEX_FULL;
9000 lp->active_duplex = DUPLEX_INVALID;
9001 lp->autoneg = 1;
9002 #if 0
9003 lp->loopback_mode = LOOPBACK_MAC;
9004 lp->active_speed = SPEED_10000;
9005 lp->active_duplex = DUPLEX_FULL;
9006 #else
9007 lp->loopback_mode = LOOPBACK_DISABLED;
9008 #endif
9009 }
9010
9011 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9012 {
9013 switch (np->port) {
9014 case 0:
9015 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9016 np->ipp_off = 0x00000;
9017 np->pcs_off = 0x04000;
9018 np->xpcs_off = 0x02000;
9019 break;
9020
9021 case 1:
9022 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9023 np->ipp_off = 0x08000;
9024 np->pcs_off = 0x0a000;
9025 np->xpcs_off = 0x08000;
9026 break;
9027
9028 case 2:
9029 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9030 np->ipp_off = 0x04000;
9031 np->pcs_off = 0x0e000;
9032 np->xpcs_off = ~0UL;
9033 break;
9034
9035 case 3:
9036 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9037 np->ipp_off = 0x0c000;
9038 np->pcs_off = 0x12000;
9039 np->xpcs_off = ~0UL;
9040 break;
9041
9042 default:
9043 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9044 return -EINVAL;
9045 }
9046
9047 return 0;
9048 }
9049
9050 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9051 {
9052 struct msix_entry msi_vec[NIU_NUM_LDG];
9053 struct niu_parent *parent = np->parent;
9054 struct pci_dev *pdev = np->pdev;
9055 int i, num_irqs, err;
9056 u8 first_ldg;
9057
9058 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9059 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9060 ldg_num_map[i] = first_ldg + i;
9061
9062 num_irqs = (parent->rxchan_per_port[np->port] +
9063 parent->txchan_per_port[np->port] +
9064 (np->port == 0 ? 3 : 1));
9065 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9066
9067 retry:
9068 for (i = 0; i < num_irqs; i++) {
9069 msi_vec[i].vector = 0;
9070 msi_vec[i].entry = i;
9071 }
9072
9073 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9074 if (err < 0) {
9075 np->flags &= ~NIU_FLAGS_MSIX;
9076 return;
9077 }
9078 if (err > 0) {
9079 num_irqs = err;
9080 goto retry;
9081 }
9082
9083 np->flags |= NIU_FLAGS_MSIX;
9084 for (i = 0; i < num_irqs; i++)
9085 np->ldg[i].irq = msi_vec[i].vector;
9086 np->num_ldg = num_irqs;
9087 }
9088
9089 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9090 {
9091 #ifdef CONFIG_SPARC64
9092 struct platform_device *op = np->op;
9093 const u32 *int_prop;
9094 int i;
9095
9096 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9097 if (!int_prop)
9098 return -ENODEV;
9099
9100 for (i = 0; i < op->archdata.num_irqs; i++) {
9101 ldg_num_map[i] = int_prop[i];
9102 np->ldg[i].irq = op->archdata.irqs[i];
9103 }
9104
9105 np->num_ldg = op->archdata.num_irqs;
9106
9107 return 0;
9108 #else
9109 return -EINVAL;
9110 #endif
9111 }
9112
9113 static int __devinit niu_ldg_init(struct niu *np)
9114 {
9115 struct niu_parent *parent = np->parent;
9116 u8 ldg_num_map[NIU_NUM_LDG];
9117 int first_chan, num_chan;
9118 int i, err, ldg_rotor;
9119 u8 port;
9120
9121 np->num_ldg = 1;
9122 np->ldg[0].irq = np->dev->irq;
9123 if (parent->plat_type == PLAT_TYPE_NIU) {
9124 err = niu_n2_irq_init(np, ldg_num_map);
9125 if (err)
9126 return err;
9127 } else
9128 niu_try_msix(np, ldg_num_map);
9129
9130 port = np->port;
9131 for (i = 0; i < np->num_ldg; i++) {
9132 struct niu_ldg *lp = &np->ldg[i];
9133
9134 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9135
9136 lp->np = np;
9137 lp->ldg_num = ldg_num_map[i];
9138 lp->timer = 2; /* XXX */
9139
9140 /* On N2 NIU the firmware has setup the SID mappings so they go
9141 * to the correct values that will route the LDG to the proper
9142 * interrupt in the NCU interrupt table.
9143 */
9144 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9145 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9146 if (err)
9147 return err;
9148 }
9149 }
9150
9151 /* We adopt the LDG assignment ordering used by the N2 NIU
9152 * 'interrupt' properties because that simplifies a lot of
9153 * things. This ordering is:
9154 *
9155 * MAC
9156 * MIF (if port zero)
9157 * SYSERR (if port zero)
9158 * RX channels
9159 * TX channels
9160 */
9161
9162 ldg_rotor = 0;
9163
9164 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9165 LDN_MAC(port));
9166 if (err)
9167 return err;
9168
9169 ldg_rotor++;
9170 if (ldg_rotor == np->num_ldg)
9171 ldg_rotor = 0;
9172
9173 if (port == 0) {
9174 err = niu_ldg_assign_ldn(np, parent,
9175 ldg_num_map[ldg_rotor],
9176 LDN_MIF);
9177 if (err)
9178 return err;
9179
9180 ldg_rotor++;
9181 if (ldg_rotor == np->num_ldg)
9182 ldg_rotor = 0;
9183
9184 err = niu_ldg_assign_ldn(np, parent,
9185 ldg_num_map[ldg_rotor],
9186 LDN_DEVICE_ERROR);
9187 if (err)
9188 return err;
9189
9190 ldg_rotor++;
9191 if (ldg_rotor == np->num_ldg)
9192 ldg_rotor = 0;
9193
9194 }
9195
9196 first_chan = 0;
9197 for (i = 0; i < port; i++)
9198 first_chan += parent->rxchan_per_port[port];
9199 num_chan = parent->rxchan_per_port[port];
9200
9201 for (i = first_chan; i < (first_chan + num_chan); i++) {
9202 err = niu_ldg_assign_ldn(np, parent,
9203 ldg_num_map[ldg_rotor],
9204 LDN_RXDMA(i));
9205 if (err)
9206 return err;
9207 ldg_rotor++;
9208 if (ldg_rotor == np->num_ldg)
9209 ldg_rotor = 0;
9210 }
9211
9212 first_chan = 0;
9213 for (i = 0; i < port; i++)
9214 first_chan += parent->txchan_per_port[port];
9215 num_chan = parent->txchan_per_port[port];
9216 for (i = first_chan; i < (first_chan + num_chan); i++) {
9217 err = niu_ldg_assign_ldn(np, parent,
9218 ldg_num_map[ldg_rotor],
9219 LDN_TXDMA(i));
9220 if (err)
9221 return err;
9222 ldg_rotor++;
9223 if (ldg_rotor == np->num_ldg)
9224 ldg_rotor = 0;
9225 }
9226
9227 return 0;
9228 }
9229
9230 static void __devexit niu_ldg_free(struct niu *np)
9231 {
9232 if (np->flags & NIU_FLAGS_MSIX)
9233 pci_disable_msix(np->pdev);
9234 }
9235
9236 static int __devinit niu_get_of_props(struct niu *np)
9237 {
9238 #ifdef CONFIG_SPARC64
9239 struct net_device *dev = np->dev;
9240 struct device_node *dp;
9241 const char *phy_type;
9242 const u8 *mac_addr;
9243 const char *model;
9244 int prop_len;
9245
9246 if (np->parent->plat_type == PLAT_TYPE_NIU)
9247 dp = np->op->dev.of_node;
9248 else
9249 dp = pci_device_to_OF_node(np->pdev);
9250
9251 phy_type = of_get_property(dp, "phy-type", &prop_len);
9252 if (!phy_type) {
9253 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9254 dp->full_name);
9255 return -EINVAL;
9256 }
9257
9258 if (!strcmp(phy_type, "none"))
9259 return -ENODEV;
9260
9261 strcpy(np->vpd.phy_type, phy_type);
9262
9263 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9264 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9265 dp->full_name, np->vpd.phy_type);
9266 return -EINVAL;
9267 }
9268
9269 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9270 if (!mac_addr) {
9271 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9272 dp->full_name);
9273 return -EINVAL;
9274 }
9275 if (prop_len != dev->addr_len) {
9276 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9277 dp->full_name, prop_len);
9278 }
9279 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9280 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9281 netdev_err(dev, "%s: OF MAC address is invalid\n",
9282 dp->full_name);
9283 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9284 return -EINVAL;
9285 }
9286
9287 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9288
9289 model = of_get_property(dp, "model", &prop_len);
9290
9291 if (model)
9292 strcpy(np->vpd.model, model);
9293
9294 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9295 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9296 NIU_FLAGS_HOTPLUG_PHY);
9297 }
9298
9299 return 0;
9300 #else
9301 return -EINVAL;
9302 #endif
9303 }
9304
9305 static int __devinit niu_get_invariants(struct niu *np)
9306 {
9307 int err, have_props;
9308 u32 offset;
9309
9310 err = niu_get_of_props(np);
9311 if (err == -ENODEV)
9312 return err;
9313
9314 have_props = !err;
9315
9316 err = niu_init_mac_ipp_pcs_base(np);
9317 if (err)
9318 return err;
9319
9320 if (have_props) {
9321 err = niu_get_and_validate_port(np);
9322 if (err)
9323 return err;
9324
9325 } else {
9326 if (np->parent->plat_type == PLAT_TYPE_NIU)
9327 return -EINVAL;
9328
9329 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9330 offset = niu_pci_vpd_offset(np);
9331 netif_printk(np, probe, KERN_DEBUG, np->dev,
9332 "%s() VPD offset [%08x]\n", __func__, offset);
9333 if (offset)
9334 niu_pci_vpd_fetch(np, offset);
9335 nw64(ESPC_PIO_EN, 0);
9336
9337 if (np->flags & NIU_FLAGS_VPD_VALID) {
9338 niu_pci_vpd_validate(np);
9339 err = niu_get_and_validate_port(np);
9340 if (err)
9341 return err;
9342 }
9343
9344 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9345 err = niu_get_and_validate_port(np);
9346 if (err)
9347 return err;
9348 err = niu_pci_probe_sprom(np);
9349 if (err)
9350 return err;
9351 }
9352 }
9353
9354 err = niu_probe_ports(np);
9355 if (err)
9356 return err;
9357
9358 niu_ldg_init(np);
9359
9360 niu_classifier_swstate_init(np);
9361 niu_link_config_init(np);
9362
9363 err = niu_determine_phy_disposition(np);
9364 if (!err)
9365 err = niu_init_link(np);
9366
9367 return err;
9368 }
9369
9370 static LIST_HEAD(niu_parent_list);
9371 static DEFINE_MUTEX(niu_parent_lock);
9372 static int niu_parent_index;
9373
9374 static ssize_t show_port_phy(struct device *dev,
9375 struct device_attribute *attr, char *buf)
9376 {
9377 struct platform_device *plat_dev = to_platform_device(dev);
9378 struct niu_parent *p = plat_dev->dev.platform_data;
9379 u32 port_phy = p->port_phy;
9380 char *orig_buf = buf;
9381 int i;
9382
9383 if (port_phy == PORT_PHY_UNKNOWN ||
9384 port_phy == PORT_PHY_INVALID)
9385 return 0;
9386
9387 for (i = 0; i < p->num_ports; i++) {
9388 const char *type_str;
9389 int type;
9390
9391 type = phy_decode(port_phy, i);
9392 if (type == PORT_TYPE_10G)
9393 type_str = "10G";
9394 else
9395 type_str = "1G";
9396 buf += sprintf(buf,
9397 (i == 0) ? "%s" : " %s",
9398 type_str);
9399 }
9400 buf += sprintf(buf, "\n");
9401 return buf - orig_buf;
9402 }
9403
9404 static ssize_t show_plat_type(struct device *dev,
9405 struct device_attribute *attr, char *buf)
9406 {
9407 struct platform_device *plat_dev = to_platform_device(dev);
9408 struct niu_parent *p = plat_dev->dev.platform_data;
9409 const char *type_str;
9410
9411 switch (p->plat_type) {
9412 case PLAT_TYPE_ATLAS:
9413 type_str = "atlas";
9414 break;
9415 case PLAT_TYPE_NIU:
9416 type_str = "niu";
9417 break;
9418 case PLAT_TYPE_VF_P0:
9419 type_str = "vf_p0";
9420 break;
9421 case PLAT_TYPE_VF_P1:
9422 type_str = "vf_p1";
9423 break;
9424 default:
9425 type_str = "unknown";
9426 break;
9427 }
9428
9429 return sprintf(buf, "%s\n", type_str);
9430 }
9431
9432 static ssize_t __show_chan_per_port(struct device *dev,
9433 struct device_attribute *attr, char *buf,
9434 int rx)
9435 {
9436 struct platform_device *plat_dev = to_platform_device(dev);
9437 struct niu_parent *p = plat_dev->dev.platform_data;
9438 char *orig_buf = buf;
9439 u8 *arr;
9440 int i;
9441
9442 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9443
9444 for (i = 0; i < p->num_ports; i++) {
9445 buf += sprintf(buf,
9446 (i == 0) ? "%d" : " %d",
9447 arr[i]);
9448 }
9449 buf += sprintf(buf, "\n");
9450
9451 return buf - orig_buf;
9452 }
9453
9454 static ssize_t show_rxchan_per_port(struct device *dev,
9455 struct device_attribute *attr, char *buf)
9456 {
9457 return __show_chan_per_port(dev, attr, buf, 1);
9458 }
9459
9460 static ssize_t show_txchan_per_port(struct device *dev,
9461 struct device_attribute *attr, char *buf)
9462 {
9463 return __show_chan_per_port(dev, attr, buf, 1);
9464 }
9465
9466 static ssize_t show_num_ports(struct device *dev,
9467 struct device_attribute *attr, char *buf)
9468 {
9469 struct platform_device *plat_dev = to_platform_device(dev);
9470 struct niu_parent *p = plat_dev->dev.platform_data;
9471
9472 return sprintf(buf, "%d\n", p->num_ports);
9473 }
9474
9475 static struct device_attribute niu_parent_attributes[] = {
9476 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9477 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9478 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9479 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9480 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9481 {}
9482 };
9483
9484 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9485 union niu_parent_id *id,
9486 u8 ptype)
9487 {
9488 struct platform_device *plat_dev;
9489 struct niu_parent *p;
9490 int i;
9491
9492 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9493 NULL, 0);
9494 if (IS_ERR(plat_dev))
9495 return NULL;
9496
9497 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9498 int err = device_create_file(&plat_dev->dev,
9499 &niu_parent_attributes[i]);
9500 if (err)
9501 goto fail_unregister;
9502 }
9503
9504 p = kzalloc(sizeof(*p), GFP_KERNEL);
9505 if (!p)
9506 goto fail_unregister;
9507
9508 p->index = niu_parent_index++;
9509
9510 plat_dev->dev.platform_data = p;
9511 p->plat_dev = plat_dev;
9512
9513 memcpy(&p->id, id, sizeof(*id));
9514 p->plat_type = ptype;
9515 INIT_LIST_HEAD(&p->list);
9516 atomic_set(&p->refcnt, 0);
9517 list_add(&p->list, &niu_parent_list);
9518 spin_lock_init(&p->lock);
9519
9520 p->rxdma_clock_divider = 7500;
9521
9522 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9523 if (p->plat_type == PLAT_TYPE_NIU)
9524 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9525
9526 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9527 int index = i - CLASS_CODE_USER_PROG1;
9528
9529 p->tcam_key[index] = TCAM_KEY_TSEL;
9530 p->flow_key[index] = (FLOW_KEY_IPSA |
9531 FLOW_KEY_IPDA |
9532 FLOW_KEY_PROTO |
9533 (FLOW_KEY_L4_BYTE12 <<
9534 FLOW_KEY_L4_0_SHIFT) |
9535 (FLOW_KEY_L4_BYTE12 <<
9536 FLOW_KEY_L4_1_SHIFT));
9537 }
9538
9539 for (i = 0; i < LDN_MAX + 1; i++)
9540 p->ldg_map[i] = LDG_INVALID;
9541
9542 return p;
9543
9544 fail_unregister:
9545 platform_device_unregister(plat_dev);
9546 return NULL;
9547 }
9548
9549 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9550 union niu_parent_id *id,
9551 u8 ptype)
9552 {
9553 struct niu_parent *p, *tmp;
9554 int port = np->port;
9555
9556 mutex_lock(&niu_parent_lock);
9557 p = NULL;
9558 list_for_each_entry(tmp, &niu_parent_list, list) {
9559 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9560 p = tmp;
9561 break;
9562 }
9563 }
9564 if (!p)
9565 p = niu_new_parent(np, id, ptype);
9566
9567 if (p) {
9568 char port_name[6];
9569 int err;
9570
9571 sprintf(port_name, "port%d", port);
9572 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9573 &np->device->kobj,
9574 port_name);
9575 if (!err) {
9576 p->ports[port] = np;
9577 atomic_inc(&p->refcnt);
9578 }
9579 }
9580 mutex_unlock(&niu_parent_lock);
9581
9582 return p;
9583 }
9584
9585 static void niu_put_parent(struct niu *np)
9586 {
9587 struct niu_parent *p = np->parent;
9588 u8 port = np->port;
9589 char port_name[6];
9590
9591 BUG_ON(!p || p->ports[port] != np);
9592
9593 netif_printk(np, probe, KERN_DEBUG, np->dev,
9594 "%s() port[%u]\n", __func__, port);
9595
9596 sprintf(port_name, "port%d", port);
9597
9598 mutex_lock(&niu_parent_lock);
9599
9600 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9601
9602 p->ports[port] = NULL;
9603 np->parent = NULL;
9604
9605 if (atomic_dec_and_test(&p->refcnt)) {
9606 list_del(&p->list);
9607 platform_device_unregister(p->plat_dev);
9608 }
9609
9610 mutex_unlock(&niu_parent_lock);
9611 }
9612
9613 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9614 u64 *handle, gfp_t flag)
9615 {
9616 dma_addr_t dh;
9617 void *ret;
9618
9619 ret = dma_alloc_coherent(dev, size, &dh, flag);
9620 if (ret)
9621 *handle = dh;
9622 return ret;
9623 }
9624
9625 static void niu_pci_free_coherent(struct device *dev, size_t size,
9626 void *cpu_addr, u64 handle)
9627 {
9628 dma_free_coherent(dev, size, cpu_addr, handle);
9629 }
9630
9631 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9632 unsigned long offset, size_t size,
9633 enum dma_data_direction direction)
9634 {
9635 return dma_map_page(dev, page, offset, size, direction);
9636 }
9637
9638 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9639 size_t size, enum dma_data_direction direction)
9640 {
9641 dma_unmap_page(dev, dma_address, size, direction);
9642 }
9643
9644 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9645 size_t size,
9646 enum dma_data_direction direction)
9647 {
9648 return dma_map_single(dev, cpu_addr, size, direction);
9649 }
9650
9651 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9652 size_t size,
9653 enum dma_data_direction direction)
9654 {
9655 dma_unmap_single(dev, dma_address, size, direction);
9656 }
9657
9658 static const struct niu_ops niu_pci_ops = {
9659 .alloc_coherent = niu_pci_alloc_coherent,
9660 .free_coherent = niu_pci_free_coherent,
9661 .map_page = niu_pci_map_page,
9662 .unmap_page = niu_pci_unmap_page,
9663 .map_single = niu_pci_map_single,
9664 .unmap_single = niu_pci_unmap_single,
9665 };
9666
9667 static void __devinit niu_driver_version(void)
9668 {
9669 static int niu_version_printed;
9670
9671 if (niu_version_printed++ == 0)
9672 pr_info("%s", version);
9673 }
9674
9675 static struct net_device * __devinit niu_alloc_and_init(
9676 struct device *gen_dev, struct pci_dev *pdev,
9677 struct platform_device *op, const struct niu_ops *ops,
9678 u8 port)
9679 {
9680 struct net_device *dev;
9681 struct niu *np;
9682
9683 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9684 if (!dev) {
9685 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9686 return NULL;
9687 }
9688
9689 SET_NETDEV_DEV(dev, gen_dev);
9690
9691 np = netdev_priv(dev);
9692 np->dev = dev;
9693 np->pdev = pdev;
9694 np->op = op;
9695 np->device = gen_dev;
9696 np->ops = ops;
9697
9698 np->msg_enable = niu_debug;
9699
9700 spin_lock_init(&np->lock);
9701 INIT_WORK(&np->reset_task, niu_reset_task);
9702
9703 np->port = port;
9704
9705 return dev;
9706 }
9707
9708 static const struct net_device_ops niu_netdev_ops = {
9709 .ndo_open = niu_open,
9710 .ndo_stop = niu_close,
9711 .ndo_start_xmit = niu_start_xmit,
9712 .ndo_get_stats = niu_get_stats,
9713 .ndo_set_multicast_list = niu_set_rx_mode,
9714 .ndo_validate_addr = eth_validate_addr,
9715 .ndo_set_mac_address = niu_set_mac_addr,
9716 .ndo_do_ioctl = niu_ioctl,
9717 .ndo_tx_timeout = niu_tx_timeout,
9718 .ndo_change_mtu = niu_change_mtu,
9719 };
9720
9721 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9722 {
9723 dev->netdev_ops = &niu_netdev_ops;
9724 dev->ethtool_ops = &niu_ethtool_ops;
9725 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9726 }
9727
9728 static void __devinit niu_device_announce(struct niu *np)
9729 {
9730 struct net_device *dev = np->dev;
9731
9732 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9733
9734 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9735 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9736 dev->name,
9737 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9738 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9739 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9740 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9741 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9742 np->vpd.phy_type);
9743 } else {
9744 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9745 dev->name,
9746 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9747 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9748 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9749 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9750 "COPPER")),
9751 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9752 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9753 np->vpd.phy_type);
9754 }
9755 }
9756
9757 static void __devinit niu_set_basic_features(struct net_device *dev)
9758 {
9759 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
9760 NETIF_F_GRO | NETIF_F_RXHASH);
9761 }
9762
9763 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9764 const struct pci_device_id *ent)
9765 {
9766 union niu_parent_id parent_id;
9767 struct net_device *dev;
9768 struct niu *np;
9769 int err, pos;
9770 u64 dma_mask;
9771 u16 val16;
9772
9773 niu_driver_version();
9774
9775 err = pci_enable_device(pdev);
9776 if (err) {
9777 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9778 return err;
9779 }
9780
9781 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9782 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9783 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9784 err = -ENODEV;
9785 goto err_out_disable_pdev;
9786 }
9787
9788 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9789 if (err) {
9790 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9791 goto err_out_disable_pdev;
9792 }
9793
9794 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9795 if (pos <= 0) {
9796 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9797 goto err_out_free_res;
9798 }
9799
9800 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9801 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9802 if (!dev) {
9803 err = -ENOMEM;
9804 goto err_out_free_res;
9805 }
9806 np = netdev_priv(dev);
9807
9808 memset(&parent_id, 0, sizeof(parent_id));
9809 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9810 parent_id.pci.bus = pdev->bus->number;
9811 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9812
9813 np->parent = niu_get_parent(np, &parent_id,
9814 PLAT_TYPE_ATLAS);
9815 if (!np->parent) {
9816 err = -ENOMEM;
9817 goto err_out_free_dev;
9818 }
9819
9820 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9821 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9822 val16 |= (PCI_EXP_DEVCTL_CERE |
9823 PCI_EXP_DEVCTL_NFERE |
9824 PCI_EXP_DEVCTL_FERE |
9825 PCI_EXP_DEVCTL_URRE |
9826 PCI_EXP_DEVCTL_RELAX_EN);
9827 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9828
9829 dma_mask = DMA_BIT_MASK(44);
9830 err = pci_set_dma_mask(pdev, dma_mask);
9831 if (!err) {
9832 dev->features |= NETIF_F_HIGHDMA;
9833 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9834 if (err) {
9835 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9836 goto err_out_release_parent;
9837 }
9838 }
9839 if (err || dma_mask == DMA_BIT_MASK(32)) {
9840 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9841 if (err) {
9842 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9843 goto err_out_release_parent;
9844 }
9845 }
9846
9847 niu_set_basic_features(dev);
9848
9849 np->regs = pci_ioremap_bar(pdev, 0);
9850 if (!np->regs) {
9851 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9852 err = -ENOMEM;
9853 goto err_out_release_parent;
9854 }
9855
9856 pci_set_master(pdev);
9857 pci_save_state(pdev);
9858
9859 dev->irq = pdev->irq;
9860
9861 niu_assign_netdev_ops(dev);
9862
9863 err = niu_get_invariants(np);
9864 if (err) {
9865 if (err != -ENODEV)
9866 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9867 goto err_out_iounmap;
9868 }
9869
9870 err = register_netdev(dev);
9871 if (err) {
9872 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9873 goto err_out_iounmap;
9874 }
9875
9876 pci_set_drvdata(pdev, dev);
9877
9878 niu_device_announce(np);
9879
9880 return 0;
9881
9882 err_out_iounmap:
9883 if (np->regs) {
9884 iounmap(np->regs);
9885 np->regs = NULL;
9886 }
9887
9888 err_out_release_parent:
9889 niu_put_parent(np);
9890
9891 err_out_free_dev:
9892 free_netdev(dev);
9893
9894 err_out_free_res:
9895 pci_release_regions(pdev);
9896
9897 err_out_disable_pdev:
9898 pci_disable_device(pdev);
9899 pci_set_drvdata(pdev, NULL);
9900
9901 return err;
9902 }
9903
9904 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9905 {
9906 struct net_device *dev = pci_get_drvdata(pdev);
9907
9908 if (dev) {
9909 struct niu *np = netdev_priv(dev);
9910
9911 unregister_netdev(dev);
9912 if (np->regs) {
9913 iounmap(np->regs);
9914 np->regs = NULL;
9915 }
9916
9917 niu_ldg_free(np);
9918
9919 niu_put_parent(np);
9920
9921 free_netdev(dev);
9922 pci_release_regions(pdev);
9923 pci_disable_device(pdev);
9924 pci_set_drvdata(pdev, NULL);
9925 }
9926 }
9927
9928 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9929 {
9930 struct net_device *dev = pci_get_drvdata(pdev);
9931 struct niu *np = netdev_priv(dev);
9932 unsigned long flags;
9933
9934 if (!netif_running(dev))
9935 return 0;
9936
9937 flush_scheduled_work();
9938 niu_netif_stop(np);
9939
9940 del_timer_sync(&np->timer);
9941
9942 spin_lock_irqsave(&np->lock, flags);
9943 niu_enable_interrupts(np, 0);
9944 spin_unlock_irqrestore(&np->lock, flags);
9945
9946 netif_device_detach(dev);
9947
9948 spin_lock_irqsave(&np->lock, flags);
9949 niu_stop_hw(np);
9950 spin_unlock_irqrestore(&np->lock, flags);
9951
9952 pci_save_state(pdev);
9953
9954 return 0;
9955 }
9956
9957 static int niu_resume(struct pci_dev *pdev)
9958 {
9959 struct net_device *dev = pci_get_drvdata(pdev);
9960 struct niu *np = netdev_priv(dev);
9961 unsigned long flags;
9962 int err;
9963
9964 if (!netif_running(dev))
9965 return 0;
9966
9967 pci_restore_state(pdev);
9968
9969 netif_device_attach(dev);
9970
9971 spin_lock_irqsave(&np->lock, flags);
9972
9973 err = niu_init_hw(np);
9974 if (!err) {
9975 np->timer.expires = jiffies + HZ;
9976 add_timer(&np->timer);
9977 niu_netif_start(np);
9978 }
9979
9980 spin_unlock_irqrestore(&np->lock, flags);
9981
9982 return err;
9983 }
9984
9985 static struct pci_driver niu_pci_driver = {
9986 .name = DRV_MODULE_NAME,
9987 .id_table = niu_pci_tbl,
9988 .probe = niu_pci_init_one,
9989 .remove = __devexit_p(niu_pci_remove_one),
9990 .suspend = niu_suspend,
9991 .resume = niu_resume,
9992 };
9993
9994 #ifdef CONFIG_SPARC64
9995 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9996 u64 *dma_addr, gfp_t flag)
9997 {
9998 unsigned long order = get_order(size);
9999 unsigned long page = __get_free_pages(flag, order);
10000
10001 if (page == 0UL)
10002 return NULL;
10003 memset((char *)page, 0, PAGE_SIZE << order);
10004 *dma_addr = __pa(page);
10005
10006 return (void *) page;
10007 }
10008
10009 static void niu_phys_free_coherent(struct device *dev, size_t size,
10010 void *cpu_addr, u64 handle)
10011 {
10012 unsigned long order = get_order(size);
10013
10014 free_pages((unsigned long) cpu_addr, order);
10015 }
10016
10017 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10018 unsigned long offset, size_t size,
10019 enum dma_data_direction direction)
10020 {
10021 return page_to_phys(page) + offset;
10022 }
10023
10024 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10025 size_t size, enum dma_data_direction direction)
10026 {
10027 /* Nothing to do. */
10028 }
10029
10030 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10031 size_t size,
10032 enum dma_data_direction direction)
10033 {
10034 return __pa(cpu_addr);
10035 }
10036
10037 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10038 size_t size,
10039 enum dma_data_direction direction)
10040 {
10041 /* Nothing to do. */
10042 }
10043
10044 static const struct niu_ops niu_phys_ops = {
10045 .alloc_coherent = niu_phys_alloc_coherent,
10046 .free_coherent = niu_phys_free_coherent,
10047 .map_page = niu_phys_map_page,
10048 .unmap_page = niu_phys_unmap_page,
10049 .map_single = niu_phys_map_single,
10050 .unmap_single = niu_phys_unmap_single,
10051 };
10052
10053 static int __devinit niu_of_probe(struct platform_device *op,
10054 const struct of_device_id *match)
10055 {
10056 union niu_parent_id parent_id;
10057 struct net_device *dev;
10058 struct niu *np;
10059 const u32 *reg;
10060 int err;
10061
10062 niu_driver_version();
10063
10064 reg = of_get_property(op->dev.of_node, "reg", NULL);
10065 if (!reg) {
10066 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10067 op->dev.of_node->full_name);
10068 return -ENODEV;
10069 }
10070
10071 dev = niu_alloc_and_init(&op->dev, NULL, op,
10072 &niu_phys_ops, reg[0] & 0x1);
10073 if (!dev) {
10074 err = -ENOMEM;
10075 goto err_out;
10076 }
10077 np = netdev_priv(dev);
10078
10079 memset(&parent_id, 0, sizeof(parent_id));
10080 parent_id.of = of_get_parent(op->dev.of_node);
10081
10082 np->parent = niu_get_parent(np, &parent_id,
10083 PLAT_TYPE_NIU);
10084 if (!np->parent) {
10085 err = -ENOMEM;
10086 goto err_out_free_dev;
10087 }
10088
10089 niu_set_basic_features(dev);
10090
10091 np->regs = of_ioremap(&op->resource[1], 0,
10092 resource_size(&op->resource[1]),
10093 "niu regs");
10094 if (!np->regs) {
10095 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10096 err = -ENOMEM;
10097 goto err_out_release_parent;
10098 }
10099
10100 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10101 resource_size(&op->resource[2]),
10102 "niu vregs-1");
10103 if (!np->vir_regs_1) {
10104 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10105 err = -ENOMEM;
10106 goto err_out_iounmap;
10107 }
10108
10109 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10110 resource_size(&op->resource[3]),
10111 "niu vregs-2");
10112 if (!np->vir_regs_2) {
10113 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10114 err = -ENOMEM;
10115 goto err_out_iounmap;
10116 }
10117
10118 niu_assign_netdev_ops(dev);
10119
10120 err = niu_get_invariants(np);
10121 if (err) {
10122 if (err != -ENODEV)
10123 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10124 goto err_out_iounmap;
10125 }
10126
10127 err = register_netdev(dev);
10128 if (err) {
10129 dev_err(&op->dev, "Cannot register net device, aborting\n");
10130 goto err_out_iounmap;
10131 }
10132
10133 dev_set_drvdata(&op->dev, dev);
10134
10135 niu_device_announce(np);
10136
10137 return 0;
10138
10139 err_out_iounmap:
10140 if (np->vir_regs_1) {
10141 of_iounmap(&op->resource[2], np->vir_regs_1,
10142 resource_size(&op->resource[2]));
10143 np->vir_regs_1 = NULL;
10144 }
10145
10146 if (np->vir_regs_2) {
10147 of_iounmap(&op->resource[3], np->vir_regs_2,
10148 resource_size(&op->resource[3]));
10149 np->vir_regs_2 = NULL;
10150 }
10151
10152 if (np->regs) {
10153 of_iounmap(&op->resource[1], np->regs,
10154 resource_size(&op->resource[1]));
10155 np->regs = NULL;
10156 }
10157
10158 err_out_release_parent:
10159 niu_put_parent(np);
10160
10161 err_out_free_dev:
10162 free_netdev(dev);
10163
10164 err_out:
10165 return err;
10166 }
10167
10168 static int __devexit niu_of_remove(struct platform_device *op)
10169 {
10170 struct net_device *dev = dev_get_drvdata(&op->dev);
10171
10172 if (dev) {
10173 struct niu *np = netdev_priv(dev);
10174
10175 unregister_netdev(dev);
10176
10177 if (np->vir_regs_1) {
10178 of_iounmap(&op->resource[2], np->vir_regs_1,
10179 resource_size(&op->resource[2]));
10180 np->vir_regs_1 = NULL;
10181 }
10182
10183 if (np->vir_regs_2) {
10184 of_iounmap(&op->resource[3], np->vir_regs_2,
10185 resource_size(&op->resource[3]));
10186 np->vir_regs_2 = NULL;
10187 }
10188
10189 if (np->regs) {
10190 of_iounmap(&op->resource[1], np->regs,
10191 resource_size(&op->resource[1]));
10192 np->regs = NULL;
10193 }
10194
10195 niu_ldg_free(np);
10196
10197 niu_put_parent(np);
10198
10199 free_netdev(dev);
10200 dev_set_drvdata(&op->dev, NULL);
10201 }
10202 return 0;
10203 }
10204
10205 static const struct of_device_id niu_match[] = {
10206 {
10207 .name = "network",
10208 .compatible = "SUNW,niusl",
10209 },
10210 {},
10211 };
10212 MODULE_DEVICE_TABLE(of, niu_match);
10213
10214 static struct of_platform_driver niu_of_driver = {
10215 .driver = {
10216 .name = "niu",
10217 .owner = THIS_MODULE,
10218 .of_match_table = niu_match,
10219 },
10220 .probe = niu_of_probe,
10221 .remove = __devexit_p(niu_of_remove),
10222 };
10223
10224 #endif /* CONFIG_SPARC64 */
10225
10226 static int __init niu_init(void)
10227 {
10228 int err = 0;
10229
10230 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10231
10232 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10233
10234 #ifdef CONFIG_SPARC64
10235 err = of_register_platform_driver(&niu_of_driver);
10236 #endif
10237
10238 if (!err) {
10239 err = pci_register_driver(&niu_pci_driver);
10240 #ifdef CONFIG_SPARC64
10241 if (err)
10242 of_unregister_platform_driver(&niu_of_driver);
10243 #endif
10244 }
10245
10246 return err;
10247 }
10248
10249 static void __exit niu_exit(void)
10250 {
10251 pci_unregister_driver(&niu_pci_driver);
10252 #ifdef CONFIG_SPARC64
10253 of_unregister_platform_driver(&niu_of_driver);
10254 #endif
10255 }
10256
10257 module_init(niu_init);
10258 module_exit(niu_exit);
kernel source for telekom puls (alcatel/mediatek)